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authorDevin Heitmueller <dheitmueller@kernellabs.com>2011-03-24 12:44:01 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-05-20 06:26:24 -0400
commit6cacdd46e23826c0591238f5f11b1bfa6490797d (patch)
tree4c77a8d327a39fc59746a24b7a145814dcb8d544 /drivers/media/dvb
parent9b316d6b42572f857161232d82b54e7ab2d33fbe (diff)
[media] drxd: Run lindent across sources
Take a first cleanup pass over the sources to bring them closer to the Linux coding style. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/frontends/drxd.h9
-rw-r--r--drivers/media/dvb/frontends/drxd_firm.c1576
-rw-r--r--drivers/media/dvb/frontends/drxd_firm.h8
-rw-r--r--drivers/media/dvb/frontends/drxd_hard.c2111
-rw-r--r--drivers/media/dvb/frontends/drxd_map_firm.h1790
5 files changed, 1819 insertions, 3675 deletions
diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h
index b21c85315d7..d3d6c924653 100644
--- a/drivers/media/dvb/frontends/drxd.h
+++ b/drivers/media/dvb/frontends/drxd.h
@@ -27,8 +27,7 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29 29
30struct drxd_config 30struct drxd_config {
31{
32 u8 index; 31 u8 index;
33 32
34 u8 pll_address; 33 u8 pll_address;
@@ -49,9 +48,9 @@ struct drxd_config
49 u8 disable_i2c_gate_ctrl; 48 u8 disable_i2c_gate_ctrl;
50 49
51 u32 IF; 50 u32 IF;
52 int (*pll_set) (void *priv, void *priv_params, 51 int (*pll_set) (void *priv, void *priv_params,
53 u8 pll_addr, u8 demoda_addr, s32 *off); 52 u8 pll_addr, u8 demoda_addr, s32 * off);
54 s16 (*osc_deviation) (void *priv, s16 dev, int flag); 53 s16(*osc_deviation) (void *priv, s16 dev, int flag);
55}; 54};
56 55
57extern 56extern
diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c
index b19a037e692..9453929d0d1 100644
--- a/drivers/media/dvb/frontends/drxd_firm.c
+++ b/drivers/media/dvb/frontends/drxd_firm.c
@@ -44,292 +44,294 @@
44/* HI firmware patches */ 44/* HI firmware patches */
45 45
46#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A 46#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
47#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ 47#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
48 48
49u8_t DRXD_InitAtomicRead[] = 49u8_t DRXD_InitAtomicRead[] = {
50{ 50 WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
51 WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE), 51 0x26, 0x00, /* 0 -> ring.rdy; */
52 0x26, 0x00, /* 0 -> ring.rdy; */ 52 0x60, 0x04, /* r0rami.dt -> ring.xba; */
53 0x60, 0x04, /* r0rami.dt -> ring.xba; */ 53 0x61, 0x04, /* r0rami.dt -> ring.xad; */
54 0x61, 0x04, /* r0rami.dt -> ring.xad; */ 54 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
55 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */ 55 0x40, 0x00, /* (long immediate) */
56 0x40, 0x00, /* (long immediate) */ 56 0x64, 0x04, /* r0rami.dt -> ring.len; */
57 0x64, 0x04, /* r0rami.dt -> ring.len; */ 57 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
58 0x65, 0x04, /* r0rami.dt -> ring.ctl; */ 58 0x26, 0x00, /* 0 -> ring.rdy; */
59 0x26, 0x00, /* 0 -> ring.rdy; */ 59 0x38, 0x00, /* 0 -> jumps.ad; */
60 0x38, 0x00, /* 0 -> jumps.ad; */ 60 END_OF_TABLE
61 END_OF_TABLE
62}; 61};
63 62
64/* Pins D0 and D1 of the parallel MPEG output can be used 63/* Pins D0 and D1 of the parallel MPEG output can be used
65 to set the I2C address of a device. */ 64 to set the I2C address of a device. */
66 65
67#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) 66#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
68#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ 67#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
69 68
70/* D0 Version */ 69/* D0 Version */
71u8_t DRXD_HiI2cPatch_1[] = 70u8_t DRXD_HiI2cPatch_1[] = {
72{ 71 WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
73 WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), 72 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
74 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ 73 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
75 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ 74 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
76 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 75 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
77 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ 76 0x23, 0x00, /* &data -> ring.iad; */
78 0x23, 0x00, /* &data -> ring.iad; */ 77 0x24, 0x00, /* 0 -> ring.len; */
79 0x24, 0x00, /* 0 -> ring.len; */ 78 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
80 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 79 0x26, 0x00, /* 0 -> ring.rdy; */
81 0x26, 0x00, /* 0 -> ring.rdy; */ 80 0x42, 0x00, /* &data+1 -> w0ram.ad; */
82 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 81 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
83 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ 82 0x63, 0x00, /* &data+1 -> ring.iad; */
84 0x63, 0x00, /* &data+1 -> ring.iad; */ 83 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
85 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 84 0x26, 0x00, /* 0 -> ring.rdy; */
86 0x26, 0x00, /* 0 -> ring.rdy; */ 85 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
87 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ 86 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
88 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 87 0x26, 0x00, /* 0 -> ring.rdy; */
89 0x26, 0x00, /* 0 -> ring.rdy; */ 88 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
90 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 89 0x23, 0x00, /* &data -> ring.iad; */
91 0x23, 0x00, /* &data -> ring.iad; */ 90 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
92 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 91 0x26, 0x00, /* 0 -> ring.rdy; */
93 0x26, 0x00, /* 0 -> ring.rdy; */ 92 0x42, 0x00, /* &data+1 -> w0ram.ad; */
94 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 93 0x0F, 0x04, /* r0ram.dt -> and.op; */
95 0x0F, 0x04, /* r0ram.dt -> and.op; */ 94 0x1C, 0x06, /* reg0.dt -> and.tr; */
96 0x1C, 0x06, /* reg0.dt -> and.tr; */ 95 0xCF, 0x04, /* and.rs -> add.op; */
97 0xCF, 0x04, /* and.rs -> add.op; */ 96 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
98 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ 97 0xD0, 0x04, /* add.rs -> add.tr; */
99 0xD0, 0x04, /* add.rs -> add.tr; */ 98 0xC8, 0x04, /* add.rs -> reg0.dt; */
100 0xC8, 0x04, /* add.rs -> reg0.dt; */ 99 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
101 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ 100 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
102 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ 101 0x01, 0x00, /* 0 -> w0rami.dt; */
103 0x01, 0x00, /* 0 -> w0rami.dt; */ 102 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
104 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 103 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
105 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ 104 0x01, 0x00, /* 0 -> w0rami.dt; */
106 0x01, 0x00, /* 0 -> w0rami.dt; */ 105 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
107 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 106 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
108 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ 107 0x01, 0x00, /* 0 -> w0rami.dt; */
109 0x01, 0x00, /* 0 -> w0rami.dt; */ 108 0x01, 0x00, /* 0 -> w0rami.dt; */
110 0x01, 0x00, /* 0 -> w0rami.dt; */ 109 0x01, 0x00, /* 0 -> w0rami.dt; */
111 0x01, 0x00, /* 0 -> w0rami.dt; */ 110 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
112 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ 111 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
113 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 112 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
114 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ 113 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
115 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 114 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
116 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 115
117 116 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
118 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 117 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
119 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 118 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
120 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 119 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
121 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 120 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
122 121 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
123 /* Force quick and dirty reset */ 122 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
124 WR16(B_HI_CT_REG_COMM_STATE__A,0), 123 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
125 END_OF_TABLE 124
125 /* Force quick and dirty reset */
126 WR16(B_HI_CT_REG_COMM_STATE__A, 0),
127 END_OF_TABLE
126}; 128};
127 129
128/* D0,D1 Version */ 130/* D0,D1 Version */
129u8_t DRXD_HiI2cPatch_3[] = 131u8_t DRXD_HiI2cPatch_3[] = {
130{ 132 WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
131 WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), 133 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
132 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ 134 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
133 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ 135 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
134 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 136 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
135 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ 137 0x23, 0x00, /* &data -> ring.iad; */
136 0x23, 0x00, /* &data -> ring.iad; */ 138 0x24, 0x00, /* 0 -> ring.len; */
137 0x24, 0x00, /* 0 -> ring.len; */ 139 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
138 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 140 0x26, 0x00, /* 0 -> ring.rdy; */
139 0x26, 0x00, /* 0 -> ring.rdy; */ 141 0x42, 0x00, /* &data+1 -> w0ram.ad; */
140 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 142 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
141 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ 143 0x63, 0x00, /* &data+1 -> ring.iad; */
142 0x63, 0x00, /* &data+1 -> ring.iad; */ 144 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
143 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 145 0x26, 0x00, /* 0 -> ring.rdy; */
144 0x26, 0x00, /* 0 -> ring.rdy; */ 146 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
145 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ 147 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
146 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 148 0x26, 0x00, /* 0 -> ring.rdy; */
147 0x26, 0x00, /* 0 -> ring.rdy; */ 149 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
148 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 150 0x23, 0x00, /* &data -> ring.iad; */
149 0x23, 0x00, /* &data -> ring.iad; */ 151 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
150 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 152 0x26, 0x00, /* 0 -> ring.rdy; */
151 0x26, 0x00, /* 0 -> ring.rdy; */ 153 0x42, 0x00, /* &data+1 -> w0ram.ad; */
152 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 154 0x0F, 0x04, /* r0ram.dt -> and.op; */
153 0x0F, 0x04, /* r0ram.dt -> and.op; */ 155 0x1C, 0x06, /* reg0.dt -> and.tr; */
154 0x1C, 0x06, /* reg0.dt -> and.tr; */ 156 0xCF, 0x04, /* and.rs -> add.op; */
155 0xCF, 0x04, /* and.rs -> add.op; */ 157 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
156 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ 158 0xD0, 0x04, /* add.rs -> add.tr; */
157 0xD0, 0x04, /* add.rs -> add.tr; */ 159 0xC8, 0x04, /* add.rs -> reg0.dt; */
158 0xC8, 0x04, /* add.rs -> reg0.dt; */ 160 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
159 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ 161 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
160 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ 162 0x01, 0x00, /* 0 -> w0rami.dt; */
161 0x01, 0x00, /* 0 -> w0rami.dt; */ 163 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
162 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 164 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
163 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ 165 0x01, 0x00, /* 0 -> w0rami.dt; */
164 0x01, 0x00, /* 0 -> w0rami.dt; */ 166 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
165 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 167 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
166 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ 168 0x01, 0x00, /* 0 -> w0rami.dt; */
167 0x01, 0x00, /* 0 -> w0rami.dt; */ 169 0x01, 0x00, /* 0 -> w0rami.dt; */
168 0x01, 0x00, /* 0 -> w0rami.dt; */ 170 0x01, 0x00, /* 0 -> w0rami.dt; */
169 0x01, 0x00, /* 0 -> w0rami.dt; */ 171 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
170 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ 172 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
171 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 173 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
172 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ 174 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
173 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 175 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
174 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 176
175 177 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
176 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 178 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
177 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 179 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
178 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 180 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
179 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), 181 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
180 182 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
181 /* Force quick and dirty reset */ 183 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
182 WR16(B_HI_CT_REG_COMM_STATE__A,0), 184 (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
183 END_OF_TABLE 185
186 /* Force quick and dirty reset */
187 WR16(B_HI_CT_REG_COMM_STATE__A, 0),
188 END_OF_TABLE
184}; 189};
185 190
186u8_t DRXD_ResetCEFR[] = 191u8_t DRXD_ResetCEFR[] = {
187{ 192 WRBLOCK(CE_REG_FR_TREAL00__A, 57),
188 WRBLOCK(CE_REG_FR_TREAL00__A, 57), 193 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
189 0x52,0x00, /* CE_REG_FR_TREAL00__A */ 194 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
190 0x00,0x00, /* CE_REG_FR_TIMAG00__A */ 195 0x52, 0x00, /* CE_REG_FR_TREAL01__A */
191 0x52,0x00, /* CE_REG_FR_TREAL01__A */ 196 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
192 0x00,0x00, /* CE_REG_FR_TIMAG01__A */ 197 0x52, 0x00, /* CE_REG_FR_TREAL02__A */
193 0x52,0x00, /* CE_REG_FR_TREAL02__A */ 198 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
194 0x00,0x00, /* CE_REG_FR_TIMAG02__A */ 199 0x52, 0x00, /* CE_REG_FR_TREAL03__A */
195 0x52,0x00, /* CE_REG_FR_TREAL03__A */ 200 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
196 0x00,0x00, /* CE_REG_FR_TIMAG03__A */ 201 0x52, 0x00, /* CE_REG_FR_TREAL04__A */
197 0x52,0x00, /* CE_REG_FR_TREAL04__A */ 202 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
198 0x00,0x00, /* CE_REG_FR_TIMAG04__A */ 203 0x52, 0x00, /* CE_REG_FR_TREAL05__A */
199 0x52,0x00, /* CE_REG_FR_TREAL05__A */ 204 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
200 0x00,0x00, /* CE_REG_FR_TIMAG05__A */ 205 0x52, 0x00, /* CE_REG_FR_TREAL06__A */
201 0x52,0x00, /* CE_REG_FR_TREAL06__A */ 206 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
202 0x00,0x00, /* CE_REG_FR_TIMAG06__A */ 207 0x52, 0x00, /* CE_REG_FR_TREAL07__A */
203 0x52,0x00, /* CE_REG_FR_TREAL07__A */ 208 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
204 0x00,0x00, /* CE_REG_FR_TIMAG07__A */ 209 0x52, 0x00, /* CE_REG_FR_TREAL08__A */
205 0x52,0x00, /* CE_REG_FR_TREAL08__A */ 210 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
206 0x00,0x00, /* CE_REG_FR_TIMAG08__A */ 211 0x52, 0x00, /* CE_REG_FR_TREAL09__A */
207 0x52,0x00, /* CE_REG_FR_TREAL09__A */ 212 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
208 0x00,0x00, /* CE_REG_FR_TIMAG09__A */ 213 0x52, 0x00, /* CE_REG_FR_TREAL10__A */
209 0x52,0x00, /* CE_REG_FR_TREAL10__A */ 214 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
210 0x00,0x00, /* CE_REG_FR_TIMAG10__A */ 215 0x52, 0x00, /* CE_REG_FR_TREAL11__A */
211 0x52,0x00, /* CE_REG_FR_TREAL11__A */ 216 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
212 0x00,0x00, /* CE_REG_FR_TIMAG11__A */ 217
213 218 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
214 0x52,0x00, /* CE_REG_FR_MID_TAP__A */ 219
215 220 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
216 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */ 221 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
217 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */ 222 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
218 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */ 223 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
219 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */ 224 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
220 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */ 225 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
221 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */ 226 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
222 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */ 227 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
223 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */ 228 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
224 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */ 229 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
225 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */ 230 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
226 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */ 231 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
227 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */ 232 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
228 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */ 233
229 234 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
230 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */ 235 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
231 0x90,0x01, /* CE_REG_FR_RIO_G01__A */ 236 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
232 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */ 237 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
233 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */ 238 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
234 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */ 239 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
235 0x85,0x00, /* CE_REG_FR_RIO_G05__A */ 240 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
236 0x72,0x00, /* CE_REG_FR_RIO_G06__A */ 241 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
237 0x64,0x00, /* CE_REG_FR_RIO_G07__A */ 242 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
238 0x59,0x00, /* CE_REG_FR_RIO_G08__A */ 243 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
239 0x50,0x00, /* CE_REG_FR_RIO_G09__A */ 244 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
240 0x49,0x00, /* CE_REG_FR_RIO_G10__A */ 245
241 246 0x10, 0x00, /* CE_REG_FR_MODE__A */
242 0x10,0x00, /* CE_REG_FR_MODE__A */ 247 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
243 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */ 248 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
244 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */ 249 0x00, 0x02, /* CE_REG_FR_BYPASS__A */
245 0x00,0x02, /* CE_REG_FR_BYPASS__A */ 250 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
246 0x0D,0x00, /* CE_REG_FR_PM_SET__A */ 251 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
247 0x07,0x00, /* CE_REG_FR_ERR_SH__A */ 252 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
248 0x04,0x00, /* CE_REG_FR_MAN_SH__A */ 253 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
249 0x06,0x00, /* CE_REG_FR_TAP_SH__A */ 254
250 255 END_OF_TABLE
251 END_OF_TABLE
252}; 256};
253 257
254 258u8_t DRXD_InitFEA2_1[] = {
255u8_t DRXD_InitFEA2_1[] = 259 WRBLOCK(FE_AD_REG_PD__A, 3),
256{ 260 0x00, 0x00, /* FE_AD_REG_PD__A */
257 WRBLOCK(FE_AD_REG_PD__A , 3), 261 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
258 0x00,0x00, /* FE_AD_REG_PD__A */ 262 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
259 0x01,0x00, /* FE_AD_REG_INVEXT__A */ 263
260 0x00,0x00, /* FE_AD_REG_CLKNEG__A */ 264 WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
261 265 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
262 WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A , 2), 266 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
263 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */ 267
264 0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */ 268 WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
265 269 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
266 WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A , 2), 270 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
267 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */ 271
268 0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */ 272 WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
269 273 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
270 WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A , 5), 274 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
271 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */ 275 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
272 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */ 276 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
273 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */ 277 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
274 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */ 278
275 0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */ 279 WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
276 280 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
277 WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A , 2), 281 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
278 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */ 282
279 0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */ 283 WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
280 284 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
281 WRBLOCK(FE_AG_REG_IND_WIN__A , 29), 285 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
282 0x00,0x00, /* FE_AG_REG_IND_WIN__A */ 286 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
283 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */ 287 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
284 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */ 288 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
285 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */ 289 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
286 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */ 290 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
287 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */ 291 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
288 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */ 292 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
289 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */ 293 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
290 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */ 294 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
291 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */ 295 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
292 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */ 296 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
293 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */ 297 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
294 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */ 298 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
295 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */ 299 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
296 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */ 300 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
297 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */ 301 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
298 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */ 302 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
299 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */ 303 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
300 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */ 304 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
301 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */ 305 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
302 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */ 306 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
303 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */ 307 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
304 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */ 308 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
305 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */ 309 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
306 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */ 310 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
307 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */ 311 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
308 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */ 312 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
309 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */ 313
310 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */ 314 WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
311 315 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
312 WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A , 2), 316 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
313 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */ 317
314 0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */ 318 WRBLOCK(FE_FD_REG_SCL__A, 3),
315 319 0x05, 0x00, /* FE_FD_REG_SCL__A */
316 WRBLOCK(FE_FD_REG_SCL__A , 3), 320 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
317 0x05,0x00, /* FE_FD_REG_SCL__A */ 321 0x05, 0x00, /* FE_FD_REG_NR__A */
318 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */ 322
319 0x05,0x00, /* FE_FD_REG_NR__A */ 323 WRBLOCK(FE_CF_REG_SCL__A, 5),
320 324 0x16, 0x00, /* FE_CF_REG_SCL__A */
321 WRBLOCK(FE_CF_REG_SCL__A , 5), 325 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
322 0x16,0x00, /* FE_CF_REG_SCL__A */ 326 0x06, 0x00, /* FE_CF_REG_NR__A */
323 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */ 327 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
324 0x06,0x00, /* FE_CF_REG_NR__A */ 328 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
325 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */ 329
326 0x01,0x00, /* FE_CF_REG_MEAS_VAL__A */ 330 WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
327 331 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
328 WRBLOCK(FE_CU_REG_FRM_CNT_RST__A , 2), 332 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
329 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */ 333
330 0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */ 334 END_OF_TABLE
331
332 END_OF_TABLE
333}; 335};
334 336
335 /* with PGA */ 337 /* with PGA */
@@ -339,603 +341,589 @@ u8_t DRXD_InitFEA2_1[] =
339/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ 341/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
340/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ 342/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
341 343
342u8_t DRXD_InitFEA2_2[] = 344u8_t DRXD_InitFEA2_2[] = {
343{ 345 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
344 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), 346 WR16(FE_AG_REG_FGM_WRI__A, 48),
345 WR16(FE_AG_REG_FGM_WRI__A , 48), 347 /* Activate measurement, activate scale */
346 /* Activate measurement, activate scale */ 348 WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
347 WR16(FE_FD_REG_MEAS_VAL__A , 0x0001), 349
348 350 WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
349 WR16(FE_CU_REG_COMM_EXEC__A, 0x0001), 351 WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
350 WR16(FE_CF_REG_COMM_EXEC__A, 0x0001), 352 WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
351 WR16(FE_IF_REG_COMM_EXEC__A, 0x0001), 353 WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
352 WR16(FE_FD_REG_COMM_EXEC__A, 0x0001), 354 WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
353 WR16(FE_FS_REG_COMM_EXEC__A, 0x0001), 355 WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
354 WR16(FE_AD_REG_COMM_EXEC__A , 0x0001), 356 WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
355 WR16(FE_AG_REG_COMM_EXEC__A , 0x0001), 357 WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
356 WR16(FE_AG_REG_AG_MODE_LOP__A , 0x895E), 358
357 359 END_OF_TABLE
358 END_OF_TABLE
359}; 360};
360 361
361u8_t DRXD_InitFEB1_1[] = 362u8_t DRXD_InitFEB1_1[] = {
362{ 363 WR16(B_FE_AD_REG_PD__A, 0x0000),
363 WR16(B_FE_AD_REG_PD__A ,0x0000 ), 364 WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
364 WR16(B_FE_AD_REG_CLKNEG__A ,0x0000 ), 365 WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
365 WR16(B_FE_AG_REG_BGC_FGC_WRI__A ,0x0000 ), 366 WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
366 WR16(B_FE_AG_REG_BGC_CGC_WRI__A ,0x0000 ), 367 WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
367 WR16(B_FE_AG_REG_AG_MODE_LOP__A ,0x000a ), 368 WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
368 WR16(B_FE_AG_REG_IND_PD1_WRI__A ,35 ), 369 WR16(B_FE_AG_REG_IND_WIN__A, 0),
369 WR16(B_FE_AG_REG_IND_WIN__A ,0 ), 370 WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
370 WR16(B_FE_AG_REG_IND_THD_LOL__A ,8 ), 371 WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
371 WR16(B_FE_AG_REG_IND_THD_HIL__A ,8 ), 372 WR16(B_FE_CF_REG_IMP_VAL__A, 1),
372 WR16(B_FE_CF_REG_IMP_VAL__A ,1 ), 373 WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
373 WR16(B_FE_AG_REG_EGC_FLA_RGN__A ,7 ), 374 END_OF_TABLE
374 END_OF_TABLE
375}; 375};
376
376 /* with PGA */ 377 /* with PGA */
377/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */ 378/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
378 /* without PGA */ 379 /* without PGA */
379/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 380/* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
380 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/ 381 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
381/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/ 382 /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
382/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ 383/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
383 384
384u8_t DRXD_InitFEB1_2[] = 385u8_t DRXD_InitFEB1_2[] = {
385{ 386 WR16(B_FE_COMM_EXEC__A, 0x0001),
386 WR16(B_FE_COMM_EXEC__A ,0x0001 ), 387
387 388 /* RF-AGC setup */
388 /* RF-AGC setup */ 389 WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
389 WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C ), 390 WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
390 WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01 ), 391 WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
391 WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02 ), 392 WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
392 WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ), 393 WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
393 WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ), 394 WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
394 WR16(B_FE_AG_REG_PDC_MAX__A , 0x02 ), 395 WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
395 WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C ), 396 WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
396 WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22 ), 397 WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
397 WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15 ), 398 WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
398 WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01 ), 399 WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
399 WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A ), 400
400 401 WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
401 WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0 ), 402 WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
402 WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000 ), 403 WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
403 WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1 ), 404 END_OF_TABLE
404 END_OF_TABLE
405}; 405};
406 406
407u8_t DRXD_InitCPA2[] = 407u8_t DRXD_InitCPA2[] = {
408{ 408 WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
409 WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2), 409 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
410 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */ 410 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
411 0x0A,0x00, /* CP_REG_BR_STR_DEL__A */ 411
412 412 WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
413 WRBLOCK(CP_REG_RT_ANG_INC0__A , 4), 413 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
414 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */ 414 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
415 0x00,0x00, /* CP_REG_RT_ANG_INC1__A */ 415 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
416 0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */ 416 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
417 0x03,0x00, /* CP_REG_RT_DETECT_TRH__A */ 417
418 418 WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
419 WRBLOCK(CP_REG_AC_NEXP_OFFS__A , 5), 419 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
420 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */ 420 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
421 0x62,0x00, /* CP_REG_AC_AVER_POW__A */ 421 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
422 0x82,0x00, /* CP_REG_AC_MAX_POW__A */ 422 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
423 0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */ 423 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
424 0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A */ 424
425 425 WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
426 WRBLOCK(CP_REG_AC_AMP_MODE__A ,2), 426 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
427 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */ 427 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
428 0x01,0x00, /* CP_REG_AC_AMP_FIX__A */ 428
429 429 WR16(CP_REG_INTERVAL__A, 0x0005),
430 WR16(CP_REG_INTERVAL__A , 0x0005 ), 430 WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
431 WR16(CP_REG_RT_EXP_MARG__A , 0x0004 ), 431 WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
432 WR16(CP_REG_AC_ANG_MODE__A , 0x0003 ), 432
433 433 WR16(CP_REG_COMM_EXEC__A, 0x0001),
434 WR16(CP_REG_COMM_EXEC__A , 0x0001 ), 434 END_OF_TABLE
435 END_OF_TABLE
436}; 435};
437 436
438u8_t DRXD_InitCPB1[] = 437u8_t DRXD_InitCPB1[] = {
439{ 438 WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
440 WR16(B_CP_REG_BR_SPL_OFFSET__A ,0x0008 ), 439 WR16(B_CP_COMM_EXEC__A, 0x0001),
441 WR16(B_CP_COMM_EXEC__A ,0x0001 ), 440 END_OF_TABLE
442 END_OF_TABLE
443}; 441};
444 442
443u8_t DRXD_InitCEA2[] = {
444 WRBLOCK(CE_REG_AVG_POW__A, 4),
445 0x62, 0x00, /* CE_REG_AVG_POW__A */
446 0x78, 0x00, /* CE_REG_MAX_POW__A */
447 0x62, 0x00, /* CE_REG_ATT__A */
448 0x17, 0x00, /* CE_REG_NRED__A */
445 449
446u8_t DRXD_InitCEA2[] = 450 WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
447{ 451 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
448 WRBLOCK(CE_REG_AVG_POW__A , 4), 452 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
449 0x62,0x00, /* CE_REG_AVG_POW__A */
450 0x78,0x00, /* CE_REG_MAX_POW__A */
451 0x62,0x00, /* CE_REG_ATT__A */
452 0x17,0x00, /* CE_REG_NRED__A */
453
454 WRBLOCK(CE_REG_NE_ERR_SELECT__A , 2),
455 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */
456 0xEB,0xFF, /* CE_REG_NE_TD_CAL__A */
457 453
458 WRBLOCK(CE_REG_NE_MIXAVG__A , 2), 454 WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
459 0x06,0x00, /* CE_REG_NE_MIXAVG__A */ 455 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
460 0x00,0x00, /* CE_REG_NE_NUPD_OFS__A */ 456 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
461 457
462 WRBLOCK(CE_REG_PE_NEXP_OFFS__A , 2), 458 WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
463 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */ 459 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
464 0x00,0x00, /* CE_REG_PE_TIMESHIFT__A */ 460 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
465 461
466 WRBLOCK(CE_REG_TP_A0_TAP_NEW__A , 3), 462 WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
467 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */ 463 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
468 0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */ 464 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
469 0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */ 465 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
470 466
471 WRBLOCK(CE_REG_TP_A1_TAP_NEW__A , 3), 467 WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
472 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */ 468 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
473 0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */ 469 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
474 0x0A,0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */ 470 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
475 471
476 WRBLOCK(CE_REG_FI_SHT_INCR__A , 2), 472 WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
477 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */ 473 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
478 0x0C,0x00, /* CE_REG_FI_EXP_NORM__A */ 474 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
479 475
480 WRBLOCK(CE_REG_IR_INPUTSEL__A , 3), 476 WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
481 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */ 477 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
482 0x00,0x00, /* CE_REG_IR_STARTPOS__A */ 478 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
483 0xFF,0x00, /* CE_REG_IR_NEXP_THRES__A */ 479 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
484 480
481 WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
485 482
486 WR16(CE_REG_TI_NEXP_OFFS__A ,0x0000), 483 END_OF_TABLE
487
488 END_OF_TABLE
489}; 484};
490 485
491u8_t DRXD_InitCEB1[] = 486u8_t DRXD_InitCEB1[] = {
492{ 487 WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
493 WR16(B_CE_REG_TI_PHN_ENABLE__A ,0x0001), 488 WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
494 WR16(B_CE_REG_FR_PM_SET__A ,0x000D),
495 489
496 END_OF_TABLE 490 END_OF_TABLE
497}; 491};
498 492
499u8_t DRXD_InitEQA2[] = 493u8_t DRXD_InitEQA2[] = {
500{ 494 WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
501 WRBLOCK(EQ_REG_OT_QNT_THRES0__A , 4), 495 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
502 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */ 496 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
503 0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */ 497 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
504 0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */ 498 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
505 0x02,0x00, /* EQ_REG_OT_CSI_OFFSET__A */ 499
506 500 WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
507 WR16(EQ_REG_TD_REQ_SMB_CNT__A ,0x0200 ), 501 WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
508 WR16(EQ_REG_IS_CLIP_EXP__A ,0x001F ), 502 WR16(EQ_REG_SN_OFFSET__A, (u16_t) (-7)),
509 WR16(EQ_REG_SN_OFFSET__A ,(u16_t)(-7) ), 503 WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
510 WR16(EQ_REG_RC_SEL_CAR__A ,0x0002 ), 504 WR16(EQ_REG_COMM_EXEC__A, 0x0001),
511 WR16(EQ_REG_COMM_EXEC__A ,0x0001 ), 505 END_OF_TABLE
512 END_OF_TABLE
513}; 506};
514 507
515u8_t DRXD_InitEQB1[] = 508u8_t DRXD_InitEQB1[] = {
516{ 509 WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
517 WR16(B_EQ_REG_COMM_EXEC__A ,0x0001 ), 510 END_OF_TABLE
518 END_OF_TABLE
519}; 511};
520 512
521u8_t DRXD_ResetECRAM[] = 513u8_t DRXD_ResetECRAM[] = {
522{ 514 /* Reset packet sync bytes in EC_VD ram */
523 /* Reset packet sync bytes in EC_VD ram */ 515 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
524 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), 516 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
525 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), 517 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
526 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), 518 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
527 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), 519 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
528 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), 520 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
529 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), 521 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
530 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), 522 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
531 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), 523 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
532 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), 524 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
533 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), 525 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
534 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), 526
535 527 /* Reset packet sync bytes in EC_RS ram */
536 /* Reset packet sync bytes in EC_RS ram */ 528 WR16(EC_RS_EC_RAM__A, 0x0000),
537 WR16(EC_RS_EC_RAM__A , 0x0000 ), 529 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
538 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), 530 END_OF_TABLE
539 END_OF_TABLE
540}; 531};
541 532
542u8_t DRXD_InitECA2[] = 533u8_t DRXD_InitECA2[] = {
543{ 534 WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
544 WRBLOCK( EC_SB_REG_CSI_HI__A , 6), 535 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
545 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */ 536 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
546 0x1E,0x00, /* EC_SB_REG_CSI_LO__A */ 537 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
547 0x01,0x00, /* EC_SB_REG_SMB_TGL__A */ 538 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
548 0x7F,0x00, /* EC_SB_REG_SNR_HI__A */ 539 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
549 0x7F,0x00, /* EC_SB_REG_SNR_MID__A */ 540 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
550 0x7F,0x00, /* EC_SB_REG_SNR_LO__A */ 541
551 542 WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
552 WRBLOCK( EC_RS_REG_REQ_PCK_CNT__A , 2), 543 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
553 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */ 544 DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
554 DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */ 545
555 546 WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
556 WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), 547 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
557 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ 548 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
558 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ 549 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
559 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ 550 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
560 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ 551 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
561 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ 552
562 553 WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
563 WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), 554 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
564 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ 555 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
565 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ 556
566 557 WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
567 WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), 558 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
568 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ 559 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
569 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ 560 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
570 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ 561 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
571 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ 562 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
572 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ 563 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
573 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ 564 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
574 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ 565
575 566 WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
576 WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), 567 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
577 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ 568 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
578 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ 569
579 570 WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
580 WR16(EC_SB_REG_CSI_OFS__A , 0x0001 ), 571 WR16(EC_VD_REG_FORCE__A, 0x0002),
581 WR16(EC_VD_REG_FORCE__A , 0x0002 ), 572 WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
582 WR16(EC_VD_REG_REQ_SMB_CNT__A , 0x0001 ), 573 WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
583 WR16(EC_VD_REG_RLK_ENA__A , 0x0001 ), 574 WR16(EC_OD_REG_SYNC__A, 0x0664),
584 WR16(EC_OD_REG_SYNC__A , 0x0664 ), 575 WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
585 WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), 576 WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
586 WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), 577 /* Output zero on monitorbus pads, power saving */
587 /* Output zero on monitorbus pads, power saving */ 578 WR16(EC_OC_REG_OCR_MON_UOS__A,
588 WR16(EC_OC_REG_OCR_MON_UOS__A , 579 (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
589 ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | 580 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
590 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | 581 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
591 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | 582 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
592 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | 583 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
593 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | 584 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
594 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | 585 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
595 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | 586 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
596 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | 587 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
597 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | 588 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
598 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | 589 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
599 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | 590 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
600 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), 591 WR16(EC_OC_REG_OCR_MON_WRI__A,
601 WR16(EC_OC_REG_OCR_MON_WRI__A, 592 EC_OC_REG_OCR_MON_WRI_INIT),
602 EC_OC_REG_OCR_MON_WRI_INIT ),
603 593
604/* CHK_ERROR(ResetECRAM(demod)); */ 594/* CHK_ERROR(ResetECRAM(demod)); */
605 /* Reset packet sync bytes in EC_VD ram */ 595 /* Reset packet sync bytes in EC_VD ram */
606 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), 596 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
607 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), 597 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
608 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), 598 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
609 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), 599 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
610 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), 600 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
611 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), 601 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
612 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), 602 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
613 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), 603 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
614 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), 604 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
615 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), 605 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
616 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), 606 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
617 607
618 /* Reset packet sync bytes in EC_RS ram */ 608 /* Reset packet sync bytes in EC_RS ram */
619 WR16(EC_RS_EC_RAM__A , 0x0000 ), 609 WR16(EC_RS_EC_RAM__A, 0x0000),
620 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), 610 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
621 611
622 WR16(EC_SB_REG_COMM_EXEC__A , 0x0001 ), 612 WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
623 WR16(EC_VD_REG_COMM_EXEC__A , 0x0001 ), 613 WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
624 WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), 614 WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
625 WR16(EC_RS_REG_COMM_EXEC__A , 0x0001 ), 615 WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
626 END_OF_TABLE 616 END_OF_TABLE
627}; 617};
628 618
629u8_t DRXD_InitECB1[] = 619u8_t DRXD_InitECB1[] = {
630{ 620 WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
631 WR16(B_EC_SB_REG_CSI_OFS0__A ,0x0001 ), 621 WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
632 WR16(B_EC_SB_REG_CSI_OFS1__A ,0x0001 ), 622 WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
633 WR16(B_EC_SB_REG_CSI_OFS2__A ,0x0001 ), 623 WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
634 WR16(B_EC_SB_REG_CSI_LO__A ,0x000c ), 624 WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
635 WR16(B_EC_SB_REG_CSI_HI__A ,0x0018 ), 625 WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
636 WR16(B_EC_SB_REG_SNR_HI__A ,0x007f ), 626 WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
637 WR16(B_EC_SB_REG_SNR_MID__A ,0x007f ), 627 WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
638 WR16(B_EC_SB_REG_SNR_LO__A ,0x007f ), 628
639 629 WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
640 WR16(B_EC_OC_REG_DTO_CLKMODE__A ,0x0002 ), 630 WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
641 WR16(B_EC_OC_REG_DTO_PER__A ,0x0006 ), 631 WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
642 WR16(B_EC_OC_REG_DTO_BUR__A ,0x0001 ), 632 WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
643 WR16(B_EC_OC_REG_RCR_CLKMODE__A ,0x0000 ), 633 WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
644 WR16(B_EC_OC_REG_RCN_GAI_LVL__A ,0x000D ), 634 WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
645 WR16(B_EC_OC_REG_OC_MPG_SIO__A ,0x0000 ), 635
646 636 /* Needed because shadow registers do not have correct default value */
647 /* Needed because shadow registers do not have correct default value */ 637 WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
648 WR16(B_EC_OC_REG_RCN_CST_LOP__A ,0x1000 ), 638 WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
649 WR16(B_EC_OC_REG_RCN_CST_HIP__A ,0x0000 ), 639 WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
650 WR16(B_EC_OC_REG_RCN_CRA_LOP__A ,0x0000 ), 640 WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
651 WR16(B_EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 ), 641 WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
652 WR16(B_EC_OC_REG_RCN_CLP_LOP__A ,0x0000 ), 642 WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
653 WR16(B_EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 ), 643 WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
654 WR16(B_EC_OC_REG_DTO_INC_LOP__A ,0x0000 ), 644 WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
655 WR16(B_EC_OC_REG_DTO_INC_HIP__A ,0x00C0 ), 645
656 646 WR16(B_EC_OD_REG_SYNC__A, 0x0664),
657 WR16(B_EC_OD_REG_SYNC__A ,0x0664 ), 647 WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
658 WR16(B_EC_RS_REG_REQ_PCK_CNT__A ,0x1000 ),
659 648
660/* CHK_ERROR(ResetECRAM(demod)); */ 649/* CHK_ERROR(ResetECRAM(demod)); */
661 /* Reset packet sync bytes in EC_VD ram */ 650 /* Reset packet sync bytes in EC_VD ram */
662 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), 651 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
663 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), 652 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
664 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), 653 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
665 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), 654 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
666 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), 655 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
667 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), 656 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
668 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), 657 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
669 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), 658 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
670 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), 659 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
671 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), 660 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
672 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), 661 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
673 662
674 /* Reset packet sync bytes in EC_RS ram */ 663 /* Reset packet sync bytes in EC_RS ram */
675 WR16(EC_RS_EC_RAM__A , 0x0000 ), 664 WR16(EC_RS_EC_RAM__A, 0x0000),
676 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), 665 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
677 666
678 WR16(B_EC_SB_REG_COMM_EXEC__A , 0x0001 ), 667 WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
679 WR16(B_EC_VD_REG_COMM_EXEC__A , 0x0001 ), 668 WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
680 WR16(B_EC_OD_REG_COMM_EXEC__A , 0x0001 ), 669 WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
681 WR16(B_EC_RS_REG_COMM_EXEC__A , 0x0001 ), 670 WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
682 END_OF_TABLE 671 END_OF_TABLE
683}; 672};
684 673
685u8_t DRXD_ResetECA2[] = 674u8_t DRXD_ResetECA2[] = {
686{ 675
687 676 WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
688 WR16(EC_OC_REG_COMM_EXEC__A , 0x0000 ), 677 WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
689 WR16(EC_OD_REG_COMM_EXEC__A , 0x0000 ), 678
690 679 WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
691 WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), 680 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
692 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ 681 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
693 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ 682 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
694 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ 683 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
695 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ 684 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
696 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ 685
697 686 WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
698 WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), 687 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
699 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ 688 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
700 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ 689
701 690 WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
702 WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), 691 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
703 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ 692 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
704 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ 693 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
705 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ 694 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
706 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ 695 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
707 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ 696 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
708 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ 697 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
709 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ 698
710 699 WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
711 WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), 700 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
712 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ 701 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
713 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ 702
714 703 WR16(EC_OD_REG_SYNC__A, 0x0664),
715 WR16(EC_OD_REG_SYNC__A , 0x0664 ), 704 WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
716 WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), 705 WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
717 WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), 706 /* Output zero on monitorbus pads, power saving */
718 /* Output zero on monitorbus pads, power saving */ 707 WR16(EC_OC_REG_OCR_MON_UOS__A,
719 WR16(EC_OC_REG_OCR_MON_UOS__A , 708 (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
720 ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | 709 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
721 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | 710 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
722 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | 711 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
723 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | 712 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
724 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | 713 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
725 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | 714 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
726 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | 715 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
727 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | 716 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
728 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | 717 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
729 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | 718 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
730 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | 719 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
731 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), 720 WR16(EC_OC_REG_OCR_MON_WRI__A,
732 WR16(EC_OC_REG_OCR_MON_WRI__A, 721 EC_OC_REG_OCR_MON_WRI_INIT),
733 EC_OC_REG_OCR_MON_WRI_INIT ),
734 722
735/* CHK_ERROR(ResetECRAM(demod)); */ 723/* CHK_ERROR(ResetECRAM(demod)); */
736 /* Reset packet sync bytes in EC_VD ram */ 724 /* Reset packet sync bytes in EC_VD ram */
737 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), 725 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
738 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), 726 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
739 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), 727 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
740 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), 728 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
741 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), 729 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
742 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), 730 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
743 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), 731 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
744 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), 732 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
745 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), 733 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
746 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), 734 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
747 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), 735 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
748 736
749 /* Reset packet sync bytes in EC_RS ram */ 737 /* Reset packet sync bytes in EC_RS ram */
750 WR16(EC_RS_EC_RAM__A , 0x0000 ), 738 WR16(EC_RS_EC_RAM__A, 0x0000),
751 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), 739 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
752 740
753 WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), 741 WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
754 END_OF_TABLE 742 END_OF_TABLE
755}; 743};
756 744
757u8_t DRXD_InitSC[] = 745u8_t DRXD_InitSC[] = {
758{ 746 WR16(SC_COMM_EXEC__A, 0),
759 WR16(SC_COMM_EXEC__A, 0 ), 747 WR16(SC_COMM_STATE__A, 0),
760 WR16(SC_COMM_STATE__A, 0 ),
761 748
762#ifdef COMPILE_FOR_QT 749#ifdef COMPILE_FOR_QT
763 WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ), 750 WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
764#endif 751#endif
765 752
766 /* SC is not started, this is done in SetChannels() */ 753 /* SC is not started, this is done in SetChannels() */
767 END_OF_TABLE 754 END_OF_TABLE
768}; 755};
769 756
770/* Diversity settings */ 757/* Diversity settings */
771 758
772u8_t DRXD_InitDiversityFront[] = 759u8_t DRXD_InitDiversityFront[] = {
773{ 760 /* Start demod ********* RF in , diversity out **************************** */
774 /* Start demod ********* RF in , diversity out *****************************/ 761 WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
775 WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | 762 B_SC_RA_RAM_CONFIG_FREQSCAN__M),
776 B_SC_RA_RAM_CONFIG_FREQSCAN__M ), 763
777 764 WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
778 WR16( B_SC_RA_RAM_LC_ABS_2K__A, 0x7), 765 WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
779 WR16( B_SC_RA_RAM_LC_ABS_8K__A, 0x7), 766 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
780 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), 767 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
781 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), 768 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
782 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), 769 WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
783 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), 770 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
784 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), 771 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
785 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), 772
786 773 WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
787 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), 774 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
788 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), 775 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
789 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), 776 WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
790 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), 777 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
791 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), 778 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
792 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), 779
793 780 WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
794 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), 781 WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
795 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), 782 WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
796 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), 783 WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
797 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), 784 WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
798 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), 785
799 786 WR16(B_CC_REG_DIVERSITY__A, 0x0001),
800 WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), 787 WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
801 WR16( B_EC_OC_REG_OC_MODE_HIP__A, 0x0010 ), 788 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
802 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | 789 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
803 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | 790
804 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), 791 /* 0x2a ), *//* CE to PASS mux */
805 792
806 793 END_OF_TABLE
807 /* 0x2a ),*/ /* CE to PASS mux */
808
809 END_OF_TABLE
810}; 794};
811 795
812u8_t DRXD_InitDiversityEnd[] = 796u8_t DRXD_InitDiversityEnd[] = {
813{ 797 /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
814 /* End demod *********** combining RF in and diversity in, MPEG TS out *****/ 798 /* disable near/far; switch on timing slave mode */
815 /* disable near/far; switch on timing slave mode */ 799 WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
816 WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | 800 B_SC_RA_RAM_CONFIG_FREQSCAN__M |
817 B_SC_RA_RAM_CONFIG_FREQSCAN__M | 801 B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
818 B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M | 802 B_SC_RA_RAM_CONFIG_SLAVE__M |
819 B_SC_RA_RAM_CONFIG_SLAVE__M | 803 B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
820 B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
821/* MV from CtrlDiversity */ 804/* MV from CtrlDiversity */
822 ), 805 ),
823#ifdef DRXDDIV_SRMM_SLAVING 806#ifdef DRXDDIV_SRMM_SLAVING
824 WR16( SC_RA_RAM_LC_ABS_2K__A, 0x3c7), 807 WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
825 WR16( SC_RA_RAM_LC_ABS_8K__A, 0x3c7), 808 WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
826#else 809#else
827 WR16( SC_RA_RAM_LC_ABS_2K__A, 0x7), 810 WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
828 WR16( SC_RA_RAM_LC_ABS_8K__A, 0x7), 811 WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
829#endif 812#endif
830 813
831 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), 814 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
832 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), 815 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
833 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), 816 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
834 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), 817 WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
835 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), 818 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
836 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), 819 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
837 820
838 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), 821 WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
839 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), 822 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
840 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), 823 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
841 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), 824 WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
842 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), 825 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
843 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), 826 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
844 827
845 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), 828 WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
846 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), 829 WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
847 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), 830 WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
848 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), 831 WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
849 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), 832 WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
850 833
851 WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), 834 WR16(B_CC_REG_DIVERSITY__A, 0x0001),
852 END_OF_TABLE 835 END_OF_TABLE
853}; 836};
854 837
855u8_t DRXD_DisableDiversity[] = 838u8_t DRXD_DisableDiversity[] = {
856{ 839 WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
857 WR16( B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), 840 WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
858 WR16( B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), 841 WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
859 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ), 842 B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
860 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ), 843 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
861 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ), 844 B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
862 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ), 845 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
863 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ), 846 B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
864 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ), 847 WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
865 848 B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
866 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ), 849 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
867 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ), 850 B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
868 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ), 851 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
869 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ), 852 B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
870 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ), 853
871 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ), 854 WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
872 855 B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
873 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), 856 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
874 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), 857 B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
875 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE), 858 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
876 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), 859 B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
877 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), 860 WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
878 861 B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
879 862 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
880 WR16( B_CC_REG_DIVERSITY__A, 0x0000 ), 863 B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
881 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT ), /* combining disabled*/ 864 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
882 865 B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
883 END_OF_TABLE 866
867 WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
868 WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
869 WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
870 WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
871 WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
872
873 WR16(B_CC_REG_DIVERSITY__A, 0x0000),
874 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
875
876 END_OF_TABLE
884}; 877};
885 878
886u8_t DRXD_StartDiversityFront[] = 879u8_t DRXD_StartDiversityFront[] = {
887{ 880 /* Start demod, RF in and diversity out, no combining */
888 /* Start demod, RF in and diversity out, no combining */ 881 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
889 WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), 882 WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
890 WR16( B_FE_AD_REG_FDB_IN__A, 0x0 ), 883 WR16(B_FE_AD_REG_INVEXT__A, 0x0),
891 WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), 884 WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
892 WR16( B_EQ_REG_COMM_MB__A, 0x12 ), /* EQ to MB out */ 885 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
893 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ 886 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
894 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | 887
895 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), 888 WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
896 889
897 WR16( SC_RA_RAM_ECHO_SHIFT_LIM__A, 2 ), 890 END_OF_TABLE
898
899 END_OF_TABLE
900}; 891};
901 892
902u8_t DRXD_StartDiversityEnd[] = 893u8_t DRXD_StartDiversityEnd[] = {
903{ 894 /* End demod, combining RF in and diversity in, MPEG TS out */
904 /* End demod, combining RF in and diversity in, MPEG TS out */ 895 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
905 WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), /* disable impulse noise cruncher */ 896 WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
906 WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), /* clock inversion (for sohard board) */ 897 WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apperently no mb delay matching is best */
907 WR16( B_CP_REG_BR_STR_DEL__A, 10 ), /* apperently no mb delay matching is best */
908 898
909 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ 899 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
910 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 900 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
911 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | 901 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
912 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ),
913 902
914 END_OF_TABLE 903 END_OF_TABLE
915}; 904};
916 905
917u8_t DRXD_DiversityDelay8MHZ[] = 906u8_t DRXD_DiversityDelay8MHZ[] = {
918{ 907 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
919 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50 ), 908 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
920 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50 ), 909 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
921 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 1000 - 50 ), 910 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
922 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 800 - 50 ), 911 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
923 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50 ), 912 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
924 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50 ), 913 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
925 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4800 - 50 ), 914 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
926 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 4000 - 50 ), 915 END_OF_TABLE
927 END_OF_TABLE
928}; 916};
929 917
930u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ 918u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
931{ 919{
932 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50 ), 920 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
933 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50 ), 921 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
934 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 900 - 50 ), 922 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
935 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 600 - 50 ), 923 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
936 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50 ), 924 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
937 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50 ), 925 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
938 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4500 - 50 ), 926 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
939 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ), 927 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
940 END_OF_TABLE 928 END_OF_TABLE
941}; 929};
diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h
index fa704cbf766..367930a1142 100644
--- a/drivers/media/dvb/frontends/drxd_firm.h
+++ b/drivers/media/dvb/frontends/drxd_firm.h
@@ -40,7 +40,7 @@ typedef unsigned long u32_t;
40#define HI_I2C_DELAY 84 40#define HI_I2C_DELAY 84
41#define HI_I2C_BRIDGE_DELAY 750 41#define HI_I2C_BRIDGE_DELAY 750
42 42
43#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ 43#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
44#define EQ_TD_TPS_PWR_QPSK 0x016a 44#define EQ_TD_TPS_PWR_QPSK 0x016a
45#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 45#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
46#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 46#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
@@ -65,7 +65,6 @@ typedef unsigned long u32_t;
65 65
66#define DRXD_SCAN_TIMEOUT (650) 66#define DRXD_SCAN_TIMEOUT (650)
67 67
68
69#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) 68#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
70#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) 69#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
71#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) 70#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
@@ -78,7 +77,6 @@ typedef unsigned long u32_t;
78#define DIFF_TARGET (4) 77#define DIFF_TARGET (4)
79#define DIFF_MARGIN (1) 78#define DIFF_MARGIN (1)
80 79
81
82extern u8_t DRXD_InitAtomicRead[]; 80extern u8_t DRXD_InitAtomicRead[];
83extern u8_t DRXD_HiI2cPatch_1[]; 81extern u8_t DRXD_HiI2cPatch_1[];
84extern u8_t DRXD_HiI2cPatch_3[]; 82extern u8_t DRXD_HiI2cPatch_3[];
@@ -95,7 +93,7 @@ extern u8_t DRXD_InitECA2[];
95extern u8_t DRXD_ResetECA2[]; 93extern u8_t DRXD_ResetECA2[];
96extern u8_t DRXD_ResetECRAM[]; 94extern u8_t DRXD_ResetECRAM[];
97 95
98extern u8_t DRXD_A2_microcode[]; 96extern u8_t DRXD_A2_microcode[];
99extern u32_t DRXD_A2_microcode_length; 97extern u32_t DRXD_A2_microcode_length;
100 98
101extern u8_t DRXD_InitFEB1_1[]; 99extern u8_t DRXD_InitFEB1_1[];
@@ -114,7 +112,7 @@ extern u8_t DRXD_StartDiversityEnd[];
114extern u8_t DRXD_DiversityDelay8MHZ[]; 112extern u8_t DRXD_DiversityDelay8MHZ[];
115extern u8_t DRXD_DiversityDelay6MHZ[]; 113extern u8_t DRXD_DiversityDelay6MHZ[];
116 114
117extern u8_t DRXD_B1_microcode[]; 115extern u8_t DRXD_B1_microcode[];
118extern u32_t DRXD_B1_microcode_length; 116extern u32_t DRXD_B1_microcode_length;
119 117
120#endif 118#endif
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c
index bdc004b65ea..ed6c529946d 100644
--- a/drivers/media/dvb/frontends/drxd_hard.c
+++ b/drivers/media/dvb/frontends/drxd_hard.c
@@ -62,7 +62,6 @@
62#define DRX_LOCK_FEC 2 62#define DRX_LOCK_FEC 2
63#define DRX_LOCK_DEMOD 4 63#define DRX_LOCK_DEMOD 4
64 64
65
66/****************************************************************************/ 65/****************************************************************************/
67 66
68enum CSCDState { 67enum CSCDState {
@@ -91,11 +90,11 @@ enum OperationMode {
91 90
92struct SCfgAgc { 91struct SCfgAgc {
93 enum AGC_CTRL_MODE ctrlMode; 92 enum AGC_CTRL_MODE ctrlMode;
94 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 93 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
95 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ 94 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
96 u16 minOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */ 95 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
97 u16 maxOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */ 96 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
98 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ 97 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
99 98
100 u16 R1; 99 u16 R1;
101 u16 R2; 100 u16 R2;
@@ -112,7 +111,7 @@ struct SNoiseCal {
112enum app_env { 111enum app_env {
113 APPENV_STATIC = 0, 112 APPENV_STATIC = 0,
114 APPENV_PORTABLE = 1, 113 APPENV_PORTABLE = 1,
115 APPENV_MOBILE = 2 114 APPENV_MOBILE = 2
116}; 115};
117 116
118enum EIFFilter { 117enum EIFFilter {
@@ -136,7 +135,7 @@ struct drxd_state {
136 int init_done; 135 int init_done;
137 struct semaphore mutex; 136 struct semaphore mutex;
138 137
139 u8 chip_adr; 138 u8 chip_adr;
140 u16 hi_cfg_timing_div; 139 u16 hi_cfg_timing_div;
141 u16 hi_cfg_bridge_delay; 140 u16 hi_cfg_bridge_delay;
142 u16 hi_cfg_wakeup_key; 141 u16 hi_cfg_wakeup_key;
@@ -205,14 +204,13 @@ struct drxd_state {
205 204
206}; 205};
207 206
208
209/****************************************************************************/ 207/****************************************************************************/
210/* I2C **********************************************************************/ 208/* I2C **********************************************************************/
211/****************************************************************************/ 209/****************************************************************************/
212 210
213static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) 211static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
214{ 212{
215 struct i2c_msg msg = { .addr=adr, .flags=0, .buf=data, .len=len }; 213 struct i2c_msg msg = {.addr = adr,.flags = 0,.buf = data,.len = len };
216 214
217 if (i2c_transfer(adap, &msg, 1) != 1) 215 if (i2c_transfer(adap, &msg, 1) != 1)
218 return -1; 216 return -1;
@@ -220,12 +218,13 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
220} 218}
221 219
222static int i2c_read(struct i2c_adapter *adap, 220static int i2c_read(struct i2c_adapter *adap,
223 u8 adr, u8 *msg, int len, u8 *answ, int alen) 221 u8 adr, u8 * msg, int len, u8 * answ, int alen)
224{ 222{
225 struct i2c_msg msgs[2] = { { .addr=adr, .flags=0, 223 struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0,
226 .buf=msg, .len=len }, 224 .buf = msg,.len = len},
227 { .addr=adr, .flags=I2C_M_RD, 225 {.addr = adr,.flags = I2C_M_RD,
228 .buf=answ, .len=alen } }; 226 .buf = answ,.len = alen}
227 };
229 if (i2c_transfer(adap, msgs, 2) != 2) 228 if (i2c_transfer(adap, msgs, 2) != 2)
230 return -1; 229 return -1;
231 return 0; 230 return 0;
@@ -235,75 +234,81 @@ inline u32 MulDiv32(u32 a, u32 b, u32 c)
235{ 234{
236 u64 tmp64; 235 u64 tmp64;
237 236
238 tmp64=(u64)a*(u64)b; 237 tmp64 = (u64) a *(u64) b;
239 do_div(tmp64, c); 238 do_div(tmp64, c);
240 239
241 return (u32) tmp64; 240 return (u32) tmp64;
242} 241}
243 242
244static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) 243static int Read16(struct drxd_state *state, u32 reg, u16 * data, u8 flags)
245{ 244{
246 u8 adr=state->config.demod_address; 245 u8 adr = state->config.demod_address;
247 u8 mm1[4]={reg&0xff, (reg>>16)&0xff, 246 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
248 flags|((reg>>24)&0xff), (reg>>8)&0xff}; 247 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
248 };
249 u8 mm2[2]; 249 u8 mm2[2];
250 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2)<0) 250 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
251 return -1; 251 return -1;
252 if (data) 252 if (data)
253 *data=mm2[0]|(mm2[1]<<8); 253 *data = mm2[0] | (mm2[1] << 8);
254 return mm2[0]|(mm2[1]<<8); 254 return mm2[0] | (mm2[1] << 8);
255} 255}
256 256
257static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) 257static int Read32(struct drxd_state *state, u32 reg, u32 * data, u8 flags)
258{ 258{
259 u8 adr=state->config.demod_address; 259 u8 adr = state->config.demod_address;
260 u8 mm1[4]={reg&0xff, (reg>>16)&0xff, 260 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
261 flags|((reg>>24)&0xff), (reg>>8)&0xff}; 261 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
262 };
262 u8 mm2[4]; 263 u8 mm2[4];
263 264
264 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4)<0) 265 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
265 return -1; 266 return -1;
266 if (data) 267 if (data)
267 *data=mm2[0]|(mm2[1]<<8)|(mm2[2]<<16)|(mm2[3]<<24); 268 *data =
269 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
268 return 0; 270 return 0;
269} 271}
270 272
271static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) 273static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
272{ 274{
273 u8 adr=state->config.demod_address; 275 u8 adr = state->config.demod_address;
274 u8 mm[6]={ reg&0xff, (reg>>16)&0xff, 276 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
275 flags|((reg>>24)&0xff), (reg>>8)&0xff, 277 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
276 data&0xff, (data>>8)&0xff }; 278 data & 0xff, (data >> 8) & 0xff
279 };
277 280
278 if (i2c_write(state->i2c, adr, mm, 6)<0) 281 if (i2c_write(state->i2c, adr, mm, 6) < 0)
279 return -1; 282 return -1;
280 return 0; 283 return 0;
281} 284}
282 285
283static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) 286static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
284{ 287{
285 u8 adr=state->config.demod_address; 288 u8 adr = state->config.demod_address;
286 u8 mm[8]={ reg&0xff, (reg>>16)&0xff, 289 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
287 flags|((reg>>24)&0xff), (reg>>8)&0xff, 290 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
288 data&0xff, (data>>8)&0xff, 291 data & 0xff, (data >> 8) & 0xff,
289 (data>>16)&0xff, (data>>24)&0xff }; 292 (data >> 16) & 0xff, (data >> 24) & 0xff
293 };
290 294
291 if (i2c_write(state->i2c, adr, mm, 8)<0) 295 if (i2c_write(state->i2c, adr, mm, 8) < 0)
292 return -1; 296 return -1;
293 return 0; 297 return 0;
294} 298}
295 299
296static int write_chunk(struct drxd_state *state, 300static int write_chunk(struct drxd_state *state,
297 u32 reg, u8 *data, u32 len, u8 flags) 301 u32 reg, u8 * data, u32 len, u8 flags)
298{ 302{
299 u8 adr=state->config.demod_address; 303 u8 adr = state->config.demod_address;
300 u8 mm[CHUNK_SIZE+4]={ reg&0xff, (reg>>16)&0xff, 304 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
301 flags|((reg>>24)&0xff), (reg>>8)&0xff }; 305 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
306 };
302 int i; 307 int i;
303 308
304 for (i=0; i<len; i++) 309 for (i = 0; i < len; i++)
305 mm[4+i]=data[i]; 310 mm[4 + i] = data[i];
306 if (i2c_write(state->i2c, adr, mm, 4+len)<0) { 311 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
307 printk("error in write_chunk\n"); 312 printk("error in write_chunk\n");
308 return -1; 313 return -1;
309 } 314 }
@@ -311,12 +316,12 @@ static int write_chunk(struct drxd_state *state,
311} 316}
312 317
313static int WriteBlock(struct drxd_state *state, 318static int WriteBlock(struct drxd_state *state,
314 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) 319 u32 Address, u16 BlockSize, u8 * pBlock, u8 Flags)
315{ 320{
316 while(BlockSize > 0) { 321 while (BlockSize > 0) {
317 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; 322 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
318 323
319 if (write_chunk(state, Address, pBlock, Chunk, Flags)<0) 324 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
320 return -1; 325 return -1;
321 pBlock += Chunk; 326 pBlock += Chunk;
322 Address += (Chunk >> 1); 327 Address += (Chunk >> 1);
@@ -325,33 +330,32 @@ static int WriteBlock(struct drxd_state *state,
325 return 0; 330 return 0;
326} 331}
327 332
328static int WriteTable(struct drxd_state *state, u8 *pTable) 333static int WriteTable(struct drxd_state *state, u8 * pTable)
329{ 334{
330 int status = 0; 335 int status = 0;
331 336
332 if( pTable == NULL ) 337 if (pTable == NULL)
333 return 0; 338 return 0;
334 339
335 while(!status) { 340 while (!status) {
336 u16 Length; 341 u16 Length;
337 u32 Address = pTable[0]|(pTable[1]<<8)| 342 u32 Address = pTable[0] | (pTable[1] << 8) |
338 (pTable[2]<<16)|(pTable[3]<<24); 343 (pTable[2] << 16) | (pTable[3] << 24);
339 344
340 if (Address==0xFFFFFFFF) 345 if (Address == 0xFFFFFFFF)
341 break; 346 break;
342 pTable += sizeof(u32); 347 pTable += sizeof(u32);
343 348
344 Length = pTable[0]|(pTable[1]<<8); 349 Length = pTable[0] | (pTable[1] << 8);
345 pTable += sizeof(u16); 350 pTable += sizeof(u16);
346 if (!Length) 351 if (!Length)
347 break; 352 break;
348 status = WriteBlock(state, Address, Length*2, pTable, 0); 353 status = WriteBlock(state, Address, Length * 2, pTable, 0);
349 pTable += (Length*2); 354 pTable += (Length * 2);
350 } 355 }
351 return status; 356 return status;
352} 357}
353 358
354
355/****************************************************************************/ 359/****************************************************************************/
356/****************************************************************************/ 360/****************************************************************************/
357/****************************************************************************/ 361/****************************************************************************/
@@ -375,32 +379,32 @@ static int InitCE(struct drxd_state *state)
375 CHK_ERROR(WriteTable(state, state->m_InitCE)); 379 CHK_ERROR(WriteTable(state, state->m_InitCE));
376 380
377 if (state->operation_mode == OM_DVBT_Diversity_Front || 381 if (state->operation_mode == OM_DVBT_Diversity_Front ||
378 state->operation_mode == OM_DVBT_Diversity_End ) { 382 state->operation_mode == OM_DVBT_Diversity_End) {
379 AppEnv = state->app_env_diversity; 383 AppEnv = state->app_env_diversity;
380 } 384 }
381 if ( AppEnv == APPENV_STATIC ) { 385 if (AppEnv == APPENV_STATIC) {
382 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0000,0)); 386 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0000, 0));
383 } else if( AppEnv == APPENV_PORTABLE ) { 387 } else if (AppEnv == APPENV_PORTABLE) {
384 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0001,0)); 388 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0001, 0));
385 } else if( AppEnv == APPENV_MOBILE && state->type_A ) { 389 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
386 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0002,0)); 390 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0002, 0));
387 } else if( AppEnv == APPENV_MOBILE && !state->type_A ) { 391 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
388 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0006,0)); 392 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0006, 0));
389 } 393 }
390 394
391 /* start ce */ 395 /* start ce */
392 CHK_ERROR(Write16(state,B_CE_REG_COMM_EXEC__A,0x0001,0)); 396 CHK_ERROR(Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0));
393 } while(0); 397 } while (0);
394 return status; 398 return status;
395} 399}
396 400
397static int StopOC(struct drxd_state *state) 401static int StopOC(struct drxd_state *state)
398{ 402{
399 int status = 0; 403 int status = 0;
400 u16 ocSyncLvl = 0; 404 u16 ocSyncLvl = 0;
401 u16 ocModeLop = state->m_EcOcRegOcModeLop; 405 u16 ocModeLop = state->m_EcOcRegOcModeLop;
402 u16 dtoIncLop = 0; 406 u16 dtoIncLop = 0;
403 u16 dtoIncHip = 0; 407 u16 dtoIncHip = 0;
404 408
405 do { 409 do {
406 /* Store output configuration */ 410 /* Store output configuration */
@@ -413,65 +417,65 @@ static int StopOC(struct drxd_state *state)
413 417
414 /* Flush FIFO (byte-boundary) at fixed rate */ 418 /* Flush FIFO (byte-boundary) at fixed rate */
415 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A, 419 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A,
416 &dtoIncLop,0 )); 420 &dtoIncLop, 0));
417 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A, 421 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A,
418 &dtoIncHip,0 )); 422 &dtoIncHip, 0));
419 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A, 423 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A,
420 dtoIncLop,0 )); 424 dtoIncLop, 0));
421 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A, 425 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A,
422 dtoIncHip,0 )); 426 dtoIncHip, 0));
423 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); 427 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
424 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; 428 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
425 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 429 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
426 ocModeLop,0 )); 430 ocModeLop, 0));
427 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 431 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
428 EC_OC_REG_COMM_EXEC_CTL_HOLD,0 )); 432 EC_OC_REG_COMM_EXEC_CTL_HOLD, 0));
429 433
430 msleep(1); 434 msleep(1);
431 /* Output pins to '0' */ 435 /* Output pins to '0' */
432 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, 436 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A,
433 EC_OC_REG_OCR_MPG_UOS__M,0 )); 437 EC_OC_REG_OCR_MPG_UOS__M, 0));
434 438
435 /* Force the OC out of sync */ 439 /* Force the OC out of sync */
436 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); 440 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
437 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, 441 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A,
438 ocSyncLvl,0 )); 442 ocSyncLvl, 0));
439 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); 443 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
440 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; 444 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
441 ocModeLop |= 0x2; /* Magically-out-of-sync */ 445 ocModeLop |= 0x2; /* Magically-out-of-sync */
442 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 446 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
443 ocModeLop,0 )); 447 ocModeLop, 0));
444 CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0,0 )); 448 CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0));
445 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 449 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
446 EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 )); 450 EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0));
447 } while(0); 451 } while (0);
448 452
449 return status; 453 return status;
450} 454}
451 455
452static int StartOC(struct drxd_state *state) 456static int StartOC(struct drxd_state *state)
453{ 457{
454 int status=0; 458 int status = 0;
455 459
456 do { 460 do {
457 /* Stop OC */ 461 /* Stop OC */
458 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 462 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
459 EC_OC_REG_COMM_EXEC_CTL_HOLD,0 )); 463 EC_OC_REG_COMM_EXEC_CTL_HOLD, 0));
460 464
461 /* Restore output configuration */ 465 /* Restore output configuration */
462 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, 466 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A,
463 state->m_EcOcRegSncSncLvl,0 )); 467 state->m_EcOcRegSncSncLvl, 0));
464 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 468 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
465 state->m_EcOcRegOcModeLop,0 )); 469 state->m_EcOcRegOcModeLop, 0));
466 470
467 /* Output pins active again */ 471 /* Output pins active again */
468 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, 472 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A,
469 EC_OC_REG_OCR_MPG_UOS_INIT,0 )); 473 EC_OC_REG_OCR_MPG_UOS_INIT, 0));
470 474
471 /* Start OC */ 475 /* Start OC */
472 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 476 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
473 EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 )); 477 EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0));
474 } while(0); 478 } while (0);
475 return status; 479 return status;
476} 480}
477 481
@@ -497,40 +501,39 @@ static int InitAtomicRead(struct drxd_state *state)
497 501
498static int CorrectSysClockDeviation(struct drxd_state *state); 502static int CorrectSysClockDeviation(struct drxd_state *state);
499 503
500static int DRX_GetLockStatus(struct drxd_state *state, u32 *pLockStatus) 504static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
501{ 505{
502 u16 ScRaRamLock = 0; 506 u16 ScRaRamLock = 0;
503 const u16 mpeg_lock_mask = ( SC_RA_RAM_LOCK_MPEG__M | 507 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
504 SC_RA_RAM_LOCK_FEC__M | 508 SC_RA_RAM_LOCK_FEC__M |
505 SC_RA_RAM_LOCK_DEMOD__M ); 509 SC_RA_RAM_LOCK_DEMOD__M);
506 const u16 fec_lock_mask = ( SC_RA_RAM_LOCK_FEC__M | 510 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
507 SC_RA_RAM_LOCK_DEMOD__M ); 511 SC_RA_RAM_LOCK_DEMOD__M);
508 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M ; 512 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
509 513
510 int status; 514 int status;
511 515
512 *pLockStatus=0; 516 *pLockStatus = 0;
513 517
514 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000 ); 518 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
515 if(status<0) { 519 if (status < 0) {
516 printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", 520 printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
517 status);
518 return status; 521 return status;
519 } 522 }
520 523
521 if( state->drxd_state != DRXD_STARTED ) 524 if (state->drxd_state != DRXD_STARTED)
522 return 0; 525 return 0;
523 526
524 if ( (ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask ) { 527 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
525 *pLockStatus|=DRX_LOCK_MPEG; 528 *pLockStatus |= DRX_LOCK_MPEG;
526 CorrectSysClockDeviation(state); 529 CorrectSysClockDeviation(state);
527 } 530 }
528 531
529 if ( (ScRaRamLock & fec_lock_mask) == fec_lock_mask ) 532 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
530 *pLockStatus|=DRX_LOCK_FEC; 533 *pLockStatus |= DRX_LOCK_FEC;
531 534
532 if ( (ScRaRamLock & demod_lock_mask) == demod_lock_mask ) 535 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
533 *pLockStatus|=DRX_LOCK_DEMOD; 536 *pLockStatus |= DRX_LOCK_DEMOD;
534 return 0; 537 return 0;
535} 538}
536 539
@@ -540,35 +543,33 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
540{ 543{
541 int status; 544 int status;
542 545
543 if( cfg->outputLevel > DRXD_FE_CTRL_MAX ) 546 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
544 return -1; 547 return -1;
545 548
546 if( cfg->ctrlMode == AGC_CTRL_USER ) { 549 if (cfg->ctrlMode == AGC_CTRL_USER) {
547 do { 550 do {
548 u16 FeAgRegPm1AgcWri; 551 u16 FeAgRegPm1AgcWri;
549 u16 FeAgRegAgModeLop; 552 u16 FeAgRegAgModeLop;
550 553
551 CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, 554 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
552 &FeAgRegAgModeLop,0)); 555 &FeAgRegAgModeLop, 0));
553 FeAgRegAgModeLop &= 556 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
554 (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 557 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
555 FeAgRegAgModeLop |= 558 CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
556 FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; 559 FeAgRegAgModeLop, 0));
557 CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A, 560
558 FeAgRegAgModeLop,0)); 561 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
559 562 FE_AG_REG_PM1_AGC_WRI__M);
560 FeAgRegPm1AgcWri = (u16)(cfg->outputLevel & 563 CHK_ERROR(Write16(state, FE_AG_REG_PM1_AGC_WRI__A,
561 FE_AG_REG_PM1_AGC_WRI__M); 564 FeAgRegPm1AgcWri, 0));
562 CHK_ERROR(Write16(state,FE_AG_REG_PM1_AGC_WRI__A,
563 FeAgRegPm1AgcWri,0));
564 } 565 }
565 while(0); 566 while (0);
566 } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) { 567 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
567 if ( ( (cfg->maxOutputLevel) < (cfg->minOutputLevel) ) || 568 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
568 ( (cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX ) || 569 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
569 ( (cfg->speed) > DRXD_FE_CTRL_MAX ) || 570 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
570 ( (cfg->settleLevel) > DRXD_FE_CTRL_MAX ) 571 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
571 ) 572 )
572 return (-1); 573 return (-1);
573 do { 574 do {
574 u16 FeAgRegAgModeLop; 575 u16 FeAgRegAgModeLop;
@@ -577,94 +578,95 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
577 578
578 /* == Mode == */ 579 /* == Mode == */
579 580
580 CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, 581 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
581 &FeAgRegAgModeLop,0)); 582 &FeAgRegAgModeLop, 0));
582 FeAgRegAgModeLop &= 583 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
583 (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
584 FeAgRegAgModeLop |= 584 FeAgRegAgModeLop |=
585 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; 585 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
586 CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A, 586 CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
587 FeAgRegAgModeLop,0)); 587 FeAgRegAgModeLop, 0));
588 588
589 /* == Settle level == */ 589 /* == Settle level == */
590 590
591 FeAgRegEgcSetLvl = (u16)(( cfg->settleLevel >> 1 ) & 591 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
592 FE_AG_REG_EGC_SET_LVL__M ); 592 FE_AG_REG_EGC_SET_LVL__M);
593 CHK_ERROR(Write16(state,FE_AG_REG_EGC_SET_LVL__A, 593 CHK_ERROR(Write16(state, FE_AG_REG_EGC_SET_LVL__A,
594 FeAgRegEgcSetLvl,0)); 594 FeAgRegEgcSetLvl, 0));
595 595
596 /* == Min/Max == */ 596 /* == Min/Max == */
597 597
598 slope = (u16)(( cfg->maxOutputLevel - 598 slope = (u16) ((cfg->maxOutputLevel -
599 cfg->minOutputLevel )/2); 599 cfg->minOutputLevel) / 2);
600 offset = (u16)(( cfg->maxOutputLevel + 600 offset = (u16) ((cfg->maxOutputLevel +
601 cfg->minOutputLevel )/2 - 511); 601 cfg->minOutputLevel) / 2 - 511);
602 602
603 CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_RIC__A, 603 CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_RIC__A,
604 slope,0)); 604 slope, 0));
605 CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_OFF__A, 605 CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_OFF__A,
606 offset,0)); 606 offset, 0));
607 607
608 /* == Speed == */ 608 /* == Speed == */
609 { 609 {
610 const u16 maxRur = 8; 610 const u16 maxRur = 8;
611 const u16 slowIncrDecLUT[]={ 3, 4, 4, 5, 6 }; 611 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
612 const u16 fastIncrDecLUT[]={ 14, 15, 15, 16, 612 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
613 17, 18, 18, 19, 613 17, 18, 18, 19,
614 20, 21, 22, 23, 614 20, 21, 22, 23,
615 24, 26, 27, 28, 615 24, 26, 27, 28,
616 29, 31}; 616 29, 31
617 617 };
618 u16 fineSteps = (DRXD_FE_CTRL_MAX+1)/ 618
619 (maxRur+1); 619 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
620 u16 fineSpeed = (u16)(cfg->speed - 620 (maxRur + 1);
621 ((cfg->speed/ 621 u16 fineSpeed = (u16) (cfg->speed -
622 fineSteps)* 622 ((cfg->speed /
623 fineSteps) *
623 fineSteps)); 624 fineSteps));
624 u16 invRurCount= (u16)(cfg->speed / 625 u16 invRurCount = (u16) (cfg->speed /
625 fineSteps); 626 fineSteps);
626 u16 rurCount; 627 u16 rurCount;
627 if ( invRurCount > maxRur ) 628 if (invRurCount > maxRur) {
628 { 629 rurCount = 0;
629 rurCount = 0;
630 fineSpeed += fineSteps; 630 fineSpeed += fineSteps;
631 } else { 631 } else {
632 rurCount = maxRur - invRurCount; 632 rurCount = maxRur - invRurCount;
633 } 633 }
634 634
635 /* 635 /*
636 fastInc = default * 636 fastInc = default *
637 (2^(fineSpeed/fineSteps)) 637 (2^(fineSpeed/fineSteps))
638 => range[default...2*default> 638 => range[default...2*default>
639 slowInc = default * 639 slowInc = default *
640 (2^(fineSpeed/fineSteps)) 640 (2^(fineSpeed/fineSteps))
641 */ 641 */
642 { 642 {
643 u16 fastIncrDec = 643 u16 fastIncrDec =
644 fastIncrDecLUT[fineSpeed/ 644 fastIncrDecLUT[fineSpeed /
645 ((fineSteps/ 645 ((fineSteps /
646 (14+1))+1) ]; 646 (14 + 1)) + 1)];
647 u16 slowIncrDec = slowIncrDecLUT[ 647 u16 slowIncrDec =
648 fineSpeed/(fineSteps/(3+1)) ]; 648 slowIncrDecLUT[fineSpeed /
649 (fineSteps /
650 (3 + 1))];
649 651
650 CHK_ERROR(Write16(state, 652 CHK_ERROR(Write16(state,
651 FE_AG_REG_EGC_RUR_CNT__A, 653 FE_AG_REG_EGC_RUR_CNT__A,
652 rurCount, 0)); 654 rurCount, 0));
653 CHK_ERROR(Write16(state, 655 CHK_ERROR(Write16(state,
654 FE_AG_REG_EGC_FAS_INC__A, 656 FE_AG_REG_EGC_FAS_INC__A,
655 fastIncrDec, 0)); 657 fastIncrDec, 0));
656 CHK_ERROR(Write16(state, 658 CHK_ERROR(Write16(state,
657 FE_AG_REG_EGC_FAS_DEC__A, 659 FE_AG_REG_EGC_FAS_DEC__A,
658 fastIncrDec, 0)); 660 fastIncrDec, 0));
659 CHK_ERROR(Write16(state, 661 CHK_ERROR(Write16(state,
660 FE_AG_REG_EGC_SLO_INC__A, 662 FE_AG_REG_EGC_SLO_INC__A,
661 slowIncrDec, 0)); 663 slowIncrDec, 0));
662 CHK_ERROR(Write16(state, 664 CHK_ERROR(Write16(state,
663 FE_AG_REG_EGC_SLO_DEC__A, 665 FE_AG_REG_EGC_SLO_DEC__A,
664 slowIncrDec, 0)); 666 slowIncrDec, 0));
665 } 667 }
666 } 668 }
667 } while(0); 669 } while (0);
668 670
669 } else { 671 } else {
670 /* No OFF mode for IF control */ 672 /* No OFF mode for IF control */
@@ -673,90 +675,87 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
673 return status; 675 return status;
674} 676}
675 677
676
677static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) 678static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
678{ 679{
679 int status = 0; 680 int status = 0;
680 681
681 if( cfg->outputLevel > DRXD_FE_CTRL_MAX ) 682 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
682 return -1; 683 return -1;
683 684
684 if( cfg->ctrlMode == AGC_CTRL_USER ) { 685 if (cfg->ctrlMode == AGC_CTRL_USER) {
685 do { 686 do {
686 u16 AgModeLop=0; 687 u16 AgModeLop = 0;
687 u16 level = ( cfg->outputLevel ); 688 u16 level = (cfg->outputLevel);
688 689
689 if (level == DRXD_FE_CTRL_MAX ) 690 if (level == DRXD_FE_CTRL_MAX)
690 level++; 691 level++;
691 692
692 CHK_ERROR( Write16(state,FE_AG_REG_PM2_AGC_WRI__A, 693 CHK_ERROR(Write16(state, FE_AG_REG_PM2_AGC_WRI__A,
693 level, 0x0000 )); 694 level, 0x0000));
694 695
695 /*==== Mode ====*/ 696 /*==== Mode ====*/
696 697
697 /* Powerdown PD2, WRI source */ 698 /* Powerdown PD2, WRI source */
698 state->m_FeAgRegAgPwd &= 699 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
699 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
700 state->m_FeAgRegAgPwd |= 700 state->m_FeAgRegAgPwd |=
701 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 701 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
702 CHK_ERROR( Write16(state,FE_AG_REG_AG_PWD__A, 702 CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A,
703 state->m_FeAgRegAgPwd,0x0000 )); 703 state->m_FeAgRegAgPwd, 0x0000));
704
705 CHK_ERROR( Read16(state,FE_AG_REG_AG_MODE_LOP__A,
706 &AgModeLop,0x0000 ));
707 AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M |
708 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
709 AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
710 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC );
711 CHK_ERROR( Write16(state,FE_AG_REG_AG_MODE_LOP__A,
712 AgModeLop,0x0000 ));
713 704
705 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
706 &AgModeLop, 0x0000));
707 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
708 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
709 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
710 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
711 CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
712 AgModeLop, 0x0000));
714 713
715 /* enable AGC2 pin */ 714 /* enable AGC2 pin */
716 { 715 {
717 u16 FeAgRegAgAgcSio = 0; 716 u16 FeAgRegAgAgcSio = 0;
718 CHK_ERROR( Read16(state, 717 CHK_ERROR(Read16(state,
719 FE_AG_REG_AG_AGC_SIO__A, 718 FE_AG_REG_AG_AGC_SIO__A,
720 &FeAgRegAgAgcSio, 0x0000 )); 719 &FeAgRegAgAgcSio, 0x0000));
721 FeAgRegAgAgcSio &= 720 FeAgRegAgAgcSio &=
722 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 721 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
723 FeAgRegAgAgcSio |= 722 FeAgRegAgAgcSio |=
724 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 723 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
725 CHK_ERROR( Write16(state, 724 CHK_ERROR(Write16(state,
726 FE_AG_REG_AG_AGC_SIO__A, 725 FE_AG_REG_AG_AGC_SIO__A,
727 FeAgRegAgAgcSio, 0x0000 )); 726 FeAgRegAgAgcSio, 0x0000));
728 } 727 }
729 728
730 } while(0); 729 } while (0);
731 } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) { 730 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
732 u16 AgModeLop=0; 731 u16 AgModeLop = 0;
733 732
734 do { 733 do {
735 u16 level; 734 u16 level;
736 /* Automatic control */ 735 /* Automatic control */
737 /* Powerup PD2, AGC2 as output, TGC source */ 736 /* Powerup PD2, AGC2 as output, TGC source */
738 (state->m_FeAgRegAgPwd) &= 737 (state->m_FeAgRegAgPwd) &=
739 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 738 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
740 (state->m_FeAgRegAgPwd) |= 739 (state->m_FeAgRegAgPwd) |=
741 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 740 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
742 CHK_ERROR(Write16(state,FE_AG_REG_AG_PWD__A, 741 CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A,
743 (state->m_FeAgRegAgPwd),0x0000 )); 742 (state->m_FeAgRegAgPwd), 0x0000));
744 743
745 CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, 744 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
746 &AgModeLop,0x0000 )); 745 &AgModeLop, 0x0000));
747 AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | 746 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
748 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 747 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
749 AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 748 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
750 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC ); 749 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
751 CHK_ERROR(Write16(state, 750 CHK_ERROR(Write16(state,
752 FE_AG_REG_AG_MODE_LOP__A, 751 FE_AG_REG_AG_MODE_LOP__A,
753 AgModeLop, 0x0000 )); 752 AgModeLop, 0x0000));
754 /* Settle level */ 753 /* Settle level */
755 level = ( (( cfg->settleLevel )>>4) & 754 level = (((cfg->settleLevel) >> 4) &
756 FE_AG_REG_TGC_SET_LVL__M ); 755 FE_AG_REG_TGC_SET_LVL__M);
757 CHK_ERROR(Write16(state, 756 CHK_ERROR(Write16(state,
758 FE_AG_REG_TGC_SET_LVL__A, 757 FE_AG_REG_TGC_SET_LVL__A,
759 level,0x0000 )); 758 level, 0x0000));
760 759
761 /* Min/max: don't care */ 760 /* Min/max: don't care */
762 761
@@ -765,91 +764,91 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
765 /* enable AGC2 pin */ 764 /* enable AGC2 pin */
766 { 765 {
767 u16 FeAgRegAgAgcSio = 0; 766 u16 FeAgRegAgAgcSio = 0;
768 CHK_ERROR( Read16(state, 767 CHK_ERROR(Read16(state,
769 FE_AG_REG_AG_AGC_SIO__A, 768 FE_AG_REG_AG_AGC_SIO__A,
770 &FeAgRegAgAgcSio, 0x0000 )); 769 &FeAgRegAgAgcSio, 0x0000));
771 FeAgRegAgAgcSio &= 770 FeAgRegAgAgcSio &=
772 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 771 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
773 FeAgRegAgAgcSio |= 772 FeAgRegAgAgcSio |=
774 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 773 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
775 CHK_ERROR( Write16(state, 774 CHK_ERROR(Write16(state,
776 FE_AG_REG_AG_AGC_SIO__A, 775 FE_AG_REG_AG_AGC_SIO__A,
777 FeAgRegAgAgcSio, 0x0000 )); 776 FeAgRegAgAgcSio, 0x0000));
778 } 777 }
779 778
780 } while(0); 779 } while (0);
781 } else { 780 } else {
782 u16 AgModeLop=0; 781 u16 AgModeLop = 0;
783 782
784 do { 783 do {
785 /* No RF AGC control */ 784 /* No RF AGC control */
786 /* Powerdown PD2, AGC2 as output, WRI source */ 785 /* Powerdown PD2, AGC2 as output, WRI source */
787 (state->m_FeAgRegAgPwd) &= 786 (state->m_FeAgRegAgPwd) &=
788 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 787 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
789 (state->m_FeAgRegAgPwd) |= 788 (state->m_FeAgRegAgPwd) |=
790 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; 789 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
791 CHK_ERROR(Write16(state, 790 CHK_ERROR(Write16(state,
792 FE_AG_REG_AG_PWD__A, 791 FE_AG_REG_AG_PWD__A,
793 (state->m_FeAgRegAgPwd),0x0000 )); 792 (state->m_FeAgRegAgPwd), 0x0000));
794 793
795 CHK_ERROR(Read16(state, 794 CHK_ERROR(Read16(state,
796 FE_AG_REG_AG_MODE_LOP__A, 795 FE_AG_REG_AG_MODE_LOP__A,
797 &AgModeLop,0x0000 )); 796 &AgModeLop, 0x0000));
798 AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | 797 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
799 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 798 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
800 AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 799 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
801 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC ); 800 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
802 CHK_ERROR(Write16(state, 801 CHK_ERROR(Write16(state,
803 FE_AG_REG_AG_MODE_LOP__A, 802 FE_AG_REG_AG_MODE_LOP__A,
804 AgModeLop,0x0000 )); 803 AgModeLop, 0x0000));
805 804
806 /* set FeAgRegAgAgcSio AGC2 (RF) as input */ 805 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
807 { 806 {
808 u16 FeAgRegAgAgcSio = 0; 807 u16 FeAgRegAgAgcSio = 0;
809 CHK_ERROR( Read16(state, 808 CHK_ERROR(Read16(state,
810 FE_AG_REG_AG_AGC_SIO__A, 809 FE_AG_REG_AG_AGC_SIO__A,
811 &FeAgRegAgAgcSio, 0x0000 )); 810 &FeAgRegAgAgcSio, 0x0000));
812 FeAgRegAgAgcSio &= 811 FeAgRegAgAgcSio &=
813 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 812 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
814 FeAgRegAgAgcSio |= 813 FeAgRegAgAgcSio |=
815 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; 814 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
816 CHK_ERROR( Write16(state, 815 CHK_ERROR(Write16(state,
817 FE_AG_REG_AG_AGC_SIO__A, 816 FE_AG_REG_AG_AGC_SIO__A,
818 FeAgRegAgAgcSio, 0x0000 )); 817 FeAgRegAgAgcSio, 0x0000));
819 } 818 }
820 } while(0); 819 } while (0);
821 } 820 }
822 return status; 821 return status;
823} 822}
824 823
825static int ReadIFAgc(struct drxd_state *state, u32 *pValue) 824static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
826{ 825{
827 int status = 0; 826 int status = 0;
828 827
829 *pValue = 0; 828 *pValue = 0;
830 if( state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF ) { 829 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
831 u16 Value; 830 u16 Value;
832 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A,&Value,0); 831 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
833 Value &= FE_AG_REG_GC1_AGC_DAT__M; 832 Value &= FE_AG_REG_GC1_AGC_DAT__M;
834 if(status>=0) { 833 if (status >= 0) {
835 /* 3.3V 834 /* 3.3V
836 | 835 |
837 R1 836 R1
838 | 837 |
839 Vin - R3 - * -- Vout 838 Vin - R3 - * -- Vout
840 | 839 |
841 R2 840 R2
842 | 841 |
843 GND 842 GND
844 */ 843 */
845 u32 R1 = state->if_agc_cfg.R1; 844 u32 R1 = state->if_agc_cfg.R1;
846 u32 R2 = state->if_agc_cfg.R2; 845 u32 R2 = state->if_agc_cfg.R2;
847 u32 R3 = state->if_agc_cfg.R3; 846 u32 R3 = state->if_agc_cfg.R3;
848 847
849 u32 Vmax = (3300 * R2) / ( R1 + R2 ); 848 u32 Vmax = (3300 * R2) / (R1 + R2);
850 u32 Rpar = ( R2 * R3 ) / ( R3 + R2 ); 849 u32 Rpar = (R2 * R3) / (R3 + R2);
851 u32 Vmin = (3300 * Rpar ) / ( R1 + Rpar ); 850 u32 Vmin = (3300 * Rpar) / (R1 + Rpar);
852 u32 Vout = Vmin + (( Vmax - Vmin ) * Value) / 1024; 851 u32 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
853 852
854 *pValue = Vout; 853 *pValue = Vout;
855 } 854 }
@@ -878,7 +877,7 @@ static int load_firmware(struct drxd_state *state, const char *fw_name)
878} 877}
879 878
880static int DownloadMicrocode(struct drxd_state *state, 879static int DownloadMicrocode(struct drxd_state *state,
881 const u8 *pMCImage, u32 Length) 880 const u8 * pMCImage, u32 Length)
882{ 881{
883 u8 *pSrc; 882 u8 *pSrc;
884 u16 Flags; 883 u16 Flags;
@@ -886,32 +885,38 @@ static int DownloadMicrocode(struct drxd_state *state,
886 u16 nBlocks; 885 u16 nBlocks;
887 u16 BlockSize; 886 u16 BlockSize;
888 u16 BlockCRC; 887 u16 BlockCRC;
889 u32 offset=0; 888 u32 offset = 0;
890 int i, status=0; 889 int i, status = 0;
891 890
892 pSrc=(u8 *) pMCImage; 891 pSrc = (u8 *) pMCImage;
893 Flags = (pSrc[0] << 8) | pSrc[1]; 892 Flags = (pSrc[0] << 8) | pSrc[1];
894 pSrc += sizeof(u16); offset += sizeof(u16); 893 pSrc += sizeof(u16);
894 offset += sizeof(u16);
895 nBlocks = (pSrc[0] << 8) | pSrc[1]; 895 nBlocks = (pSrc[0] << 8) | pSrc[1];
896 pSrc += sizeof(u16); offset += sizeof(u16); 896 pSrc += sizeof(u16);
897 offset += sizeof(u16);
897 898
898 for(i=0; i<nBlocks; i++ ) { 899 for (i = 0; i < nBlocks; i++) {
899 Address=(pSrc[0] << 24) | (pSrc[1] << 16) | 900 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
900 (pSrc[2] << 8) | pSrc[3]; 901 (pSrc[2] << 8) | pSrc[3];
901 pSrc += sizeof(u32); offset += sizeof(u32); 902 pSrc += sizeof(u32);
903 offset += sizeof(u32);
902 904
903 BlockSize = ( (pSrc[0] << 8) | pSrc[1] ) * sizeof(u16); 905 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
904 pSrc += sizeof(u16); offset += sizeof(u16); 906 pSrc += sizeof(u16);
907 offset += sizeof(u16);
905 908
906 Flags = (pSrc[0] << 8) | pSrc[1]; 909 Flags = (pSrc[0] << 8) | pSrc[1];
907 pSrc += sizeof(u16); offset += sizeof(u16); 910 pSrc += sizeof(u16);
911 offset += sizeof(u16);
908 912
909 BlockCRC = (pSrc[0] << 8) | pSrc[1]; 913 BlockCRC = (pSrc[0] << 8) | pSrc[1];
910 pSrc += sizeof(u16); offset += sizeof(u16); 914 pSrc += sizeof(u16);
915 offset += sizeof(u16);
911 916
912 status = WriteBlock(state,Address,BlockSize, 917 status = WriteBlock(state, Address, BlockSize,
913 pSrc,DRX_I2C_CLEARCRC); 918 pSrc, DRX_I2C_CLEARCRC);
914 if (status<0) 919 if (status < 0)
915 break; 920 break;
916 pSrc += BlockSize; 921 pSrc += BlockSize;
917 offset += BlockSize; 922 offset += BlockSize;
@@ -920,51 +925,48 @@ static int DownloadMicrocode(struct drxd_state *state,
920 return status; 925 return status;
921} 926}
922 927
923static int HI_Command(struct drxd_state *state, u16 cmd, u16 *pResult) 928static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
924{ 929{
925 u32 nrRetries = 0; 930 u32 nrRetries = 0;
926 u16 waitCmd; 931 u16 waitCmd;
927 int status; 932 int status;
928 933
929 if ((status=Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0))<0) 934 if ((status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0)) < 0)
930 return status; 935 return status;
931 936
932 do { 937 do {
933 nrRetries+=1; 938 nrRetries += 1;
934 if (nrRetries>DRXD_MAX_RETRIES) { 939 if (nrRetries > DRXD_MAX_RETRIES) {
935 status=-1; 940 status = -1;
936 break; 941 break;
937 }; 942 };
938 status=Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); 943 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
939 } while (waitCmd!=0); 944 } while (waitCmd != 0);
940 945
941 if (status>=0) 946 if (status >= 0)
942 status=Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); 947 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
943 return status; 948 return status;
944} 949}
945 950
946static int HI_CfgCommand(struct drxd_state *state) 951static int HI_CfgCommand(struct drxd_state *state)
947{ 952{
948 int status=0; 953 int status = 0;
949 954
950 down(&state->mutex); 955 down(&state->mutex);
951 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, 956 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
952 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
953 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); 957 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
954 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, 958 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
955 state->hi_cfg_bridge_delay, 0);
956 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); 959 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
957 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); 960 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
958 961
959 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, 962 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
960 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
961 963
962 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)== 964 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
963 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) 965 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
964 status=Write16(state, HI_RA_RAM_SRV_CMD__A, 966 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
965 HI_RA_RAM_SRV_CMD_CONFIG, 0); 967 HI_RA_RAM_SRV_CMD_CONFIG, 0);
966 else 968 else
967 status=HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); 969 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
968 up(&state->mutex); 970 up(&state->mutex);
969 return status; 971 return status;
970} 972}
@@ -974,7 +976,7 @@ static int InitHI(struct drxd_state *state)
974 state->hi_cfg_wakeup_key = (state->chip_adr); 976 state->hi_cfg_wakeup_key = (state->chip_adr);
975 /* port/bridge/power down ctrl */ 977 /* port/bridge/power down ctrl */
976 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; 978 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
977 return HI_CfgCommand(state); 979 return HI_CfgCommand(state);
978} 980}
979 981
980static int HI_ResetCommand(struct drxd_state *state) 982static int HI_ResetCommand(struct drxd_state *state)
@@ -982,20 +984,19 @@ static int HI_ResetCommand(struct drxd_state *state)
982 int status; 984 int status;
983 985
984 down(&state->mutex); 986 down(&state->mutex);
985 status=Write16(state, HI_RA_RAM_SRV_RST_KEY__A, 987 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
986 HI_RA_RAM_SRV_RST_KEY_ACT, 0); 988 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
987 if (status==0) 989 if (status == 0)
988 status=HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); 990 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
989 up(&state->mutex); 991 up(&state->mutex);
990 msleep(1); 992 msleep(1);
991 return status; 993 return status;
992} 994}
993 995
994static int DRX_ConfigureI2CBridge(struct drxd_state *state, 996static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
995 int bEnableBridge)
996{ 997{
997 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); 998 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
998 if ( bEnableBridge ) 999 if (bEnableBridge)
999 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; 1000 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1000 else 1001 else
1001 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; 1002 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
@@ -1010,13 +1011,13 @@ static int DRX_ConfigureI2CBridge(struct drxd_state *state,
1010 1011
1011#if 0 1012#if 0
1012static int AtomicReadBlock(struct drxd_state *state, 1013static int AtomicReadBlock(struct drxd_state *state,
1013 u32 Addr, u16 DataSize, u8 *pData, u8 Flags) 1014 u32 Addr, u16 DataSize, u8 * pData, u8 Flags)
1014{ 1015{
1015 int status; 1016 int status;
1016 int i=0; 1017 int i = 0;
1017 1018
1018 /* Parameter check */ 1019 /* Parameter check */
1019 if ( (!pData) || ( (DataSize & 1)!=0 ) ) 1020 if ((!pData) || ((DataSize & 1) != 0))
1020 return -1; 1021 return -1;
1021 1022
1022 down(&state->mutex); 1023 down(&state->mutex);
@@ -1024,31 +1025,31 @@ static int AtomicReadBlock(struct drxd_state *state,
1024 do { 1025 do {
1025 /* Instruct HI to read n bytes */ 1026 /* Instruct HI to read n bytes */
1026 /* TODO use proper names forthese egisters */ 1027 /* TODO use proper names forthese egisters */
1027 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_KEY__A, 1028 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_KEY__A,
1028 (HI_TR_FUNC_ADDR & 0xFFFF), 0)); 1029 (HI_TR_FUNC_ADDR & 0xFFFF), 0));
1029 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_DIV__A, 1030 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_DIV__A,
1030 (u16)(Addr >> 16), 0)); 1031 (u16) (Addr >> 16), 0));
1031 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_BDL__A, 1032 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_BDL__A,
1032 (u16)(Addr & 0xFFFF), 0)); 1033 (u16) (Addr & 0xFFFF), 0));
1033 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_WUP__A, 1034 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_WUP__A,
1034 (u16)((DataSize/2) - 1), 0)); 1035 (u16) ((DataSize / 2) - 1), 0));
1035 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_ACT__A, 1036 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_ACT__A,
1036 HI_TR_READ, 0)); 1037 HI_TR_READ, 0));
1037 1038
1038 CHK_ERROR( HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE,0)); 1039 CHK_ERROR(HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0));
1039 1040
1040 } while(0); 1041 } while (0);
1041 1042
1042 if (status>=0) { 1043 if (status >= 0) {
1043 for (i = 0; i < (DataSize/2); i += 1) { 1044 for (i = 0; i < (DataSize / 2); i += 1) {
1044 u16 word; 1045 u16 word;
1045 1046
1046 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), 1047 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1047 &word, 0); 1048 &word, 0);
1048 if( status<0) 1049 if (status < 0)
1049 break; 1050 break;
1050 pData[2*i] = (u8) (word & 0xFF); 1051 pData[2 * i] = (u8) (word & 0xFF);
1051 pData[(2*i) + 1] = (u8) (word >> 8 ); 1052 pData[(2 * i) + 1] = (u8) (word >> 8);
1052 } 1053 }
1053 } 1054 }
1054 up(&state->mutex); 1055 up(&state->mutex);
@@ -1056,18 +1057,17 @@ static int AtomicReadBlock(struct drxd_state *state,
1056} 1057}
1057 1058
1058static int AtomicReadReg32(struct drxd_state *state, 1059static int AtomicReadReg32(struct drxd_state *state,
1059 u32 Addr, u32 *pData, u8 Flags) 1060 u32 Addr, u32 * pData, u8 Flags)
1060{ 1061{
1061 u8 buf[sizeof (u32)]; 1062 u8 buf[sizeof(u32)];
1062 int status; 1063 int status;
1063 1064
1064 if (!pData) 1065 if (!pData)
1065 return -1; 1066 return -1;
1066 status=AtomicReadBlock(state, Addr, sizeof (u32), buf, Flags); 1067 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1067 *pData = (((u32) buf[0]) << 0) + 1068 *pData = (((u32) buf[0]) << 0) +
1068 (((u32) buf[1]) << 8) + 1069 (((u32) buf[1]) << 8) +
1069 (((u32) buf[2]) << 16) + 1070 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1070 (((u32) buf[3]) << 24);
1071 return status; 1071 return status;
1072} 1072}
1073#endif 1073#endif
@@ -1095,7 +1095,7 @@ static int InitCC(struct drxd_state *state)
1095{ 1095{
1096 if (state->osc_clock_freq == 0 || 1096 if (state->osc_clock_freq == 0 ||
1097 state->osc_clock_freq > 20000 || 1097 state->osc_clock_freq > 20000 ||
1098 (state->osc_clock_freq % 4000 ) != 0 ) { 1098 (state->osc_clock_freq % 4000) != 0) {
1099 printk("invalid osc frequency %d\n", state->osc_clock_freq); 1099 printk("invalid osc frequency %d\n", state->osc_clock_freq);
1100 return -1; 1100 return -1;
1101 } 1101 }
@@ -1103,7 +1103,7 @@ static int InitCC(struct drxd_state *state)
1103 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); 1103 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1104 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | 1104 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1105 CC_REG_PLL_MODE_PUMP_CUR_12, 0); 1105 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1106 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq/4000, 0); 1106 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1107 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); 1107 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1108 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); 1108 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1109 1109
@@ -1114,19 +1114,18 @@ static int ResetECOD(struct drxd_state *state)
1114{ 1114{
1115 int status = 0; 1115 int status = 0;
1116 1116
1117 if(state->type_A ) 1117 if (state->type_A)
1118 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); 1118 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1119 else 1119 else
1120 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); 1120 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1121 1121
1122 if (!(status<0)) 1122 if (!(status < 0))
1123 status = WriteTable(state, state->m_ResetECRAM); 1123 status = WriteTable(state, state->m_ResetECRAM);
1124 if (!(status<0)) 1124 if (!(status < 0))
1125 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); 1125 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1126 return status; 1126 return status;
1127} 1127}
1128 1128
1129
1130/* Configure PGA switch */ 1129/* Configure PGA switch */
1131 1130
1132static int SetCfgPga(struct drxd_state *state, int pgaSwitch) 1131static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
@@ -1135,28 +1134,28 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1135 u16 AgModeLop = 0; 1134 u16 AgModeLop = 0;
1136 u16 AgModeHip = 0; 1135 u16 AgModeHip = 0;
1137 do { 1136 do {
1138 if ( pgaSwitch ) { 1137 if (pgaSwitch) {
1139 /* PGA on */ 1138 /* PGA on */
1140 /* fine gain */ 1139 /* fine gain */
1141 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1140 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1142 &AgModeLop, 0x0000)); 1141 &AgModeLop, 0x0000));
1143 AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1142 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1144 AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; 1143 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1145 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1144 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1146 AgModeLop, 0x0000)); 1145 AgModeLop, 0x0000));
1147 1146
1148 /* coarse gain */ 1147 /* coarse gain */
1149 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1148 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1150 &AgModeHip, 0x0000)); 1149 &AgModeHip, 0x0000));
1151 AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1150 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1152 AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC ; 1151 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1153 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1152 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1154 AgModeHip, 0x0000)); 1153 AgModeHip, 0x0000));
1155 1154
1156 /* enable fine and coarse gain, enable AAF, 1155 /* enable fine and coarse gain, enable AAF,
1157 no ext resistor */ 1156 no ext resistor */
1158 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1157 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1159 B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 1158 B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN,
1160 0x0000)); 1159 0x0000));
1161 } else { 1160 } else {
1162 /* PGA off, bypass */ 1161 /* PGA off, bypass */
@@ -1164,71 +1163,73 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1164 /* fine gain */ 1163 /* fine gain */
1165 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1164 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1166 &AgModeLop, 0x0000)); 1165 &AgModeLop, 0x0000));
1167 AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1166 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1168 AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC ; 1167 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1169 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1168 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1170 AgModeLop, 0x0000)); 1169 AgModeLop, 0x0000));
1171 1170
1172 /* coarse gain */ 1171 /* coarse gain */
1173 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1172 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1174 &AgModeHip, 0x0000)); 1173 &AgModeHip, 0x0000));
1175 AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1174 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1176 AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC ; 1175 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1177 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1176 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1178 AgModeHip, 0x0000)); 1177 AgModeHip, 0x0000));
1179 1178
1180 /* disable fine and coarse gain, enable AAF, 1179 /* disable fine and coarse gain, enable AAF,
1181 no ext resistor */ 1180 no ext resistor */
1182 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1181 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1183 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1182 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1184 0x0000)); 1183 0x0000));
1185 } 1184 }
1186 } 1185 }
1187 while(0); 1186 while (0);
1188 return status; 1187 return status;
1189} 1188}
1190 1189
1191static int InitFE(struct drxd_state *state) 1190static int InitFE(struct drxd_state *state)
1192{ 1191{
1193 int status; 1192 int status;
1194
1195 do
1196 {
1197 CHK_ERROR( WriteTable(state, state->m_InitFE_1));
1198 1193
1199 if( state->type_A ) { 1194 do {
1200 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, 1195 CHK_ERROR(WriteTable(state, state->m_InitFE_1));
1201 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0);
1202 } else {
1203 if (state->PGA)
1204 status = SetCfgPga(state, 0);
1205 else
1206 status =
1207 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1208 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0);
1209 }
1210 1196
1211 if (status<0) break; 1197 if (state->type_A) {
1212 CHK_ERROR( Write16( state, FE_AG_REG_AG_AGC_SIO__A, 1198 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1213 state->m_FeAgRegAgAgcSio, 0x0000)); 1199 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1214 CHK_ERROR( Write16( state, FE_AG_REG_AG_PWD__A,state->m_FeAgRegAgPwd, 1200 0);
1215 0x0000)); 1201 } else {
1202 if (state->PGA)
1203 status = SetCfgPga(state, 0);
1204 else
1205 status =
1206 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1207 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1208 0);
1209 }
1216 1210
1217 CHK_ERROR( WriteTable(state, state->m_InitFE_2)); 1211 if (status < 0)
1212 break;
1213 CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A,
1214 state->m_FeAgRegAgAgcSio, 0x0000));
1215 CHK_ERROR(Write16
1216 (state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd,
1217 0x0000));
1218 1218
1219 CHK_ERROR(WriteTable(state, state->m_InitFE_2));
1219 1220
1220 } while(0); 1221 } while (0);
1221 1222
1222 return status; 1223 return status;
1223} 1224}
1224 1225
1225static int InitFT(struct drxd_state *state) 1226static int InitFT(struct drxd_state *state)
1226{ 1227{
1227 /* 1228 /*
1228 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk 1229 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1229 SC stuff 1230 SC stuff
1230 */ 1231 */
1231 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000 ); 1232 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1232} 1233}
1233 1234
1234static int SC_WaitForReady(struct drxd_state *state) 1235static int SC_WaitForReady(struct drxd_state *state)
@@ -1236,10 +1237,9 @@ static int SC_WaitForReady(struct drxd_state *state)
1236 u16 curCmd; 1237 u16 curCmd;
1237 int i; 1238 int i;
1238 1239
1239 for(i = 0; i < DRXD_MAX_RETRIES; i += 1 ) 1240 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1240 { 1241 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1241 int status = Read16(state, SC_RA_RAM_CMD__A,&curCmd,0); 1242 if (status == 0 || curCmd == 0)
1242 if (status==0 || curCmd == 0 )
1243 return status; 1243 return status;
1244 } 1244 }
1245 return -1; 1245 return -1;
@@ -1247,79 +1247,75 @@ static int SC_WaitForReady(struct drxd_state *state)
1247 1247
1248static int SC_SendCommand(struct drxd_state *state, u16 cmd) 1248static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1249{ 1249{
1250 int status=0; 1250 int status = 0;
1251 u16 errCode; 1251 u16 errCode;
1252 1252
1253 Write16(state, SC_RA_RAM_CMD__A,cmd,0); 1253 Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1254 SC_WaitForReady(state); 1254 SC_WaitForReady(state);
1255 1255
1256 Read16(state, SC_RA_RAM_CMD_ADDR__A,&errCode,0); 1256 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1257 1257
1258 if( errCode == 0xFFFF ) 1258 if (errCode == 0xFFFF) {
1259 { 1259 printk("Command Error\n");
1260 printk("Command Error\n"); 1260 status = -1;
1261 status = -1;
1262 } 1261 }
1263 1262
1264 return status; 1263 return status;
1265} 1264}
1266 1265
1267static int SC_ProcStartCommand(struct drxd_state *state, 1266static int SC_ProcStartCommand(struct drxd_state *state,
1268 u16 subCmd,u16 param0,u16 param1) 1267 u16 subCmd, u16 param0, u16 param1)
1269{ 1268{
1270 int status=0; 1269 int status = 0;
1271 u16 scExec; 1270 u16 scExec;
1272 1271
1273 down(&state->mutex); 1272 down(&state->mutex);
1274 do { 1273 do {
1275 Read16(state, SC_COMM_EXEC__A, &scExec, 0); 1274 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1276 if (scExec != 1) { 1275 if (scExec != 1) {
1277 status=-1; 1276 status = -1;
1278 break; 1277 break;
1279 } 1278 }
1280 SC_WaitForReady(state); 1279 SC_WaitForReady(state);
1281 Write16(state, SC_RA_RAM_CMD_ADDR__A,subCmd,0); 1280 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1282 Write16(state, SC_RA_RAM_PARAM1__A,param1,0); 1281 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1283 Write16(state, SC_RA_RAM_PARAM0__A,param0,0); 1282 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1284 1283
1285 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); 1284 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1286 } while(0); 1285 } while (0);
1287 up(&state->mutex); 1286 up(&state->mutex);
1288 return status; 1287 return status;
1289} 1288}
1290 1289
1291
1292static int SC_SetPrefParamCommand(struct drxd_state *state, 1290static int SC_SetPrefParamCommand(struct drxd_state *state,
1293 u16 subCmd,u16 param0,u16 param1) 1291 u16 subCmd, u16 param0, u16 param1)
1294{ 1292{
1295 int status; 1293 int status;
1296 1294
1297 down(&state->mutex); 1295 down(&state->mutex);
1298 do { 1296 do {
1299 CHK_ERROR( SC_WaitForReady(state) ); 1297 CHK_ERROR(SC_WaitForReady(state));
1300 CHK_ERROR( Write16(state,SC_RA_RAM_CMD_ADDR__A,subCmd,0) ); 1298 CHK_ERROR(Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0));
1301 CHK_ERROR( Write16(state,SC_RA_RAM_PARAM1__A,param1,0) ); 1299 CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0));
1302 CHK_ERROR( Write16(state,SC_RA_RAM_PARAM0__A,param0,0) ); 1300 CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0));
1303 1301
1304 CHK_ERROR( SC_SendCommand(state, 1302 CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM));
1305 SC_RA_RAM_CMD_SET_PREF_PARAM) ); 1303 } while (0);
1306 } while(0);
1307 up(&state->mutex); 1304 up(&state->mutex);
1308 return status; 1305 return status;
1309} 1306}
1310 1307
1311#if 0 1308#if 0
1312static int SC_GetOpParamCommand(struct drxd_state *state, u16 *result) 1309static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1313{ 1310{
1314 int status=0; 1311 int status = 0;
1315 1312
1316 down(&state->mutex); 1313 down(&state->mutex);
1317 do { 1314 do {
1318 CHK_ERROR( SC_WaitForReady(state) ); 1315 CHK_ERROR(SC_WaitForReady(state));
1319 CHK_ERROR( SC_SendCommand(state, 1316 CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM));
1320 SC_RA_RAM_CMD_GET_OP_PARAM) ); 1317 CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0));
1321 CHK_ERROR( Read16(state, SC_RA_RAM_PARAM0__A,result, 0 ) ); 1318 } while (0);
1322 } while(0);
1323 up(&state->mutex); 1319 up(&state->mutex);
1324 return status; 1320 return status;
1325} 1321}
@@ -1333,45 +1329,38 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1333 u16 EcOcRegIprInvMpg = 0; 1329 u16 EcOcRegIprInvMpg = 0;
1334 u16 EcOcRegOcModeLop = 0; 1330 u16 EcOcRegOcModeLop = 0;
1335 u16 EcOcRegOcModeHip = 0; 1331 u16 EcOcRegOcModeHip = 0;
1336 u16 EcOcRegOcMpgSio = 0; 1332 u16 EcOcRegOcMpgSio = 0;
1337 1333
1338 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, 1334 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A,
1339 &EcOcRegOcModeLop, 0));*/ 1335 &EcOcRegOcModeLop, 0)); */
1340 1336
1341 if( state->operation_mode == OM_DVBT_Diversity_Front ) 1337 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1342 { 1338 if (bEnableOutput) {
1343 if ( bEnableOutput )
1344 {
1345 EcOcRegOcModeHip |= 1339 EcOcRegOcModeHip |=
1346 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; 1340 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1347 } 1341 } else
1348 else
1349 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1342 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1350 EcOcRegOcModeLop |= 1343 EcOcRegOcModeLop |=
1351 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1344 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1352 } 1345 } else {
1353 else
1354 {
1355 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; 1346 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1356 1347
1357 if (bEnableOutput) 1348 if (bEnableOutput)
1358 EcOcRegOcMpgSio &= 1349 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1359 (~(EC_OC_REG_OC_MPG_SIO__M));
1360 else 1350 else
1361 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; 1351 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1362 1352
1363 /* Don't Insert RS Byte */ 1353 /* Don't Insert RS Byte */
1364 if( state->insert_rs_byte ) 1354 if (state->insert_rs_byte) {
1365 {
1366 EcOcRegOcModeLop &= 1355 EcOcRegOcModeLop &=
1367 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); 1356 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1368 EcOcRegOcModeHip &= 1357 EcOcRegOcModeHip &=
1369 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1358 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1370 EcOcRegOcModeHip |= 1359 EcOcRegOcModeHip |=
1371 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE; 1360 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1372 } else { 1361 } else {
1373 EcOcRegOcModeLop |= 1362 EcOcRegOcModeLop |=
1374 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; 1363 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1375 EcOcRegOcModeHip &= 1364 EcOcRegOcModeHip &=
1376 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); 1365 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1377 EcOcRegOcModeHip |= 1366 EcOcRegOcModeHip |=
@@ -1379,7 +1368,7 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1379 } 1368 }
1380 1369
1381 /* Mode = Parallel */ 1370 /* Mode = Parallel */
1382 if( state->enable_parallel ) 1371 if (state->enable_parallel)
1383 EcOcRegOcModeLop &= 1372 EcOcRegOcModeLop &=
1384 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M)); 1373 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1385 else 1374 else
@@ -1407,114 +1396,114 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1407 EcOcRegIprInvMpg &= (~(0x0800)); 1396 EcOcRegIprInvMpg &= (~(0x0800));
1408 1397
1409 /* EcOcRegOcModeLop =0x05; */ 1398 /* EcOcRegOcModeLop =0x05; */
1410 CHK_ERROR( Write16(state, EC_OC_REG_IPR_INV_MPG__A, 1399 CHK_ERROR(Write16(state, EC_OC_REG_IPR_INV_MPG__A,
1411 EcOcRegIprInvMpg, 0)); 1400 EcOcRegIprInvMpg, 0));
1412 CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_LOP__A, 1401 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
1413 EcOcRegOcModeLop, 0) ); 1402 EcOcRegOcModeLop, 0));
1414 CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_HIP__A, 1403 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_HIP__A,
1415 EcOcRegOcModeHip, 0x0000 ) ); 1404 EcOcRegOcModeHip, 0x0000));
1416 CHK_ERROR( Write16(state, EC_OC_REG_OC_MPG_SIO__A, 1405 CHK_ERROR(Write16(state, EC_OC_REG_OC_MPG_SIO__A,
1417 EcOcRegOcMpgSio, 0) ); 1406 EcOcRegOcMpgSio, 0));
1418 } while(0); 1407 } while (0);
1419 return status; 1408 return status;
1420} 1409}
1421 1410
1422static int SetDeviceTypeId(struct drxd_state *state) 1411static int SetDeviceTypeId(struct drxd_state *state)
1423{ 1412{
1424 int status = 0; 1413 int status = 0;
1425 u16 deviceId = 0 ; 1414 u16 deviceId = 0;
1426 1415
1427 do { 1416 do {
1428 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); 1417 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0));
1429 /* TODO: why twice? */ 1418 /* TODO: why twice? */
1430 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); 1419 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0));
1431 printk( "drxd: deviceId = %04x\n",deviceId); 1420 printk("drxd: deviceId = %04x\n", deviceId);
1432 1421
1433 state->type_A = 0; 1422 state->type_A = 0;
1434 state->PGA = 0; 1423 state->PGA = 0;
1435 state->diversity = 0; 1424 state->diversity = 0;
1436 if (deviceId == 0) { /* on A2 only 3975 available */ 1425 if (deviceId == 0) { /* on A2 only 3975 available */
1437 state->type_A = 1; 1426 state->type_A = 1;
1438 printk("DRX3975D-A2\n"); 1427 printk("DRX3975D-A2\n");
1439 } else { 1428 } else {
1440 deviceId >>= 12; 1429 deviceId >>= 12;
1441 printk("DRX397%dD-B1\n",deviceId); 1430 printk("DRX397%dD-B1\n", deviceId);
1442 switch(deviceId) { 1431 switch (deviceId) {
1443 case 4: 1432 case 4:
1444 state->diversity = 1; 1433 state->diversity = 1;
1445 case 3: 1434 case 3:
1446 case 7: 1435 case 7:
1447 state->PGA = 1; 1436 state->PGA = 1;
1448 break; 1437 break;
1449 case 6: 1438 case 6:
1450 state->diversity = 1; 1439 state->diversity = 1;
1451 case 5: 1440 case 5:
1452 case 8: 1441 case 8:
1453 break; 1442 break;
1454 default: 1443 default:
1455 status = -1; 1444 status = -1;
1456 break; 1445 break;
1457 } 1446 }
1458 } 1447 }
1459 } while(0); 1448 } while (0);
1460 1449
1461 if (status<0) 1450 if (status < 0)
1462 return status; 1451 return status;
1463 1452
1464 /* Init Table selection */ 1453 /* Init Table selection */
1465 state->m_InitAtomicRead = DRXD_InitAtomicRead; 1454 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1466 state->m_InitSC = DRXD_InitSC; 1455 state->m_InitSC = DRXD_InitSC;
1467 state->m_ResetECRAM = DRXD_ResetECRAM; 1456 state->m_ResetECRAM = DRXD_ResetECRAM;
1468 if (state->type_A) { 1457 if (state->type_A) {
1469 state->m_ResetCEFR = DRXD_ResetCEFR; 1458 state->m_ResetCEFR = DRXD_ResetCEFR;
1470 state->m_InitFE_1 = DRXD_InitFEA2_1; 1459 state->m_InitFE_1 = DRXD_InitFEA2_1;
1471 state->m_InitFE_2 = DRXD_InitFEA2_2; 1460 state->m_InitFE_2 = DRXD_InitFEA2_2;
1472 state->m_InitCP = DRXD_InitCPA2; 1461 state->m_InitCP = DRXD_InitCPA2;
1473 state->m_InitCE = DRXD_InitCEA2; 1462 state->m_InitCE = DRXD_InitCEA2;
1474 state->m_InitEQ = DRXD_InitEQA2; 1463 state->m_InitEQ = DRXD_InitEQA2;
1475 state->m_InitEC = DRXD_InitECA2; 1464 state->m_InitEC = DRXD_InitECA2;
1476 if (load_firmware(state, DRX_FW_FILENAME_A2)) 1465 if (load_firmware(state, DRX_FW_FILENAME_A2))
1477 return -EIO; 1466 return -EIO;
1478 } else { 1467 } else {
1479 state->m_ResetCEFR = NULL; 1468 state->m_ResetCEFR = NULL;
1480 state->m_InitFE_1 = DRXD_InitFEB1_1; 1469 state->m_InitFE_1 = DRXD_InitFEB1_1;
1481 state->m_InitFE_2 = DRXD_InitFEB1_2; 1470 state->m_InitFE_2 = DRXD_InitFEB1_2;
1482 state->m_InitCP = DRXD_InitCPB1; 1471 state->m_InitCP = DRXD_InitCPB1;
1483 state->m_InitCE = DRXD_InitCEB1; 1472 state->m_InitCE = DRXD_InitCEB1;
1484 state->m_InitEQ = DRXD_InitEQB1; 1473 state->m_InitEQ = DRXD_InitEQB1;
1485 state->m_InitEC = DRXD_InitECB1; 1474 state->m_InitEC = DRXD_InitECB1;
1486 if (load_firmware(state, DRX_FW_FILENAME_B1)) 1475 if (load_firmware(state, DRX_FW_FILENAME_B1))
1487 return -EIO; 1476 return -EIO;
1488 } 1477 }
1489 if (state->diversity) { 1478 if (state->diversity) {
1490 state->m_InitDiversityFront = DRXD_InitDiversityFront; 1479 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1491 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; 1480 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1492 state->m_DisableDiversity = DRXD_DisableDiversity; 1481 state->m_DisableDiversity = DRXD_DisableDiversity;
1493 state->m_StartDiversityFront = DRXD_StartDiversityFront; 1482 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1494 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; 1483 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1495 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; 1484 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1496 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; 1485 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1497 } else { 1486 } else {
1498 state->m_InitDiversityFront = NULL; 1487 state->m_InitDiversityFront = NULL;
1499 state->m_InitDiversityEnd = NULL; 1488 state->m_InitDiversityEnd = NULL;
1500 state->m_DisableDiversity = NULL; 1489 state->m_DisableDiversity = NULL;
1501 state->m_StartDiversityFront = NULL; 1490 state->m_StartDiversityFront = NULL;
1502 state->m_StartDiversityEnd = NULL; 1491 state->m_StartDiversityEnd = NULL;
1503 state->m_DiversityDelay8MHZ = NULL; 1492 state->m_DiversityDelay8MHZ = NULL;
1504 state->m_DiversityDelay6MHZ = NULL; 1493 state->m_DiversityDelay6MHZ = NULL;
1505 } 1494 }
1506 1495
1507 return status; 1496 return status;
1508} 1497}
1509 1498
1510static int CorrectSysClockDeviation(struct drxd_state *state) 1499static int CorrectSysClockDeviation(struct drxd_state *state)
1511{ 1500{
1512 int status; 1501 int status;
1513 s32 incr = 0; 1502 s32 incr = 0;
1514 s32 nomincr = 0; 1503 s32 nomincr = 0;
1515 u32 bandwidth=0; 1504 u32 bandwidth = 0;
1516 u32 sysClockInHz=0; 1505 u32 sysClockInHz = 0;
1517 u32 sysClockFreq=0; /* in kHz */ 1506 u32 sysClockFreq = 0; /* in kHz */
1518 s16 oscClockDeviation; 1507 s16 oscClockDeviation;
1519 s16 Diff; 1508 s16 Diff;
1520 1509
@@ -1523,79 +1512,75 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
1523 1512
1524 /* These accesses should be AtomicReadReg32, but that 1513 /* These accesses should be AtomicReadReg32, but that
1525 causes trouble (at least for diversity */ 1514 causes trouble (at least for diversity */
1526 CHK_ERROR( Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, 1515 CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A,
1527 ((u32 *)&nomincr),0 )); 1516 ((u32 *) & nomincr), 0));
1528 CHK_ERROR( Read32(state, FE_IF_REG_INCR0__A, 1517 CHK_ERROR(Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0));
1529 (u32 *) &incr,0 )); 1518
1530 1519 if (state->type_A) {
1531 if( state->type_A ) { 1520 if ((nomincr - incr < -500) || (nomincr - incr > 500))
1532 if( (nomincr - incr < -500) ||
1533 (nomincr - incr > 500 ) )
1534 break; 1521 break;
1535 } else { 1522 } else {
1536 if( (nomincr - incr < -2000 ) || 1523 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1537 (nomincr - incr > 2000 ) )
1538 break; 1524 break;
1539 } 1525 }
1540 1526
1541 switch( state->param.u.ofdm.bandwidth ) 1527 switch (state->param.u.ofdm.bandwidth) {
1542 { 1528 case BANDWIDTH_8_MHZ:
1543 case BANDWIDTH_8_MHZ :
1544 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; 1529 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1545 break; 1530 break;
1546 case BANDWIDTH_7_MHZ : 1531 case BANDWIDTH_7_MHZ:
1547 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 1532 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1548 break; 1533 break;
1549 case BANDWIDTH_6_MHZ : 1534 case BANDWIDTH_6_MHZ:
1550 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 1535 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1551 break; 1536 break;
1552 default : 1537 default:
1553 return -1; 1538 return -1;
1554 break; 1539 break;
1555 } 1540 }
1556 1541
1557 /* Compute new sysclock value 1542 /* Compute new sysclock value
1558 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */ 1543 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1559 incr += (1<<23); 1544 incr += (1 << 23);
1560 sysClockInHz = MulDiv32(incr,bandwidth,1<<21); 1545 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1561 sysClockFreq= (u32)(sysClockInHz/1000); 1546 sysClockFreq = (u32) (sysClockInHz / 1000);
1562 /* rounding */ 1547 /* rounding */
1563 if ( ( sysClockInHz%1000 ) > 500 ) 1548 if ((sysClockInHz % 1000) > 500) {
1564 {
1565 sysClockFreq++; 1549 sysClockFreq++;
1566 } 1550 }
1567 1551
1568 /* Compute clock deviation in ppm */ 1552 /* Compute clock deviation in ppm */
1569 oscClockDeviation = (u16) ( 1553 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1570 (((s32)(sysClockFreq) - 1554 (s32)
1571 (s32)(state->expected_sys_clock_freq))* 1555 (state->expected_sys_clock_freq)) *
1572 1000000L)/(s32)(state->expected_sys_clock_freq) ); 1556 1000000L) /
1557 (s32)
1558 (state->expected_sys_clock_freq));
1573 1559
1574 Diff = oscClockDeviation - state->osc_clock_deviation; 1560 Diff = oscClockDeviation - state->osc_clock_deviation;
1575 /*printk("sysclockdiff=%d\n", Diff);*/ 1561 /*printk("sysclockdiff=%d\n", Diff); */
1576 if( Diff >= -200 && Diff <= 200 ) { 1562 if (Diff >= -200 && Diff <= 200) {
1577 state->sys_clock_freq = (u16) sysClockFreq; 1563 state->sys_clock_freq = (u16) sysClockFreq;
1578 if( oscClockDeviation != 1564 if (oscClockDeviation != state->osc_clock_deviation) {
1579 state->osc_clock_deviation ) {
1580 if (state->config.osc_deviation) { 1565 if (state->config.osc_deviation) {
1581 state->config.osc_deviation( 1566 state->config.osc_deviation(state->priv,
1582 state->priv, 1567 oscClockDeviation,
1583 oscClockDeviation, 1); 1568 1);
1584 state->osc_clock_deviation= 1569 state->osc_clock_deviation =
1585 oscClockDeviation; 1570 oscClockDeviation;
1586 } 1571 }
1587 } 1572 }
1588 /* switch OFF SRMM scan in SC */ 1573 /* switch OFF SRMM scan in SC */
1589 CHK_ERROR( Write16( state, 1574 CHK_ERROR(Write16(state,
1590 SC_RA_RAM_SAMPLE_RATE_COUNT__A, 1575 SC_RA_RAM_SAMPLE_RATE_COUNT__A,
1591 DRXD_OSCDEV_DONT_SCAN,0)); 1576 DRXD_OSCDEV_DONT_SCAN, 0));
1592 /* overrule FE_IF internal value for 1577 /* overrule FE_IF internal value for
1593 proper re-locking */ 1578 proper re-locking */
1594 CHK_ERROR( Write16( state, SC_RA_RAM_IF_SAVE__AX, 1579 CHK_ERROR(Write16(state, SC_RA_RAM_IF_SAVE__AX,
1595 state->current_fe_if_incr, 0)); 1580 state->current_fe_if_incr, 0));
1596 state->cscd_state = CSCD_SAVED; 1581 state->cscd_state = CSCD_SAVED;
1597 } 1582 }
1598 } while(0); 1583 } while (0);
1599 1584
1600 return (status); 1585 return (status);
1601} 1586}
@@ -1604,60 +1589,58 @@ static int DRX_Stop(struct drxd_state *state)
1604{ 1589{
1605 int status; 1590 int status;
1606 1591
1607 if( state->drxd_state != DRXD_STARTED ) 1592 if (state->drxd_state != DRXD_STARTED)
1608 return 0; 1593 return 0;
1609 1594
1610 do { 1595 do {
1611 if (state->cscd_state != CSCD_SAVED ) { 1596 if (state->cscd_state != CSCD_SAVED) {
1612 u32 lock; 1597 u32 lock;
1613 CHK_ERROR( DRX_GetLockStatus(state, &lock)); 1598 CHK_ERROR(DRX_GetLockStatus(state, &lock));
1614 } 1599 }
1615 1600
1616 CHK_ERROR(StopOC(state)); 1601 CHK_ERROR(StopOC(state));
1617 1602
1618 state->drxd_state = DRXD_STOPPED; 1603 state->drxd_state = DRXD_STOPPED;
1619 1604
1620 CHK_ERROR( ConfigureMPEGOutput(state, 0) ); 1605 CHK_ERROR(ConfigureMPEGOutput(state, 0));
1621 1606
1622 if(state->type_A ) { 1607 if (state->type_A) {
1623 /* Stop relevant processors off the device */ 1608 /* Stop relevant processors off the device */
1624 CHK_ERROR( Write16(state, EC_OD_REG_COMM_EXEC__A, 1609 CHK_ERROR(Write16(state, EC_OD_REG_COMM_EXEC__A,
1625 0x0000, 0x0000)); 1610 0x0000, 0x0000));
1626 1611
1627 CHK_ERROR( Write16(state, SC_COMM_EXEC__A, 1612 CHK_ERROR(Write16(state, SC_COMM_EXEC__A,
1628 SC_COMM_EXEC_CTL_STOP, 0 )); 1613 SC_COMM_EXEC_CTL_STOP, 0));
1629 CHK_ERROR( Write16(state, LC_COMM_EXEC__A, 1614 CHK_ERROR(Write16(state, LC_COMM_EXEC__A,
1630 SC_COMM_EXEC_CTL_STOP, 0 )); 1615 SC_COMM_EXEC_CTL_STOP, 0));
1631 } else { 1616 } else {
1632 /* Stop all processors except HI & CC & FE */ 1617 /* Stop all processors except HI & CC & FE */
1633 CHK_ERROR(Write16(state, 1618 CHK_ERROR(Write16(state,
1634 B_SC_COMM_EXEC__A, 1619 B_SC_COMM_EXEC__A,
1635 SC_COMM_EXEC_CTL_STOP, 0 )); 1620 SC_COMM_EXEC_CTL_STOP, 0));
1636 CHK_ERROR(Write16(state, 1621 CHK_ERROR(Write16(state,
1637 B_LC_COMM_EXEC__A, 1622 B_LC_COMM_EXEC__A,
1638 SC_COMM_EXEC_CTL_STOP, 0 )); 1623 SC_COMM_EXEC_CTL_STOP, 0));
1639 CHK_ERROR(Write16(state, 1624 CHK_ERROR(Write16(state,
1640 B_FT_COMM_EXEC__A, 1625 B_FT_COMM_EXEC__A,
1641 SC_COMM_EXEC_CTL_STOP, 0 )); 1626 SC_COMM_EXEC_CTL_STOP, 0));
1642 CHK_ERROR(Write16(state, 1627 CHK_ERROR(Write16(state,
1643 B_CP_COMM_EXEC__A, 1628 B_CP_COMM_EXEC__A,
1644 SC_COMM_EXEC_CTL_STOP, 0 )); 1629 SC_COMM_EXEC_CTL_STOP, 0));
1645 CHK_ERROR(Write16(state, 1630 CHK_ERROR(Write16(state,
1646 B_CE_COMM_EXEC__A, 1631 B_CE_COMM_EXEC__A,
1647 SC_COMM_EXEC_CTL_STOP, 0 )); 1632 SC_COMM_EXEC_CTL_STOP, 0));
1648 CHK_ERROR(Write16(state, 1633 CHK_ERROR(Write16(state,
1649 B_EQ_COMM_EXEC__A, 1634 B_EQ_COMM_EXEC__A,
1650 SC_COMM_EXEC_CTL_STOP, 0 )); 1635 SC_COMM_EXEC_CTL_STOP, 0));
1651 CHK_ERROR(Write16(state, 1636 CHK_ERROR(Write16(state,
1652 EC_OD_REG_COMM_EXEC__A, 1637 EC_OD_REG_COMM_EXEC__A, 0x0000, 0));
1653 0x0000, 0 ));
1654 } 1638 }
1655 1639
1656 } while(0); 1640 } while (0);
1657 return status; 1641 return status;
1658} 1642}
1659 1643
1660
1661int SetOperationMode(struct drxd_state *state, int oMode) 1644int SetOperationMode(struct drxd_state *state, int oMode)
1662{ 1645{
1663 int status; 1646 int status;
@@ -1678,15 +1661,12 @@ int SetOperationMode(struct drxd_state *state, int oMode)
1678 break; 1661 break;
1679 } 1662 }
1680 1663
1681 switch(oMode) 1664 switch (oMode) {
1682 {
1683 case OM_DVBT_Diversity_Front: 1665 case OM_DVBT_Diversity_Front:
1684 status = WriteTable(state, 1666 status = WriteTable(state, state->m_InitDiversityFront);
1685 state->m_InitDiversityFront);
1686 break; 1667 break;
1687 case OM_DVBT_Diversity_End: 1668 case OM_DVBT_Diversity_End:
1688 status = WriteTable(state, 1669 status = WriteTable(state, state->m_InitDiversityEnd);
1689 state->m_InitDiversityEnd);
1690 break; 1670 break;
1691 case OM_Default: 1671 case OM_Default:
1692 /* We need to check how to 1672 /* We need to check how to
@@ -1695,58 +1675,52 @@ int SetOperationMode(struct drxd_state *state, int oMode)
1695 status = WriteTable(state, state->m_DisableDiversity); 1675 status = WriteTable(state, state->m_DisableDiversity);
1696 break; 1676 break;
1697 } 1677 }
1698 } while(0); 1678 } while (0);
1699 1679
1700 if (!status) 1680 if (!status)
1701 state->operation_mode = oMode; 1681 state->operation_mode = oMode;
1702 return status; 1682 return status;
1703} 1683}
1704 1684
1705
1706
1707static int StartDiversity(struct drxd_state *state) 1685static int StartDiversity(struct drxd_state *state)
1708{ 1686{
1709 int status=0; 1687 int status = 0;
1710 u16 rcControl; 1688 u16 rcControl;
1711 1689
1712 do { 1690 do {
1713 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1691 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1714 CHK_ERROR(WriteTable(state, 1692 CHK_ERROR(WriteTable(state,
1715 state->m_StartDiversityFront)); 1693 state->m_StartDiversityFront));
1716 } else if( state->operation_mode == OM_DVBT_Diversity_End ) { 1694 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1717 CHK_ERROR(WriteTable(state, 1695 CHK_ERROR(WriteTable(state,
1718 state->m_StartDiversityEnd)); 1696 state->m_StartDiversityEnd));
1719 if( state->param.u.ofdm.bandwidth == 1697 if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1720 BANDWIDTH_8_MHZ ) { 1698 CHK_ERROR(WriteTable(state,
1721 CHK_ERROR( 1699 state->
1722 WriteTable(state, 1700 m_DiversityDelay8MHZ));
1723 state->
1724 m_DiversityDelay8MHZ));
1725 } else { 1701 } else {
1726 CHK_ERROR( 1702 CHK_ERROR(WriteTable(state,
1727 WriteTable(state, 1703 state->
1728 state-> 1704 m_DiversityDelay6MHZ));
1729 m_DiversityDelay6MHZ));
1730 } 1705 }
1731 1706
1732 CHK_ERROR(Read16(state, 1707 CHK_ERROR(Read16(state,
1733 B_EQ_REG_RC_SEL_CAR__A, 1708 B_EQ_REG_RC_SEL_CAR__A,
1734 &rcControl,0)); 1709 &rcControl, 0));
1735 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); 1710 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1736 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | 1711 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1737 /* combining enabled */ 1712 /* combining enabled */
1738 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 1713 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1739 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | 1714 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1740 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; 1715 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1741 CHK_ERROR(Write16(state, 1716 CHK_ERROR(Write16(state,
1742 B_EQ_REG_RC_SEL_CAR__A, 1717 B_EQ_REG_RC_SEL_CAR__A,
1743 rcControl,0)); 1718 rcControl, 0));
1744 } 1719 }
1745 } while(0); 1720 } while (0);
1746 return status; 1721 return status;
1747} 1722}
1748 1723
1749
1750static int SetFrequencyShift(struct drxd_state *state, 1724static int SetFrequencyShift(struct drxd_state *state,
1751 u32 offsetFreq, int channelMirrored) 1725 u32 offsetFreq, int channelMirrored)
1752{ 1726{
@@ -1763,60 +1737,55 @@ static int SetFrequencyShift(struct drxd_state *state,
1763 */ 1737 */
1764 1738
1765 /* Compute register value, unsigned computation */ 1739 /* Compute register value, unsigned computation */
1766 state->fe_fs_add_incr = MulDiv32( state->intermediate_freq + 1740 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1767 offsetFreq, 1741 offsetFreq,
1768 1<<28, state->sys_clock_freq); 1742 1 << 28, state->sys_clock_freq);
1769 /* Remove integer part */ 1743 /* Remove integer part */
1770 state->fe_fs_add_incr &= 0x0FFFFFFFL; 1744 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1771 if (negativeShift) 1745 if (negativeShift) {
1772 { 1746 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1773 state->fe_fs_add_incr = ((1<<28) - state->fe_fs_add_incr);
1774 } 1747 }
1775 1748
1776 /* Save the frequency shift without tunerOffset compensation 1749 /* Save the frequency shift without tunerOffset compensation
1777 for CtrlGetChannel. */ 1750 for CtrlGetChannel. */
1778 state->org_fe_fs_add_incr = MulDiv32( state->intermediate_freq, 1751 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1779 1<<28, state->sys_clock_freq); 1752 1 << 28, state->sys_clock_freq);
1780 /* Remove integer part */ 1753 /* Remove integer part */
1781 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; 1754 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1782 if (negativeShift) 1755 if (negativeShift)
1783 state->org_fe_fs_add_incr = ((1L<<28) - 1756 state->org_fe_fs_add_incr = ((1L << 28) -
1784 state->org_fe_fs_add_incr); 1757 state->org_fe_fs_add_incr);
1785 1758
1786 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, 1759 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1787 state->fe_fs_add_incr, 0); 1760 state->fe_fs_add_incr, 0);
1788} 1761}
1789 1762
1790static int SetCfgNoiseCalibration (struct drxd_state *state, 1763static int SetCfgNoiseCalibration(struct drxd_state *state,
1791 struct SNoiseCal* noiseCal ) 1764 struct SNoiseCal *noiseCal)
1792{ 1765{
1793 u16 beOptEna; 1766 u16 beOptEna;
1794 int status=0; 1767 int status = 0;
1795 1768
1796 do { 1769 do {
1797 CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, 1770 CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0));
1798 &beOptEna, 0)); 1771 if (noiseCal->cpOpt) {
1799 if (noiseCal->cpOpt)
1800 {
1801 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1772 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1802 } else { 1773 } else {
1803 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1774 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1804 CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A, 1775 CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A,
1805 noiseCal->cpNexpOfs, 0)); 1776 noiseCal->cpNexpOfs, 0));
1806 } 1777 }
1807 CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, 1778 CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0));
1808 beOptEna, 0));
1809 1779
1810 if( !state->type_A ) 1780 if (!state->type_A) {
1811 { 1781 CHK_ERROR(Write16(state,
1812 CHK_ERROR(Write16( state, 1782 B_SC_RA_RAM_CO_TD_CAL_2K__A,
1813 B_SC_RA_RAM_CO_TD_CAL_2K__A, 1783 noiseCal->tdCal2k, 0));
1814 noiseCal->tdCal2k,0)); 1784 CHK_ERROR(Write16(state,
1815 CHK_ERROR(Write16( state, 1785 B_SC_RA_RAM_CO_TD_CAL_8K__A,
1816 B_SC_RA_RAM_CO_TD_CAL_8K__A, 1786 noiseCal->tdCal8k, 0));
1817 noiseCal->tdCal8k,0));
1818 } 1787 }
1819 } while(0); 1788 } while (0);
1820 1789
1821 return status; 1790 return status;
1822} 1791}
@@ -1826,84 +1795,83 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1826 struct dvb_ofdm_parameters *p = &state->param.u.ofdm; 1795 struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1827 int status; 1796 int status;
1828 1797
1829 u16 transmissionParams = 0; 1798 u16 transmissionParams = 0;
1830 u16 operationMode = 0; 1799 u16 operationMode = 0;
1831 u16 qpskTdTpsPwr = 0; 1800 u16 qpskTdTpsPwr = 0;
1832 u16 qam16TdTpsPwr = 0; 1801 u16 qam16TdTpsPwr = 0;
1833 u16 qam64TdTpsPwr = 0; 1802 u16 qam64TdTpsPwr = 0;
1834 u32 feIfIncr = 0; 1803 u32 feIfIncr = 0;
1835 u32 bandwidth = 0; 1804 u32 bandwidth = 0;
1836 int mirrorFreqSpect; 1805 int mirrorFreqSpect;
1837 1806
1838 u16 qpskSnCeGain = 0; 1807 u16 qpskSnCeGain = 0;
1839 u16 qam16SnCeGain = 0; 1808 u16 qam16SnCeGain = 0;
1840 u16 qam64SnCeGain = 0; 1809 u16 qam64SnCeGain = 0;
1841 u16 qpskIsGainMan = 0; 1810 u16 qpskIsGainMan = 0;
1842 u16 qam16IsGainMan = 0; 1811 u16 qam16IsGainMan = 0;
1843 u16 qam64IsGainMan = 0; 1812 u16 qam64IsGainMan = 0;
1844 u16 qpskIsGainExp = 0; 1813 u16 qpskIsGainExp = 0;
1845 u16 qam16IsGainExp = 0; 1814 u16 qam16IsGainExp = 0;
1846 u16 qam64IsGainExp = 0; 1815 u16 qam64IsGainExp = 0;
1847 u16 bandwidthParam = 0; 1816 u16 bandwidthParam = 0;
1848 1817
1849 if (off<0) 1818 if (off < 0)
1850 off=(off-500)/1000; 1819 off = (off - 500) / 1000;
1851 else 1820 else
1852 off=(off+500)/1000; 1821 off = (off + 500) / 1000;
1853 1822
1854 do { 1823 do {
1855 if (state->drxd_state != DRXD_STOPPED) 1824 if (state->drxd_state != DRXD_STOPPED)
1856 return -1; 1825 return -1;
1857 CHK_ERROR( ResetECOD(state) ); 1826 CHK_ERROR(ResetECOD(state));
1858 if (state->type_A) { 1827 if (state->type_A) {
1859 CHK_ERROR( InitSC(state) ); 1828 CHK_ERROR(InitSC(state));
1860 } else { 1829 } else {
1861 CHK_ERROR( InitFT(state) ); 1830 CHK_ERROR(InitFT(state));
1862 CHK_ERROR( InitCP(state) ); 1831 CHK_ERROR(InitCP(state));
1863 CHK_ERROR( InitCE(state) ); 1832 CHK_ERROR(InitCE(state));
1864 CHK_ERROR( InitEQ(state) ); 1833 CHK_ERROR(InitEQ(state));
1865 CHK_ERROR( InitSC(state) ); 1834 CHK_ERROR(InitSC(state));
1866 } 1835 }
1867 1836
1868 /* Restore current IF & RF AGC settings */ 1837 /* Restore current IF & RF AGC settings */
1869 1838
1870 CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg )); 1839 CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg));
1871 CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg )); 1840 CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg));
1872 1841
1873 mirrorFreqSpect=( state->param.inversion==INVERSION_ON); 1842 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1874 1843
1875 switch (p->transmission_mode) { 1844 switch (p->transmission_mode) {
1876 default: /* Not set, detect it automatically */ 1845 default: /* Not set, detect it automatically */
1877 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M; 1846 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1878 /* fall through , try first guess DRX_FFTMODE_8K */ 1847 /* fall through , try first guess DRX_FFTMODE_8K */
1879 case TRANSMISSION_MODE_8K : 1848 case TRANSMISSION_MODE_8K:
1880 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; 1849 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1881 if (state->type_A) { 1850 if (state->type_A) {
1882 CHK_ERROR( Write16(state, 1851 CHK_ERROR(Write16(state,
1883 EC_SB_REG_TR_MODE__A, 1852 EC_SB_REG_TR_MODE__A,
1884 EC_SB_REG_TR_MODE_8K, 1853 EC_SB_REG_TR_MODE_8K,
1885 0x0000 )); 1854 0x0000));
1886 qpskSnCeGain = 99; 1855 qpskSnCeGain = 99;
1887 qam16SnCeGain = 83; 1856 qam16SnCeGain = 83;
1888 qam64SnCeGain = 67; 1857 qam64SnCeGain = 67;
1889 } 1858 }
1890 break; 1859 break;
1891 case TRANSMISSION_MODE_2K : 1860 case TRANSMISSION_MODE_2K:
1892 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; 1861 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1893 if (state->type_A) { 1862 if (state->type_A) {
1894 CHK_ERROR( Write16(state, 1863 CHK_ERROR(Write16(state,
1895 EC_SB_REG_TR_MODE__A, 1864 EC_SB_REG_TR_MODE__A,
1896 EC_SB_REG_TR_MODE_2K, 1865 EC_SB_REG_TR_MODE_2K,
1897 0x0000 )); 1866 0x0000));
1898 qpskSnCeGain = 97; 1867 qpskSnCeGain = 97;
1899 qam16SnCeGain = 71; 1868 qam16SnCeGain = 71;
1900 qam64SnCeGain = 65; 1869 qam64SnCeGain = 65;
1901 } 1870 }
1902 break; 1871 break;
1903 } 1872 }
1904 1873
1905 switch( p->guard_interval ) 1874 switch (p->guard_interval) {
1906 {
1907 case GUARD_INTERVAL_1_4: 1875 case GUARD_INTERVAL_1_4:
1908 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 1876 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1909 break; 1877 break;
@@ -1916,95 +1884,94 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1916 case GUARD_INTERVAL_1_32: 1884 case GUARD_INTERVAL_1_32:
1917 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32; 1885 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
1918 break; 1886 break;
1919 default: /* Not set, detect it automatically */ 1887 default: /* Not set, detect it automatically */
1920 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M; 1888 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
1921 /* try first guess 1/4 */ 1889 /* try first guess 1/4 */
1922 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; 1890 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1923 break; 1891 break;
1924 } 1892 }
1925 1893
1926 switch( p->hierarchy_information ) 1894 switch (p->hierarchy_information) {
1927 {
1928 case HIERARCHY_1: 1895 case HIERARCHY_1:
1929 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; 1896 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
1930 if (state->type_A) { 1897 if (state->type_A) {
1931 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, 1898 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A,
1932 0x0001, 0x0000 ) ); 1899 0x0001, 0x0000));
1933 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, 1900 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A,
1934 0x0001, 0x0000 ) ); 1901 0x0001, 0x0000));
1935 1902
1936 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 1903 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1937 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; 1904 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
1938 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1; 1905 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
1939 1906
1940 qpskIsGainMan = 1907 qpskIsGainMan =
1941 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 1908 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
1942 qam16IsGainMan = 1909 qam16IsGainMan =
1943 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 1910 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
1944 qam64IsGainMan = 1911 qam64IsGainMan =
1945 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 1912 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
1946 1913
1947 qpskIsGainExp = 1914 qpskIsGainExp =
1948 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 1915 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
1949 qam16IsGainExp = 1916 qam16IsGainExp =
1950 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 1917 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
1951 qam64IsGainExp = 1918 qam64IsGainExp =
1952 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 1919 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
1953 } 1920 }
1954 break; 1921 break;
1955 1922
1956 case HIERARCHY_2: 1923 case HIERARCHY_2:
1957 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; 1924 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
1958 if (state->type_A) { 1925 if (state->type_A) {
1959 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, 1926 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A,
1960 0x0002, 0x0000 ) ); 1927 0x0002, 0x0000));
1961 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, 1928 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A,
1962 0x0002, 0x0000 ) ); 1929 0x0002, 0x0000));
1963 1930
1964 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 1931 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1965 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; 1932 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
1966 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2; 1933 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
1967 1934
1968 qpskIsGainMan = 1935 qpskIsGainMan =
1969 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 1936 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
1970 qam16IsGainMan = 1937 qam16IsGainMan =
1971 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; 1938 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
1972 qam64IsGainMan = 1939 qam64IsGainMan =
1973 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; 1940 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
1974 1941
1975 qpskIsGainExp = 1942 qpskIsGainExp =
1976 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 1943 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
1977 qam16IsGainExp = 1944 qam16IsGainExp =
1978 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; 1945 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
1979 qam64IsGainExp = 1946 qam64IsGainExp =
1980 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; 1947 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
1981 } 1948 }
1982 break; 1949 break;
1983 case HIERARCHY_4: 1950 case HIERARCHY_4:
1984 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; 1951 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
1985 if (state->type_A) { 1952 if (state->type_A) {
1986 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, 1953 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A,
1987 0x0003, 0x0000 )); 1954 0x0003, 0x0000));
1988 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, 1955 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A,
1989 0x0003, 0x0000 ) ); 1956 0x0003, 0x0000));
1990 1957
1991 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 1958 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1992 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; 1959 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
1993 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4; 1960 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
1994 1961
1995 qpskIsGainMan = 1962 qpskIsGainMan =
1996 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; 1963 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
1997 qam16IsGainMan = 1964 qam16IsGainMan =
1998 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; 1965 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
1999 qam64IsGainMan = 1966 qam64IsGainMan =
2000 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; 1967 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2001 1968
2002 qpskIsGainExp = 1969 qpskIsGainExp =
2003 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; 1970 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2004 qam16IsGainExp = 1971 qam16IsGainExp =
2005 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; 1972 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2006 qam64IsGainExp = 1973 qam64IsGainExp =
2007 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; 1974 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2008 } 1975 }
2009 break; 1976 break;
2010 case HIERARCHY_AUTO: 1977 case HIERARCHY_AUTO:
@@ -2013,34 +1980,34 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2013 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; 1980 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2014 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; 1981 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2015 if (state->type_A) { 1982 if (state->type_A) {
2016 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, 1983 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A,
2017 0x0000, 0x0000 ) ); 1984 0x0000, 0x0000));
2018 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, 1985 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A,
2019 0x0000, 0x0000 ) ); 1986 0x0000, 0x0000));
2020 1987
2021 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; 1988 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2022 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; 1989 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2023 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN; 1990 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2024 1991
2025 qpskIsGainMan = 1992 qpskIsGainMan =
2026 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; 1993 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2027 qam16IsGainMan = 1994 qam16IsGainMan =
2028 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; 1995 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2029 qam64IsGainMan = 1996 qam64IsGainMan =
2030 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; 1997 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2031 1998
2032 qpskIsGainExp = 1999 qpskIsGainExp =
2033 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; 2000 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2034 qam16IsGainExp = 2001 qam16IsGainExp =
2035 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; 2002 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2036 qam64IsGainExp = 2003 qam64IsGainExp =
2037 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; 2004 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2038 } 2005 }
2039 break; 2006 break;
2040 } 2007 }
2041 CHK_ERROR( status ); 2008 CHK_ERROR(status);
2042 2009
2043 switch( p->constellation ) { 2010 switch (p->constellation) {
2044 default: 2011 default:
2045 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; 2012 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2046 /* fall through , try first guess 2013 /* fall through , try first guess
@@ -2049,60 +2016,60 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2049 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; 2016 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2050 if (state->type_A) { 2017 if (state->type_A) {
2051 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, 2018 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A,
2052 0x0002, 0x0000 ) ); 2019 0x0002, 0x0000));
2053 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, 2020 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A,
2054 EC_SB_REG_CONST_64QAM, 2021 EC_SB_REG_CONST_64QAM,
2055 0x0000) ); 2022 0x0000));
2056 CHK_ERROR(Write16(state, 2023 CHK_ERROR(Write16(state,
2057 EC_SB_REG_SCALE_MSB__A, 2024 EC_SB_REG_SCALE_MSB__A,
2058 0x0020, 0x0000 ) ); 2025 0x0020, 0x0000));
2059 CHK_ERROR(Write16(state, 2026 CHK_ERROR(Write16(state,
2060 EC_SB_REG_SCALE_BIT2__A, 2027 EC_SB_REG_SCALE_BIT2__A,
2061 0x0008, 0x0000 ) ); 2028 0x0008, 0x0000));
2062 CHK_ERROR(Write16(state, 2029 CHK_ERROR(Write16(state,
2063 EC_SB_REG_SCALE_LSB__A, 2030 EC_SB_REG_SCALE_LSB__A,
2064 0x0002, 0x0000 ) ); 2031 0x0002, 0x0000));
2065 2032
2066 CHK_ERROR(Write16(state, 2033 CHK_ERROR(Write16(state,
2067 EQ_REG_TD_TPS_PWR_OFS__A, 2034 EQ_REG_TD_TPS_PWR_OFS__A,
2068 qam64TdTpsPwr, 0x0000 ) ); 2035 qam64TdTpsPwr, 0x0000));
2069 CHK_ERROR( Write16(state,EQ_REG_SN_CEGAIN__A, 2036 CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A,
2070 qam64SnCeGain, 0x0000 )); 2037 qam64SnCeGain, 0x0000));
2071 CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_MAN__A, 2038 CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_MAN__A,
2072 qam64IsGainMan, 0x0000 )); 2039 qam64IsGainMan, 0x0000));
2073 CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_EXP__A, 2040 CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_EXP__A,
2074 qam64IsGainExp, 0x0000 )); 2041 qam64IsGainExp, 0x0000));
2075 } 2042 }
2076 break; 2043 break;
2077 case QPSK : 2044 case QPSK:
2078 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; 2045 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2079 if (state->type_A) { 2046 if (state->type_A) {
2080 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, 2047 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A,
2081 0x0000, 0x0000 ) ); 2048 0x0000, 0x0000));
2082 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, 2049 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A,
2083 EC_SB_REG_CONST_QPSK, 2050 EC_SB_REG_CONST_QPSK,
2084 0x0000) ); 2051 0x0000));
2085 CHK_ERROR(Write16(state, 2052 CHK_ERROR(Write16(state,
2086 EC_SB_REG_SCALE_MSB__A, 2053 EC_SB_REG_SCALE_MSB__A,
2087 0x0010, 0x0000 ) ); 2054 0x0010, 0x0000));
2088 CHK_ERROR(Write16(state, 2055 CHK_ERROR(Write16(state,
2089 EC_SB_REG_SCALE_BIT2__A, 2056 EC_SB_REG_SCALE_BIT2__A,
2090 0x0000, 0x0000 ) ); 2057 0x0000, 0x0000));
2091 CHK_ERROR(Write16(state, 2058 CHK_ERROR(Write16(state,
2092 EC_SB_REG_SCALE_LSB__A, 2059 EC_SB_REG_SCALE_LSB__A,
2093 0x0000, 0x0000 ) ); 2060 0x0000, 0x0000));
2094 2061
2095 CHK_ERROR(Write16(state, 2062 CHK_ERROR(Write16(state,
2096 EQ_REG_TD_TPS_PWR_OFS__A, 2063 EQ_REG_TD_TPS_PWR_OFS__A,
2097 qpskTdTpsPwr, 0x0000 ) ); 2064 qpskTdTpsPwr, 0x0000));
2098 CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A, 2065 CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A,
2099 qpskSnCeGain, 0x0000 )); 2066 qpskSnCeGain, 0x0000));
2100 CHK_ERROR( Write16(state, 2067 CHK_ERROR(Write16(state,
2101 EQ_REG_IS_GAIN_MAN__A, 2068 EQ_REG_IS_GAIN_MAN__A,
2102 qpskIsGainMan, 0x0000 )); 2069 qpskIsGainMan, 0x0000));
2103 CHK_ERROR( Write16(state, 2070 CHK_ERROR(Write16(state,
2104 EQ_REG_IS_GAIN_EXP__A, 2071 EQ_REG_IS_GAIN_EXP__A,
2105 qpskIsGainExp, 0x0000 )); 2072 qpskIsGainExp, 0x0000));
2106 } 2073 }
2107 break; 2074 break;
2108 2075
@@ -2110,104 +2077,103 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2110 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; 2077 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2111 if (state->type_A) { 2078 if (state->type_A) {
2112 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, 2079 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A,
2113 0x0001, 0x0000 ) ); 2080 0x0001, 0x0000));
2114 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, 2081 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A,
2115 EC_SB_REG_CONST_16QAM, 2082 EC_SB_REG_CONST_16QAM,
2116 0x0000) ); 2083 0x0000));
2117 CHK_ERROR(Write16(state, 2084 CHK_ERROR(Write16(state,
2118 EC_SB_REG_SCALE_MSB__A, 2085 EC_SB_REG_SCALE_MSB__A,
2119 0x0010, 0x0000 ) ); 2086 0x0010, 0x0000));
2120 CHK_ERROR(Write16(state, 2087 CHK_ERROR(Write16(state,
2121 EC_SB_REG_SCALE_BIT2__A, 2088 EC_SB_REG_SCALE_BIT2__A,
2122 0x0004, 0x0000 ) ); 2089 0x0004, 0x0000));
2123 CHK_ERROR(Write16(state, 2090 CHK_ERROR(Write16(state,
2124 EC_SB_REG_SCALE_LSB__A, 2091 EC_SB_REG_SCALE_LSB__A,
2125 0x0000, 0x0000 ) ); 2092 0x0000, 0x0000));
2126 2093
2127 CHK_ERROR(Write16(state, 2094 CHK_ERROR(Write16(state,
2128 EQ_REG_TD_TPS_PWR_OFS__A, 2095 EQ_REG_TD_TPS_PWR_OFS__A,
2129 qam16TdTpsPwr, 0x0000 ) ); 2096 qam16TdTpsPwr, 0x0000));
2130 CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A, 2097 CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A,
2131 qam16SnCeGain, 0x0000 )); 2098 qam16SnCeGain, 0x0000));
2132 CHK_ERROR( Write16(state, 2099 CHK_ERROR(Write16(state,
2133 EQ_REG_IS_GAIN_MAN__A, 2100 EQ_REG_IS_GAIN_MAN__A,
2134 qam16IsGainMan, 0x0000 )); 2101 qam16IsGainMan, 0x0000));
2135 CHK_ERROR( Write16(state, 2102 CHK_ERROR(Write16(state,
2136 EQ_REG_IS_GAIN_EXP__A, 2103 EQ_REG_IS_GAIN_EXP__A,
2137 qam16IsGainExp, 0x0000 )); 2104 qam16IsGainExp, 0x0000));
2138 } 2105 }
2139 break; 2106 break;
2140 2107
2141 } 2108 }
2142 CHK_ERROR( status ); 2109 CHK_ERROR(status);
2143 2110
2144 switch (DRX_CHANNEL_HIGH) { 2111 switch (DRX_CHANNEL_HIGH) {
2145 default: 2112 default:
2146 case DRX_CHANNEL_AUTO: 2113 case DRX_CHANNEL_AUTO:
2147 case DRX_CHANNEL_LOW: 2114 case DRX_CHANNEL_LOW:
2148 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; 2115 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2149 CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A, 2116 CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A,
2150 EC_SB_REG_PRIOR_LO, 0x0000 )); 2117 EC_SB_REG_PRIOR_LO, 0x0000));
2151 break; 2118 break;
2152 case DRX_CHANNEL_HIGH: 2119 case DRX_CHANNEL_HIGH:
2153 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; 2120 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2154 CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A, 2121 CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A,
2155 EC_SB_REG_PRIOR_HI, 0x0000 )); 2122 EC_SB_REG_PRIOR_HI, 0x0000));
2156 break; 2123 break;
2157 2124
2158 } 2125 }
2159 2126
2160 switch( p->code_rate_HP ) 2127 switch (p->code_rate_HP) {
2161 {
2162 case FEC_1_2: 2128 case FEC_1_2:
2163 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; 2129 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2164 if (state->type_A) { 2130 if (state->type_A) {
2165 CHK_ERROR( Write16(state, 2131 CHK_ERROR(Write16(state,
2166 EC_VD_REG_SET_CODERATE__A, 2132 EC_VD_REG_SET_CODERATE__A,
2167 EC_VD_REG_SET_CODERATE_C1_2, 2133 EC_VD_REG_SET_CODERATE_C1_2,
2168 0x0000 ) ); 2134 0x0000));
2169 } 2135 }
2170 break; 2136 break;
2171 default: 2137 default:
2172 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M; 2138 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2173 case FEC_2_3 : 2139 case FEC_2_3:
2174 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; 2140 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2175 if (state->type_A) { 2141 if (state->type_A) {
2176 CHK_ERROR( Write16(state, 2142 CHK_ERROR(Write16(state,
2177 EC_VD_REG_SET_CODERATE__A, 2143 EC_VD_REG_SET_CODERATE__A,
2178 EC_VD_REG_SET_CODERATE_C2_3, 2144 EC_VD_REG_SET_CODERATE_C2_3,
2179 0x0000 ) ); 2145 0x0000));
2180 } 2146 }
2181 break; 2147 break;
2182 case FEC_3_4 : 2148 case FEC_3_4:
2183 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; 2149 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2184 if (state->type_A) { 2150 if (state->type_A) {
2185 CHK_ERROR( Write16(state, 2151 CHK_ERROR(Write16(state,
2186 EC_VD_REG_SET_CODERATE__A, 2152 EC_VD_REG_SET_CODERATE__A,
2187 EC_VD_REG_SET_CODERATE_C3_4, 2153 EC_VD_REG_SET_CODERATE_C3_4,
2188 0x0000 ) ); 2154 0x0000));
2189 } 2155 }
2190 break; 2156 break;
2191 case FEC_5_6 : 2157 case FEC_5_6:
2192 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; 2158 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2193 if (state->type_A) { 2159 if (state->type_A) {
2194 CHK_ERROR( Write16(state, 2160 CHK_ERROR(Write16(state,
2195 EC_VD_REG_SET_CODERATE__A, 2161 EC_VD_REG_SET_CODERATE__A,
2196 EC_VD_REG_SET_CODERATE_C5_6, 2162 EC_VD_REG_SET_CODERATE_C5_6,
2197 0x0000 ) ); 2163 0x0000));
2198 } 2164 }
2199 break; 2165 break;
2200 case FEC_7_8 : 2166 case FEC_7_8:
2201 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; 2167 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2202 if (state->type_A) { 2168 if (state->type_A) {
2203 CHK_ERROR( Write16(state, 2169 CHK_ERROR(Write16(state,
2204 EC_VD_REG_SET_CODERATE__A, 2170 EC_VD_REG_SET_CODERATE__A,
2205 EC_VD_REG_SET_CODERATE_C7_8, 2171 EC_VD_REG_SET_CODERATE_C7_8,
2206 0x0000 ) ); 2172 0x0000));
2207 } 2173 }
2208 break; 2174 break;
2209 } 2175 }
2210 CHK_ERROR( status ); 2176 CHK_ERROR(status);
2211 2177
2212 /* First determine real bandwidth (Hz) */ 2178 /* First determine real bandwidth (Hz) */
2213 /* Also set delay for impulse noise cruncher (only A2) */ 2179 /* Also set delay for impulse noise cruncher (only A2) */
@@ -2216,8 +2182,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2216 by SC for fix for some 8K,1/8 guard but is restored by 2182 by SC for fix for some 8K,1/8 guard but is restored by
2217 InitEC and ResetEC 2183 InitEC and ResetEC
2218 functions */ 2184 functions */
2219 switch( p->bandwidth ) 2185 switch (p->bandwidth) {
2220 {
2221 case BANDWIDTH_AUTO: 2186 case BANDWIDTH_AUTO:
2222 case BANDWIDTH_8_MHZ: 2187 case BANDWIDTH_8_MHZ:
2223 /* (64/7)*(8/8)*1000000 */ 2188 /* (64/7)*(8/8)*1000000 */
@@ -2225,27 +2190,27 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2225 2190
2226 bandwidthParam = 0; 2191 bandwidthParam = 0;
2227 status = Write16(state, 2192 status = Write16(state,
2228 FE_AG_REG_IND_DEL__A , 50 , 0x0000 ); 2193 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2229 break; 2194 break;
2230 case BANDWIDTH_7_MHZ: 2195 case BANDWIDTH_7_MHZ:
2231 /* (64/7)*(7/8)*1000000 */ 2196 /* (64/7)*(7/8)*1000000 */
2232 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; 2197 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2233 bandwidthParam =0x4807; /*binary:0100 1000 0000 0111 */ 2198 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2234 status = Write16(state, 2199 status = Write16(state,
2235 FE_AG_REG_IND_DEL__A , 59 , 0x0000 ); 2200 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2236 break; 2201 break;
2237 case BANDWIDTH_6_MHZ: 2202 case BANDWIDTH_6_MHZ:
2238 /* (64/7)*(6/8)*1000000 */ 2203 /* (64/7)*(6/8)*1000000 */
2239 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; 2204 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2240 bandwidthParam =0x0F07; /*binary: 0000 1111 0000 0111*/ 2205 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2241 status = Write16(state, 2206 status = Write16(state,
2242 FE_AG_REG_IND_DEL__A , 71 , 0x0000 ); 2207 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2243 break; 2208 break;
2244 } 2209 }
2245 CHK_ERROR( status ); 2210 CHK_ERROR(status);
2246 2211
2247 CHK_ERROR( Write16(state, 2212 CHK_ERROR(Write16(state,
2248 SC_RA_RAM_BAND__A, bandwidthParam, 0x0000)); 2213 SC_RA_RAM_BAND__A, bandwidthParam, 0x0000));
2249 2214
2250 { 2215 {
2251 u16 sc_config; 2216 u16 sc_config;
@@ -2254,45 +2219,43 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2254 2219
2255 /* enable SLAVE mode in 2k 1/32 to 2220 /* enable SLAVE mode in 2k 1/32 to
2256 prevent timing change glitches */ 2221 prevent timing change glitches */
2257 if ( (p->transmission_mode==TRANSMISSION_MODE_2K) && 2222 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2258 (p->guard_interval==GUARD_INTERVAL_1_32) ) { 2223 (p->guard_interval == GUARD_INTERVAL_1_32)) {
2259 /* enable slave */ 2224 /* enable slave */
2260 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M; 2225 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2261 } else { 2226 } else {
2262 /* disable slave */ 2227 /* disable slave */
2263 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; 2228 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2264 } 2229 }
2265 CHK_ERROR( Write16(state, 2230 CHK_ERROR(Write16(state,
2266 SC_RA_RAM_CONFIG__A, sc_config,0 )); 2231 SC_RA_RAM_CONFIG__A, sc_config, 0));
2267 } 2232 }
2268 2233
2269 CHK_ERROR( SetCfgNoiseCalibration(state, &state->noise_cal)); 2234 CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal));
2270 2235
2271 if (state->cscd_state == CSCD_INIT ) 2236 if (state->cscd_state == CSCD_INIT) {
2272 {
2273 /* switch on SRMM scan in SC */ 2237 /* switch on SRMM scan in SC */
2274 CHK_ERROR( Write16(state, 2238 CHK_ERROR(Write16(state,
2275 SC_RA_RAM_SAMPLE_RATE_COUNT__A, 2239 SC_RA_RAM_SAMPLE_RATE_COUNT__A,
2276 DRXD_OSCDEV_DO_SCAN, 0x0000 )); 2240 DRXD_OSCDEV_DO_SCAN, 0x0000));
2277/* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A, 2241/* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A,
2278 DRXD_OSCDEV_STEP , 0x0000 ));*/ 2242 DRXD_OSCDEV_STEP , 0x0000 ));*/
2279 state->cscd_state = CSCD_SET; 2243 state->cscd_state = CSCD_SET;
2280 } 2244 }
2281 2245
2282
2283 /* Now compute FE_IF_REG_INCR */ 2246 /* Now compute FE_IF_REG_INCR */
2284 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => 2247 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2285 ((SysFreq / BandWidth) * (2^21) ) - (2^23)*/ 2248 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2286 feIfIncr = MulDiv32(state->sys_clock_freq*1000, 2249 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2287 ( 1ULL<< 21 ), bandwidth) - (1<<23) ; 2250 (1ULL << 21), bandwidth) - (1 << 23);
2288 CHK_ERROR( Write16(state, 2251 CHK_ERROR(Write16(state,
2289 FE_IF_REG_INCR0__A, 2252 FE_IF_REG_INCR0__A,
2290 (u16)(feIfIncr & FE_IF_REG_INCR0__M ), 2253 (u16) (feIfIncr & FE_IF_REG_INCR0__M),
2291 0x0000) ); 2254 0x0000));
2292 CHK_ERROR( Write16(state, 2255 CHK_ERROR(Write16(state,
2293 FE_IF_REG_INCR1__A, 2256 FE_IF_REG_INCR1__A,
2294 (u16)((feIfIncr >> FE_IF_REG_INCR0__W) & 2257 (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) &
2295 FE_IF_REG_INCR1__M ), 0x0000) ); 2258 FE_IF_REG_INCR1__M), 0x0000));
2296 /* Bandwidth setting done */ 2259 /* Bandwidth setting done */
2297 2260
2298 /* Mirror & frequency offset */ 2261 /* Mirror & frequency offset */
@@ -2301,34 +2264,34 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2301 /* Start SC, write channel settings to SC */ 2264 /* Start SC, write channel settings to SC */
2302 2265
2303 /* Enable SC after setting all other parameters */ 2266 /* Enable SC after setting all other parameters */
2304 CHK_ERROR( Write16(state, SC_COMM_STATE__A, 0, 0x0000)); 2267 CHK_ERROR(Write16(state, SC_COMM_STATE__A, 0, 0x0000));
2305 CHK_ERROR( Write16(state, SC_COMM_EXEC__A, 1, 0x0000)); 2268 CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 1, 0x0000));
2306 2269
2307 /* Write SC parameter registers, operation mode */ 2270 /* Write SC parameter registers, operation mode */
2308#if 1 2271#if 1
2309 operationMode =( SC_RA_RAM_OP_AUTO_MODE__M | 2272 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2310 SC_RA_RAM_OP_AUTO_GUARD__M | 2273 SC_RA_RAM_OP_AUTO_GUARD__M |
2311 SC_RA_RAM_OP_AUTO_CONST__M | 2274 SC_RA_RAM_OP_AUTO_CONST__M |
2312 SC_RA_RAM_OP_AUTO_HIER__M | 2275 SC_RA_RAM_OP_AUTO_HIER__M |
2313 SC_RA_RAM_OP_AUTO_RATE__M ); 2276 SC_RA_RAM_OP_AUTO_RATE__M);
2314#endif 2277#endif
2315 CHK_ERROR( SC_SetPrefParamCommand(state, 0x0000, 2278 CHK_ERROR(SC_SetPrefParamCommand(state, 0x0000,
2316 transmissionParams, 2279 transmissionParams,
2317 operationMode) ); 2280 operationMode));
2318 2281
2319 /* Start correct processes to get in lock */ 2282 /* Start correct processes to get in lock */
2320 CHK_ERROR( SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, 2283 CHK_ERROR(SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK,
2321 SC_RA_RAM_SW_EVENT_RUN_NMASK__M, 2284 SC_RA_RAM_SW_EVENT_RUN_NMASK__M,
2322 SC_RA_RAM_LOCKTRACK_MIN) ); 2285 SC_RA_RAM_LOCKTRACK_MIN));
2323 2286
2324 CHK_ERROR( StartOC(state) ); 2287 CHK_ERROR(StartOC(state));
2325 2288
2326 if( state->operation_mode != OM_Default ) { 2289 if (state->operation_mode != OM_Default) {
2327 CHK_ERROR(StartDiversity(state)); 2290 CHK_ERROR(StartDiversity(state));
2328 } 2291 }
2329 2292
2330 state->drxd_state = DRXD_STARTED; 2293 state->drxd_state = DRXD_STARTED;
2331 } while(0); 2294 } while (0);
2332 2295
2333 return status; 2296 return status;
2334} 2297}
@@ -2336,140 +2299,136 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2336static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) 2299static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2337{ 2300{
2338 u32 ulRfAgcOutputLevel = 0xffffffff; 2301 u32 ulRfAgcOutputLevel = 0xffffffff;
2339 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ 2302 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2340 u32 ulRfAgcMinLevel = 0; /* Currently unused */ 2303 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2341 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ 2304 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2342 u32 ulRfAgcSpeed = 0; /* Currently unused */ 2305 u32 ulRfAgcSpeed = 0; /* Currently unused */
2343 u32 ulRfAgcMode = 0;/*2; Off */ 2306 u32 ulRfAgcMode = 0; /*2; Off */
2344 u32 ulRfAgcR1 = 820; 2307 u32 ulRfAgcR1 = 820;
2345 u32 ulRfAgcR2 = 2200; 2308 u32 ulRfAgcR2 = 2200;
2346 u32 ulRfAgcR3 = 150; 2309 u32 ulRfAgcR3 = 150;
2347 u32 ulIfAgcMode = 0; /* Auto */ 2310 u32 ulIfAgcMode = 0; /* Auto */
2348 u32 ulIfAgcOutputLevel = 0xffffffff; 2311 u32 ulIfAgcOutputLevel = 0xffffffff;
2349 u32 ulIfAgcSettleLevel = 0xffffffff; 2312 u32 ulIfAgcSettleLevel = 0xffffffff;
2350 u32 ulIfAgcMinLevel = 0xffffffff; 2313 u32 ulIfAgcMinLevel = 0xffffffff;
2351 u32 ulIfAgcMaxLevel = 0xffffffff; 2314 u32 ulIfAgcMaxLevel = 0xffffffff;
2352 u32 ulIfAgcSpeed = 0xffffffff; 2315 u32 ulIfAgcSpeed = 0xffffffff;
2353 u32 ulIfAgcR1 = 820; 2316 u32 ulIfAgcR1 = 820;
2354 u32 ulIfAgcR2 = 2200; 2317 u32 ulIfAgcR2 = 2200;
2355 u32 ulIfAgcR3 = 150; 2318 u32 ulIfAgcR3 = 150;
2356 u32 ulClock = state->config.clock; 2319 u32 ulClock = state->config.clock;
2357 u32 ulSerialMode = 0; 2320 u32 ulSerialMode = 0;
2358 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ 2321 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2359 u32 ulHiI2cDelay = HI_I2C_DELAY; 2322 u32 ulHiI2cDelay = HI_I2C_DELAY;
2360 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY; 2323 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2361 u32 ulHiI2cPatch = 0; 2324 u32 ulHiI2cPatch = 0;
2362 u32 ulEnvironment = APPENV_PORTABLE; 2325 u32 ulEnvironment = APPENV_PORTABLE;
2363 u32 ulEnvironmentDiversity = APPENV_MOBILE; 2326 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2364 u32 ulIFFilter = IFFILTER_SAW; 2327 u32 ulIFFilter = IFFILTER_SAW;
2365 2328
2366 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2329 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2367 state->if_agc_cfg.outputLevel = 0; 2330 state->if_agc_cfg.outputLevel = 0;
2368 state->if_agc_cfg.settleLevel = 140; 2331 state->if_agc_cfg.settleLevel = 140;
2369 state->if_agc_cfg.minOutputLevel = 0; 2332 state->if_agc_cfg.minOutputLevel = 0;
2370 state->if_agc_cfg.maxOutputLevel = 1023; 2333 state->if_agc_cfg.maxOutputLevel = 1023;
2371 state->if_agc_cfg.speed = 904; 2334 state->if_agc_cfg.speed = 904;
2372 2335
2373 if( ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX ) 2336 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2374 { 2337 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2375 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; 2338 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2376 state->if_agc_cfg.outputLevel = (u16)(ulIfAgcOutputLevel);
2377 } 2339 }
2378 2340
2379 if( ulIfAgcMode == 0 && 2341 if (ulIfAgcMode == 0 &&
2380 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2342 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2381 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2343 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2382 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2344 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2383 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX 2345 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2384 ) 2346 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2385 { 2347 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2386 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2348 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2387 state->if_agc_cfg.settleLevel = (u16)(ulIfAgcSettleLevel); 2349 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2388 state->if_agc_cfg.minOutputLevel = (u16)(ulIfAgcMinLevel); 2350 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2389 state->if_agc_cfg.maxOutputLevel = (u16)(ulIfAgcMaxLevel);
2390 state->if_agc_cfg.speed = (u16)(ulIfAgcSpeed);
2391 } 2351 }
2392 2352
2393 state->if_agc_cfg.R1 = (u16)(ulIfAgcR1); 2353 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2394 state->if_agc_cfg.R2 = (u16)(ulIfAgcR2); 2354 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2395 state->if_agc_cfg.R3 = (u16)(ulIfAgcR3); 2355 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2396 2356
2397 state->rf_agc_cfg.R1 = (u16)(ulRfAgcR1); 2357 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2398 state->rf_agc_cfg.R2 = (u16)(ulRfAgcR2); 2358 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2399 state->rf_agc_cfg.R3 = (u16)(ulRfAgcR3); 2359 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2400 2360
2401 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2361 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2402 /* rest of the RFAgcCfg structure currently unused */ 2362 /* rest of the RFAgcCfg structure currently unused */
2403 if (ulRfAgcMode==1 && ulRfAgcOutputLevel<=DRXD_FE_CTRL_MAX) { 2363 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2404 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; 2364 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2405 state->rf_agc_cfg.outputLevel = (u16)(ulRfAgcOutputLevel); 2365 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2406 } 2366 }
2407 2367
2408 if( ulRfAgcMode == 0 && 2368 if (ulRfAgcMode == 0 &&
2409 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && 2369 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2410 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && 2370 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2411 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && 2371 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2412 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX 2372 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2413 ) 2373 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2414 { 2374 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2415 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; 2375 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2416 state->rf_agc_cfg.settleLevel = (u16)(ulRfAgcSettleLevel); 2376 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2417 state->rf_agc_cfg.minOutputLevel = (u16)(ulRfAgcMinLevel); 2377 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2418 state->rf_agc_cfg.maxOutputLevel = (u16)(ulRfAgcMaxLevel);
2419 state->rf_agc_cfg.speed = (u16)(ulRfAgcSpeed);
2420 } 2378 }
2421 2379
2422 if( ulRfAgcMode == 2 ) 2380 if (ulRfAgcMode == 2) {
2423 { 2381 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2424 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2425 } 2382 }
2426 2383
2427 if (ulEnvironment <= 2) 2384 if (ulEnvironment <= 2)
2428 state->app_env_default = (enum app_env) 2385 state->app_env_default = (enum app_env)
2429 (ulEnvironment); 2386 (ulEnvironment);
2430 if (ulEnvironmentDiversity <= 2) 2387 if (ulEnvironmentDiversity <= 2)
2431 state->app_env_diversity = (enum app_env) 2388 state->app_env_diversity = (enum app_env)
2432 (ulEnvironmentDiversity); 2389 (ulEnvironmentDiversity);
2433 2390
2434 if( ulIFFilter == IFFILTER_DISCRETE ) 2391 if (ulIFFilter == IFFILTER_DISCRETE) {
2435 {
2436 /* discrete filter */ 2392 /* discrete filter */
2437 state->noise_cal.cpOpt = 0; 2393 state->noise_cal.cpOpt = 0;
2438 state->noise_cal.cpNexpOfs = 40; 2394 state->noise_cal.cpNexpOfs = 40;
2439 state->noise_cal.tdCal2k = -40; 2395 state->noise_cal.tdCal2k = -40;
2440 state->noise_cal.tdCal8k = -24; 2396 state->noise_cal.tdCal8k = -24;
2441 } else { 2397 } else {
2442 /* SAW filter */ 2398 /* SAW filter */
2443 state->noise_cal.cpOpt = 1; 2399 state->noise_cal.cpOpt = 1;
2444 state->noise_cal.cpNexpOfs = 0; 2400 state->noise_cal.cpNexpOfs = 0;
2445 state->noise_cal.tdCal2k = -21; 2401 state->noise_cal.tdCal2k = -21;
2446 state->noise_cal.tdCal8k = -24; 2402 state->noise_cal.tdCal8k = -24;
2447 } 2403 }
2448 state->m_EcOcRegOcModeLop = (u16)(ulEcOcRegOcModeLop); 2404 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2449 2405
2450 state->chip_adr = (state->config.demod_address<<1)|1; 2406 state->chip_adr = (state->config.demod_address << 1) | 1;
2451 switch( ulHiI2cPatch ) 2407 switch (ulHiI2cPatch) {
2452 { 2408 case 1:
2453 case 1 : state->m_HiI2cPatch = DRXD_HiI2cPatch_1; break; 2409 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2454 case 3 : state->m_HiI2cPatch = DRXD_HiI2cPatch_3; break; 2410 break;
2411 case 3:
2412 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2413 break;
2455 default: 2414 default:
2456 state->m_HiI2cPatch = NULL; 2415 state->m_HiI2cPatch = NULL;
2457 } 2416 }
2458 2417
2459 /* modify tuner and clock attributes */ 2418 /* modify tuner and clock attributes */
2460 state->intermediate_freq = (u16)(IntermediateFrequency/1000); 2419 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2461 /* expected system clock frequency in kHz */ 2420 /* expected system clock frequency in kHz */
2462 state->expected_sys_clock_freq = 48000; 2421 state->expected_sys_clock_freq = 48000;
2463 /* real system clock frequency in kHz */ 2422 /* real system clock frequency in kHz */
2464 state->sys_clock_freq = 48000; 2423 state->sys_clock_freq = 48000;
2465 state->osc_clock_freq = (u16) ulClock; 2424 state->osc_clock_freq = (u16) ulClock;
2466 state->osc_clock_deviation = 0; 2425 state->osc_clock_deviation = 0;
2467 state->cscd_state = CSCD_INIT; 2426 state->cscd_state = CSCD_INIT;
2468 state->drxd_state = DRXD_UNINITIALIZED; 2427 state->drxd_state = DRXD_UNINITIALIZED;
2469 2428
2470 state->PGA=0; 2429 state->PGA = 0;
2471 state->type_A=0; 2430 state->type_A = 0;
2472 state->tuner_mirrors=0; 2431 state->tuner_mirrors = 0;
2473 2432
2474 /* modify MPEG output attributes */ 2433 /* modify MPEG output attributes */
2475 state->insert_rs_byte = state->config.insert_rs_byte; 2434 state->insert_rs_byte = state->config.insert_rs_byte;
@@ -2478,12 +2437,12 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2478 /* Timing div, 250ns/Psys */ 2437 /* Timing div, 250ns/Psys */
2479 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ 2438 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2480 2439
2481 state->hi_cfg_timing_div = (u16)((state->sys_clock_freq/1000)* 2440 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2482 ulHiI2cDelay)/1000 ; 2441 ulHiI2cDelay) / 1000;
2483 /* Bridge delay, uses oscilator clock */ 2442 /* Bridge delay, uses oscilator clock */
2484 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ 2443 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2485 state->hi_cfg_bridge_delay = (u16)((state->osc_clock_freq/1000) * 2444 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2486 ulHiI2cBridgeDelay)/1000 ; 2445 ulHiI2cBridgeDelay) / 1000;
2487 2446
2488 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2447 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2489 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ 2448 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
@@ -2491,9 +2450,9 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2491 return 0; 2450 return 0;
2492} 2451}
2493 2452
2494int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) 2453int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2495{ 2454{
2496 int status=0; 2455 int status = 0;
2497 u32 driverVersion; 2456 u32 driverVersion;
2498 2457
2499 if (state->init_done) 2458 if (state->init_done)
@@ -2504,10 +2463,10 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2504 do { 2463 do {
2505 state->operation_mode = OM_Default; 2464 state->operation_mode = OM_Default;
2506 2465
2507 CHK_ERROR( SetDeviceTypeId(state) ); 2466 CHK_ERROR(SetDeviceTypeId(state));
2508 2467
2509 /* Apply I2c address patch to B1 */ 2468 /* Apply I2c address patch to B1 */
2510 if( !state->type_A && state->m_HiI2cPatch != NULL ) 2469 if (!state->type_A && state->m_HiI2cPatch != NULL)
2511 CHK_ERROR(WriteTable(state, state->m_HiI2cPatch)); 2470 CHK_ERROR(WriteTable(state, state->m_HiI2cPatch));
2512 2471
2513 if (state->type_A) { 2472 if (state->type_A) {
@@ -2516,7 +2475,7 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2516 CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0)); 2475 CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0));
2517 } 2476 }
2518 2477
2519 CHK_ERROR( HI_ResetCommand(state)); 2478 CHK_ERROR(HI_ResetCommand(state));
2520 2479
2521 CHK_ERROR(StopAllProcessors(state)); 2480 CHK_ERROR(StopAllProcessors(state));
2522 CHK_ERROR(InitCC(state)); 2481 CHK_ERROR(InitCC(state));
@@ -2525,29 +2484,27 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2525 2484
2526 if (state->config.osc_deviation) 2485 if (state->config.osc_deviation)
2527 state->osc_clock_deviation = 2486 state->osc_clock_deviation =
2528 state->config.osc_deviation(state->priv, 2487 state->config.osc_deviation(state->priv, 0, 0);
2529 0, 0);
2530 { 2488 {
2531 /* Handle clock deviation */ 2489 /* Handle clock deviation */
2532 s32 devB; 2490 s32 devB;
2533 s32 devA = (s32)(state->osc_clock_deviation) * 2491 s32 devA = (s32) (state->osc_clock_deviation) *
2534 (s32)(state->expected_sys_clock_freq); 2492 (s32) (state->expected_sys_clock_freq);
2535 /* deviation in kHz */ 2493 /* deviation in kHz */
2536 s32 deviation = ( devA /(1000000L)); 2494 s32 deviation = (devA / (1000000L));
2537 /* rounding, signed */ 2495 /* rounding, signed */
2538 if ( devA > 0 ) 2496 if (devA > 0)
2539 devB=(2); 2497 devB = (2);
2540 else 2498 else
2541 devB=(-2); 2499 devB = (-2);
2542 if ( (devB*(devA%1000000L)>1000000L ) ) 2500 if ((devB * (devA % 1000000L) > 1000000L)) {
2543 {
2544 /* add +1 or -1 */ 2501 /* add +1 or -1 */
2545 deviation += (devB/2); 2502 deviation += (devB / 2);
2546 } 2503 }
2547 2504
2548 state->sys_clock_freq=(u16)((state-> 2505 state->sys_clock_freq =
2549 expected_sys_clock_freq)+ 2506 (u16) ((state->expected_sys_clock_freq) +
2550 deviation); 2507 deviation);
2551 } 2508 }
2552 CHK_ERROR(InitHI(state)); 2509 CHK_ERROR(InitHI(state));
2553 CHK_ERROR(InitAtomicRead(state)); 2510 CHK_ERROR(InitAtomicRead(state));
@@ -2565,7 +2522,7 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2565 2522
2566 if (state->PGA) { 2523 if (state->PGA) {
2567 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; 2524 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2568 SetCfgPga(state, 0); /* PGA = 0 dB */ 2525 SetCfgPga(state, 0); /* PGA = 0 dB */
2569 } else { 2526 } else {
2570 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; 2527 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2571 } 2528 }
@@ -2587,39 +2544,37 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2587 CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 2544 CHK_ERROR(Write16(state, SC_COMM_EXEC__A,
2588 SC_COMM_EXEC_CTL_STOP, 0)); 2545 SC_COMM_EXEC_CTL_STOP, 0));
2589 CHK_ERROR(Write16(state, LC_COMM_EXEC__A, 2546 CHK_ERROR(Write16(state, LC_COMM_EXEC__A,
2590 SC_COMM_EXEC_CTL_STOP, 0 )); 2547 SC_COMM_EXEC_CTL_STOP, 0));
2591
2592 2548
2593 driverVersion = (((VERSION_MAJOR/10) << 4) + 2549 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2594 (VERSION_MAJOR%10)) << 24; 2550 (VERSION_MAJOR % 10)) << 24;
2595 driverVersion += (((VERSION_MINOR/10) << 4) + 2551 driverVersion += (((VERSION_MINOR / 10) << 4) +
2596 (VERSION_MINOR%10)) << 16; 2552 (VERSION_MINOR % 10)) << 16;
2597 driverVersion += ((VERSION_PATCH/1000)<<12) + 2553 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2598 ((VERSION_PATCH/100)<<8) + 2554 ((VERSION_PATCH / 100) << 8) +
2599 ((VERSION_PATCH/10 )<< 4) + 2555 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2600 (VERSION_PATCH%10 );
2601 2556
2602 CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, 2557 CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX,
2603 driverVersion,0 )); 2558 driverVersion, 0));
2604 2559
2605 CHK_ERROR( StopOC(state) ); 2560 CHK_ERROR(StopOC(state));
2606 2561
2607 state->drxd_state = DRXD_STOPPED; 2562 state->drxd_state = DRXD_STOPPED;
2608 state->init_done=1; 2563 state->init_done = 1;
2609 status=0; 2564 status = 0;
2610 } while (0); 2565 } while (0);
2611 return status; 2566 return status;
2612} 2567}
2613 2568
2614int DRXD_status(struct drxd_state *state, u32 *pLockStatus) 2569int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2615{ 2570{
2616 DRX_GetLockStatus(state, pLockStatus); 2571 DRX_GetLockStatus(state, pLockStatus);
2617 2572
2618 /*if (*pLockStatus&DRX_LOCK_MPEG)*/ 2573 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2619 if (*pLockStatus&DRX_LOCK_FEC) { 2574 if (*pLockStatus & DRX_LOCK_FEC) {
2620 ConfigureMPEGOutput(state, 1); 2575 ConfigureMPEGOutput(state, 1);
2621 /* Get status again, in case we have MPEG lock now */ 2576 /* Get status again, in case we have MPEG lock now */
2622 /*DRX_GetLockStatus(state, pLockStatus);*/ 2577 /*DRX_GetLockStatus(state, pLockStatus); */
2623 } 2578 }
2624 2579
2625 return 0; 2580 return 0;
@@ -2629,61 +2584,59 @@ int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2629/****************************************************************************/ 2584/****************************************************************************/
2630/****************************************************************************/ 2585/****************************************************************************/
2631 2586
2632static int drxd_read_signal_strength(struct dvb_frontend *fe, 2587static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2633 u16 *strength)
2634{ 2588{
2635 struct drxd_state *state = fe->demodulator_priv; 2589 struct drxd_state *state = fe->demodulator_priv;
2636 u32 value; 2590 u32 value;
2637 int res; 2591 int res;
2638 2592
2639 res=ReadIFAgc(state, &value); 2593 res = ReadIFAgc(state, &value);
2640 if (res<0) 2594 if (res < 0)
2641 *strength=0; 2595 *strength = 0;
2642 else 2596 else
2643 *strength=0xffff-(value<<4); 2597 *strength = 0xffff - (value << 4);
2644 return 0; 2598 return 0;
2645} 2599}
2646 2600
2647 2601static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2648static int drxd_read_status(struct dvb_frontend *fe, fe_status_t *status)
2649{ 2602{
2650 struct drxd_state *state = fe->demodulator_priv; 2603 struct drxd_state *state = fe->demodulator_priv;
2651 u32 lock; 2604 u32 lock;
2652 2605
2653 DRXD_status(state, &lock); 2606 DRXD_status(state, &lock);
2654 *status=0; 2607 *status = 0;
2655 /* No MPEG lock in V255 firmware, bug ? */ 2608 /* No MPEG lock in V255 firmware, bug ? */
2656#if 1 2609#if 1
2657 if (lock&DRX_LOCK_MPEG) 2610 if (lock & DRX_LOCK_MPEG)
2658 *status|=FE_HAS_LOCK; 2611 *status |= FE_HAS_LOCK;
2659#else 2612#else
2660 if (lock&DRX_LOCK_FEC) 2613 if (lock & DRX_LOCK_FEC)
2661 *status|=FE_HAS_LOCK; 2614 *status |= FE_HAS_LOCK;
2662#endif 2615#endif
2663 if (lock&DRX_LOCK_FEC) 2616 if (lock & DRX_LOCK_FEC)
2664 *status|=FE_HAS_VITERBI|FE_HAS_SYNC; 2617 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2665 if (lock&DRX_LOCK_DEMOD) 2618 if (lock & DRX_LOCK_DEMOD)
2666 *status|=FE_HAS_CARRIER|FE_HAS_SIGNAL; 2619 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2667 2620
2668 return 0; 2621 return 0;
2669} 2622}
2670 2623
2671static int drxd_init(struct dvb_frontend *fe) 2624static int drxd_init(struct dvb_frontend *fe)
2672{ 2625{
2673 struct drxd_state *state=fe->demodulator_priv; 2626 struct drxd_state *state = fe->demodulator_priv;
2674 int err=0; 2627 int err = 0;
2675 2628
2676/* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */ 2629/* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2677 return DRXD_init(state, 0, 0); 2630 return DRXD_init(state, 0, 0);
2678 2631
2679 err=DRXD_init(state, state->fw->data, state->fw->size); 2632 err = DRXD_init(state, state->fw->data, state->fw->size);
2680 release_firmware(state->fw); 2633 release_firmware(state->fw);
2681 return err; 2634 return err;
2682} 2635}
2683 2636
2684int drxd_config_i2c(struct dvb_frontend *fe, int onoff) 2637int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2685{ 2638{
2686 struct drxd_state *state=fe->demodulator_priv; 2639 struct drxd_state *state = fe->demodulator_priv;
2687 2640
2688 if (state->config.disable_i2c_gate_ctrl == 1) 2641 if (state->config.disable_i2c_gate_ctrl == 1)
2689 return 0; 2642 return 0;
@@ -2692,58 +2645,58 @@ int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2692} 2645}
2693 2646
2694static int drxd_get_tune_settings(struct dvb_frontend *fe, 2647static int drxd_get_tune_settings(struct dvb_frontend *fe,
2695 struct dvb_frontend_tune_settings *sets) 2648 struct dvb_frontend_tune_settings *sets)
2696{ 2649{
2697 sets->min_delay_ms=10000; 2650 sets->min_delay_ms = 10000;
2698 sets->max_drift=0; 2651 sets->max_drift = 0;
2699 sets->step_size=0; 2652 sets->step_size = 0;
2700 return 0; 2653 return 0;
2701} 2654}
2702 2655
2703static int drxd_read_ber(struct dvb_frontend *fe, u32 *ber) 2656static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2704{ 2657{
2705 *ber = 0; 2658 *ber = 0;
2706 return 0; 2659 return 0;
2707} 2660}
2708 2661
2709static int drxd_read_snr(struct dvb_frontend *fe, u16 *snr) 2662static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2710{ 2663{
2711 *snr=0; 2664 *snr = 0;
2712 return 0; 2665 return 0;
2713} 2666}
2714 2667
2715static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 2668static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2716{ 2669{
2717 *ucblocks=0; 2670 *ucblocks = 0;
2718 return 0; 2671 return 0;
2719} 2672}
2720 2673
2721static int drxd_sleep(struct dvb_frontend* fe) 2674static int drxd_sleep(struct dvb_frontend *fe)
2722{ 2675{
2723 struct drxd_state *state=fe->demodulator_priv; 2676 struct drxd_state *state = fe->demodulator_priv;
2724 2677
2725 ConfigureMPEGOutput(state, 0); 2678 ConfigureMPEGOutput(state, 0);
2726 return 0; 2679 return 0;
2727} 2680}
2728 2681
2729static int drxd_get_frontend(struct dvb_frontend *fe, 2682static int drxd_get_frontend(struct dvb_frontend *fe,
2730 struct dvb_frontend_parameters *param) 2683 struct dvb_frontend_parameters *param)
2731{ 2684{
2732 return 0; 2685 return 0;
2733} 2686}
2734 2687
2735static int drxd_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) 2688static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2736{ 2689{
2737 return drxd_config_i2c(fe, enable); 2690 return drxd_config_i2c(fe, enable);
2738} 2691}
2739 2692
2740static int drxd_set_frontend(struct dvb_frontend *fe, 2693static int drxd_set_frontend(struct dvb_frontend *fe,
2741 struct dvb_frontend_parameters *param) 2694 struct dvb_frontend_parameters *param)
2742{ 2695{
2743 struct drxd_state *state=fe->demodulator_priv; 2696 struct drxd_state *state = fe->demodulator_priv;
2744 s32 off=0; 2697 s32 off = 0;
2745 2698
2746 state->param=*param; 2699 state->param = *param;
2747 DRX_Stop(state); 2700 DRX_Stop(state);
2748 2701
2749 if (fe->ops.tuner_ops.set_params) { 2702 if (fe->ops.tuner_ops.set_params) {
@@ -2756,8 +2709,7 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
2756 if (state->config.pll_set && 2709 if (state->config.pll_set &&
2757 state->config.pll_set(state->priv, param, 2710 state->config.pll_set(state->priv, param,
2758 state->config.pll_address, 2711 state->config.pll_address,
2759 state->config.demoda_address, 2712 state->config.demoda_address, &off) < 0) {
2760 &off)<0) {
2761 printk("Error in pll_set\n"); 2713 printk("Error in pll_set\n");
2762 return -1; 2714 return -1;
2763 } 2715 }
@@ -2767,7 +2719,6 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
2767 return DRX_Start(state, off); 2719 return DRX_Start(state, off);
2768} 2720}
2769 2721
2770
2771static void drxd_release(struct dvb_frontend *fe) 2722static void drxd_release(struct dvb_frontend *fe)
2772{ 2723{
2773 struct drxd_state *state = fe->demodulator_priv; 2724 struct drxd_state *state = fe->demodulator_priv;
@@ -2778,22 +2729,20 @@ static void drxd_release(struct dvb_frontend *fe)
2778static struct dvb_frontend_ops drxd_ops = { 2729static struct dvb_frontend_ops drxd_ops = {
2779 2730
2780 .info = { 2731 .info = {
2781 .name = "Micronas DRXD DVB-T", 2732 .name = "Micronas DRXD DVB-T",
2782 .type = FE_OFDM, 2733 .type = FE_OFDM,
2783 .frequency_min = 47125000, 2734 .frequency_min = 47125000,
2784 .frequency_max = 855250000, 2735 .frequency_max = 855250000,
2785 .frequency_stepsize = 166667, 2736 .frequency_stepsize = 166667,
2786 .frequency_tolerance = 0, 2737 .frequency_tolerance = 0,
2787 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 2738 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2788 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 2739 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2789 FE_CAN_FEC_AUTO | 2740 FE_CAN_FEC_AUTO |
2790 FE_CAN_QAM_16 | FE_CAN_QAM_64 | 2741 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2791 FE_CAN_QAM_AUTO | 2742 FE_CAN_QAM_AUTO |
2792 FE_CAN_TRANSMISSION_MODE_AUTO | 2743 FE_CAN_TRANSMISSION_MODE_AUTO |
2793 FE_CAN_GUARD_INTERVAL_AUTO | 2744 FE_CAN_GUARD_INTERVAL_AUTO |
2794 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | 2745 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2795 FE_CAN_MUTE_TS
2796 },
2797 2746
2798 .release = drxd_release, 2747 .release = drxd_release,
2799 .init = drxd_init, 2748 .init = drxd_init,
@@ -2817,29 +2766,29 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2817{ 2766{
2818 struct drxd_state *state = NULL; 2767 struct drxd_state *state = NULL;
2819 2768
2820 state=kmalloc(sizeof(struct drxd_state), GFP_KERNEL); 2769 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2821 if (!state) 2770 if (!state)
2822 return NULL; 2771 return NULL;
2823 memset(state, 0, sizeof(*state)); 2772 memset(state, 0, sizeof(*state));
2824 2773
2825 memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops)); 2774 memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2826 state->dev=dev; 2775 state->dev = dev;
2827 state->config=*config; 2776 state->config = *config;
2828 state->i2c=i2c; 2777 state->i2c = i2c;
2829 state->priv=priv; 2778 state->priv = priv;
2830 2779
2831 sema_init(&state->mutex, 1); 2780 sema_init(&state->mutex, 1);
2832 2781
2833 if (Read16(state, 0, 0, 0)<0) 2782 if (Read16(state, 0, 0, 0) < 0)
2834 goto error; 2783 goto error;
2835 2784
2836#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 2785#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
2837 state->frontend.ops=&state->ops; 2786 state->frontend.ops = &state->ops;
2838#else 2787#else
2839 memcpy(&state->frontend.ops, &drxd_ops, 2788 memcpy(&state->frontend.ops, &drxd_ops,
2840 sizeof(struct dvb_frontend_ops)); 2789 sizeof(struct dvb_frontend_ops));
2841#endif 2790#endif
2842 state->frontend.demodulator_priv=state; 2791 state->frontend.demodulator_priv = state;
2843 ConfigureMPEGOutput(state, 0); 2792 ConfigureMPEGOutput(state, 0);
2844 return &state->frontend; 2793 return &state->frontend;
2845 2794
diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h
index 3523cfee747..c9fbb459b20 100644
--- a/drivers/media/dvb/frontends/drxd_map_firm.h
+++ b/drivers/media/dvb/frontends/drxd_map_firm.h
@@ -24,16 +24,8 @@
24#ifndef __DRX3973D_MAP__H__ 24#ifndef __DRX3973D_MAP__H__
25#define __DRX3973D_MAP__H__ 25#define __DRX3973D_MAP__H__
26 26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31#define HI_SID 0x10 27#define HI_SID 0x10
32 28
33
34
35
36
37#define HI_COMM_EXEC__A 0x400000 29#define HI_COMM_EXEC__A 0x400000
38#define HI_COMM_EXEC__W 3 30#define HI_COMM_EXEC__W 3
39#define HI_COMM_EXEC__M 0x7 31#define HI_COMM_EXEC__M 0x7
@@ -66,11 +58,6 @@ extern "C" {
66#define HI_COMM_INT_MSK__W 16 58#define HI_COMM_INT_MSK__W 16
67#define HI_COMM_INT_MSK__M 0xFFFF 59#define HI_COMM_INT_MSK__M 0xFFFF
68 60
69
70
71
72
73
74#define HI_CT_REG_COMM_EXEC__A 0x410000 61#define HI_CT_REG_COMM_EXEC__A 0x410000
75#define HI_CT_REG_COMM_EXEC__W 3 62#define HI_CT_REG_COMM_EXEC__W 3
76#define HI_CT_REG_COMM_EXEC__M 0x7 63#define HI_CT_REG_COMM_EXEC__M 0x7
@@ -82,7 +69,6 @@ extern "C" {
82#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 69#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2
83#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 70#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3
84 71
85
86#define HI_CT_REG_COMM_STATE__A 0x410001 72#define HI_CT_REG_COMM_STATE__A 0x410001
87#define HI_CT_REG_COMM_STATE__W 10 73#define HI_CT_REG_COMM_STATE__W 10
88#define HI_CT_REG_COMM_STATE__M 0x3FF 74#define HI_CT_REG_COMM_STATE__M 0x3FF
@@ -96,7 +82,6 @@ extern "C" {
96#define HI_CT_REG_COMM_SERVICE1_HI__W 1 82#define HI_CT_REG_COMM_SERVICE1_HI__W 1
97#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 83#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1
98 84
99
100#define HI_CT_REG_COMM_INT_STA__A 0x410007 85#define HI_CT_REG_COMM_INT_STA__A 0x410007
101#define HI_CT_REG_COMM_INT_STA__W 1 86#define HI_CT_REG_COMM_INT_STA__W 1
102#define HI_CT_REG_COMM_INT_STA__M 0x1 87#define HI_CT_REG_COMM_INT_STA__M 0x1
@@ -104,7 +89,6 @@ extern "C" {
104#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 89#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1
105#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 90#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1
106 91
107
108#define HI_CT_REG_COMM_INT_MSK__A 0x410008 92#define HI_CT_REG_COMM_INT_MSK__A 0x410008
109#define HI_CT_REG_COMM_INT_MSK__W 1 93#define HI_CT_REG_COMM_INT_MSK__W 1
110#define HI_CT_REG_COMM_INT_MSK__M 0x1 94#define HI_CT_REG_COMM_INT_MSK__M 0x1
@@ -112,9 +96,6 @@ extern "C" {
112#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 96#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1
113#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 97#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
114 98
115
116
117
118#define HI_CT_REG_CTL_STK__AX 0x410010 99#define HI_CT_REG_CTL_STK__AX 0x410010
119#define HI_CT_REG_CTL_STK__XSZ 4 100#define HI_CT_REG_CTL_STK__XSZ 4
120#define HI_CT_REG_CTL_STK__W 10 101#define HI_CT_REG_CTL_STK__W 10
@@ -128,18 +109,12 @@ extern "C" {
128#define HI_CT_REG_CTL_BPT__W 10 109#define HI_CT_REG_CTL_BPT__W 10
129#define HI_CT_REG_CTL_BPT__M 0x3FF 110#define HI_CT_REG_CTL_BPT__M 0x3FF
130 111
131
132
133
134
135
136#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 112#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010
137#define HI_RA_RAM_SLV0_FLG_SMM__W 1 113#define HI_RA_RAM_SLV0_FLG_SMM__W 1
138#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 114#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1
139#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 115#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0
140#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 116#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1
141 117
142
143#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 118#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011
144#define HI_RA_RAM_SLV0_DEV_ID__W 7 119#define HI_RA_RAM_SLV0_DEV_ID__W 7
145#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F 120#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F
@@ -150,7 +125,6 @@ extern "C" {
150#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 125#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0
151#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 126#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1
152 127
153
154#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 128#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013
155#define HI_RA_RAM_SLV0_FLG_ACC__W 3 129#define HI_RA_RAM_SLV0_FLG_ACC__W 3
156#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 130#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7
@@ -165,14 +139,12 @@ extern "C" {
165#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 139#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0
166#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 140#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4
167 141
168
169#define HI_RA_RAM_SLV0_STATE__A 0x420014 142#define HI_RA_RAM_SLV0_STATE__A 0x420014
170#define HI_RA_RAM_SLV0_STATE__W 1 143#define HI_RA_RAM_SLV0_STATE__W 1
171#define HI_RA_RAM_SLV0_STATE__M 0x1 144#define HI_RA_RAM_SLV0_STATE__M 0x1
172#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 145#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0
173#define HI_RA_RAM_SLV0_STATE_DATA 0x1 146#define HI_RA_RAM_SLV0_STATE_DATA 0x1
174 147
175
176#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 148#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015
177#define HI_RA_RAM_SLV0_BLK_BNK__W 12 149#define HI_RA_RAM_SLV0_BLK_BNK__W 12
178#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF 150#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF
@@ -183,7 +155,6 @@ extern "C" {
183#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 155#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6
184#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 156#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0
185 157
186
187#define HI_RA_RAM_SLV0_ADDR__A 0x420016 158#define HI_RA_RAM_SLV0_ADDR__A 0x420016
188#define HI_RA_RAM_SLV0_ADDR__W 16 159#define HI_RA_RAM_SLV0_ADDR__W 16
189#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF 160#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF
@@ -196,16 +167,12 @@ extern "C" {
196#define HI_RA_RAM_SLV0_READBACK__W 16 167#define HI_RA_RAM_SLV0_READBACK__W 16
197#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF 168#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF
198 169
199
200
201
202#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 170#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020
203#define HI_RA_RAM_SLV1_FLG_SMM__W 1 171#define HI_RA_RAM_SLV1_FLG_SMM__W 1
204#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 172#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1
205#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 173#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0
206#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 174#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1
207 175
208
209#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 176#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021
210#define HI_RA_RAM_SLV1_DEV_ID__W 7 177#define HI_RA_RAM_SLV1_DEV_ID__W 7
211#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F 178#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F
@@ -216,7 +183,6 @@ extern "C" {
216#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 183#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0
217#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 184#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1
218 185
219
220#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 186#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023
221#define HI_RA_RAM_SLV1_FLG_ACC__W 3 187#define HI_RA_RAM_SLV1_FLG_ACC__W 3
222#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 188#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7
@@ -231,14 +197,12 @@ extern "C" {
231#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 197#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0
232#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 198#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4
233 199
234
235#define HI_RA_RAM_SLV1_STATE__A 0x420024 200#define HI_RA_RAM_SLV1_STATE__A 0x420024
236#define HI_RA_RAM_SLV1_STATE__W 1 201#define HI_RA_RAM_SLV1_STATE__W 1
237#define HI_RA_RAM_SLV1_STATE__M 0x1 202#define HI_RA_RAM_SLV1_STATE__M 0x1
238#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 203#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0
239#define HI_RA_RAM_SLV1_STATE_DATA 0x1 204#define HI_RA_RAM_SLV1_STATE_DATA 0x1
240 205
241
242#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 206#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025
243#define HI_RA_RAM_SLV1_BLK_BNK__W 12 207#define HI_RA_RAM_SLV1_BLK_BNK__W 12
244#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF 208#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF
@@ -249,7 +213,6 @@ extern "C" {
249#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 213#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6
250#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 214#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0
251 215
252
253#define HI_RA_RAM_SLV1_ADDR__A 0x420026 216#define HI_RA_RAM_SLV1_ADDR__A 0x420026
254#define HI_RA_RAM_SLV1_ADDR__W 16 217#define HI_RA_RAM_SLV1_ADDR__W 16
255#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF 218#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF
@@ -262,16 +225,12 @@ extern "C" {
262#define HI_RA_RAM_SLV1_READBACK__W 16 225#define HI_RA_RAM_SLV1_READBACK__W 16
263#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF 226#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF
264 227
265
266
267
268#define HI_RA_RAM_SRV_SEM__A 0x420030 228#define HI_RA_RAM_SRV_SEM__A 0x420030
269#define HI_RA_RAM_SRV_SEM__W 1 229#define HI_RA_RAM_SRV_SEM__W 1
270#define HI_RA_RAM_SRV_SEM__M 0x1 230#define HI_RA_RAM_SRV_SEM__M 0x1
271#define HI_RA_RAM_SRV_SEM_FREE 0x0 231#define HI_RA_RAM_SRV_SEM_FREE 0x0
272#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 232#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1
273 233
274
275#define HI_RA_RAM_SRV_RES__A 0x420031 234#define HI_RA_RAM_SRV_RES__A 0x420031
276#define HI_RA_RAM_SRV_RES__W 3 235#define HI_RA_RAM_SRV_RES__W 3
277#define HI_RA_RAM_SRV_RES__M 0x7 236#define HI_RA_RAM_SRV_RES__M 0x7
@@ -281,7 +240,6 @@ extern "C" {
281#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 240#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3
282#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 241#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4
283 242
284
285#define HI_RA_RAM_SRV_CMD__A 0x420032 243#define HI_RA_RAM_SRV_CMD__A 0x420032
286#define HI_RA_RAM_SRV_CMD__W 3 244#define HI_RA_RAM_SRV_CMD__W 3
287#define HI_RA_RAM_SRV_CMD__M 0x7 245#define HI_RA_RAM_SRV_CMD__M 0x7
@@ -293,22 +251,17 @@ extern "C" {
293#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 251#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5
294#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 252#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
295 253
296
297#define HI_RA_RAM_SRV_PAR__AX 0x420033 254#define HI_RA_RAM_SRV_PAR__AX 0x420033
298#define HI_RA_RAM_SRV_PAR__XSZ 5 255#define HI_RA_RAM_SRV_PAR__XSZ 5
299#define HI_RA_RAM_SRV_PAR__W 16 256#define HI_RA_RAM_SRV_PAR__W 16
300#define HI_RA_RAM_SRV_PAR__M 0xFFFF 257#define HI_RA_RAM_SRV_PAR__M 0xFFFF
301 258
302
303
304#define HI_RA_RAM_SRV_NOP_RES__A 0x420031 259#define HI_RA_RAM_SRV_NOP_RES__A 0x420031
305#define HI_RA_RAM_SRV_NOP_RES__W 3 260#define HI_RA_RAM_SRV_NOP_RES__W 3
306#define HI_RA_RAM_SRV_NOP_RES__M 0x7 261#define HI_RA_RAM_SRV_NOP_RES__M 0x7
307#define HI_RA_RAM_SRV_NOP_RES_OK 0x0 262#define HI_RA_RAM_SRV_NOP_RES_OK 0x0
308#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 263#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4
309 264
310
311
312#define HI_RA_RAM_SRV_UIO_RES__A 0x420031 265#define HI_RA_RAM_SRV_UIO_RES__A 0x420031
313#define HI_RA_RAM_SRV_UIO_RES__W 3 266#define HI_RA_RAM_SRV_UIO_RES__W 3
314#define HI_RA_RAM_SRV_UIO_RES__M 0x7 267#define HI_RA_RAM_SRV_UIO_RES__M 0x7
@@ -340,8 +293,6 @@ extern "C" {
340#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 293#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0
341#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 294#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2
342 295
343
344
345#define HI_RA_RAM_SRV_RST_RES__A 0x420031 296#define HI_RA_RAM_SRV_RST_RES__A 0x420031
346#define HI_RA_RAM_SRV_RST_RES__W 1 297#define HI_RA_RAM_SRV_RST_RES__W 1
347#define HI_RA_RAM_SRV_RST_RES__M 0x1 298#define HI_RA_RAM_SRV_RST_RES__M 0x1
@@ -353,8 +304,6 @@ extern "C" {
353#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF 304#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF
354#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 305#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
355 306
356
357
358#define HI_RA_RAM_SRV_CFG_RES__A 0x420031 307#define HI_RA_RAM_SRV_CFG_RES__A 0x420031
359#define HI_RA_RAM_SRV_CFG_RES__W 1 308#define HI_RA_RAM_SRV_CFG_RES__W 1
360#define HI_RA_RAM_SRV_CFG_RES__M 0x1 309#define HI_RA_RAM_SRV_CFG_RES__M 0x1
@@ -366,7 +315,6 @@ extern "C" {
366#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF 315#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF
367#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 316#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973
368 317
369
370#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 318#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034
371#define HI_RA_RAM_SRV_CFG_DIV__W 5 319#define HI_RA_RAM_SRV_CFG_DIV__W 5
372#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F 320#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F
@@ -403,15 +351,12 @@ extern "C" {
403#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 351#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0
404#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 352#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
405 353
406
407
408#define HI_RA_RAM_SRV_CPY_RES__A 0x420031 354#define HI_RA_RAM_SRV_CPY_RES__A 0x420031
409#define HI_RA_RAM_SRV_CPY_RES__W 1 355#define HI_RA_RAM_SRV_CPY_RES__W 1
410#define HI_RA_RAM_SRV_CPY_RES__M 0x1 356#define HI_RA_RAM_SRV_CPY_RES__M 0x1
411#define HI_RA_RAM_SRV_CPY_RES_OK 0x0 357#define HI_RA_RAM_SRV_CPY_RES_OK 0x0
412#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 358#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1
413 359
414
415#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 360#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033
416#define HI_RA_RAM_SRV_CPY_SBB__W 12 361#define HI_RA_RAM_SRV_CPY_SBB__W 12
417#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF 362#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF
@@ -422,7 +367,6 @@ extern "C" {
422#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 367#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6
423#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 368#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0
424 369
425
426#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 370#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034
427#define HI_RA_RAM_SRV_CPY_SAD__W 16 371#define HI_RA_RAM_SRV_CPY_SAD__W 16
428#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF 372#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF
@@ -441,13 +385,10 @@ extern "C" {
441#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 385#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6
442#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 386#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0
443 387
444
445#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 388#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034
446#define HI_RA_RAM_SRV_CPY_DAD__W 16 389#define HI_RA_RAM_SRV_CPY_DAD__W 16
447#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF 390#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF
448 391
449
450
451#define HI_RA_RAM_SRV_TRM_RES__A 0x420031 392#define HI_RA_RAM_SRV_TRM_RES__A 0x420031
452#define HI_RA_RAM_SRV_TRM_RES__W 2 393#define HI_RA_RAM_SRV_TRM_RES__W 2
453#define HI_RA_RAM_SRV_TRM_RES__M 0x3 394#define HI_RA_RAM_SRV_TRM_RES__M 0x3
@@ -455,7 +396,6 @@ extern "C" {
455#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 396#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1
456#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 397#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3
457 398
458
459#define HI_RA_RAM_SRV_TRM_MST__A 0x420033 399#define HI_RA_RAM_SRV_TRM_MST__A 0x420033
460#define HI_RA_RAM_SRV_TRM_MST__W 12 400#define HI_RA_RAM_SRV_TRM_MST__W 12
461#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF 401#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF
@@ -471,7 +411,6 @@ extern "C" {
471#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 411#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8
472#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF 412#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF
473 413
474
475#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 414#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033
476#define HI_RA_RAM_SRV_TRM_DBB__W 12 415#define HI_RA_RAM_SRV_TRM_DBB__W 12
477#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF 416#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF
@@ -482,14 +421,10 @@ extern "C" {
482#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 421#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6
483#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 422#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0
484 423
485
486#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 424#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034
487#define HI_RA_RAM_SRV_TRM_DAD__W 16 425#define HI_RA_RAM_SRV_TRM_DAD__W 16
488#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF 426#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF
489 427
490
491
492
493#define HI_RA_RAM_USR_BEGIN__A 0x420040 428#define HI_RA_RAM_USR_BEGIN__A 0x420040
494#define HI_RA_RAM_USR_BEGIN__W 16 429#define HI_RA_RAM_USR_BEGIN__W 16
495#define HI_RA_RAM_USR_BEGIN__M 0xFFFF 430#define HI_RA_RAM_USR_BEGIN__M 0xFFFF
@@ -498,11 +433,6 @@ extern "C" {
498#define HI_RA_RAM_USR_END__W 16 433#define HI_RA_RAM_USR_END__W 16
499#define HI_RA_RAM_USR_END__M 0xFFFF 434#define HI_RA_RAM_USR_END__M 0xFFFF
500 435
501
502
503
504
505
506#define HI_IF_RAM_TRP_BPT0__AX 0x430000 436#define HI_IF_RAM_TRP_BPT0__AX 0x430000
507#define HI_IF_RAM_TRP_BPT0__XSZ 2 437#define HI_IF_RAM_TRP_BPT0__XSZ 2
508#define HI_IF_RAM_TRP_BPT0__W 12 438#define HI_IF_RAM_TRP_BPT0__W 12
@@ -513,9 +443,6 @@ extern "C" {
513#define HI_IF_RAM_TRP_STKU__W 12 443#define HI_IF_RAM_TRP_STKU__W 12
514#define HI_IF_RAM_TRP_STKU__M 0xFFF 444#define HI_IF_RAM_TRP_STKU__M 0xFFF
515 445
516
517
518
519#define HI_IF_RAM_USR_BEGIN__A 0x430200 446#define HI_IF_RAM_USR_BEGIN__A 0x430200
520#define HI_IF_RAM_USR_BEGIN__W 12 447#define HI_IF_RAM_USR_BEGIN__W 12
521#define HI_IF_RAM_USR_BEGIN__M 0xFFF 448#define HI_IF_RAM_USR_BEGIN__M 0xFFF
@@ -524,16 +451,8 @@ extern "C" {
524#define HI_IF_RAM_USR_END__W 12 451#define HI_IF_RAM_USR_END__W 12
525#define HI_IF_RAM_USR_END__M 0xFFF 452#define HI_IF_RAM_USR_END__M 0xFFF
526 453
527
528
529
530
531#define SC_SID 0x11 454#define SC_SID 0x11
532 455
533
534
535
536
537#define SC_COMM_EXEC__A 0x800000 456#define SC_COMM_EXEC__A 0x800000
538#define SC_COMM_EXEC__W 3 457#define SC_COMM_EXEC__W 3
539#define SC_COMM_EXEC__M 0x7 458#define SC_COMM_EXEC__M 0x7
@@ -566,11 +485,6 @@ extern "C" {
566#define SC_COMM_INT_MSK__W 16 485#define SC_COMM_INT_MSK__W 16
567#define SC_COMM_INT_MSK__M 0xFFFF 486#define SC_COMM_INT_MSK__M 0xFFFF
568 487
569
570
571
572
573
574#define SC_CT_REG_COMM_EXEC__A 0x810000 488#define SC_CT_REG_COMM_EXEC__A 0x810000
575#define SC_CT_REG_COMM_EXEC__W 3 489#define SC_CT_REG_COMM_EXEC__W 3
576#define SC_CT_REG_COMM_EXEC__M 0x7 490#define SC_CT_REG_COMM_EXEC__M 0x7
@@ -582,7 +496,6 @@ extern "C" {
582#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 496#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
583#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 497#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3
584 498
585
586#define SC_CT_REG_COMM_STATE__A 0x810001 499#define SC_CT_REG_COMM_STATE__A 0x810001
587#define SC_CT_REG_COMM_STATE__W 10 500#define SC_CT_REG_COMM_STATE__W 10
588#define SC_CT_REG_COMM_STATE__M 0x3FF 501#define SC_CT_REG_COMM_STATE__M 0x3FF
@@ -596,7 +509,6 @@ extern "C" {
596#define SC_CT_REG_COMM_SERVICE1_SC__W 1 509#define SC_CT_REG_COMM_SERVICE1_SC__W 1
597#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 510#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2
598 511
599
600#define SC_CT_REG_COMM_INT_STA__A 0x810007 512#define SC_CT_REG_COMM_INT_STA__A 0x810007
601#define SC_CT_REG_COMM_INT_STA__W 1 513#define SC_CT_REG_COMM_INT_STA__W 1
602#define SC_CT_REG_COMM_INT_STA__M 0x1 514#define SC_CT_REG_COMM_INT_STA__M 0x1
@@ -604,7 +516,6 @@ extern "C" {
604#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 516#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1
605#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 517#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
606 518
607
608#define SC_CT_REG_COMM_INT_MSK__A 0x810008 519#define SC_CT_REG_COMM_INT_MSK__A 0x810008
609#define SC_CT_REG_COMM_INT_MSK__W 1 520#define SC_CT_REG_COMM_INT_MSK__W 1
610#define SC_CT_REG_COMM_INT_MSK__M 0x1 521#define SC_CT_REG_COMM_INT_MSK__M 0x1
@@ -612,9 +523,6 @@ extern "C" {
612#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 523#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1
613#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 524#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
614 525
615
616
617
618#define SC_CT_REG_CTL_STK__AX 0x810010 526#define SC_CT_REG_CTL_STK__AX 0x810010
619#define SC_CT_REG_CTL_STK__XSZ 4 527#define SC_CT_REG_CTL_STK__XSZ 4
620#define SC_CT_REG_CTL_STK__W 10 528#define SC_CT_REG_CTL_STK__W 10
@@ -628,10 +536,6 @@ extern "C" {
628#define SC_CT_REG_CTL_BPT__W 10 536#define SC_CT_REG_CTL_BPT__W 10
629#define SC_CT_REG_CTL_BPT__M 0x3FF 537#define SC_CT_REG_CTL_BPT__M 0x3FF
630 538
631
632
633
634
635#define SC_RA_RAM_PARAM0__A 0x820040 539#define SC_RA_RAM_PARAM0__A 0x820040
636#define SC_RA_RAM_PARAM0__W 16 540#define SC_RA_RAM_PARAM0__W 16
637#define SC_RA_RAM_PARAM0__M 0xFFFF 541#define SC_RA_RAM_PARAM0__M 0xFFFF
@@ -722,8 +626,6 @@ extern "C" {
722#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC 626#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC
723#define SC_RA_RAM_LOCKTRACK_MAX 0xD 627#define SC_RA_RAM_LOCKTRACK_MAX 0xD
724 628
725
726
727#define SC_RA_RAM_OP_PARAM__A 0x820048 629#define SC_RA_RAM_OP_PARAM__A 0x820048
728#define SC_RA_RAM_OP_PARAM__W 13 630#define SC_RA_RAM_OP_PARAM__W 13
729#define SC_RA_RAM_OP_PARAM__M 0x1FFF 631#define SC_RA_RAM_OP_PARAM__M 0x1FFF
@@ -812,8 +714,6 @@ extern "C" {
812#define SC_RA_RAM_LOCK_NODVBT__W 1 714#define SC_RA_RAM_LOCK_NODVBT__W 1
813#define SC_RA_RAM_LOCK_NODVBT__M 0x8 715#define SC_RA_RAM_LOCK_NODVBT__M 0x8
814 716
815
816
817#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C 717#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C
818#define SC_RA_RAM_BE_OPT_ENA__W 5 718#define SC_RA_RAM_BE_OPT_ENA__W 5
819#define SC_RA_RAM_BE_OPT_ENA__M 0x1F 719#define SC_RA_RAM_BE_OPT_ENA__M 0x1F
@@ -873,8 +773,6 @@ extern "C" {
873#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 773#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1
874#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 774#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000
875 775
876
877
878#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 776#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051
879#define SC_RA_RAM_PILOT_THRES_SPD__W 16 777#define SC_RA_RAM_PILOT_THRES_SPD__W 16
880#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF 778#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF
@@ -888,8 +786,6 @@ extern "C" {
888#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF 786#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF
889#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 787#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406
890 788
891
892
893#define SC_RA_RAM_CO_THRES_8K__A 0x820055 789#define SC_RA_RAM_CO_THRES_8K__A 0x820055
894#define SC_RA_RAM_CO_THRES_8K__W 16 790#define SC_RA_RAM_CO_THRES_8K__W 16
895#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF 791#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF
@@ -991,17 +887,11 @@ extern "C" {
991#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF 887#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF
992#define SC_RA_RAM_ECHO_GUARD__PRE 0x18 888#define SC_RA_RAM_ECHO_GUARD__PRE 0x18
993 889
994
995
996#define SC_RA_RAM_IR_FREQ__A 0x8200D0 890#define SC_RA_RAM_IR_FREQ__A 0x8200D0
997#define SC_RA_RAM_IR_FREQ__W 16 891#define SC_RA_RAM_IR_FREQ__W 16
998#define SC_RA_RAM_IR_FREQ__M 0xFFFF 892#define SC_RA_RAM_IR_FREQ__M 0xFFFF
999#define SC_RA_RAM_IR_FREQ__PRE 0x0 893#define SC_RA_RAM_IR_FREQ__PRE 0x0
1000 894
1001
1002
1003
1004
1005#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 895#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
1006#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 896#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16
1007#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF 897#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF
@@ -1015,8 +905,6 @@ extern "C" {
1015#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF 905#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF
1016#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 906#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
1017 907
1018
1019
1020#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 908#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
1021#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 909#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16
1022#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF 910#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF
@@ -1030,10 +918,6 @@ extern "C" {
1030#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF 918#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF
1031#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 919#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
1032 920
1033
1034
1035
1036
1037#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 921#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
1038#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 922#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16
1039#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF 923#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF
@@ -1047,8 +931,6 @@ extern "C" {
1047#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF 931#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF
1048#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 932#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
1049 933
1050
1051
1052#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 934#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
1053#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 935#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16
1054#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF 936#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF
@@ -1062,8 +944,6 @@ extern "C" {
1062#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF 944#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF
1063#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 945#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
1064 946
1065
1066
1067#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 947#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
1068#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 948#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16
1069#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF 949#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF
@@ -1077,10 +957,6 @@ extern "C" {
1077#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF 957#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF
1078#define SC_RA_RAM_ECHO_FILTER__PRE 0x2 958#define SC_RA_RAM_ECHO_FILTER__PRE 0x2
1079 959
1080
1081
1082
1083
1084#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 960#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0
1085#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 961#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16
1086#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF 962#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF
@@ -1094,8 +970,6 @@ extern "C" {
1094#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF 970#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF
1095#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 971#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8
1096 972
1097
1098
1099#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 973#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3
1100#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 974#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16
1101#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF 975#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF
@@ -1109,8 +983,6 @@ extern "C" {
1109#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF 983#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF
1110#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 984#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0
1111 985
1112
1113
1114#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 986#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
1115#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 987#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16
1116#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF 988#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF
@@ -1120,8 +992,6 @@ extern "C" {
1120#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF 992#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF
1121#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 993#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113
1122 994
1123
1124
1125#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA 995#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA
1126#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 996#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16
1127#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF 997#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF
@@ -1176,8 +1046,6 @@ extern "C" {
1176#define SC_RA_RAM_BOOTCOUNT__W 16 1046#define SC_RA_RAM_BOOTCOUNT__W 16
1177#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF 1047#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF
1178 1048
1179
1180
1181#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 1049#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4
1182#define SC_RA_RAM_LC_ABS_2K__W 16 1050#define SC_RA_RAM_LC_ABS_2K__W 16
1183#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF 1051#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF
@@ -1187,10 +1055,6 @@ extern "C" {
1187#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF 1055#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF
1188#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F 1056#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F
1189 1057
1190
1191
1192
1193
1194#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 1058#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6
1195#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 1059#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16
1196#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF 1060#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF
@@ -1200,8 +1064,6 @@ extern "C" {
1200#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF 1064#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF
1201#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 1065#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0
1202 1066
1203
1204
1205#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 1067#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8
1206#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 1068#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16
1207#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF 1069#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF
@@ -1217,8 +1079,6 @@ extern "C" {
1217#define SC_RA_RAM_STACKUNDERFLOW__W 16 1079#define SC_RA_RAM_STACKUNDERFLOW__W 16
1218#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF 1080#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF
1219 1081
1220
1221
1222#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 1082#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148
1223#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 1083#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16
1224#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF 1084#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF
@@ -1246,10 +1106,6 @@ extern "C" {
1246#define SC_RA_RAM_NF_ECHOTABLE__W 16 1106#define SC_RA_RAM_NF_ECHOTABLE__W 16
1247#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF 1107#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF
1248 1108
1249
1250
1251
1252
1253#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 1109#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0
1254#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 1110#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16
1255#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF 1111#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF
@@ -1259,8 +1115,6 @@ extern "C" {
1259#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF 1115#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF
1260#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 1116#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
1261 1117
1262
1263
1264#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 1118#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2
1265#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 1119#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16
1266#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF 1120#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF
@@ -1270,8 +1124,6 @@ extern "C" {
1270#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF 1124#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF
1271#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 1125#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5
1272 1126
1273
1274
1275#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 1127#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4
1276#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 1128#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16
1277#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF 1129#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF
@@ -1281,8 +1133,6 @@ extern "C" {
1281#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF 1133#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF
1282#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 1134#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
1283 1135
1284
1285
1286#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 1136#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6
1287#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 1137#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16
1288#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF 1138#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF
@@ -1292,8 +1142,6 @@ extern "C" {
1292#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF 1142#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF
1293#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 1143#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5
1294 1144
1295
1296
1297#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 1145#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8
1298#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 1146#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16
1299#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF 1147#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF
@@ -1303,8 +1151,6 @@ extern "C" {
1303#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF 1151#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF
1304#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 1152#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6
1305 1153
1306
1307
1308#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA 1154#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA
1309#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 1155#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16
1310#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF 1156#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF
@@ -1314,8 +1160,6 @@ extern "C" {
1314#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF 1160#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF
1315#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 1161#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
1316 1162
1317
1318
1319#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC 1163#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC
1320#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 1164#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16
1321#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF 1165#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF
@@ -1325,8 +1169,6 @@ extern "C" {
1325#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF 1169#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF
1326#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 1170#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5
1327 1171
1328
1329
1330#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE 1172#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE
1331#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 1173#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16
1332#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF 1174#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF
@@ -1357,11 +1199,6 @@ extern "C" {
1357#define SC_RA_RAM_PROC_EQ 0x7 1199#define SC_RA_RAM_PROC_EQ 0x7
1358#define SC_RA_RAM_PROC_MAX 0x8 1200#define SC_RA_RAM_PROC_MAX 0x8
1359 1201
1360
1361
1362
1363
1364
1365#define SC_IF_RAM_TRP_RST__AX 0x830000 1202#define SC_IF_RAM_TRP_RST__AX 0x830000
1366#define SC_IF_RAM_TRP_RST__XSZ 2 1203#define SC_IF_RAM_TRP_RST__XSZ 2
1367#define SC_IF_RAM_TRP_RST__W 12 1204#define SC_IF_RAM_TRP_RST__W 12
@@ -1377,9 +1214,6 @@ extern "C" {
1377#define SC_IF_RAM_TRP_STKU__W 12 1214#define SC_IF_RAM_TRP_STKU__W 12
1378#define SC_IF_RAM_TRP_STKU__M 0xFFF 1215#define SC_IF_RAM_TRP_STKU__M 0xFFF
1379 1216
1380
1381
1382
1383#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE 1217#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE
1384#define SC_IF_RAM_VERSION_MA_MI__W 12 1218#define SC_IF_RAM_VERSION_MA_MI__W 12
1385#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF 1219#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF
@@ -1388,14 +1222,6 @@ extern "C" {
1388#define SC_IF_RAM_VERSION_PATCH__W 12 1222#define SC_IF_RAM_VERSION_PATCH__W 12
1389#define SC_IF_RAM_VERSION_PATCH__M 0xFFF 1223#define SC_IF_RAM_VERSION_PATCH__M 0xFFF
1390 1224
1391
1392
1393
1394
1395
1396
1397
1398
1399#define FE_COMM_EXEC__A 0xC00000 1225#define FE_COMM_EXEC__A 0xC00000
1400#define FE_COMM_EXEC__W 3 1226#define FE_COMM_EXEC__W 3
1401#define FE_COMM_EXEC__M 0x7 1227#define FE_COMM_EXEC__M 0x7
@@ -1428,17 +1254,8 @@ extern "C" {
1428#define FE_COMM_INT_MSK__W 16 1254#define FE_COMM_INT_MSK__W 16
1429#define FE_COMM_INT_MSK__M 0xFFFF 1255#define FE_COMM_INT_MSK__M 0xFFFF
1430 1256
1431
1432
1433
1434
1435#define FE_AD_SID 0x1 1257#define FE_AD_SID 0x1
1436 1258
1437
1438
1439
1440
1441
1442#define FE_AD_REG_COMM_EXEC__A 0xC10000 1259#define FE_AD_REG_COMM_EXEC__A 0xC10000
1443#define FE_AD_REG_COMM_EXEC__W 3 1260#define FE_AD_REG_COMM_EXEC__W 3
1444#define FE_AD_REG_COMM_EXEC__M 0x7 1261#define FE_AD_REG_COMM_EXEC__M 0x7
@@ -1450,7 +1267,6 @@ extern "C" {
1450#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 1267#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2
1451#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 1268#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3
1452 1269
1453
1454#define FE_AD_REG_COMM_MB__A 0xC10002 1270#define FE_AD_REG_COMM_MB__A 0xC10002
1455#define FE_AD_REG_COMM_MB__W 2 1271#define FE_AD_REG_COMM_MB__W 2
1456#define FE_AD_REG_COMM_MB__M 0x3 1272#define FE_AD_REG_COMM_MB__M 0x3
@@ -1483,7 +1299,6 @@ extern "C" {
1483#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 1299#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1
1484#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 1300#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1
1485 1301
1486
1487#define FE_AD_REG_COMM_INT_MSK__A 0xC10008 1302#define FE_AD_REG_COMM_INT_MSK__A 0xC10008
1488#define FE_AD_REG_COMM_INT_MSK__W 2 1303#define FE_AD_REG_COMM_INT_MSK__W 2
1489#define FE_AD_REG_COMM_INT_MSK__M 0x3 1304#define FE_AD_REG_COMM_INT_MSK__M 0x3
@@ -1491,137 +1306,108 @@ extern "C" {
1491#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 1306#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1
1492#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 1307#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1
1493 1308
1494
1495#define FE_AD_REG_CUR_SEL__A 0xC10010 1309#define FE_AD_REG_CUR_SEL__A 0xC10010
1496#define FE_AD_REG_CUR_SEL__W 2 1310#define FE_AD_REG_CUR_SEL__W 2
1497#define FE_AD_REG_CUR_SEL__M 0x3 1311#define FE_AD_REG_CUR_SEL__M 0x3
1498#define FE_AD_REG_CUR_SEL_INIT 0x2 1312#define FE_AD_REG_CUR_SEL_INIT 0x2
1499 1313
1500
1501#define FE_AD_REG_OVERFLOW__A 0xC10011 1314#define FE_AD_REG_OVERFLOW__A 0xC10011
1502#define FE_AD_REG_OVERFLOW__W 1 1315#define FE_AD_REG_OVERFLOW__W 1
1503#define FE_AD_REG_OVERFLOW__M 0x1 1316#define FE_AD_REG_OVERFLOW__M 0x1
1504#define FE_AD_REG_OVERFLOW_INIT 0x0 1317#define FE_AD_REG_OVERFLOW_INIT 0x0
1505 1318
1506
1507#define FE_AD_REG_FDB_IN__A 0xC10012 1319#define FE_AD_REG_FDB_IN__A 0xC10012
1508#define FE_AD_REG_FDB_IN__W 1 1320#define FE_AD_REG_FDB_IN__W 1
1509#define FE_AD_REG_FDB_IN__M 0x1 1321#define FE_AD_REG_FDB_IN__M 0x1
1510#define FE_AD_REG_FDB_IN_INIT 0x0 1322#define FE_AD_REG_FDB_IN_INIT 0x0
1511 1323
1512
1513#define FE_AD_REG_PD__A 0xC10013 1324#define FE_AD_REG_PD__A 0xC10013
1514#define FE_AD_REG_PD__W 1 1325#define FE_AD_REG_PD__W 1
1515#define FE_AD_REG_PD__M 0x1 1326#define FE_AD_REG_PD__M 0x1
1516#define FE_AD_REG_PD_INIT 0x1 1327#define FE_AD_REG_PD_INIT 0x1
1517 1328
1518
1519#define FE_AD_REG_INVEXT__A 0xC10014 1329#define FE_AD_REG_INVEXT__A 0xC10014
1520#define FE_AD_REG_INVEXT__W 1 1330#define FE_AD_REG_INVEXT__W 1
1521#define FE_AD_REG_INVEXT__M 0x1 1331#define FE_AD_REG_INVEXT__M 0x1
1522#define FE_AD_REG_INVEXT_INIT 0x0 1332#define FE_AD_REG_INVEXT_INIT 0x0
1523 1333
1524
1525#define FE_AD_REG_CLKNEG__A 0xC10015 1334#define FE_AD_REG_CLKNEG__A 0xC10015
1526#define FE_AD_REG_CLKNEG__W 1 1335#define FE_AD_REG_CLKNEG__W 1
1527#define FE_AD_REG_CLKNEG__M 0x1 1336#define FE_AD_REG_CLKNEG__M 0x1
1528#define FE_AD_REG_CLKNEG_INIT 0x0 1337#define FE_AD_REG_CLKNEG_INIT 0x0
1529 1338
1530
1531#define FE_AD_REG_MON_IN_MUX__A 0xC10016 1339#define FE_AD_REG_MON_IN_MUX__A 0xC10016
1532#define FE_AD_REG_MON_IN_MUX__W 2 1340#define FE_AD_REG_MON_IN_MUX__W 2
1533#define FE_AD_REG_MON_IN_MUX__M 0x3 1341#define FE_AD_REG_MON_IN_MUX__M 0x3
1534#define FE_AD_REG_MON_IN_MUX_INIT 0x0 1342#define FE_AD_REG_MON_IN_MUX_INIT 0x0
1535 1343
1536
1537#define FE_AD_REG_MON_IN5__A 0xC10017 1344#define FE_AD_REG_MON_IN5__A 0xC10017
1538#define FE_AD_REG_MON_IN5__W 10 1345#define FE_AD_REG_MON_IN5__W 10
1539#define FE_AD_REG_MON_IN5__M 0x3FF 1346#define FE_AD_REG_MON_IN5__M 0x3FF
1540#define FE_AD_REG_MON_IN5_INIT 0x0 1347#define FE_AD_REG_MON_IN5_INIT 0x0
1541 1348
1542
1543#define FE_AD_REG_MON_IN4__A 0xC10018 1349#define FE_AD_REG_MON_IN4__A 0xC10018
1544#define FE_AD_REG_MON_IN4__W 10 1350#define FE_AD_REG_MON_IN4__W 10
1545#define FE_AD_REG_MON_IN4__M 0x3FF 1351#define FE_AD_REG_MON_IN4__M 0x3FF
1546#define FE_AD_REG_MON_IN4_INIT 0x0 1352#define FE_AD_REG_MON_IN4_INIT 0x0
1547 1353
1548
1549#define FE_AD_REG_MON_IN3__A 0xC10019 1354#define FE_AD_REG_MON_IN3__A 0xC10019
1550#define FE_AD_REG_MON_IN3__W 10 1355#define FE_AD_REG_MON_IN3__W 10
1551#define FE_AD_REG_MON_IN3__M 0x3FF 1356#define FE_AD_REG_MON_IN3__M 0x3FF
1552#define FE_AD_REG_MON_IN3_INIT 0x0 1357#define FE_AD_REG_MON_IN3_INIT 0x0
1553 1358
1554
1555#define FE_AD_REG_MON_IN2__A 0xC1001A 1359#define FE_AD_REG_MON_IN2__A 0xC1001A
1556#define FE_AD_REG_MON_IN2__W 10 1360#define FE_AD_REG_MON_IN2__W 10
1557#define FE_AD_REG_MON_IN2__M 0x3FF 1361#define FE_AD_REG_MON_IN2__M 0x3FF
1558#define FE_AD_REG_MON_IN2_INIT 0x0 1362#define FE_AD_REG_MON_IN2_INIT 0x0
1559 1363
1560
1561#define FE_AD_REG_MON_IN1__A 0xC1001B 1364#define FE_AD_REG_MON_IN1__A 0xC1001B
1562#define FE_AD_REG_MON_IN1__W 10 1365#define FE_AD_REG_MON_IN1__W 10
1563#define FE_AD_REG_MON_IN1__M 0x3FF 1366#define FE_AD_REG_MON_IN1__M 0x3FF
1564#define FE_AD_REG_MON_IN1_INIT 0x0 1367#define FE_AD_REG_MON_IN1_INIT 0x0
1565 1368
1566
1567#define FE_AD_REG_MON_IN0__A 0xC1001C 1369#define FE_AD_REG_MON_IN0__A 0xC1001C
1568#define FE_AD_REG_MON_IN0__W 10 1370#define FE_AD_REG_MON_IN0__W 10
1569#define FE_AD_REG_MON_IN0__M 0x3FF 1371#define FE_AD_REG_MON_IN0__M 0x3FF
1570#define FE_AD_REG_MON_IN0_INIT 0x0 1372#define FE_AD_REG_MON_IN0_INIT 0x0
1571 1373
1572
1573#define FE_AD_REG_MON_IN_VAL__A 0xC1001D 1374#define FE_AD_REG_MON_IN_VAL__A 0xC1001D
1574#define FE_AD_REG_MON_IN_VAL__W 1 1375#define FE_AD_REG_MON_IN_VAL__W 1
1575#define FE_AD_REG_MON_IN_VAL__M 0x1 1376#define FE_AD_REG_MON_IN_VAL__M 0x1
1576#define FE_AD_REG_MON_IN_VAL_INIT 0x0 1377#define FE_AD_REG_MON_IN_VAL_INIT 0x0
1577 1378
1578
1579#define FE_AD_REG_CTR_CLK_O__A 0xC1001E 1379#define FE_AD_REG_CTR_CLK_O__A 0xC1001E
1580#define FE_AD_REG_CTR_CLK_O__W 1 1380#define FE_AD_REG_CTR_CLK_O__W 1
1581#define FE_AD_REG_CTR_CLK_O__M 0x1 1381#define FE_AD_REG_CTR_CLK_O__M 0x1
1582#define FE_AD_REG_CTR_CLK_O_INIT 0x0 1382#define FE_AD_REG_CTR_CLK_O_INIT 0x0
1583 1383
1584
1585#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F 1384#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F
1586#define FE_AD_REG_CTR_CLK_E_O__W 1 1385#define FE_AD_REG_CTR_CLK_E_O__W 1
1587#define FE_AD_REG_CTR_CLK_E_O__M 0x1 1386#define FE_AD_REG_CTR_CLK_E_O__M 0x1
1588#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 1387#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1
1589 1388
1590
1591#define FE_AD_REG_CTR_VAL_O__A 0xC10020 1389#define FE_AD_REG_CTR_VAL_O__A 0xC10020
1592#define FE_AD_REG_CTR_VAL_O__W 1 1390#define FE_AD_REG_CTR_VAL_O__W 1
1593#define FE_AD_REG_CTR_VAL_O__M 0x1 1391#define FE_AD_REG_CTR_VAL_O__M 0x1
1594#define FE_AD_REG_CTR_VAL_O_INIT 0x0 1392#define FE_AD_REG_CTR_VAL_O_INIT 0x0
1595 1393
1596
1597#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 1394#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021
1598#define FE_AD_REG_CTR_VAL_E_O__W 1 1395#define FE_AD_REG_CTR_VAL_E_O__W 1
1599#define FE_AD_REG_CTR_VAL_E_O__M 0x1 1396#define FE_AD_REG_CTR_VAL_E_O__M 0x1
1600#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 1397#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1
1601 1398
1602
1603#define FE_AD_REG_CTR_DATA_O__A 0xC10022 1399#define FE_AD_REG_CTR_DATA_O__A 0xC10022
1604#define FE_AD_REG_CTR_DATA_O__W 10 1400#define FE_AD_REG_CTR_DATA_O__W 10
1605#define FE_AD_REG_CTR_DATA_O__M 0x3FF 1401#define FE_AD_REG_CTR_DATA_O__M 0x3FF
1606#define FE_AD_REG_CTR_DATA_O_INIT 0x0 1402#define FE_AD_REG_CTR_DATA_O_INIT 0x0
1607 1403
1608
1609#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 1404#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023
1610#define FE_AD_REG_CTR_DATA_E_O__W 10 1405#define FE_AD_REG_CTR_DATA_E_O__W 10
1611#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF 1406#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF
1612#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF 1407#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF
1613 1408
1614
1615
1616
1617
1618#define FE_AG_SID 0x2 1409#define FE_AG_SID 0x2
1619 1410
1620
1621
1622
1623
1624
1625#define FE_AG_REG_COMM_EXEC__A 0xC20000 1411#define FE_AG_REG_COMM_EXEC__A 0xC20000
1626#define FE_AG_REG_COMM_EXEC__W 3 1412#define FE_AG_REG_COMM_EXEC__W 3
1627#define FE_AG_REG_COMM_EXEC__M 0x7 1413#define FE_AG_REG_COMM_EXEC__M 0x7
@@ -1651,7 +1437,6 @@ extern "C" {
1651#define FE_AG_REG_COMM_MB_OBS_OFF 0x0 1437#define FE_AG_REG_COMM_MB_OBS_OFF 0x0
1652#define FE_AG_REG_COMM_MB_OBS_ON 0x2 1438#define FE_AG_REG_COMM_MB_OBS_ON 0x2
1653 1439
1654
1655#define FE_AG_REG_COMM_SERVICE0__A 0xC20003 1440#define FE_AG_REG_COMM_SERVICE0__A 0xC20003
1656#define FE_AG_REG_COMM_SERVICE0__W 10 1441#define FE_AG_REG_COMM_SERVICE0__W 10
1657#define FE_AG_REG_COMM_SERVICE0__M 0x3FF 1442#define FE_AG_REG_COMM_SERVICE0__M 0x3FF
@@ -1688,7 +1473,6 @@ extern "C" {
1688#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 1473#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1
1689#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 1474#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80
1690 1475
1691
1692#define FE_AG_REG_COMM_INT_MSK__A 0xC20008 1476#define FE_AG_REG_COMM_INT_MSK__A 0xC20008
1693#define FE_AG_REG_COMM_INT_MSK__W 8 1477#define FE_AG_REG_COMM_INT_MSK__W 8
1694#define FE_AG_REG_COMM_INT_MSK__M 0xFF 1478#define FE_AG_REG_COMM_INT_MSK__M 0xFF
@@ -1717,7 +1501,6 @@ extern "C" {
1717#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 1501#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1
1718#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 1502#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80
1719 1503
1720
1721#define FE_AG_REG_AG_MODE_LOP__A 0xC20010 1504#define FE_AG_REG_AG_MODE_LOP__A 0xC20010
1722#define FE_AG_REG_AG_MODE_LOP__W 16 1505#define FE_AG_REG_AG_MODE_LOP__W 16
1723#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF 1506#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF
@@ -1819,7 +1602,6 @@ extern "C" {
1819#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 1602#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0
1820#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 1603#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000
1821 1604
1822
1823#define FE_AG_REG_AG_MODE_HIP__A 0xC20011 1605#define FE_AG_REG_AG_MODE_HIP__A 0xC20011
1824#define FE_AG_REG_AG_MODE_HIP__W 2 1606#define FE_AG_REG_AG_MODE_HIP__W 2
1825#define FE_AG_REG_AG_MODE_HIP__M 0x3 1607#define FE_AG_REG_AG_MODE_HIP__M 0x3
@@ -1837,7 +1619,6 @@ extern "C" {
1837#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 1619#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0
1838#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 1620#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2
1839 1621
1840
1841#define FE_AG_REG_AG_PGA_MODE__A 0xC20012 1622#define FE_AG_REG_AG_PGA_MODE__A 0xC20012
1842#define FE_AG_REG_AG_PGA_MODE__W 3 1623#define FE_AG_REG_AG_PGA_MODE__W 3
1843#define FE_AG_REG_AG_PGA_MODE__M 0x7 1624#define FE_AG_REG_AG_PGA_MODE__M 0x7
@@ -1851,7 +1632,6 @@ extern "C" {
1851#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 1632#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6
1852#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 1633#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7
1853 1634
1854
1855#define FE_AG_REG_AG_AGC_SIO__A 0xC20013 1635#define FE_AG_REG_AG_AGC_SIO__A 0xC20013
1856#define FE_AG_REG_AG_AGC_SIO__W 2 1636#define FE_AG_REG_AG_AGC_SIO__W 2
1857#define FE_AG_REG_AG_AGC_SIO__M 0x3 1637#define FE_AG_REG_AG_AGC_SIO__M 0x3
@@ -1869,7 +1649,6 @@ extern "C" {
1869#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 1649#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
1870#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 1650#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
1871 1651
1872
1873#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 1652#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014
1874#define FE_AG_REG_AG_AGC_USR_DAT__W 2 1653#define FE_AG_REG_AG_AGC_USR_DAT__W 2
1875#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 1654#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3
@@ -1880,7 +1659,6 @@ extern "C" {
1880#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 1659#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1
1881#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 1660#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2
1882 1661
1883
1884#define FE_AG_REG_AG_PWD__A 0xC20015 1662#define FE_AG_REG_AG_PWD__A 0xC20015
1885#define FE_AG_REG_AG_PWD__W 5 1663#define FE_AG_REG_AG_PWD__W 5
1886#define FE_AG_REG_AG_PWD__M 0x1F 1664#define FE_AG_REG_AG_PWD__M 0x1F
@@ -1916,19 +1694,16 @@ extern "C" {
1916#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 1694#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0
1917#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 1695#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10
1918 1696
1919
1920#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 1697#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016
1921#define FE_AG_REG_DCE_AUR_CNT__W 5 1698#define FE_AG_REG_DCE_AUR_CNT__W 5
1922#define FE_AG_REG_DCE_AUR_CNT__M 0x1F 1699#define FE_AG_REG_DCE_AUR_CNT__M 0x1F
1923#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 1700#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0
1924 1701
1925
1926#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 1702#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017
1927#define FE_AG_REG_DCE_RUR_CNT__W 5 1703#define FE_AG_REG_DCE_RUR_CNT__W 5
1928#define FE_AG_REG_DCE_RUR_CNT__M 0x1F 1704#define FE_AG_REG_DCE_RUR_CNT__M 0x1F
1929#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 1705#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0
1930 1706
1931
1932#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 1707#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018
1933#define FE_AG_REG_DCE_AVE_DAT__W 10 1708#define FE_AG_REG_DCE_AVE_DAT__W 10
1934#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF 1709#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF
@@ -1938,19 +1713,16 @@ extern "C" {
1938#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF 1713#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF
1939#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 1714#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0
1940 1715
1941
1942#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 1716#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
1943#define FE_AG_REG_ACE_AUR_CNT__W 5 1717#define FE_AG_REG_ACE_AUR_CNT__W 5
1944#define FE_AG_REG_ACE_AUR_CNT__M 0x1F 1718#define FE_AG_REG_ACE_AUR_CNT__M 0x1F
1945#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 1719#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0
1946 1720
1947
1948#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 1721#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
1949#define FE_AG_REG_ACE_RUR_CNT__W 5 1722#define FE_AG_REG_ACE_RUR_CNT__W 5
1950#define FE_AG_REG_ACE_RUR_CNT__M 0x1F 1723#define FE_AG_REG_ACE_RUR_CNT__M 0x1F
1951#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 1724#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0
1952 1725
1953
1954#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C 1726#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C
1955#define FE_AG_REG_ACE_AVE_DAT__W 10 1727#define FE_AG_REG_ACE_AVE_DAT__W 10
1956#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF 1728#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF
@@ -1960,7 +1732,6 @@ extern "C" {
1960#define FE_AG_REG_AEC_AVE_INC__M 0x3FF 1732#define FE_AG_REG_AEC_AVE_INC__M 0x3FF
1961#define FE_AG_REG_AEC_AVE_INC_INIT 0x0 1733#define FE_AG_REG_AEC_AVE_INC_INIT 0x0
1962 1734
1963
1964#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E 1735#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E
1965#define FE_AG_REG_AEC_AVE_DAT__W 10 1736#define FE_AG_REG_AEC_AVE_DAT__W 10
1966#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF 1737#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF
@@ -1970,13 +1741,11 @@ extern "C" {
1970#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF 1741#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF
1971#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 1742#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0
1972 1743
1973
1974#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 1744#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020
1975#define FE_AG_REG_CDR_RUR_CNT__W 5 1745#define FE_AG_REG_CDR_RUR_CNT__W 5
1976#define FE_AG_REG_CDR_RUR_CNT__M 0x1F 1746#define FE_AG_REG_CDR_RUR_CNT__M 0x1F
1977#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 1747#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0
1978 1748
1979
1980#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 1749#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021
1981#define FE_AG_REG_CDR_CLP_DAT__W 16 1750#define FE_AG_REG_CDR_CLP_DAT__W 16
1982#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF 1751#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF
@@ -1986,79 +1755,66 @@ extern "C" {
1986#define FE_AG_REG_CDR_CLP_POS__M 0x3FF 1755#define FE_AG_REG_CDR_CLP_POS__M 0x3FF
1987#define FE_AG_REG_CDR_CLP_POS_INIT 0x0 1756#define FE_AG_REG_CDR_CLP_POS_INIT 0x0
1988 1757
1989
1990#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 1758#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023
1991#define FE_AG_REG_CDR_CLP_NEG__W 10 1759#define FE_AG_REG_CDR_CLP_NEG__W 10
1992#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF 1760#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF
1993#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 1761#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0
1994 1762
1995
1996#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 1763#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024
1997#define FE_AG_REG_EGC_RUR_CNT__W 5 1764#define FE_AG_REG_EGC_RUR_CNT__W 5
1998#define FE_AG_REG_EGC_RUR_CNT__M 0x1F 1765#define FE_AG_REG_EGC_RUR_CNT__M 0x1F
1999#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 1766#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0
2000 1767
2001
2002#define FE_AG_REG_EGC_SET_LVL__A 0xC20025 1768#define FE_AG_REG_EGC_SET_LVL__A 0xC20025
2003#define FE_AG_REG_EGC_SET_LVL__W 9 1769#define FE_AG_REG_EGC_SET_LVL__W 9
2004#define FE_AG_REG_EGC_SET_LVL__M 0x1FF 1770#define FE_AG_REG_EGC_SET_LVL__M 0x1FF
2005#define FE_AG_REG_EGC_SET_LVL_INIT 0x0 1771#define FE_AG_REG_EGC_SET_LVL_INIT 0x0
2006 1772
2007
2008#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 1773#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026
2009#define FE_AG_REG_EGC_FLA_RGN__W 9 1774#define FE_AG_REG_EGC_FLA_RGN__W 9
2010#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF 1775#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF
2011#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 1776#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0
2012 1777
2013
2014#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 1778#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027
2015#define FE_AG_REG_EGC_SLO_RGN__W 9 1779#define FE_AG_REG_EGC_SLO_RGN__W 9
2016#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF 1780#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF
2017#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 1781#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0
2018 1782
2019
2020#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 1783#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028
2021#define FE_AG_REG_EGC_JMP_PSN__W 4 1784#define FE_AG_REG_EGC_JMP_PSN__W 4
2022#define FE_AG_REG_EGC_JMP_PSN__M 0xF 1785#define FE_AG_REG_EGC_JMP_PSN__M 0xF
2023#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 1786#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0
2024 1787
2025
2026#define FE_AG_REG_EGC_FLA_INC__A 0xC20029 1788#define FE_AG_REG_EGC_FLA_INC__A 0xC20029
2027#define FE_AG_REG_EGC_FLA_INC__W 16 1789#define FE_AG_REG_EGC_FLA_INC__W 16
2028#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF 1790#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF
2029#define FE_AG_REG_EGC_FLA_INC_INIT 0x0 1791#define FE_AG_REG_EGC_FLA_INC_INIT 0x0
2030 1792
2031
2032#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 1793#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
2033#define FE_AG_REG_EGC_FLA_DEC__W 16 1794#define FE_AG_REG_EGC_FLA_DEC__W 16
2034#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF 1795#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF
2035#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 1796#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0
2036 1797
2037
2038#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B 1798#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B
2039#define FE_AG_REG_EGC_SLO_INC__W 16 1799#define FE_AG_REG_EGC_SLO_INC__W 16
2040#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF 1800#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF
2041#define FE_AG_REG_EGC_SLO_INC_INIT 0x0 1801#define FE_AG_REG_EGC_SLO_INC_INIT 0x0
2042 1802
2043
2044#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 1803#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
2045#define FE_AG_REG_EGC_SLO_DEC__W 16 1804#define FE_AG_REG_EGC_SLO_DEC__W 16
2046#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF 1805#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF
2047#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 1806#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0
2048 1807
2049
2050#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D 1808#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D
2051#define FE_AG_REG_EGC_FAS_INC__W 16 1809#define FE_AG_REG_EGC_FAS_INC__W 16
2052#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF 1810#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF
2053#define FE_AG_REG_EGC_FAS_INC_INIT 0x0 1811#define FE_AG_REG_EGC_FAS_INC_INIT 0x0
2054 1812
2055
2056#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 1813#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
2057#define FE_AG_REG_EGC_FAS_DEC__W 16 1814#define FE_AG_REG_EGC_FAS_DEC__W 16
2058#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF 1815#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF
2059#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 1816#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0
2060 1817
2061
2062#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F 1818#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F
2063#define FE_AG_REG_EGC_MAP_DAT__W 16 1819#define FE_AG_REG_EGC_MAP_DAT__W 16
2064#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF 1820#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF
@@ -2068,31 +1824,26 @@ extern "C" {
2068#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF 1824#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF
2069#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 1825#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0
2070 1826
2071
2072#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 1827#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031
2073#define FE_AG_REG_GC1_AGC_RIC__W 16 1828#define FE_AG_REG_GC1_AGC_RIC__W 16
2074#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF 1829#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF
2075#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 1830#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0
2076 1831
2077
2078#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 1832#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032
2079#define FE_AG_REG_GC1_AGC_OFF__W 16 1833#define FE_AG_REG_GC1_AGC_OFF__W 16
2080#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF 1834#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF
2081#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 1835#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0
2082 1836
2083
2084#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 1837#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033
2085#define FE_AG_REG_GC1_AGC_MAX__W 10 1838#define FE_AG_REG_GC1_AGC_MAX__W 10
2086#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF 1839#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF
2087#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 1840#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0
2088 1841
2089
2090#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 1842#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034
2091#define FE_AG_REG_GC1_AGC_MIN__W 10 1843#define FE_AG_REG_GC1_AGC_MIN__W 10
2092#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF 1844#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF
2093#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 1845#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0
2094 1846
2095
2096#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 1847#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035
2097#define FE_AG_REG_GC1_AGC_DAT__W 10 1848#define FE_AG_REG_GC1_AGC_DAT__W 10
2098#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF 1849#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF
@@ -2102,31 +1853,26 @@ extern "C" {
2102#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF 1853#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF
2103#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 1854#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0
2104 1855
2105
2106#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 1856#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037
2107#define FE_AG_REG_GC2_AGC_RIC__W 16 1857#define FE_AG_REG_GC2_AGC_RIC__W 16
2108#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF 1858#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF
2109#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 1859#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0
2110 1860
2111
2112#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 1861#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038
2113#define FE_AG_REG_GC2_AGC_OFF__W 16 1862#define FE_AG_REG_GC2_AGC_OFF__W 16
2114#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF 1863#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF
2115#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 1864#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0
2116 1865
2117
2118#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 1866#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039
2119#define FE_AG_REG_GC2_AGC_MAX__W 10 1867#define FE_AG_REG_GC2_AGC_MAX__W 10
2120#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF 1868#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF
2121#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 1869#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0
2122 1870
2123
2124#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A 1871#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A
2125#define FE_AG_REG_GC2_AGC_MIN__W 10 1872#define FE_AG_REG_GC2_AGC_MIN__W 10
2126#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF 1873#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF
2127#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 1874#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0
2128 1875
2129
2130#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B 1876#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B
2131#define FE_AG_REG_GC2_AGC_DAT__W 10 1877#define FE_AG_REG_GC2_AGC_DAT__W 10
2132#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF 1878#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF
@@ -2136,43 +1882,36 @@ extern "C" {
2136#define FE_AG_REG_IND_WIN__M 0x1F 1882#define FE_AG_REG_IND_WIN__M 0x1F
2137#define FE_AG_REG_IND_WIN_INIT 0x0 1883#define FE_AG_REG_IND_WIN_INIT 0x0
2138 1884
2139
2140#define FE_AG_REG_IND_THD_LOL__A 0xC2003D 1885#define FE_AG_REG_IND_THD_LOL__A 0xC2003D
2141#define FE_AG_REG_IND_THD_LOL__W 6 1886#define FE_AG_REG_IND_THD_LOL__W 6
2142#define FE_AG_REG_IND_THD_LOL__M 0x3F 1887#define FE_AG_REG_IND_THD_LOL__M 0x3F
2143#define FE_AG_REG_IND_THD_LOL_INIT 0x0 1888#define FE_AG_REG_IND_THD_LOL_INIT 0x0
2144 1889
2145
2146#define FE_AG_REG_IND_THD_HIL__A 0xC2003E 1890#define FE_AG_REG_IND_THD_HIL__A 0xC2003E
2147#define FE_AG_REG_IND_THD_HIL__W 6 1891#define FE_AG_REG_IND_THD_HIL__W 6
2148#define FE_AG_REG_IND_THD_HIL__M 0x3F 1892#define FE_AG_REG_IND_THD_HIL__M 0x3F
2149#define FE_AG_REG_IND_THD_HIL_INIT 0x0 1893#define FE_AG_REG_IND_THD_HIL_INIT 0x0
2150 1894
2151
2152#define FE_AG_REG_IND_DEL__A 0xC2003F 1895#define FE_AG_REG_IND_DEL__A 0xC2003F
2153#define FE_AG_REG_IND_DEL__W 7 1896#define FE_AG_REG_IND_DEL__W 7
2154#define FE_AG_REG_IND_DEL__M 0x7F 1897#define FE_AG_REG_IND_DEL__M 0x7F
2155#define FE_AG_REG_IND_DEL_INIT 0x0 1898#define FE_AG_REG_IND_DEL_INIT 0x0
2156 1899
2157
2158#define FE_AG_REG_IND_PD1_WRI__A 0xC20040 1900#define FE_AG_REG_IND_PD1_WRI__A 0xC20040
2159#define FE_AG_REG_IND_PD1_WRI__W 6 1901#define FE_AG_REG_IND_PD1_WRI__W 6
2160#define FE_AG_REG_IND_PD1_WRI__M 0x3F 1902#define FE_AG_REG_IND_PD1_WRI__M 0x3F
2161#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F 1903#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F
2162 1904
2163
2164#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 1905#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041
2165#define FE_AG_REG_PDA_AUR_CNT__W 5 1906#define FE_AG_REG_PDA_AUR_CNT__W 5
2166#define FE_AG_REG_PDA_AUR_CNT__M 0x1F 1907#define FE_AG_REG_PDA_AUR_CNT__M 0x1F
2167#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 1908#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0
2168 1909
2169
2170#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 1910#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042
2171#define FE_AG_REG_PDA_RUR_CNT__W 5 1911#define FE_AG_REG_PDA_RUR_CNT__W 5
2172#define FE_AG_REG_PDA_RUR_CNT__M 0x1F 1912#define FE_AG_REG_PDA_RUR_CNT__M 0x1F
2173#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 1913#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0
2174 1914
2175
2176#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 1915#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043
2177#define FE_AG_REG_PDA_AVE_DAT__W 6 1916#define FE_AG_REG_PDA_AVE_DAT__W 6
2178#define FE_AG_REG_PDA_AVE_DAT__M 0x3F 1917#define FE_AG_REG_PDA_AVE_DAT__M 0x3F
@@ -2182,43 +1921,36 @@ extern "C" {
2182#define FE_AG_REG_PDC_RUR_CNT__M 0x1F 1921#define FE_AG_REG_PDC_RUR_CNT__M 0x1F
2183#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 1922#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0
2184 1923
2185
2186#define FE_AG_REG_PDC_SET_LVL__A 0xC20045 1924#define FE_AG_REG_PDC_SET_LVL__A 0xC20045
2187#define FE_AG_REG_PDC_SET_LVL__W 6 1925#define FE_AG_REG_PDC_SET_LVL__W 6
2188#define FE_AG_REG_PDC_SET_LVL__M 0x3F 1926#define FE_AG_REG_PDC_SET_LVL__M 0x3F
2189#define FE_AG_REG_PDC_SET_LVL_INIT 0x10 1927#define FE_AG_REG_PDC_SET_LVL_INIT 0x10
2190 1928
2191
2192#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 1929#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046
2193#define FE_AG_REG_PDC_FLA_RGN__W 6 1930#define FE_AG_REG_PDC_FLA_RGN__W 6
2194#define FE_AG_REG_PDC_FLA_RGN__M 0x3F 1931#define FE_AG_REG_PDC_FLA_RGN__M 0x3F
2195#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 1932#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0
2196 1933
2197
2198#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 1934#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047
2199#define FE_AG_REG_PDC_JMP_PSN__W 3 1935#define FE_AG_REG_PDC_JMP_PSN__W 3
2200#define FE_AG_REG_PDC_JMP_PSN__M 0x7 1936#define FE_AG_REG_PDC_JMP_PSN__M 0x7
2201#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 1937#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0
2202 1938
2203
2204#define FE_AG_REG_PDC_FLA_STP__A 0xC20048 1939#define FE_AG_REG_PDC_FLA_STP__A 0xC20048
2205#define FE_AG_REG_PDC_FLA_STP__W 16 1940#define FE_AG_REG_PDC_FLA_STP__W 16
2206#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF 1941#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF
2207#define FE_AG_REG_PDC_FLA_STP_INIT 0x0 1942#define FE_AG_REG_PDC_FLA_STP_INIT 0x0
2208 1943
2209
2210#define FE_AG_REG_PDC_SLO_STP__A 0xC20049 1944#define FE_AG_REG_PDC_SLO_STP__A 0xC20049
2211#define FE_AG_REG_PDC_SLO_STP__W 16 1945#define FE_AG_REG_PDC_SLO_STP__W 16
2212#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF 1946#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF
2213#define FE_AG_REG_PDC_SLO_STP_INIT 0x0 1947#define FE_AG_REG_PDC_SLO_STP_INIT 0x0
2214 1948
2215
2216#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 1949#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
2217#define FE_AG_REG_PDC_PD2_WRI__W 6 1950#define FE_AG_REG_PDC_PD2_WRI__W 6
2218#define FE_AG_REG_PDC_PD2_WRI__M 0x3F 1951#define FE_AG_REG_PDC_PD2_WRI__M 0x3F
2219#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 1952#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0
2220 1953
2221
2222#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 1954#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
2223#define FE_AG_REG_PDC_MAP_DAT__W 6 1955#define FE_AG_REG_PDC_MAP_DAT__W 6
2224#define FE_AG_REG_PDC_MAP_DAT__M 0x3F 1956#define FE_AG_REG_PDC_MAP_DAT__M 0x3F
@@ -2228,19 +1960,16 @@ extern "C" {
2228#define FE_AG_REG_PDC_MAX__M 0x3F 1960#define FE_AG_REG_PDC_MAX__M 0x3F
2229#define FE_AG_REG_PDC_MAX_INIT 0x2 1961#define FE_AG_REG_PDC_MAX_INIT 0x2
2230 1962
2231
2232#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 1963#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
2233#define FE_AG_REG_TGA_AUR_CNT__W 5 1964#define FE_AG_REG_TGA_AUR_CNT__W 5
2234#define FE_AG_REG_TGA_AUR_CNT__M 0x1F 1965#define FE_AG_REG_TGA_AUR_CNT__M 0x1F
2235#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 1966#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0
2236 1967
2237
2238#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 1968#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
2239#define FE_AG_REG_TGA_RUR_CNT__W 5 1969#define FE_AG_REG_TGA_RUR_CNT__W 5
2240#define FE_AG_REG_TGA_RUR_CNT__M 0x1F 1970#define FE_AG_REG_TGA_RUR_CNT__M 0x1F
2241#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 1971#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0
2242 1972
2243
2244#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 1973#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
2245#define FE_AG_REG_TGA_AVE_DAT__W 6 1974#define FE_AG_REG_TGA_AVE_DAT__W 6
2246#define FE_AG_REG_TGA_AVE_DAT__M 0x3F 1975#define FE_AG_REG_TGA_AVE_DAT__M 0x3F
@@ -2250,37 +1979,31 @@ extern "C" {
2250#define FE_AG_REG_TGC_RUR_CNT__M 0x1F 1979#define FE_AG_REG_TGC_RUR_CNT__M 0x1F
2251#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 1980#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0
2252 1981
2253
2254#define FE_AG_REG_TGC_SET_LVL__A 0xC20051 1982#define FE_AG_REG_TGC_SET_LVL__A 0xC20051
2255#define FE_AG_REG_TGC_SET_LVL__W 6 1983#define FE_AG_REG_TGC_SET_LVL__W 6
2256#define FE_AG_REG_TGC_SET_LVL__M 0x3F 1984#define FE_AG_REG_TGC_SET_LVL__M 0x3F
2257#define FE_AG_REG_TGC_SET_LVL_INIT 0x0 1985#define FE_AG_REG_TGC_SET_LVL_INIT 0x0
2258 1986
2259
2260#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 1987#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052
2261#define FE_AG_REG_TGC_FLA_RGN__W 6 1988#define FE_AG_REG_TGC_FLA_RGN__W 6
2262#define FE_AG_REG_TGC_FLA_RGN__M 0x3F 1989#define FE_AG_REG_TGC_FLA_RGN__M 0x3F
2263#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 1990#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0
2264 1991
2265
2266#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 1992#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053
2267#define FE_AG_REG_TGC_JMP_PSN__W 4 1993#define FE_AG_REG_TGC_JMP_PSN__W 4
2268#define FE_AG_REG_TGC_JMP_PSN__M 0xF 1994#define FE_AG_REG_TGC_JMP_PSN__M 0xF
2269#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 1995#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0
2270 1996
2271
2272#define FE_AG_REG_TGC_FLA_STP__A 0xC20054 1997#define FE_AG_REG_TGC_FLA_STP__A 0xC20054
2273#define FE_AG_REG_TGC_FLA_STP__W 16 1998#define FE_AG_REG_TGC_FLA_STP__W 16
2274#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF 1999#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF
2275#define FE_AG_REG_TGC_FLA_STP_INIT 0x0 2000#define FE_AG_REG_TGC_FLA_STP_INIT 0x0
2276 2001
2277
2278#define FE_AG_REG_TGC_SLO_STP__A 0xC20055 2002#define FE_AG_REG_TGC_SLO_STP__A 0xC20055
2279#define FE_AG_REG_TGC_SLO_STP__W 16 2003#define FE_AG_REG_TGC_SLO_STP__W 16
2280#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF 2004#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF
2281#define FE_AG_REG_TGC_SLO_STP_INIT 0x0 2005#define FE_AG_REG_TGC_SLO_STP_INIT 0x0
2282 2006
2283
2284#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 2007#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056
2285#define FE_AG_REG_TGC_MAP_DAT__W 10 2008#define FE_AG_REG_TGC_MAP_DAT__W 10
2286#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF 2009#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF
@@ -2290,13 +2013,11 @@ extern "C" {
2290#define FE_AG_REG_FGA_AUR_CNT__M 0x1F 2013#define FE_AG_REG_FGA_AUR_CNT__M 0x1F
2291#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 2014#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0
2292 2015
2293
2294#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 2016#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058
2295#define FE_AG_REG_FGA_RUR_CNT__W 5 2017#define FE_AG_REG_FGA_RUR_CNT__W 5
2296#define FE_AG_REG_FGA_RUR_CNT__M 0x1F 2018#define FE_AG_REG_FGA_RUR_CNT__M 0x1F
2297#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 2019#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0
2298 2020
2299
2300#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 2021#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059
2301#define FE_AG_REG_FGA_AVE_DAT__W 10 2022#define FE_AG_REG_FGA_AVE_DAT__W 10
2302#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF 2023#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF
@@ -2306,37 +2027,31 @@ extern "C" {
2306#define FE_AG_REG_FGC_RUR_CNT__M 0x1F 2027#define FE_AG_REG_FGC_RUR_CNT__M 0x1F
2307#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 2028#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0
2308 2029
2309
2310#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B 2030#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B
2311#define FE_AG_REG_FGC_SET_LVL__W 9 2031#define FE_AG_REG_FGC_SET_LVL__W 9
2312#define FE_AG_REG_FGC_SET_LVL__M 0x1FF 2032#define FE_AG_REG_FGC_SET_LVL__M 0x1FF
2313#define FE_AG_REG_FGC_SET_LVL_INIT 0x0 2033#define FE_AG_REG_FGC_SET_LVL_INIT 0x0
2314 2034
2315
2316#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C 2035#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C
2317#define FE_AG_REG_FGC_FLA_RGN__W 9 2036#define FE_AG_REG_FGC_FLA_RGN__W 9
2318#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF 2037#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF
2319#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 2038#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0
2320 2039
2321
2322#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D 2040#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D
2323#define FE_AG_REG_FGC_JMP_PSN__W 4 2041#define FE_AG_REG_FGC_JMP_PSN__W 4
2324#define FE_AG_REG_FGC_JMP_PSN__M 0xF 2042#define FE_AG_REG_FGC_JMP_PSN__M 0xF
2325#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 2043#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0
2326 2044
2327
2328#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E 2045#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E
2329#define FE_AG_REG_FGC_FLA_STP__W 16 2046#define FE_AG_REG_FGC_FLA_STP__W 16
2330#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF 2047#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF
2331#define FE_AG_REG_FGC_FLA_STP_INIT 0x0 2048#define FE_AG_REG_FGC_FLA_STP_INIT 0x0
2332 2049
2333
2334#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F 2050#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F
2335#define FE_AG_REG_FGC_SLO_STP__W 16 2051#define FE_AG_REG_FGC_SLO_STP__W 16
2336#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF 2052#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF
2337#define FE_AG_REG_FGC_SLO_STP_INIT 0x0 2053#define FE_AG_REG_FGC_SLO_STP_INIT 0x0
2338 2054
2339
2340#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 2055#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060
2341#define FE_AG_REG_FGC_MAP_DAT__W 10 2056#define FE_AG_REG_FGC_MAP_DAT__W 10
2342#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF 2057#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF
@@ -2346,70 +2061,52 @@ extern "C" {
2346#define FE_AG_REG_FGM_WRI__M 0x3FF 2061#define FE_AG_REG_FGM_WRI__M 0x3FF
2347#define FE_AG_REG_FGM_WRI_INIT 0x20 2062#define FE_AG_REG_FGM_WRI_INIT 0x20
2348 2063
2349
2350#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 2064#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062
2351#define FE_AG_REG_BGC_RUR_CNT__W 5 2065#define FE_AG_REG_BGC_RUR_CNT__W 5
2352#define FE_AG_REG_BGC_RUR_CNT__M 0x1F 2066#define FE_AG_REG_BGC_RUR_CNT__M 0x1F
2353#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 2067#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0
2354 2068
2355
2356#define FE_AG_REG_BGC_SET_LVL__A 0xC20063 2069#define FE_AG_REG_BGC_SET_LVL__A 0xC20063
2357#define FE_AG_REG_BGC_SET_LVL__W 9 2070#define FE_AG_REG_BGC_SET_LVL__W 9
2358#define FE_AG_REG_BGC_SET_LVL__M 0x1FF 2071#define FE_AG_REG_BGC_SET_LVL__M 0x1FF
2359#define FE_AG_REG_BGC_SET_LVL_INIT 0x0 2072#define FE_AG_REG_BGC_SET_LVL_INIT 0x0
2360 2073
2361
2362#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 2074#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064
2363#define FE_AG_REG_BGC_FLA_RGN__W 9 2075#define FE_AG_REG_BGC_FLA_RGN__W 9
2364#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF 2076#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF
2365#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 2077#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0
2366 2078
2367
2368#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 2079#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065
2369#define FE_AG_REG_BGC_JMP_PSN__W 4 2080#define FE_AG_REG_BGC_JMP_PSN__W 4
2370#define FE_AG_REG_BGC_JMP_PSN__M 0xF 2081#define FE_AG_REG_BGC_JMP_PSN__M 0xF
2371#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 2082#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0
2372 2083
2373
2374#define FE_AG_REG_BGC_FLA_STP__A 0xC20066 2084#define FE_AG_REG_BGC_FLA_STP__A 0xC20066
2375#define FE_AG_REG_BGC_FLA_STP__W 16 2085#define FE_AG_REG_BGC_FLA_STP__W 16
2376#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF 2086#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF
2377#define FE_AG_REG_BGC_FLA_STP_INIT 0x0 2087#define FE_AG_REG_BGC_FLA_STP_INIT 0x0
2378 2088
2379
2380#define FE_AG_REG_BGC_SLO_STP__A 0xC20067 2089#define FE_AG_REG_BGC_SLO_STP__A 0xC20067
2381#define FE_AG_REG_BGC_SLO_STP__W 16 2090#define FE_AG_REG_BGC_SLO_STP__W 16
2382#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF 2091#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF
2383#define FE_AG_REG_BGC_SLO_STP_INIT 0x0 2092#define FE_AG_REG_BGC_SLO_STP_INIT 0x0
2384 2093
2385
2386#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 2094#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068
2387#define FE_AG_REG_BGC_FGC_WRI__W 4 2095#define FE_AG_REG_BGC_FGC_WRI__W 4
2388#define FE_AG_REG_BGC_FGC_WRI__M 0xF 2096#define FE_AG_REG_BGC_FGC_WRI__M 0xF
2389#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 2097#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7
2390 2098
2391
2392#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 2099#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069
2393#define FE_AG_REG_BGC_CGC_WRI__W 2 2100#define FE_AG_REG_BGC_CGC_WRI__W 2
2394#define FE_AG_REG_BGC_CGC_WRI__M 0x3 2101#define FE_AG_REG_BGC_CGC_WRI__M 0x3
2395#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 2102#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1
2396 2103
2397
2398#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A 2104#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A
2399#define FE_AG_REG_BGC_FGC_DAT__W 4 2105#define FE_AG_REG_BGC_FGC_DAT__W 4
2400#define FE_AG_REG_BGC_FGC_DAT__M 0xF 2106#define FE_AG_REG_BGC_FGC_DAT__M 0xF
2401 2107
2402
2403
2404
2405
2406#define FE_FS_SID 0x3 2108#define FE_FS_SID 0x3
2407 2109
2408
2409
2410
2411
2412
2413#define FE_FS_REG_COMM_EXEC__A 0xC30000 2110#define FE_FS_REG_COMM_EXEC__A 0xC30000
2414#define FE_FS_REG_COMM_EXEC__W 3 2111#define FE_FS_REG_COMM_EXEC__W 3
2415#define FE_FS_REG_COMM_EXEC__M 0x7 2112#define FE_FS_REG_COMM_EXEC__M 0x7
@@ -2444,7 +2141,6 @@ extern "C" {
2444#define FE_FS_REG_COMM_MB_MUX_REAL 0x0 2141#define FE_FS_REG_COMM_MB_MUX_REAL 0x0
2445#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 2142#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4
2446 2143
2447
2448#define FE_FS_REG_COMM_SERVICE0__A 0xC30003 2144#define FE_FS_REG_COMM_SERVICE0__A 0xC30003
2449#define FE_FS_REG_COMM_SERVICE0__W 10 2145#define FE_FS_REG_COMM_SERVICE0__W 10
2450#define FE_FS_REG_COMM_SERVICE0__M 0x3FF 2146#define FE_FS_REG_COMM_SERVICE0__M 0x3FF
@@ -2466,35 +2162,23 @@ extern "C" {
2466#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF 2162#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF
2467#define FE_FS_REG_ADD_INC_LOP_INIT 0x0 2163#define FE_FS_REG_ADD_INC_LOP_INIT 0x0
2468 2164
2469
2470#define FE_FS_REG_ADD_INC_HIP__A 0xC30011 2165#define FE_FS_REG_ADD_INC_HIP__A 0xC30011
2471#define FE_FS_REG_ADD_INC_HIP__W 12 2166#define FE_FS_REG_ADD_INC_HIP__W 12
2472#define FE_FS_REG_ADD_INC_HIP__M 0xFFF 2167#define FE_FS_REG_ADD_INC_HIP__M 0xFFF
2473#define FE_FS_REG_ADD_INC_HIP_INIT 0x0 2168#define FE_FS_REG_ADD_INC_HIP_INIT 0x0
2474 2169
2475
2476#define FE_FS_REG_ADD_OFF__A 0xC30012 2170#define FE_FS_REG_ADD_OFF__A 0xC30012
2477#define FE_FS_REG_ADD_OFF__W 12 2171#define FE_FS_REG_ADD_OFF__W 12
2478#define FE_FS_REG_ADD_OFF__M 0xFFF 2172#define FE_FS_REG_ADD_OFF__M 0xFFF
2479#define FE_FS_REG_ADD_OFF_INIT 0x0 2173#define FE_FS_REG_ADD_OFF_INIT 0x0
2480 2174
2481
2482#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 2175#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013
2483#define FE_FS_REG_ADD_OFF_VAL__W 1 2176#define FE_FS_REG_ADD_OFF_VAL__W 1
2484#define FE_FS_REG_ADD_OFF_VAL__M 0x1 2177#define FE_FS_REG_ADD_OFF_VAL__M 0x1
2485#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 2178#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0
2486 2179
2487
2488
2489
2490
2491#define FE_FD_SID 0x4 2180#define FE_FD_SID 0x4
2492 2181
2493
2494
2495
2496
2497
2498#define FE_FD_REG_COMM_EXEC__A 0xC40000 2182#define FE_FD_REG_COMM_EXEC__A 0xC40000
2499#define FE_FD_REG_COMM_EXEC__W 3 2183#define FE_FD_REG_COMM_EXEC__W 3
2500#define FE_FD_REG_COMM_EXEC__M 0x7 2184#define FE_FD_REG_COMM_EXEC__M 0x7
@@ -2506,7 +2190,6 @@ extern "C" {
2506#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 2190#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2
2507#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 2191#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3
2508 2192
2509
2510#define FE_FD_REG_COMM_MB__A 0xC40002 2193#define FE_FD_REG_COMM_MB__A 0xC40002
2511#define FE_FD_REG_COMM_MB__W 3 2194#define FE_FD_REG_COMM_MB__W 3
2512#define FE_FD_REG_COMM_MB__M 0x7 2195#define FE_FD_REG_COMM_MB__M 0x7
@@ -2535,7 +2218,6 @@ extern "C" {
2535#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 2218#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1
2536#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 2219#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1
2537 2220
2538
2539#define FE_FD_REG_COMM_INT_MSK__A 0xC40008 2221#define FE_FD_REG_COMM_INT_MSK__A 0xC40008
2540#define FE_FD_REG_COMM_INT_MSK__W 1 2222#define FE_FD_REG_COMM_INT_MSK__W 1
2541#define FE_FD_REG_COMM_INT_MSK__M 0x1 2223#define FE_FD_REG_COMM_INT_MSK__M 0x1
@@ -2543,7 +2225,6 @@ extern "C" {
2543#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 2225#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1
2544#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 2226#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
2545 2227
2546
2547#define FE_FD_REG_SCL__A 0xC40010 2228#define FE_FD_REG_SCL__A 0xC40010
2548#define FE_FD_REG_SCL__W 6 2229#define FE_FD_REG_SCL__W 6
2549#define FE_FD_REG_SCL__M 0x3F 2230#define FE_FD_REG_SCL__M 0x3F
@@ -2572,17 +2253,8 @@ extern "C" {
2572#define FE_FD_REG_POWER__W 10 2253#define FE_FD_REG_POWER__W 10
2573#define FE_FD_REG_POWER__M 0x3FF 2254#define FE_FD_REG_POWER__M 0x3FF
2574 2255
2575
2576
2577
2578
2579#define FE_IF_SID 0x5 2256#define FE_IF_SID 0x5
2580 2257
2581
2582
2583
2584
2585
2586#define FE_IF_REG_COMM_EXEC__A 0xC50000 2258#define FE_IF_REG_COMM_EXEC__A 0xC50000
2587#define FE_IF_REG_COMM_EXEC__W 3 2259#define FE_IF_REG_COMM_EXEC__W 3
2588#define FE_IF_REG_COMM_EXEC__M 0x7 2260#define FE_IF_REG_COMM_EXEC__M 0x7
@@ -2594,7 +2266,6 @@ extern "C" {
2594#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 2266#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2
2595#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 2267#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3
2596 2268
2597
2598#define FE_IF_REG_COMM_MB__A 0xC50002 2269#define FE_IF_REG_COMM_MB__A 0xC50002
2599#define FE_IF_REG_COMM_MB__W 3 2270#define FE_IF_REG_COMM_MB__W 3
2600#define FE_IF_REG_COMM_MB__M 0x7 2271#define FE_IF_REG_COMM_MB__M 0x7
@@ -2609,29 +2280,18 @@ extern "C" {
2609#define FE_IF_REG_COMM_MB_OBS_OFF 0x0 2280#define FE_IF_REG_COMM_MB_OBS_OFF 0x0
2610#define FE_IF_REG_COMM_MB_OBS_ON 0x2 2281#define FE_IF_REG_COMM_MB_OBS_ON 0x2
2611 2282
2612
2613#define FE_IF_REG_INCR0__A 0xC50010 2283#define FE_IF_REG_INCR0__A 0xC50010
2614#define FE_IF_REG_INCR0__W 16 2284#define FE_IF_REG_INCR0__W 16
2615#define FE_IF_REG_INCR0__M 0xFFFF 2285#define FE_IF_REG_INCR0__M 0xFFFF
2616#define FE_IF_REG_INCR0_INIT 0x0 2286#define FE_IF_REG_INCR0_INIT 0x0
2617 2287
2618
2619#define FE_IF_REG_INCR1__A 0xC50011 2288#define FE_IF_REG_INCR1__A 0xC50011
2620#define FE_IF_REG_INCR1__W 8 2289#define FE_IF_REG_INCR1__W 8
2621#define FE_IF_REG_INCR1__M 0xFF 2290#define FE_IF_REG_INCR1__M 0xFF
2622#define FE_IF_REG_INCR1_INIT 0x28 2291#define FE_IF_REG_INCR1_INIT 0x28
2623 2292
2624
2625
2626
2627
2628#define FE_CF_SID 0x6 2293#define FE_CF_SID 0x6
2629 2294
2630
2631
2632
2633
2634
2635#define FE_CF_REG_COMM_EXEC__A 0xC60000 2295#define FE_CF_REG_COMM_EXEC__A 0xC60000
2636#define FE_CF_REG_COMM_EXEC__W 3 2296#define FE_CF_REG_COMM_EXEC__W 3
2637#define FE_CF_REG_COMM_EXEC__M 0x7 2297#define FE_CF_REG_COMM_EXEC__M 0x7
@@ -2643,7 +2303,6 @@ extern "C" {
2643#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 2303#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2
2644#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 2304#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3
2645 2305
2646
2647#define FE_CF_REG_COMM_MB__A 0xC60002 2306#define FE_CF_REG_COMM_MB__A 0xC60002
2648#define FE_CF_REG_COMM_MB__W 3 2307#define FE_CF_REG_COMM_MB__W 3
2649#define FE_CF_REG_COMM_MB__M 0x7 2308#define FE_CF_REG_COMM_MB__M 0x7
@@ -2672,7 +2331,6 @@ extern "C" {
2672#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 2331#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1
2673#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 2332#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1
2674 2333
2675
2676#define FE_CF_REG_COMM_INT_MSK__A 0xC60008 2334#define FE_CF_REG_COMM_INT_MSK__A 0xC60008
2677#define FE_CF_REG_COMM_INT_MSK__W 2 2335#define FE_CF_REG_COMM_INT_MSK__W 2
2678#define FE_CF_REG_COMM_INT_MSK__M 0x3 2336#define FE_CF_REG_COMM_INT_MSK__M 0x3
@@ -2680,7 +2338,6 @@ extern "C" {
2680#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 2338#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1
2681#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 2339#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
2682 2340
2683
2684#define FE_CF_REG_SCL__A 0xC60010 2341#define FE_CF_REG_SCL__A 0xC60010
2685#define FE_CF_REG_SCL__W 9 2342#define FE_CF_REG_SCL__W 9
2686#define FE_CF_REG_SCL__M 0x1FF 2343#define FE_CF_REG_SCL__M 0x1FF
@@ -2709,17 +2366,8 @@ extern "C" {
2709#define FE_CF_REG_POWER__W 10 2366#define FE_CF_REG_POWER__W 10
2710#define FE_CF_REG_POWER__M 0x3FF 2367#define FE_CF_REG_POWER__M 0x3FF
2711 2368
2712
2713
2714
2715
2716#define FE_CU_SID 0x7 2369#define FE_CU_SID 0x7
2717 2370
2718
2719
2720
2721
2722
2723#define FE_CU_REG_COMM_EXEC__A 0xC70000 2371#define FE_CU_REG_COMM_EXEC__A 0xC70000
2724#define FE_CU_REG_COMM_EXEC__W 3 2372#define FE_CU_REG_COMM_EXEC__W 3
2725#define FE_CU_REG_COMM_EXEC__M 0x7 2373#define FE_CU_REG_COMM_EXEC__M 0x7
@@ -2754,7 +2402,6 @@ extern "C" {
2754#define FE_CU_REG_COMM_MB_MUX_REAL 0x0 2402#define FE_CU_REG_COMM_MB_MUX_REAL 0x0
2755#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 2403#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4
2756 2404
2757
2758#define FE_CU_REG_COMM_SERVICE0__A 0xC70003 2405#define FE_CU_REG_COMM_SERVICE0__A 0xC70003
2759#define FE_CU_REG_COMM_SERVICE0__W 10 2406#define FE_CU_REG_COMM_SERVICE0__W 10
2760#define FE_CU_REG_COMM_SERVICE0__M 0x3FF 2407#define FE_CU_REG_COMM_SERVICE0__M 0x3FF
@@ -2781,7 +2428,6 @@ extern "C" {
2781#define FE_CU_REG_COMM_INT_STA_FT_START__W 1 2428#define FE_CU_REG_COMM_INT_STA_FT_START__W 1
2782#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 2429#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2
2783 2430
2784
2785#define FE_CU_REG_COMM_INT_MSK__A 0xC70008 2431#define FE_CU_REG_COMM_INT_MSK__A 0xC70008
2786#define FE_CU_REG_COMM_INT_MSK__W 2 2432#define FE_CU_REG_COMM_INT_MSK__W 2
2787#define FE_CU_REG_COMM_INT_MSK__M 0x3 2433#define FE_CU_REG_COMM_INT_MSK__M 0x3
@@ -2792,7 +2438,6 @@ extern "C" {
2792#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 2438#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1
2793#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 2439#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2
2794 2440
2795
2796#define FE_CU_REG_MODE__A 0xC70010 2441#define FE_CU_REG_MODE__A 0xC70010
2797#define FE_CU_REG_MODE__W 3 2442#define FE_CU_REG_MODE__W 3
2798#define FE_CU_REG_MODE__M 0x7 2443#define FE_CU_REG_MODE__M 0x7
@@ -2816,19 +2461,16 @@ extern "C" {
2816#define FE_CU_REG_MODE_IFD_ENABLE 0x0 2461#define FE_CU_REG_MODE_IFD_ENABLE 0x0
2817#define FE_CU_REG_MODE_IFD_DISABLE 0x4 2462#define FE_CU_REG_MODE_IFD_DISABLE 0x4
2818 2463
2819
2820#define FE_CU_REG_FRM_CNT_RST__A 0xC70011 2464#define FE_CU_REG_FRM_CNT_RST__A 0xC70011
2821#define FE_CU_REG_FRM_CNT_RST__W 15 2465#define FE_CU_REG_FRM_CNT_RST__W 15
2822#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF 2466#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF
2823#define FE_CU_REG_FRM_CNT_RST_INIT 0x0 2467#define FE_CU_REG_FRM_CNT_RST_INIT 0x0
2824 2468
2825
2826#define FE_CU_REG_FRM_CNT_STR__A 0xC70012 2469#define FE_CU_REG_FRM_CNT_STR__A 0xC70012
2827#define FE_CU_REG_FRM_CNT_STR__W 15 2470#define FE_CU_REG_FRM_CNT_STR__W 15
2828#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF 2471#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF
2829#define FE_CU_REG_FRM_CNT_STR_INIT 0x0 2472#define FE_CU_REG_FRM_CNT_STR_INIT 0x0
2830 2473
2831
2832#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 2474#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013
2833#define FE_CU_REG_FRM_SMP_CNT__W 15 2475#define FE_CU_REG_FRM_SMP_CNT__W 15
2834#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF 2476#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF
@@ -2850,25 +2492,21 @@ extern "C" {
2850#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF 2492#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF
2851#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 2493#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0
2852 2494
2853
2854#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 2495#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018
2855#define FE_CU_REG_CTR_NF1_WHI__W 15 2496#define FE_CU_REG_CTR_NF1_WHI__W 15
2856#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF 2497#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF
2857#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 2498#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0
2858 2499
2859
2860#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 2500#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019
2861#define FE_CU_REG_CTR_NF2_WLO__W 15 2501#define FE_CU_REG_CTR_NF2_WLO__W 15
2862#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF 2502#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF
2863#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 2503#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0
2864 2504
2865
2866#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A 2505#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A
2867#define FE_CU_REG_CTR_NF2_WHI__W 15 2506#define FE_CU_REG_CTR_NF2_WHI__W 15
2868#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF 2507#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF
2869#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 2508#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0
2870 2509
2871
2872#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B 2510#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B
2873#define FE_CU_REG_DIV_NF1_REA__W 12 2511#define FE_CU_REG_DIV_NF1_REA__W 12
2874#define FE_CU_REG_DIV_NF1_REA__M 0xFFF 2512#define FE_CU_REG_DIV_NF1_REA__M 0xFFF
@@ -2885,24 +2523,12 @@ extern "C" {
2885#define FE_CU_REG_DIV_NF2_IMA__W 12 2523#define FE_CU_REG_DIV_NF2_IMA__W 12
2886#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF 2524#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF
2887 2525
2888
2889
2890#define FE_CU_BUF_RAM__A 0xC80000 2526#define FE_CU_BUF_RAM__A 0xC80000
2891 2527
2892
2893
2894#define FE_CU_CMP_RAM__A 0xC90000 2528#define FE_CU_CMP_RAM__A 0xC90000
2895 2529
2896
2897
2898
2899
2900#define FT_SID 0x8 2530#define FT_SID 0x8
2901 2531
2902
2903
2904
2905
2906#define FT_COMM_EXEC__A 0x1000000 2532#define FT_COMM_EXEC__A 0x1000000
2907#define FT_COMM_EXEC__W 3 2533#define FT_COMM_EXEC__W 3
2908#define FT_COMM_EXEC__M 0x7 2534#define FT_COMM_EXEC__M 0x7
@@ -2935,11 +2561,6 @@ extern "C" {
2935#define FT_COMM_INT_MSK__W 16 2561#define FT_COMM_INT_MSK__W 16
2936#define FT_COMM_INT_MSK__M 0xFFFF 2562#define FT_COMM_INT_MSK__M 0xFFFF
2937 2563
2938
2939
2940
2941
2942
2943#define FT_REG_COMM_EXEC__A 0x1010000 2564#define FT_REG_COMM_EXEC__A 0x1010000
2944#define FT_REG_COMM_EXEC__W 3 2565#define FT_REG_COMM_EXEC__W 3
2945#define FT_REG_COMM_EXEC__M 0x7 2566#define FT_REG_COMM_EXEC__M 0x7
@@ -2951,7 +2572,6 @@ extern "C" {
2951#define FT_REG_COMM_EXEC_CTL_HOLD 0x2 2572#define FT_REG_COMM_EXEC_CTL_HOLD 0x2
2952#define FT_REG_COMM_EXEC_CTL_STEP 0x3 2573#define FT_REG_COMM_EXEC_CTL_STEP 0x3
2953 2574
2954
2955#define FT_REG_COMM_MB__A 0x1010002 2575#define FT_REG_COMM_MB__A 0x1010002
2956#define FT_REG_COMM_MB__W 3 2576#define FT_REG_COMM_MB__W 3
2957#define FT_REG_COMM_MB__M 0x7 2577#define FT_REG_COMM_MB__M 0x7
@@ -2984,7 +2604,6 @@ extern "C" {
2984#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 2604#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1
2985#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 2605#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1
2986 2606
2987
2988#define FT_REG_COMM_INT_MSK__A 0x1010008 2607#define FT_REG_COMM_INT_MSK__A 0x1010008
2989#define FT_REG_COMM_INT_MSK__W 2 2608#define FT_REG_COMM_INT_MSK__W 2
2990#define FT_REG_COMM_INT_MSK__M 0x3 2609#define FT_REG_COMM_INT_MSK__M 0x3
@@ -2992,7 +2611,6 @@ extern "C" {
2992#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 2611#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1
2993#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 2612#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
2994 2613
2995
2996#define FT_REG_MODE_2K__A 0x1010010 2614#define FT_REG_MODE_2K__A 0x1010010
2997#define FT_REG_MODE_2K__W 1 2615#define FT_REG_MODE_2K__W 1
2998#define FT_REG_MODE_2K__M 0x1 2616#define FT_REG_MODE_2K__M 0x1
@@ -3000,7 +2618,6 @@ extern "C" {
3000#define FT_REG_MODE_2K_MODE_2K 0x1 2618#define FT_REG_MODE_2K_MODE_2K 0x1
3001#define FT_REG_MODE_2K_INIT 0x0 2619#define FT_REG_MODE_2K_INIT 0x0
3002 2620
3003
3004#define FT_REG_BUS_MOD__A 0x1010011 2621#define FT_REG_BUS_MOD__A 0x1010011
3005#define FT_REG_BUS_MOD__W 1 2622#define FT_REG_BUS_MOD__W 1
3006#define FT_REG_BUS_MOD__M 0x1 2623#define FT_REG_BUS_MOD__M 0x1
@@ -3008,74 +2625,47 @@ extern "C" {
3008#define FT_REG_BUS_MOD_PILOT 0x1 2625#define FT_REG_BUS_MOD_PILOT 0x1
3009#define FT_REG_BUS_MOD_INIT 0x0 2626#define FT_REG_BUS_MOD_INIT 0x0
3010 2627
3011
3012#define FT_REG_BUS_REAL__A 0x1010012 2628#define FT_REG_BUS_REAL__A 0x1010012
3013#define FT_REG_BUS_REAL__W 10 2629#define FT_REG_BUS_REAL__W 10
3014#define FT_REG_BUS_REAL__M 0x3FF 2630#define FT_REG_BUS_REAL__M 0x3FF
3015#define FT_REG_BUS_REAL_INIT 0x0 2631#define FT_REG_BUS_REAL_INIT 0x0
3016 2632
3017
3018#define FT_REG_BUS_IMAG__A 0x1010013 2633#define FT_REG_BUS_IMAG__A 0x1010013
3019#define FT_REG_BUS_IMAG__W 10 2634#define FT_REG_BUS_IMAG__W 10
3020#define FT_REG_BUS_IMAG__M 0x3FF 2635#define FT_REG_BUS_IMAG__M 0x3FF
3021#define FT_REG_BUS_IMAG_INIT 0x0 2636#define FT_REG_BUS_IMAG_INIT 0x0
3022 2637
3023
3024#define FT_REG_BUS_VAL__A 0x1010014 2638#define FT_REG_BUS_VAL__A 0x1010014
3025#define FT_REG_BUS_VAL__W 1 2639#define FT_REG_BUS_VAL__W 1
3026#define FT_REG_BUS_VAL__M 0x1 2640#define FT_REG_BUS_VAL__M 0x1
3027#define FT_REG_BUS_VAL_INIT 0x0 2641#define FT_REG_BUS_VAL_INIT 0x0
3028 2642
3029
3030#define FT_REG_PEAK__A 0x1010015 2643#define FT_REG_PEAK__A 0x1010015
3031#define FT_REG_PEAK__W 11 2644#define FT_REG_PEAK__W 11
3032#define FT_REG_PEAK__M 0x7FF 2645#define FT_REG_PEAK__M 0x7FF
3033#define FT_REG_PEAK_INIT 0x0 2646#define FT_REG_PEAK_INIT 0x0
3034 2647
3035
3036#define FT_REG_NORM_OFF__A 0x1010016 2648#define FT_REG_NORM_OFF__A 0x1010016
3037#define FT_REG_NORM_OFF__W 4 2649#define FT_REG_NORM_OFF__W 4
3038#define FT_REG_NORM_OFF__M 0xF 2650#define FT_REG_NORM_OFF__M 0xF
3039#define FT_REG_NORM_OFF_INIT 0x2 2651#define FT_REG_NORM_OFF_INIT 0x2
3040 2652
3041
3042
3043#define FT_ST1_RAM__A 0x1020000 2653#define FT_ST1_RAM__A 0x1020000
3044 2654
3045
3046
3047#define FT_ST2_RAM__A 0x1030000 2655#define FT_ST2_RAM__A 0x1030000
3048 2656
3049
3050
3051#define FT_ST3_RAM__A 0x1040000 2657#define FT_ST3_RAM__A 0x1040000
3052 2658
3053
3054
3055#define FT_ST5_RAM__A 0x1050000 2659#define FT_ST5_RAM__A 0x1050000
3056 2660
3057
3058
3059#define FT_ST6_RAM__A 0x1060000 2661#define FT_ST6_RAM__A 0x1060000
3060 2662
3061
3062
3063#define FT_ST8_RAM__A 0x1070000 2663#define FT_ST8_RAM__A 0x1070000
3064 2664
3065
3066
3067#define FT_ST9_RAM__A 0x1080000 2665#define FT_ST9_RAM__A 0x1080000
3068 2666
3069
3070
3071
3072
3073#define CP_SID 0x9 2667#define CP_SID 0x9
3074 2668
3075
3076
3077
3078
3079#define CP_COMM_EXEC__A 0x1400000 2669#define CP_COMM_EXEC__A 0x1400000
3080#define CP_COMM_EXEC__W 3 2670#define CP_COMM_EXEC__W 3
3081#define CP_COMM_EXEC__M 0x7 2671#define CP_COMM_EXEC__M 0x7
@@ -3108,11 +2698,6 @@ extern "C" {
3108#define CP_COMM_INT_MSK__W 16 2698#define CP_COMM_INT_MSK__W 16
3109#define CP_COMM_INT_MSK__M 0xFFFF 2699#define CP_COMM_INT_MSK__M 0xFFFF
3110 2700
3111
3112
3113
3114
3115
3116#define CP_REG_COMM_EXEC__A 0x1410000 2701#define CP_REG_COMM_EXEC__A 0x1410000
3117#define CP_REG_COMM_EXEC__W 3 2702#define CP_REG_COMM_EXEC__W 3
3118#define CP_REG_COMM_EXEC__M 0x7 2703#define CP_REG_COMM_EXEC__M 0x7
@@ -3124,7 +2709,6 @@ extern "C" {
3124#define CP_REG_COMM_EXEC_CTL_HOLD 0x2 2709#define CP_REG_COMM_EXEC_CTL_HOLD 0x2
3125#define CP_REG_COMM_EXEC_CTL_STEP 0x3 2710#define CP_REG_COMM_EXEC_CTL_STEP 0x3
3126 2711
3127
3128#define CP_REG_COMM_MB__A 0x1410002 2712#define CP_REG_COMM_MB__A 0x1410002
3129#define CP_REG_COMM_MB__W 3 2713#define CP_REG_COMM_MB__W 3
3130#define CP_REG_COMM_MB__M 0x7 2714#define CP_REG_COMM_MB__M 0x7
@@ -3157,7 +2741,6 @@ extern "C" {
3157#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 2741#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1
3158#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 2742#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1
3159 2743
3160
3161#define CP_REG_COMM_INT_MSK__A 0x1410008 2744#define CP_REG_COMM_INT_MSK__A 0x1410008
3162#define CP_REG_COMM_INT_MSK__W 2 2745#define CP_REG_COMM_INT_MSK__W 2
3163#define CP_REG_COMM_INT_MSK__M 0x3 2746#define CP_REG_COMM_INT_MSK__M 0x3
@@ -3165,55 +2748,46 @@ extern "C" {
3165#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 2748#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1
3166#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 2749#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
3167 2750
3168
3169#define CP_REG_MODE_2K__A 0x1410010 2751#define CP_REG_MODE_2K__A 0x1410010
3170#define CP_REG_MODE_2K__W 1 2752#define CP_REG_MODE_2K__W 1
3171#define CP_REG_MODE_2K__M 0x1 2753#define CP_REG_MODE_2K__M 0x1
3172#define CP_REG_MODE_2K_INIT 0x0 2754#define CP_REG_MODE_2K_INIT 0x0
3173 2755
3174
3175#define CP_REG_INTERVAL__A 0x1410011 2756#define CP_REG_INTERVAL__A 0x1410011
3176#define CP_REG_INTERVAL__W 4 2757#define CP_REG_INTERVAL__W 4
3177#define CP_REG_INTERVAL__M 0xF 2758#define CP_REG_INTERVAL__M 0xF
3178#define CP_REG_INTERVAL_INIT 0x5 2759#define CP_REG_INTERVAL_INIT 0x5
3179 2760
3180
3181#define CP_REG_SKIP_START0__A 0x1410012 2761#define CP_REG_SKIP_START0__A 0x1410012
3182#define CP_REG_SKIP_START0__W 13 2762#define CP_REG_SKIP_START0__W 13
3183#define CP_REG_SKIP_START0__M 0x1FFF 2763#define CP_REG_SKIP_START0__M 0x1FFF
3184#define CP_REG_SKIP_START0_INIT 0x0 2764#define CP_REG_SKIP_START0_INIT 0x0
3185 2765
3186
3187#define CP_REG_SKIP_STOP0__A 0x1410013 2766#define CP_REG_SKIP_STOP0__A 0x1410013
3188#define CP_REG_SKIP_STOP0__W 13 2767#define CP_REG_SKIP_STOP0__W 13
3189#define CP_REG_SKIP_STOP0__M 0x1FFF 2768#define CP_REG_SKIP_STOP0__M 0x1FFF
3190#define CP_REG_SKIP_STOP0_INIT 0x0 2769#define CP_REG_SKIP_STOP0_INIT 0x0
3191 2770
3192
3193#define CP_REG_SKIP_START1__A 0x1410014 2771#define CP_REG_SKIP_START1__A 0x1410014
3194#define CP_REG_SKIP_START1__W 13 2772#define CP_REG_SKIP_START1__W 13
3195#define CP_REG_SKIP_START1__M 0x1FFF 2773#define CP_REG_SKIP_START1__M 0x1FFF
3196#define CP_REG_SKIP_START1_INIT 0x0 2774#define CP_REG_SKIP_START1_INIT 0x0
3197 2775
3198
3199#define CP_REG_SKIP_STOP1__A 0x1410015 2776#define CP_REG_SKIP_STOP1__A 0x1410015
3200#define CP_REG_SKIP_STOP1__W 13 2777#define CP_REG_SKIP_STOP1__W 13
3201#define CP_REG_SKIP_STOP1__M 0x1FFF 2778#define CP_REG_SKIP_STOP1__M 0x1FFF
3202#define CP_REG_SKIP_STOP1_INIT 0x0 2779#define CP_REG_SKIP_STOP1_INIT 0x0
3203 2780
3204
3205#define CP_REG_SKIP_START2__A 0x1410016 2781#define CP_REG_SKIP_START2__A 0x1410016
3206#define CP_REG_SKIP_START2__W 13 2782#define CP_REG_SKIP_START2__W 13
3207#define CP_REG_SKIP_START2__M 0x1FFF 2783#define CP_REG_SKIP_START2__M 0x1FFF
3208#define CP_REG_SKIP_START2_INIT 0x0 2784#define CP_REG_SKIP_START2_INIT 0x0
3209 2785
3210
3211#define CP_REG_SKIP_STOP2__A 0x1410017 2786#define CP_REG_SKIP_STOP2__A 0x1410017
3212#define CP_REG_SKIP_STOP2__W 13 2787#define CP_REG_SKIP_STOP2__W 13
3213#define CP_REG_SKIP_STOP2__M 0x1FFF 2788#define CP_REG_SKIP_STOP2__M 0x1FFF
3214#define CP_REG_SKIP_STOP2_INIT 0x0 2789#define CP_REG_SKIP_STOP2_INIT 0x0
3215 2790
3216
3217#define CP_REG_SKIP_ENA__A 0x1410018 2791#define CP_REG_SKIP_ENA__A 0x1410018
3218#define CP_REG_SKIP_ENA__W 3 2792#define CP_REG_SKIP_ENA__W 3
3219#define CP_REG_SKIP_ENA__M 0x7 2793#define CP_REG_SKIP_ENA__M 0x7
@@ -3231,13 +2805,11 @@ extern "C" {
3231#define CP_REG_SKIP_ENA_CPD__M 0x4 2805#define CP_REG_SKIP_ENA_CPD__M 0x4
3232#define CP_REG_SKIP_ENA_INIT 0x0 2806#define CP_REG_SKIP_ENA_INIT 0x0
3233 2807
3234
3235#define CP_REG_BR_MODE_MIX__A 0x1410020 2808#define CP_REG_BR_MODE_MIX__A 0x1410020
3236#define CP_REG_BR_MODE_MIX__W 1 2809#define CP_REG_BR_MODE_MIX__W 1
3237#define CP_REG_BR_MODE_MIX__M 0x1 2810#define CP_REG_BR_MODE_MIX__M 0x1
3238#define CP_REG_BR_MODE_MIX_INIT 0x0 2811#define CP_REG_BR_MODE_MIX_INIT 0x0
3239 2812
3240
3241#define CP_REG_BR_SMB_NR__A 0x1410021 2813#define CP_REG_BR_SMB_NR__A 0x1410021
3242#define CP_REG_BR_SMB_NR__W 3 2814#define CP_REG_BR_SMB_NR__W 3
3243#define CP_REG_BR_SMB_NR__M 0x7 2815#define CP_REG_BR_SMB_NR__M 0x7
@@ -3251,37 +2823,31 @@ extern "C" {
3251#define CP_REG_BR_SMB_NR_VAL__M 0x4 2823#define CP_REG_BR_SMB_NR_VAL__M 0x4
3252#define CP_REG_BR_SMB_NR_INIT 0x0 2824#define CP_REG_BR_SMB_NR_INIT 0x0
3253 2825
3254
3255#define CP_REG_BR_CP_SMB_NR__A 0x1410022 2826#define CP_REG_BR_CP_SMB_NR__A 0x1410022
3256#define CP_REG_BR_CP_SMB_NR__W 2 2827#define CP_REG_BR_CP_SMB_NR__W 2
3257#define CP_REG_BR_CP_SMB_NR__M 0x3 2828#define CP_REG_BR_CP_SMB_NR__M 0x3
3258#define CP_REG_BR_CP_SMB_NR_INIT 0x0 2829#define CP_REG_BR_CP_SMB_NR_INIT 0x0
3259 2830
3260
3261#define CP_REG_BR_SPL_OFFSET__A 0x1410023 2831#define CP_REG_BR_SPL_OFFSET__A 0x1410023
3262#define CP_REG_BR_SPL_OFFSET__W 3 2832#define CP_REG_BR_SPL_OFFSET__W 3
3263#define CP_REG_BR_SPL_OFFSET__M 0x7 2833#define CP_REG_BR_SPL_OFFSET__M 0x7
3264#define CP_REG_BR_SPL_OFFSET_INIT 0x0 2834#define CP_REG_BR_SPL_OFFSET_INIT 0x0
3265 2835
3266
3267#define CP_REG_BR_STR_DEL__A 0x1410024 2836#define CP_REG_BR_STR_DEL__A 0x1410024
3268#define CP_REG_BR_STR_DEL__W 10 2837#define CP_REG_BR_STR_DEL__W 10
3269#define CP_REG_BR_STR_DEL__M 0x3FF 2838#define CP_REG_BR_STR_DEL__M 0x3FF
3270#define CP_REG_BR_STR_DEL_INIT 0xA 2839#define CP_REG_BR_STR_DEL_INIT 0xA
3271 2840
3272
3273#define CP_REG_RT_ANG_INC0__A 0x1410030 2841#define CP_REG_RT_ANG_INC0__A 0x1410030
3274#define CP_REG_RT_ANG_INC0__W 16 2842#define CP_REG_RT_ANG_INC0__W 16
3275#define CP_REG_RT_ANG_INC0__M 0xFFFF 2843#define CP_REG_RT_ANG_INC0__M 0xFFFF
3276#define CP_REG_RT_ANG_INC0_INIT 0x0 2844#define CP_REG_RT_ANG_INC0_INIT 0x0
3277 2845
3278
3279#define CP_REG_RT_ANG_INC1__A 0x1410031 2846#define CP_REG_RT_ANG_INC1__A 0x1410031
3280#define CP_REG_RT_ANG_INC1__W 8 2847#define CP_REG_RT_ANG_INC1__W 8
3281#define CP_REG_RT_ANG_INC1__M 0xFF 2848#define CP_REG_RT_ANG_INC1__M 0xFF
3282#define CP_REG_RT_ANG_INC1_INIT 0x0 2849#define CP_REG_RT_ANG_INC1_INIT 0x0
3283 2850
3284
3285#define CP_REG_RT_DETECT_ENA__A 0x1410032 2851#define CP_REG_RT_DETECT_ENA__A 0x1410032
3286#define CP_REG_RT_DETECT_ENA__W 2 2852#define CP_REG_RT_DETECT_ENA__W 2
3287#define CP_REG_RT_DETECT_ENA__M 0x3 2853#define CP_REG_RT_DETECT_ENA__M 0x3
@@ -3295,37 +2861,31 @@ extern "C" {
3295#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 2861#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2
3296#define CP_REG_RT_DETECT_ENA_INIT 0x0 2862#define CP_REG_RT_DETECT_ENA_INIT 0x0
3297 2863
3298
3299#define CP_REG_RT_DETECT_TRH__A 0x1410033 2864#define CP_REG_RT_DETECT_TRH__A 0x1410033
3300#define CP_REG_RT_DETECT_TRH__W 2 2865#define CP_REG_RT_DETECT_TRH__W 2
3301#define CP_REG_RT_DETECT_TRH__M 0x3 2866#define CP_REG_RT_DETECT_TRH__M 0x3
3302#define CP_REG_RT_DETECT_TRH_INIT 0x3 2867#define CP_REG_RT_DETECT_TRH_INIT 0x3
3303 2868
3304
3305#define CP_REG_RT_SPD_RELIABLE__A 0x1410034 2869#define CP_REG_RT_SPD_RELIABLE__A 0x1410034
3306#define CP_REG_RT_SPD_RELIABLE__W 3 2870#define CP_REG_RT_SPD_RELIABLE__W 3
3307#define CP_REG_RT_SPD_RELIABLE__M 0x7 2871#define CP_REG_RT_SPD_RELIABLE__M 0x7
3308#define CP_REG_RT_SPD_RELIABLE_INIT 0x0 2872#define CP_REG_RT_SPD_RELIABLE_INIT 0x0
3309 2873
3310
3311#define CP_REG_RT_SPD_DIRECTION__A 0x1410035 2874#define CP_REG_RT_SPD_DIRECTION__A 0x1410035
3312#define CP_REG_RT_SPD_DIRECTION__W 1 2875#define CP_REG_RT_SPD_DIRECTION__W 1
3313#define CP_REG_RT_SPD_DIRECTION__M 0x1 2876#define CP_REG_RT_SPD_DIRECTION__M 0x1
3314#define CP_REG_RT_SPD_DIRECTION_INIT 0x0 2877#define CP_REG_RT_SPD_DIRECTION_INIT 0x0
3315 2878
3316
3317#define CP_REG_RT_SPD_MOD__A 0x1410036 2879#define CP_REG_RT_SPD_MOD__A 0x1410036
3318#define CP_REG_RT_SPD_MOD__W 2 2880#define CP_REG_RT_SPD_MOD__W 2
3319#define CP_REG_RT_SPD_MOD__M 0x3 2881#define CP_REG_RT_SPD_MOD__M 0x3
3320#define CP_REG_RT_SPD_MOD_INIT 0x0 2882#define CP_REG_RT_SPD_MOD_INIT 0x0
3321 2883
3322
3323#define CP_REG_RT_SPD_SMB__A 0x1410037 2884#define CP_REG_RT_SPD_SMB__A 0x1410037
3324#define CP_REG_RT_SPD_SMB__W 2 2885#define CP_REG_RT_SPD_SMB__W 2
3325#define CP_REG_RT_SPD_SMB__M 0x3 2886#define CP_REG_RT_SPD_SMB__M 0x3
3326#define CP_REG_RT_SPD_SMB_INIT 0x0 2887#define CP_REG_RT_SPD_SMB_INIT 0x0
3327 2888
3328
3329#define CP_REG_RT_CPD_MODE__A 0x1410038 2889#define CP_REG_RT_CPD_MODE__A 0x1410038
3330#define CP_REG_RT_CPD_MODE__W 3 2890#define CP_REG_RT_CPD_MODE__W 3
3331#define CP_REG_RT_CPD_MODE__M 0x7 2891#define CP_REG_RT_CPD_MODE__M 0x7
@@ -3339,25 +2899,21 @@ extern "C" {
3339#define CP_REG_RT_CPD_MODE_ADD__M 0x4 2899#define CP_REG_RT_CPD_MODE_ADD__M 0x4
3340#define CP_REG_RT_CPD_MODE_INIT 0x0 2900#define CP_REG_RT_CPD_MODE_INIT 0x0
3341 2901
3342
3343#define CP_REG_RT_CPD_RELIABLE__A 0x1410039 2902#define CP_REG_RT_CPD_RELIABLE__A 0x1410039
3344#define CP_REG_RT_CPD_RELIABLE__W 3 2903#define CP_REG_RT_CPD_RELIABLE__W 3
3345#define CP_REG_RT_CPD_RELIABLE__M 0x7 2904#define CP_REG_RT_CPD_RELIABLE__M 0x7
3346#define CP_REG_RT_CPD_RELIABLE_INIT 0x0 2905#define CP_REG_RT_CPD_RELIABLE_INIT 0x0
3347 2906
3348
3349#define CP_REG_RT_CPD_BIN__A 0x141003A 2907#define CP_REG_RT_CPD_BIN__A 0x141003A
3350#define CP_REG_RT_CPD_BIN__W 5 2908#define CP_REG_RT_CPD_BIN__W 5
3351#define CP_REG_RT_CPD_BIN__M 0x1F 2909#define CP_REG_RT_CPD_BIN__M 0x1F
3352#define CP_REG_RT_CPD_BIN_INIT 0x0 2910#define CP_REG_RT_CPD_BIN_INIT 0x0
3353 2911
3354
3355#define CP_REG_RT_CPD_MAX__A 0x141003B 2912#define CP_REG_RT_CPD_MAX__A 0x141003B
3356#define CP_REG_RT_CPD_MAX__W 4 2913#define CP_REG_RT_CPD_MAX__W 4
3357#define CP_REG_RT_CPD_MAX__M 0xF 2914#define CP_REG_RT_CPD_MAX__M 0xF
3358#define CP_REG_RT_CPD_MAX_INIT 0x0 2915#define CP_REG_RT_CPD_MAX_INIT 0x0
3359 2916
3360
3361#define CP_REG_RT_SUPR_VAL__A 0x141003C 2917#define CP_REG_RT_SUPR_VAL__A 0x141003C
3362#define CP_REG_RT_SUPR_VAL__W 2 2918#define CP_REG_RT_SUPR_VAL__W 2
3363#define CP_REG_RT_SUPR_VAL__M 0x3 2919#define CP_REG_RT_SUPR_VAL__M 0x3
@@ -3371,61 +2927,51 @@ extern "C" {
3371#define CP_REG_RT_SUPR_VAL_DL__M 0x2 2927#define CP_REG_RT_SUPR_VAL_DL__M 0x2
3372#define CP_REG_RT_SUPR_VAL_INIT 0x0 2928#define CP_REG_RT_SUPR_VAL_INIT 0x0
3373 2929
3374
3375#define CP_REG_RT_EXP_AVE__A 0x141003D 2930#define CP_REG_RT_EXP_AVE__A 0x141003D
3376#define CP_REG_RT_EXP_AVE__W 5 2931#define CP_REG_RT_EXP_AVE__W 5
3377#define CP_REG_RT_EXP_AVE__M 0x1F 2932#define CP_REG_RT_EXP_AVE__M 0x1F
3378#define CP_REG_RT_EXP_AVE_INIT 0x0 2933#define CP_REG_RT_EXP_AVE_INIT 0x0
3379 2934
3380
3381#define CP_REG_RT_EXP_MARG__A 0x141003E 2935#define CP_REG_RT_EXP_MARG__A 0x141003E
3382#define CP_REG_RT_EXP_MARG__W 5 2936#define CP_REG_RT_EXP_MARG__W 5
3383#define CP_REG_RT_EXP_MARG__M 0x1F 2937#define CP_REG_RT_EXP_MARG__M 0x1F
3384#define CP_REG_RT_EXP_MARG_INIT 0x0 2938#define CP_REG_RT_EXP_MARG_INIT 0x0
3385 2939
3386
3387#define CP_REG_AC_NEXP_OFFS__A 0x1410040 2940#define CP_REG_AC_NEXP_OFFS__A 0x1410040
3388#define CP_REG_AC_NEXP_OFFS__W 8 2941#define CP_REG_AC_NEXP_OFFS__W 8
3389#define CP_REG_AC_NEXP_OFFS__M 0xFF 2942#define CP_REG_AC_NEXP_OFFS__M 0xFF
3390#define CP_REG_AC_NEXP_OFFS_INIT 0x0 2943#define CP_REG_AC_NEXP_OFFS_INIT 0x0
3391 2944
3392
3393#define CP_REG_AC_AVER_POW__A 0x1410041 2945#define CP_REG_AC_AVER_POW__A 0x1410041
3394#define CP_REG_AC_AVER_POW__W 8 2946#define CP_REG_AC_AVER_POW__W 8
3395#define CP_REG_AC_AVER_POW__M 0xFF 2947#define CP_REG_AC_AVER_POW__M 0xFF
3396#define CP_REG_AC_AVER_POW_INIT 0x5F 2948#define CP_REG_AC_AVER_POW_INIT 0x5F
3397 2949
3398
3399#define CP_REG_AC_MAX_POW__A 0x1410042 2950#define CP_REG_AC_MAX_POW__A 0x1410042
3400#define CP_REG_AC_MAX_POW__W 8 2951#define CP_REG_AC_MAX_POW__W 8
3401#define CP_REG_AC_MAX_POW__M 0xFF 2952#define CP_REG_AC_MAX_POW__M 0xFF
3402#define CP_REG_AC_MAX_POW_INIT 0x7A 2953#define CP_REG_AC_MAX_POW_INIT 0x7A
3403 2954
3404
3405#define CP_REG_AC_WEIGHT_MAN__A 0x1410043 2955#define CP_REG_AC_WEIGHT_MAN__A 0x1410043
3406#define CP_REG_AC_WEIGHT_MAN__W 6 2956#define CP_REG_AC_WEIGHT_MAN__W 6
3407#define CP_REG_AC_WEIGHT_MAN__M 0x3F 2957#define CP_REG_AC_WEIGHT_MAN__M 0x3F
3408#define CP_REG_AC_WEIGHT_MAN_INIT 0x31 2958#define CP_REG_AC_WEIGHT_MAN_INIT 0x31
3409 2959
3410
3411#define CP_REG_AC_WEIGHT_EXP__A 0x1410044 2960#define CP_REG_AC_WEIGHT_EXP__A 0x1410044
3412#define CP_REG_AC_WEIGHT_EXP__W 5 2961#define CP_REG_AC_WEIGHT_EXP__W 5
3413#define CP_REG_AC_WEIGHT_EXP__M 0x1F 2962#define CP_REG_AC_WEIGHT_EXP__M 0x1F
3414#define CP_REG_AC_WEIGHT_EXP_INIT 0x10 2963#define CP_REG_AC_WEIGHT_EXP_INIT 0x10
3415 2964
3416
3417#define CP_REG_AC_GAIN_MAN__A 0x1410045 2965#define CP_REG_AC_GAIN_MAN__A 0x1410045
3418#define CP_REG_AC_GAIN_MAN__W 16 2966#define CP_REG_AC_GAIN_MAN__W 16
3419#define CP_REG_AC_GAIN_MAN__M 0xFFFF 2967#define CP_REG_AC_GAIN_MAN__M 0xFFFF
3420#define CP_REG_AC_GAIN_MAN_INIT 0x0 2968#define CP_REG_AC_GAIN_MAN_INIT 0x0
3421 2969
3422
3423#define CP_REG_AC_GAIN_EXP__A 0x1410046 2970#define CP_REG_AC_GAIN_EXP__A 0x1410046
3424#define CP_REG_AC_GAIN_EXP__W 5 2971#define CP_REG_AC_GAIN_EXP__W 5
3425#define CP_REG_AC_GAIN_EXP__M 0x1F 2972#define CP_REG_AC_GAIN_EXP__M 0x1F
3426#define CP_REG_AC_GAIN_EXP_INIT 0x0 2973#define CP_REG_AC_GAIN_EXP_INIT 0x0
3427 2974
3428
3429#define CP_REG_AC_AMP_MODE__A 0x1410047 2975#define CP_REG_AC_AMP_MODE__A 0x1410047
3430#define CP_REG_AC_AMP_MODE__W 2 2976#define CP_REG_AC_AMP_MODE__W 2
3431#define CP_REG_AC_AMP_MODE__M 0x3 2977#define CP_REG_AC_AMP_MODE__M 0x3
@@ -3434,19 +2980,16 @@ extern "C" {
3434#define CP_REG_AC_AMP_MODE_FIXED 0x2 2980#define CP_REG_AC_AMP_MODE_FIXED 0x2
3435#define CP_REG_AC_AMP_MODE_INIT 0x2 2981#define CP_REG_AC_AMP_MODE_INIT 0x2
3436 2982
3437
3438#define CP_REG_AC_AMP_FIX__A 0x1410048 2983#define CP_REG_AC_AMP_FIX__A 0x1410048
3439#define CP_REG_AC_AMP_FIX__W 14 2984#define CP_REG_AC_AMP_FIX__W 14
3440#define CP_REG_AC_AMP_FIX__M 0x3FFF 2985#define CP_REG_AC_AMP_FIX__M 0x3FFF
3441#define CP_REG_AC_AMP_FIX_INIT 0x1FF 2986#define CP_REG_AC_AMP_FIX_INIT 0x1FF
3442 2987
3443
3444#define CP_REG_AC_AMP_READ__A 0x1410049 2988#define CP_REG_AC_AMP_READ__A 0x1410049
3445#define CP_REG_AC_AMP_READ__W 14 2989#define CP_REG_AC_AMP_READ__W 14
3446#define CP_REG_AC_AMP_READ__M 0x3FFF 2990#define CP_REG_AC_AMP_READ__M 0x3FFF
3447#define CP_REG_AC_AMP_READ_INIT 0x0 2991#define CP_REG_AC_AMP_READ_INIT 0x0
3448 2992
3449
3450#define CP_REG_AC_ANG_MODE__A 0x141004A 2993#define CP_REG_AC_ANG_MODE__A 0x141004A
3451#define CP_REG_AC_ANG_MODE__W 2 2994#define CP_REG_AC_ANG_MODE__W 2
3452#define CP_REG_AC_ANG_MODE__M 0x3 2995#define CP_REG_AC_ANG_MODE__M 0x3
@@ -3456,25 +2999,21 @@ extern "C" {
3456#define CP_REG_AC_ANG_MODE_OFFSET 0x3 2999#define CP_REG_AC_ANG_MODE_OFFSET 0x3
3457#define CP_REG_AC_ANG_MODE_INIT 0x3 3000#define CP_REG_AC_ANG_MODE_INIT 0x3
3458 3001
3459
3460#define CP_REG_AC_ANG_OFFS__A 0x141004B 3002#define CP_REG_AC_ANG_OFFS__A 0x141004B
3461#define CP_REG_AC_ANG_OFFS__W 14 3003#define CP_REG_AC_ANG_OFFS__W 14
3462#define CP_REG_AC_ANG_OFFS__M 0x3FFF 3004#define CP_REG_AC_ANG_OFFS__M 0x3FFF
3463#define CP_REG_AC_ANG_OFFS_INIT 0x0 3005#define CP_REG_AC_ANG_OFFS_INIT 0x0
3464 3006
3465
3466#define CP_REG_AC_ANG_READ__A 0x141004C 3007#define CP_REG_AC_ANG_READ__A 0x141004C
3467#define CP_REG_AC_ANG_READ__W 16 3008#define CP_REG_AC_ANG_READ__W 16
3468#define CP_REG_AC_ANG_READ__M 0xFFFF 3009#define CP_REG_AC_ANG_READ__M 0xFFFF
3469#define CP_REG_AC_ANG_READ_INIT 0x0 3010#define CP_REG_AC_ANG_READ_INIT 0x0
3470 3011
3471
3472#define CP_REG_DL_MB_WR_ADDR__A 0x1410050 3012#define CP_REG_DL_MB_WR_ADDR__A 0x1410050
3473#define CP_REG_DL_MB_WR_ADDR__W 15 3013#define CP_REG_DL_MB_WR_ADDR__W 15
3474#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF 3014#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF
3475#define CP_REG_DL_MB_WR_ADDR_INIT 0x0 3015#define CP_REG_DL_MB_WR_ADDR_INIT 0x0
3476 3016
3477
3478#define CP_REG_DL_MB_WR_CTR__A 0x1410051 3017#define CP_REG_DL_MB_WR_CTR__A 0x1410051
3479#define CP_REG_DL_MB_WR_CTR__W 5 3018#define CP_REG_DL_MB_WR_CTR__W 5
3480#define CP_REG_DL_MB_WR_CTR__M 0x1F 3019#define CP_REG_DL_MB_WR_CTR__M 0x1F
@@ -3492,13 +3031,11 @@ extern "C" {
3492#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 3031#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1
3493#define CP_REG_DL_MB_WR_CTR_INIT 0x0 3032#define CP_REG_DL_MB_WR_CTR_INIT 0x0
3494 3033
3495
3496#define CP_REG_DL_MB_RD_ADDR__A 0x1410052 3034#define CP_REG_DL_MB_RD_ADDR__A 0x1410052
3497#define CP_REG_DL_MB_RD_ADDR__W 15 3035#define CP_REG_DL_MB_RD_ADDR__W 15
3498#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF 3036#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF
3499#define CP_REG_DL_MB_RD_ADDR_INIT 0x0 3037#define CP_REG_DL_MB_RD_ADDR_INIT 0x0
3500 3038
3501
3502#define CP_REG_DL_MB_RD_CTR__A 0x1410053 3039#define CP_REG_DL_MB_RD_CTR__A 0x1410053
3503#define CP_REG_DL_MB_RD_CTR__W 11 3040#define CP_REG_DL_MB_RD_CTR__W 11
3504#define CP_REG_DL_MB_RD_CTR__M 0x7FF 3041#define CP_REG_DL_MB_RD_CTR__M 0x7FF
@@ -3528,36 +3065,18 @@ extern "C" {
3528#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 3065#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1
3529#define CP_REG_DL_MB_RD_CTR_INIT 0x0 3066#define CP_REG_DL_MB_RD_CTR_INIT 0x0
3530 3067
3531
3532
3533#define CP_BR_BUF_RAM__A 0x1420000 3068#define CP_BR_BUF_RAM__A 0x1420000
3534 3069
3535
3536
3537#define CP_BR_CPL_RAM__A 0x1430000 3070#define CP_BR_CPL_RAM__A 0x1430000
3538 3071
3539
3540
3541#define CP_PB_DL0_RAM__A 0x1440000 3072#define CP_PB_DL0_RAM__A 0x1440000
3542 3073
3543
3544
3545#define CP_PB_DL1_RAM__A 0x1450000 3074#define CP_PB_DL1_RAM__A 0x1450000
3546 3075
3547
3548
3549#define CP_PB_DL2_RAM__A 0x1460000 3076#define CP_PB_DL2_RAM__A 0x1460000
3550 3077
3551
3552
3553
3554
3555#define CE_SID 0xA 3078#define CE_SID 0xA
3556 3079
3557
3558
3559
3560
3561#define CE_COMM_EXEC__A 0x1800000 3080#define CE_COMM_EXEC__A 0x1800000
3562#define CE_COMM_EXEC__W 3 3081#define CE_COMM_EXEC__W 3
3563#define CE_COMM_EXEC__M 0x7 3082#define CE_COMM_EXEC__M 0x7
@@ -3590,11 +3109,6 @@ extern "C" {
3590#define CE_COMM_INT_MSK__W 16 3109#define CE_COMM_INT_MSK__W 16
3591#define CE_COMM_INT_MSK__M 0xFFFF 3110#define CE_COMM_INT_MSK__M 0xFFFF
3592 3111
3593
3594
3595
3596
3597
3598#define CE_REG_COMM_EXEC__A 0x1810000 3112#define CE_REG_COMM_EXEC__A 0x1810000
3599#define CE_REG_COMM_EXEC__W 3 3113#define CE_REG_COMM_EXEC__W 3
3600#define CE_REG_COMM_EXEC__M 0x7 3114#define CE_REG_COMM_EXEC__M 0x7
@@ -3606,7 +3120,6 @@ extern "C" {
3606#define CE_REG_COMM_EXEC_CTL_HOLD 0x2 3120#define CE_REG_COMM_EXEC_CTL_HOLD 0x2
3607#define CE_REG_COMM_EXEC_CTL_STEP 0x3 3121#define CE_REG_COMM_EXEC_CTL_STEP 0x3
3608 3122
3609
3610#define CE_REG_COMM_MB__A 0x1810002 3123#define CE_REG_COMM_MB__A 0x1810002
3611#define CE_REG_COMM_MB__W 4 3124#define CE_REG_COMM_MB__W 4
3612#define CE_REG_COMM_MB__M 0xF 3125#define CE_REG_COMM_MB__M 0xF
@@ -3652,7 +3165,6 @@ extern "C" {
3652#define CE_REG_COMM_INT_STA_CE_FI__W 1 3165#define CE_REG_COMM_INT_STA_CE_FI__W 1
3653#define CE_REG_COMM_INT_STA_CE_FI__M 0x4 3166#define CE_REG_COMM_INT_STA_CE_FI__M 0x4
3654 3167
3655
3656#define CE_REG_COMM_INT_MSK__A 0x1810008 3168#define CE_REG_COMM_INT_MSK__A 0x1810008
3657#define CE_REG_COMM_INT_MSK__W 3 3169#define CE_REG_COMM_INT_MSK__W 3
3658#define CE_REG_COMM_INT_MSK__M 0x7 3170#define CE_REG_COMM_INT_MSK__M 0x7
@@ -3666,19 +3178,15 @@ extern "C" {
3666#define CE_REG_COMM_INT_MSK_CE_FI__W 1 3178#define CE_REG_COMM_INT_MSK_CE_FI__W 1
3667#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 3179#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4
3668 3180
3669
3670#define CE_REG_2K__A 0x1810010 3181#define CE_REG_2K__A 0x1810010
3671#define CE_REG_2K__W 1 3182#define CE_REG_2K__W 1
3672#define CE_REG_2K__M 0x1 3183#define CE_REG_2K__M 0x1
3673#define CE_REG_2K_INIT 0x0 3184#define CE_REG_2K_INIT 0x0
3674 3185
3675
3676#define CE_REG_TAPSET__A 0x1810011 3186#define CE_REG_TAPSET__A 0x1810011
3677#define CE_REG_TAPSET__W 2 3187#define CE_REG_TAPSET__W 2
3678#define CE_REG_TAPSET__M 0x3 3188#define CE_REG_TAPSET__M 0x3
3679 3189
3680
3681
3682#define CE_REG_TAPSET_MOTION_INIT 0x0 3190#define CE_REG_TAPSET_MOTION_INIT 0x0
3683 3191
3684#define CE_REG_TAPSET_MOTION_NO 0x0 3192#define CE_REG_TAPSET_MOTION_NO 0x0
@@ -3689,43 +3197,36 @@ extern "C" {
3689 3197
3690#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 3198#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3
3691 3199
3692
3693#define CE_REG_AVG_POW__A 0x1810012 3200#define CE_REG_AVG_POW__A 0x1810012
3694#define CE_REG_AVG_POW__W 8 3201#define CE_REG_AVG_POW__W 8
3695#define CE_REG_AVG_POW__M 0xFF 3202#define CE_REG_AVG_POW__M 0xFF
3696#define CE_REG_AVG_POW_INIT 0x0 3203#define CE_REG_AVG_POW_INIT 0x0
3697 3204
3698
3699#define CE_REG_MAX_POW__A 0x1810013 3205#define CE_REG_MAX_POW__A 0x1810013
3700#define CE_REG_MAX_POW__W 8 3206#define CE_REG_MAX_POW__W 8
3701#define CE_REG_MAX_POW__M 0xFF 3207#define CE_REG_MAX_POW__M 0xFF
3702#define CE_REG_MAX_POW_INIT 0x0 3208#define CE_REG_MAX_POW_INIT 0x0
3703 3209
3704
3705#define CE_REG_ATT__A 0x1810014 3210#define CE_REG_ATT__A 0x1810014
3706#define CE_REG_ATT__W 8 3211#define CE_REG_ATT__W 8
3707#define CE_REG_ATT__M 0xFF 3212#define CE_REG_ATT__M 0xFF
3708#define CE_REG_ATT_INIT 0x0 3213#define CE_REG_ATT_INIT 0x0
3709 3214
3710
3711#define CE_REG_NRED__A 0x1810015 3215#define CE_REG_NRED__A 0x1810015
3712#define CE_REG_NRED__W 6 3216#define CE_REG_NRED__W 6
3713#define CE_REG_NRED__M 0x3F 3217#define CE_REG_NRED__M 0x3F
3714#define CE_REG_NRED_INIT 0x0 3218#define CE_REG_NRED_INIT 0x0
3715 3219
3716
3717#define CE_REG_PU_SIGN__A 0x1810020 3220#define CE_REG_PU_SIGN__A 0x1810020
3718#define CE_REG_PU_SIGN__W 1 3221#define CE_REG_PU_SIGN__W 1
3719#define CE_REG_PU_SIGN__M 0x1 3222#define CE_REG_PU_SIGN__M 0x1
3720#define CE_REG_PU_SIGN_INIT 0x0 3223#define CE_REG_PU_SIGN_INIT 0x0
3721 3224
3722
3723#define CE_REG_PU_MIX__A 0x1810021 3225#define CE_REG_PU_MIX__A 0x1810021
3724#define CE_REG_PU_MIX__W 7 3226#define CE_REG_PU_MIX__W 7
3725#define CE_REG_PU_MIX__M 0x7F 3227#define CE_REG_PU_MIX__M 0x7F
3726#define CE_REG_PU_MIX_INIT 0x0 3228#define CE_REG_PU_MIX_INIT 0x0
3727 3229
3728
3729#define CE_REG_PB_PILOT_REQ__A 0x1810030 3230#define CE_REG_PB_PILOT_REQ__A 0x1810030
3730#define CE_REG_PB_PILOT_REQ__W 15 3231#define CE_REG_PB_PILOT_REQ__W 15
3731#define CE_REG_PB_PILOT_REQ__M 0x7FFF 3232#define CE_REG_PB_PILOT_REQ__M 0x7FFF
@@ -3737,49 +3238,41 @@ extern "C" {
3737#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 3238#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12
3738#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF 3239#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF
3739 3240
3740
3741#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 3241#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031
3742#define CE_REG_PB_PILOT_REQ_VALID__W 1 3242#define CE_REG_PB_PILOT_REQ_VALID__W 1
3743#define CE_REG_PB_PILOT_REQ_VALID__M 0x1 3243#define CE_REG_PB_PILOT_REQ_VALID__M 0x1
3744#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 3244#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0
3745 3245
3746
3747#define CE_REG_PB_FREEZE__A 0x1810032 3246#define CE_REG_PB_FREEZE__A 0x1810032
3748#define CE_REG_PB_FREEZE__W 1 3247#define CE_REG_PB_FREEZE__W 1
3749#define CE_REG_PB_FREEZE__M 0x1 3248#define CE_REG_PB_FREEZE__M 0x1
3750#define CE_REG_PB_FREEZE_INIT 0x0 3249#define CE_REG_PB_FREEZE_INIT 0x0
3751 3250
3752
3753#define CE_REG_PB_PILOT_EXP__A 0x1810038 3251#define CE_REG_PB_PILOT_EXP__A 0x1810038
3754#define CE_REG_PB_PILOT_EXP__W 4 3252#define CE_REG_PB_PILOT_EXP__W 4
3755#define CE_REG_PB_PILOT_EXP__M 0xF 3253#define CE_REG_PB_PILOT_EXP__M 0xF
3756#define CE_REG_PB_PILOT_EXP_INIT 0x0 3254#define CE_REG_PB_PILOT_EXP_INIT 0x0
3757 3255
3758
3759#define CE_REG_PB_PILOT_REAL__A 0x1810039 3256#define CE_REG_PB_PILOT_REAL__A 0x1810039
3760#define CE_REG_PB_PILOT_REAL__W 10 3257#define CE_REG_PB_PILOT_REAL__W 10
3761#define CE_REG_PB_PILOT_REAL__M 0x3FF 3258#define CE_REG_PB_PILOT_REAL__M 0x3FF
3762#define CE_REG_PB_PILOT_REAL_INIT 0x0 3259#define CE_REG_PB_PILOT_REAL_INIT 0x0
3763 3260
3764
3765#define CE_REG_PB_PILOT_IMAG__A 0x181003A 3261#define CE_REG_PB_PILOT_IMAG__A 0x181003A
3766#define CE_REG_PB_PILOT_IMAG__W 10 3262#define CE_REG_PB_PILOT_IMAG__W 10
3767#define CE_REG_PB_PILOT_IMAG__M 0x3FF 3263#define CE_REG_PB_PILOT_IMAG__M 0x3FF
3768#define CE_REG_PB_PILOT_IMAG_INIT 0x0 3264#define CE_REG_PB_PILOT_IMAG_INIT 0x0
3769 3265
3770
3771#define CE_REG_PB_SMBNR__A 0x181003B 3266#define CE_REG_PB_SMBNR__A 0x181003B
3772#define CE_REG_PB_SMBNR__W 5 3267#define CE_REG_PB_SMBNR__W 5
3773#define CE_REG_PB_SMBNR__M 0x1F 3268#define CE_REG_PB_SMBNR__M 0x1F
3774#define CE_REG_PB_SMBNR_INIT 0x0 3269#define CE_REG_PB_SMBNR_INIT 0x0
3775 3270
3776
3777#define CE_REG_NE_PILOT_REQ__A 0x1810040 3271#define CE_REG_NE_PILOT_REQ__A 0x1810040
3778#define CE_REG_NE_PILOT_REQ__W 12 3272#define CE_REG_NE_PILOT_REQ__W 12
3779#define CE_REG_NE_PILOT_REQ__M 0xFFF 3273#define CE_REG_NE_PILOT_REQ__M 0xFFF
3780#define CE_REG_NE_PILOT_REQ_INIT 0x0 3274#define CE_REG_NE_PILOT_REQ_INIT 0x0
3781 3275
3782
3783#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 3276#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041
3784#define CE_REG_NE_PILOT_REQ_VALID__W 2 3277#define CE_REG_NE_PILOT_REQ_VALID__W 2
3785#define CE_REG_NE_PILOT_REQ_VALID__M 0x3 3278#define CE_REG_NE_PILOT_REQ_VALID__M 0x3
@@ -3791,13 +3284,11 @@ extern "C" {
3791#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 3284#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1
3792#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 3285#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1
3793 3286
3794
3795#define CE_REG_NE_PILOT_DATA__A 0x1810042 3287#define CE_REG_NE_PILOT_DATA__A 0x1810042
3796#define CE_REG_NE_PILOT_DATA__W 10 3288#define CE_REG_NE_PILOT_DATA__W 10
3797#define CE_REG_NE_PILOT_DATA__M 0x3FF 3289#define CE_REG_NE_PILOT_DATA__M 0x3FF
3798#define CE_REG_NE_PILOT_DATA_INIT 0x0 3290#define CE_REG_NE_PILOT_DATA_INIT 0x0
3799 3291
3800
3801#define CE_REG_NE_ERR_SELECT__A 0x1810043 3292#define CE_REG_NE_ERR_SELECT__A 0x1810043
3802#define CE_REG_NE_ERR_SELECT__W 3 3293#define CE_REG_NE_ERR_SELECT__W 3
3803#define CE_REG_NE_ERR_SELECT__M 0x7 3294#define CE_REG_NE_ERR_SELECT__M 0x7
@@ -3815,31 +3306,26 @@ extern "C" {
3815#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 3306#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1
3816#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 3307#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1
3817 3308
3818
3819#define CE_REG_NE_TD_CAL__A 0x1810044 3309#define CE_REG_NE_TD_CAL__A 0x1810044
3820#define CE_REG_NE_TD_CAL__W 9 3310#define CE_REG_NE_TD_CAL__W 9
3821#define CE_REG_NE_TD_CAL__M 0x1FF 3311#define CE_REG_NE_TD_CAL__M 0x1FF
3822#define CE_REG_NE_TD_CAL_INIT 0x0 3312#define CE_REG_NE_TD_CAL_INIT 0x0
3823 3313
3824
3825#define CE_REG_NE_FD_CAL__A 0x1810045 3314#define CE_REG_NE_FD_CAL__A 0x1810045
3826#define CE_REG_NE_FD_CAL__W 9 3315#define CE_REG_NE_FD_CAL__W 9
3827#define CE_REG_NE_FD_CAL__M 0x1FF 3316#define CE_REG_NE_FD_CAL__M 0x1FF
3828#define CE_REG_NE_FD_CAL_INIT 0x0 3317#define CE_REG_NE_FD_CAL_INIT 0x0
3829 3318
3830
3831#define CE_REG_NE_MIXAVG__A 0x1810046 3319#define CE_REG_NE_MIXAVG__A 0x1810046
3832#define CE_REG_NE_MIXAVG__W 3 3320#define CE_REG_NE_MIXAVG__W 3
3833#define CE_REG_NE_MIXAVG__M 0x7 3321#define CE_REG_NE_MIXAVG__M 0x7
3834#define CE_REG_NE_MIXAVG_INIT 0x0 3322#define CE_REG_NE_MIXAVG_INIT 0x0
3835 3323
3836
3837#define CE_REG_NE_NUPD_OFS__A 0x1810047 3324#define CE_REG_NE_NUPD_OFS__A 0x1810047
3838#define CE_REG_NE_NUPD_OFS__W 7 3325#define CE_REG_NE_NUPD_OFS__W 7
3839#define CE_REG_NE_NUPD_OFS__M 0x7F 3326#define CE_REG_NE_NUPD_OFS__M 0x7F
3840#define CE_REG_NE_NUPD_OFS_INIT 0x0 3327#define CE_REG_NE_NUPD_OFS_INIT 0x0
3841 3328
3842
3843#define CE_REG_NE_TD_POW__A 0x1810048 3329#define CE_REG_NE_TD_POW__A 0x1810048
3844#define CE_REG_NE_TD_POW__W 15 3330#define CE_REG_NE_TD_POW__W 15
3845#define CE_REG_NE_TD_POW__M 0x7FFF 3331#define CE_REG_NE_TD_POW__M 0x7FFF
@@ -3853,7 +3339,6 @@ extern "C" {
3853#define CE_REG_NE_TD_POW_MANTISSA__W 10 3339#define CE_REG_NE_TD_POW_MANTISSA__W 10
3854#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF 3340#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF
3855 3341
3856
3857#define CE_REG_NE_FD_POW__A 0x1810049 3342#define CE_REG_NE_FD_POW__A 0x1810049
3858#define CE_REG_NE_FD_POW__W 15 3343#define CE_REG_NE_FD_POW__W 15
3859#define CE_REG_NE_FD_POW__M 0x7FFF 3344#define CE_REG_NE_FD_POW__M 0x7FFF
@@ -3867,97 +3352,81 @@ extern "C" {
3867#define CE_REG_NE_FD_POW_MANTISSA__W 10 3352#define CE_REG_NE_FD_POW_MANTISSA__W 10
3868#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF 3353#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF
3869 3354
3870
3871#define CE_REG_NE_NEXP_AVG__A 0x181004A 3355#define CE_REG_NE_NEXP_AVG__A 0x181004A
3872#define CE_REG_NE_NEXP_AVG__W 8 3356#define CE_REG_NE_NEXP_AVG__W 8
3873#define CE_REG_NE_NEXP_AVG__M 0xFF 3357#define CE_REG_NE_NEXP_AVG__M 0xFF
3874#define CE_REG_NE_NEXP_AVG_INIT 0x0 3358#define CE_REG_NE_NEXP_AVG_INIT 0x0
3875 3359
3876
3877#define CE_REG_NE_OFFSET__A 0x181004B 3360#define CE_REG_NE_OFFSET__A 0x181004B
3878#define CE_REG_NE_OFFSET__W 9 3361#define CE_REG_NE_OFFSET__W 9
3879#define CE_REG_NE_OFFSET__M 0x1FF 3362#define CE_REG_NE_OFFSET__M 0x1FF
3880#define CE_REG_NE_OFFSET_INIT 0x0 3363#define CE_REG_NE_OFFSET_INIT 0x0
3881 3364
3882
3883#define CE_REG_PE_NEXP_OFFS__A 0x1810050 3365#define CE_REG_PE_NEXP_OFFS__A 0x1810050
3884#define CE_REG_PE_NEXP_OFFS__W 8 3366#define CE_REG_PE_NEXP_OFFS__W 8
3885#define CE_REG_PE_NEXP_OFFS__M 0xFF 3367#define CE_REG_PE_NEXP_OFFS__M 0xFF
3886#define CE_REG_PE_NEXP_OFFS_INIT 0x0 3368#define CE_REG_PE_NEXP_OFFS_INIT 0x0
3887 3369
3888
3889#define CE_REG_PE_TIMESHIFT__A 0x1810051 3370#define CE_REG_PE_TIMESHIFT__A 0x1810051
3890#define CE_REG_PE_TIMESHIFT__W 14 3371#define CE_REG_PE_TIMESHIFT__W 14
3891#define CE_REG_PE_TIMESHIFT__M 0x3FFF 3372#define CE_REG_PE_TIMESHIFT__M 0x3FFF
3892#define CE_REG_PE_TIMESHIFT_INIT 0x0 3373#define CE_REG_PE_TIMESHIFT_INIT 0x0
3893 3374
3894
3895#define CE_REG_PE_DIF_REAL_L__A 0x1810052 3375#define CE_REG_PE_DIF_REAL_L__A 0x1810052
3896#define CE_REG_PE_DIF_REAL_L__W 16 3376#define CE_REG_PE_DIF_REAL_L__W 16
3897#define CE_REG_PE_DIF_REAL_L__M 0xFFFF 3377#define CE_REG_PE_DIF_REAL_L__M 0xFFFF
3898#define CE_REG_PE_DIF_REAL_L_INIT 0x0 3378#define CE_REG_PE_DIF_REAL_L_INIT 0x0
3899 3379
3900
3901#define CE_REG_PE_DIF_IMAG_L__A 0x1810053 3380#define CE_REG_PE_DIF_IMAG_L__A 0x1810053
3902#define CE_REG_PE_DIF_IMAG_L__W 16 3381#define CE_REG_PE_DIF_IMAG_L__W 16
3903#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF 3382#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF
3904#define CE_REG_PE_DIF_IMAG_L_INIT 0x0 3383#define CE_REG_PE_DIF_IMAG_L_INIT 0x0
3905 3384
3906
3907#define CE_REG_PE_DIF_REAL_R__A 0x1810054 3385#define CE_REG_PE_DIF_REAL_R__A 0x1810054
3908#define CE_REG_PE_DIF_REAL_R__W 16 3386#define CE_REG_PE_DIF_REAL_R__W 16
3909#define CE_REG_PE_DIF_REAL_R__M 0xFFFF 3387#define CE_REG_PE_DIF_REAL_R__M 0xFFFF
3910#define CE_REG_PE_DIF_REAL_R_INIT 0x0 3388#define CE_REG_PE_DIF_REAL_R_INIT 0x0
3911 3389
3912
3913#define CE_REG_PE_DIF_IMAG_R__A 0x1810055 3390#define CE_REG_PE_DIF_IMAG_R__A 0x1810055
3914#define CE_REG_PE_DIF_IMAG_R__W 16 3391#define CE_REG_PE_DIF_IMAG_R__W 16
3915#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF 3392#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF
3916#define CE_REG_PE_DIF_IMAG_R_INIT 0x0 3393#define CE_REG_PE_DIF_IMAG_R_INIT 0x0
3917 3394
3918
3919#define CE_REG_PE_ABS_REAL_L__A 0x1810056 3395#define CE_REG_PE_ABS_REAL_L__A 0x1810056
3920#define CE_REG_PE_ABS_REAL_L__W 16 3396#define CE_REG_PE_ABS_REAL_L__W 16
3921#define CE_REG_PE_ABS_REAL_L__M 0xFFFF 3397#define CE_REG_PE_ABS_REAL_L__M 0xFFFF
3922#define CE_REG_PE_ABS_REAL_L_INIT 0x0 3398#define CE_REG_PE_ABS_REAL_L_INIT 0x0
3923 3399
3924
3925#define CE_REG_PE_ABS_IMAG_L__A 0x1810057 3400#define CE_REG_PE_ABS_IMAG_L__A 0x1810057
3926#define CE_REG_PE_ABS_IMAG_L__W 16 3401#define CE_REG_PE_ABS_IMAG_L__W 16
3927#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF 3402#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF
3928#define CE_REG_PE_ABS_IMAG_L_INIT 0x0 3403#define CE_REG_PE_ABS_IMAG_L_INIT 0x0
3929 3404
3930
3931#define CE_REG_PE_ABS_REAL_R__A 0x1810058 3405#define CE_REG_PE_ABS_REAL_R__A 0x1810058
3932#define CE_REG_PE_ABS_REAL_R__W 16 3406#define CE_REG_PE_ABS_REAL_R__W 16
3933#define CE_REG_PE_ABS_REAL_R__M 0xFFFF 3407#define CE_REG_PE_ABS_REAL_R__M 0xFFFF
3934#define CE_REG_PE_ABS_REAL_R_INIT 0x0 3408#define CE_REG_PE_ABS_REAL_R_INIT 0x0
3935 3409
3936
3937#define CE_REG_PE_ABS_IMAG_R__A 0x1810059 3410#define CE_REG_PE_ABS_IMAG_R__A 0x1810059
3938#define CE_REG_PE_ABS_IMAG_R__W 16 3411#define CE_REG_PE_ABS_IMAG_R__W 16
3939#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF 3412#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF
3940#define CE_REG_PE_ABS_IMAG_R_INIT 0x0 3413#define CE_REG_PE_ABS_IMAG_R_INIT 0x0
3941 3414
3942
3943#define CE_REG_PE_ABS_EXP_L__A 0x181005A 3415#define CE_REG_PE_ABS_EXP_L__A 0x181005A
3944#define CE_REG_PE_ABS_EXP_L__W 5 3416#define CE_REG_PE_ABS_EXP_L__W 5
3945#define CE_REG_PE_ABS_EXP_L__M 0x1F 3417#define CE_REG_PE_ABS_EXP_L__M 0x1F
3946#define CE_REG_PE_ABS_EXP_L_INIT 0x0 3418#define CE_REG_PE_ABS_EXP_L_INIT 0x0
3947 3419
3948
3949#define CE_REG_PE_ABS_EXP_R__A 0x181005B 3420#define CE_REG_PE_ABS_EXP_R__A 0x181005B
3950#define CE_REG_PE_ABS_EXP_R__W 5 3421#define CE_REG_PE_ABS_EXP_R__W 5
3951#define CE_REG_PE_ABS_EXP_R__M 0x1F 3422#define CE_REG_PE_ABS_EXP_R__M 0x1F
3952#define CE_REG_PE_ABS_EXP_R_INIT 0x0 3423#define CE_REG_PE_ABS_EXP_R_INIT 0x0
3953 3424
3954
3955#define CE_REG_TP_UPDATE_MODE__A 0x1810060 3425#define CE_REG_TP_UPDATE_MODE__A 0x1810060
3956#define CE_REG_TP_UPDATE_MODE__W 1 3426#define CE_REG_TP_UPDATE_MODE__W 1
3957#define CE_REG_TP_UPDATE_MODE__M 0x1 3427#define CE_REG_TP_UPDATE_MODE__M 0x1
3958#define CE_REG_TP_UPDATE_MODE_INIT 0x0 3428#define CE_REG_TP_UPDATE_MODE_INIT 0x0
3959 3429
3960
3961#define CE_REG_TP_LMS_TAP_ON__A 0x1810061 3430#define CE_REG_TP_LMS_TAP_ON__A 0x1810061
3962#define CE_REG_TP_LMS_TAP_ON__W 1 3431#define CE_REG_TP_LMS_TAP_ON__W 1
3963#define CE_REG_TP_LMS_TAP_ON__M 0x1 3432#define CE_REG_TP_LMS_TAP_ON__M 0x1
@@ -4007,7 +3476,6 @@ extern "C" {
4007#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 3476#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10
4008#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF 3477#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF
4009 3478
4010
4011#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D 3479#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D
4012#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 3480#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15
4013#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF 3481#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF
@@ -4021,7 +3489,6 @@ extern "C" {
4021#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 3489#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10
4022#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF 3490#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF
4023 3491
4024
4025#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E 3492#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E
4026#define CE_REG_TP_A0_TAP_ENERGY__W 15 3493#define CE_REG_TP_A0_TAP_ENERGY__W 15
4027#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF 3494#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF
@@ -4035,7 +3502,6 @@ extern "C" {
4035#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 3502#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10
4036#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF 3503#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF
4037 3504
4038
4039#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F 3505#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F
4040#define CE_REG_TP_A1_TAP_ENERGY__W 15 3506#define CE_REG_TP_A1_TAP_ENERGY__W 15
4041#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF 3507#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF
@@ -4049,399 +3515,331 @@ extern "C" {
4049#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 3515#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10
4050#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF 3516#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF
4051 3517
4052
4053#define CE_REG_TI_NEXP_OFFS__A 0x1810070 3518#define CE_REG_TI_NEXP_OFFS__A 0x1810070
4054#define CE_REG_TI_NEXP_OFFS__W 8 3519#define CE_REG_TI_NEXP_OFFS__W 8
4055#define CE_REG_TI_NEXP_OFFS__M 0xFF 3520#define CE_REG_TI_NEXP_OFFS__M 0xFF
4056#define CE_REG_TI_NEXP_OFFS_INIT 0x0 3521#define CE_REG_TI_NEXP_OFFS_INIT 0x0
4057 3522
4058
4059#define CE_REG_TI_PEAK__A 0x1810071 3523#define CE_REG_TI_PEAK__A 0x1810071
4060#define CE_REG_TI_PEAK__W 8 3524#define CE_REG_TI_PEAK__W 8
4061#define CE_REG_TI_PEAK__M 0xFF 3525#define CE_REG_TI_PEAK__M 0xFF
4062#define CE_REG_TI_PEAK_INIT 0x0 3526#define CE_REG_TI_PEAK_INIT 0x0
4063 3527
4064
4065#define CE_REG_FI_SHT_INCR__A 0x1810090 3528#define CE_REG_FI_SHT_INCR__A 0x1810090
4066#define CE_REG_FI_SHT_INCR__W 7 3529#define CE_REG_FI_SHT_INCR__W 7
4067#define CE_REG_FI_SHT_INCR__M 0x7F 3530#define CE_REG_FI_SHT_INCR__M 0x7F
4068#define CE_REG_FI_SHT_INCR_INIT 0x9 3531#define CE_REG_FI_SHT_INCR_INIT 0x9
4069 3532
4070
4071#define CE_REG_FI_EXP_NORM__A 0x1810091 3533#define CE_REG_FI_EXP_NORM__A 0x1810091
4072#define CE_REG_FI_EXP_NORM__W 4 3534#define CE_REG_FI_EXP_NORM__W 4
4073#define CE_REG_FI_EXP_NORM__M 0xF 3535#define CE_REG_FI_EXP_NORM__M 0xF
4074#define CE_REG_FI_EXP_NORM_INIT 0x4 3536#define CE_REG_FI_EXP_NORM_INIT 0x4
4075 3537
4076
4077#define CE_REG_FI_SUPR_VAL__A 0x1810092 3538#define CE_REG_FI_SUPR_VAL__A 0x1810092
4078#define CE_REG_FI_SUPR_VAL__W 1 3539#define CE_REG_FI_SUPR_VAL__W 1
4079#define CE_REG_FI_SUPR_VAL__M 0x1 3540#define CE_REG_FI_SUPR_VAL__M 0x1
4080#define CE_REG_FI_SUPR_VAL_INIT 0x1 3541#define CE_REG_FI_SUPR_VAL_INIT 0x1
4081 3542
4082
4083#define CE_REG_IR_INPUTSEL__A 0x18100A0 3543#define CE_REG_IR_INPUTSEL__A 0x18100A0
4084#define CE_REG_IR_INPUTSEL__W 1 3544#define CE_REG_IR_INPUTSEL__W 1
4085#define CE_REG_IR_INPUTSEL__M 0x1 3545#define CE_REG_IR_INPUTSEL__M 0x1
4086#define CE_REG_IR_INPUTSEL_INIT 0x0 3546#define CE_REG_IR_INPUTSEL_INIT 0x0
4087 3547
4088
4089#define CE_REG_IR_STARTPOS__A 0x18100A1 3548#define CE_REG_IR_STARTPOS__A 0x18100A1
4090#define CE_REG_IR_STARTPOS__W 8 3549#define CE_REG_IR_STARTPOS__W 8
4091#define CE_REG_IR_STARTPOS__M 0xFF 3550#define CE_REG_IR_STARTPOS__M 0xFF
4092#define CE_REG_IR_STARTPOS_INIT 0x0 3551#define CE_REG_IR_STARTPOS_INIT 0x0
4093 3552
4094
4095#define CE_REG_IR_NEXP_THRES__A 0x18100A2 3553#define CE_REG_IR_NEXP_THRES__A 0x18100A2
4096#define CE_REG_IR_NEXP_THRES__W 8 3554#define CE_REG_IR_NEXP_THRES__W 8
4097#define CE_REG_IR_NEXP_THRES__M 0xFF 3555#define CE_REG_IR_NEXP_THRES__M 0xFF
4098#define CE_REG_IR_NEXP_THRES_INIT 0x0 3556#define CE_REG_IR_NEXP_THRES_INIT 0x0
4099 3557
4100
4101#define CE_REG_IR_LENGTH__A 0x18100A3 3558#define CE_REG_IR_LENGTH__A 0x18100A3
4102#define CE_REG_IR_LENGTH__W 4 3559#define CE_REG_IR_LENGTH__W 4
4103#define CE_REG_IR_LENGTH__M 0xF 3560#define CE_REG_IR_LENGTH__M 0xF
4104#define CE_REG_IR_LENGTH_INIT 0x0 3561#define CE_REG_IR_LENGTH_INIT 0x0
4105 3562
4106
4107#define CE_REG_IR_FREQ__A 0x18100A4 3563#define CE_REG_IR_FREQ__A 0x18100A4
4108#define CE_REG_IR_FREQ__W 11 3564#define CE_REG_IR_FREQ__W 11
4109#define CE_REG_IR_FREQ__M 0x7FF 3565#define CE_REG_IR_FREQ__M 0x7FF
4110#define CE_REG_IR_FREQ_INIT 0x0 3566#define CE_REG_IR_FREQ_INIT 0x0
4111 3567
4112
4113#define CE_REG_IR_FREQINC__A 0x18100A5 3568#define CE_REG_IR_FREQINC__A 0x18100A5
4114#define CE_REG_IR_FREQINC__W 11 3569#define CE_REG_IR_FREQINC__W 11
4115#define CE_REG_IR_FREQINC__M 0x7FF 3570#define CE_REG_IR_FREQINC__M 0x7FF
4116#define CE_REG_IR_FREQINC_INIT 0x0 3571#define CE_REG_IR_FREQINC_INIT 0x0
4117 3572
4118
4119#define CE_REG_IR_KAISINC__A 0x18100A6 3573#define CE_REG_IR_KAISINC__A 0x18100A6
4120#define CE_REG_IR_KAISINC__W 15 3574#define CE_REG_IR_KAISINC__W 15
4121#define CE_REG_IR_KAISINC__M 0x7FFF 3575#define CE_REG_IR_KAISINC__M 0x7FFF
4122#define CE_REG_IR_KAISINC_INIT 0x0 3576#define CE_REG_IR_KAISINC_INIT 0x0
4123 3577
4124
4125#define CE_REG_IR_CTL__A 0x18100A7 3578#define CE_REG_IR_CTL__A 0x18100A7
4126#define CE_REG_IR_CTL__W 3 3579#define CE_REG_IR_CTL__W 3
4127#define CE_REG_IR_CTL__M 0x7 3580#define CE_REG_IR_CTL__M 0x7
4128#define CE_REG_IR_CTL_INIT 0x0 3581#define CE_REG_IR_CTL_INIT 0x0
4129 3582
4130
4131#define CE_REG_IR_REAL__A 0x18100A8 3583#define CE_REG_IR_REAL__A 0x18100A8
4132#define CE_REG_IR_REAL__W 16 3584#define CE_REG_IR_REAL__W 16
4133#define CE_REG_IR_REAL__M 0xFFFF 3585#define CE_REG_IR_REAL__M 0xFFFF
4134#define CE_REG_IR_REAL_INIT 0x0 3586#define CE_REG_IR_REAL_INIT 0x0
4135 3587
4136
4137#define CE_REG_IR_IMAG__A 0x18100A9 3588#define CE_REG_IR_IMAG__A 0x18100A9
4138#define CE_REG_IR_IMAG__W 16 3589#define CE_REG_IR_IMAG__W 16
4139#define CE_REG_IR_IMAG__M 0xFFFF 3590#define CE_REG_IR_IMAG__M 0xFFFF
4140#define CE_REG_IR_IMAG_INIT 0x0 3591#define CE_REG_IR_IMAG_INIT 0x0
4141 3592
4142
4143#define CE_REG_IR_INDEX__A 0x18100AA 3593#define CE_REG_IR_INDEX__A 0x18100AA
4144#define CE_REG_IR_INDEX__W 12 3594#define CE_REG_IR_INDEX__W 12
4145#define CE_REG_IR_INDEX__M 0xFFF 3595#define CE_REG_IR_INDEX__M 0xFFF
4146#define CE_REG_IR_INDEX_INIT 0x0 3596#define CE_REG_IR_INDEX_INIT 0x0
4147 3597
4148
4149
4150
4151#define CE_REG_FR_TREAL00__A 0x1820010 3598#define CE_REG_FR_TREAL00__A 0x1820010
4152#define CE_REG_FR_TREAL00__W 11 3599#define CE_REG_FR_TREAL00__W 11
4153#define CE_REG_FR_TREAL00__M 0x7FF 3600#define CE_REG_FR_TREAL00__M 0x7FF
4154#define CE_REG_FR_TREAL00_INIT 0x52 3601#define CE_REG_FR_TREAL00_INIT 0x52
4155 3602
4156
4157#define CE_REG_FR_TIMAG00__A 0x1820011 3603#define CE_REG_FR_TIMAG00__A 0x1820011
4158#define CE_REG_FR_TIMAG00__W 11 3604#define CE_REG_FR_TIMAG00__W 11
4159#define CE_REG_FR_TIMAG00__M 0x7FF 3605#define CE_REG_FR_TIMAG00__M 0x7FF
4160#define CE_REG_FR_TIMAG00_INIT 0x0 3606#define CE_REG_FR_TIMAG00_INIT 0x0
4161 3607
4162
4163#define CE_REG_FR_TREAL01__A 0x1820012 3608#define CE_REG_FR_TREAL01__A 0x1820012
4164#define CE_REG_FR_TREAL01__W 11 3609#define CE_REG_FR_TREAL01__W 11
4165#define CE_REG_FR_TREAL01__M 0x7FF 3610#define CE_REG_FR_TREAL01__M 0x7FF
4166#define CE_REG_FR_TREAL01_INIT 0x52 3611#define CE_REG_FR_TREAL01_INIT 0x52
4167 3612
4168
4169#define CE_REG_FR_TIMAG01__A 0x1820013 3613#define CE_REG_FR_TIMAG01__A 0x1820013
4170#define CE_REG_FR_TIMAG01__W 11 3614#define CE_REG_FR_TIMAG01__W 11
4171#define CE_REG_FR_TIMAG01__M 0x7FF 3615#define CE_REG_FR_TIMAG01__M 0x7FF
4172#define CE_REG_FR_TIMAG01_INIT 0x0 3616#define CE_REG_FR_TIMAG01_INIT 0x0
4173 3617
4174
4175#define CE_REG_FR_TREAL02__A 0x1820014 3618#define CE_REG_FR_TREAL02__A 0x1820014
4176#define CE_REG_FR_TREAL02__W 11 3619#define CE_REG_FR_TREAL02__W 11
4177#define CE_REG_FR_TREAL02__M 0x7FF 3620#define CE_REG_FR_TREAL02__M 0x7FF
4178#define CE_REG_FR_TREAL02_INIT 0x52 3621#define CE_REG_FR_TREAL02_INIT 0x52
4179 3622
4180
4181#define CE_REG_FR_TIMAG02__A 0x1820015 3623#define CE_REG_FR_TIMAG02__A 0x1820015
4182#define CE_REG_FR_TIMAG02__W 11 3624#define CE_REG_FR_TIMAG02__W 11
4183#define CE_REG_FR_TIMAG02__M 0x7FF 3625#define CE_REG_FR_TIMAG02__M 0x7FF
4184#define CE_REG_FR_TIMAG02_INIT 0x0 3626#define CE_REG_FR_TIMAG02_INIT 0x0
4185 3627
4186
4187#define CE_REG_FR_TREAL03__A 0x1820016 3628#define CE_REG_FR_TREAL03__A 0x1820016
4188#define CE_REG_FR_TREAL03__W 11 3629#define CE_REG_FR_TREAL03__W 11
4189#define CE_REG_FR_TREAL03__M 0x7FF 3630#define CE_REG_FR_TREAL03__M 0x7FF
4190#define CE_REG_FR_TREAL03_INIT 0x52 3631#define CE_REG_FR_TREAL03_INIT 0x52
4191 3632
4192
4193#define CE_REG_FR_TIMAG03__A 0x1820017 3633#define CE_REG_FR_TIMAG03__A 0x1820017
4194#define CE_REG_FR_TIMAG03__W 11 3634#define CE_REG_FR_TIMAG03__W 11
4195#define CE_REG_FR_TIMAG03__M 0x7FF 3635#define CE_REG_FR_TIMAG03__M 0x7FF
4196#define CE_REG_FR_TIMAG03_INIT 0x0 3636#define CE_REG_FR_TIMAG03_INIT 0x0
4197 3637
4198
4199#define CE_REG_FR_TREAL04__A 0x1820018 3638#define CE_REG_FR_TREAL04__A 0x1820018
4200#define CE_REG_FR_TREAL04__W 11 3639#define CE_REG_FR_TREAL04__W 11
4201#define CE_REG_FR_TREAL04__M 0x7FF 3640#define CE_REG_FR_TREAL04__M 0x7FF
4202#define CE_REG_FR_TREAL04_INIT 0x52 3641#define CE_REG_FR_TREAL04_INIT 0x52
4203 3642
4204
4205#define CE_REG_FR_TIMAG04__A 0x1820019 3643#define CE_REG_FR_TIMAG04__A 0x1820019
4206#define CE_REG_FR_TIMAG04__W 11 3644#define CE_REG_FR_TIMAG04__W 11
4207#define CE_REG_FR_TIMAG04__M 0x7FF 3645#define CE_REG_FR_TIMAG04__M 0x7FF
4208#define CE_REG_FR_TIMAG04_INIT 0x0 3646#define CE_REG_FR_TIMAG04_INIT 0x0
4209 3647
4210
4211#define CE_REG_FR_TREAL05__A 0x182001A 3648#define CE_REG_FR_TREAL05__A 0x182001A
4212#define CE_REG_FR_TREAL05__W 11 3649#define CE_REG_FR_TREAL05__W 11
4213#define CE_REG_FR_TREAL05__M 0x7FF 3650#define CE_REG_FR_TREAL05__M 0x7FF
4214#define CE_REG_FR_TREAL05_INIT 0x52 3651#define CE_REG_FR_TREAL05_INIT 0x52
4215 3652
4216
4217#define CE_REG_FR_TIMAG05__A 0x182001B 3653#define CE_REG_FR_TIMAG05__A 0x182001B
4218#define CE_REG_FR_TIMAG05__W 11 3654#define CE_REG_FR_TIMAG05__W 11
4219#define CE_REG_FR_TIMAG05__M 0x7FF 3655#define CE_REG_FR_TIMAG05__M 0x7FF
4220#define CE_REG_FR_TIMAG05_INIT 0x0 3656#define CE_REG_FR_TIMAG05_INIT 0x0
4221 3657
4222
4223#define CE_REG_FR_TREAL06__A 0x182001C 3658#define CE_REG_FR_TREAL06__A 0x182001C
4224#define CE_REG_FR_TREAL06__W 11 3659#define CE_REG_FR_TREAL06__W 11
4225#define CE_REG_FR_TREAL06__M 0x7FF 3660#define CE_REG_FR_TREAL06__M 0x7FF
4226#define CE_REG_FR_TREAL06_INIT 0x52 3661#define CE_REG_FR_TREAL06_INIT 0x52
4227 3662
4228
4229#define CE_REG_FR_TIMAG06__A 0x182001D 3663#define CE_REG_FR_TIMAG06__A 0x182001D
4230#define CE_REG_FR_TIMAG06__W 11 3664#define CE_REG_FR_TIMAG06__W 11
4231#define CE_REG_FR_TIMAG06__M 0x7FF 3665#define CE_REG_FR_TIMAG06__M 0x7FF
4232#define CE_REG_FR_TIMAG06_INIT 0x0 3666#define CE_REG_FR_TIMAG06_INIT 0x0
4233 3667
4234
4235#define CE_REG_FR_TREAL07__A 0x182001E 3668#define CE_REG_FR_TREAL07__A 0x182001E
4236#define CE_REG_FR_TREAL07__W 11 3669#define CE_REG_FR_TREAL07__W 11
4237#define CE_REG_FR_TREAL07__M 0x7FF 3670#define CE_REG_FR_TREAL07__M 0x7FF
4238#define CE_REG_FR_TREAL07_INIT 0x52 3671#define CE_REG_FR_TREAL07_INIT 0x52
4239 3672
4240
4241#define CE_REG_FR_TIMAG07__A 0x182001F 3673#define CE_REG_FR_TIMAG07__A 0x182001F
4242#define CE_REG_FR_TIMAG07__W 11 3674#define CE_REG_FR_TIMAG07__W 11
4243#define CE_REG_FR_TIMAG07__M 0x7FF 3675#define CE_REG_FR_TIMAG07__M 0x7FF
4244#define CE_REG_FR_TIMAG07_INIT 0x0 3676#define CE_REG_FR_TIMAG07_INIT 0x0
4245 3677
4246
4247#define CE_REG_FR_TREAL08__A 0x1820020 3678#define CE_REG_FR_TREAL08__A 0x1820020
4248#define CE_REG_FR_TREAL08__W 11 3679#define CE_REG_FR_TREAL08__W 11
4249#define CE_REG_FR_TREAL08__M 0x7FF 3680#define CE_REG_FR_TREAL08__M 0x7FF
4250#define CE_REG_FR_TREAL08_INIT 0x52 3681#define CE_REG_FR_TREAL08_INIT 0x52
4251 3682
4252
4253#define CE_REG_FR_TIMAG08__A 0x1820021 3683#define CE_REG_FR_TIMAG08__A 0x1820021
4254#define CE_REG_FR_TIMAG08__W 11 3684#define CE_REG_FR_TIMAG08__W 11
4255#define CE_REG_FR_TIMAG08__M 0x7FF 3685#define CE_REG_FR_TIMAG08__M 0x7FF
4256#define CE_REG_FR_TIMAG08_INIT 0x0 3686#define CE_REG_FR_TIMAG08_INIT 0x0
4257 3687
4258
4259#define CE_REG_FR_TREAL09__A 0x1820022 3688#define CE_REG_FR_TREAL09__A 0x1820022
4260#define CE_REG_FR_TREAL09__W 11 3689#define CE_REG_FR_TREAL09__W 11
4261#define CE_REG_FR_TREAL09__M 0x7FF 3690#define CE_REG_FR_TREAL09__M 0x7FF
4262#define CE_REG_FR_TREAL09_INIT 0x52 3691#define CE_REG_FR_TREAL09_INIT 0x52
4263 3692
4264
4265#define CE_REG_FR_TIMAG09__A 0x1820023 3693#define CE_REG_FR_TIMAG09__A 0x1820023
4266#define CE_REG_FR_TIMAG09__W 11 3694#define CE_REG_FR_TIMAG09__W 11
4267#define CE_REG_FR_TIMAG09__M 0x7FF 3695#define CE_REG_FR_TIMAG09__M 0x7FF
4268#define CE_REG_FR_TIMAG09_INIT 0x0 3696#define CE_REG_FR_TIMAG09_INIT 0x0
4269 3697
4270
4271#define CE_REG_FR_TREAL10__A 0x1820024 3698#define CE_REG_FR_TREAL10__A 0x1820024
4272#define CE_REG_FR_TREAL10__W 11 3699#define CE_REG_FR_TREAL10__W 11
4273#define CE_REG_FR_TREAL10__M 0x7FF 3700#define CE_REG_FR_TREAL10__M 0x7FF
4274#define CE_REG_FR_TREAL10_INIT 0x52 3701#define CE_REG_FR_TREAL10_INIT 0x52
4275 3702
4276
4277#define CE_REG_FR_TIMAG10__A 0x1820025 3703#define CE_REG_FR_TIMAG10__A 0x1820025
4278#define CE_REG_FR_TIMAG10__W 11 3704#define CE_REG_FR_TIMAG10__W 11
4279#define CE_REG_FR_TIMAG10__M 0x7FF 3705#define CE_REG_FR_TIMAG10__M 0x7FF
4280#define CE_REG_FR_TIMAG10_INIT 0x0 3706#define CE_REG_FR_TIMAG10_INIT 0x0
4281 3707
4282
4283#define CE_REG_FR_TREAL11__A 0x1820026 3708#define CE_REG_FR_TREAL11__A 0x1820026
4284#define CE_REG_FR_TREAL11__W 11 3709#define CE_REG_FR_TREAL11__W 11
4285#define CE_REG_FR_TREAL11__M 0x7FF 3710#define CE_REG_FR_TREAL11__M 0x7FF
4286#define CE_REG_FR_TREAL11_INIT 0x52 3711#define CE_REG_FR_TREAL11_INIT 0x52
4287 3712
4288
4289#define CE_REG_FR_TIMAG11__A 0x1820027 3713#define CE_REG_FR_TIMAG11__A 0x1820027
4290#define CE_REG_FR_TIMAG11__W 11 3714#define CE_REG_FR_TIMAG11__W 11
4291#define CE_REG_FR_TIMAG11__M 0x7FF 3715#define CE_REG_FR_TIMAG11__M 0x7FF
4292#define CE_REG_FR_TIMAG11_INIT 0x0 3716#define CE_REG_FR_TIMAG11_INIT 0x0
4293 3717
4294
4295#define CE_REG_FR_MID_TAP__A 0x1820028 3718#define CE_REG_FR_MID_TAP__A 0x1820028
4296#define CE_REG_FR_MID_TAP__W 11 3719#define CE_REG_FR_MID_TAP__W 11
4297#define CE_REG_FR_MID_TAP__M 0x7FF 3720#define CE_REG_FR_MID_TAP__M 0x7FF
4298#define CE_REG_FR_MID_TAP_INIT 0x51 3721#define CE_REG_FR_MID_TAP_INIT 0x51
4299 3722
4300
4301#define CE_REG_FR_SQS_G00__A 0x1820029 3723#define CE_REG_FR_SQS_G00__A 0x1820029
4302#define CE_REG_FR_SQS_G00__W 8 3724#define CE_REG_FR_SQS_G00__W 8
4303#define CE_REG_FR_SQS_G00__M 0xFF 3725#define CE_REG_FR_SQS_G00__M 0xFF
4304#define CE_REG_FR_SQS_G00_INIT 0xB 3726#define CE_REG_FR_SQS_G00_INIT 0xB
4305 3727
4306
4307#define CE_REG_FR_SQS_G01__A 0x182002A 3728#define CE_REG_FR_SQS_G01__A 0x182002A
4308#define CE_REG_FR_SQS_G01__W 8 3729#define CE_REG_FR_SQS_G01__W 8
4309#define CE_REG_FR_SQS_G01__M 0xFF 3730#define CE_REG_FR_SQS_G01__M 0xFF
4310#define CE_REG_FR_SQS_G01_INIT 0xB 3731#define CE_REG_FR_SQS_G01_INIT 0xB
4311 3732
4312
4313#define CE_REG_FR_SQS_G02__A 0x182002B 3733#define CE_REG_FR_SQS_G02__A 0x182002B
4314#define CE_REG_FR_SQS_G02__W 8 3734#define CE_REG_FR_SQS_G02__W 8
4315#define CE_REG_FR_SQS_G02__M 0xFF 3735#define CE_REG_FR_SQS_G02__M 0xFF
4316#define CE_REG_FR_SQS_G02_INIT 0xB 3736#define CE_REG_FR_SQS_G02_INIT 0xB
4317 3737
4318
4319#define CE_REG_FR_SQS_G03__A 0x182002C 3738#define CE_REG_FR_SQS_G03__A 0x182002C
4320#define CE_REG_FR_SQS_G03__W 8 3739#define CE_REG_FR_SQS_G03__W 8
4321#define CE_REG_FR_SQS_G03__M 0xFF 3740#define CE_REG_FR_SQS_G03__M 0xFF
4322#define CE_REG_FR_SQS_G03_INIT 0xB 3741#define CE_REG_FR_SQS_G03_INIT 0xB
4323 3742
4324
4325#define CE_REG_FR_SQS_G04__A 0x182002D 3743#define CE_REG_FR_SQS_G04__A 0x182002D
4326#define CE_REG_FR_SQS_G04__W 8 3744#define CE_REG_FR_SQS_G04__W 8
4327#define CE_REG_FR_SQS_G04__M 0xFF 3745#define CE_REG_FR_SQS_G04__M 0xFF
4328#define CE_REG_FR_SQS_G04_INIT 0xB 3746#define CE_REG_FR_SQS_G04_INIT 0xB
4329 3747
4330
4331#define CE_REG_FR_SQS_G05__A 0x182002E 3748#define CE_REG_FR_SQS_G05__A 0x182002E
4332#define CE_REG_FR_SQS_G05__W 8 3749#define CE_REG_FR_SQS_G05__W 8
4333#define CE_REG_FR_SQS_G05__M 0xFF 3750#define CE_REG_FR_SQS_G05__M 0xFF
4334#define CE_REG_FR_SQS_G05_INIT 0xB 3751#define CE_REG_FR_SQS_G05_INIT 0xB
4335 3752
4336
4337#define CE_REG_FR_SQS_G06__A 0x182002F 3753#define CE_REG_FR_SQS_G06__A 0x182002F
4338#define CE_REG_FR_SQS_G06__W 8 3754#define CE_REG_FR_SQS_G06__W 8
4339#define CE_REG_FR_SQS_G06__M 0xFF 3755#define CE_REG_FR_SQS_G06__M 0xFF
4340#define CE_REG_FR_SQS_G06_INIT 0xB 3756#define CE_REG_FR_SQS_G06_INIT 0xB
4341 3757
4342
4343#define CE_REG_FR_SQS_G07__A 0x1820030 3758#define CE_REG_FR_SQS_G07__A 0x1820030
4344#define CE_REG_FR_SQS_G07__W 8 3759#define CE_REG_FR_SQS_G07__W 8
4345#define CE_REG_FR_SQS_G07__M 0xFF 3760#define CE_REG_FR_SQS_G07__M 0xFF
4346#define CE_REG_FR_SQS_G07_INIT 0xB 3761#define CE_REG_FR_SQS_G07_INIT 0xB
4347 3762
4348
4349#define CE_REG_FR_SQS_G08__A 0x1820031 3763#define CE_REG_FR_SQS_G08__A 0x1820031
4350#define CE_REG_FR_SQS_G08__W 8 3764#define CE_REG_FR_SQS_G08__W 8
4351#define CE_REG_FR_SQS_G08__M 0xFF 3765#define CE_REG_FR_SQS_G08__M 0xFF
4352#define CE_REG_FR_SQS_G08_INIT 0xB 3766#define CE_REG_FR_SQS_G08_INIT 0xB
4353 3767
4354
4355#define CE_REG_FR_SQS_G09__A 0x1820032 3768#define CE_REG_FR_SQS_G09__A 0x1820032
4356#define CE_REG_FR_SQS_G09__W 8 3769#define CE_REG_FR_SQS_G09__W 8
4357#define CE_REG_FR_SQS_G09__M 0xFF 3770#define CE_REG_FR_SQS_G09__M 0xFF
4358#define CE_REG_FR_SQS_G09_INIT 0xB 3771#define CE_REG_FR_SQS_G09_INIT 0xB
4359 3772
4360
4361#define CE_REG_FR_SQS_G10__A 0x1820033 3773#define CE_REG_FR_SQS_G10__A 0x1820033
4362#define CE_REG_FR_SQS_G10__W 8 3774#define CE_REG_FR_SQS_G10__W 8
4363#define CE_REG_FR_SQS_G10__M 0xFF 3775#define CE_REG_FR_SQS_G10__M 0xFF
4364#define CE_REG_FR_SQS_G10_INIT 0xB 3776#define CE_REG_FR_SQS_G10_INIT 0xB
4365 3777
4366
4367#define CE_REG_FR_SQS_G11__A 0x1820034 3778#define CE_REG_FR_SQS_G11__A 0x1820034
4368#define CE_REG_FR_SQS_G11__W 8 3779#define CE_REG_FR_SQS_G11__W 8
4369#define CE_REG_FR_SQS_G11__M 0xFF 3780#define CE_REG_FR_SQS_G11__M 0xFF
4370#define CE_REG_FR_SQS_G11_INIT 0xB 3781#define CE_REG_FR_SQS_G11_INIT 0xB
4371 3782
4372
4373#define CE_REG_FR_SQS_G12__A 0x1820035 3783#define CE_REG_FR_SQS_G12__A 0x1820035
4374#define CE_REG_FR_SQS_G12__W 8 3784#define CE_REG_FR_SQS_G12__W 8
4375#define CE_REG_FR_SQS_G12__M 0xFF 3785#define CE_REG_FR_SQS_G12__M 0xFF
4376#define CE_REG_FR_SQS_G12_INIT 0x5 3786#define CE_REG_FR_SQS_G12_INIT 0x5
4377 3787
4378
4379#define CE_REG_FR_RIO_G00__A 0x1820036 3788#define CE_REG_FR_RIO_G00__A 0x1820036
4380#define CE_REG_FR_RIO_G00__W 9 3789#define CE_REG_FR_RIO_G00__W 9
4381#define CE_REG_FR_RIO_G00__M 0x1FF 3790#define CE_REG_FR_RIO_G00__M 0x1FF
4382#define CE_REG_FR_RIO_G00_INIT 0x1FF 3791#define CE_REG_FR_RIO_G00_INIT 0x1FF
4383 3792
4384
4385#define CE_REG_FR_RIO_G01__A 0x1820037 3793#define CE_REG_FR_RIO_G01__A 0x1820037
4386#define CE_REG_FR_RIO_G01__W 9 3794#define CE_REG_FR_RIO_G01__W 9
4387#define CE_REG_FR_RIO_G01__M 0x1FF 3795#define CE_REG_FR_RIO_G01__M 0x1FF
4388#define CE_REG_FR_RIO_G01_INIT 0x190 3796#define CE_REG_FR_RIO_G01_INIT 0x190
4389 3797
4390
4391#define CE_REG_FR_RIO_G02__A 0x1820038 3798#define CE_REG_FR_RIO_G02__A 0x1820038
4392#define CE_REG_FR_RIO_G02__W 9 3799#define CE_REG_FR_RIO_G02__W 9
4393#define CE_REG_FR_RIO_G02__M 0x1FF 3800#define CE_REG_FR_RIO_G02__M 0x1FF
4394#define CE_REG_FR_RIO_G02_INIT 0x10B 3801#define CE_REG_FR_RIO_G02_INIT 0x10B
4395 3802
4396
4397#define CE_REG_FR_RIO_G03__A 0x1820039 3803#define CE_REG_FR_RIO_G03__A 0x1820039
4398#define CE_REG_FR_RIO_G03__W 9 3804#define CE_REG_FR_RIO_G03__W 9
4399#define CE_REG_FR_RIO_G03__M 0x1FF 3805#define CE_REG_FR_RIO_G03__M 0x1FF
4400#define CE_REG_FR_RIO_G03_INIT 0xC8 3806#define CE_REG_FR_RIO_G03_INIT 0xC8
4401 3807
4402
4403#define CE_REG_FR_RIO_G04__A 0x182003A 3808#define CE_REG_FR_RIO_G04__A 0x182003A
4404#define CE_REG_FR_RIO_G04__W 9 3809#define CE_REG_FR_RIO_G04__W 9
4405#define CE_REG_FR_RIO_G04__M 0x1FF 3810#define CE_REG_FR_RIO_G04__M 0x1FF
4406#define CE_REG_FR_RIO_G04_INIT 0xA0 3811#define CE_REG_FR_RIO_G04_INIT 0xA0
4407 3812
4408
4409#define CE_REG_FR_RIO_G05__A 0x182003B 3813#define CE_REG_FR_RIO_G05__A 0x182003B
4410#define CE_REG_FR_RIO_G05__W 9 3814#define CE_REG_FR_RIO_G05__W 9
4411#define CE_REG_FR_RIO_G05__M 0x1FF 3815#define CE_REG_FR_RIO_G05__M 0x1FF
4412#define CE_REG_FR_RIO_G05_INIT 0x85 3816#define CE_REG_FR_RIO_G05_INIT 0x85
4413 3817
4414
4415#define CE_REG_FR_RIO_G06__A 0x182003C 3818#define CE_REG_FR_RIO_G06__A 0x182003C
4416#define CE_REG_FR_RIO_G06__W 9 3819#define CE_REG_FR_RIO_G06__W 9
4417#define CE_REG_FR_RIO_G06__M 0x1FF 3820#define CE_REG_FR_RIO_G06__M 0x1FF
4418#define CE_REG_FR_RIO_G06_INIT 0x72 3821#define CE_REG_FR_RIO_G06_INIT 0x72
4419 3822
4420
4421#define CE_REG_FR_RIO_G07__A 0x182003D 3823#define CE_REG_FR_RIO_G07__A 0x182003D
4422#define CE_REG_FR_RIO_G07__W 9 3824#define CE_REG_FR_RIO_G07__W 9
4423#define CE_REG_FR_RIO_G07__M 0x1FF 3825#define CE_REG_FR_RIO_G07__M 0x1FF
4424#define CE_REG_FR_RIO_G07_INIT 0x64 3826#define CE_REG_FR_RIO_G07_INIT 0x64
4425 3827
4426
4427#define CE_REG_FR_RIO_G08__A 0x182003E 3828#define CE_REG_FR_RIO_G08__A 0x182003E
4428#define CE_REG_FR_RIO_G08__W 9 3829#define CE_REG_FR_RIO_G08__W 9
4429#define CE_REG_FR_RIO_G08__M 0x1FF 3830#define CE_REG_FR_RIO_G08__M 0x1FF
4430#define CE_REG_FR_RIO_G08_INIT 0x59 3831#define CE_REG_FR_RIO_G08_INIT 0x59
4431 3832
4432
4433#define CE_REG_FR_RIO_G09__A 0x182003F 3833#define CE_REG_FR_RIO_G09__A 0x182003F
4434#define CE_REG_FR_RIO_G09__W 9 3834#define CE_REG_FR_RIO_G09__W 9
4435#define CE_REG_FR_RIO_G09__M 0x1FF 3835#define CE_REG_FR_RIO_G09__M 0x1FF
4436#define CE_REG_FR_RIO_G09_INIT 0x50 3836#define CE_REG_FR_RIO_G09_INIT 0x50
4437 3837
4438
4439#define CE_REG_FR_RIO_G10__A 0x1820040 3838#define CE_REG_FR_RIO_G10__A 0x1820040
4440#define CE_REG_FR_RIO_G10__W 9 3839#define CE_REG_FR_RIO_G10__W 9
4441#define CE_REG_FR_RIO_G10__M 0x1FF 3840#define CE_REG_FR_RIO_G10__M 0x1FF
4442#define CE_REG_FR_RIO_G10_INIT 0x49 3841#define CE_REG_FR_RIO_G10_INIT 0x49
4443 3842
4444
4445#define CE_REG_FR_MODE__A 0x1820041 3843#define CE_REG_FR_MODE__A 0x1820041
4446#define CE_REG_FR_MODE__W 6 3844#define CE_REG_FR_MODE__W 6
4447#define CE_REG_FR_MODE__M 0x3F 3845#define CE_REG_FR_MODE__M 0x3F
@@ -4471,19 +3869,16 @@ extern "C" {
4471#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 3869#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20
4472#define CE_REG_FR_MODE_INIT 0x3E 3870#define CE_REG_FR_MODE_INIT 0x3E
4473 3871
4474
4475#define CE_REG_FR_SQS_TRH__A 0x1820042 3872#define CE_REG_FR_SQS_TRH__A 0x1820042
4476#define CE_REG_FR_SQS_TRH__W 8 3873#define CE_REG_FR_SQS_TRH__W 8
4477#define CE_REG_FR_SQS_TRH__M 0xFF 3874#define CE_REG_FR_SQS_TRH__M 0xFF
4478#define CE_REG_FR_SQS_TRH_INIT 0x80 3875#define CE_REG_FR_SQS_TRH_INIT 0x80
4479 3876
4480
4481#define CE_REG_FR_RIO_GAIN__A 0x1820043 3877#define CE_REG_FR_RIO_GAIN__A 0x1820043
4482#define CE_REG_FR_RIO_GAIN__W 3 3878#define CE_REG_FR_RIO_GAIN__W 3
4483#define CE_REG_FR_RIO_GAIN__M 0x7 3879#define CE_REG_FR_RIO_GAIN__M 0x7
4484#define CE_REG_FR_RIO_GAIN_INIT 0x2 3880#define CE_REG_FR_RIO_GAIN_INIT 0x2
4485 3881
4486
4487#define CE_REG_FR_BYPASS__A 0x1820044 3882#define CE_REG_FR_BYPASS__A 0x1820044
4488#define CE_REG_FR_BYPASS__W 10 3883#define CE_REG_FR_BYPASS__W 10
4489#define CE_REG_FR_BYPASS__M 0x3FF 3884#define CE_REG_FR_BYPASS__M 0x3FF
@@ -4501,54 +3896,37 @@ extern "C" {
4501#define CE_REG_FR_BYPASS_TOTAL__M 0x200 3896#define CE_REG_FR_BYPASS_TOTAL__M 0x200
4502#define CE_REG_FR_BYPASS_INIT 0x13B 3897#define CE_REG_FR_BYPASS_INIT 0x13B
4503 3898
4504
4505#define CE_REG_FR_PM_SET__A 0x1820045 3899#define CE_REG_FR_PM_SET__A 0x1820045
4506#define CE_REG_FR_PM_SET__W 4 3900#define CE_REG_FR_PM_SET__W 4
4507#define CE_REG_FR_PM_SET__M 0xF 3901#define CE_REG_FR_PM_SET__M 0xF
4508#define CE_REG_FR_PM_SET_INIT 0x4 3902#define CE_REG_FR_PM_SET_INIT 0x4
4509 3903
4510
4511#define CE_REG_FR_ERR_SH__A 0x1820046 3904#define CE_REG_FR_ERR_SH__A 0x1820046
4512#define CE_REG_FR_ERR_SH__W 4 3905#define CE_REG_FR_ERR_SH__W 4
4513#define CE_REG_FR_ERR_SH__M 0xF 3906#define CE_REG_FR_ERR_SH__M 0xF
4514#define CE_REG_FR_ERR_SH_INIT 0x4 3907#define CE_REG_FR_ERR_SH_INIT 0x4
4515 3908
4516
4517#define CE_REG_FR_MAN_SH__A 0x1820047 3909#define CE_REG_FR_MAN_SH__A 0x1820047
4518#define CE_REG_FR_MAN_SH__W 4 3910#define CE_REG_FR_MAN_SH__W 4
4519#define CE_REG_FR_MAN_SH__M 0xF 3911#define CE_REG_FR_MAN_SH__M 0xF
4520#define CE_REG_FR_MAN_SH_INIT 0x7 3912#define CE_REG_FR_MAN_SH_INIT 0x7
4521 3913
4522
4523#define CE_REG_FR_TAP_SH__A 0x1820048 3914#define CE_REG_FR_TAP_SH__A 0x1820048
4524#define CE_REG_FR_TAP_SH__W 3 3915#define CE_REG_FR_TAP_SH__W 3
4525#define CE_REG_FR_TAP_SH__M 0x7 3916#define CE_REG_FR_TAP_SH__M 0x7
4526#define CE_REG_FR_TAP_SH_INIT 0x3 3917#define CE_REG_FR_TAP_SH_INIT 0x3
4527 3918
4528
4529#define CE_REG_FR_CLIP__A 0x1820049 3919#define CE_REG_FR_CLIP__A 0x1820049
4530#define CE_REG_FR_CLIP__W 9 3920#define CE_REG_FR_CLIP__W 9
4531#define CE_REG_FR_CLIP__M 0x1FF 3921#define CE_REG_FR_CLIP__M 0x1FF
4532#define CE_REG_FR_CLIP_INIT 0x49 3922#define CE_REG_FR_CLIP_INIT 0x49
4533 3923
4534
4535
4536#define CE_PB_RAM__A 0x1830000 3924#define CE_PB_RAM__A 0x1830000
4537 3925
4538
4539
4540#define CE_NE_RAM__A 0x1840000 3926#define CE_NE_RAM__A 0x1840000
4541 3927
4542
4543
4544
4545
4546#define EQ_SID 0xE 3928#define EQ_SID 0xE
4547 3929
4548
4549
4550
4551
4552#define EQ_COMM_EXEC__A 0x1C00000 3930#define EQ_COMM_EXEC__A 0x1C00000
4553#define EQ_COMM_EXEC__W 3 3931#define EQ_COMM_EXEC__W 3
4554#define EQ_COMM_EXEC__M 0x7 3932#define EQ_COMM_EXEC__M 0x7
@@ -4581,11 +3959,6 @@ extern "C" {
4581#define EQ_COMM_INT_MSK__W 16 3959#define EQ_COMM_INT_MSK__W 16
4582#define EQ_COMM_INT_MSK__M 0xFFFF 3960#define EQ_COMM_INT_MSK__M 0xFFFF
4583 3961
4584
4585
4586
4587
4588
4589#define EQ_REG_COMM_EXEC__A 0x1C10000 3962#define EQ_REG_COMM_EXEC__A 0x1C10000
4590#define EQ_REG_COMM_EXEC__W 3 3963#define EQ_REG_COMM_EXEC__W 3
4591#define EQ_REG_COMM_EXEC__M 0x7 3964#define EQ_REG_COMM_EXEC__M 0x7
@@ -4628,7 +4001,6 @@ extern "C" {
4628#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 4001#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20
4629#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 4002#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30
4630 4003
4631
4632#define EQ_REG_COMM_SERVICE0__A 0x1C10003 4004#define EQ_REG_COMM_SERVICE0__A 0x1C10003
4633#define EQ_REG_COMM_SERVICE0__W 10 4005#define EQ_REG_COMM_SERVICE0__W 10
4634#define EQ_REG_COMM_SERVICE0__M 0x3FF 4006#define EQ_REG_COMM_SERVICE0__M 0x3FF
@@ -4647,7 +4019,6 @@ extern "C" {
4647#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 4019#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1
4648#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 4020#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2
4649 4021
4650
4651#define EQ_REG_COMM_INT_MSK__A 0x1C10008 4022#define EQ_REG_COMM_INT_MSK__A 0x1C10008
4652#define EQ_REG_COMM_INT_MSK__W 2 4023#define EQ_REG_COMM_INT_MSK__W 2
4653#define EQ_REG_COMM_INT_MSK__M 0x3 4024#define EQ_REG_COMM_INT_MSK__M 0x3
@@ -4658,7 +4029,6 @@ extern "C" {
4658#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 4029#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1
4659#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 4030#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2
4660 4031
4661
4662#define EQ_REG_IS_MODE__A 0x1C10014 4032#define EQ_REG_IS_MODE__A 0x1C10014
4663#define EQ_REG_IS_MODE__W 4 4033#define EQ_REG_IS_MODE__W 4
4664#define EQ_REG_IS_MODE__M 0xF 4034#define EQ_REG_IS_MODE__M 0xF
@@ -4676,25 +4046,21 @@ extern "C" {
4676#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 4046#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0
4677#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 4047#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2
4678 4048
4679
4680#define EQ_REG_IS_GAIN_MAN__A 0x1C10015 4049#define EQ_REG_IS_GAIN_MAN__A 0x1C10015
4681#define EQ_REG_IS_GAIN_MAN__W 10 4050#define EQ_REG_IS_GAIN_MAN__W 10
4682#define EQ_REG_IS_GAIN_MAN__M 0x3FF 4051#define EQ_REG_IS_GAIN_MAN__M 0x3FF
4683#define EQ_REG_IS_GAIN_MAN_INIT 0x0 4052#define EQ_REG_IS_GAIN_MAN_INIT 0x0
4684 4053
4685
4686#define EQ_REG_IS_GAIN_EXP__A 0x1C10016 4054#define EQ_REG_IS_GAIN_EXP__A 0x1C10016
4687#define EQ_REG_IS_GAIN_EXP__W 5 4055#define EQ_REG_IS_GAIN_EXP__W 5
4688#define EQ_REG_IS_GAIN_EXP__M 0x1F 4056#define EQ_REG_IS_GAIN_EXP__M 0x1F
4689#define EQ_REG_IS_GAIN_EXP_INIT 0x0 4057#define EQ_REG_IS_GAIN_EXP_INIT 0x0
4690 4058
4691
4692#define EQ_REG_IS_CLIP_EXP__A 0x1C10017 4059#define EQ_REG_IS_CLIP_EXP__A 0x1C10017
4693#define EQ_REG_IS_CLIP_EXP__W 5 4060#define EQ_REG_IS_CLIP_EXP__W 5
4694#define EQ_REG_IS_CLIP_EXP__M 0x1F 4061#define EQ_REG_IS_CLIP_EXP__M 0x1F
4695#define EQ_REG_IS_CLIP_EXP_INIT 0x0 4062#define EQ_REG_IS_CLIP_EXP_INIT 0x0
4696 4063
4697
4698#define EQ_REG_DV_MODE__A 0x1C1001E 4064#define EQ_REG_DV_MODE__A 0x1C1001E
4699#define EQ_REG_DV_MODE__W 4 4065#define EQ_REG_DV_MODE__W 4
4700#define EQ_REG_DV_MODE__M 0xF 4066#define EQ_REG_DV_MODE__M 0xF
@@ -4724,7 +4090,6 @@ extern "C" {
4724#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 4090#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0
4725#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 4091#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8
4726 4092
4727
4728#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F 4093#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F
4729#define EQ_REG_DV_POS_CLIP_DAT__W 16 4094#define EQ_REG_DV_POS_CLIP_DAT__W 16
4730#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF 4095#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF
@@ -4782,31 +4147,26 @@ extern "C" {
4782#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 4147#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0
4783#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 4148#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80
4784 4149
4785
4786#define EQ_REG_SN_PFIX__A 0x1C10029 4150#define EQ_REG_SN_PFIX__A 0x1C10029
4787#define EQ_REG_SN_PFIX__W 8 4151#define EQ_REG_SN_PFIX__W 8
4788#define EQ_REG_SN_PFIX__M 0xFF 4152#define EQ_REG_SN_PFIX__M 0xFF
4789#define EQ_REG_SN_PFIX_INIT 0x0 4153#define EQ_REG_SN_PFIX_INIT 0x0
4790 4154
4791
4792#define EQ_REG_SN_CEGAIN__A 0x1C1002A 4155#define EQ_REG_SN_CEGAIN__A 0x1C1002A
4793#define EQ_REG_SN_CEGAIN__W 8 4156#define EQ_REG_SN_CEGAIN__W 8
4794#define EQ_REG_SN_CEGAIN__M 0xFF 4157#define EQ_REG_SN_CEGAIN__M 0xFF
4795#define EQ_REG_SN_CEGAIN_INIT 0x0 4158#define EQ_REG_SN_CEGAIN_INIT 0x0
4796 4159
4797
4798#define EQ_REG_SN_OFFSET__A 0x1C1002B 4160#define EQ_REG_SN_OFFSET__A 0x1C1002B
4799#define EQ_REG_SN_OFFSET__W 6 4161#define EQ_REG_SN_OFFSET__W 6
4800#define EQ_REG_SN_OFFSET__M 0x3F 4162#define EQ_REG_SN_OFFSET__M 0x3F
4801#define EQ_REG_SN_OFFSET_INIT 0x0 4163#define EQ_REG_SN_OFFSET_INIT 0x0
4802 4164
4803
4804#define EQ_REG_SN_NULLIFY__A 0x1C1002C 4165#define EQ_REG_SN_NULLIFY__A 0x1C1002C
4805#define EQ_REG_SN_NULLIFY__W 6 4166#define EQ_REG_SN_NULLIFY__W 6
4806#define EQ_REG_SN_NULLIFY__M 0x3F 4167#define EQ_REG_SN_NULLIFY__M 0x3F
4807#define EQ_REG_SN_NULLIFY_INIT 0x0 4168#define EQ_REG_SN_NULLIFY_INIT 0x0
4808 4169
4809
4810#define EQ_REG_SN_SQUASH__A 0x1C1002D 4170#define EQ_REG_SN_SQUASH__A 0x1C1002D
4811#define EQ_REG_SN_SQUASH__W 10 4171#define EQ_REG_SN_SQUASH__W 10
4812#define EQ_REG_SN_SQUASH__M 0x3FF 4172#define EQ_REG_SN_SQUASH__M 0x3FF
@@ -4820,9 +4180,6 @@ extern "C" {
4820#define EQ_REG_SN_SQUASH_EXP__W 4 4180#define EQ_REG_SN_SQUASH_EXP__W 4
4821#define EQ_REG_SN_SQUASH_EXP__M 0x3C0 4181#define EQ_REG_SN_SQUASH_EXP__M 0x3C0
4822 4182
4823
4824
4825
4826#define EQ_REG_RC_SEL_CAR__A 0x1C10032 4183#define EQ_REG_RC_SEL_CAR__A 0x1C10032
4827#define EQ_REG_RC_SEL_CAR__W 6 4184#define EQ_REG_RC_SEL_CAR__W 6
4828#define EQ_REG_RC_SEL_CAR__M 0x3F 4185#define EQ_REG_RC_SEL_CAR__M 0x3F
@@ -4855,7 +4212,6 @@ extern "C" {
4855#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 4212#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
4856#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 4213#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
4857 4214
4858
4859#define EQ_REG_RC_STS__A 0x1C10033 4215#define EQ_REG_RC_STS__A 0x1C10033
4860#define EQ_REG_RC_STS__W 12 4216#define EQ_REG_RC_STS__W 12
4861#define EQ_REG_RC_STS__M 0xFFF 4217#define EQ_REG_RC_STS__M 0xFFF
@@ -4882,45 +4238,36 @@ extern "C" {
4882#define EQ_REG_RC_STS_OVERFLOW_NO 0x0 4238#define EQ_REG_RC_STS_OVERFLOW_NO 0x0
4883#define EQ_REG_RC_STS_OVERFLOW_YES 0x800 4239#define EQ_REG_RC_STS_OVERFLOW_YES 0x800
4884 4240
4885
4886#define EQ_REG_OT_CONST__A 0x1C10046 4241#define EQ_REG_OT_CONST__A 0x1C10046
4887#define EQ_REG_OT_CONST__W 2 4242#define EQ_REG_OT_CONST__W 2
4888#define EQ_REG_OT_CONST__M 0x3 4243#define EQ_REG_OT_CONST__M 0x3
4889#define EQ_REG_OT_CONST_INIT 0x0 4244#define EQ_REG_OT_CONST_INIT 0x0
4890 4245
4891
4892#define EQ_REG_OT_ALPHA__A 0x1C10047 4246#define EQ_REG_OT_ALPHA__A 0x1C10047
4893#define EQ_REG_OT_ALPHA__W 2 4247#define EQ_REG_OT_ALPHA__W 2
4894#define EQ_REG_OT_ALPHA__M 0x3 4248#define EQ_REG_OT_ALPHA__M 0x3
4895#define EQ_REG_OT_ALPHA_INIT 0x0 4249#define EQ_REG_OT_ALPHA_INIT 0x0
4896 4250
4897
4898#define EQ_REG_OT_QNT_THRES0__A 0x1C10048 4251#define EQ_REG_OT_QNT_THRES0__A 0x1C10048
4899#define EQ_REG_OT_QNT_THRES0__W 5 4252#define EQ_REG_OT_QNT_THRES0__W 5
4900#define EQ_REG_OT_QNT_THRES0__M 0x1F 4253#define EQ_REG_OT_QNT_THRES0__M 0x1F
4901#define EQ_REG_OT_QNT_THRES0_INIT 0x0 4254#define EQ_REG_OT_QNT_THRES0_INIT 0x0
4902 4255
4903
4904#define EQ_REG_OT_QNT_THRES1__A 0x1C10049 4256#define EQ_REG_OT_QNT_THRES1__A 0x1C10049
4905#define EQ_REG_OT_QNT_THRES1__W 5 4257#define EQ_REG_OT_QNT_THRES1__W 5
4906#define EQ_REG_OT_QNT_THRES1__M 0x1F 4258#define EQ_REG_OT_QNT_THRES1__M 0x1F
4907#define EQ_REG_OT_QNT_THRES1_INIT 0x0 4259#define EQ_REG_OT_QNT_THRES1_INIT 0x0
4908 4260
4909
4910#define EQ_REG_OT_CSI_STEP__A 0x1C1004A 4261#define EQ_REG_OT_CSI_STEP__A 0x1C1004A
4911#define EQ_REG_OT_CSI_STEP__W 4 4262#define EQ_REG_OT_CSI_STEP__W 4
4912#define EQ_REG_OT_CSI_STEP__M 0xF 4263#define EQ_REG_OT_CSI_STEP__M 0xF
4913#define EQ_REG_OT_CSI_STEP_INIT 0x0 4264#define EQ_REG_OT_CSI_STEP_INIT 0x0
4914 4265
4915
4916#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 4266#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
4917#define EQ_REG_OT_CSI_OFFSET__W 7 4267#define EQ_REG_OT_CSI_OFFSET__W 7
4918#define EQ_REG_OT_CSI_OFFSET__M 0x7F 4268#define EQ_REG_OT_CSI_OFFSET__M 0x7F
4919#define EQ_REG_OT_CSI_OFFSET_INIT 0x0 4269#define EQ_REG_OT_CSI_OFFSET_INIT 0x0
4920 4270
4921
4922
4923
4924#define EQ_REG_TD_TPS_INIT__A 0x1C10050 4271#define EQ_REG_TD_TPS_INIT__A 0x1C10050
4925#define EQ_REG_TD_TPS_INIT__W 1 4272#define EQ_REG_TD_TPS_INIT__W 1
4926#define EQ_REG_TD_TPS_INIT__M 0x1 4273#define EQ_REG_TD_TPS_INIT__M 0x1
@@ -4928,7 +4275,6 @@ extern "C" {
4928#define EQ_REG_TD_TPS_INIT_POS 0x0 4275#define EQ_REG_TD_TPS_INIT_POS 0x0
4929#define EQ_REG_TD_TPS_INIT_NEG 0x1 4276#define EQ_REG_TD_TPS_INIT_NEG 0x1
4930 4277
4931
4932#define EQ_REG_TD_TPS_SYNC__A 0x1C10051 4278#define EQ_REG_TD_TPS_SYNC__A 0x1C10051
4933#define EQ_REG_TD_TPS_SYNC__W 16 4279#define EQ_REG_TD_TPS_SYNC__W 16
4934#define EQ_REG_TD_TPS_SYNC__M 0xFFFF 4280#define EQ_REG_TD_TPS_SYNC__M 0xFFFF
@@ -4936,7 +4282,6 @@ extern "C" {
4936#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE 4282#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE
4937#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 4283#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11
4938 4284
4939
4940#define EQ_REG_TD_TPS_LEN__A 0x1C10052 4285#define EQ_REG_TD_TPS_LEN__A 0x1C10052
4941#define EQ_REG_TD_TPS_LEN__W 6 4286#define EQ_REG_TD_TPS_LEN__W 6
4942#define EQ_REG_TD_TPS_LEN__M 0x3F 4287#define EQ_REG_TD_TPS_LEN__M 0x3F
@@ -4944,7 +4289,6 @@ extern "C" {
4944#define EQ_REG_TD_TPS_LEN_DEF 0x17 4289#define EQ_REG_TD_TPS_LEN_DEF 0x17
4945#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F 4290#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F
4946 4291
4947
4948#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 4292#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053
4949#define EQ_REG_TD_TPS_FRM_NMB__W 2 4293#define EQ_REG_TD_TPS_FRM_NMB__W 2
4950#define EQ_REG_TD_TPS_FRM_NMB__M 0x3 4294#define EQ_REG_TD_TPS_FRM_NMB__M 0x3
@@ -4954,7 +4298,6 @@ extern "C" {
4954#define EQ_REG_TD_TPS_FRM_NMB_3 0x2 4298#define EQ_REG_TD_TPS_FRM_NMB_3 0x2
4955#define EQ_REG_TD_TPS_FRM_NMB_4 0x3 4299#define EQ_REG_TD_TPS_FRM_NMB_4 0x3
4956 4300
4957
4958#define EQ_REG_TD_TPS_CONST__A 0x1C10054 4301#define EQ_REG_TD_TPS_CONST__A 0x1C10054
4959#define EQ_REG_TD_TPS_CONST__W 2 4302#define EQ_REG_TD_TPS_CONST__W 2
4960#define EQ_REG_TD_TPS_CONST__M 0x3 4303#define EQ_REG_TD_TPS_CONST__M 0x3
@@ -4963,7 +4306,6 @@ extern "C" {
4963#define EQ_REG_TD_TPS_CONST_16QAM 0x1 4306#define EQ_REG_TD_TPS_CONST_16QAM 0x1
4964#define EQ_REG_TD_TPS_CONST_64QAM 0x2 4307#define EQ_REG_TD_TPS_CONST_64QAM 0x2
4965 4308
4966
4967#define EQ_REG_TD_TPS_HINFO__A 0x1C10055 4309#define EQ_REG_TD_TPS_HINFO__A 0x1C10055
4968#define EQ_REG_TD_TPS_HINFO__W 3 4310#define EQ_REG_TD_TPS_HINFO__W 3
4969#define EQ_REG_TD_TPS_HINFO__M 0x7 4311#define EQ_REG_TD_TPS_HINFO__M 0x7
@@ -4973,7 +4315,6 @@ extern "C" {
4973#define EQ_REG_TD_TPS_HINFO_H2 0x2 4315#define EQ_REG_TD_TPS_HINFO_H2 0x2
4974#define EQ_REG_TD_TPS_HINFO_H4 0x3 4316#define EQ_REG_TD_TPS_HINFO_H4 0x3
4975 4317
4976
4977#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 4318#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056
4978#define EQ_REG_TD_TPS_CODE_HP__W 3 4319#define EQ_REG_TD_TPS_CODE_HP__W 3
4979#define EQ_REG_TD_TPS_CODE_HP__M 0x7 4320#define EQ_REG_TD_TPS_CODE_HP__M 0x7
@@ -4984,7 +4325,6 @@ extern "C" {
4984#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 4325#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3
4985#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 4326#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4
4986 4327
4987
4988#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 4328#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057
4989#define EQ_REG_TD_TPS_CODE_LP__W 3 4329#define EQ_REG_TD_TPS_CODE_LP__W 3
4990#define EQ_REG_TD_TPS_CODE_LP__M 0x7 4330#define EQ_REG_TD_TPS_CODE_LP__M 0x7
@@ -4995,7 +4335,6 @@ extern "C" {
4995#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 4335#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3
4996#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 4336#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4
4997 4337
4998
4999#define EQ_REG_TD_TPS_GUARD__A 0x1C10058 4338#define EQ_REG_TD_TPS_GUARD__A 0x1C10058
5000#define EQ_REG_TD_TPS_GUARD__W 2 4339#define EQ_REG_TD_TPS_GUARD__W 2
5001#define EQ_REG_TD_TPS_GUARD__M 0x3 4340#define EQ_REG_TD_TPS_GUARD__M 0x3
@@ -5005,7 +4344,6 @@ extern "C" {
5005#define EQ_REG_TD_TPS_GUARD_08 0x2 4344#define EQ_REG_TD_TPS_GUARD_08 0x2
5006#define EQ_REG_TD_TPS_GUARD_04 0x3 4345#define EQ_REG_TD_TPS_GUARD_04 0x3
5007 4346
5008
5009#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 4347#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059
5010#define EQ_REG_TD_TPS_TR_MODE__W 2 4348#define EQ_REG_TD_TPS_TR_MODE__W 2
5011#define EQ_REG_TD_TPS_TR_MODE__M 0x3 4349#define EQ_REG_TD_TPS_TR_MODE__M 0x3
@@ -5013,68 +4351,51 @@ extern "C" {
5013#define EQ_REG_TD_TPS_TR_MODE_2K 0x0 4351#define EQ_REG_TD_TPS_TR_MODE_2K 0x0
5014#define EQ_REG_TD_TPS_TR_MODE_8K 0x1 4352#define EQ_REG_TD_TPS_TR_MODE_8K 0x1
5015 4353
5016
5017#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A 4354#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A
5018#define EQ_REG_TD_TPS_CELL_ID_HI__W 8 4355#define EQ_REG_TD_TPS_CELL_ID_HI__W 8
5019#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF 4356#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF
5020#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 4357#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0
5021 4358
5022
5023#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B 4359#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B
5024#define EQ_REG_TD_TPS_CELL_ID_LO__W 8 4360#define EQ_REG_TD_TPS_CELL_ID_LO__W 8
5025#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF 4361#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF
5026#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 4362#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0
5027 4363
5028
5029#define EQ_REG_TD_TPS_RSV__A 0x1C1005C 4364#define EQ_REG_TD_TPS_RSV__A 0x1C1005C
5030#define EQ_REG_TD_TPS_RSV__W 6 4365#define EQ_REG_TD_TPS_RSV__W 6
5031#define EQ_REG_TD_TPS_RSV__M 0x3F 4366#define EQ_REG_TD_TPS_RSV__M 0x3F
5032#define EQ_REG_TD_TPS_RSV_INIT 0x0 4367#define EQ_REG_TD_TPS_RSV_INIT 0x0
5033 4368
5034
5035#define EQ_REG_TD_TPS_BCH__A 0x1C1005D 4369#define EQ_REG_TD_TPS_BCH__A 0x1C1005D
5036#define EQ_REG_TD_TPS_BCH__W 14 4370#define EQ_REG_TD_TPS_BCH__W 14
5037#define EQ_REG_TD_TPS_BCH__M 0x3FFF 4371#define EQ_REG_TD_TPS_BCH__M 0x3FFF
5038#define EQ_REG_TD_TPS_BCH_INIT 0x0 4372#define EQ_REG_TD_TPS_BCH_INIT 0x0
5039 4373
5040
5041#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E 4374#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E
5042#define EQ_REG_TD_SQR_ERR_I__W 16 4375#define EQ_REG_TD_SQR_ERR_I__W 16
5043#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF 4376#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF
5044#define EQ_REG_TD_SQR_ERR_I_INIT 0x0 4377#define EQ_REG_TD_SQR_ERR_I_INIT 0x0
5045 4378
5046
5047#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F 4379#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F
5048#define EQ_REG_TD_SQR_ERR_Q__W 16 4380#define EQ_REG_TD_SQR_ERR_Q__W 16
5049#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF 4381#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF
5050#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 4382#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0
5051 4383
5052
5053#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 4384#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060
5054#define EQ_REG_TD_SQR_ERR_EXP__W 4 4385#define EQ_REG_TD_SQR_ERR_EXP__W 4
5055#define EQ_REG_TD_SQR_ERR_EXP__M 0xF 4386#define EQ_REG_TD_SQR_ERR_EXP__M 0xF
5056#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 4387#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0
5057 4388
5058
5059#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 4389#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
5060#define EQ_REG_TD_REQ_SMB_CNT__W 16 4390#define EQ_REG_TD_REQ_SMB_CNT__W 16
5061#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF 4391#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF
5062#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 4392#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0
5063 4393
5064
5065#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 4394#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
5066#define EQ_REG_TD_TPS_PWR_OFS__W 16 4395#define EQ_REG_TD_TPS_PWR_OFS__W 16
5067#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF 4396#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF
5068#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 4397#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0
5069 4398
5070
5071
5072
5073
5074
5075
5076
5077
5078#define EC_COMM_EXEC__A 0x2000000 4399#define EC_COMM_EXEC__A 0x2000000
5079#define EC_COMM_EXEC__W 3 4400#define EC_COMM_EXEC__W 3
5080#define EC_COMM_EXEC__M 0x7 4401#define EC_COMM_EXEC__M 0x7
@@ -5107,16 +4428,8 @@ extern "C" {
5107#define EC_COMM_INT_MSK__W 16 4428#define EC_COMM_INT_MSK__W 16
5108#define EC_COMM_INT_MSK__M 0xFFFF 4429#define EC_COMM_INT_MSK__M 0xFFFF
5109 4430
5110
5111
5112
5113
5114#define EC_SB_SID 0x16 4431#define EC_SB_SID 0x16
5115 4432
5116
5117
5118
5119
5120#define EC_SB_REG_COMM_EXEC__A 0x2010000 4433#define EC_SB_REG_COMM_EXEC__A 0x2010000
5121#define EC_SB_REG_COMM_EXEC__W 3 4434#define EC_SB_REG_COMM_EXEC__W 3
5122#define EC_SB_REG_COMM_EXEC__M 0x7 4435#define EC_SB_REG_COMM_EXEC__M 0x7
@@ -5144,7 +4457,6 @@ extern "C" {
5144#define EC_SB_REG_COMM_MB_OBS_OFF 0x0 4457#define EC_SB_REG_COMM_MB_OBS_OFF 0x0
5145#define EC_SB_REG_COMM_MB_OBS_ON 0x2 4458#define EC_SB_REG_COMM_MB_OBS_ON 0x2
5146 4459
5147
5148#define EC_SB_REG_TR_MODE__A 0x2010010 4460#define EC_SB_REG_TR_MODE__A 0x2010010
5149#define EC_SB_REG_TR_MODE__W 1 4461#define EC_SB_REG_TR_MODE__W 1
5150#define EC_SB_REG_TR_MODE__M 0x1 4462#define EC_SB_REG_TR_MODE__M 0x1
@@ -5152,7 +4464,6 @@ extern "C" {
5152#define EC_SB_REG_TR_MODE_8K 0x0 4464#define EC_SB_REG_TR_MODE_8K 0x0
5153#define EC_SB_REG_TR_MODE_2K 0x1 4465#define EC_SB_REG_TR_MODE_2K 0x1
5154 4466
5155
5156#define EC_SB_REG_CONST__A 0x2010011 4467#define EC_SB_REG_CONST__A 0x2010011
5157#define EC_SB_REG_CONST__W 2 4468#define EC_SB_REG_CONST__W 2
5158#define EC_SB_REG_CONST__M 0x3 4469#define EC_SB_REG_CONST__M 0x3
@@ -5161,7 +4472,6 @@ extern "C" {
5161#define EC_SB_REG_CONST_16QAM 0x1 4472#define EC_SB_REG_CONST_16QAM 0x1
5162#define EC_SB_REG_CONST_64QAM 0x2 4473#define EC_SB_REG_CONST_64QAM 0x2
5163 4474
5164
5165#define EC_SB_REG_ALPHA__A 0x2010012 4475#define EC_SB_REG_ALPHA__A 0x2010012
5166#define EC_SB_REG_ALPHA__W 3 4476#define EC_SB_REG_ALPHA__W 3
5167#define EC_SB_REG_ALPHA__M 0x7 4477#define EC_SB_REG_ALPHA__M 0x7
@@ -5176,7 +4486,6 @@ extern "C" {
5176 4486
5177#define EC_SB_REG_ALPHA_H4 0x3 4487#define EC_SB_REG_ALPHA_H4 0x3
5178 4488
5179
5180#define EC_SB_REG_PRIOR__A 0x2010013 4489#define EC_SB_REG_PRIOR__A 0x2010013
5181#define EC_SB_REG_PRIOR__W 1 4490#define EC_SB_REG_PRIOR__W 1
5182#define EC_SB_REG_PRIOR__M 0x1 4491#define EC_SB_REG_PRIOR__M 0x1
@@ -5184,7 +4493,6 @@ extern "C" {
5184#define EC_SB_REG_PRIOR_HI 0x0 4493#define EC_SB_REG_PRIOR_HI 0x0
5185#define EC_SB_REG_PRIOR_LO 0x1 4494#define EC_SB_REG_PRIOR_LO 0x1
5186 4495
5187
5188#define EC_SB_REG_CSI_HI__A 0x2010014 4496#define EC_SB_REG_CSI_HI__A 0x2010014
5189#define EC_SB_REG_CSI_HI__W 5 4497#define EC_SB_REG_CSI_HI__W 5
5190#define EC_SB_REG_CSI_HI__M 0x1F 4498#define EC_SB_REG_CSI_HI__M 0x1F
@@ -5193,7 +4501,6 @@ extern "C" {
5193#define EC_SB_REG_CSI_HI_MIN 0x0 4501#define EC_SB_REG_CSI_HI_MIN 0x0
5194#define EC_SB_REG_CSI_HI_TAG 0x0 4502#define EC_SB_REG_CSI_HI_TAG 0x0
5195 4503
5196
5197#define EC_SB_REG_CSI_LO__A 0x2010015 4504#define EC_SB_REG_CSI_LO__A 0x2010015
5198#define EC_SB_REG_CSI_LO__W 5 4505#define EC_SB_REG_CSI_LO__W 5
5199#define EC_SB_REG_CSI_LO__M 0x1F 4506#define EC_SB_REG_CSI_LO__M 0x1F
@@ -5202,14 +4509,12 @@ extern "C" {
5202#define EC_SB_REG_CSI_LO_MIN 0x0 4509#define EC_SB_REG_CSI_LO_MIN 0x0
5203#define EC_SB_REG_CSI_LO_TAG 0x0 4510#define EC_SB_REG_CSI_LO_TAG 0x0
5204 4511
5205
5206#define EC_SB_REG_SMB_TGL__A 0x2010016 4512#define EC_SB_REG_SMB_TGL__A 0x2010016
5207#define EC_SB_REG_SMB_TGL__W 1 4513#define EC_SB_REG_SMB_TGL__W 1
5208#define EC_SB_REG_SMB_TGL__M 0x1 4514#define EC_SB_REG_SMB_TGL__M 0x1
5209#define EC_SB_REG_SMB_TGL_OFF 0x0 4515#define EC_SB_REG_SMB_TGL_OFF 0x0
5210#define EC_SB_REG_SMB_TGL_ON 0x1 4516#define EC_SB_REG_SMB_TGL_ON 0x1
5211 4517
5212
5213#define EC_SB_REG_SNR_HI__A 0x2010017 4518#define EC_SB_REG_SNR_HI__A 0x2010017
5214#define EC_SB_REG_SNR_HI__W 8 4519#define EC_SB_REG_SNR_HI__W 8
5215#define EC_SB_REG_SNR_HI__M 0xFF 4520#define EC_SB_REG_SNR_HI__M 0xFF
@@ -5218,7 +4523,6 @@ extern "C" {
5218#define EC_SB_REG_SNR_HI_MIN 0x0 4523#define EC_SB_REG_SNR_HI_MIN 0x0
5219#define EC_SB_REG_SNR_HI_TAG 0x0 4524#define EC_SB_REG_SNR_HI_TAG 0x0
5220 4525
5221
5222#define EC_SB_REG_SNR_MID__A 0x2010018 4526#define EC_SB_REG_SNR_MID__A 0x2010018
5223#define EC_SB_REG_SNR_MID__W 8 4527#define EC_SB_REG_SNR_MID__W 8
5224#define EC_SB_REG_SNR_MID__M 0xFF 4528#define EC_SB_REG_SNR_MID__M 0xFF
@@ -5227,7 +4531,6 @@ extern "C" {
5227#define EC_SB_REG_SNR_MID_MIN 0x0 4531#define EC_SB_REG_SNR_MID_MIN 0x0
5228#define EC_SB_REG_SNR_MID_TAG 0x0 4532#define EC_SB_REG_SNR_MID_TAG 0x0
5229 4533
5230
5231#define EC_SB_REG_SNR_LO__A 0x2010019 4534#define EC_SB_REG_SNR_LO__A 0x2010019
5232#define EC_SB_REG_SNR_LO__W 8 4535#define EC_SB_REG_SNR_LO__W 8
5233#define EC_SB_REG_SNR_LO__M 0xFF 4536#define EC_SB_REG_SNR_LO__M 0xFF
@@ -5236,28 +4539,24 @@ extern "C" {
5236#define EC_SB_REG_SNR_LO_MIN 0x0 4539#define EC_SB_REG_SNR_LO_MIN 0x0
5237#define EC_SB_REG_SNR_LO_TAG 0x0 4540#define EC_SB_REG_SNR_LO_TAG 0x0
5238 4541
5239
5240#define EC_SB_REG_SCALE_MSB__A 0x201001A 4542#define EC_SB_REG_SCALE_MSB__A 0x201001A
5241#define EC_SB_REG_SCALE_MSB__W 6 4543#define EC_SB_REG_SCALE_MSB__W 6
5242#define EC_SB_REG_SCALE_MSB__M 0x3F 4544#define EC_SB_REG_SCALE_MSB__M 0x3F
5243#define EC_SB_REG_SCALE_MSB_INIT 0x30 4545#define EC_SB_REG_SCALE_MSB_INIT 0x30
5244#define EC_SB_REG_SCALE_MSB_MAX 0x3F 4546#define EC_SB_REG_SCALE_MSB_MAX 0x3F
5245 4547
5246
5247#define EC_SB_REG_SCALE_BIT2__A 0x201001B 4548#define EC_SB_REG_SCALE_BIT2__A 0x201001B
5248#define EC_SB_REG_SCALE_BIT2__W 6 4549#define EC_SB_REG_SCALE_BIT2__W 6
5249#define EC_SB_REG_SCALE_BIT2__M 0x3F 4550#define EC_SB_REG_SCALE_BIT2__M 0x3F
5250#define EC_SB_REG_SCALE_BIT2_INIT 0x20 4551#define EC_SB_REG_SCALE_BIT2_INIT 0x20
5251#define EC_SB_REG_SCALE_BIT2_MAX 0x3F 4552#define EC_SB_REG_SCALE_BIT2_MAX 0x3F
5252 4553
5253
5254#define EC_SB_REG_SCALE_LSB__A 0x201001C 4554#define EC_SB_REG_SCALE_LSB__A 0x201001C
5255#define EC_SB_REG_SCALE_LSB__W 6 4555#define EC_SB_REG_SCALE_LSB__W 6
5256#define EC_SB_REG_SCALE_LSB__M 0x3F 4556#define EC_SB_REG_SCALE_LSB__M 0x3F
5257#define EC_SB_REG_SCALE_LSB_INIT 0x10 4557#define EC_SB_REG_SCALE_LSB_INIT 0x10
5258#define EC_SB_REG_SCALE_LSB_MAX 0x3F 4558#define EC_SB_REG_SCALE_LSB_MAX 0x3F
5259 4559
5260
5261#define EC_SB_REG_CSI_OFS__A 0x201001D 4560#define EC_SB_REG_CSI_OFS__A 0x201001D
5262#define EC_SB_REG_CSI_OFS__W 4 4561#define EC_SB_REG_CSI_OFS__W 4
5263#define EC_SB_REG_CSI_OFS__M 0xF 4562#define EC_SB_REG_CSI_OFS__M 0xF
@@ -5271,28 +4570,14 @@ extern "C" {
5271#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 4570#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0
5272#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 4571#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8
5273 4572
5274
5275
5276#define EC_SB_SD_RAM__A 0x2020000 4573#define EC_SB_SD_RAM__A 0x2020000
5277 4574
5278
5279
5280#define EC_SB_BD0_RAM__A 0x2030000 4575#define EC_SB_BD0_RAM__A 0x2030000
5281 4576
5282
5283
5284#define EC_SB_BD1_RAM__A 0x2040000 4577#define EC_SB_BD1_RAM__A 0x2040000
5285 4578
5286
5287
5288
5289
5290#define EC_VD_SID 0x17 4579#define EC_VD_SID 0x17
5291 4580
5292
5293
5294
5295
5296#define EC_VD_REG_COMM_EXEC__A 0x2090000 4581#define EC_VD_REG_COMM_EXEC__A 0x2090000
5297#define EC_VD_REG_COMM_EXEC__W 3 4582#define EC_VD_REG_COMM_EXEC__W 3
5298#define EC_VD_REG_COMM_EXEC__M 0x7 4583#define EC_VD_REG_COMM_EXEC__M 0x7
@@ -5340,7 +4625,6 @@ extern "C" {
5340#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 4625#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1
5341#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 4626#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1
5342 4627
5343
5344#define EC_VD_REG_FORCE__A 0x2090010 4628#define EC_VD_REG_FORCE__A 0x2090010
5345#define EC_VD_REG_FORCE__W 2 4629#define EC_VD_REG_FORCE__W 2
5346#define EC_VD_REG_FORCE__M 0x3 4630#define EC_VD_REG_FORCE__M 0x3
@@ -5350,7 +4634,6 @@ extern "C" {
5350#define EC_VD_REG_FORCE_FORCED 0x2 4634#define EC_VD_REG_FORCE_FORCED 0x2
5351#define EC_VD_REG_FORCE_FIXED 0x3 4635#define EC_VD_REG_FORCE_FIXED 0x3
5352 4636
5353
5354#define EC_VD_REG_SET_CODERATE__A 0x2090011 4637#define EC_VD_REG_SET_CODERATE__A 0x2090011
5355#define EC_VD_REG_SET_CODERATE__W 3 4638#define EC_VD_REG_SET_CODERATE__W 3
5356#define EC_VD_REG_SET_CODERATE__M 0x7 4639#define EC_VD_REG_SET_CODERATE__M 0x7
@@ -5361,19 +4644,16 @@ extern "C" {
5361#define EC_VD_REG_SET_CODERATE_C5_6 0x3 4644#define EC_VD_REG_SET_CODERATE_C5_6 0x3
5362#define EC_VD_REG_SET_CODERATE_C7_8 0x4 4645#define EC_VD_REG_SET_CODERATE_C7_8 0x4
5363 4646
5364
5365#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 4647#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012
5366#define EC_VD_REG_REQ_SMB_CNT__W 16 4648#define EC_VD_REG_REQ_SMB_CNT__W 16
5367#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF 4649#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF
5368#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 4650#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0
5369 4651
5370
5371#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 4652#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013
5372#define EC_VD_REG_REQ_BIT_CNT__W 16 4653#define EC_VD_REG_REQ_BIT_CNT__W 16
5373#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF 4654#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF
5374#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF 4655#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF
5375 4656
5376
5377#define EC_VD_REG_RLK_ENA__A 0x2090014 4657#define EC_VD_REG_RLK_ENA__A 0x2090014
5378#define EC_VD_REG_RLK_ENA__W 1 4658#define EC_VD_REG_RLK_ENA__W 1
5379#define EC_VD_REG_RLK_ENA__M 0x1 4659#define EC_VD_REG_RLK_ENA__M 0x1
@@ -5381,7 +4661,6 @@ extern "C" {
5381#define EC_VD_REG_RLK_ENA_OFF 0x0 4661#define EC_VD_REG_RLK_ENA_OFF 0x0
5382#define EC_VD_REG_RLK_ENA_ON 0x1 4662#define EC_VD_REG_RLK_ENA_ON 0x1
5383 4663
5384
5385#define EC_VD_REG_VAL__A 0x2090015 4664#define EC_VD_REG_VAL__A 0x2090015
5386#define EC_VD_REG_VAL__W 2 4665#define EC_VD_REG_VAL__W 2
5387#define EC_VD_REG_VAL__M 0x3 4666#define EC_VD_REG_VAL__M 0x3
@@ -5389,7 +4668,6 @@ extern "C" {
5389#define EC_VD_REG_VAL_CODE 0x1 4668#define EC_VD_REG_VAL_CODE 0x1
5390#define EC_VD_REG_VAL_CNT 0x2 4669#define EC_VD_REG_VAL_CNT 0x2
5391 4670
5392
5393#define EC_VD_REG_GET_CODERATE__A 0x2090016 4671#define EC_VD_REG_GET_CODERATE__A 0x2090016
5394#define EC_VD_REG_GET_CODERATE__W 3 4672#define EC_VD_REG_GET_CODERATE__W 3
5395#define EC_VD_REG_GET_CODERATE__M 0x7 4673#define EC_VD_REG_GET_CODERATE__M 0x7
@@ -5400,19 +4678,16 @@ extern "C" {
5400#define EC_VD_REG_GET_CODERATE_C5_6 0x3 4678#define EC_VD_REG_GET_CODERATE_C5_6 0x3
5401#define EC_VD_REG_GET_CODERATE_C7_8 0x4 4679#define EC_VD_REG_GET_CODERATE_C7_8 0x4
5402 4680
5403
5404#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 4681#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017
5405#define EC_VD_REG_ERR_BIT_CNT__W 16 4682#define EC_VD_REG_ERR_BIT_CNT__W 16
5406#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF 4683#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF
5407#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF 4684#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF
5408 4685
5409
5410#define EC_VD_REG_IN_BIT_CNT__A 0x2090018 4686#define EC_VD_REG_IN_BIT_CNT__A 0x2090018
5411#define EC_VD_REG_IN_BIT_CNT__W 16 4687#define EC_VD_REG_IN_BIT_CNT__W 16
5412#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF 4688#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF
5413#define EC_VD_REG_IN_BIT_CNT_INIT 0x0 4689#define EC_VD_REG_IN_BIT_CNT_INIT 0x0
5414 4690
5415
5416#define EC_VD_REG_STS__A 0x2090019 4691#define EC_VD_REG_STS__A 0x2090019
5417#define EC_VD_REG_STS__W 1 4692#define EC_VD_REG_STS__W 1
5418#define EC_VD_REG_STS__M 0x1 4693#define EC_VD_REG_STS__M 0x1
@@ -5420,43 +4695,23 @@ extern "C" {
5420#define EC_VD_REG_STS_NO_LOCK 0x0 4695#define EC_VD_REG_STS_NO_LOCK 0x0
5421#define EC_VD_REG_STS_IN_LOCK 0x1 4696#define EC_VD_REG_STS_IN_LOCK 0x1
5422 4697
5423
5424#define EC_VD_REG_RLK_CNT__A 0x209001A 4698#define EC_VD_REG_RLK_CNT__A 0x209001A
5425#define EC_VD_REG_RLK_CNT__W 16 4699#define EC_VD_REG_RLK_CNT__W 16
5426#define EC_VD_REG_RLK_CNT__M 0xFFFF 4700#define EC_VD_REG_RLK_CNT__M 0xFFFF
5427#define EC_VD_REG_RLK_CNT_INIT 0x0 4701#define EC_VD_REG_RLK_CNT_INIT 0x0
5428 4702
5429
5430
5431#define EC_VD_TB0_RAM__A 0x20A0000 4703#define EC_VD_TB0_RAM__A 0x20A0000
5432 4704
5433
5434
5435#define EC_VD_TB1_RAM__A 0x20B0000 4705#define EC_VD_TB1_RAM__A 0x20B0000
5436 4706
5437
5438
5439#define EC_VD_TB2_RAM__A 0x20C0000 4707#define EC_VD_TB2_RAM__A 0x20C0000
5440 4708
5441
5442
5443#define EC_VD_TB3_RAM__A 0x20D0000 4709#define EC_VD_TB3_RAM__A 0x20D0000
5444 4710
5445
5446
5447#define EC_VD_RE_RAM__A 0x2100000 4711#define EC_VD_RE_RAM__A 0x2100000
5448 4712
5449
5450
5451
5452
5453#define EC_OD_SID 0x18 4713#define EC_OD_SID 0x18
5454 4714
5455
5456
5457
5458
5459
5460#define EC_OD_REG_COMM_EXEC__A 0x2110000 4715#define EC_OD_REG_COMM_EXEC__A 0x2110000
5461#define EC_OD_REG_COMM_EXEC__W 3 4716#define EC_OD_REG_COMM_EXEC__W 3
5462#define EC_OD_REG_COMM_EXEC__M 0x7 4717#define EC_OD_REG_COMM_EXEC__M 0x7
@@ -5468,7 +4723,6 @@ extern "C" {
5468#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 4723#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2
5469#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 4724#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3
5470 4725
5471
5472#define EC_OD_REG_COMM_MB__A 0x2110002 4726#define EC_OD_REG_COMM_MB__A 0x2110002
5473#define EC_OD_REG_COMM_MB__W 3 4727#define EC_OD_REG_COMM_MB__W 3
5474#define EC_OD_REG_COMM_MB__M 0x7 4728#define EC_OD_REG_COMM_MB__M 0x7
@@ -5508,7 +4762,6 @@ extern "C" {
5508#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 4762#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1
5509#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 4763#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2
5510 4764
5511
5512#define EC_OD_REG_COMM_INT_MSK__A 0x2110008 4765#define EC_OD_REG_COMM_INT_MSK__A 0x2110008
5513#define EC_OD_REG_COMM_INT_MSK__W 2 4766#define EC_OD_REG_COMM_INT_MSK__W 2
5514#define EC_OD_REG_COMM_INT_MSK__M 0x3 4767#define EC_OD_REG_COMM_INT_MSK__M 0x3
@@ -5519,7 +4772,6 @@ extern "C" {
5519#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 4772#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1
5520#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 4773#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2
5521 4774
5522
5523#define EC_OD_REG_SYNC__A 0x2110010 4775#define EC_OD_REG_SYNC__A 0x2110010
5524#define EC_OD_REG_SYNC__W 12 4776#define EC_OD_REG_SYNC__W 12
5525#define EC_OD_REG_SYNC__M 0xFFF 4777#define EC_OD_REG_SYNC__M 0xFFF
@@ -5533,25 +4785,14 @@ extern "C" {
5533#define EC_OD_REG_SYNC_OUT_SYNC__W 3 4785#define EC_OD_REG_SYNC_OUT_SYNC__W 3
5534#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 4786#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00
5535 4787
5536
5537#define EC_OD_REG_NOSYNC__A 0x2110011 4788#define EC_OD_REG_NOSYNC__A 0x2110011
5538#define EC_OD_REG_NOSYNC__W 8 4789#define EC_OD_REG_NOSYNC__W 8
5539#define EC_OD_REG_NOSYNC__M 0xFF 4790#define EC_OD_REG_NOSYNC__M 0xFF
5540 4791
5541
5542
5543#define EC_OD_DEINT_RAM__A 0x2120000 4792#define EC_OD_DEINT_RAM__A 0x2120000
5544 4793
5545
5546
5547
5548
5549#define EC_RS_SID 0x19 4794#define EC_RS_SID 0x19
5550 4795
5551
5552
5553
5554
5555#define EC_RS_REG_COMM_EXEC__A 0x2130000 4796#define EC_RS_REG_COMM_EXEC__A 0x2130000
5556#define EC_RS_REG_COMM_EXEC__W 3 4797#define EC_RS_REG_COMM_EXEC__W 3
5557#define EC_RS_REG_COMM_EXEC__M 0x7 4798#define EC_RS_REG_COMM_EXEC__M 0x7
@@ -5599,58 +4840,41 @@ extern "C" {
5599#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 4840#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1
5600#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 4841#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1
5601 4842
5602
5603#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 4843#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010
5604#define EC_RS_REG_REQ_PCK_CNT__W 16 4844#define EC_RS_REG_REQ_PCK_CNT__W 16
5605#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF 4845#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF
5606#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF 4846#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF
5607 4847
5608
5609#define EC_RS_REG_VAL__A 0x2130011 4848#define EC_RS_REG_VAL__A 0x2130011
5610#define EC_RS_REG_VAL__W 1 4849#define EC_RS_REG_VAL__W 1
5611#define EC_RS_REG_VAL__M 0x1 4850#define EC_RS_REG_VAL__M 0x1
5612#define EC_RS_REG_VAL_INIT 0x0 4851#define EC_RS_REG_VAL_INIT 0x0
5613#define EC_RS_REG_VAL_PCK 0x1 4852#define EC_RS_REG_VAL_PCK 0x1
5614 4853
5615
5616#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 4854#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012
5617#define EC_RS_REG_ERR_PCK_CNT__W 16 4855#define EC_RS_REG_ERR_PCK_CNT__W 16
5618#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF 4856#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF
5619#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF 4857#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF
5620 4858
5621
5622#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 4859#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013
5623#define EC_RS_REG_ERR_SMB_CNT__W 16 4860#define EC_RS_REG_ERR_SMB_CNT__W 16
5624#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF 4861#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF
5625#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF 4862#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF
5626 4863
5627
5628#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 4864#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014
5629#define EC_RS_REG_ERR_BIT_CNT__W 16 4865#define EC_RS_REG_ERR_BIT_CNT__W 16
5630#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF 4866#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF
5631#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF 4867#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF
5632 4868
5633
5634#define EC_RS_REG_IN_PCK_CNT__A 0x2130015 4869#define EC_RS_REG_IN_PCK_CNT__A 0x2130015
5635#define EC_RS_REG_IN_PCK_CNT__W 16 4870#define EC_RS_REG_IN_PCK_CNT__W 16
5636#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF 4871#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF
5637#define EC_RS_REG_IN_PCK_CNT_INIT 0x0 4872#define EC_RS_REG_IN_PCK_CNT_INIT 0x0
5638 4873
5639
5640
5641#define EC_RS_EC_RAM__A 0x2140000 4874#define EC_RS_EC_RAM__A 0x2140000
5642 4875
5643
5644
5645
5646
5647#define EC_OC_SID 0x1A 4876#define EC_OC_SID 0x1A
5648 4877
5649
5650
5651
5652
5653
5654#define EC_OC_REG_COMM_EXEC__A 0x2150000 4878#define EC_OC_REG_COMM_EXEC__A 0x2150000
5655#define EC_OC_REG_COMM_EXEC__W 3 4879#define EC_OC_REG_COMM_EXEC__W 3
5656#define EC_OC_REG_COMM_EXEC__M 0x7 4880#define EC_OC_REG_COMM_EXEC__M 0x7
@@ -5680,7 +4904,6 @@ extern "C" {
5680#define EC_OC_REG_COMM_MB_OBS_OFF 0x0 4904#define EC_OC_REG_COMM_MB_OBS_OFF 0x0
5681#define EC_OC_REG_COMM_MB_OBS_ON 0x2 4905#define EC_OC_REG_COMM_MB_OBS_ON 0x2
5682 4906
5683
5684#define EC_OC_REG_COMM_SERVICE0__A 0x2150003 4907#define EC_OC_REG_COMM_SERVICE0__A 0x2150003
5685#define EC_OC_REG_COMM_SERVICE0__W 10 4908#define EC_OC_REG_COMM_SERVICE0__W 10
5686#define EC_OC_REG_COMM_SERVICE0__M 0x3FF 4909#define EC_OC_REG_COMM_SERVICE0__M 0x3FF
@@ -5711,7 +4934,6 @@ extern "C" {
5711#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 4934#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1
5712#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 4935#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20
5713 4936
5714
5715#define EC_OC_REG_COMM_INT_MSK__A 0x2150008 4937#define EC_OC_REG_COMM_INT_MSK__A 0x2150008
5716#define EC_OC_REG_COMM_INT_MSK__W 6 4938#define EC_OC_REG_COMM_INT_MSK__W 6
5717#define EC_OC_REG_COMM_INT_MSK__M 0x3F 4939#define EC_OC_REG_COMM_INT_MSK__M 0x3F
@@ -5734,7 +4956,6 @@ extern "C" {
5734#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 4956#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1
5735#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 4957#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20
5736 4958
5737
5738#define EC_OC_REG_OC_MODE_LOP__A 0x2150010 4959#define EC_OC_REG_OC_MODE_LOP__A 0x2150010
5739#define EC_OC_REG_OC_MODE_LOP__W 16 4960#define EC_OC_REG_OC_MODE_LOP__W 16
5740#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF 4961#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF
@@ -5824,7 +5045,6 @@ extern "C" {
5824#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 5045#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0
5825#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 5046#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000
5826 5047
5827
5828#define EC_OC_REG_OC_MODE_HIP__A 0x2150011 5048#define EC_OC_REG_OC_MODE_HIP__A 0x2150011
5829#define EC_OC_REG_OC_MODE_HIP__W 14 5049#define EC_OC_REG_OC_MODE_HIP__W 14
5830#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF 5050#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF
@@ -5914,7 +5134,6 @@ extern "C" {
5914#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 5134#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0
5915#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 5135#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000
5916 5136
5917
5918#define EC_OC_REG_OC_MPG_SIO__A 0x2150012 5137#define EC_OC_REG_OC_MPG_SIO__A 0x2150012
5919#define EC_OC_REG_OC_MPG_SIO__W 12 5138#define EC_OC_REG_OC_MPG_SIO__W 12
5920#define EC_OC_REG_OC_MPG_SIO__M 0xFFF 5139#define EC_OC_REG_OC_MPG_SIO__M 0xFFF
@@ -5992,7 +5211,6 @@ extern "C" {
5992#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 5211#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0
5993#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 5212#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800
5994 5213
5995
5996#define EC_OC_REG_OC_MON_SIO__A 0x2150013 5214#define EC_OC_REG_OC_MON_SIO__A 0x2150013
5997#define EC_OC_REG_OC_MON_SIO__W 12 5215#define EC_OC_REG_OC_MON_SIO__W 12
5998#define EC_OC_REG_OC_MON_SIO__M 0xFFF 5216#define EC_OC_REG_OC_MON_SIO__M 0xFFF
@@ -6070,19 +5288,16 @@ extern "C" {
6070#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 5288#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0
6071#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 5289#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800
6072 5290
6073
6074#define EC_OC_REG_DTO_INC_LOP__A 0x2150014 5291#define EC_OC_REG_DTO_INC_LOP__A 0x2150014
6075#define EC_OC_REG_DTO_INC_LOP__W 16 5292#define EC_OC_REG_DTO_INC_LOP__W 16
6076#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF 5293#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF
6077#define EC_OC_REG_DTO_INC_LOP_INIT 0x0 5294#define EC_OC_REG_DTO_INC_LOP_INIT 0x0
6078 5295
6079
6080#define EC_OC_REG_DTO_INC_HIP__A 0x2150015 5296#define EC_OC_REG_DTO_INC_HIP__A 0x2150015
6081#define EC_OC_REG_DTO_INC_HIP__W 8 5297#define EC_OC_REG_DTO_INC_HIP__W 8
6082#define EC_OC_REG_DTO_INC_HIP__M 0xFF 5298#define EC_OC_REG_DTO_INC_HIP__M 0xFF
6083#define EC_OC_REG_DTO_INC_HIP_INIT 0x0 5299#define EC_OC_REG_DTO_INC_HIP_INIT 0x0
6084 5300
6085
6086#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 5301#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016
6087#define EC_OC_REG_SNC_ISC_LVL__W 12 5302#define EC_OC_REG_SNC_ISC_LVL__W 12
6088#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF 5303#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF
@@ -6100,13 +5315,11 @@ extern "C" {
6100#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 5315#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4
6101#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 5316#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00
6102 5317
6103
6104#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 5318#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017
6105#define EC_OC_REG_SNC_NSC_LVL__W 8 5319#define EC_OC_REG_SNC_NSC_LVL__W 8
6106#define EC_OC_REG_SNC_NSC_LVL__M 0xFF 5320#define EC_OC_REG_SNC_NSC_LVL__M 0xFF
6107#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 5321#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0
6108 5322
6109
6110#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 5323#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019
6111#define EC_OC_REG_SNC_SNC_MODE__W 2 5324#define EC_OC_REG_SNC_SNC_MODE__W 2
6112#define EC_OC_REG_SNC_SNC_MODE__M 0x3 5325#define EC_OC_REG_SNC_SNC_MODE__M 0x3
@@ -6114,7 +5327,6 @@ extern "C" {
6114#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 5327#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1
6115#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 5328#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2
6116 5329
6117
6118#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A 5330#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A
6119#define EC_OC_REG_SNC_PCK_NMB__W 16 5331#define EC_OC_REG_SNC_PCK_NMB__W 16
6120#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF 5332#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF
@@ -6136,49 +5348,41 @@ extern "C" {
6136#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 5348#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2
6137#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 5349#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3
6138 5350
6139
6140#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E 5351#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E
6141#define EC_OC_REG_TMD_TOP_CNT__W 10 5352#define EC_OC_REG_TMD_TOP_CNT__W 10
6142#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF 5353#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF
6143#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 5354#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0
6144 5355
6145
6146#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F 5356#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F
6147#define EC_OC_REG_TMD_HIL_MAR__W 10 5357#define EC_OC_REG_TMD_HIL_MAR__W 10
6148#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF 5358#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF
6149#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 5359#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0
6150 5360
6151
6152#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 5361#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020
6153#define EC_OC_REG_TMD_LOL_MAR__W 10 5362#define EC_OC_REG_TMD_LOL_MAR__W 10
6154#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF 5363#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF
6155#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 5364#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0
6156 5365
6157
6158#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 5366#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021
6159#define EC_OC_REG_TMD_CUR_CNT__W 4 5367#define EC_OC_REG_TMD_CUR_CNT__W 4
6160#define EC_OC_REG_TMD_CUR_CNT__M 0xF 5368#define EC_OC_REG_TMD_CUR_CNT__M 0xF
6161#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 5369#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0
6162 5370
6163
6164#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 5371#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022
6165#define EC_OC_REG_TMD_IUR_CNT__W 4 5372#define EC_OC_REG_TMD_IUR_CNT__W 4
6166#define EC_OC_REG_TMD_IUR_CNT__M 0xF 5373#define EC_OC_REG_TMD_IUR_CNT__M 0xF
6167#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 5374#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0
6168 5375
6169
6170#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 5376#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023
6171#define EC_OC_REG_AVR_ASH_CNT__W 4 5377#define EC_OC_REG_AVR_ASH_CNT__W 4
6172#define EC_OC_REG_AVR_ASH_CNT__M 0xF 5378#define EC_OC_REG_AVR_ASH_CNT__M 0xF
6173#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 5379#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0
6174 5380
6175
6176#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 5381#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024
6177#define EC_OC_REG_AVR_BSH_CNT__W 4 5382#define EC_OC_REG_AVR_BSH_CNT__W 4
6178#define EC_OC_REG_AVR_BSH_CNT__M 0xF 5383#define EC_OC_REG_AVR_BSH_CNT__M 0xF
6179#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 5384#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0
6180 5385
6181
6182#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 5386#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025
6183#define EC_OC_REG_AVR_AVE_LOP__W 16 5387#define EC_OC_REG_AVR_AVE_LOP__W 16
6184#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF 5388#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF
@@ -6210,43 +5414,36 @@ extern "C" {
6210#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 5414#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4
6211#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 5415#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0
6212 5416
6213
6214#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 5417#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028
6215#define EC_OC_REG_RCN_CRA_LOP__W 16 5418#define EC_OC_REG_RCN_CRA_LOP__W 16
6216#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF 5419#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF
6217#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 5420#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0
6218 5421
6219
6220#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 5422#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029
6221#define EC_OC_REG_RCN_CRA_HIP__W 8 5423#define EC_OC_REG_RCN_CRA_HIP__W 8
6222#define EC_OC_REG_RCN_CRA_HIP__M 0xFF 5424#define EC_OC_REG_RCN_CRA_HIP__M 0xFF
6223#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 5425#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0
6224 5426
6225
6226#define EC_OC_REG_RCN_CST_LOP__A 0x215002A 5427#define EC_OC_REG_RCN_CST_LOP__A 0x215002A
6227#define EC_OC_REG_RCN_CST_LOP__W 16 5428#define EC_OC_REG_RCN_CST_LOP__W 16
6228#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF 5429#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF
6229#define EC_OC_REG_RCN_CST_LOP_INIT 0x0 5430#define EC_OC_REG_RCN_CST_LOP_INIT 0x0
6230 5431
6231
6232#define EC_OC_REG_RCN_CST_HIP__A 0x215002B 5432#define EC_OC_REG_RCN_CST_HIP__A 0x215002B
6233#define EC_OC_REG_RCN_CST_HIP__W 8 5433#define EC_OC_REG_RCN_CST_HIP__W 8
6234#define EC_OC_REG_RCN_CST_HIP__M 0xFF 5434#define EC_OC_REG_RCN_CST_HIP__M 0xFF
6235#define EC_OC_REG_RCN_CST_HIP_INIT 0x0 5435#define EC_OC_REG_RCN_CST_HIP_INIT 0x0
6236 5436
6237
6238#define EC_OC_REG_RCN_SET_LVL__A 0x215002C 5437#define EC_OC_REG_RCN_SET_LVL__A 0x215002C
6239#define EC_OC_REG_RCN_SET_LVL__W 9 5438#define EC_OC_REG_RCN_SET_LVL__W 9
6240#define EC_OC_REG_RCN_SET_LVL__M 0x1FF 5439#define EC_OC_REG_RCN_SET_LVL__M 0x1FF
6241#define EC_OC_REG_RCN_SET_LVL_INIT 0x0 5440#define EC_OC_REG_RCN_SET_LVL_INIT 0x0
6242 5441
6243
6244#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D 5442#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D
6245#define EC_OC_REG_RCN_GAI_LVL__W 4 5443#define EC_OC_REG_RCN_GAI_LVL__W 4
6246#define EC_OC_REG_RCN_GAI_LVL__M 0xF 5444#define EC_OC_REG_RCN_GAI_LVL__M 0xF
6247#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 5445#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0
6248 5446
6249
6250#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E 5447#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E
6251#define EC_OC_REG_RCN_DRA_LOP__W 16 5448#define EC_OC_REG_RCN_DRA_LOP__W 16
6252#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF 5449#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF
@@ -6268,13 +5465,11 @@ extern "C" {
6268#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF 5465#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF
6269#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF 5466#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF
6270 5467
6271
6272#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 5468#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033
6273#define EC_OC_REG_RCN_CLP_HIP__W 8 5469#define EC_OC_REG_RCN_CLP_HIP__W 8
6274#define EC_OC_REG_RCN_CLP_HIP__M 0xFF 5470#define EC_OC_REG_RCN_CLP_HIP__M 0xFF
6275#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF 5471#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF
6276 5472
6277
6278#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 5473#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034
6279#define EC_OC_REG_RCN_MAP_LOP__W 16 5474#define EC_OC_REG_RCN_MAP_LOP__W 16
6280#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF 5475#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF
@@ -6360,7 +5555,6 @@ extern "C" {
6360#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 5555#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0
6361#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 5556#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800
6362 5557
6363
6364#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 5558#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037
6365#define EC_OC_REG_OCR_MPG_WRI__W 12 5559#define EC_OC_REG_OCR_MPG_WRI__W 12
6366#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF 5560#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF
@@ -6426,7 +5620,6 @@ extern "C" {
6426#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 5620#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0
6427#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 5621#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800
6428 5622
6429
6430#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 5623#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
6431#define EC_OC_REG_OCR_MPG_USR_DAT__W 12 5624#define EC_OC_REG_OCR_MPG_USR_DAT__W 12
6432#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF 5625#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF
@@ -6508,7 +5701,6 @@ extern "C" {
6508#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 5701#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0
6509#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 5702#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800
6510 5703
6511
6512#define EC_OC_REG_OCR_MON_WRI__A 0x215003A 5704#define EC_OC_REG_OCR_MON_WRI__A 0x215003A
6513#define EC_OC_REG_OCR_MON_WRI__W 12 5705#define EC_OC_REG_OCR_MON_WRI__W 12
6514#define EC_OC_REG_OCR_MON_WRI__M 0xFFF 5706#define EC_OC_REG_OCR_MON_WRI__M 0xFFF
@@ -6574,7 +5766,6 @@ extern "C" {
6574#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 5766#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0
6575#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 5767#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800
6576 5768
6577
6578#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B 5769#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B
6579#define EC_OC_REG_OCR_MON_USR_DAT__W 12 5770#define EC_OC_REG_OCR_MON_USR_DAT__W 12
6580#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF 5771#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF
@@ -6584,13 +5775,11 @@ extern "C" {
6584#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF 5775#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF
6585#define EC_OC_REG_OCR_MON_CNT_INIT 0x0 5776#define EC_OC_REG_OCR_MON_CNT_INIT 0x0
6586 5777
6587
6588#define EC_OC_REG_OCR_MON_RDX__A 0x215003D 5778#define EC_OC_REG_OCR_MON_RDX__A 0x215003D
6589#define EC_OC_REG_OCR_MON_RDX__W 1 5779#define EC_OC_REG_OCR_MON_RDX__W 1
6590#define EC_OC_REG_OCR_MON_RDX__M 0x1 5780#define EC_OC_REG_OCR_MON_RDX__M 0x1
6591#define EC_OC_REG_OCR_MON_RDX_INIT 0x0 5781#define EC_OC_REG_OCR_MON_RDX_INIT 0x0
6592 5782
6593
6594#define EC_OC_REG_OCR_MON_RD0__A 0x215003E 5783#define EC_OC_REG_OCR_MON_RD0__A 0x215003E
6595#define EC_OC_REG_OCR_MON_RD0__W 10 5784#define EC_OC_REG_OCR_MON_RD0__W 10
6596#define EC_OC_REG_OCR_MON_RD0__M 0x3FF 5785#define EC_OC_REG_OCR_MON_RD0__M 0x3FF
@@ -6620,32 +5809,20 @@ extern "C" {
6620#define EC_OC_REG_OCR_INV_MON__M 0xFFF 5809#define EC_OC_REG_OCR_INV_MON__M 0xFFF
6621#define EC_OC_REG_OCR_INV_MON_INIT 0x0 5810#define EC_OC_REG_OCR_INV_MON_INIT 0x0
6622 5811
6623
6624#define EC_OC_REG_IPR_INV_MPG__A 0x2150045 5812#define EC_OC_REG_IPR_INV_MPG__A 0x2150045
6625#define EC_OC_REG_IPR_INV_MPG__W 12 5813#define EC_OC_REG_IPR_INV_MPG__W 12
6626#define EC_OC_REG_IPR_INV_MPG__M 0xFFF 5814#define EC_OC_REG_IPR_INV_MPG__M 0xFFF
6627#define EC_OC_REG_IPR_INV_MPG_INIT 0x0 5815#define EC_OC_REG_IPR_INV_MPG_INIT 0x0
6628 5816
6629
6630#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 5817#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046
6631#define EC_OC_REG_IPR_MSR_SNC__W 6 5818#define EC_OC_REG_IPR_MSR_SNC__W 6
6632#define EC_OC_REG_IPR_MSR_SNC__M 0x3F 5819#define EC_OC_REG_IPR_MSR_SNC__M 0x3F
6633#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 5820#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0
6634 5821
6635
6636
6637#define EC_OC_RAM__A 0x2160000 5822#define EC_OC_RAM__A 0x2160000
6638 5823
6639
6640
6641
6642
6643#define CC_SID 0x1B 5824#define CC_SID 0x1B
6644 5825
6645
6646
6647
6648
6649#define CC_COMM_EXEC__A 0x2400000 5826#define CC_COMM_EXEC__A 0x2400000
6650#define CC_COMM_EXEC__W 3 5827#define CC_COMM_EXEC__W 3
6651#define CC_COMM_EXEC__M 0x7 5828#define CC_COMM_EXEC__M 0x7
@@ -6678,12 +5855,6 @@ extern "C" {
6678#define CC_COMM_INT_MSK__W 16 5855#define CC_COMM_INT_MSK__W 16
6679#define CC_COMM_INT_MSK__M 0xFFFF 5856#define CC_COMM_INT_MSK__M 0xFFFF
6680 5857
6681
6682
6683
6684
6685
6686
6687#define CC_REG_COMM_EXEC__A 0x2410000 5858#define CC_REG_COMM_EXEC__A 0x2410000
6688#define CC_REG_COMM_EXEC__W 3 5859#define CC_REG_COMM_EXEC__W 3
6689#define CC_REG_COMM_EXEC__M 0x7 5860#define CC_REG_COMM_EXEC__M 0x7
@@ -6723,7 +5894,6 @@ extern "C" {
6723#define CC_REG_OSC_MODE_M20 0x1 5894#define CC_REG_OSC_MODE_M20 0x1
6724#define CC_REG_OSC_MODE_M48 0x2 5895#define CC_REG_OSC_MODE_M48 0x2
6725 5896
6726
6727#define CC_REG_PLL_MODE__A 0x2410011 5897#define CC_REG_PLL_MODE__A 0x2410011
6728#define CC_REG_PLL_MODE__W 6 5898#define CC_REG_PLL_MODE__W 6
6729#define CC_REG_PLL_MODE__M 0x3F 5899#define CC_REG_PLL_MODE__M 0x3F
@@ -6749,7 +5919,6 @@ extern "C" {
6749#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 5919#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0
6750#define CC_REG_PLL_MODE_OUT_EN_ON 0x20 5920#define CC_REG_PLL_MODE_OUT_EN_ON 0x20
6751 5921
6752
6753#define CC_REG_REF_DIVIDE__A 0x2410012 5922#define CC_REG_REF_DIVIDE__A 0x2410012
6754#define CC_REG_REF_DIVIDE__W 4 5923#define CC_REG_REF_DIVIDE__W 4
6755#define CC_REG_REF_DIVIDE__M 0xF 5924#define CC_REG_REF_DIVIDE__M 0xF
@@ -6766,7 +5935,6 @@ extern "C" {
6766#define CC_REG_REF_DIVIDE_D09 0x9 5935#define CC_REG_REF_DIVIDE_D09 0x9
6767#define CC_REG_REF_DIVIDE_D10 0xA 5936#define CC_REG_REF_DIVIDE_D10 0xA
6768 5937
6769
6770#define CC_REG_REF_DELAY__A 0x2410013 5938#define CC_REG_REF_DELAY__A 0x2410013
6771#define CC_REG_REF_DELAY__W 3 5939#define CC_REG_REF_DELAY__W 3
6772#define CC_REG_REF_DELAY__M 0x7 5940#define CC_REG_REF_DELAY__M 0x7
@@ -6783,13 +5951,11 @@ extern "C" {
6783#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 5951#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4
6784#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 5952#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6
6785 5953
6786
6787#define CC_REG_CLK_DELAY__A 0x2410014 5954#define CC_REG_CLK_DELAY__A 0x2410014
6788#define CC_REG_CLK_DELAY__W 4 5955#define CC_REG_CLK_DELAY__W 4
6789#define CC_REG_CLK_DELAY__M 0xF 5956#define CC_REG_CLK_DELAY__M 0xF
6790#define CC_REG_CLK_DELAY_OFF 0x0 5957#define CC_REG_CLK_DELAY_OFF 0x0
6791 5958
6792
6793#define CC_REG_PWD_MODE__A 0x2410015 5959#define CC_REG_PWD_MODE__A 0x2410015
6794#define CC_REG_PWD_MODE__W 2 5960#define CC_REG_PWD_MODE__W 2
6795#define CC_REG_PWD_MODE__M 0x3 5961#define CC_REG_PWD_MODE__M 0x3
@@ -6798,7 +5964,6 @@ extern "C" {
6798#define CC_REG_PWD_MODE_DOWN_PLL 0x2 5964#define CC_REG_PWD_MODE_DOWN_PLL 0x2
6799#define CC_REG_PWD_MODE_DOWN_OSC 0x3 5965#define CC_REG_PWD_MODE_DOWN_OSC 0x3
6800 5966
6801
6802#define CC_REG_SOFT_RST__A 0x2410016 5967#define CC_REG_SOFT_RST__A 0x2410016
6803#define CC_REG_SOFT_RST__W 2 5968#define CC_REG_SOFT_RST__W 2
6804#define CC_REG_SOFT_RST__M 0x3 5969#define CC_REG_SOFT_RST__M 0x3
@@ -6809,40 +5974,28 @@ extern "C" {
6809#define CC_REG_SOFT_RST_OSC__W 1 5974#define CC_REG_SOFT_RST_OSC__W 1
6810#define CC_REG_SOFT_RST_OSC__M 0x2 5975#define CC_REG_SOFT_RST_OSC__M 0x2
6811 5976
6812
6813#define CC_REG_UPDATE__A 0x2410017 5977#define CC_REG_UPDATE__A 0x2410017
6814#define CC_REG_UPDATE__W 16 5978#define CC_REG_UPDATE__W 16
6815#define CC_REG_UPDATE__M 0xFFFF 5979#define CC_REG_UPDATE__M 0xFFFF
6816#define CC_REG_UPDATE_KEY 0x3973 5980#define CC_REG_UPDATE_KEY 0x3973
6817 5981
6818
6819#define CC_REG_PLL_LOCK__A 0x2410018 5982#define CC_REG_PLL_LOCK__A 0x2410018
6820#define CC_REG_PLL_LOCK__W 1 5983#define CC_REG_PLL_LOCK__W 1
6821#define CC_REG_PLL_LOCK__M 0x1 5984#define CC_REG_PLL_LOCK__M 0x1
6822#define CC_REG_PLL_LOCK_LOCK 0x1 5985#define CC_REG_PLL_LOCK_LOCK 0x1
6823 5986
6824
6825#define CC_REG_JTAGID_L__A 0x2410019 5987#define CC_REG_JTAGID_L__A 0x2410019
6826#define CC_REG_JTAGID_L__W 16 5988#define CC_REG_JTAGID_L__W 16
6827#define CC_REG_JTAGID_L__M 0xFFFF 5989#define CC_REG_JTAGID_L__M 0xFFFF
6828#define CC_REG_JTAGID_L_INIT 0x0 5990#define CC_REG_JTAGID_L_INIT 0x0
6829 5991
6830
6831#define CC_REG_JTAGID_H__A 0x241001A 5992#define CC_REG_JTAGID_H__A 0x241001A
6832#define CC_REG_JTAGID_H__W 16 5993#define CC_REG_JTAGID_H__W 16
6833#define CC_REG_JTAGID_H__M 0xFFFF 5994#define CC_REG_JTAGID_H__M 0xFFFF
6834#define CC_REG_JTAGID_H_INIT 0x0 5995#define CC_REG_JTAGID_H_INIT 0x0
6835 5996
6836
6837
6838
6839
6840#define LC_SID 0x1C 5997#define LC_SID 0x1C
6841 5998
6842
6843
6844
6845
6846#define LC_COMM_EXEC__A 0x2800000 5999#define LC_COMM_EXEC__A 0x2800000
6847#define LC_COMM_EXEC__W 3 6000#define LC_COMM_EXEC__W 3
6848#define LC_COMM_EXEC__M 0x7 6001#define LC_COMM_EXEC__M 0x7
@@ -6875,11 +6028,6 @@ extern "C" {
6875#define LC_COMM_INT_MSK__W 16 6028#define LC_COMM_INT_MSK__W 16
6876#define LC_COMM_INT_MSK__M 0xFFFF 6029#define LC_COMM_INT_MSK__M 0xFFFF
6877 6030
6878
6879
6880
6881
6882
6883#define LC_CT_REG_COMM_EXEC__A 0x2810000 6031#define LC_CT_REG_COMM_EXEC__A 0x2810000
6884#define LC_CT_REG_COMM_EXEC__W 3 6032#define LC_CT_REG_COMM_EXEC__W 3
6885#define LC_CT_REG_COMM_EXEC__M 0x7 6033#define LC_CT_REG_COMM_EXEC__M 0x7
@@ -6891,7 +6039,6 @@ extern "C" {
6891#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 6039#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
6892#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 6040#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3
6893 6041
6894
6895#define LC_CT_REG_COMM_STATE__A 0x2810001 6042#define LC_CT_REG_COMM_STATE__A 0x2810001
6896#define LC_CT_REG_COMM_STATE__W 10 6043#define LC_CT_REG_COMM_STATE__W 10
6897#define LC_CT_REG_COMM_STATE__M 0x3FF 6044#define LC_CT_REG_COMM_STATE__M 0x3FF
@@ -6905,7 +6052,6 @@ extern "C" {
6905#define LC_CT_REG_COMM_SERVICE1_LC__W 1 6052#define LC_CT_REG_COMM_SERVICE1_LC__W 1
6906#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 6053#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000
6907 6054
6908
6909#define LC_CT_REG_COMM_INT_STA__A 0x2810007 6055#define LC_CT_REG_COMM_INT_STA__A 0x2810007
6910#define LC_CT_REG_COMM_INT_STA__W 1 6056#define LC_CT_REG_COMM_INT_STA__W 1
6911#define LC_CT_REG_COMM_INT_STA__M 0x1 6057#define LC_CT_REG_COMM_INT_STA__M 0x1
@@ -6913,7 +6059,6 @@ extern "C" {
6913#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 6059#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1
6914#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 6060#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
6915 6061
6916
6917#define LC_CT_REG_COMM_INT_MSK__A 0x2810008 6062#define LC_CT_REG_COMM_INT_MSK__A 0x2810008
6918#define LC_CT_REG_COMM_INT_MSK__W 1 6063#define LC_CT_REG_COMM_INT_MSK__W 1
6919#define LC_CT_REG_COMM_INT_MSK__M 0x1 6064#define LC_CT_REG_COMM_INT_MSK__M 0x1
@@ -6921,9 +6066,6 @@ extern "C" {
6921#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 6066#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1
6922#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 6067#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
6923 6068
6924
6925
6926
6927#define LC_CT_REG_CTL_STK__AX 0x2810010 6069#define LC_CT_REG_CTL_STK__AX 0x2810010
6928#define LC_CT_REG_CTL_STK__XSZ 4 6070#define LC_CT_REG_CTL_STK__XSZ 4
6929#define LC_CT_REG_CTL_STK__W 10 6071#define LC_CT_REG_CTL_STK__W 10
@@ -6937,10 +6079,6 @@ extern "C" {
6937#define LC_CT_REG_CTL_BPT__W 10 6079#define LC_CT_REG_CTL_BPT__W 10
6938#define LC_CT_REG_CTL_BPT__M 0x3FF 6080#define LC_CT_REG_CTL_BPT__M 0x3FF
6939 6081
6940
6941
6942
6943
6944#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 6082#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006
6945#define LC_RA_RAM_PROC_DELAY_IF__W 16 6083#define LC_RA_RAM_PROC_DELAY_IF__W 16
6946#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF 6084#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF
@@ -7060,10 +6198,6 @@ extern "C" {
7060#define LC_RA_RAM_ADJUST_DELAY__W 16 6198#define LC_RA_RAM_ADJUST_DELAY__W 16
7061#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF 6199#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF
7062 6200
7063
7064
7065
7066
7067#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 6201#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028
7068#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 6202#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16
7069#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF 6203#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF
@@ -7083,8 +6217,6 @@ extern "C" {
7083#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 6217#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16
7084#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF 6218#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF
7085 6219
7086
7087
7088#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 6220#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030
7089#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 6221#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16
7090#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF 6222#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF
@@ -7104,8 +6236,6 @@ extern "C" {
7104#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 6236#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16
7105#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF 6237#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF
7106 6238
7107
7108
7109#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 6239#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038
7110#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 6240#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16
7111#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF 6241#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF
@@ -7125,10 +6255,6 @@ extern "C" {
7125#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 6255#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16
7126#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF 6256#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF
7127 6257
7128
7129
7130
7131
7132#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 6258#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
7133#define LC_RA_RAM_FILTER_CRMM_A__W 16 6259#define LC_RA_RAM_FILTER_CRMM_A__W 16
7134#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF 6260#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF
@@ -7150,8 +6276,6 @@ extern "C" {
7150#define LC_RA_RAM_FILTER_CRMM_TMP__W 16 6276#define LC_RA_RAM_FILTER_CRMM_TMP__W 16
7151#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF 6277#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF
7152 6278
7153
7154
7155#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 6279#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
7156#define LC_RA_RAM_FILTER_SRMM_A__W 16 6280#define LC_RA_RAM_FILTER_SRMM_A__W 16
7157#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF 6281#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF
@@ -7173,8 +6297,6 @@ extern "C" {
7173#define LC_RA_RAM_FILTER_SRMM_TMP__W 16 6297#define LC_RA_RAM_FILTER_SRMM_TMP__W 16
7174#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF 6298#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF
7175 6299
7176
7177
7178#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 6300#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070
7179#define LC_RA_RAM_FILTER_PHASE_A__W 16 6301#define LC_RA_RAM_FILTER_PHASE_A__W 16
7180#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF 6302#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF
@@ -7196,8 +6318,6 @@ extern "C" {
7196#define LC_RA_RAM_FILTER_PHASE_TMP__W 16 6318#define LC_RA_RAM_FILTER_PHASE_TMP__W 16
7197#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF 6319#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF
7198 6320
7199
7200
7201#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 6321#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078
7202#define LC_RA_RAM_FILTER_DELAY_A__W 16 6322#define LC_RA_RAM_FILTER_DELAY_A__W 16
7203#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF 6323#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF
@@ -7219,11 +6339,6 @@ extern "C" {
7219#define LC_RA_RAM_FILTER_DELAY_TMP__W 16 6339#define LC_RA_RAM_FILTER_DELAY_TMP__W 16
7220#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF 6340#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF
7221 6341
7222
7223
7224
7225
7226
7227#define LC_IF_RAM_TRP_BPT0__AX 0x2830000 6342#define LC_IF_RAM_TRP_BPT0__AX 0x2830000
7228#define LC_IF_RAM_TRP_BPT0__XSZ 2 6343#define LC_IF_RAM_TRP_BPT0__XSZ 2
7229#define LC_IF_RAM_TRP_BPT0__W 12 6344#define LC_IF_RAM_TRP_BPT0__W 12
@@ -7239,18 +6354,8 @@ extern "C" {
7239#define LC_IF_RAM_TRP_WARM__W 12 6354#define LC_IF_RAM_TRP_WARM__W 12
7240#define LC_IF_RAM_TRP_WARM__M 0xFFF 6355#define LC_IF_RAM_TRP_WARM__M 0xFFF
7241 6356
7242
7243
7244
7245
7246
7247
7248#define B_HI_SID 0x10 6357#define B_HI_SID 0x10
7249 6358
7250
7251
7252
7253
7254#define B_HI_COMM_EXEC__A 0x400000 6359#define B_HI_COMM_EXEC__A 0x400000
7255#define B_HI_COMM_EXEC__W 3 6360#define B_HI_COMM_EXEC__W 3
7256#define B_HI_COMM_EXEC__M 0x7 6361#define B_HI_COMM_EXEC__M 0x7
@@ -7283,11 +6388,6 @@ extern "C" {
7283#define B_HI_COMM_INT_MSK__W 16 6388#define B_HI_COMM_INT_MSK__W 16
7284#define B_HI_COMM_INT_MSK__M 0xFFFF 6389#define B_HI_COMM_INT_MSK__M 0xFFFF
7285 6390
7286
7287
7288
7289
7290
7291#define B_HI_CT_REG_COMM_EXEC__A 0x410000 6391#define B_HI_CT_REG_COMM_EXEC__A 0x410000
7292#define B_HI_CT_REG_COMM_EXEC__W 3 6392#define B_HI_CT_REG_COMM_EXEC__W 3
7293#define B_HI_CT_REG_COMM_EXEC__M 0x7 6393#define B_HI_CT_REG_COMM_EXEC__M 0x7
@@ -7299,7 +6399,6 @@ extern "C" {
7299#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 6399#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2
7300#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 6400#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3
7301 6401
7302
7303#define B_HI_CT_REG_COMM_STATE__A 0x410001 6402#define B_HI_CT_REG_COMM_STATE__A 0x410001
7304#define B_HI_CT_REG_COMM_STATE__W 10 6403#define B_HI_CT_REG_COMM_STATE__W 10
7305#define B_HI_CT_REG_COMM_STATE__M 0x3FF 6404#define B_HI_CT_REG_COMM_STATE__M 0x3FF
@@ -7313,7 +6412,6 @@ extern "C" {
7313#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 6412#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1
7314#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 6413#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1
7315 6414
7316
7317#define B_HI_CT_REG_COMM_INT_STA__A 0x410007 6415#define B_HI_CT_REG_COMM_INT_STA__A 0x410007
7318#define B_HI_CT_REG_COMM_INT_STA__W 1 6416#define B_HI_CT_REG_COMM_INT_STA__W 1
7319#define B_HI_CT_REG_COMM_INT_STA__M 0x1 6417#define B_HI_CT_REG_COMM_INT_STA__M 0x1
@@ -7321,7 +6419,6 @@ extern "C" {
7321#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 6419#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1
7322#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 6420#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1
7323 6421
7324
7325#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 6422#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008
7326#define B_HI_CT_REG_COMM_INT_MSK__W 1 6423#define B_HI_CT_REG_COMM_INT_MSK__W 1
7327#define B_HI_CT_REG_COMM_INT_MSK__M 0x1 6424#define B_HI_CT_REG_COMM_INT_MSK__M 0x1
@@ -7329,9 +6426,6 @@ extern "C" {
7329#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 6426#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1
7330#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 6427#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
7331 6428
7332
7333
7334
7335#define B_HI_CT_REG_CTL_STK__AX 0x410010 6429#define B_HI_CT_REG_CTL_STK__AX 0x410010
7336#define B_HI_CT_REG_CTL_STK__XSZ 4 6430#define B_HI_CT_REG_CTL_STK__XSZ 4
7337#define B_HI_CT_REG_CTL_STK__W 10 6431#define B_HI_CT_REG_CTL_STK__W 10
@@ -7345,18 +6439,12 @@ extern "C" {
7345#define B_HI_CT_REG_CTL_BPT__W 10 6439#define B_HI_CT_REG_CTL_BPT__W 10
7346#define B_HI_CT_REG_CTL_BPT__M 0x3FF 6440#define B_HI_CT_REG_CTL_BPT__M 0x3FF
7347 6441
7348
7349
7350
7351
7352
7353#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 6442#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010
7354#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 6443#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1
7355#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 6444#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1
7356#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 6445#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0
7357#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 6446#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1
7358 6447
7359
7360#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 6448#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011
7361#define B_HI_RA_RAM_SLV0_DEV_ID__W 7 6449#define B_HI_RA_RAM_SLV0_DEV_ID__W 7
7362#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F 6450#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F
@@ -7367,7 +6455,6 @@ extern "C" {
7367#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 6455#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0
7368#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 6456#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1
7369 6457
7370
7371#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 6458#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013
7372#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 6459#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3
7373#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 6460#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7
@@ -7382,14 +6469,12 @@ extern "C" {
7382#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 6469#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0
7383#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 6470#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4
7384 6471
7385
7386#define B_HI_RA_RAM_SLV0_STATE__A 0x420014 6472#define B_HI_RA_RAM_SLV0_STATE__A 0x420014
7387#define B_HI_RA_RAM_SLV0_STATE__W 1 6473#define B_HI_RA_RAM_SLV0_STATE__W 1
7388#define B_HI_RA_RAM_SLV0_STATE__M 0x1 6474#define B_HI_RA_RAM_SLV0_STATE__M 0x1
7389#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 6475#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0
7390#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 6476#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1
7391 6477
7392
7393#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 6478#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015
7394#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 6479#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12
7395#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF 6480#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF
@@ -7400,7 +6485,6 @@ extern "C" {
7400#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 6485#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6
7401#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 6486#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0
7402 6487
7403
7404#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 6488#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016
7405#define B_HI_RA_RAM_SLV0_ADDR__W 16 6489#define B_HI_RA_RAM_SLV0_ADDR__W 16
7406#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF 6490#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF
@@ -7413,16 +6497,12 @@ extern "C" {
7413#define B_HI_RA_RAM_SLV0_READBACK__W 16 6497#define B_HI_RA_RAM_SLV0_READBACK__W 16
7414#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF 6498#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF
7415 6499
7416
7417
7418
7419#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 6500#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020
7420#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 6501#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1
7421#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 6502#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1
7422#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 6503#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0
7423#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 6504#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1
7424 6505
7425
7426#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 6506#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021
7427#define B_HI_RA_RAM_SLV1_DEV_ID__W 7 6507#define B_HI_RA_RAM_SLV1_DEV_ID__W 7
7428#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F 6508#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F
@@ -7433,7 +6513,6 @@ extern "C" {
7433#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 6513#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0
7434#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 6514#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1
7435 6515
7436
7437#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 6516#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023
7438#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 6517#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3
7439#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 6518#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7
@@ -7448,14 +6527,12 @@ extern "C" {
7448#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 6527#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0
7449#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 6528#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4
7450 6529
7451
7452#define B_HI_RA_RAM_SLV1_STATE__A 0x420024 6530#define B_HI_RA_RAM_SLV1_STATE__A 0x420024
7453#define B_HI_RA_RAM_SLV1_STATE__W 1 6531#define B_HI_RA_RAM_SLV1_STATE__W 1
7454#define B_HI_RA_RAM_SLV1_STATE__M 0x1 6532#define B_HI_RA_RAM_SLV1_STATE__M 0x1
7455#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 6533#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0
7456#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 6534#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1
7457 6535
7458
7459#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 6536#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025
7460#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 6537#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12
7461#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF 6538#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF
@@ -7466,7 +6543,6 @@ extern "C" {
7466#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 6543#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6
7467#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 6544#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0
7468 6545
7469
7470#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 6546#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026
7471#define B_HI_RA_RAM_SLV1_ADDR__W 16 6547#define B_HI_RA_RAM_SLV1_ADDR__W 16
7472#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF 6548#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF
@@ -7479,16 +6555,12 @@ extern "C" {
7479#define B_HI_RA_RAM_SLV1_READBACK__W 16 6555#define B_HI_RA_RAM_SLV1_READBACK__W 16
7480#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF 6556#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF
7481 6557
7482
7483
7484
7485#define B_HI_RA_RAM_SRV_SEM__A 0x420030 6558#define B_HI_RA_RAM_SRV_SEM__A 0x420030
7486#define B_HI_RA_RAM_SRV_SEM__W 1 6559#define B_HI_RA_RAM_SRV_SEM__W 1
7487#define B_HI_RA_RAM_SRV_SEM__M 0x1 6560#define B_HI_RA_RAM_SRV_SEM__M 0x1
7488#define B_HI_RA_RAM_SRV_SEM_FREE 0x0 6561#define B_HI_RA_RAM_SRV_SEM_FREE 0x0
7489#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 6562#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1
7490 6563
7491
7492#define B_HI_RA_RAM_SRV_RES__A 0x420031 6564#define B_HI_RA_RAM_SRV_RES__A 0x420031
7493#define B_HI_RA_RAM_SRV_RES__W 3 6565#define B_HI_RA_RAM_SRV_RES__W 3
7494#define B_HI_RA_RAM_SRV_RES__M 0x7 6566#define B_HI_RA_RAM_SRV_RES__M 0x7
@@ -7498,7 +6570,6 @@ extern "C" {
7498#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 6570#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3
7499#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 6571#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4
7500 6572
7501
7502#define B_HI_RA_RAM_SRV_CMD__A 0x420032 6573#define B_HI_RA_RAM_SRV_CMD__A 0x420032
7503#define B_HI_RA_RAM_SRV_CMD__W 3 6574#define B_HI_RA_RAM_SRV_CMD__W 3
7504#define B_HI_RA_RAM_SRV_CMD__M 0x7 6575#define B_HI_RA_RAM_SRV_CMD__M 0x7
@@ -7510,22 +6581,17 @@ extern "C" {
7510#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 6581#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5
7511#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 6582#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6
7512 6583
7513
7514#define B_HI_RA_RAM_SRV_PAR__AX 0x420033 6584#define B_HI_RA_RAM_SRV_PAR__AX 0x420033
7515#define B_HI_RA_RAM_SRV_PAR__XSZ 5 6585#define B_HI_RA_RAM_SRV_PAR__XSZ 5
7516#define B_HI_RA_RAM_SRV_PAR__W 16 6586#define B_HI_RA_RAM_SRV_PAR__W 16
7517#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF 6587#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF
7518 6588
7519
7520
7521#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 6589#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031
7522#define B_HI_RA_RAM_SRV_NOP_RES__W 3 6590#define B_HI_RA_RAM_SRV_NOP_RES__W 3
7523#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 6591#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7
7524#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 6592#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0
7525#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 6593#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4
7526 6594
7527
7528
7529#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 6595#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031
7530#define B_HI_RA_RAM_SRV_UIO_RES__W 3 6596#define B_HI_RA_RAM_SRV_UIO_RES__W 3
7531#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 6597#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7
@@ -7557,8 +6623,6 @@ extern "C" {
7557#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 6623#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0
7558#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 6624#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2
7559 6625
7560
7561
7562#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 6626#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031
7563#define B_HI_RA_RAM_SRV_RST_RES__W 1 6627#define B_HI_RA_RAM_SRV_RST_RES__W 1
7564#define B_HI_RA_RAM_SRV_RST_RES__M 0x1 6628#define B_HI_RA_RAM_SRV_RST_RES__M 0x1
@@ -7570,8 +6634,6 @@ extern "C" {
7570#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF 6634#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF
7571#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 6635#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
7572 6636
7573
7574
7575#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 6637#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031
7576#define B_HI_RA_RAM_SRV_CFG_RES__W 1 6638#define B_HI_RA_RAM_SRV_CFG_RES__W 1
7577#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 6639#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1
@@ -7583,7 +6645,6 @@ extern "C" {
7583#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF 6645#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF
7584#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 6646#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973
7585 6647
7586
7587#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 6648#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034
7588#define B_HI_RA_RAM_SRV_CFG_DIV__W 5 6649#define B_HI_RA_RAM_SRV_CFG_DIV__W 5
7589#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F 6650#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F
@@ -7620,15 +6681,12 @@ extern "C" {
7620#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 6681#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0
7621#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 6682#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
7622 6683
7623
7624
7625#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 6684#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031
7626#define B_HI_RA_RAM_SRV_CPY_RES__W 1 6685#define B_HI_RA_RAM_SRV_CPY_RES__W 1
7627#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 6686#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1
7628#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 6687#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0
7629#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 6688#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1
7630 6689
7631
7632#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 6690#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033
7633#define B_HI_RA_RAM_SRV_CPY_SBB__W 12 6691#define B_HI_RA_RAM_SRV_CPY_SBB__W 12
7634#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF 6692#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF
@@ -7639,7 +6697,6 @@ extern "C" {
7639#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 6697#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6
7640#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 6698#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0
7641 6699
7642
7643#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 6700#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034
7644#define B_HI_RA_RAM_SRV_CPY_SAD__W 16 6701#define B_HI_RA_RAM_SRV_CPY_SAD__W 16
7645#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF 6702#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF
@@ -7658,13 +6715,10 @@ extern "C" {
7658#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 6715#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6
7659#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 6716#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0
7660 6717
7661
7662#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 6718#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034
7663#define B_HI_RA_RAM_SRV_CPY_DAD__W 16 6719#define B_HI_RA_RAM_SRV_CPY_DAD__W 16
7664#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF 6720#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF
7665 6721
7666
7667
7668#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 6722#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031
7669#define B_HI_RA_RAM_SRV_TRM_RES__W 2 6723#define B_HI_RA_RAM_SRV_TRM_RES__W 2
7670#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 6724#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3
@@ -7672,7 +6726,6 @@ extern "C" {
7672#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 6726#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1
7673#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 6727#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3
7674 6728
7675
7676#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 6729#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033
7677#define B_HI_RA_RAM_SRV_TRM_MST__W 12 6730#define B_HI_RA_RAM_SRV_TRM_MST__W 12
7678#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF 6731#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF
@@ -7688,7 +6741,6 @@ extern "C" {
7688#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 6741#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8
7689#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF 6742#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF
7690 6743
7691
7692#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 6744#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033
7693#define B_HI_RA_RAM_SRV_TRM_DBB__W 12 6745#define B_HI_RA_RAM_SRV_TRM_DBB__W 12
7694#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF 6746#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF
@@ -7699,14 +6751,10 @@ extern "C" {
7699#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 6751#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6
7700#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 6752#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0
7701 6753
7702
7703#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 6754#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034
7704#define B_HI_RA_RAM_SRV_TRM_DAD__W 16 6755#define B_HI_RA_RAM_SRV_TRM_DAD__W 16
7705#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF 6756#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF
7706 6757
7707
7708
7709
7710#define B_HI_RA_RAM_USR_BEGIN__A 0x420040 6758#define B_HI_RA_RAM_USR_BEGIN__A 0x420040
7711#define B_HI_RA_RAM_USR_BEGIN__W 16 6759#define B_HI_RA_RAM_USR_BEGIN__W 16
7712#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF 6760#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF
@@ -7715,11 +6763,6 @@ extern "C" {
7715#define B_HI_RA_RAM_USR_END__W 16 6763#define B_HI_RA_RAM_USR_END__W 16
7716#define B_HI_RA_RAM_USR_END__M 0xFFFF 6764#define B_HI_RA_RAM_USR_END__M 0xFFFF
7717 6765
7718
7719
7720
7721
7722
7723#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 6766#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000
7724#define B_HI_IF_RAM_TRP_BPT0__XSZ 2 6767#define B_HI_IF_RAM_TRP_BPT0__XSZ 2
7725#define B_HI_IF_RAM_TRP_BPT0__W 12 6768#define B_HI_IF_RAM_TRP_BPT0__W 12
@@ -7730,9 +6773,6 @@ extern "C" {
7730#define B_HI_IF_RAM_TRP_STKU__W 12 6773#define B_HI_IF_RAM_TRP_STKU__W 12
7731#define B_HI_IF_RAM_TRP_STKU__M 0xFFF 6774#define B_HI_IF_RAM_TRP_STKU__M 0xFFF
7732 6775
7733
7734
7735
7736#define B_HI_IF_RAM_USR_BEGIN__A 0x430200 6776#define B_HI_IF_RAM_USR_BEGIN__A 0x430200
7737#define B_HI_IF_RAM_USR_BEGIN__W 12 6777#define B_HI_IF_RAM_USR_BEGIN__W 12
7738#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF 6778#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF
@@ -7741,16 +6781,8 @@ extern "C" {
7741#define B_HI_IF_RAM_USR_END__W 12 6781#define B_HI_IF_RAM_USR_END__W 12
7742#define B_HI_IF_RAM_USR_END__M 0xFFF 6782#define B_HI_IF_RAM_USR_END__M 0xFFF
7743 6783
7744
7745
7746
7747
7748#define B_SC_SID 0x11 6784#define B_SC_SID 0x11
7749 6785
7750
7751
7752
7753
7754#define B_SC_COMM_EXEC__A 0x800000 6786#define B_SC_COMM_EXEC__A 0x800000
7755#define B_SC_COMM_EXEC__W 3 6787#define B_SC_COMM_EXEC__W 3
7756#define B_SC_COMM_EXEC__M 0x7 6788#define B_SC_COMM_EXEC__M 0x7
@@ -7783,11 +6815,6 @@ extern "C" {
7783#define B_SC_COMM_INT_MSK__W 16 6815#define B_SC_COMM_INT_MSK__W 16
7784#define B_SC_COMM_INT_MSK__M 0xFFFF 6816#define B_SC_COMM_INT_MSK__M 0xFFFF
7785 6817
7786
7787
7788
7789
7790
7791#define B_SC_CT_REG_COMM_EXEC__A 0x810000 6818#define B_SC_CT_REG_COMM_EXEC__A 0x810000
7792#define B_SC_CT_REG_COMM_EXEC__W 3 6819#define B_SC_CT_REG_COMM_EXEC__W 3
7793#define B_SC_CT_REG_COMM_EXEC__M 0x7 6820#define B_SC_CT_REG_COMM_EXEC__M 0x7
@@ -7799,7 +6826,6 @@ extern "C" {
7799#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 6826#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
7800#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 6827#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3
7801 6828
7802
7803#define B_SC_CT_REG_COMM_STATE__A 0x810001 6829#define B_SC_CT_REG_COMM_STATE__A 0x810001
7804#define B_SC_CT_REG_COMM_STATE__W 10 6830#define B_SC_CT_REG_COMM_STATE__W 10
7805#define B_SC_CT_REG_COMM_STATE__M 0x3FF 6831#define B_SC_CT_REG_COMM_STATE__M 0x3FF
@@ -7813,7 +6839,6 @@ extern "C" {
7813#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 6839#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1
7814#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 6840#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2
7815 6841
7816
7817#define B_SC_CT_REG_COMM_INT_STA__A 0x810007 6842#define B_SC_CT_REG_COMM_INT_STA__A 0x810007
7818#define B_SC_CT_REG_COMM_INT_STA__W 1 6843#define B_SC_CT_REG_COMM_INT_STA__W 1
7819#define B_SC_CT_REG_COMM_INT_STA__M 0x1 6844#define B_SC_CT_REG_COMM_INT_STA__M 0x1
@@ -7821,7 +6846,6 @@ extern "C" {
7821#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 6846#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1
7822#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 6847#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
7823 6848
7824
7825#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 6849#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008
7826#define B_SC_CT_REG_COMM_INT_MSK__W 1 6850#define B_SC_CT_REG_COMM_INT_MSK__W 1
7827#define B_SC_CT_REG_COMM_INT_MSK__M 0x1 6851#define B_SC_CT_REG_COMM_INT_MSK__M 0x1
@@ -7829,9 +6853,6 @@ extern "C" {
7829#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 6853#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1
7830#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 6854#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
7831 6855
7832
7833
7834
7835#define B_SC_CT_REG_CTL_STK__AX 0x810010 6856#define B_SC_CT_REG_CTL_STK__AX 0x810010
7836#define B_SC_CT_REG_CTL_STK__XSZ 4 6857#define B_SC_CT_REG_CTL_STK__XSZ 4
7837#define B_SC_CT_REG_CTL_STK__W 10 6858#define B_SC_CT_REG_CTL_STK__W 10
@@ -7845,10 +6866,6 @@ extern "C" {
7845#define B_SC_CT_REG_CTL_BPT__W 10 6866#define B_SC_CT_REG_CTL_BPT__W 10
7846#define B_SC_CT_REG_CTL_BPT__M 0x3FF 6867#define B_SC_CT_REG_CTL_BPT__M 0x3FF
7847 6868
7848
7849
7850
7851
7852#define B_SC_RA_RAM_PARAM0__A 0x820040 6869#define B_SC_RA_RAM_PARAM0__A 0x820040
7853#define B_SC_RA_RAM_PARAM0__W 16 6870#define B_SC_RA_RAM_PARAM0__W 16
7854#define B_SC_RA_RAM_PARAM0__M 0xFFFF 6871#define B_SC_RA_RAM_PARAM0__M 0xFFFF
@@ -7934,8 +6951,6 @@ extern "C" {
7934#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA 6951#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA
7935#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB 6952#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB
7936 6953
7937
7938
7939#define B_SC_RA_RAM_OP_PARAM__A 0x820048 6954#define B_SC_RA_RAM_OP_PARAM__A 0x820048
7940#define B_SC_RA_RAM_OP_PARAM__W 13 6955#define B_SC_RA_RAM_OP_PARAM__W 13
7941#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF 6956#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF
@@ -8025,8 +7040,6 @@ extern "C" {
8025#define B_SC_RA_RAM_LOCK_NODVBT__W 1 7040#define B_SC_RA_RAM_LOCK_NODVBT__W 1
8026#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 7041#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8
8027 7042
8028
8029
8030#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C 7043#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C
8031#define B_SC_RA_RAM_BE_OPT_ENA__W 5 7044#define B_SC_RA_RAM_BE_OPT_ENA__W 5
8032#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F 7045#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F
@@ -8098,10 +7111,6 @@ extern "C" {
8098#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF 7111#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF
8099#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 7112#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0
8100 7113
8101
8102
8103
8104
8105#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 7114#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055
8106#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 7115#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16
8107#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF 7116#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF
@@ -8119,8 +7128,6 @@ extern "C" {
8119#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF 7128#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF
8120#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 7129#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2
8121 7130
8122
8123
8124#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 7131#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059
8125#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 7132#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16
8126#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF 7133#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF
@@ -8138,8 +7145,6 @@ extern "C" {
8138#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF 7145#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF
8139#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 7146#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2
8140 7147
8141
8142
8143#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D 7148#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D
8144#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 7149#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16
8145#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF 7150#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF
@@ -8215,10 +7220,6 @@ extern "C" {
8215#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF 7220#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF
8216#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 7221#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0
8217 7222
8218
8219
8220
8221
8222#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 7223#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098
8223#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 7224#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16
8224#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF 7225#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF
@@ -8236,8 +7237,6 @@ extern "C" {
8236#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF 7237#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF
8237#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 7238#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258
8238 7239
8239
8240
8241#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C 7240#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C
8242#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 7241#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16
8243#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF 7242#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF
@@ -8255,17 +7254,11 @@ extern "C" {
8255#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF 7254#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF
8256#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC 7255#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC
8257 7256
8258
8259
8260#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 7257#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0
8261#define B_SC_RA_RAM_IR_FREQ__W 16 7258#define B_SC_RA_RAM_IR_FREQ__W 16
8262#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF 7259#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF
8263#define B_SC_RA_RAM_IR_FREQ__PRE 0x0 7260#define B_SC_RA_RAM_IR_FREQ__PRE 0x0
8264 7261
8265
8266
8267
8268
8269#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 7262#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
8270#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 7263#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16
8271#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF 7264#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF
@@ -8279,8 +7272,6 @@ extern "C" {
8279#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF 7272#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF
8280#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 7273#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
8281 7274
8282
8283
8284#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 7275#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
8285#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 7276#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16
8286#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF 7277#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF
@@ -8294,10 +7285,6 @@ extern "C" {
8294#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF 7285#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF
8295#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 7286#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
8296 7287
8297
8298
8299
8300
8301#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 7288#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
8302#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 7289#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16
8303#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF 7290#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF
@@ -8311,8 +7298,6 @@ extern "C" {
8311#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF 7298#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF
8312#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 7299#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
8313 7300
8314
8315
8316#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 7301#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
8317#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 7302#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16
8318#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF 7303#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF
@@ -8326,8 +7311,6 @@ extern "C" {
8326#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF 7311#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF
8327#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 7312#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
8328 7313
8329
8330
8331#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 7314#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
8332#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 7315#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16
8333#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF 7316#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF
@@ -8347,10 +7330,6 @@ extern "C" {
8347#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 7330#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6
8348#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 7331#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00
8349 7332
8350
8351
8352
8353
8354#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 7333#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0
8355#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 7334#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16
8356#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF 7335#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF
@@ -8364,8 +7343,6 @@ extern "C" {
8364#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF 7343#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF
8365#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 7344#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8
8366 7345
8367
8368
8369#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 7346#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3
8370#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 7347#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16
8371#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF 7348#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF
@@ -8379,8 +7356,6 @@ extern "C" {
8379#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF 7356#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF
8380#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 7357#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0
8381 7358
8382
8383
8384#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 7359#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
8385#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 7360#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16
8386#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF 7361#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF
@@ -8390,8 +7365,6 @@ extern "C" {
8390#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF 7365#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF
8391#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C 7366#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C
8392 7367
8393
8394
8395#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA 7368#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA
8396#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 7369#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16
8397#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF 7370#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF
@@ -8446,8 +7419,6 @@ extern "C" {
8446#define B_SC_RA_RAM_BOOTCOUNT__W 16 7419#define B_SC_RA_RAM_BOOTCOUNT__W 16
8447#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF 7420#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF
8448 7421
8449
8450
8451#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 7422#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4
8452#define B_SC_RA_RAM_LC_ABS_2K__W 16 7423#define B_SC_RA_RAM_LC_ABS_2K__W 16
8453#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF 7424#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF
@@ -8471,8 +7442,6 @@ extern "C" {
8471#define B_SC_RA_RAM_STACKUNDERFLOW__W 16 7442#define B_SC_RA_RAM_STACKUNDERFLOW__W 16
8472#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF 7443#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF
8473 7444
8474
8475
8476#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 7445#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148
8477#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 7446#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16
8478#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF 7447#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF
@@ -8500,10 +7469,6 @@ extern "C" {
8500#define B_SC_RA_RAM_NF_ECHOTABLE__W 16 7469#define B_SC_RA_RAM_NF_ECHOTABLE__W 16
8501#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF 7470#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF
8502 7471
8503
8504
8505
8506
8507#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 7472#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0
8508#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 7473#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16
8509#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF 7474#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF
@@ -8513,8 +7478,6 @@ extern "C" {
8513#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF 7478#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF
8514#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 7479#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
8515 7480
8516
8517
8518#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 7481#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2
8519#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 7482#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16
8520#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF 7483#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF
@@ -8524,8 +7487,6 @@ extern "C" {
8524#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF 7487#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF
8525#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 7488#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4
8526 7489
8527
8528
8529#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 7490#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4
8530#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 7491#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16
8531#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF 7492#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF
@@ -8535,8 +7496,6 @@ extern "C" {
8535#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF 7496#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF
8536#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 7497#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
8537 7498
8538
8539
8540#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 7499#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6
8541#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 7500#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16
8542#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF 7501#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF
@@ -8546,8 +7505,6 @@ extern "C" {
8546#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF 7505#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF
8547#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 7506#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4
8548 7507
8549
8550
8551#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 7508#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8
8552#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 7509#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16
8553#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF 7510#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF
@@ -8557,8 +7514,6 @@ extern "C" {
8557#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF 7514#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF
8558#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 7515#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5
8559 7516
8560
8561
8562#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA 7517#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA
8563#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 7518#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16
8564#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF 7519#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF
@@ -8568,8 +7523,6 @@ extern "C" {
8568#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF 7523#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF
8569#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 7524#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
8570 7525
8571
8572
8573#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC 7526#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC
8574#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 7527#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16
8575#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF 7528#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF
@@ -8579,8 +7532,6 @@ extern "C" {
8579#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF 7532#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF
8580#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 7533#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4
8581 7534
8582
8583
8584#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE 7535#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE
8585#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 7536#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16
8586#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF 7537#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF
@@ -8609,11 +7560,6 @@ extern "C" {
8609#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 7560#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8
8610#define B_SC_RA_RAM_PROC_MAX 0x9 7561#define B_SC_RA_RAM_PROC_MAX 0x9
8611 7562
8612
8613
8614
8615
8616
8617#define B_SC_IF_RAM_TRP_RST__AX 0x830000 7563#define B_SC_IF_RAM_TRP_RST__AX 0x830000
8618#define B_SC_IF_RAM_TRP_RST__XSZ 2 7564#define B_SC_IF_RAM_TRP_RST__XSZ 2
8619#define B_SC_IF_RAM_TRP_RST__W 12 7565#define B_SC_IF_RAM_TRP_RST__W 12
@@ -8629,9 +7575,6 @@ extern "C" {
8629#define B_SC_IF_RAM_TRP_STKU__W 12 7575#define B_SC_IF_RAM_TRP_STKU__W 12
8630#define B_SC_IF_RAM_TRP_STKU__M 0xFFF 7576#define B_SC_IF_RAM_TRP_STKU__M 0xFFF
8631 7577
8632
8633
8634
8635#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE 7578#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE
8636#define B_SC_IF_RAM_VERSION_MA_MI__W 12 7579#define B_SC_IF_RAM_VERSION_MA_MI__W 12
8637#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF 7580#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF
@@ -8640,14 +7583,6 @@ extern "C" {
8640#define B_SC_IF_RAM_VERSION_PATCH__W 12 7583#define B_SC_IF_RAM_VERSION_PATCH__W 12
8641#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF 7584#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF
8642 7585
8643
8644
8645
8646
8647
8648
8649
8650
8651#define B_FE_COMM_EXEC__A 0xC00000 7586#define B_FE_COMM_EXEC__A 0xC00000
8652#define B_FE_COMM_EXEC__W 3 7587#define B_FE_COMM_EXEC__W 3
8653#define B_FE_COMM_EXEC__M 0x7 7588#define B_FE_COMM_EXEC__M 0x7
@@ -8680,17 +7615,8 @@ extern "C" {
8680#define B_FE_COMM_INT_MSK__W 16 7615#define B_FE_COMM_INT_MSK__W 16
8681#define B_FE_COMM_INT_MSK__M 0xFFFF 7616#define B_FE_COMM_INT_MSK__M 0xFFFF
8682 7617
8683
8684
8685
8686
8687#define B_FE_AD_SID 0x1 7618#define B_FE_AD_SID 0x1
8688 7619
8689
8690
8691
8692
8693
8694#define B_FE_AD_REG_COMM_EXEC__A 0xC10000 7620#define B_FE_AD_REG_COMM_EXEC__A 0xC10000
8695#define B_FE_AD_REG_COMM_EXEC__W 3 7621#define B_FE_AD_REG_COMM_EXEC__W 3
8696#define B_FE_AD_REG_COMM_EXEC__M 0x7 7622#define B_FE_AD_REG_COMM_EXEC__M 0x7
@@ -8702,7 +7628,6 @@ extern "C" {
8702#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 7628#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2
8703#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 7629#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3
8704 7630
8705
8706#define B_FE_AD_REG_COMM_MB__A 0xC10002 7631#define B_FE_AD_REG_COMM_MB__A 0xC10002
8707#define B_FE_AD_REG_COMM_MB__W 2 7632#define B_FE_AD_REG_COMM_MB__W 2
8708#define B_FE_AD_REG_COMM_MB__M 0x3 7633#define B_FE_AD_REG_COMM_MB__M 0x3
@@ -8735,7 +7660,6 @@ extern "C" {
8735#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 7660#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1
8736#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 7661#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1
8737 7662
8738
8739#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 7663#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008
8740#define B_FE_AD_REG_COMM_INT_MSK__W 2 7664#define B_FE_AD_REG_COMM_INT_MSK__W 2
8741#define B_FE_AD_REG_COMM_INT_MSK__M 0x3 7665#define B_FE_AD_REG_COMM_INT_MSK__M 0x3
@@ -8743,137 +7667,108 @@ extern "C" {
8743#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 7667#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1
8744#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 7668#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1
8745 7669
8746
8747#define B_FE_AD_REG_CUR_SEL__A 0xC10010 7670#define B_FE_AD_REG_CUR_SEL__A 0xC10010
8748#define B_FE_AD_REG_CUR_SEL__W 2 7671#define B_FE_AD_REG_CUR_SEL__W 2
8749#define B_FE_AD_REG_CUR_SEL__M 0x3 7672#define B_FE_AD_REG_CUR_SEL__M 0x3
8750#define B_FE_AD_REG_CUR_SEL_INIT 0x2 7673#define B_FE_AD_REG_CUR_SEL_INIT 0x2
8751 7674
8752
8753#define B_FE_AD_REG_OVERFLOW__A 0xC10011 7675#define B_FE_AD_REG_OVERFLOW__A 0xC10011
8754#define B_FE_AD_REG_OVERFLOW__W 1 7676#define B_FE_AD_REG_OVERFLOW__W 1
8755#define B_FE_AD_REG_OVERFLOW__M 0x1 7677#define B_FE_AD_REG_OVERFLOW__M 0x1
8756#define B_FE_AD_REG_OVERFLOW_INIT 0x0 7678#define B_FE_AD_REG_OVERFLOW_INIT 0x0
8757 7679
8758
8759#define B_FE_AD_REG_FDB_IN__A 0xC10012 7680#define B_FE_AD_REG_FDB_IN__A 0xC10012
8760#define B_FE_AD_REG_FDB_IN__W 1 7681#define B_FE_AD_REG_FDB_IN__W 1
8761#define B_FE_AD_REG_FDB_IN__M 0x1 7682#define B_FE_AD_REG_FDB_IN__M 0x1
8762#define B_FE_AD_REG_FDB_IN_INIT 0x0 7683#define B_FE_AD_REG_FDB_IN_INIT 0x0
8763 7684
8764
8765#define B_FE_AD_REG_PD__A 0xC10013 7685#define B_FE_AD_REG_PD__A 0xC10013
8766#define B_FE_AD_REG_PD__W 1 7686#define B_FE_AD_REG_PD__W 1
8767#define B_FE_AD_REG_PD__M 0x1 7687#define B_FE_AD_REG_PD__M 0x1
8768#define B_FE_AD_REG_PD_INIT 0x1 7688#define B_FE_AD_REG_PD_INIT 0x1
8769 7689
8770
8771#define B_FE_AD_REG_INVEXT__A 0xC10014 7690#define B_FE_AD_REG_INVEXT__A 0xC10014
8772#define B_FE_AD_REG_INVEXT__W 1 7691#define B_FE_AD_REG_INVEXT__W 1
8773#define B_FE_AD_REG_INVEXT__M 0x1 7692#define B_FE_AD_REG_INVEXT__M 0x1
8774#define B_FE_AD_REG_INVEXT_INIT 0x0 7693#define B_FE_AD_REG_INVEXT_INIT 0x0
8775 7694
8776
8777#define B_FE_AD_REG_CLKNEG__A 0xC10015 7695#define B_FE_AD_REG_CLKNEG__A 0xC10015
8778#define B_FE_AD_REG_CLKNEG__W 1 7696#define B_FE_AD_REG_CLKNEG__W 1
8779#define B_FE_AD_REG_CLKNEG__M 0x1 7697#define B_FE_AD_REG_CLKNEG__M 0x1
8780#define B_FE_AD_REG_CLKNEG_INIT 0x0 7698#define B_FE_AD_REG_CLKNEG_INIT 0x0
8781 7699
8782
8783#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 7700#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016
8784#define B_FE_AD_REG_MON_IN_MUX__W 2 7701#define B_FE_AD_REG_MON_IN_MUX__W 2
8785#define B_FE_AD_REG_MON_IN_MUX__M 0x3 7702#define B_FE_AD_REG_MON_IN_MUX__M 0x3
8786#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 7703#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0
8787 7704
8788
8789#define B_FE_AD_REG_MON_IN5__A 0xC10017 7705#define B_FE_AD_REG_MON_IN5__A 0xC10017
8790#define B_FE_AD_REG_MON_IN5__W 10 7706#define B_FE_AD_REG_MON_IN5__W 10
8791#define B_FE_AD_REG_MON_IN5__M 0x3FF 7707#define B_FE_AD_REG_MON_IN5__M 0x3FF
8792#define B_FE_AD_REG_MON_IN5_INIT 0x0 7708#define B_FE_AD_REG_MON_IN5_INIT 0x0
8793 7709
8794
8795#define B_FE_AD_REG_MON_IN4__A 0xC10018 7710#define B_FE_AD_REG_MON_IN4__A 0xC10018
8796#define B_FE_AD_REG_MON_IN4__W 10 7711#define B_FE_AD_REG_MON_IN4__W 10
8797#define B_FE_AD_REG_MON_IN4__M 0x3FF 7712#define B_FE_AD_REG_MON_IN4__M 0x3FF
8798#define B_FE_AD_REG_MON_IN4_INIT 0x0 7713#define B_FE_AD_REG_MON_IN4_INIT 0x0
8799 7714
8800
8801#define B_FE_AD_REG_MON_IN3__A 0xC10019 7715#define B_FE_AD_REG_MON_IN3__A 0xC10019
8802#define B_FE_AD_REG_MON_IN3__W 10 7716#define B_FE_AD_REG_MON_IN3__W 10
8803#define B_FE_AD_REG_MON_IN3__M 0x3FF 7717#define B_FE_AD_REG_MON_IN3__M 0x3FF
8804#define B_FE_AD_REG_MON_IN3_INIT 0x0 7718#define B_FE_AD_REG_MON_IN3_INIT 0x0
8805 7719
8806
8807#define B_FE_AD_REG_MON_IN2__A 0xC1001A 7720#define B_FE_AD_REG_MON_IN2__A 0xC1001A
8808#define B_FE_AD_REG_MON_IN2__W 10 7721#define B_FE_AD_REG_MON_IN2__W 10
8809#define B_FE_AD_REG_MON_IN2__M 0x3FF 7722#define B_FE_AD_REG_MON_IN2__M 0x3FF
8810#define B_FE_AD_REG_MON_IN2_INIT 0x0 7723#define B_FE_AD_REG_MON_IN2_INIT 0x0
8811 7724
8812
8813#define B_FE_AD_REG_MON_IN1__A 0xC1001B 7725#define B_FE_AD_REG_MON_IN1__A 0xC1001B
8814#define B_FE_AD_REG_MON_IN1__W 10 7726#define B_FE_AD_REG_MON_IN1__W 10
8815#define B_FE_AD_REG_MON_IN1__M 0x3FF 7727#define B_FE_AD_REG_MON_IN1__M 0x3FF
8816#define B_FE_AD_REG_MON_IN1_INIT 0x0 7728#define B_FE_AD_REG_MON_IN1_INIT 0x0
8817 7729
8818
8819#define B_FE_AD_REG_MON_IN0__A 0xC1001C 7730#define B_FE_AD_REG_MON_IN0__A 0xC1001C
8820#define B_FE_AD_REG_MON_IN0__W 10 7731#define B_FE_AD_REG_MON_IN0__W 10
8821#define B_FE_AD_REG_MON_IN0__M 0x3FF 7732#define B_FE_AD_REG_MON_IN0__M 0x3FF
8822#define B_FE_AD_REG_MON_IN0_INIT 0x0 7733#define B_FE_AD_REG_MON_IN0_INIT 0x0
8823 7734
8824
8825#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D 7735#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D
8826#define B_FE_AD_REG_MON_IN_VAL__W 1 7736#define B_FE_AD_REG_MON_IN_VAL__W 1
8827#define B_FE_AD_REG_MON_IN_VAL__M 0x1 7737#define B_FE_AD_REG_MON_IN_VAL__M 0x1
8828#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 7738#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0
8829 7739
8830
8831#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E 7740#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E
8832#define B_FE_AD_REG_CTR_CLK_O__W 1 7741#define B_FE_AD_REG_CTR_CLK_O__W 1
8833#define B_FE_AD_REG_CTR_CLK_O__M 0x1 7742#define B_FE_AD_REG_CTR_CLK_O__M 0x1
8834#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 7743#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0
8835 7744
8836
8837#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F 7745#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F
8838#define B_FE_AD_REG_CTR_CLK_E_O__W 1 7746#define B_FE_AD_REG_CTR_CLK_E_O__W 1
8839#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 7747#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1
8840#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 7748#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1
8841 7749
8842
8843#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 7750#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020
8844#define B_FE_AD_REG_CTR_VAL_O__W 1 7751#define B_FE_AD_REG_CTR_VAL_O__W 1
8845#define B_FE_AD_REG_CTR_VAL_O__M 0x1 7752#define B_FE_AD_REG_CTR_VAL_O__M 0x1
8846#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 7753#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0
8847 7754
8848
8849#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 7755#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021
8850#define B_FE_AD_REG_CTR_VAL_E_O__W 1 7756#define B_FE_AD_REG_CTR_VAL_E_O__W 1
8851#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 7757#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1
8852#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 7758#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1
8853 7759
8854
8855#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 7760#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022
8856#define B_FE_AD_REG_CTR_DATA_O__W 10 7761#define B_FE_AD_REG_CTR_DATA_O__W 10
8857#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF 7762#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF
8858#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 7763#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0
8859 7764
8860
8861#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 7765#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023
8862#define B_FE_AD_REG_CTR_DATA_E_O__W 10 7766#define B_FE_AD_REG_CTR_DATA_E_O__W 10
8863#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF 7767#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF
8864#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF 7768#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF
8865 7769
8866
8867
8868
8869
8870#define B_FE_AG_SID 0x2 7770#define B_FE_AG_SID 0x2
8871 7771
8872
8873
8874
8875
8876
8877#define B_FE_AG_REG_COMM_EXEC__A 0xC20000 7772#define B_FE_AG_REG_COMM_EXEC__A 0xC20000
8878#define B_FE_AG_REG_COMM_EXEC__W 3 7773#define B_FE_AG_REG_COMM_EXEC__W 3
8879#define B_FE_AG_REG_COMM_EXEC__M 0x7 7774#define B_FE_AG_REG_COMM_EXEC__M 0x7
@@ -8905,7 +7800,6 @@ extern "C" {
8905#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 7800#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8
8906#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC 7801#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC
8907 7802
8908
8909#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 7803#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003
8910#define B_FE_AG_REG_COMM_SERVICE0__W 10 7804#define B_FE_AG_REG_COMM_SERVICE0__W 10
8911#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF 7805#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF
@@ -8939,7 +7833,6 @@ extern "C" {
8939#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 7833#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1
8940#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 7834#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80
8941 7835
8942
8943#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 7836#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008
8944#define B_FE_AG_REG_COMM_INT_MSK__W 8 7837#define B_FE_AG_REG_COMM_INT_MSK__W 8
8945#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF 7838#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF
@@ -8965,7 +7858,6 @@ extern "C" {
8965#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 7858#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1
8966#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 7859#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80
8967 7860
8968
8969#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 7861#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010
8970#define B_FE_AG_REG_AG_MODE_LOP__W 15 7862#define B_FE_AG_REG_AG_MODE_LOP__W 15
8971#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF 7863#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF
@@ -9055,7 +7947,6 @@ extern "C" {
9055#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 7947#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
9056#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 7948#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
9057 7949
9058
9059#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 7950#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011
9060#define B_FE_AG_REG_AG_MODE_HIP__W 5 7951#define B_FE_AG_REG_AG_MODE_HIP__W 5
9061#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F 7952#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F
@@ -9091,7 +7982,6 @@ extern "C" {
9091#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 7982#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0
9092#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 7983#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10
9093 7984
9094
9095#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 7985#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012
9096#define B_FE_AG_REG_AG_PGA_MODE__W 3 7986#define B_FE_AG_REG_AG_PGA_MODE__W 3
9097#define B_FE_AG_REG_AG_PGA_MODE__M 0x7 7987#define B_FE_AG_REG_AG_PGA_MODE__M 0x7
@@ -9105,7 +7995,6 @@ extern "C" {
9105#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 7995#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6
9106#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 7996#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7
9107 7997
9108
9109#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 7998#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013
9110#define B_FE_AG_REG_AG_AGC_SIO__W 2 7999#define B_FE_AG_REG_AG_AGC_SIO__W 2
9111#define B_FE_AG_REG_AG_AGC_SIO__M 0x3 8000#define B_FE_AG_REG_AG_AGC_SIO__M 0x3
@@ -9123,7 +8012,6 @@ extern "C" {
9123#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 8012#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
9124#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 8013#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
9125 8014
9126
9127#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 8015#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014
9128#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 8016#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2
9129#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 8017#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3
@@ -9134,7 +8022,6 @@ extern "C" {
9134#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 8022#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1
9135#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 8023#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2
9136 8024
9137
9138#define B_FE_AG_REG_AG_PWD__A 0xC20015 8025#define B_FE_AG_REG_AG_PWD__A 0xC20015
9139#define B_FE_AG_REG_AG_PWD__W 5 8026#define B_FE_AG_REG_AG_PWD__W 5
9140#define B_FE_AG_REG_AG_PWD__M 0x1F 8027#define B_FE_AG_REG_AG_PWD__M 0x1F
@@ -9170,19 +8057,16 @@ extern "C" {
9170#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 8057#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0
9171#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 8058#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10
9172 8059
9173
9174#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 8060#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016
9175#define B_FE_AG_REG_DCE_AUR_CNT__W 5 8061#define B_FE_AG_REG_DCE_AUR_CNT__W 5
9176#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F 8062#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F
9177#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 8063#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10
9178 8064
9179
9180#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 8065#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017
9181#define B_FE_AG_REG_DCE_RUR_CNT__W 5 8066#define B_FE_AG_REG_DCE_RUR_CNT__W 5
9182#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F 8067#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F
9183#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 8068#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0
9184 8069
9185
9186#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 8070#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018
9187#define B_FE_AG_REG_DCE_AVE_DAT__W 10 8071#define B_FE_AG_REG_DCE_AVE_DAT__W 10
9188#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF 8072#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF
@@ -9192,19 +8076,16 @@ extern "C" {
9192#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF 8076#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF
9193#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 8077#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0
9194 8078
9195
9196#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 8079#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
9197#define B_FE_AG_REG_ACE_AUR_CNT__W 5 8080#define B_FE_AG_REG_ACE_AUR_CNT__W 5
9198#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F 8081#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F
9199#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE 8082#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE
9200 8083
9201
9202#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 8084#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
9203#define B_FE_AG_REG_ACE_RUR_CNT__W 5 8085#define B_FE_AG_REG_ACE_RUR_CNT__W 5
9204#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F 8086#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F
9205#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 8087#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0
9206 8088
9207
9208#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C 8089#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C
9209#define B_FE_AG_REG_ACE_AVE_DAT__W 10 8090#define B_FE_AG_REG_ACE_AVE_DAT__W 10
9210#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF 8091#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF
@@ -9214,7 +8095,6 @@ extern "C" {
9214#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF 8095#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF
9215#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 8096#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0
9216 8097
9217
9218#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E 8098#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E
9219#define B_FE_AG_REG_AEC_AVE_DAT__W 10 8099#define B_FE_AG_REG_AEC_AVE_DAT__W 10
9220#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF 8100#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF
@@ -9224,13 +8104,11 @@ extern "C" {
9224#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF 8104#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF
9225#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 8105#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0
9226 8106
9227
9228#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 8107#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020
9229#define B_FE_AG_REG_CDR_RUR_CNT__W 5 8108#define B_FE_AG_REG_CDR_RUR_CNT__W 5
9230#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F 8109#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F
9231#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 8110#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10
9232 8111
9233
9234#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 8112#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021
9235#define B_FE_AG_REG_CDR_CLP_DAT__W 16 8113#define B_FE_AG_REG_CDR_CLP_DAT__W 16
9236#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF 8114#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF
@@ -9240,79 +8118,66 @@ extern "C" {
9240#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF 8118#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF
9241#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A 8119#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A
9242 8120
9243
9244#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 8121#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023
9245#define B_FE_AG_REG_CDR_CLP_NEG__W 10 8122#define B_FE_AG_REG_CDR_CLP_NEG__W 10
9246#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF 8123#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF
9247#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 8124#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296
9248 8125
9249
9250#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 8126#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024
9251#define B_FE_AG_REG_EGC_RUR_CNT__W 5 8127#define B_FE_AG_REG_EGC_RUR_CNT__W 5
9252#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F 8128#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F
9253#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 8129#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0
9254 8130
9255
9256#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 8131#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025
9257#define B_FE_AG_REG_EGC_SET_LVL__W 9 8132#define B_FE_AG_REG_EGC_SET_LVL__W 9
9258#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF 8133#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF
9259#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 8134#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46
9260 8135
9261
9262#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 8136#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026
9263#define B_FE_AG_REG_EGC_FLA_RGN__W 9 8137#define B_FE_AG_REG_EGC_FLA_RGN__W 9
9264#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF 8138#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF
9265#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 8139#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4
9266 8140
9267
9268#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 8141#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027
9269#define B_FE_AG_REG_EGC_SLO_RGN__W 9 8142#define B_FE_AG_REG_EGC_SLO_RGN__W 9
9270#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF 8143#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF
9271#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F 8144#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F
9272 8145
9273
9274#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 8146#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028
9275#define B_FE_AG_REG_EGC_JMP_PSN__W 4 8147#define B_FE_AG_REG_EGC_JMP_PSN__W 4
9276#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF 8148#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF
9277#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 8149#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0
9278 8150
9279
9280#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 8151#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029
9281#define B_FE_AG_REG_EGC_FLA_INC__W 16 8152#define B_FE_AG_REG_EGC_FLA_INC__W 16
9282#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF 8153#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF
9283#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 8154#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0
9284 8155
9285
9286#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 8156#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
9287#define B_FE_AG_REG_EGC_FLA_DEC__W 16 8157#define B_FE_AG_REG_EGC_FLA_DEC__W 16
9288#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF 8158#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF
9289#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 8159#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0
9290 8160
9291
9292#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B 8161#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B
9293#define B_FE_AG_REG_EGC_SLO_INC__W 16 8162#define B_FE_AG_REG_EGC_SLO_INC__W 16
9294#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF 8163#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF
9295#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 8164#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3
9296 8165
9297
9298#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 8166#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
9299#define B_FE_AG_REG_EGC_SLO_DEC__W 16 8167#define B_FE_AG_REG_EGC_SLO_DEC__W 16
9300#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF 8168#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF
9301#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 8169#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3
9302 8170
9303
9304#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D 8171#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D
9305#define B_FE_AG_REG_EGC_FAS_INC__W 16 8172#define B_FE_AG_REG_EGC_FAS_INC__W 16
9306#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF 8173#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF
9307#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE 8174#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE
9308 8175
9309
9310#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 8176#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
9311#define B_FE_AG_REG_EGC_FAS_DEC__W 16 8177#define B_FE_AG_REG_EGC_FAS_DEC__W 16
9312#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF 8178#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF
9313#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE 8179#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE
9314 8180
9315
9316#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F 8181#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F
9317#define B_FE_AG_REG_EGC_MAP_DAT__W 16 8182#define B_FE_AG_REG_EGC_MAP_DAT__W 16
9318#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF 8183#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF
@@ -9322,31 +8187,26 @@ extern "C" {
9322#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF 8187#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF
9323#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 8188#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0
9324 8189
9325
9326#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 8190#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031
9327#define B_FE_AG_REG_GC1_AGC_RIC__W 16 8191#define B_FE_AG_REG_GC1_AGC_RIC__W 16
9328#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF 8192#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF
9329#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 8193#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64
9330 8194
9331
9332#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 8195#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032
9333#define B_FE_AG_REG_GC1_AGC_OFF__W 16 8196#define B_FE_AG_REG_GC1_AGC_OFF__W 16
9334#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF 8197#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF
9335#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 8198#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8
9336 8199
9337
9338#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 8200#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033
9339#define B_FE_AG_REG_GC1_AGC_MAX__W 10 8201#define B_FE_AG_REG_GC1_AGC_MAX__W 10
9340#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF 8202#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF
9341#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF 8203#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF
9342 8204
9343
9344#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 8205#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034
9345#define B_FE_AG_REG_GC1_AGC_MIN__W 10 8206#define B_FE_AG_REG_GC1_AGC_MIN__W 10
9346#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF 8207#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF
9347#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 8208#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200
9348 8209
9349
9350#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 8210#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035
9351#define B_FE_AG_REG_GC1_AGC_DAT__W 10 8211#define B_FE_AG_REG_GC1_AGC_DAT__W 10
9352#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF 8212#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF
@@ -9356,31 +8216,26 @@ extern "C" {
9356#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF 8216#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF
9357#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 8217#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0
9358 8218
9359
9360#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 8219#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037
9361#define B_FE_AG_REG_GC2_AGC_RIC__W 16 8220#define B_FE_AG_REG_GC2_AGC_RIC__W 16
9362#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF 8221#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF
9363#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 8222#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64
9364 8223
9365
9366#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 8224#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038
9367#define B_FE_AG_REG_GC2_AGC_OFF__W 16 8225#define B_FE_AG_REG_GC2_AGC_OFF__W 16
9368#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF 8226#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF
9369#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 8227#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8
9370 8228
9371
9372#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 8229#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039
9373#define B_FE_AG_REG_GC2_AGC_MAX__W 10 8230#define B_FE_AG_REG_GC2_AGC_MAX__W 10
9374#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF 8231#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF
9375#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF 8232#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF
9376 8233
9377
9378#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A 8234#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A
9379#define B_FE_AG_REG_GC2_AGC_MIN__W 10 8235#define B_FE_AG_REG_GC2_AGC_MIN__W 10
9380#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF 8236#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF
9381#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 8237#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200
9382 8238
9383
9384#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B 8239#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B
9385#define B_FE_AG_REG_GC2_AGC_DAT__W 10 8240#define B_FE_AG_REG_GC2_AGC_DAT__W 10
9386#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF 8241#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF
@@ -9390,43 +8245,36 @@ extern "C" {
9390#define B_FE_AG_REG_IND_WIN__M 0x1F 8245#define B_FE_AG_REG_IND_WIN__M 0x1F
9391#define B_FE_AG_REG_IND_WIN_INIT 0x0 8246#define B_FE_AG_REG_IND_WIN_INIT 0x0
9392 8247
9393
9394#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D 8248#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D
9395#define B_FE_AG_REG_IND_THD_LOL__W 6 8249#define B_FE_AG_REG_IND_THD_LOL__W 6
9396#define B_FE_AG_REG_IND_THD_LOL__M 0x3F 8250#define B_FE_AG_REG_IND_THD_LOL__M 0x3F
9397#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 8251#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5
9398 8252
9399
9400#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E 8253#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E
9401#define B_FE_AG_REG_IND_THD_HIL__W 6 8254#define B_FE_AG_REG_IND_THD_HIL__W 6
9402#define B_FE_AG_REG_IND_THD_HIL__M 0x3F 8255#define B_FE_AG_REG_IND_THD_HIL__M 0x3F
9403#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF 8256#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF
9404 8257
9405
9406#define B_FE_AG_REG_IND_DEL__A 0xC2003F 8258#define B_FE_AG_REG_IND_DEL__A 0xC2003F
9407#define B_FE_AG_REG_IND_DEL__W 7 8259#define B_FE_AG_REG_IND_DEL__W 7
9408#define B_FE_AG_REG_IND_DEL__M 0x7F 8260#define B_FE_AG_REG_IND_DEL__M 0x7F
9409#define B_FE_AG_REG_IND_DEL_INIT 0x32 8261#define B_FE_AG_REG_IND_DEL_INIT 0x32
9410 8262
9411
9412#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 8263#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040
9413#define B_FE_AG_REG_IND_PD1_WRI__W 6 8264#define B_FE_AG_REG_IND_PD1_WRI__W 6
9414#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F 8265#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F
9415#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E 8266#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E
9416 8267
9417
9418#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 8268#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041
9419#define B_FE_AG_REG_PDA_AUR_CNT__W 5 8269#define B_FE_AG_REG_PDA_AUR_CNT__W 5
9420#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F 8270#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F
9421#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 8271#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10
9422 8272
9423
9424#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 8273#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042
9425#define B_FE_AG_REG_PDA_RUR_CNT__W 5 8274#define B_FE_AG_REG_PDA_RUR_CNT__W 5
9426#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F 8275#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F
9427#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 8276#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0
9428 8277
9429
9430#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 8278#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043
9431#define B_FE_AG_REG_PDA_AVE_DAT__W 6 8279#define B_FE_AG_REG_PDA_AVE_DAT__W 6
9432#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F 8280#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F
@@ -9436,43 +8284,36 @@ extern "C" {
9436#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F 8284#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F
9437#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 8285#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0
9438 8286
9439
9440#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 8287#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045
9441#define B_FE_AG_REG_PDC_SET_LVL__W 6 8288#define B_FE_AG_REG_PDC_SET_LVL__W 6
9442#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F 8289#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F
9443#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 8290#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10
9444 8291
9445
9446#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 8292#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046
9447#define B_FE_AG_REG_PDC_FLA_RGN__W 6 8293#define B_FE_AG_REG_PDC_FLA_RGN__W 6
9448#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F 8294#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F
9449#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 8295#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0
9450 8296
9451
9452#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 8297#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047
9453#define B_FE_AG_REG_PDC_JMP_PSN__W 3 8298#define B_FE_AG_REG_PDC_JMP_PSN__W 3
9454#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 8299#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7
9455#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 8300#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0
9456 8301
9457
9458#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 8302#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048
9459#define B_FE_AG_REG_PDC_FLA_STP__W 16 8303#define B_FE_AG_REG_PDC_FLA_STP__W 16
9460#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF 8304#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF
9461#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 8305#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0
9462 8306
9463
9464#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 8307#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049
9465#define B_FE_AG_REG_PDC_SLO_STP__W 16 8308#define B_FE_AG_REG_PDC_SLO_STP__W 16
9466#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF 8309#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF
9467#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 8310#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1
9468 8311
9469
9470#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 8312#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
9471#define B_FE_AG_REG_PDC_PD2_WRI__W 6 8313#define B_FE_AG_REG_PDC_PD2_WRI__W 6
9472#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F 8314#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F
9473#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F 8315#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F
9474 8316
9475
9476#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 8317#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
9477#define B_FE_AG_REG_PDC_MAP_DAT__W 6 8318#define B_FE_AG_REG_PDC_MAP_DAT__W 6
9478#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F 8319#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F
@@ -9482,19 +8323,16 @@ extern "C" {
9482#define B_FE_AG_REG_PDC_MAX__M 0x3F 8323#define B_FE_AG_REG_PDC_MAX__M 0x3F
9483#define B_FE_AG_REG_PDC_MAX_INIT 0x2 8324#define B_FE_AG_REG_PDC_MAX_INIT 0x2
9484 8325
9485
9486#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 8326#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
9487#define B_FE_AG_REG_TGA_AUR_CNT__W 5 8327#define B_FE_AG_REG_TGA_AUR_CNT__W 5
9488#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F 8328#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F
9489#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 8329#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10
9490 8330
9491
9492#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 8331#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
9493#define B_FE_AG_REG_TGA_RUR_CNT__W 5 8332#define B_FE_AG_REG_TGA_RUR_CNT__W 5
9494#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F 8333#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F
9495#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 8334#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0
9496 8335
9497
9498#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 8336#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
9499#define B_FE_AG_REG_TGA_AVE_DAT__W 6 8337#define B_FE_AG_REG_TGA_AVE_DAT__W 6
9500#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F 8338#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F
@@ -9504,37 +8342,31 @@ extern "C" {
9504#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F 8342#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F
9505#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 8343#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0
9506 8344
9507
9508#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 8345#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051
9509#define B_FE_AG_REG_TGC_SET_LVL__W 6 8346#define B_FE_AG_REG_TGC_SET_LVL__W 6
9510#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F 8347#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F
9511#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 8348#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18
9512 8349
9513
9514#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 8350#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052
9515#define B_FE_AG_REG_TGC_FLA_RGN__W 6 8351#define B_FE_AG_REG_TGC_FLA_RGN__W 6
9516#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F 8352#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F
9517#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 8353#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0
9518 8354
9519
9520#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 8355#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053
9521#define B_FE_AG_REG_TGC_JMP_PSN__W 4 8356#define B_FE_AG_REG_TGC_JMP_PSN__W 4
9522#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF 8357#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF
9523#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 8358#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0
9524 8359
9525
9526#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 8360#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054
9527#define B_FE_AG_REG_TGC_FLA_STP__W 16 8361#define B_FE_AG_REG_TGC_FLA_STP__W 16
9528#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF 8362#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF
9529#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 8363#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0
9530 8364
9531
9532#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 8365#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055
9533#define B_FE_AG_REG_TGC_SLO_STP__W 16 8366#define B_FE_AG_REG_TGC_SLO_STP__W 16
9534#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF 8367#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF
9535#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 8368#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1
9536 8369
9537
9538#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 8370#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056
9539#define B_FE_AG_REG_TGC_MAP_DAT__W 10 8371#define B_FE_AG_REG_TGC_MAP_DAT__W 10
9540#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF 8372#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF
@@ -9544,31 +8376,26 @@ extern "C" {
9544#define B_FE_AG_REG_FGM_WRI__M 0x3FF 8376#define B_FE_AG_REG_FGM_WRI__M 0x3FF
9545#define B_FE_AG_REG_FGM_WRI_INIT 0x80 8377#define B_FE_AG_REG_FGM_WRI_INIT 0x80
9546 8378
9547
9548#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 8379#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068
9549#define B_FE_AG_REG_BGC_FGC_WRI__W 4 8380#define B_FE_AG_REG_BGC_FGC_WRI__W 4
9550#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF 8381#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF
9551#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 8382#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0
9552 8383
9553
9554#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 8384#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069
9555#define B_FE_AG_REG_BGC_CGC_WRI__W 2 8385#define B_FE_AG_REG_BGC_CGC_WRI__W 2
9556#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 8386#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3
9557#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 8387#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0
9558 8388
9559
9560#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B 8389#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B
9561#define B_FE_AG_REG_BGC_THD_LVL__W 4 8390#define B_FE_AG_REG_BGC_THD_LVL__W 4
9562#define B_FE_AG_REG_BGC_THD_LVL__M 0xF 8391#define B_FE_AG_REG_BGC_THD_LVL__M 0xF
9563#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF 8392#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF
9564 8393
9565
9566#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C 8394#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C
9567#define B_FE_AG_REG_BGC_THD_INC__W 4 8395#define B_FE_AG_REG_BGC_THD_INC__W 4
9568#define B_FE_AG_REG_BGC_THD_INC__M 0xF 8396#define B_FE_AG_REG_BGC_THD_INC__M 0xF
9569#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 8397#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8
9570 8398
9571
9572#define B_FE_AG_REG_BGC_DAT__A 0xC2006D 8399#define B_FE_AG_REG_BGC_DAT__A 0xC2006D
9573#define B_FE_AG_REG_BGC_DAT__W 4 8400#define B_FE_AG_REG_BGC_DAT__W 4
9574#define B_FE_AG_REG_BGC_DAT__M 0xF 8401#define B_FE_AG_REG_BGC_DAT__M 0xF
@@ -9578,7 +8405,6 @@ extern "C" {
9578#define B_FE_AG_REG_IND_PD1_COM__M 0x3F 8405#define B_FE_AG_REG_IND_PD1_COM__M 0x3F
9579#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 8406#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7
9580 8407
9581
9582#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F 8408#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F
9583#define B_FE_AG_REG_AG_AGC_BUF__W 2 8409#define B_FE_AG_REG_AG_AGC_BUF__W 2
9584#define B_FE_AG_REG_AG_AGC_BUF__M 0x3 8410#define B_FE_AG_REG_AG_AGC_BUF__M 0x3
@@ -9596,7 +8422,6 @@ extern "C" {
9596#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 8422#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0
9597#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 8423#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2
9598 8424
9599
9600#define B_FE_AG_REG_PMX_SPE__A 0xC20070 8425#define B_FE_AG_REG_PMX_SPE__A 0xC20070
9601#define B_FE_AG_REG_PMX_SPE__W 3 8426#define B_FE_AG_REG_PMX_SPE__W 3
9602#define B_FE_AG_REG_PMX_SPE__M 0x7 8427#define B_FE_AG_REG_PMX_SPE__M 0x7
@@ -9610,17 +8435,8 @@ extern "C" {
9610#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 8435#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6
9611#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 8436#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7
9612 8437
9613
9614
9615
9616
9617#define B_FE_FS_SID 0x3 8438#define B_FE_FS_SID 0x3
9618 8439
9619
9620
9621
9622
9623
9624#define B_FE_FS_REG_COMM_EXEC__A 0xC30000 8440#define B_FE_FS_REG_COMM_EXEC__A 0xC30000
9625#define B_FE_FS_REG_COMM_EXEC__W 3 8441#define B_FE_FS_REG_COMM_EXEC__W 3
9626#define B_FE_FS_REG_COMM_EXEC__M 0x7 8442#define B_FE_FS_REG_COMM_EXEC__M 0x7
@@ -9655,7 +8471,6 @@ extern "C" {
9655#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 8471#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0
9656#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 8472#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4
9657 8473
9658
9659#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 8474#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003
9660#define B_FE_FS_REG_COMM_SERVICE0__W 10 8475#define B_FE_FS_REG_COMM_SERVICE0__W 10
9661#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF 8476#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF
@@ -9677,35 +8492,23 @@ extern "C" {
9677#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF 8492#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF
9678#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 8493#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0
9679 8494
9680
9681#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 8495#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011
9682#define B_FE_FS_REG_ADD_INC_HIP__W 12 8496#define B_FE_FS_REG_ADD_INC_HIP__W 12
9683#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF 8497#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF
9684#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 8498#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00
9685 8499
9686
9687#define B_FE_FS_REG_ADD_OFF__A 0xC30012 8500#define B_FE_FS_REG_ADD_OFF__A 0xC30012
9688#define B_FE_FS_REG_ADD_OFF__W 12 8501#define B_FE_FS_REG_ADD_OFF__W 12
9689#define B_FE_FS_REG_ADD_OFF__M 0xFFF 8502#define B_FE_FS_REG_ADD_OFF__M 0xFFF
9690#define B_FE_FS_REG_ADD_OFF_INIT 0x0 8503#define B_FE_FS_REG_ADD_OFF_INIT 0x0
9691 8504
9692
9693#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 8505#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013
9694#define B_FE_FS_REG_ADD_OFF_VAL__W 1 8506#define B_FE_FS_REG_ADD_OFF_VAL__W 1
9695#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 8507#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1
9696#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 8508#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0
9697 8509
9698
9699
9700
9701
9702#define B_FE_FD_SID 0x4 8510#define B_FE_FD_SID 0x4
9703 8511
9704
9705
9706
9707
9708
9709#define B_FE_FD_REG_COMM_EXEC__A 0xC40000 8512#define B_FE_FD_REG_COMM_EXEC__A 0xC40000
9710#define B_FE_FD_REG_COMM_EXEC__W 3 8513#define B_FE_FD_REG_COMM_EXEC__W 3
9711#define B_FE_FD_REG_COMM_EXEC__M 0x7 8514#define B_FE_FD_REG_COMM_EXEC__M 0x7
@@ -9717,7 +8520,6 @@ extern "C" {
9717#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 8520#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2
9718#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 8521#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3
9719 8522
9720
9721#define B_FE_FD_REG_COMM_MB__A 0xC40002 8523#define B_FE_FD_REG_COMM_MB__A 0xC40002
9722#define B_FE_FD_REG_COMM_MB__W 3 8524#define B_FE_FD_REG_COMM_MB__W 3
9723#define B_FE_FD_REG_COMM_MB__M 0x7 8525#define B_FE_FD_REG_COMM_MB__M 0x7
@@ -9746,7 +8548,6 @@ extern "C" {
9746#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 8548#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1
9747#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 8549#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1
9748 8550
9749
9750#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 8551#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008
9751#define B_FE_FD_REG_COMM_INT_MSK__W 1 8552#define B_FE_FD_REG_COMM_INT_MSK__W 1
9752#define B_FE_FD_REG_COMM_INT_MSK__M 0x1 8553#define B_FE_FD_REG_COMM_INT_MSK__M 0x1
@@ -9754,7 +8555,6 @@ extern "C" {
9754#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 8555#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1
9755#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 8556#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
9756 8557
9757
9758#define B_FE_FD_REG_SCL__A 0xC40010 8558#define B_FE_FD_REG_SCL__A 0xC40010
9759#define B_FE_FD_REG_SCL__W 6 8559#define B_FE_FD_REG_SCL__W 6
9760#define B_FE_FD_REG_SCL__M 0x3F 8560#define B_FE_FD_REG_SCL__M 0x3F
@@ -9779,17 +8579,8 @@ extern "C" {
9779#define B_FE_FD_REG_MAX__W 16 8579#define B_FE_FD_REG_MAX__W 16
9780#define B_FE_FD_REG_MAX__M 0xFFFF 8580#define B_FE_FD_REG_MAX__M 0xFFFF
9781 8581
9782
9783
9784
9785
9786#define B_FE_IF_SID 0x5 8582#define B_FE_IF_SID 0x5
9787 8583
9788
9789
9790
9791
9792
9793#define B_FE_IF_REG_COMM_EXEC__A 0xC50000 8584#define B_FE_IF_REG_COMM_EXEC__A 0xC50000
9794#define B_FE_IF_REG_COMM_EXEC__W 3 8585#define B_FE_IF_REG_COMM_EXEC__W 3
9795#define B_FE_IF_REG_COMM_EXEC__M 0x7 8586#define B_FE_IF_REG_COMM_EXEC__M 0x7
@@ -9801,7 +8592,6 @@ extern "C" {
9801#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 8592#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2
9802#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 8593#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3
9803 8594
9804
9805#define B_FE_IF_REG_COMM_MB__A 0xC50002 8595#define B_FE_IF_REG_COMM_MB__A 0xC50002
9806#define B_FE_IF_REG_COMM_MB__W 3 8596#define B_FE_IF_REG_COMM_MB__W 3
9807#define B_FE_IF_REG_COMM_MB__M 0x7 8597#define B_FE_IF_REG_COMM_MB__M 0x7
@@ -9816,29 +8606,18 @@ extern "C" {
9816#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 8606#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0
9817#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 8607#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2
9818 8608
9819
9820#define B_FE_IF_REG_INCR0__A 0xC50010 8609#define B_FE_IF_REG_INCR0__A 0xC50010
9821#define B_FE_IF_REG_INCR0__W 16 8610#define B_FE_IF_REG_INCR0__W 16
9822#define B_FE_IF_REG_INCR0__M 0xFFFF 8611#define B_FE_IF_REG_INCR0__M 0xFFFF
9823#define B_FE_IF_REG_INCR0_INIT 0x0 8612#define B_FE_IF_REG_INCR0_INIT 0x0
9824 8613
9825
9826#define B_FE_IF_REG_INCR1__A 0xC50011 8614#define B_FE_IF_REG_INCR1__A 0xC50011
9827#define B_FE_IF_REG_INCR1__W 8 8615#define B_FE_IF_REG_INCR1__W 8
9828#define B_FE_IF_REG_INCR1__M 0xFF 8616#define B_FE_IF_REG_INCR1__M 0xFF
9829#define B_FE_IF_REG_INCR1_INIT 0x28 8617#define B_FE_IF_REG_INCR1_INIT 0x28
9830 8618
9831
9832
9833
9834
9835#define B_FE_CF_SID 0x6 8619#define B_FE_CF_SID 0x6
9836 8620
9837
9838
9839
9840
9841
9842#define B_FE_CF_REG_COMM_EXEC__A 0xC60000 8621#define B_FE_CF_REG_COMM_EXEC__A 0xC60000
9843#define B_FE_CF_REG_COMM_EXEC__W 3 8622#define B_FE_CF_REG_COMM_EXEC__W 3
9844#define B_FE_CF_REG_COMM_EXEC__M 0x7 8623#define B_FE_CF_REG_COMM_EXEC__M 0x7
@@ -9850,7 +8629,6 @@ extern "C" {
9850#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 8629#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2
9851#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 8630#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3
9852 8631
9853
9854#define B_FE_CF_REG_COMM_MB__A 0xC60002 8632#define B_FE_CF_REG_COMM_MB__A 0xC60002
9855#define B_FE_CF_REG_COMM_MB__W 3 8633#define B_FE_CF_REG_COMM_MB__W 3
9856#define B_FE_CF_REG_COMM_MB__M 0x7 8634#define B_FE_CF_REG_COMM_MB__M 0x7
@@ -9879,7 +8657,6 @@ extern "C" {
9879#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 8657#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1
9880#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 8658#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1
9881 8659
9882
9883#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 8660#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008
9884#define B_FE_CF_REG_COMM_INT_MSK__W 2 8661#define B_FE_CF_REG_COMM_INT_MSK__W 2
9885#define B_FE_CF_REG_COMM_INT_MSK__M 0x3 8662#define B_FE_CF_REG_COMM_INT_MSK__M 0x3
@@ -9887,7 +8664,6 @@ extern "C" {
9887#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 8664#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1
9888#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 8665#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
9889 8666
9890
9891#define B_FE_CF_REG_SCL__A 0xC60010 8667#define B_FE_CF_REG_SCL__A 0xC60010
9892#define B_FE_CF_REG_SCL__W 9 8668#define B_FE_CF_REG_SCL__W 9
9893#define B_FE_CF_REG_SCL__M 0x1FF 8669#define B_FE_CF_REG_SCL__M 0x1FF
@@ -9912,17 +8688,8 @@ extern "C" {
9912#define B_FE_CF_REG_MAX__W 16 8688#define B_FE_CF_REG_MAX__W 16
9913#define B_FE_CF_REG_MAX__M 0xFFFF 8689#define B_FE_CF_REG_MAX__M 0xFFFF
9914 8690
9915
9916
9917
9918
9919#define B_FE_CU_SID 0x7 8691#define B_FE_CU_SID 0x7
9920 8692
9921
9922
9923
9924
9925
9926#define B_FE_CU_REG_COMM_EXEC__A 0xC70000 8693#define B_FE_CU_REG_COMM_EXEC__A 0xC70000
9927#define B_FE_CU_REG_COMM_EXEC__W 3 8694#define B_FE_CU_REG_COMM_EXEC__W 3
9928#define B_FE_CU_REG_COMM_EXEC__M 0x7 8695#define B_FE_CU_REG_COMM_EXEC__M 0x7
@@ -9957,7 +8724,6 @@ extern "C" {
9957#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 8724#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0
9958#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 8725#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4
9959 8726
9960
9961#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 8727#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003
9962#define B_FE_CU_REG_COMM_SERVICE0__W 10 8728#define B_FE_CU_REG_COMM_SERVICE0__W 10
9963#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF 8729#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF
@@ -9990,7 +8756,6 @@ extern "C" {
9990#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 8756#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1
9991#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 8757#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8
9992 8758
9993
9994#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 8759#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008
9995#define B_FE_CU_REG_COMM_INT_MSK__W 4 8760#define B_FE_CU_REG_COMM_INT_MSK__W 4
9996#define B_FE_CU_REG_COMM_INT_MSK__M 0xF 8761#define B_FE_CU_REG_COMM_INT_MSK__M 0xF
@@ -10007,7 +8772,6 @@ extern "C" {
10007#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 8772#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1
10008#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 8773#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8
10009 8774
10010
10011#define B_FE_CU_REG_MODE__A 0xC70010 8775#define B_FE_CU_REG_MODE__A 0xC70010
10012#define B_FE_CU_REG_MODE__W 5 8776#define B_FE_CU_REG_MODE__W 5
10013#define B_FE_CU_REG_MODE__M 0x1F 8777#define B_FE_CU_REG_MODE__M 0x1F
@@ -10043,19 +8807,16 @@ extern "C" {
10043#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 8807#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0
10044#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 8808#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10
10045 8809
10046
10047#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 8810#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011
10048#define B_FE_CU_REG_FRM_CNT_RST__W 15 8811#define B_FE_CU_REG_FRM_CNT_RST__W 15
10049#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF 8812#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF
10050#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF 8813#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF
10051 8814
10052
10053#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 8815#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012
10054#define B_FE_CU_REG_FRM_CNT_STR__W 15 8816#define B_FE_CU_REG_FRM_CNT_STR__W 15
10055#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF 8817#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF
10056#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E 8818#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E
10057 8819
10058
10059#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 8820#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013
10060#define B_FE_CU_REG_FRM_SMP_CNT__W 15 8821#define B_FE_CU_REG_FRM_SMP_CNT__W 15
10061#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF 8822#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF
@@ -10077,19 +8838,16 @@ extern "C" {
10077#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF 8838#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF
10078#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 8839#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0
10079 8840
10080
10081#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 8841#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020
10082#define B_FE_CU_REG_CTR_NFC_ICR__W 5 8842#define B_FE_CU_REG_CTR_NFC_ICR__W 5
10083#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F 8843#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F
10084#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 8844#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0
10085 8845
10086
10087#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 8846#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021
10088#define B_FE_CU_REG_CTR_NFC_OCR__W 15 8847#define B_FE_CU_REG_CTR_NFC_OCR__W 15
10089#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF 8848#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF
10090#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 8849#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8
10091 8850
10092
10093#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 8851#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022
10094#define B_FE_CU_REG_CTR_NFC_CNT__W 15 8852#define B_FE_CU_REG_CTR_NFC_CNT__W 15
10095#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF 8853#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF
@@ -10102,7 +8860,6 @@ extern "C" {
10102#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 8860#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2
10103#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 8861#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4
10104 8862
10105
10106#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 8863#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024
10107#define B_FE_CU_REG_DIV_NFC_REA__W 14 8864#define B_FE_CU_REG_DIV_NFC_REA__W 14
10108#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF 8865#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF
@@ -10116,7 +8873,6 @@ extern "C" {
10116#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF 8873#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF
10117#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF 8874#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF
10118 8875
10119
10120#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 8876#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027
10121#define B_FE_CU_REG_DIV_NFC_CLP__W 2 8877#define B_FE_CU_REG_DIV_NFC_CLP__W 2
10122#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 8878#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3
@@ -10126,24 +8882,12 @@ extern "C" {
10126#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 8882#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2
10127#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 8883#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3
10128 8884
10129
10130
10131#define B_FE_CU_BUF_RAM__A 0xC80000 8885#define B_FE_CU_BUF_RAM__A 0xC80000
10132 8886
10133
10134
10135#define B_FE_CU_CMP_RAM__A 0xC90000 8887#define B_FE_CU_CMP_RAM__A 0xC90000
10136 8888
10137
10138
10139
10140
10141#define B_FT_SID 0x8 8889#define B_FT_SID 0x8
10142 8890
10143
10144
10145
10146
10147#define B_FT_COMM_EXEC__A 0x1000000 8891#define B_FT_COMM_EXEC__A 0x1000000
10148#define B_FT_COMM_EXEC__W 3 8892#define B_FT_COMM_EXEC__W 3
10149#define B_FT_COMM_EXEC__M 0x7 8893#define B_FT_COMM_EXEC__M 0x7
@@ -10176,11 +8920,6 @@ extern "C" {
10176#define B_FT_COMM_INT_MSK__W 16 8920#define B_FT_COMM_INT_MSK__W 16
10177#define B_FT_COMM_INT_MSK__M 0xFFFF 8921#define B_FT_COMM_INT_MSK__M 0xFFFF
10178 8922
10179
10180
10181
10182
10183
10184#define B_FT_REG_COMM_EXEC__A 0x1010000 8923#define B_FT_REG_COMM_EXEC__A 0x1010000
10185#define B_FT_REG_COMM_EXEC__W 3 8924#define B_FT_REG_COMM_EXEC__W 3
10186#define B_FT_REG_COMM_EXEC__M 0x7 8925#define B_FT_REG_COMM_EXEC__M 0x7
@@ -10192,7 +8931,6 @@ extern "C" {
10192#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 8931#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2
10193#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 8932#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3
10194 8933
10195
10196#define B_FT_REG_COMM_MB__A 0x1010002 8934#define B_FT_REG_COMM_MB__A 0x1010002
10197#define B_FT_REG_COMM_MB__W 3 8935#define B_FT_REG_COMM_MB__W 3
10198#define B_FT_REG_COMM_MB__M 0x7 8936#define B_FT_REG_COMM_MB__M 0x7
@@ -10207,7 +8945,6 @@ extern "C" {
10207#define B_FT_REG_COMM_MB_OBS_OFF 0x0 8945#define B_FT_REG_COMM_MB_OBS_OFF 0x0
10208#define B_FT_REG_COMM_MB_OBS_ON 0x2 8946#define B_FT_REG_COMM_MB_OBS_ON 0x2
10209 8947
10210
10211#define B_FT_REG_MODE_2K__A 0x1010010 8948#define B_FT_REG_MODE_2K__A 0x1010010
10212#define B_FT_REG_MODE_2K__W 1 8949#define B_FT_REG_MODE_2K__W 1
10213#define B_FT_REG_MODE_2K__M 0x1 8950#define B_FT_REG_MODE_2K__M 0x1
@@ -10215,50 +8952,27 @@ extern "C" {
10215#define B_FT_REG_MODE_2K_MODE_2K 0x1 8952#define B_FT_REG_MODE_2K_MODE_2K 0x1
10216#define B_FT_REG_MODE_2K_INIT 0x0 8953#define B_FT_REG_MODE_2K_INIT 0x0
10217 8954
10218
10219#define B_FT_REG_NORM_OFF__A 0x1010016 8955#define B_FT_REG_NORM_OFF__A 0x1010016
10220#define B_FT_REG_NORM_OFF__W 4 8956#define B_FT_REG_NORM_OFF__W 4
10221#define B_FT_REG_NORM_OFF__M 0xF 8957#define B_FT_REG_NORM_OFF__M 0xF
10222#define B_FT_REG_NORM_OFF_INIT 0x2 8958#define B_FT_REG_NORM_OFF_INIT 0x2
10223 8959
10224
10225
10226#define B_FT_ST1_RAM__A 0x1020000 8960#define B_FT_ST1_RAM__A 0x1020000
10227 8961
10228
10229
10230#define B_FT_ST2_RAM__A 0x1030000 8962#define B_FT_ST2_RAM__A 0x1030000
10231 8963
10232
10233
10234#define B_FT_ST3_RAM__A 0x1040000 8964#define B_FT_ST3_RAM__A 0x1040000
10235 8965
10236
10237
10238#define B_FT_ST5_RAM__A 0x1050000 8966#define B_FT_ST5_RAM__A 0x1050000
10239 8967
10240
10241
10242#define B_FT_ST6_RAM__A 0x1060000 8968#define B_FT_ST6_RAM__A 0x1060000
10243 8969
10244
10245
10246#define B_FT_ST8_RAM__A 0x1070000 8970#define B_FT_ST8_RAM__A 0x1070000
10247 8971
10248
10249
10250#define B_FT_ST9_RAM__A 0x1080000 8972#define B_FT_ST9_RAM__A 0x1080000
10251 8973
10252
10253
10254
10255
10256#define B_CP_SID 0x9 8974#define B_CP_SID 0x9
10257 8975
10258
10259
10260
10261
10262#define B_CP_COMM_EXEC__A 0x1400000 8976#define B_CP_COMM_EXEC__A 0x1400000
10263#define B_CP_COMM_EXEC__W 3 8977#define B_CP_COMM_EXEC__W 3
10264#define B_CP_COMM_EXEC__M 0x7 8978#define B_CP_COMM_EXEC__M 0x7
@@ -10291,11 +9005,6 @@ extern "C" {
10291#define B_CP_COMM_INT_MSK__W 16 9005#define B_CP_COMM_INT_MSK__W 16
10292#define B_CP_COMM_INT_MSK__M 0xFFFF 9006#define B_CP_COMM_INT_MSK__M 0xFFFF
10293 9007
10294
10295
10296
10297
10298
10299#define B_CP_REG_COMM_EXEC__A 0x1410000 9008#define B_CP_REG_COMM_EXEC__A 0x1410000
10300#define B_CP_REG_COMM_EXEC__W 3 9009#define B_CP_REG_COMM_EXEC__W 3
10301#define B_CP_REG_COMM_EXEC__M 0x7 9010#define B_CP_REG_COMM_EXEC__M 0x7
@@ -10307,7 +9016,6 @@ extern "C" {
10307#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 9016#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2
10308#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 9017#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3
10309 9018
10310
10311#define B_CP_REG_COMM_MB__A 0x1410002 9019#define B_CP_REG_COMM_MB__A 0x1410002
10312#define B_CP_REG_COMM_MB__W 3 9020#define B_CP_REG_COMM_MB__W 3
10313#define B_CP_REG_COMM_MB__M 0x7 9021#define B_CP_REG_COMM_MB__M 0x7
@@ -10340,7 +9048,6 @@ extern "C" {
10340#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 9048#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1
10341#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 9049#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1
10342 9050
10343
10344#define B_CP_REG_COMM_INT_MSK__A 0x1410008 9051#define B_CP_REG_COMM_INT_MSK__A 0x1410008
10345#define B_CP_REG_COMM_INT_MSK__W 2 9052#define B_CP_REG_COMM_INT_MSK__W 2
10346#define B_CP_REG_COMM_INT_MSK__M 0x3 9053#define B_CP_REG_COMM_INT_MSK__M 0x3
@@ -10348,19 +9055,16 @@ extern "C" {
10348#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 9055#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1
10349#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 9056#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
10350 9057
10351
10352#define B_CP_REG_MODE_2K__A 0x1410010 9058#define B_CP_REG_MODE_2K__A 0x1410010
10353#define B_CP_REG_MODE_2K__W 1 9059#define B_CP_REG_MODE_2K__W 1
10354#define B_CP_REG_MODE_2K__M 0x1 9060#define B_CP_REG_MODE_2K__M 0x1
10355#define B_CP_REG_MODE_2K_INIT 0x0 9061#define B_CP_REG_MODE_2K_INIT 0x0
10356 9062
10357
10358#define B_CP_REG_INTERVAL__A 0x1410011 9063#define B_CP_REG_INTERVAL__A 0x1410011
10359#define B_CP_REG_INTERVAL__W 4 9064#define B_CP_REG_INTERVAL__W 4
10360#define B_CP_REG_INTERVAL__M 0xF 9065#define B_CP_REG_INTERVAL__M 0xF
10361#define B_CP_REG_INTERVAL_INIT 0x5 9066#define B_CP_REG_INTERVAL_INIT 0x5
10362 9067
10363
10364#define B_CP_REG_DETECT_ENA__A 0x1410012 9068#define B_CP_REG_DETECT_ENA__A 0x1410012
10365#define B_CP_REG_DETECT_ENA__W 2 9069#define B_CP_REG_DETECT_ENA__W 2
10366#define B_CP_REG_DETECT_ENA__M 0x3 9070#define B_CP_REG_DETECT_ENA__M 0x3
@@ -10374,7 +9078,6 @@ extern "C" {
10374#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 9078#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2
10375#define B_CP_REG_DETECT_ENA_INIT 0x0 9079#define B_CP_REG_DETECT_ENA_INIT 0x0
10376 9080
10377
10378#define B_CP_REG_BR_SMB_NR__A 0x1410021 9081#define B_CP_REG_BR_SMB_NR__A 0x1410021
10379#define B_CP_REG_BR_SMB_NR__W 4 9082#define B_CP_REG_BR_SMB_NR__W 4
10380#define B_CP_REG_BR_SMB_NR__M 0xF 9083#define B_CP_REG_BR_SMB_NR__M 0xF
@@ -10392,79 +9095,66 @@ extern "C" {
10392#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 9095#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8
10393#define B_CP_REG_BR_SMB_NR_INIT 0x0 9096#define B_CP_REG_BR_SMB_NR_INIT 0x0
10394 9097
10395
10396#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 9098#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022
10397#define B_CP_REG_BR_CP_SMB_NR__W 2 9099#define B_CP_REG_BR_CP_SMB_NR__W 2
10398#define B_CP_REG_BR_CP_SMB_NR__M 0x3 9100#define B_CP_REG_BR_CP_SMB_NR__M 0x3
10399#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 9101#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0
10400 9102
10401
10402#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 9103#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023
10403#define B_CP_REG_BR_SPL_OFFSET__W 3 9104#define B_CP_REG_BR_SPL_OFFSET__W 3
10404#define B_CP_REG_BR_SPL_OFFSET__M 0x7 9105#define B_CP_REG_BR_SPL_OFFSET__M 0x7
10405#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 9106#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0
10406 9107
10407
10408#define B_CP_REG_BR_STR_DEL__A 0x1410024 9108#define B_CP_REG_BR_STR_DEL__A 0x1410024
10409#define B_CP_REG_BR_STR_DEL__W 10 9109#define B_CP_REG_BR_STR_DEL__W 10
10410#define B_CP_REG_BR_STR_DEL__M 0x3FF 9110#define B_CP_REG_BR_STR_DEL__M 0x3FF
10411#define B_CP_REG_BR_STR_DEL_INIT 0xA 9111#define B_CP_REG_BR_STR_DEL_INIT 0xA
10412 9112
10413
10414#define B_CP_REG_BR_EXP_ADJ__A 0x1410025 9113#define B_CP_REG_BR_EXP_ADJ__A 0x1410025
10415#define B_CP_REG_BR_EXP_ADJ__W 5 9114#define B_CP_REG_BR_EXP_ADJ__W 5
10416#define B_CP_REG_BR_EXP_ADJ__M 0x1F 9115#define B_CP_REG_BR_EXP_ADJ__M 0x1F
10417#define B_CP_REG_BR_EXP_ADJ_INIT 0x10 9116#define B_CP_REG_BR_EXP_ADJ_INIT 0x10
10418 9117
10419
10420#define B_CP_REG_RT_ANG_INC0__A 0x1410030 9118#define B_CP_REG_RT_ANG_INC0__A 0x1410030
10421#define B_CP_REG_RT_ANG_INC0__W 16 9119#define B_CP_REG_RT_ANG_INC0__W 16
10422#define B_CP_REG_RT_ANG_INC0__M 0xFFFF 9120#define B_CP_REG_RT_ANG_INC0__M 0xFFFF
10423#define B_CP_REG_RT_ANG_INC0_INIT 0x0 9121#define B_CP_REG_RT_ANG_INC0_INIT 0x0
10424 9122
10425
10426#define B_CP_REG_RT_ANG_INC1__A 0x1410031 9123#define B_CP_REG_RT_ANG_INC1__A 0x1410031
10427#define B_CP_REG_RT_ANG_INC1__W 8 9124#define B_CP_REG_RT_ANG_INC1__W 8
10428#define B_CP_REG_RT_ANG_INC1__M 0xFF 9125#define B_CP_REG_RT_ANG_INC1__M 0xFF
10429#define B_CP_REG_RT_ANG_INC1_INIT 0x0 9126#define B_CP_REG_RT_ANG_INC1_INIT 0x0
10430 9127
10431
10432#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 9128#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032
10433#define B_CP_REG_RT_SPD_EXP_MARG__W 5 9129#define B_CP_REG_RT_SPD_EXP_MARG__W 5
10434#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F 9130#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F
10435#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 9131#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5
10436 9132
10437
10438#define B_CP_REG_RT_DETECT_TRH__A 0x1410033 9133#define B_CP_REG_RT_DETECT_TRH__A 0x1410033
10439#define B_CP_REG_RT_DETECT_TRH__W 2 9134#define B_CP_REG_RT_DETECT_TRH__W 2
10440#define B_CP_REG_RT_DETECT_TRH__M 0x3 9135#define B_CP_REG_RT_DETECT_TRH__M 0x3
10441#define B_CP_REG_RT_DETECT_TRH_INIT 0x3 9136#define B_CP_REG_RT_DETECT_TRH_INIT 0x3
10442 9137
10443
10444#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 9138#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034
10445#define B_CP_REG_RT_SPD_RELIABLE__W 3 9139#define B_CP_REG_RT_SPD_RELIABLE__W 3
10446#define B_CP_REG_RT_SPD_RELIABLE__M 0x7 9140#define B_CP_REG_RT_SPD_RELIABLE__M 0x7
10447#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 9141#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0
10448 9142
10449
10450#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 9143#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035
10451#define B_CP_REG_RT_SPD_DIRECTION__W 1 9144#define B_CP_REG_RT_SPD_DIRECTION__W 1
10452#define B_CP_REG_RT_SPD_DIRECTION__M 0x1 9145#define B_CP_REG_RT_SPD_DIRECTION__M 0x1
10453#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 9146#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0
10454 9147
10455
10456#define B_CP_REG_RT_SPD_MOD__A 0x1410036 9148#define B_CP_REG_RT_SPD_MOD__A 0x1410036
10457#define B_CP_REG_RT_SPD_MOD__W 2 9149#define B_CP_REG_RT_SPD_MOD__W 2
10458#define B_CP_REG_RT_SPD_MOD__M 0x3 9150#define B_CP_REG_RT_SPD_MOD__M 0x3
10459#define B_CP_REG_RT_SPD_MOD_INIT 0x0 9151#define B_CP_REG_RT_SPD_MOD_INIT 0x0
10460 9152
10461
10462#define B_CP_REG_RT_SPD_SMB__A 0x1410037 9153#define B_CP_REG_RT_SPD_SMB__A 0x1410037
10463#define B_CP_REG_RT_SPD_SMB__W 2 9154#define B_CP_REG_RT_SPD_SMB__W 2
10464#define B_CP_REG_RT_SPD_SMB__M 0x3 9155#define B_CP_REG_RT_SPD_SMB__M 0x3
10465#define B_CP_REG_RT_SPD_SMB_INIT 0x0 9156#define B_CP_REG_RT_SPD_SMB_INIT 0x0
10466 9157
10467
10468#define B_CP_REG_RT_CPD_MODE__A 0x1410038 9158#define B_CP_REG_RT_CPD_MODE__A 0x1410038
10469#define B_CP_REG_RT_CPD_MODE__W 3 9159#define B_CP_REG_RT_CPD_MODE__W 3
10470#define B_CP_REG_RT_CPD_MODE__M 0x7 9160#define B_CP_REG_RT_CPD_MODE__M 0x7
@@ -10478,25 +9168,21 @@ extern "C" {
10478#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 9168#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4
10479#define B_CP_REG_RT_CPD_MODE_INIT 0x0 9169#define B_CP_REG_RT_CPD_MODE_INIT 0x0
10480 9170
10481
10482#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 9171#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039
10483#define B_CP_REG_RT_CPD_RELIABLE__W 3 9172#define B_CP_REG_RT_CPD_RELIABLE__W 3
10484#define B_CP_REG_RT_CPD_RELIABLE__M 0x7 9173#define B_CP_REG_RT_CPD_RELIABLE__M 0x7
10485#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 9174#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0
10486 9175
10487
10488#define B_CP_REG_RT_CPD_BIN__A 0x141003A 9176#define B_CP_REG_RT_CPD_BIN__A 0x141003A
10489#define B_CP_REG_RT_CPD_BIN__W 5 9177#define B_CP_REG_RT_CPD_BIN__W 5
10490#define B_CP_REG_RT_CPD_BIN__M 0x1F 9178#define B_CP_REG_RT_CPD_BIN__M 0x1F
10491#define B_CP_REG_RT_CPD_BIN_INIT 0x0 9179#define B_CP_REG_RT_CPD_BIN_INIT 0x0
10492 9180
10493
10494#define B_CP_REG_RT_CPD_MAX__A 0x141003B 9181#define B_CP_REG_RT_CPD_MAX__A 0x141003B
10495#define B_CP_REG_RT_CPD_MAX__W 4 9182#define B_CP_REG_RT_CPD_MAX__W 4
10496#define B_CP_REG_RT_CPD_MAX__M 0xF 9183#define B_CP_REG_RT_CPD_MAX__M 0xF
10497#define B_CP_REG_RT_CPD_MAX_INIT 0x0 9184#define B_CP_REG_RT_CPD_MAX_INIT 0x0
10498 9185
10499
10500#define B_CP_REG_RT_SUPR_VAL__A 0x141003C 9186#define B_CP_REG_RT_SUPR_VAL__A 0x141003C
10501#define B_CP_REG_RT_SUPR_VAL__W 2 9187#define B_CP_REG_RT_SUPR_VAL__W 2
10502#define B_CP_REG_RT_SUPR_VAL__M 0x3 9188#define B_CP_REG_RT_SUPR_VAL__M 0x3
@@ -10510,61 +9196,51 @@ extern "C" {
10510#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 9196#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2
10511#define B_CP_REG_RT_SUPR_VAL_INIT 0x0 9197#define B_CP_REG_RT_SUPR_VAL_INIT 0x0
10512 9198
10513
10514#define B_CP_REG_RT_EXP_AVE__A 0x141003D 9199#define B_CP_REG_RT_EXP_AVE__A 0x141003D
10515#define B_CP_REG_RT_EXP_AVE__W 5 9200#define B_CP_REG_RT_EXP_AVE__W 5
10516#define B_CP_REG_RT_EXP_AVE__M 0x1F 9201#define B_CP_REG_RT_EXP_AVE__M 0x1F
10517#define B_CP_REG_RT_EXP_AVE_INIT 0x0 9202#define B_CP_REG_RT_EXP_AVE_INIT 0x0
10518 9203
10519
10520#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E 9204#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E
10521#define B_CP_REG_RT_CPD_EXP_MARG__W 5 9205#define B_CP_REG_RT_CPD_EXP_MARG__W 5
10522#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F 9206#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F
10523#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 9207#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3
10524 9208
10525
10526#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 9209#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040
10527#define B_CP_REG_AC_NEXP_OFFS__W 8 9210#define B_CP_REG_AC_NEXP_OFFS__W 8
10528#define B_CP_REG_AC_NEXP_OFFS__M 0xFF 9211#define B_CP_REG_AC_NEXP_OFFS__M 0xFF
10529#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 9212#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0
10530 9213
10531
10532#define B_CP_REG_AC_AVER_POW__A 0x1410041 9214#define B_CP_REG_AC_AVER_POW__A 0x1410041
10533#define B_CP_REG_AC_AVER_POW__W 8 9215#define B_CP_REG_AC_AVER_POW__W 8
10534#define B_CP_REG_AC_AVER_POW__M 0xFF 9216#define B_CP_REG_AC_AVER_POW__M 0xFF
10535#define B_CP_REG_AC_AVER_POW_INIT 0x5F 9217#define B_CP_REG_AC_AVER_POW_INIT 0x5F
10536 9218
10537
10538#define B_CP_REG_AC_MAX_POW__A 0x1410042 9219#define B_CP_REG_AC_MAX_POW__A 0x1410042
10539#define B_CP_REG_AC_MAX_POW__W 8 9220#define B_CP_REG_AC_MAX_POW__W 8
10540#define B_CP_REG_AC_MAX_POW__M 0xFF 9221#define B_CP_REG_AC_MAX_POW__M 0xFF
10541#define B_CP_REG_AC_MAX_POW_INIT 0x7A 9222#define B_CP_REG_AC_MAX_POW_INIT 0x7A
10542 9223
10543
10544#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 9224#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043
10545#define B_CP_REG_AC_WEIGHT_MAN__W 6 9225#define B_CP_REG_AC_WEIGHT_MAN__W 6
10546#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F 9226#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F
10547#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 9227#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31
10548 9228
10549
10550#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 9229#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044
10551#define B_CP_REG_AC_WEIGHT_EXP__W 5 9230#define B_CP_REG_AC_WEIGHT_EXP__W 5
10552#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F 9231#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F
10553#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 9232#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10
10554 9233
10555
10556#define B_CP_REG_AC_GAIN_MAN__A 0x1410045 9234#define B_CP_REG_AC_GAIN_MAN__A 0x1410045
10557#define B_CP_REG_AC_GAIN_MAN__W 16 9235#define B_CP_REG_AC_GAIN_MAN__W 16
10558#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF 9236#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF
10559#define B_CP_REG_AC_GAIN_MAN_INIT 0x0 9237#define B_CP_REG_AC_GAIN_MAN_INIT 0x0
10560 9238
10561
10562#define B_CP_REG_AC_GAIN_EXP__A 0x1410046 9239#define B_CP_REG_AC_GAIN_EXP__A 0x1410046
10563#define B_CP_REG_AC_GAIN_EXP__W 5 9240#define B_CP_REG_AC_GAIN_EXP__W 5
10564#define B_CP_REG_AC_GAIN_EXP__M 0x1F 9241#define B_CP_REG_AC_GAIN_EXP__M 0x1F
10565#define B_CP_REG_AC_GAIN_EXP_INIT 0x0 9242#define B_CP_REG_AC_GAIN_EXP_INIT 0x0
10566 9243
10567
10568#define B_CP_REG_AC_AMP_MODE__A 0x1410047 9244#define B_CP_REG_AC_AMP_MODE__A 0x1410047
10569#define B_CP_REG_AC_AMP_MODE__W 2 9245#define B_CP_REG_AC_AMP_MODE__W 2
10570#define B_CP_REG_AC_AMP_MODE__M 0x3 9246#define B_CP_REG_AC_AMP_MODE__M 0x3
@@ -10573,19 +9249,16 @@ extern "C" {
10573#define B_CP_REG_AC_AMP_MODE_FIXED 0x2 9249#define B_CP_REG_AC_AMP_MODE_FIXED 0x2
10574#define B_CP_REG_AC_AMP_MODE_INIT 0x2 9250#define B_CP_REG_AC_AMP_MODE_INIT 0x2
10575 9251
10576
10577#define B_CP_REG_AC_AMP_FIX__A 0x1410048 9252#define B_CP_REG_AC_AMP_FIX__A 0x1410048
10578#define B_CP_REG_AC_AMP_FIX__W 14 9253#define B_CP_REG_AC_AMP_FIX__W 14
10579#define B_CP_REG_AC_AMP_FIX__M 0x3FFF 9254#define B_CP_REG_AC_AMP_FIX__M 0x3FFF
10580#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF 9255#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF
10581 9256
10582
10583#define B_CP_REG_AC_AMP_READ__A 0x1410049 9257#define B_CP_REG_AC_AMP_READ__A 0x1410049
10584#define B_CP_REG_AC_AMP_READ__W 14 9258#define B_CP_REG_AC_AMP_READ__W 14
10585#define B_CP_REG_AC_AMP_READ__M 0x3FFF 9259#define B_CP_REG_AC_AMP_READ__M 0x3FFF
10586#define B_CP_REG_AC_AMP_READ_INIT 0x0 9260#define B_CP_REG_AC_AMP_READ_INIT 0x0
10587 9261
10588
10589#define B_CP_REG_AC_ANG_MODE__A 0x141004A 9262#define B_CP_REG_AC_ANG_MODE__A 0x141004A
10590#define B_CP_REG_AC_ANG_MODE__W 2 9263#define B_CP_REG_AC_ANG_MODE__W 2
10591#define B_CP_REG_AC_ANG_MODE__M 0x3 9264#define B_CP_REG_AC_ANG_MODE__M 0x3
@@ -10595,49 +9268,41 @@ extern "C" {
10595#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 9268#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3
10596#define B_CP_REG_AC_ANG_MODE_INIT 0x3 9269#define B_CP_REG_AC_ANG_MODE_INIT 0x3
10597 9270
10598
10599#define B_CP_REG_AC_ANG_OFFS__A 0x141004B 9271#define B_CP_REG_AC_ANG_OFFS__A 0x141004B
10600#define B_CP_REG_AC_ANG_OFFS__W 14 9272#define B_CP_REG_AC_ANG_OFFS__W 14
10601#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF 9273#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF
10602#define B_CP_REG_AC_ANG_OFFS_INIT 0x0 9274#define B_CP_REG_AC_ANG_OFFS_INIT 0x0
10603 9275
10604
10605#define B_CP_REG_AC_ANG_READ__A 0x141004C 9276#define B_CP_REG_AC_ANG_READ__A 0x141004C
10606#define B_CP_REG_AC_ANG_READ__W 16 9277#define B_CP_REG_AC_ANG_READ__W 16
10607#define B_CP_REG_AC_ANG_READ__M 0xFFFF 9278#define B_CP_REG_AC_ANG_READ__M 0xFFFF
10608#define B_CP_REG_AC_ANG_READ_INIT 0x0 9279#define B_CP_REG_AC_ANG_READ_INIT 0x0
10609 9280
10610
10611#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 9281#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060
10612#define B_CP_REG_AC_ACCU_REAL0__W 8 9282#define B_CP_REG_AC_ACCU_REAL0__W 8
10613#define B_CP_REG_AC_ACCU_REAL0__M 0xFF 9283#define B_CP_REG_AC_ACCU_REAL0__M 0xFF
10614#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 9284#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0
10615 9285
10616
10617#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 9286#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061
10618#define B_CP_REG_AC_ACCU_IMAG0__W 8 9287#define B_CP_REG_AC_ACCU_IMAG0__W 8
10619#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF 9288#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF
10620#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 9289#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0
10621 9290
10622
10623#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 9291#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062
10624#define B_CP_REG_AC_ACCU_REAL1__W 8 9292#define B_CP_REG_AC_ACCU_REAL1__W 8
10625#define B_CP_REG_AC_ACCU_REAL1__M 0xFF 9293#define B_CP_REG_AC_ACCU_REAL1__M 0xFF
10626#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 9294#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0
10627 9295
10628
10629#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 9296#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063
10630#define B_CP_REG_AC_ACCU_IMAG1__W 8 9297#define B_CP_REG_AC_ACCU_IMAG1__W 8
10631#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF 9298#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF
10632#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 9299#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0
10633 9300
10634
10635#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 9301#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050
10636#define B_CP_REG_DL_MB_WR_ADDR__W 15 9302#define B_CP_REG_DL_MB_WR_ADDR__W 15
10637#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF 9303#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF
10638#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 9304#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0
10639 9305
10640
10641#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 9306#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051
10642#define B_CP_REG_DL_MB_WR_CTR__W 5 9307#define B_CP_REG_DL_MB_WR_CTR__W 5
10643#define B_CP_REG_DL_MB_WR_CTR__M 0x1F 9308#define B_CP_REG_DL_MB_WR_CTR__M 0x1F
@@ -10655,13 +9320,11 @@ extern "C" {
10655#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 9320#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1
10656#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 9321#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0
10657 9322
10658
10659#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 9323#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052
10660#define B_CP_REG_DL_MB_RD_ADDR__W 15 9324#define B_CP_REG_DL_MB_RD_ADDR__W 15
10661#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF 9325#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF
10662#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 9326#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0
10663 9327
10664
10665#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 9328#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053
10666#define B_CP_REG_DL_MB_RD_CTR__W 11 9329#define B_CP_REG_DL_MB_RD_CTR__W 11
10667#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF 9330#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF
@@ -10691,36 +9354,18 @@ extern "C" {
10691#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 9354#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1
10692#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 9355#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0
10693 9356
10694
10695
10696#define B_CP_BR_BUF_RAM__A 0x1420000 9357#define B_CP_BR_BUF_RAM__A 0x1420000
10697 9358
10698
10699
10700#define B_CP_BR_CPL_RAM__A 0x1430000 9359#define B_CP_BR_CPL_RAM__A 0x1430000
10701 9360
10702
10703
10704#define B_CP_PB_DL0_RAM__A 0x1440000 9361#define B_CP_PB_DL0_RAM__A 0x1440000
10705 9362
10706
10707
10708#define B_CP_PB_DL1_RAM__A 0x1450000 9363#define B_CP_PB_DL1_RAM__A 0x1450000
10709 9364
10710
10711
10712#define B_CP_PB_DL2_RAM__A 0x1460000 9365#define B_CP_PB_DL2_RAM__A 0x1460000
10713 9366
10714
10715
10716
10717
10718#define B_CE_SID 0xA 9367#define B_CE_SID 0xA
10719 9368
10720
10721
10722
10723
10724#define B_CE_COMM_EXEC__A 0x1800000 9369#define B_CE_COMM_EXEC__A 0x1800000
10725#define B_CE_COMM_EXEC__W 3 9370#define B_CE_COMM_EXEC__W 3
10726#define B_CE_COMM_EXEC__M 0x7 9371#define B_CE_COMM_EXEC__M 0x7
@@ -10753,11 +9398,6 @@ extern "C" {
10753#define B_CE_COMM_INT_MSK__W 16 9398#define B_CE_COMM_INT_MSK__W 16
10754#define B_CE_COMM_INT_MSK__M 0xFFFF 9399#define B_CE_COMM_INT_MSK__M 0xFFFF
10755 9400
10756
10757
10758
10759
10760
10761#define B_CE_REG_COMM_EXEC__A 0x1810000 9401#define B_CE_REG_COMM_EXEC__A 0x1810000
10762#define B_CE_REG_COMM_EXEC__W 3 9402#define B_CE_REG_COMM_EXEC__W 3
10763#define B_CE_REG_COMM_EXEC__M 0x7 9403#define B_CE_REG_COMM_EXEC__M 0x7
@@ -10769,7 +9409,6 @@ extern "C" {
10769#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 9409#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2
10770#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 9410#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3
10771 9411
10772
10773#define B_CE_REG_COMM_MB__A 0x1810002 9412#define B_CE_REG_COMM_MB__A 0x1810002
10774#define B_CE_REG_COMM_MB__W 4 9413#define B_CE_REG_COMM_MB__W 4
10775#define B_CE_REG_COMM_MB__M 0xF 9414#define B_CE_REG_COMM_MB__M 0xF
@@ -10815,7 +9454,6 @@ extern "C" {
10815#define B_CE_REG_COMM_INT_STA_CE_FI__W 1 9454#define B_CE_REG_COMM_INT_STA_CE_FI__W 1
10816#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 9455#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4
10817 9456
10818
10819#define B_CE_REG_COMM_INT_MSK__A 0x1810008 9457#define B_CE_REG_COMM_INT_MSK__A 0x1810008
10820#define B_CE_REG_COMM_INT_MSK__W 3 9458#define B_CE_REG_COMM_INT_MSK__W 3
10821#define B_CE_REG_COMM_INT_MSK__M 0x7 9459#define B_CE_REG_COMM_INT_MSK__M 0x7
@@ -10829,19 +9467,15 @@ extern "C" {
10829#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 9467#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1
10830#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 9468#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4
10831 9469
10832
10833#define B_CE_REG_2K__A 0x1810010 9470#define B_CE_REG_2K__A 0x1810010
10834#define B_CE_REG_2K__W 1 9471#define B_CE_REG_2K__W 1
10835#define B_CE_REG_2K__M 0x1 9472#define B_CE_REG_2K__M 0x1
10836#define B_CE_REG_2K_INIT 0x0 9473#define B_CE_REG_2K_INIT 0x0
10837 9474
10838
10839#define B_CE_REG_TAPSET__A 0x1810011 9475#define B_CE_REG_TAPSET__A 0x1810011
10840#define B_CE_REG_TAPSET__W 4 9476#define B_CE_REG_TAPSET__W 4
10841#define B_CE_REG_TAPSET__M 0xF 9477#define B_CE_REG_TAPSET__M 0xF
10842 9478
10843
10844
10845#define B_CE_REG_TAPSET_MOTION_INIT 0x0 9479#define B_CE_REG_TAPSET_MOTION_INIT 0x0
10846 9480
10847#define B_CE_REG_TAPSET_MOTION_NO 0x0 9481#define B_CE_REG_TAPSET_MOTION_NO 0x0
@@ -10854,43 +9488,36 @@ extern "C" {
10854 9488
10855#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 9489#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8
10856 9490
10857
10858#define B_CE_REG_AVG_POW__A 0x1810012 9491#define B_CE_REG_AVG_POW__A 0x1810012
10859#define B_CE_REG_AVG_POW__W 8 9492#define B_CE_REG_AVG_POW__W 8
10860#define B_CE_REG_AVG_POW__M 0xFF 9493#define B_CE_REG_AVG_POW__M 0xFF
10861#define B_CE_REG_AVG_POW_INIT 0x0 9494#define B_CE_REG_AVG_POW_INIT 0x0
10862 9495
10863
10864#define B_CE_REG_MAX_POW__A 0x1810013 9496#define B_CE_REG_MAX_POW__A 0x1810013
10865#define B_CE_REG_MAX_POW__W 8 9497#define B_CE_REG_MAX_POW__W 8
10866#define B_CE_REG_MAX_POW__M 0xFF 9498#define B_CE_REG_MAX_POW__M 0xFF
10867#define B_CE_REG_MAX_POW_INIT 0x0 9499#define B_CE_REG_MAX_POW_INIT 0x0
10868 9500
10869
10870#define B_CE_REG_ATT__A 0x1810014 9501#define B_CE_REG_ATT__A 0x1810014
10871#define B_CE_REG_ATT__W 8 9502#define B_CE_REG_ATT__W 8
10872#define B_CE_REG_ATT__M 0xFF 9503#define B_CE_REG_ATT__M 0xFF
10873#define B_CE_REG_ATT_INIT 0x0 9504#define B_CE_REG_ATT_INIT 0x0
10874 9505
10875
10876#define B_CE_REG_NRED__A 0x1810015 9506#define B_CE_REG_NRED__A 0x1810015
10877#define B_CE_REG_NRED__W 6 9507#define B_CE_REG_NRED__W 6
10878#define B_CE_REG_NRED__M 0x3F 9508#define B_CE_REG_NRED__M 0x3F
10879#define B_CE_REG_NRED_INIT 0x0 9509#define B_CE_REG_NRED_INIT 0x0
10880 9510
10881
10882#define B_CE_REG_PU_SIGN__A 0x1810020 9511#define B_CE_REG_PU_SIGN__A 0x1810020
10883#define B_CE_REG_PU_SIGN__W 1 9512#define B_CE_REG_PU_SIGN__W 1
10884#define B_CE_REG_PU_SIGN__M 0x1 9513#define B_CE_REG_PU_SIGN__M 0x1
10885#define B_CE_REG_PU_SIGN_INIT 0x0 9514#define B_CE_REG_PU_SIGN_INIT 0x0
10886 9515
10887
10888#define B_CE_REG_PU_MIX__A 0x1810021 9516#define B_CE_REG_PU_MIX__A 0x1810021
10889#define B_CE_REG_PU_MIX__W 1 9517#define B_CE_REG_PU_MIX__W 1
10890#define B_CE_REG_PU_MIX__M 0x1 9518#define B_CE_REG_PU_MIX__M 0x1
10891#define B_CE_REG_PU_MIX_INIT 0x0 9519#define B_CE_REG_PU_MIX_INIT 0x0
10892 9520
10893
10894#define B_CE_REG_PB_PILOT_REQ__A 0x1810030 9521#define B_CE_REG_PB_PILOT_REQ__A 0x1810030
10895#define B_CE_REG_PB_PILOT_REQ__W 15 9522#define B_CE_REG_PB_PILOT_REQ__W 15
10896#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF 9523#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF
@@ -10902,49 +9529,41 @@ extern "C" {
10902#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 9529#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12
10903#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF 9530#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF
10904 9531
10905
10906#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 9532#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031
10907#define B_CE_REG_PB_PILOT_REQ_VALID__W 1 9533#define B_CE_REG_PB_PILOT_REQ_VALID__W 1
10908#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 9534#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1
10909#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 9535#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0
10910 9536
10911
10912#define B_CE_REG_PB_FREEZE__A 0x1810032 9537#define B_CE_REG_PB_FREEZE__A 0x1810032
10913#define B_CE_REG_PB_FREEZE__W 1 9538#define B_CE_REG_PB_FREEZE__W 1
10914#define B_CE_REG_PB_FREEZE__M 0x1 9539#define B_CE_REG_PB_FREEZE__M 0x1
10915#define B_CE_REG_PB_FREEZE_INIT 0x0 9540#define B_CE_REG_PB_FREEZE_INIT 0x0
10916 9541
10917
10918#define B_CE_REG_PB_PILOT_EXP__A 0x1810038 9542#define B_CE_REG_PB_PILOT_EXP__A 0x1810038
10919#define B_CE_REG_PB_PILOT_EXP__W 4 9543#define B_CE_REG_PB_PILOT_EXP__W 4
10920#define B_CE_REG_PB_PILOT_EXP__M 0xF 9544#define B_CE_REG_PB_PILOT_EXP__M 0xF
10921#define B_CE_REG_PB_PILOT_EXP_INIT 0x0 9545#define B_CE_REG_PB_PILOT_EXP_INIT 0x0
10922 9546
10923
10924#define B_CE_REG_PB_PILOT_REAL__A 0x1810039 9547#define B_CE_REG_PB_PILOT_REAL__A 0x1810039
10925#define B_CE_REG_PB_PILOT_REAL__W 10 9548#define B_CE_REG_PB_PILOT_REAL__W 10
10926#define B_CE_REG_PB_PILOT_REAL__M 0x3FF 9549#define B_CE_REG_PB_PILOT_REAL__M 0x3FF
10927#define B_CE_REG_PB_PILOT_REAL_INIT 0x0 9550#define B_CE_REG_PB_PILOT_REAL_INIT 0x0
10928 9551
10929
10930#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A 9552#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A
10931#define B_CE_REG_PB_PILOT_IMAG__W 10 9553#define B_CE_REG_PB_PILOT_IMAG__W 10
10932#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF 9554#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF
10933#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 9555#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0
10934 9556
10935
10936#define B_CE_REG_PB_SMBNR__A 0x181003B 9557#define B_CE_REG_PB_SMBNR__A 0x181003B
10937#define B_CE_REG_PB_SMBNR__W 5 9558#define B_CE_REG_PB_SMBNR__W 5
10938#define B_CE_REG_PB_SMBNR__M 0x1F 9559#define B_CE_REG_PB_SMBNR__M 0x1F
10939#define B_CE_REG_PB_SMBNR_INIT 0x0 9560#define B_CE_REG_PB_SMBNR_INIT 0x0
10940 9561
10941
10942#define B_CE_REG_NE_PILOT_REQ__A 0x1810040 9562#define B_CE_REG_NE_PILOT_REQ__A 0x1810040
10943#define B_CE_REG_NE_PILOT_REQ__W 12 9563#define B_CE_REG_NE_PILOT_REQ__W 12
10944#define B_CE_REG_NE_PILOT_REQ__M 0xFFF 9564#define B_CE_REG_NE_PILOT_REQ__M 0xFFF
10945#define B_CE_REG_NE_PILOT_REQ_INIT 0x0 9565#define B_CE_REG_NE_PILOT_REQ_INIT 0x0
10946 9566
10947
10948#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 9567#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041
10949#define B_CE_REG_NE_PILOT_REQ_VALID__W 2 9568#define B_CE_REG_NE_PILOT_REQ_VALID__W 2
10950#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 9569#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3
@@ -10956,13 +9575,11 @@ extern "C" {
10956#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 9575#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1
10957#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 9576#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1
10958 9577
10959
10960#define B_CE_REG_NE_PILOT_DATA__A 0x1810042 9578#define B_CE_REG_NE_PILOT_DATA__A 0x1810042
10961#define B_CE_REG_NE_PILOT_DATA__W 10 9579#define B_CE_REG_NE_PILOT_DATA__W 10
10962#define B_CE_REG_NE_PILOT_DATA__M 0x3FF 9580#define B_CE_REG_NE_PILOT_DATA__M 0x3FF
10963#define B_CE_REG_NE_PILOT_DATA_INIT 0x0 9581#define B_CE_REG_NE_PILOT_DATA_INIT 0x0
10964 9582
10965
10966#define B_CE_REG_NE_ERR_SELECT__A 0x1810043 9583#define B_CE_REG_NE_ERR_SELECT__A 0x1810043
10967#define B_CE_REG_NE_ERR_SELECT__W 5 9584#define B_CE_REG_NE_ERR_SELECT__W 5
10968#define B_CE_REG_NE_ERR_SELECT__M 0x1F 9585#define B_CE_REG_NE_ERR_SELECT__M 0x1F
@@ -10988,31 +9605,26 @@ extern "C" {
10988#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 9605#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1
10989#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 9606#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1
10990 9607
10991
10992#define B_CE_REG_NE_TD_CAL__A 0x1810044 9608#define B_CE_REG_NE_TD_CAL__A 0x1810044
10993#define B_CE_REG_NE_TD_CAL__W 9 9609#define B_CE_REG_NE_TD_CAL__W 9
10994#define B_CE_REG_NE_TD_CAL__M 0x1FF 9610#define B_CE_REG_NE_TD_CAL__M 0x1FF
10995#define B_CE_REG_NE_TD_CAL_INIT 0x1E8 9611#define B_CE_REG_NE_TD_CAL_INIT 0x1E8
10996 9612
10997
10998#define B_CE_REG_NE_FD_CAL__A 0x1810045 9613#define B_CE_REG_NE_FD_CAL__A 0x1810045
10999#define B_CE_REG_NE_FD_CAL__W 9 9614#define B_CE_REG_NE_FD_CAL__W 9
11000#define B_CE_REG_NE_FD_CAL__M 0x1FF 9615#define B_CE_REG_NE_FD_CAL__M 0x1FF
11001#define B_CE_REG_NE_FD_CAL_INIT 0x1D9 9616#define B_CE_REG_NE_FD_CAL_INIT 0x1D9
11002 9617
11003
11004#define B_CE_REG_NE_MIXAVG__A 0x1810046 9618#define B_CE_REG_NE_MIXAVG__A 0x1810046
11005#define B_CE_REG_NE_MIXAVG__W 3 9619#define B_CE_REG_NE_MIXAVG__W 3
11006#define B_CE_REG_NE_MIXAVG__M 0x7 9620#define B_CE_REG_NE_MIXAVG__M 0x7
11007#define B_CE_REG_NE_MIXAVG_INIT 0x6 9621#define B_CE_REG_NE_MIXAVG_INIT 0x6
11008 9622
11009
11010#define B_CE_REG_NE_NUPD_OFS__A 0x1810047 9623#define B_CE_REG_NE_NUPD_OFS__A 0x1810047
11011#define B_CE_REG_NE_NUPD_OFS__W 4 9624#define B_CE_REG_NE_NUPD_OFS__W 4
11012#define B_CE_REG_NE_NUPD_OFS__M 0xF 9625#define B_CE_REG_NE_NUPD_OFS__M 0xF
11013#define B_CE_REG_NE_NUPD_OFS_INIT 0x4 9626#define B_CE_REG_NE_NUPD_OFS_INIT 0x4
11014 9627
11015
11016#define B_CE_REG_NE_TD_POW__A 0x1810048 9628#define B_CE_REG_NE_TD_POW__A 0x1810048
11017#define B_CE_REG_NE_TD_POW__W 15 9629#define B_CE_REG_NE_TD_POW__W 15
11018#define B_CE_REG_NE_TD_POW__M 0x7FFF 9630#define B_CE_REG_NE_TD_POW__M 0x7FFF
@@ -11026,7 +9638,6 @@ extern "C" {
11026#define B_CE_REG_NE_TD_POW_MANTISSA__W 10 9638#define B_CE_REG_NE_TD_POW_MANTISSA__W 10
11027#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF 9639#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF
11028 9640
11029
11030#define B_CE_REG_NE_FD_POW__A 0x1810049 9641#define B_CE_REG_NE_FD_POW__A 0x1810049
11031#define B_CE_REG_NE_FD_POW__W 15 9642#define B_CE_REG_NE_FD_POW__W 15
11032#define B_CE_REG_NE_FD_POW__M 0x7FFF 9643#define B_CE_REG_NE_FD_POW__M 0x7FFF
@@ -11040,103 +9651,86 @@ extern "C" {
11040#define B_CE_REG_NE_FD_POW_MANTISSA__W 10 9651#define B_CE_REG_NE_FD_POW_MANTISSA__W 10
11041#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF 9652#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF
11042 9653
11043
11044#define B_CE_REG_NE_NEXP_AVG__A 0x181004A 9654#define B_CE_REG_NE_NEXP_AVG__A 0x181004A
11045#define B_CE_REG_NE_NEXP_AVG__W 8 9655#define B_CE_REG_NE_NEXP_AVG__W 8
11046#define B_CE_REG_NE_NEXP_AVG__M 0xFF 9656#define B_CE_REG_NE_NEXP_AVG__M 0xFF
11047#define B_CE_REG_NE_NEXP_AVG_INIT 0x0 9657#define B_CE_REG_NE_NEXP_AVG_INIT 0x0
11048 9658
11049
11050#define B_CE_REG_NE_OFFSET__A 0x181004B 9659#define B_CE_REG_NE_OFFSET__A 0x181004B
11051#define B_CE_REG_NE_OFFSET__W 9 9660#define B_CE_REG_NE_OFFSET__W 9
11052#define B_CE_REG_NE_OFFSET__M 0x1FF 9661#define B_CE_REG_NE_OFFSET__M 0x1FF
11053#define B_CE_REG_NE_OFFSET_INIT 0x0 9662#define B_CE_REG_NE_OFFSET_INIT 0x0
11054 9663
11055
11056#define B_CE_REG_NE_NUPD_TRH__A 0x181004C 9664#define B_CE_REG_NE_NUPD_TRH__A 0x181004C
11057#define B_CE_REG_NE_NUPD_TRH__W 5 9665#define B_CE_REG_NE_NUPD_TRH__W 5
11058#define B_CE_REG_NE_NUPD_TRH__M 0x1F 9666#define B_CE_REG_NE_NUPD_TRH__M 0x1F
11059#define B_CE_REG_NE_NUPD_TRH_INIT 0x14 9667#define B_CE_REG_NE_NUPD_TRH_INIT 0x14
11060 9668
11061
11062#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 9669#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050
11063#define B_CE_REG_PE_NEXP_OFFS__W 8 9670#define B_CE_REG_PE_NEXP_OFFS__W 8
11064#define B_CE_REG_PE_NEXP_OFFS__M 0xFF 9671#define B_CE_REG_PE_NEXP_OFFS__M 0xFF
11065#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 9672#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0
11066 9673
11067
11068#define B_CE_REG_PE_TIMESHIFT__A 0x1810051 9674#define B_CE_REG_PE_TIMESHIFT__A 0x1810051
11069#define B_CE_REG_PE_TIMESHIFT__W 14 9675#define B_CE_REG_PE_TIMESHIFT__W 14
11070#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF 9676#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF
11071#define B_CE_REG_PE_TIMESHIFT_INIT 0x0 9677#define B_CE_REG_PE_TIMESHIFT_INIT 0x0
11072 9678
11073
11074#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 9679#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052
11075#define B_CE_REG_PE_DIF_REAL_L__W 16 9680#define B_CE_REG_PE_DIF_REAL_L__W 16
11076#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF 9681#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF
11077#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 9682#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0
11078 9683
11079
11080#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 9684#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053
11081#define B_CE_REG_PE_DIF_IMAG_L__W 16 9685#define B_CE_REG_PE_DIF_IMAG_L__W 16
11082#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF 9686#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF
11083#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 9687#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0
11084 9688
11085
11086#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 9689#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054
11087#define B_CE_REG_PE_DIF_REAL_R__W 16 9690#define B_CE_REG_PE_DIF_REAL_R__W 16
11088#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF 9691#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF
11089#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 9692#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0
11090 9693
11091
11092#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 9694#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055
11093#define B_CE_REG_PE_DIF_IMAG_R__W 16 9695#define B_CE_REG_PE_DIF_IMAG_R__W 16
11094#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF 9696#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF
11095#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 9697#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0
11096 9698
11097
11098#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 9699#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056
11099#define B_CE_REG_PE_ABS_REAL_L__W 16 9700#define B_CE_REG_PE_ABS_REAL_L__W 16
11100#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF 9701#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF
11101#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 9702#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0
11102 9703
11103
11104#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 9704#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057
11105#define B_CE_REG_PE_ABS_IMAG_L__W 16 9705#define B_CE_REG_PE_ABS_IMAG_L__W 16
11106#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF 9706#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF
11107#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 9707#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0
11108 9708
11109
11110#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 9709#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058
11111#define B_CE_REG_PE_ABS_REAL_R__W 16 9710#define B_CE_REG_PE_ABS_REAL_R__W 16
11112#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF 9711#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF
11113#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 9712#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0
11114 9713
11115
11116#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 9714#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059
11117#define B_CE_REG_PE_ABS_IMAG_R__W 16 9715#define B_CE_REG_PE_ABS_IMAG_R__W 16
11118#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF 9716#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF
11119#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 9717#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0
11120 9718
11121
11122#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A 9719#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A
11123#define B_CE_REG_PE_ABS_EXP_L__W 5 9720#define B_CE_REG_PE_ABS_EXP_L__W 5
11124#define B_CE_REG_PE_ABS_EXP_L__M 0x1F 9721#define B_CE_REG_PE_ABS_EXP_L__M 0x1F
11125#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 9722#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0
11126 9723
11127
11128#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B 9724#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B
11129#define B_CE_REG_PE_ABS_EXP_R__W 5 9725#define B_CE_REG_PE_ABS_EXP_R__W 5
11130#define B_CE_REG_PE_ABS_EXP_R__M 0x1F 9726#define B_CE_REG_PE_ABS_EXP_R__M 0x1F
11131#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 9727#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0
11132 9728
11133
11134#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 9729#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060
11135#define B_CE_REG_TP_UPDATE_MODE__W 1 9730#define B_CE_REG_TP_UPDATE_MODE__W 1
11136#define B_CE_REG_TP_UPDATE_MODE__M 0x1 9731#define B_CE_REG_TP_UPDATE_MODE__M 0x1
11137#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 9732#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0
11138 9733
11139
11140#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 9734#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061
11141#define B_CE_REG_TP_LMS_TAP_ON__W 1 9735#define B_CE_REG_TP_LMS_TAP_ON__W 1
11142#define B_CE_REG_TP_LMS_TAP_ON__M 0x1 9736#define B_CE_REG_TP_LMS_TAP_ON__M 0x1
@@ -11186,7 +9780,6 @@ extern "C" {
11186#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 9780#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10
11187#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF 9781#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF
11188 9782
11189
11190#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D 9783#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D
11191#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 9784#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15
11192#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF 9785#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF
@@ -11200,7 +9793,6 @@ extern "C" {
11200#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 9793#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10
11201#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF 9794#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF
11202 9795
11203
11204#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E 9796#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E
11205#define B_CE_REG_TP_A0_TAP_ENERGY__W 15 9797#define B_CE_REG_TP_A0_TAP_ENERGY__W 15
11206#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF 9798#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF
@@ -11214,7 +9806,6 @@ extern "C" {
11214#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 9806#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10
11215#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF 9807#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF
11216 9808
11217
11218#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F 9809#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F
11219#define B_CE_REG_TP_A1_TAP_ENERGY__W 15 9810#define B_CE_REG_TP_A1_TAP_ENERGY__W 15
11220#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF 9811#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF
@@ -11228,147 +9819,121 @@ extern "C" {
11228#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 9819#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10
11229#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF 9820#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF
11230 9821
11231
11232#define B_CE_REG_TI_SYM_CNT__A 0x1810072 9822#define B_CE_REG_TI_SYM_CNT__A 0x1810072
11233#define B_CE_REG_TI_SYM_CNT__W 6 9823#define B_CE_REG_TI_SYM_CNT__W 6
11234#define B_CE_REG_TI_SYM_CNT__M 0x3F 9824#define B_CE_REG_TI_SYM_CNT__M 0x3F
11235#define B_CE_REG_TI_SYM_CNT_INIT 0x0 9825#define B_CE_REG_TI_SYM_CNT_INIT 0x0
11236 9826
11237
11238#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 9827#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073
11239#define B_CE_REG_TI_PHN_ENABLE__W 1 9828#define B_CE_REG_TI_PHN_ENABLE__W 1
11240#define B_CE_REG_TI_PHN_ENABLE__M 0x1 9829#define B_CE_REG_TI_PHN_ENABLE__M 0x1
11241#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 9830#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0
11242 9831
11243
11244#define B_CE_REG_TI_SHIFT__A 0x1810074 9832#define B_CE_REG_TI_SHIFT__A 0x1810074
11245#define B_CE_REG_TI_SHIFT__W 2 9833#define B_CE_REG_TI_SHIFT__W 2
11246#define B_CE_REG_TI_SHIFT__M 0x3 9834#define B_CE_REG_TI_SHIFT__M 0x3
11247#define B_CE_REG_TI_SHIFT_INIT 0x0 9835#define B_CE_REG_TI_SHIFT_INIT 0x0
11248 9836
11249
11250#define B_CE_REG_TI_SLOW__A 0x1810075 9837#define B_CE_REG_TI_SLOW__A 0x1810075
11251#define B_CE_REG_TI_SLOW__W 1 9838#define B_CE_REG_TI_SLOW__W 1
11252#define B_CE_REG_TI_SLOW__M 0x1 9839#define B_CE_REG_TI_SLOW__M 0x1
11253#define B_CE_REG_TI_SLOW_INIT 0x0 9840#define B_CE_REG_TI_SLOW_INIT 0x0
11254 9841
11255
11256#define B_CE_REG_TI_MGAIN__A 0x1810076 9842#define B_CE_REG_TI_MGAIN__A 0x1810076
11257#define B_CE_REG_TI_MGAIN__W 8 9843#define B_CE_REG_TI_MGAIN__W 8
11258#define B_CE_REG_TI_MGAIN__M 0xFF 9844#define B_CE_REG_TI_MGAIN__M 0xFF
11259#define B_CE_REG_TI_MGAIN_INIT 0x0 9845#define B_CE_REG_TI_MGAIN_INIT 0x0
11260 9846
11261
11262#define B_CE_REG_TI_ACCU1__A 0x1810077 9847#define B_CE_REG_TI_ACCU1__A 0x1810077
11263#define B_CE_REG_TI_ACCU1__W 8 9848#define B_CE_REG_TI_ACCU1__W 8
11264#define B_CE_REG_TI_ACCU1__M 0xFF 9849#define B_CE_REG_TI_ACCU1__M 0xFF
11265#define B_CE_REG_TI_ACCU1_INIT 0x0 9850#define B_CE_REG_TI_ACCU1_INIT 0x0
11266 9851
11267
11268#define B_CE_REG_NI_PER_LEFT__A 0x18100B0 9852#define B_CE_REG_NI_PER_LEFT__A 0x18100B0
11269#define B_CE_REG_NI_PER_LEFT__W 5 9853#define B_CE_REG_NI_PER_LEFT__W 5
11270#define B_CE_REG_NI_PER_LEFT__M 0x1F 9854#define B_CE_REG_NI_PER_LEFT__M 0x1F
11271#define B_CE_REG_NI_PER_LEFT_INIT 0xE 9855#define B_CE_REG_NI_PER_LEFT_INIT 0xE
11272 9856
11273
11274#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 9857#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1
11275#define B_CE_REG_NI_PER_RIGHT__W 5 9858#define B_CE_REG_NI_PER_RIGHT__W 5
11276#define B_CE_REG_NI_PER_RIGHT__M 0x1F 9859#define B_CE_REG_NI_PER_RIGHT__M 0x1F
11277#define B_CE_REG_NI_PER_RIGHT_INIT 0x7 9860#define B_CE_REG_NI_PER_RIGHT_INIT 0x7
11278 9861
11279
11280#define B_CE_REG_NI_POS_LR__A 0x18100B2 9862#define B_CE_REG_NI_POS_LR__A 0x18100B2
11281#define B_CE_REG_NI_POS_LR__W 9 9863#define B_CE_REG_NI_POS_LR__W 9
11282#define B_CE_REG_NI_POS_LR__M 0x1FF 9864#define B_CE_REG_NI_POS_LR__M 0x1FF
11283#define B_CE_REG_NI_POS_LR_INIT 0xA0 9865#define B_CE_REG_NI_POS_LR_INIT 0xA0
11284 9866
11285
11286#define B_CE_REG_FI_SHT_INCR__A 0x1810090 9867#define B_CE_REG_FI_SHT_INCR__A 0x1810090
11287#define B_CE_REG_FI_SHT_INCR__W 7 9868#define B_CE_REG_FI_SHT_INCR__W 7
11288#define B_CE_REG_FI_SHT_INCR__M 0x7F 9869#define B_CE_REG_FI_SHT_INCR__M 0x7F
11289#define B_CE_REG_FI_SHT_INCR_INIT 0x9 9870#define B_CE_REG_FI_SHT_INCR_INIT 0x9
11290 9871
11291
11292#define B_CE_REG_FI_EXP_NORM__A 0x1810091 9872#define B_CE_REG_FI_EXP_NORM__A 0x1810091
11293#define B_CE_REG_FI_EXP_NORM__W 4 9873#define B_CE_REG_FI_EXP_NORM__W 4
11294#define B_CE_REG_FI_EXP_NORM__M 0xF 9874#define B_CE_REG_FI_EXP_NORM__M 0xF
11295#define B_CE_REG_FI_EXP_NORM_INIT 0x4 9875#define B_CE_REG_FI_EXP_NORM_INIT 0x4
11296 9876
11297
11298#define B_CE_REG_FI_SUPR_VAL__A 0x1810092 9877#define B_CE_REG_FI_SUPR_VAL__A 0x1810092
11299#define B_CE_REG_FI_SUPR_VAL__W 1 9878#define B_CE_REG_FI_SUPR_VAL__W 1
11300#define B_CE_REG_FI_SUPR_VAL__M 0x1 9879#define B_CE_REG_FI_SUPR_VAL__M 0x1
11301#define B_CE_REG_FI_SUPR_VAL_INIT 0x1 9880#define B_CE_REG_FI_SUPR_VAL_INIT 0x1
11302 9881
11303
11304#define B_CE_REG_IR_INPUTSEL__A 0x18100A0 9882#define B_CE_REG_IR_INPUTSEL__A 0x18100A0
11305#define B_CE_REG_IR_INPUTSEL__W 1 9883#define B_CE_REG_IR_INPUTSEL__W 1
11306#define B_CE_REG_IR_INPUTSEL__M 0x1 9884#define B_CE_REG_IR_INPUTSEL__M 0x1
11307#define B_CE_REG_IR_INPUTSEL_INIT 0x0 9885#define B_CE_REG_IR_INPUTSEL_INIT 0x0
11308 9886
11309
11310#define B_CE_REG_IR_STARTPOS__A 0x18100A1 9887#define B_CE_REG_IR_STARTPOS__A 0x18100A1
11311#define B_CE_REG_IR_STARTPOS__W 8 9888#define B_CE_REG_IR_STARTPOS__W 8
11312#define B_CE_REG_IR_STARTPOS__M 0xFF 9889#define B_CE_REG_IR_STARTPOS__M 0xFF
11313#define B_CE_REG_IR_STARTPOS_INIT 0x0 9890#define B_CE_REG_IR_STARTPOS_INIT 0x0
11314 9891
11315
11316#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 9892#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2
11317#define B_CE_REG_IR_NEXP_THRES__W 8 9893#define B_CE_REG_IR_NEXP_THRES__W 8
11318#define B_CE_REG_IR_NEXP_THRES__M 0xFF 9894#define B_CE_REG_IR_NEXP_THRES__M 0xFF
11319#define B_CE_REG_IR_NEXP_THRES_INIT 0x0 9895#define B_CE_REG_IR_NEXP_THRES_INIT 0x0
11320 9896
11321
11322#define B_CE_REG_IR_LENGTH__A 0x18100A3 9897#define B_CE_REG_IR_LENGTH__A 0x18100A3
11323#define B_CE_REG_IR_LENGTH__W 4 9898#define B_CE_REG_IR_LENGTH__W 4
11324#define B_CE_REG_IR_LENGTH__M 0xF 9899#define B_CE_REG_IR_LENGTH__M 0xF
11325#define B_CE_REG_IR_LENGTH_INIT 0x0 9900#define B_CE_REG_IR_LENGTH_INIT 0x0
11326 9901
11327
11328#define B_CE_REG_IR_FREQ__A 0x18100A4 9902#define B_CE_REG_IR_FREQ__A 0x18100A4
11329#define B_CE_REG_IR_FREQ__W 11 9903#define B_CE_REG_IR_FREQ__W 11
11330#define B_CE_REG_IR_FREQ__M 0x7FF 9904#define B_CE_REG_IR_FREQ__M 0x7FF
11331#define B_CE_REG_IR_FREQ_INIT 0x0 9905#define B_CE_REG_IR_FREQ_INIT 0x0
11332 9906
11333
11334#define B_CE_REG_IR_FREQINC__A 0x18100A5 9907#define B_CE_REG_IR_FREQINC__A 0x18100A5
11335#define B_CE_REG_IR_FREQINC__W 11 9908#define B_CE_REG_IR_FREQINC__W 11
11336#define B_CE_REG_IR_FREQINC__M 0x7FF 9909#define B_CE_REG_IR_FREQINC__M 0x7FF
11337#define B_CE_REG_IR_FREQINC_INIT 0x0 9910#define B_CE_REG_IR_FREQINC_INIT 0x0
11338 9911
11339
11340#define B_CE_REG_IR_KAISINC__A 0x18100A6 9912#define B_CE_REG_IR_KAISINC__A 0x18100A6
11341#define B_CE_REG_IR_KAISINC__W 15 9913#define B_CE_REG_IR_KAISINC__W 15
11342#define B_CE_REG_IR_KAISINC__M 0x7FFF 9914#define B_CE_REG_IR_KAISINC__M 0x7FFF
11343#define B_CE_REG_IR_KAISINC_INIT 0x0 9915#define B_CE_REG_IR_KAISINC_INIT 0x0
11344 9916
11345
11346#define B_CE_REG_IR_CTL__A 0x18100A7 9917#define B_CE_REG_IR_CTL__A 0x18100A7
11347#define B_CE_REG_IR_CTL__W 3 9918#define B_CE_REG_IR_CTL__W 3
11348#define B_CE_REG_IR_CTL__M 0x7 9919#define B_CE_REG_IR_CTL__M 0x7
11349#define B_CE_REG_IR_CTL_INIT 0x0 9920#define B_CE_REG_IR_CTL_INIT 0x0
11350 9921
11351
11352#define B_CE_REG_IR_REAL__A 0x18100A8 9922#define B_CE_REG_IR_REAL__A 0x18100A8
11353#define B_CE_REG_IR_REAL__W 16 9923#define B_CE_REG_IR_REAL__W 16
11354#define B_CE_REG_IR_REAL__M 0xFFFF 9924#define B_CE_REG_IR_REAL__M 0xFFFF
11355#define B_CE_REG_IR_REAL_INIT 0x0 9925#define B_CE_REG_IR_REAL_INIT 0x0
11356 9926
11357
11358#define B_CE_REG_IR_IMAG__A 0x18100A9 9927#define B_CE_REG_IR_IMAG__A 0x18100A9
11359#define B_CE_REG_IR_IMAG__W 16 9928#define B_CE_REG_IR_IMAG__W 16
11360#define B_CE_REG_IR_IMAG__M 0xFFFF 9929#define B_CE_REG_IR_IMAG__M 0xFFFF
11361#define B_CE_REG_IR_IMAG_INIT 0x0 9930#define B_CE_REG_IR_IMAG_INIT 0x0
11362 9931
11363
11364#define B_CE_REG_IR_INDEX__A 0x18100AA 9932#define B_CE_REG_IR_INDEX__A 0x18100AA
11365#define B_CE_REG_IR_INDEX__W 12 9933#define B_CE_REG_IR_INDEX__W 12
11366#define B_CE_REG_IR_INDEX__M 0xFFF 9934#define B_CE_REG_IR_INDEX__M 0xFFF
11367#define B_CE_REG_IR_INDEX_INIT 0x0 9935#define B_CE_REG_IR_INDEX_INIT 0x0
11368 9936
11369
11370
11371
11372#define B_CE_REG_FR_COMM_EXEC__A 0x1820000 9937#define B_CE_REG_FR_COMM_EXEC__A 0x1820000
11373#define B_CE_REG_FR_COMM_EXEC__W 1 9938#define B_CE_REG_FR_COMM_EXEC__W 1
11374#define B_CE_REG_FR_COMM_EXEC__M 0x1 9939#define B_CE_REG_FR_COMM_EXEC__M 0x1
@@ -11378,295 +9943,246 @@ extern "C" {
11378#define B_CE_REG_FR_TREAL00__M 0x7FF 9943#define B_CE_REG_FR_TREAL00__M 0x7FF
11379#define B_CE_REG_FR_TREAL00_INIT 0x52 9944#define B_CE_REG_FR_TREAL00_INIT 0x52
11380 9945
11381
11382#define B_CE_REG_FR_TIMAG00__A 0x1820011 9946#define B_CE_REG_FR_TIMAG00__A 0x1820011
11383#define B_CE_REG_FR_TIMAG00__W 11 9947#define B_CE_REG_FR_TIMAG00__W 11
11384#define B_CE_REG_FR_TIMAG00__M 0x7FF 9948#define B_CE_REG_FR_TIMAG00__M 0x7FF
11385#define B_CE_REG_FR_TIMAG00_INIT 0x0 9949#define B_CE_REG_FR_TIMAG00_INIT 0x0
11386 9950
11387
11388#define B_CE_REG_FR_TREAL01__A 0x1820012 9951#define B_CE_REG_FR_TREAL01__A 0x1820012
11389#define B_CE_REG_FR_TREAL01__W 11 9952#define B_CE_REG_FR_TREAL01__W 11
11390#define B_CE_REG_FR_TREAL01__M 0x7FF 9953#define B_CE_REG_FR_TREAL01__M 0x7FF
11391#define B_CE_REG_FR_TREAL01_INIT 0x52 9954#define B_CE_REG_FR_TREAL01_INIT 0x52
11392 9955
11393
11394#define B_CE_REG_FR_TIMAG01__A 0x1820013 9956#define B_CE_REG_FR_TIMAG01__A 0x1820013
11395#define B_CE_REG_FR_TIMAG01__W 11 9957#define B_CE_REG_FR_TIMAG01__W 11
11396#define B_CE_REG_FR_TIMAG01__M 0x7FF 9958#define B_CE_REG_FR_TIMAG01__M 0x7FF
11397#define B_CE_REG_FR_TIMAG01_INIT 0x0 9959#define B_CE_REG_FR_TIMAG01_INIT 0x0
11398 9960
11399
11400#define B_CE_REG_FR_TREAL02__A 0x1820014 9961#define B_CE_REG_FR_TREAL02__A 0x1820014
11401#define B_CE_REG_FR_TREAL02__W 11 9962#define B_CE_REG_FR_TREAL02__W 11
11402#define B_CE_REG_FR_TREAL02__M 0x7FF 9963#define B_CE_REG_FR_TREAL02__M 0x7FF
11403#define B_CE_REG_FR_TREAL02_INIT 0x52 9964#define B_CE_REG_FR_TREAL02_INIT 0x52
11404 9965
11405
11406#define B_CE_REG_FR_TIMAG02__A 0x1820015 9966#define B_CE_REG_FR_TIMAG02__A 0x1820015
11407#define B_CE_REG_FR_TIMAG02__W 11 9967#define B_CE_REG_FR_TIMAG02__W 11
11408#define B_CE_REG_FR_TIMAG02__M 0x7FF 9968#define B_CE_REG_FR_TIMAG02__M 0x7FF
11409#define B_CE_REG_FR_TIMAG02_INIT 0x0 9969#define B_CE_REG_FR_TIMAG02_INIT 0x0
11410 9970
11411
11412#define B_CE_REG_FR_TREAL03__A 0x1820016 9971#define B_CE_REG_FR_TREAL03__A 0x1820016
11413#define B_CE_REG_FR_TREAL03__W 11 9972#define B_CE_REG_FR_TREAL03__W 11
11414#define B_CE_REG_FR_TREAL03__M 0x7FF 9973#define B_CE_REG_FR_TREAL03__M 0x7FF
11415#define B_CE_REG_FR_TREAL03_INIT 0x52 9974#define B_CE_REG_FR_TREAL03_INIT 0x52
11416 9975
11417
11418#define B_CE_REG_FR_TIMAG03__A 0x1820017 9976#define B_CE_REG_FR_TIMAG03__A 0x1820017
11419#define B_CE_REG_FR_TIMAG03__W 11 9977#define B_CE_REG_FR_TIMAG03__W 11
11420#define B_CE_REG_FR_TIMAG03__M 0x7FF 9978#define B_CE_REG_FR_TIMAG03__M 0x7FF
11421#define B_CE_REG_FR_TIMAG03_INIT 0x0 9979#define B_CE_REG_FR_TIMAG03_INIT 0x0
11422 9980
11423
11424#define B_CE_REG_FR_TREAL04__A 0x1820018 9981#define B_CE_REG_FR_TREAL04__A 0x1820018
11425#define B_CE_REG_FR_TREAL04__W 11 9982#define B_CE_REG_FR_TREAL04__W 11
11426#define B_CE_REG_FR_TREAL04__M 0x7FF 9983#define B_CE_REG_FR_TREAL04__M 0x7FF
11427#define B_CE_REG_FR_TREAL04_INIT 0x52 9984#define B_CE_REG_FR_TREAL04_INIT 0x52
11428 9985
11429
11430#define B_CE_REG_FR_TIMAG04__A 0x1820019 9986#define B_CE_REG_FR_TIMAG04__A 0x1820019
11431#define B_CE_REG_FR_TIMAG04__W 11 9987#define B_CE_REG_FR_TIMAG04__W 11
11432#define B_CE_REG_FR_TIMAG04__M 0x7FF 9988#define B_CE_REG_FR_TIMAG04__M 0x7FF
11433#define B_CE_REG_FR_TIMAG04_INIT 0x0 9989#define B_CE_REG_FR_TIMAG04_INIT 0x0
11434 9990
11435
11436#define B_CE_REG_FR_TREAL05__A 0x182001A 9991#define B_CE_REG_FR_TREAL05__A 0x182001A
11437#define B_CE_REG_FR_TREAL05__W 11 9992#define B_CE_REG_FR_TREAL05__W 11
11438#define B_CE_REG_FR_TREAL05__M 0x7FF 9993#define B_CE_REG_FR_TREAL05__M 0x7FF
11439#define B_CE_REG_FR_TREAL05_INIT 0x52 9994#define B_CE_REG_FR_TREAL05_INIT 0x52
11440 9995
11441
11442#define B_CE_REG_FR_TIMAG05__A 0x182001B 9996#define B_CE_REG_FR_TIMAG05__A 0x182001B
11443#define B_CE_REG_FR_TIMAG05__W 11 9997#define B_CE_REG_FR_TIMAG05__W 11
11444#define B_CE_REG_FR_TIMAG05__M 0x7FF 9998#define B_CE_REG_FR_TIMAG05__M 0x7FF
11445#define B_CE_REG_FR_TIMAG05_INIT 0x0 9999#define B_CE_REG_FR_TIMAG05_INIT 0x0
11446 10000
11447
11448#define B_CE_REG_FR_TREAL06__A 0x182001C 10001#define B_CE_REG_FR_TREAL06__A 0x182001C
11449#define B_CE_REG_FR_TREAL06__W 11 10002#define B_CE_REG_FR_TREAL06__W 11
11450#define B_CE_REG_FR_TREAL06__M 0x7FF 10003#define B_CE_REG_FR_TREAL06__M 0x7FF
11451#define B_CE_REG_FR_TREAL06_INIT 0x52 10004#define B_CE_REG_FR_TREAL06_INIT 0x52
11452 10005
11453
11454#define B_CE_REG_FR_TIMAG06__A 0x182001D 10006#define B_CE_REG_FR_TIMAG06__A 0x182001D
11455#define B_CE_REG_FR_TIMAG06__W 11 10007#define B_CE_REG_FR_TIMAG06__W 11
11456#define B_CE_REG_FR_TIMAG06__M 0x7FF 10008#define B_CE_REG_FR_TIMAG06__M 0x7FF
11457#define B_CE_REG_FR_TIMAG06_INIT 0x0 10009#define B_CE_REG_FR_TIMAG06_INIT 0x0
11458 10010
11459
11460#define B_CE_REG_FR_TREAL07__A 0x182001E 10011#define B_CE_REG_FR_TREAL07__A 0x182001E
11461#define B_CE_REG_FR_TREAL07__W 11 10012#define B_CE_REG_FR_TREAL07__W 11
11462#define B_CE_REG_FR_TREAL07__M 0x7FF 10013#define B_CE_REG_FR_TREAL07__M 0x7FF
11463#define B_CE_REG_FR_TREAL07_INIT 0x52 10014#define B_CE_REG_FR_TREAL07_INIT 0x52
11464 10015
11465
11466#define B_CE_REG_FR_TIMAG07__A 0x182001F 10016#define B_CE_REG_FR_TIMAG07__A 0x182001F
11467#define B_CE_REG_FR_TIMAG07__W 11 10017#define B_CE_REG_FR_TIMAG07__W 11
11468#define B_CE_REG_FR_TIMAG07__M 0x7FF 10018#define B_CE_REG_FR_TIMAG07__M 0x7FF
11469#define B_CE_REG_FR_TIMAG07_INIT 0x0 10019#define B_CE_REG_FR_TIMAG07_INIT 0x0
11470 10020
11471
11472#define B_CE_REG_FR_TREAL08__A 0x1820020 10021#define B_CE_REG_FR_TREAL08__A 0x1820020
11473#define B_CE_REG_FR_TREAL08__W 11 10022#define B_CE_REG_FR_TREAL08__W 11
11474#define B_CE_REG_FR_TREAL08__M 0x7FF 10023#define B_CE_REG_FR_TREAL08__M 0x7FF
11475#define B_CE_REG_FR_TREAL08_INIT 0x52 10024#define B_CE_REG_FR_TREAL08_INIT 0x52
11476 10025
11477
11478#define B_CE_REG_FR_TIMAG08__A 0x1820021 10026#define B_CE_REG_FR_TIMAG08__A 0x1820021
11479#define B_CE_REG_FR_TIMAG08__W 11 10027#define B_CE_REG_FR_TIMAG08__W 11
11480#define B_CE_REG_FR_TIMAG08__M 0x7FF 10028#define B_CE_REG_FR_TIMAG08__M 0x7FF
11481#define B_CE_REG_FR_TIMAG08_INIT 0x0 10029#define B_CE_REG_FR_TIMAG08_INIT 0x0
11482 10030
11483
11484#define B_CE_REG_FR_TREAL09__A 0x1820022 10031#define B_CE_REG_FR_TREAL09__A 0x1820022
11485#define B_CE_REG_FR_TREAL09__W 11 10032#define B_CE_REG_FR_TREAL09__W 11
11486#define B_CE_REG_FR_TREAL09__M 0x7FF 10033#define B_CE_REG_FR_TREAL09__M 0x7FF
11487#define B_CE_REG_FR_TREAL09_INIT 0x52 10034#define B_CE_REG_FR_TREAL09_INIT 0x52
11488 10035
11489
11490#define B_CE_REG_FR_TIMAG09__A 0x1820023 10036#define B_CE_REG_FR_TIMAG09__A 0x1820023
11491#define B_CE_REG_FR_TIMAG09__W 11 10037#define B_CE_REG_FR_TIMAG09__W 11
11492#define B_CE_REG_FR_TIMAG09__M 0x7FF 10038#define B_CE_REG_FR_TIMAG09__M 0x7FF
11493#define B_CE_REG_FR_TIMAG09_INIT 0x0 10039#define B_CE_REG_FR_TIMAG09_INIT 0x0
11494 10040
11495
11496#define B_CE_REG_FR_TREAL10__A 0x1820024 10041#define B_CE_REG_FR_TREAL10__A 0x1820024
11497#define B_CE_REG_FR_TREAL10__W 11 10042#define B_CE_REG_FR_TREAL10__W 11
11498#define B_CE_REG_FR_TREAL10__M 0x7FF 10043#define B_CE_REG_FR_TREAL10__M 0x7FF
11499#define B_CE_REG_FR_TREAL10_INIT 0x52 10044#define B_CE_REG_FR_TREAL10_INIT 0x52
11500 10045
11501
11502#define B_CE_REG_FR_TIMAG10__A 0x1820025 10046#define B_CE_REG_FR_TIMAG10__A 0x1820025
11503#define B_CE_REG_FR_TIMAG10__W 11 10047#define B_CE_REG_FR_TIMAG10__W 11
11504#define B_CE_REG_FR_TIMAG10__M 0x7FF 10048#define B_CE_REG_FR_TIMAG10__M 0x7FF
11505#define B_CE_REG_FR_TIMAG10_INIT 0x0 10049#define B_CE_REG_FR_TIMAG10_INIT 0x0
11506 10050
11507
11508#define B_CE_REG_FR_TREAL11__A 0x1820026 10051#define B_CE_REG_FR_TREAL11__A 0x1820026
11509#define B_CE_REG_FR_TREAL11__W 11 10052#define B_CE_REG_FR_TREAL11__W 11
11510#define B_CE_REG_FR_TREAL11__M 0x7FF 10053#define B_CE_REG_FR_TREAL11__M 0x7FF
11511#define B_CE_REG_FR_TREAL11_INIT 0x52 10054#define B_CE_REG_FR_TREAL11_INIT 0x52
11512 10055
11513
11514#define B_CE_REG_FR_TIMAG11__A 0x1820027 10056#define B_CE_REG_FR_TIMAG11__A 0x1820027
11515#define B_CE_REG_FR_TIMAG11__W 11 10057#define B_CE_REG_FR_TIMAG11__W 11
11516#define B_CE_REG_FR_TIMAG11__M 0x7FF 10058#define B_CE_REG_FR_TIMAG11__M 0x7FF
11517#define B_CE_REG_FR_TIMAG11_INIT 0x0 10059#define B_CE_REG_FR_TIMAG11_INIT 0x0
11518 10060
11519
11520#define B_CE_REG_FR_MID_TAP__A 0x1820028 10061#define B_CE_REG_FR_MID_TAP__A 0x1820028
11521#define B_CE_REG_FR_MID_TAP__W 11 10062#define B_CE_REG_FR_MID_TAP__W 11
11522#define B_CE_REG_FR_MID_TAP__M 0x7FF 10063#define B_CE_REG_FR_MID_TAP__M 0x7FF
11523#define B_CE_REG_FR_MID_TAP_INIT 0x51 10064#define B_CE_REG_FR_MID_TAP_INIT 0x51
11524 10065
11525
11526#define B_CE_REG_FR_SQS_G00__A 0x1820029 10066#define B_CE_REG_FR_SQS_G00__A 0x1820029
11527#define B_CE_REG_FR_SQS_G00__W 8 10067#define B_CE_REG_FR_SQS_G00__W 8
11528#define B_CE_REG_FR_SQS_G00__M 0xFF 10068#define B_CE_REG_FR_SQS_G00__M 0xFF
11529#define B_CE_REG_FR_SQS_G00_INIT 0xB 10069#define B_CE_REG_FR_SQS_G00_INIT 0xB
11530 10070
11531
11532#define B_CE_REG_FR_SQS_G01__A 0x182002A 10071#define B_CE_REG_FR_SQS_G01__A 0x182002A
11533#define B_CE_REG_FR_SQS_G01__W 8 10072#define B_CE_REG_FR_SQS_G01__W 8
11534#define B_CE_REG_FR_SQS_G01__M 0xFF 10073#define B_CE_REG_FR_SQS_G01__M 0xFF
11535#define B_CE_REG_FR_SQS_G01_INIT 0xB 10074#define B_CE_REG_FR_SQS_G01_INIT 0xB
11536 10075
11537
11538#define B_CE_REG_FR_SQS_G02__A 0x182002B 10076#define B_CE_REG_FR_SQS_G02__A 0x182002B
11539#define B_CE_REG_FR_SQS_G02__W 8 10077#define B_CE_REG_FR_SQS_G02__W 8
11540#define B_CE_REG_FR_SQS_G02__M 0xFF 10078#define B_CE_REG_FR_SQS_G02__M 0xFF
11541#define B_CE_REG_FR_SQS_G02_INIT 0xB 10079#define B_CE_REG_FR_SQS_G02_INIT 0xB
11542 10080
11543
11544#define B_CE_REG_FR_SQS_G03__A 0x182002C 10081#define B_CE_REG_FR_SQS_G03__A 0x182002C
11545#define B_CE_REG_FR_SQS_G03__W 8 10082#define B_CE_REG_FR_SQS_G03__W 8
11546#define B_CE_REG_FR_SQS_G03__M 0xFF 10083#define B_CE_REG_FR_SQS_G03__M 0xFF
11547#define B_CE_REG_FR_SQS_G03_INIT 0xB 10084#define B_CE_REG_FR_SQS_G03_INIT 0xB
11548 10085
11549
11550#define B_CE_REG_FR_SQS_G04__A 0x182002D 10086#define B_CE_REG_FR_SQS_G04__A 0x182002D
11551#define B_CE_REG_FR_SQS_G04__W 8 10087#define B_CE_REG_FR_SQS_G04__W 8
11552#define B_CE_REG_FR_SQS_G04__M 0xFF 10088#define B_CE_REG_FR_SQS_G04__M 0xFF
11553#define B_CE_REG_FR_SQS_G04_INIT 0xB 10089#define B_CE_REG_FR_SQS_G04_INIT 0xB
11554 10090
11555
11556#define B_CE_REG_FR_SQS_G05__A 0x182002E 10091#define B_CE_REG_FR_SQS_G05__A 0x182002E
11557#define B_CE_REG_FR_SQS_G05__W 8 10092#define B_CE_REG_FR_SQS_G05__W 8
11558#define B_CE_REG_FR_SQS_G05__M 0xFF 10093#define B_CE_REG_FR_SQS_G05__M 0xFF
11559#define B_CE_REG_FR_SQS_G05_INIT 0xB 10094#define B_CE_REG_FR_SQS_G05_INIT 0xB
11560 10095
11561
11562#define B_CE_REG_FR_SQS_G06__A 0x182002F 10096#define B_CE_REG_FR_SQS_G06__A 0x182002F
11563#define B_CE_REG_FR_SQS_G06__W 8 10097#define B_CE_REG_FR_SQS_G06__W 8
11564#define B_CE_REG_FR_SQS_G06__M 0xFF 10098#define B_CE_REG_FR_SQS_G06__M 0xFF
11565#define B_CE_REG_FR_SQS_G06_INIT 0xB 10099#define B_CE_REG_FR_SQS_G06_INIT 0xB
11566 10100
11567
11568#define B_CE_REG_FR_SQS_G07__A 0x1820030 10101#define B_CE_REG_FR_SQS_G07__A 0x1820030
11569#define B_CE_REG_FR_SQS_G07__W 8 10102#define B_CE_REG_FR_SQS_G07__W 8
11570#define B_CE_REG_FR_SQS_G07__M 0xFF 10103#define B_CE_REG_FR_SQS_G07__M 0xFF
11571#define B_CE_REG_FR_SQS_G07_INIT 0xB 10104#define B_CE_REG_FR_SQS_G07_INIT 0xB
11572 10105
11573
11574#define B_CE_REG_FR_SQS_G08__A 0x1820031 10106#define B_CE_REG_FR_SQS_G08__A 0x1820031
11575#define B_CE_REG_FR_SQS_G08__W 8 10107#define B_CE_REG_FR_SQS_G08__W 8
11576#define B_CE_REG_FR_SQS_G08__M 0xFF 10108#define B_CE_REG_FR_SQS_G08__M 0xFF
11577#define B_CE_REG_FR_SQS_G08_INIT 0xB 10109#define B_CE_REG_FR_SQS_G08_INIT 0xB
11578 10110
11579
11580#define B_CE_REG_FR_SQS_G09__A 0x1820032 10111#define B_CE_REG_FR_SQS_G09__A 0x1820032
11581#define B_CE_REG_FR_SQS_G09__W 8 10112#define B_CE_REG_FR_SQS_G09__W 8
11582#define B_CE_REG_FR_SQS_G09__M 0xFF 10113#define B_CE_REG_FR_SQS_G09__M 0xFF
11583#define B_CE_REG_FR_SQS_G09_INIT 0xB 10114#define B_CE_REG_FR_SQS_G09_INIT 0xB
11584 10115
11585
11586#define B_CE_REG_FR_SQS_G10__A 0x1820033 10116#define B_CE_REG_FR_SQS_G10__A 0x1820033
11587#define B_CE_REG_FR_SQS_G10__W 8 10117#define B_CE_REG_FR_SQS_G10__W 8
11588#define B_CE_REG_FR_SQS_G10__M 0xFF 10118#define B_CE_REG_FR_SQS_G10__M 0xFF
11589#define B_CE_REG_FR_SQS_G10_INIT 0xB 10119#define B_CE_REG_FR_SQS_G10_INIT 0xB
11590 10120
11591
11592#define B_CE_REG_FR_SQS_G11__A 0x1820034 10121#define B_CE_REG_FR_SQS_G11__A 0x1820034
11593#define B_CE_REG_FR_SQS_G11__W 8 10122#define B_CE_REG_FR_SQS_G11__W 8
11594#define B_CE_REG_FR_SQS_G11__M 0xFF 10123#define B_CE_REG_FR_SQS_G11__M 0xFF
11595#define B_CE_REG_FR_SQS_G11_INIT 0xB 10124#define B_CE_REG_FR_SQS_G11_INIT 0xB
11596 10125
11597
11598#define B_CE_REG_FR_SQS_G12__A 0x1820035 10126#define B_CE_REG_FR_SQS_G12__A 0x1820035
11599#define B_CE_REG_FR_SQS_G12__W 8 10127#define B_CE_REG_FR_SQS_G12__W 8
11600#define B_CE_REG_FR_SQS_G12__M 0xFF 10128#define B_CE_REG_FR_SQS_G12__M 0xFF
11601#define B_CE_REG_FR_SQS_G12_INIT 0x5 10129#define B_CE_REG_FR_SQS_G12_INIT 0x5
11602 10130
11603
11604#define B_CE_REG_FR_RIO_G00__A 0x1820036 10131#define B_CE_REG_FR_RIO_G00__A 0x1820036
11605#define B_CE_REG_FR_RIO_G00__W 9 10132#define B_CE_REG_FR_RIO_G00__W 9
11606#define B_CE_REG_FR_RIO_G00__M 0x1FF 10133#define B_CE_REG_FR_RIO_G00__M 0x1FF
11607#define B_CE_REG_FR_RIO_G00_INIT 0x1FF 10134#define B_CE_REG_FR_RIO_G00_INIT 0x1FF
11608 10135
11609
11610#define B_CE_REG_FR_RIO_G01__A 0x1820037 10136#define B_CE_REG_FR_RIO_G01__A 0x1820037
11611#define B_CE_REG_FR_RIO_G01__W 9 10137#define B_CE_REG_FR_RIO_G01__W 9
11612#define B_CE_REG_FR_RIO_G01__M 0x1FF 10138#define B_CE_REG_FR_RIO_G01__M 0x1FF
11613#define B_CE_REG_FR_RIO_G01_INIT 0x190 10139#define B_CE_REG_FR_RIO_G01_INIT 0x190
11614 10140
11615
11616#define B_CE_REG_FR_RIO_G02__A 0x1820038 10141#define B_CE_REG_FR_RIO_G02__A 0x1820038
11617#define B_CE_REG_FR_RIO_G02__W 9 10142#define B_CE_REG_FR_RIO_G02__W 9
11618#define B_CE_REG_FR_RIO_G02__M 0x1FF 10143#define B_CE_REG_FR_RIO_G02__M 0x1FF
11619#define B_CE_REG_FR_RIO_G02_INIT 0x10B 10144#define B_CE_REG_FR_RIO_G02_INIT 0x10B
11620 10145
11621
11622#define B_CE_REG_FR_RIO_G03__A 0x1820039 10146#define B_CE_REG_FR_RIO_G03__A 0x1820039
11623#define B_CE_REG_FR_RIO_G03__W 9 10147#define B_CE_REG_FR_RIO_G03__W 9
11624#define B_CE_REG_FR_RIO_G03__M 0x1FF 10148#define B_CE_REG_FR_RIO_G03__M 0x1FF
11625#define B_CE_REG_FR_RIO_G03_INIT 0xC8 10149#define B_CE_REG_FR_RIO_G03_INIT 0xC8
11626 10150
11627
11628#define B_CE_REG_FR_RIO_G04__A 0x182003A 10151#define B_CE_REG_FR_RIO_G04__A 0x182003A
11629#define B_CE_REG_FR_RIO_G04__W 9 10152#define B_CE_REG_FR_RIO_G04__W 9
11630#define B_CE_REG_FR_RIO_G04__M 0x1FF 10153#define B_CE_REG_FR_RIO_G04__M 0x1FF
11631#define B_CE_REG_FR_RIO_G04_INIT 0xA0 10154#define B_CE_REG_FR_RIO_G04_INIT 0xA0
11632 10155
11633
11634#define B_CE_REG_FR_RIO_G05__A 0x182003B 10156#define B_CE_REG_FR_RIO_G05__A 0x182003B
11635#define B_CE_REG_FR_RIO_G05__W 9 10157#define B_CE_REG_FR_RIO_G05__W 9
11636#define B_CE_REG_FR_RIO_G05__M 0x1FF 10158#define B_CE_REG_FR_RIO_G05__M 0x1FF
11637#define B_CE_REG_FR_RIO_G05_INIT 0x85 10159#define B_CE_REG_FR_RIO_G05_INIT 0x85
11638 10160
11639
11640#define B_CE_REG_FR_RIO_G06__A 0x182003C 10161#define B_CE_REG_FR_RIO_G06__A 0x182003C
11641#define B_CE_REG_FR_RIO_G06__W 9 10162#define B_CE_REG_FR_RIO_G06__W 9
11642#define B_CE_REG_FR_RIO_G06__M 0x1FF 10163#define B_CE_REG_FR_RIO_G06__M 0x1FF
11643#define B_CE_REG_FR_RIO_G06_INIT 0x72 10164#define B_CE_REG_FR_RIO_G06_INIT 0x72
11644 10165
11645
11646#define B_CE_REG_FR_RIO_G07__A 0x182003D 10166#define B_CE_REG_FR_RIO_G07__A 0x182003D
11647#define B_CE_REG_FR_RIO_G07__W 9 10167#define B_CE_REG_FR_RIO_G07__W 9
11648#define B_CE_REG_FR_RIO_G07__M 0x1FF 10168#define B_CE_REG_FR_RIO_G07__M 0x1FF
11649#define B_CE_REG_FR_RIO_G07_INIT 0x64 10169#define B_CE_REG_FR_RIO_G07_INIT 0x64
11650 10170
11651
11652#define B_CE_REG_FR_RIO_G08__A 0x182003E 10171#define B_CE_REG_FR_RIO_G08__A 0x182003E
11653#define B_CE_REG_FR_RIO_G08__W 9 10172#define B_CE_REG_FR_RIO_G08__W 9
11654#define B_CE_REG_FR_RIO_G08__M 0x1FF 10173#define B_CE_REG_FR_RIO_G08__M 0x1FF
11655#define B_CE_REG_FR_RIO_G08_INIT 0x59 10174#define B_CE_REG_FR_RIO_G08_INIT 0x59
11656 10175
11657
11658#define B_CE_REG_FR_RIO_G09__A 0x182003F 10176#define B_CE_REG_FR_RIO_G09__A 0x182003F
11659#define B_CE_REG_FR_RIO_G09__W 9 10177#define B_CE_REG_FR_RIO_G09__W 9
11660#define B_CE_REG_FR_RIO_G09__M 0x1FF 10178#define B_CE_REG_FR_RIO_G09__M 0x1FF
11661#define B_CE_REG_FR_RIO_G09_INIT 0x50 10179#define B_CE_REG_FR_RIO_G09_INIT 0x50
11662 10180
11663
11664#define B_CE_REG_FR_RIO_G10__A 0x1820040 10181#define B_CE_REG_FR_RIO_G10__A 0x1820040
11665#define B_CE_REG_FR_RIO_G10__W 9 10182#define B_CE_REG_FR_RIO_G10__W 9
11666#define B_CE_REG_FR_RIO_G10__M 0x1FF 10183#define B_CE_REG_FR_RIO_G10__M 0x1FF
11667#define B_CE_REG_FR_RIO_G10_INIT 0x49 10184#define B_CE_REG_FR_RIO_G10_INIT 0x49
11668 10185
11669
11670#define B_CE_REG_FR_MODE__A 0x1820041 10186#define B_CE_REG_FR_MODE__A 0x1820041
11671#define B_CE_REG_FR_MODE__W 9 10187#define B_CE_REG_FR_MODE__W 9
11672#define B_CE_REG_FR_MODE__M 0x1FF 10188#define B_CE_REG_FR_MODE__M 0x1FF
@@ -11708,19 +10224,16 @@ extern "C" {
11708#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 10224#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100
11709#define B_CE_REG_FR_MODE_INIT 0xDE 10225#define B_CE_REG_FR_MODE_INIT 0xDE
11710 10226
11711
11712#define B_CE_REG_FR_SQS_TRH__A 0x1820042 10227#define B_CE_REG_FR_SQS_TRH__A 0x1820042
11713#define B_CE_REG_FR_SQS_TRH__W 8 10228#define B_CE_REG_FR_SQS_TRH__W 8
11714#define B_CE_REG_FR_SQS_TRH__M 0xFF 10229#define B_CE_REG_FR_SQS_TRH__M 0xFF
11715#define B_CE_REG_FR_SQS_TRH_INIT 0x80 10230#define B_CE_REG_FR_SQS_TRH_INIT 0x80
11716 10231
11717
11718#define B_CE_REG_FR_RIO_GAIN__A 0x1820043 10232#define B_CE_REG_FR_RIO_GAIN__A 0x1820043
11719#define B_CE_REG_FR_RIO_GAIN__W 3 10233#define B_CE_REG_FR_RIO_GAIN__W 3
11720#define B_CE_REG_FR_RIO_GAIN__M 0x7 10234#define B_CE_REG_FR_RIO_GAIN__M 0x7
11721#define B_CE_REG_FR_RIO_GAIN_INIT 0x2 10235#define B_CE_REG_FR_RIO_GAIN_INIT 0x2
11722 10236
11723
11724#define B_CE_REG_FR_BYPASS__A 0x1820044 10237#define B_CE_REG_FR_BYPASS__A 0x1820044
11725#define B_CE_REG_FR_BYPASS__W 10 10238#define B_CE_REG_FR_BYPASS__W 10
11726#define B_CE_REG_FR_BYPASS__M 0x3FF 10239#define B_CE_REG_FR_BYPASS__M 0x3FF
@@ -11738,66 +10251,47 @@ extern "C" {
11738#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 10251#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200
11739#define B_CE_REG_FR_BYPASS_INIT 0x13B 10252#define B_CE_REG_FR_BYPASS_INIT 0x13B
11740 10253
11741
11742#define B_CE_REG_FR_PM_SET__A 0x1820045 10254#define B_CE_REG_FR_PM_SET__A 0x1820045
11743#define B_CE_REG_FR_PM_SET__W 4 10255#define B_CE_REG_FR_PM_SET__W 4
11744#define B_CE_REG_FR_PM_SET__M 0xF 10256#define B_CE_REG_FR_PM_SET__M 0xF
11745#define B_CE_REG_FR_PM_SET_INIT 0x4 10257#define B_CE_REG_FR_PM_SET_INIT 0x4
11746 10258
11747
11748#define B_CE_REG_FR_ERR_SH__A 0x1820046 10259#define B_CE_REG_FR_ERR_SH__A 0x1820046
11749#define B_CE_REG_FR_ERR_SH__W 4 10260#define B_CE_REG_FR_ERR_SH__W 4
11750#define B_CE_REG_FR_ERR_SH__M 0xF 10261#define B_CE_REG_FR_ERR_SH__M 0xF
11751#define B_CE_REG_FR_ERR_SH_INIT 0x4 10262#define B_CE_REG_FR_ERR_SH_INIT 0x4
11752 10263
11753
11754#define B_CE_REG_FR_MAN_SH__A 0x1820047 10264#define B_CE_REG_FR_MAN_SH__A 0x1820047
11755#define B_CE_REG_FR_MAN_SH__W 4 10265#define B_CE_REG_FR_MAN_SH__W 4
11756#define B_CE_REG_FR_MAN_SH__M 0xF 10266#define B_CE_REG_FR_MAN_SH__M 0xF
11757#define B_CE_REG_FR_MAN_SH_INIT 0x7 10267#define B_CE_REG_FR_MAN_SH_INIT 0x7
11758 10268
11759
11760#define B_CE_REG_FR_TAP_SH__A 0x1820048 10269#define B_CE_REG_FR_TAP_SH__A 0x1820048
11761#define B_CE_REG_FR_TAP_SH__W 3 10270#define B_CE_REG_FR_TAP_SH__W 3
11762#define B_CE_REG_FR_TAP_SH__M 0x7 10271#define B_CE_REG_FR_TAP_SH__M 0x7
11763#define B_CE_REG_FR_TAP_SH_INIT 0x3 10272#define B_CE_REG_FR_TAP_SH_INIT 0x3
11764 10273
11765
11766#define B_CE_REG_FR_CLIP__A 0x1820049 10274#define B_CE_REG_FR_CLIP__A 0x1820049
11767#define B_CE_REG_FR_CLIP__W 9 10275#define B_CE_REG_FR_CLIP__W 9
11768#define B_CE_REG_FR_CLIP__M 0x1FF 10276#define B_CE_REG_FR_CLIP__M 0x1FF
11769#define B_CE_REG_FR_CLIP_INIT 0x49 10277#define B_CE_REG_FR_CLIP_INIT 0x49
11770 10278
11771
11772#define B_CE_REG_FR_LEAK_UPD__A 0x182004A 10279#define B_CE_REG_FR_LEAK_UPD__A 0x182004A
11773#define B_CE_REG_FR_LEAK_UPD__W 3 10280#define B_CE_REG_FR_LEAK_UPD__W 3
11774#define B_CE_REG_FR_LEAK_UPD__M 0x7 10281#define B_CE_REG_FR_LEAK_UPD__M 0x7
11775#define B_CE_REG_FR_LEAK_UPD_INIT 0x1 10282#define B_CE_REG_FR_LEAK_UPD_INIT 0x1
11776 10283
11777
11778#define B_CE_REG_FR_LEAK_SH__A 0x182004B 10284#define B_CE_REG_FR_LEAK_SH__A 0x182004B
11779#define B_CE_REG_FR_LEAK_SH__W 3 10285#define B_CE_REG_FR_LEAK_SH__W 3
11780#define B_CE_REG_FR_LEAK_SH__M 0x7 10286#define B_CE_REG_FR_LEAK_SH__M 0x7
11781#define B_CE_REG_FR_LEAK_SH_INIT 0x1 10287#define B_CE_REG_FR_LEAK_SH_INIT 0x1
11782 10288
11783
11784
11785#define B_CE_PB_RAM__A 0x1830000 10289#define B_CE_PB_RAM__A 0x1830000
11786 10290
11787
11788
11789#define B_CE_NE_RAM__A 0x1840000 10291#define B_CE_NE_RAM__A 0x1840000
11790 10292
11791
11792
11793
11794
11795#define B_EQ_SID 0xE 10293#define B_EQ_SID 0xE
11796 10294
11797
11798
11799
11800
11801#define B_EQ_COMM_EXEC__A 0x1C00000 10295#define B_EQ_COMM_EXEC__A 0x1C00000
11802#define B_EQ_COMM_EXEC__W 3 10296#define B_EQ_COMM_EXEC__W 3
11803#define B_EQ_COMM_EXEC__M 0x7 10297#define B_EQ_COMM_EXEC__M 0x7
@@ -11830,11 +10324,6 @@ extern "C" {
11830#define B_EQ_COMM_INT_MSK__W 16 10324#define B_EQ_COMM_INT_MSK__W 16
11831#define B_EQ_COMM_INT_MSK__M 0xFFFF 10325#define B_EQ_COMM_INT_MSK__M 0xFFFF
11832 10326
11833
11834
11835
11836
11837
11838#define B_EQ_REG_COMM_EXEC__A 0x1C10000 10327#define B_EQ_REG_COMM_EXEC__A 0x1C10000
11839#define B_EQ_REG_COMM_EXEC__W 3 10328#define B_EQ_REG_COMM_EXEC__W 3
11840#define B_EQ_REG_COMM_EXEC__M 0x7 10329#define B_EQ_REG_COMM_EXEC__M 0x7
@@ -11877,7 +10366,6 @@ extern "C" {
11877#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 10366#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20
11878#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 10367#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30
11879 10368
11880
11881#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 10369#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003
11882#define B_EQ_REG_COMM_SERVICE0__W 10 10370#define B_EQ_REG_COMM_SERVICE0__W 10
11883#define B_EQ_REG_COMM_SERVICE0__M 0x3FF 10371#define B_EQ_REG_COMM_SERVICE0__M 0x3FF
@@ -11896,7 +10384,6 @@ extern "C" {
11896#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 10384#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1
11897#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 10385#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2
11898 10386
11899
11900#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 10387#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008
11901#define B_EQ_REG_COMM_INT_MSK__W 2 10388#define B_EQ_REG_COMM_INT_MSK__W 2
11902#define B_EQ_REG_COMM_INT_MSK__M 0x3 10389#define B_EQ_REG_COMM_INT_MSK__M 0x3
@@ -11907,7 +10394,6 @@ extern "C" {
11907#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 10394#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1
11908#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 10395#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2
11909 10396
11910
11911#define B_EQ_REG_IS_MODE__A 0x1C10014 10397#define B_EQ_REG_IS_MODE__A 0x1C10014
11912#define B_EQ_REG_IS_MODE__W 4 10398#define B_EQ_REG_IS_MODE__W 4
11913#define B_EQ_REG_IS_MODE__M 0xF 10399#define B_EQ_REG_IS_MODE__M 0xF
@@ -11925,25 +10411,21 @@ extern "C" {
11925#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 10411#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0
11926#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 10412#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2
11927 10413
11928
11929#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 10414#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015
11930#define B_EQ_REG_IS_GAIN_MAN__W 10 10415#define B_EQ_REG_IS_GAIN_MAN__W 10
11931#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF 10416#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF
11932#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 10417#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114
11933 10418
11934
11935#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 10419#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016
11936#define B_EQ_REG_IS_GAIN_EXP__W 5 10420#define B_EQ_REG_IS_GAIN_EXP__W 5
11937#define B_EQ_REG_IS_GAIN_EXP__M 0x1F 10421#define B_EQ_REG_IS_GAIN_EXP__M 0x1F
11938#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 10422#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5
11939 10423
11940
11941#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 10424#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017
11942#define B_EQ_REG_IS_CLIP_EXP__W 5 10425#define B_EQ_REG_IS_CLIP_EXP__W 5
11943#define B_EQ_REG_IS_CLIP_EXP__M 0x1F 10426#define B_EQ_REG_IS_CLIP_EXP__M 0x1F
11944#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 10427#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10
11945 10428
11946
11947#define B_EQ_REG_DV_MODE__A 0x1C1001E 10429#define B_EQ_REG_DV_MODE__A 0x1C1001E
11948#define B_EQ_REG_DV_MODE__W 4 10430#define B_EQ_REG_DV_MODE__W 4
11949#define B_EQ_REG_DV_MODE__M 0xF 10431#define B_EQ_REG_DV_MODE__M 0xF
@@ -11973,7 +10455,6 @@ extern "C" {
11973#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 10455#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0
11974#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 10456#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8
11975 10457
11976
11977#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F 10458#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F
11978#define B_EQ_REG_DV_POS_CLIP_DAT__W 16 10459#define B_EQ_REG_DV_POS_CLIP_DAT__W 16
11979#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF 10460#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF
@@ -12031,31 +10512,26 @@ extern "C" {
12031#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 10512#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0
12032#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 10513#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80
12033 10514
12034
12035#define B_EQ_REG_SN_PFIX__A 0x1C10029 10515#define B_EQ_REG_SN_PFIX__A 0x1C10029
12036#define B_EQ_REG_SN_PFIX__W 8 10516#define B_EQ_REG_SN_PFIX__W 8
12037#define B_EQ_REG_SN_PFIX__M 0xFF 10517#define B_EQ_REG_SN_PFIX__M 0xFF
12038#define B_EQ_REG_SN_PFIX_INIT 0x0 10518#define B_EQ_REG_SN_PFIX_INIT 0x0
12039 10519
12040
12041#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A 10520#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A
12042#define B_EQ_REG_SN_CEGAIN__W 8 10521#define B_EQ_REG_SN_CEGAIN__W 8
12043#define B_EQ_REG_SN_CEGAIN__M 0xFF 10522#define B_EQ_REG_SN_CEGAIN__M 0xFF
12044#define B_EQ_REG_SN_CEGAIN_INIT 0x30 10523#define B_EQ_REG_SN_CEGAIN_INIT 0x30
12045 10524
12046
12047#define B_EQ_REG_SN_OFFSET__A 0x1C1002B 10525#define B_EQ_REG_SN_OFFSET__A 0x1C1002B
12048#define B_EQ_REG_SN_OFFSET__W 6 10526#define B_EQ_REG_SN_OFFSET__W 6
12049#define B_EQ_REG_SN_OFFSET__M 0x3F 10527#define B_EQ_REG_SN_OFFSET__M 0x3F
12050#define B_EQ_REG_SN_OFFSET_INIT 0x39 10528#define B_EQ_REG_SN_OFFSET_INIT 0x39
12051 10529
12052
12053#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C 10530#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C
12054#define B_EQ_REG_SN_NULLIFY__W 6 10531#define B_EQ_REG_SN_NULLIFY__W 6
12055#define B_EQ_REG_SN_NULLIFY__M 0x3F 10532#define B_EQ_REG_SN_NULLIFY__M 0x3F
12056#define B_EQ_REG_SN_NULLIFY_INIT 0x0 10533#define B_EQ_REG_SN_NULLIFY_INIT 0x0
12057 10534
12058
12059#define B_EQ_REG_SN_SQUASH__A 0x1C1002D 10535#define B_EQ_REG_SN_SQUASH__A 0x1C1002D
12060#define B_EQ_REG_SN_SQUASH__W 10 10536#define B_EQ_REG_SN_SQUASH__W 10
12061#define B_EQ_REG_SN_SQUASH__M 0x3FF 10537#define B_EQ_REG_SN_SQUASH__M 0x3FF
@@ -12069,9 +10545,6 @@ extern "C" {
12069#define B_EQ_REG_SN_SQUASH_EXP__W 4 10545#define B_EQ_REG_SN_SQUASH_EXP__W 4
12070#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 10546#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0
12071 10547
12072
12073
12074
12075#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 10548#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032
12076#define B_EQ_REG_RC_SEL_CAR__W 8 10549#define B_EQ_REG_RC_SEL_CAR__W 8
12077#define B_EQ_REG_RC_SEL_CAR__M 0xFF 10550#define B_EQ_REG_RC_SEL_CAR__M 0xFF
@@ -12112,7 +10585,6 @@ extern "C" {
12112#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 10585#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0
12113#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 10586#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80
12114 10587
12115
12116#define B_EQ_REG_RC_STS__A 0x1C10033 10588#define B_EQ_REG_RC_STS__A 0x1C10033
12117#define B_EQ_REG_RC_STS__W 14 10589#define B_EQ_REG_RC_STS__W 14
12118#define B_EQ_REG_RC_STS__M 0x3FFF 10590#define B_EQ_REG_RC_STS__M 0x3FFF
@@ -12151,49 +10623,41 @@ extern "C" {
12151#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 10623#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0
12152#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 10624#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000
12153 10625
12154
12155#define B_EQ_REG_OT_CONST__A 0x1C10046 10626#define B_EQ_REG_OT_CONST__A 0x1C10046
12156#define B_EQ_REG_OT_CONST__W 2 10627#define B_EQ_REG_OT_CONST__W 2
12157#define B_EQ_REG_OT_CONST__M 0x3 10628#define B_EQ_REG_OT_CONST__M 0x3
12158#define B_EQ_REG_OT_CONST_INIT 0x2 10629#define B_EQ_REG_OT_CONST_INIT 0x2
12159 10630
12160
12161#define B_EQ_REG_OT_ALPHA__A 0x1C10047 10631#define B_EQ_REG_OT_ALPHA__A 0x1C10047
12162#define B_EQ_REG_OT_ALPHA__W 2 10632#define B_EQ_REG_OT_ALPHA__W 2
12163#define B_EQ_REG_OT_ALPHA__M 0x3 10633#define B_EQ_REG_OT_ALPHA__M 0x3
12164#define B_EQ_REG_OT_ALPHA_INIT 0x0 10634#define B_EQ_REG_OT_ALPHA_INIT 0x0
12165 10635
12166
12167#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 10636#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048
12168#define B_EQ_REG_OT_QNT_THRES0__W 5 10637#define B_EQ_REG_OT_QNT_THRES0__W 5
12169#define B_EQ_REG_OT_QNT_THRES0__M 0x1F 10638#define B_EQ_REG_OT_QNT_THRES0__M 0x1F
12170#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E 10639#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E
12171 10640
12172
12173#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 10641#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049
12174#define B_EQ_REG_OT_QNT_THRES1__W 5 10642#define B_EQ_REG_OT_QNT_THRES1__W 5
12175#define B_EQ_REG_OT_QNT_THRES1__M 0x1F 10643#define B_EQ_REG_OT_QNT_THRES1__M 0x1F
12176#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F 10644#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F
12177 10645
12178
12179#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A 10646#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A
12180#define B_EQ_REG_OT_CSI_STEP__W 4 10647#define B_EQ_REG_OT_CSI_STEP__W 4
12181#define B_EQ_REG_OT_CSI_STEP__M 0xF 10648#define B_EQ_REG_OT_CSI_STEP__M 0xF
12182#define B_EQ_REG_OT_CSI_STEP_INIT 0x5 10649#define B_EQ_REG_OT_CSI_STEP_INIT 0x5
12183 10650
12184
12185#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 10651#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
12186#define B_EQ_REG_OT_CSI_OFFSET__W 7 10652#define B_EQ_REG_OT_CSI_OFFSET__W 7
12187#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F 10653#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F
12188#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 10654#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5
12189 10655
12190
12191#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C 10656#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C
12192#define B_EQ_REG_OT_CSI_GAIN__W 8 10657#define B_EQ_REG_OT_CSI_GAIN__W 8
12193#define B_EQ_REG_OT_CSI_GAIN__M 0xFF 10658#define B_EQ_REG_OT_CSI_GAIN__M 0xFF
12194#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B 10659#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B
12195 10660
12196
12197#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D 10661#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D
12198#define B_EQ_REG_OT_CSI_MEAN__W 7 10662#define B_EQ_REG_OT_CSI_MEAN__W 7
12199#define B_EQ_REG_OT_CSI_MEAN__M 0x7F 10663#define B_EQ_REG_OT_CSI_MEAN__M 0x7F
@@ -12202,9 +10666,6 @@ extern "C" {
12202#define B_EQ_REG_OT_CSI_VARIANCE__W 7 10666#define B_EQ_REG_OT_CSI_VARIANCE__W 7
12203#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F 10667#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F
12204 10668
12205
12206
12207
12208#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 10669#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050
12209#define B_EQ_REG_TD_TPS_INIT__W 1 10670#define B_EQ_REG_TD_TPS_INIT__W 1
12210#define B_EQ_REG_TD_TPS_INIT__M 0x1 10671#define B_EQ_REG_TD_TPS_INIT__M 0x1
@@ -12212,7 +10673,6 @@ extern "C" {
12212#define B_EQ_REG_TD_TPS_INIT_POS 0x0 10673#define B_EQ_REG_TD_TPS_INIT_POS 0x0
12213#define B_EQ_REG_TD_TPS_INIT_NEG 0x1 10674#define B_EQ_REG_TD_TPS_INIT_NEG 0x1
12214 10675
12215
12216#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 10676#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051
12217#define B_EQ_REG_TD_TPS_SYNC__W 16 10677#define B_EQ_REG_TD_TPS_SYNC__W 16
12218#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF 10678#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF
@@ -12220,7 +10680,6 @@ extern "C" {
12220#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE 10680#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE
12221#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 10681#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11
12222 10682
12223
12224#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 10683#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052
12225#define B_EQ_REG_TD_TPS_LEN__W 6 10684#define B_EQ_REG_TD_TPS_LEN__W 6
12226#define B_EQ_REG_TD_TPS_LEN__M 0x3F 10685#define B_EQ_REG_TD_TPS_LEN__M 0x3F
@@ -12228,7 +10687,6 @@ extern "C" {
12228#define B_EQ_REG_TD_TPS_LEN_DEF 0x17 10687#define B_EQ_REG_TD_TPS_LEN_DEF 0x17
12229#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F 10688#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F
12230 10689
12231
12232#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 10690#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053
12233#define B_EQ_REG_TD_TPS_FRM_NMB__W 2 10691#define B_EQ_REG_TD_TPS_FRM_NMB__W 2
12234#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 10692#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3
@@ -12238,7 +10696,6 @@ extern "C" {
12238#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 10696#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2
12239#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 10697#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3
12240 10698
12241
12242#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 10699#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054
12243#define B_EQ_REG_TD_TPS_CONST__W 2 10700#define B_EQ_REG_TD_TPS_CONST__W 2
12244#define B_EQ_REG_TD_TPS_CONST__M 0x3 10701#define B_EQ_REG_TD_TPS_CONST__M 0x3
@@ -12247,7 +10704,6 @@ extern "C" {
12247#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 10704#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1
12248#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 10705#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2
12249 10706
12250
12251#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 10707#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055
12252#define B_EQ_REG_TD_TPS_HINFO__W 3 10708#define B_EQ_REG_TD_TPS_HINFO__W 3
12253#define B_EQ_REG_TD_TPS_HINFO__M 0x7 10709#define B_EQ_REG_TD_TPS_HINFO__M 0x7
@@ -12257,7 +10713,6 @@ extern "C" {
12257#define B_EQ_REG_TD_TPS_HINFO_H2 0x2 10713#define B_EQ_REG_TD_TPS_HINFO_H2 0x2
12258#define B_EQ_REG_TD_TPS_HINFO_H4 0x3 10714#define B_EQ_REG_TD_TPS_HINFO_H4 0x3
12259 10715
12260
12261#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 10716#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056
12262#define B_EQ_REG_TD_TPS_CODE_HP__W 3 10717#define B_EQ_REG_TD_TPS_CODE_HP__W 3
12263#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 10718#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7
@@ -12268,7 +10723,6 @@ extern "C" {
12268#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 10723#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3
12269#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 10724#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4
12270 10725
12271
12272#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 10726#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057
12273#define B_EQ_REG_TD_TPS_CODE_LP__W 3 10727#define B_EQ_REG_TD_TPS_CODE_LP__W 3
12274#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 10728#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7
@@ -12279,7 +10733,6 @@ extern "C" {
12279#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 10733#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3
12280#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 10734#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4
12281 10735
12282
12283#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 10736#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058
12284#define B_EQ_REG_TD_TPS_GUARD__W 2 10737#define B_EQ_REG_TD_TPS_GUARD__W 2
12285#define B_EQ_REG_TD_TPS_GUARD__M 0x3 10738#define B_EQ_REG_TD_TPS_GUARD__M 0x3
@@ -12289,7 +10742,6 @@ extern "C" {
12289#define B_EQ_REG_TD_TPS_GUARD_08 0x2 10742#define B_EQ_REG_TD_TPS_GUARD_08 0x2
12290#define B_EQ_REG_TD_TPS_GUARD_04 0x3 10743#define B_EQ_REG_TD_TPS_GUARD_04 0x3
12291 10744
12292
12293#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 10745#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059
12294#define B_EQ_REG_TD_TPS_TR_MODE__W 2 10746#define B_EQ_REG_TD_TPS_TR_MODE__W 2
12295#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 10747#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3
@@ -12297,68 +10749,51 @@ extern "C" {
12297#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 10749#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0
12298#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 10750#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1
12299 10751
12300
12301#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A 10752#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A
12302#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 10753#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8
12303#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF 10754#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF
12304#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 10755#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0
12305 10756
12306
12307#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B 10757#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B
12308#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 10758#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8
12309#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF 10759#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF
12310#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 10760#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0
12311 10761
12312
12313#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C 10762#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C
12314#define B_EQ_REG_TD_TPS_RSV__W 6 10763#define B_EQ_REG_TD_TPS_RSV__W 6
12315#define B_EQ_REG_TD_TPS_RSV__M 0x3F 10764#define B_EQ_REG_TD_TPS_RSV__M 0x3F
12316#define B_EQ_REG_TD_TPS_RSV_INIT 0x0 10765#define B_EQ_REG_TD_TPS_RSV_INIT 0x0
12317 10766
12318
12319#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D 10767#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D
12320#define B_EQ_REG_TD_TPS_BCH__W 14 10768#define B_EQ_REG_TD_TPS_BCH__W 14
12321#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF 10769#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF
12322#define B_EQ_REG_TD_TPS_BCH_INIT 0x0 10770#define B_EQ_REG_TD_TPS_BCH_INIT 0x0
12323 10771
12324
12325#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E 10772#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E
12326#define B_EQ_REG_TD_SQR_ERR_I__W 16 10773#define B_EQ_REG_TD_SQR_ERR_I__W 16
12327#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF 10774#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF
12328#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 10775#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0
12329 10776
12330
12331#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F 10777#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F
12332#define B_EQ_REG_TD_SQR_ERR_Q__W 16 10778#define B_EQ_REG_TD_SQR_ERR_Q__W 16
12333#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF 10779#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF
12334#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 10780#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0
12335 10781
12336
12337#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 10782#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060
12338#define B_EQ_REG_TD_SQR_ERR_EXP__W 4 10783#define B_EQ_REG_TD_SQR_ERR_EXP__W 4
12339#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF 10784#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF
12340#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 10785#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0
12341 10786
12342
12343#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 10787#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
12344#define B_EQ_REG_TD_REQ_SMB_CNT__W 16 10788#define B_EQ_REG_TD_REQ_SMB_CNT__W 16
12345#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF 10789#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF
12346#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 10790#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200
12347 10791
12348
12349#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 10792#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
12350#define B_EQ_REG_TD_TPS_PWR_OFS__W 16 10793#define B_EQ_REG_TD_TPS_PWR_OFS__W 16
12351#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF 10794#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF
12352#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F 10795#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F
12353 10796
12354
12355
12356
12357
12358
12359
12360
12361
12362#define B_EC_COMM_EXEC__A 0x2000000 10797#define B_EC_COMM_EXEC__A 0x2000000
12363#define B_EC_COMM_EXEC__W 3 10798#define B_EC_COMM_EXEC__W 3
12364#define B_EC_COMM_EXEC__M 0x7 10799#define B_EC_COMM_EXEC__M 0x7
@@ -12391,16 +10826,8 @@ extern "C" {
12391#define B_EC_COMM_INT_MSK__W 16 10826#define B_EC_COMM_INT_MSK__W 16
12392#define B_EC_COMM_INT_MSK__M 0xFFFF 10827#define B_EC_COMM_INT_MSK__M 0xFFFF
12393 10828
12394
12395
12396
12397
12398#define B_EC_SB_SID 0x16 10829#define B_EC_SB_SID 0x16
12399 10830
12400
12401
12402
12403
12404#define B_EC_SB_REG_COMM_EXEC__A 0x2010000 10831#define B_EC_SB_REG_COMM_EXEC__A 0x2010000
12405#define B_EC_SB_REG_COMM_EXEC__W 3 10832#define B_EC_SB_REG_COMM_EXEC__W 3
12406#define B_EC_SB_REG_COMM_EXEC__M 0x7 10833#define B_EC_SB_REG_COMM_EXEC__M 0x7
@@ -12428,7 +10855,6 @@ extern "C" {
12428#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 10855#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0
12429#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 10856#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2
12430 10857
12431
12432#define B_EC_SB_REG_TR_MODE__A 0x2010010 10858#define B_EC_SB_REG_TR_MODE__A 0x2010010
12433#define B_EC_SB_REG_TR_MODE__W 1 10859#define B_EC_SB_REG_TR_MODE__W 1
12434#define B_EC_SB_REG_TR_MODE__M 0x1 10860#define B_EC_SB_REG_TR_MODE__M 0x1
@@ -12436,7 +10862,6 @@ extern "C" {
12436#define B_EC_SB_REG_TR_MODE_8K 0x0 10862#define B_EC_SB_REG_TR_MODE_8K 0x0
12437#define B_EC_SB_REG_TR_MODE_2K 0x1 10863#define B_EC_SB_REG_TR_MODE_2K 0x1
12438 10864
12439
12440#define B_EC_SB_REG_CONST__A 0x2010011 10865#define B_EC_SB_REG_CONST__A 0x2010011
12441#define B_EC_SB_REG_CONST__W 2 10866#define B_EC_SB_REG_CONST__W 2
12442#define B_EC_SB_REG_CONST__M 0x3 10867#define B_EC_SB_REG_CONST__M 0x3
@@ -12445,7 +10870,6 @@ extern "C" {
12445#define B_EC_SB_REG_CONST_16QAM 0x1 10870#define B_EC_SB_REG_CONST_16QAM 0x1
12446#define B_EC_SB_REG_CONST_64QAM 0x2 10871#define B_EC_SB_REG_CONST_64QAM 0x2
12447 10872
12448
12449#define B_EC_SB_REG_ALPHA__A 0x2010012 10873#define B_EC_SB_REG_ALPHA__A 0x2010012
12450#define B_EC_SB_REG_ALPHA__W 3 10874#define B_EC_SB_REG_ALPHA__W 3
12451#define B_EC_SB_REG_ALPHA__M 0x7 10875#define B_EC_SB_REG_ALPHA__M 0x7
@@ -12460,7 +10884,6 @@ extern "C" {
12460 10884
12461#define B_EC_SB_REG_ALPHA_H4 0x3 10885#define B_EC_SB_REG_ALPHA_H4 0x3
12462 10886
12463
12464#define B_EC_SB_REG_PRIOR__A 0x2010013 10887#define B_EC_SB_REG_PRIOR__A 0x2010013
12465#define B_EC_SB_REG_PRIOR__W 1 10888#define B_EC_SB_REG_PRIOR__W 1
12466#define B_EC_SB_REG_PRIOR__M 0x1 10889#define B_EC_SB_REG_PRIOR__M 0x1
@@ -12468,7 +10891,6 @@ extern "C" {
12468#define B_EC_SB_REG_PRIOR_HI 0x0 10891#define B_EC_SB_REG_PRIOR_HI 0x0
12469#define B_EC_SB_REG_PRIOR_LO 0x1 10892#define B_EC_SB_REG_PRIOR_LO 0x1
12470 10893
12471
12472#define B_EC_SB_REG_CSI_HI__A 0x2010014 10894#define B_EC_SB_REG_CSI_HI__A 0x2010014
12473#define B_EC_SB_REG_CSI_HI__W 5 10895#define B_EC_SB_REG_CSI_HI__W 5
12474#define B_EC_SB_REG_CSI_HI__M 0x1F 10896#define B_EC_SB_REG_CSI_HI__M 0x1F
@@ -12477,7 +10899,6 @@ extern "C" {
12477#define B_EC_SB_REG_CSI_HI_MIN 0x0 10899#define B_EC_SB_REG_CSI_HI_MIN 0x0
12478#define B_EC_SB_REG_CSI_HI_TAG 0x0 10900#define B_EC_SB_REG_CSI_HI_TAG 0x0
12479 10901
12480
12481#define B_EC_SB_REG_CSI_LO__A 0x2010015 10902#define B_EC_SB_REG_CSI_LO__A 0x2010015
12482#define B_EC_SB_REG_CSI_LO__W 5 10903#define B_EC_SB_REG_CSI_LO__W 5
12483#define B_EC_SB_REG_CSI_LO__M 0x1F 10904#define B_EC_SB_REG_CSI_LO__M 0x1F
@@ -12486,7 +10907,6 @@ extern "C" {
12486#define B_EC_SB_REG_CSI_LO_MIN 0x0 10907#define B_EC_SB_REG_CSI_LO_MIN 0x0
12487#define B_EC_SB_REG_CSI_LO_TAG 0x0 10908#define B_EC_SB_REG_CSI_LO_TAG 0x0
12488 10909
12489
12490#define B_EC_SB_REG_SMB_TGL__A 0x2010016 10910#define B_EC_SB_REG_SMB_TGL__A 0x2010016
12491#define B_EC_SB_REG_SMB_TGL__W 1 10911#define B_EC_SB_REG_SMB_TGL__W 1
12492#define B_EC_SB_REG_SMB_TGL__M 0x1 10912#define B_EC_SB_REG_SMB_TGL__M 0x1
@@ -12494,7 +10914,6 @@ extern "C" {
12494#define B_EC_SB_REG_SMB_TGL_ON 0x1 10914#define B_EC_SB_REG_SMB_TGL_ON 0x1
12495#define B_EC_SB_REG_SMB_TGL_INIT 0x1 10915#define B_EC_SB_REG_SMB_TGL_INIT 0x1
12496 10916
12497
12498#define B_EC_SB_REG_SNR_HI__A 0x2010017 10917#define B_EC_SB_REG_SNR_HI__A 0x2010017
12499#define B_EC_SB_REG_SNR_HI__W 8 10918#define B_EC_SB_REG_SNR_HI__W 8
12500#define B_EC_SB_REG_SNR_HI__M 0xFF 10919#define B_EC_SB_REG_SNR_HI__M 0xFF
@@ -12503,7 +10922,6 @@ extern "C" {
12503#define B_EC_SB_REG_SNR_HI_MIN 0x0 10922#define B_EC_SB_REG_SNR_HI_MIN 0x0
12504#define B_EC_SB_REG_SNR_HI_TAG 0x0 10923#define B_EC_SB_REG_SNR_HI_TAG 0x0
12505 10924
12506
12507#define B_EC_SB_REG_SNR_MID__A 0x2010018 10925#define B_EC_SB_REG_SNR_MID__A 0x2010018
12508#define B_EC_SB_REG_SNR_MID__W 8 10926#define B_EC_SB_REG_SNR_MID__W 8
12509#define B_EC_SB_REG_SNR_MID__M 0xFF 10927#define B_EC_SB_REG_SNR_MID__M 0xFF
@@ -12512,7 +10930,6 @@ extern "C" {
12512#define B_EC_SB_REG_SNR_MID_MIN 0x0 10930#define B_EC_SB_REG_SNR_MID_MIN 0x0
12513#define B_EC_SB_REG_SNR_MID_TAG 0x0 10931#define B_EC_SB_REG_SNR_MID_TAG 0x0
12514 10932
12515
12516#define B_EC_SB_REG_SNR_LO__A 0x2010019 10933#define B_EC_SB_REG_SNR_LO__A 0x2010019
12517#define B_EC_SB_REG_SNR_LO__W 8 10934#define B_EC_SB_REG_SNR_LO__W 8
12518#define B_EC_SB_REG_SNR_LO__M 0xFF 10935#define B_EC_SB_REG_SNR_LO__M 0xFF
@@ -12521,91 +10938,67 @@ extern "C" {
12521#define B_EC_SB_REG_SNR_LO_MIN 0x0 10938#define B_EC_SB_REG_SNR_LO_MIN 0x0
12522#define B_EC_SB_REG_SNR_LO_TAG 0x0 10939#define B_EC_SB_REG_SNR_LO_TAG 0x0
12523 10940
12524
12525#define B_EC_SB_REG_SCALE_MSB__A 0x201001A 10941#define B_EC_SB_REG_SCALE_MSB__A 0x201001A
12526#define B_EC_SB_REG_SCALE_MSB__W 6 10942#define B_EC_SB_REG_SCALE_MSB__W 6
12527#define B_EC_SB_REG_SCALE_MSB__M 0x3F 10943#define B_EC_SB_REG_SCALE_MSB__M 0x3F
12528#define B_EC_SB_REG_SCALE_MSB_INIT 0x30 10944#define B_EC_SB_REG_SCALE_MSB_INIT 0x30
12529#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F 10945#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F
12530 10946
12531
12532#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B 10947#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B
12533#define B_EC_SB_REG_SCALE_BIT2__W 6 10948#define B_EC_SB_REG_SCALE_BIT2__W 6
12534#define B_EC_SB_REG_SCALE_BIT2__M 0x3F 10949#define B_EC_SB_REG_SCALE_BIT2__M 0x3F
12535#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC 10950#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC
12536#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F 10951#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F
12537 10952
12538
12539#define B_EC_SB_REG_SCALE_LSB__A 0x201001C 10953#define B_EC_SB_REG_SCALE_LSB__A 0x201001C
12540#define B_EC_SB_REG_SCALE_LSB__W 6 10954#define B_EC_SB_REG_SCALE_LSB__W 6
12541#define B_EC_SB_REG_SCALE_LSB__M 0x3F 10955#define B_EC_SB_REG_SCALE_LSB__M 0x3F
12542#define B_EC_SB_REG_SCALE_LSB_INIT 0x3 10956#define B_EC_SB_REG_SCALE_LSB_INIT 0x3
12543#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F 10957#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F
12544 10958
12545
12546#define B_EC_SB_REG_CSI_OFS0__A 0x201001D 10959#define B_EC_SB_REG_CSI_OFS0__A 0x201001D
12547#define B_EC_SB_REG_CSI_OFS0__W 4 10960#define B_EC_SB_REG_CSI_OFS0__W 4
12548#define B_EC_SB_REG_CSI_OFS0__M 0xF 10961#define B_EC_SB_REG_CSI_OFS0__M 0xF
12549#define B_EC_SB_REG_CSI_OFS0_INIT 0x4 10962#define B_EC_SB_REG_CSI_OFS0_INIT 0x4
12550 10963
12551
12552#define B_EC_SB_REG_CSI_OFS1__A 0x201001E 10964#define B_EC_SB_REG_CSI_OFS1__A 0x201001E
12553#define B_EC_SB_REG_CSI_OFS1__W 4 10965#define B_EC_SB_REG_CSI_OFS1__W 4
12554#define B_EC_SB_REG_CSI_OFS1__M 0xF 10966#define B_EC_SB_REG_CSI_OFS1__M 0xF
12555#define B_EC_SB_REG_CSI_OFS1_INIT 0x1 10967#define B_EC_SB_REG_CSI_OFS1_INIT 0x1
12556 10968
12557
12558#define B_EC_SB_REG_CSI_OFS2__A 0x201001F 10969#define B_EC_SB_REG_CSI_OFS2__A 0x201001F
12559#define B_EC_SB_REG_CSI_OFS2__W 4 10970#define B_EC_SB_REG_CSI_OFS2__W 4
12560#define B_EC_SB_REG_CSI_OFS2__M 0xF 10971#define B_EC_SB_REG_CSI_OFS2__M 0xF
12561#define B_EC_SB_REG_CSI_OFS2_INIT 0x2 10972#define B_EC_SB_REG_CSI_OFS2_INIT 0x2
12562 10973
12563
12564#define B_EC_SB_REG_MAX0__A 0x2010020 10974#define B_EC_SB_REG_MAX0__A 0x2010020
12565#define B_EC_SB_REG_MAX0__W 6 10975#define B_EC_SB_REG_MAX0__W 6
12566#define B_EC_SB_REG_MAX0__M 0x3F 10976#define B_EC_SB_REG_MAX0__M 0x3F
12567#define B_EC_SB_REG_MAX0_INIT 0x3F 10977#define B_EC_SB_REG_MAX0_INIT 0x3F
12568 10978
12569
12570#define B_EC_SB_REG_MAX1__A 0x2010021 10979#define B_EC_SB_REG_MAX1__A 0x2010021
12571#define B_EC_SB_REG_MAX1__W 6 10980#define B_EC_SB_REG_MAX1__W 6
12572#define B_EC_SB_REG_MAX1__M 0x3F 10981#define B_EC_SB_REG_MAX1__M 0x3F
12573#define B_EC_SB_REG_MAX1_INIT 0x3F 10982#define B_EC_SB_REG_MAX1_INIT 0x3F
12574 10983
12575
12576#define B_EC_SB_REG_MAX2__A 0x2010022 10984#define B_EC_SB_REG_MAX2__A 0x2010022
12577#define B_EC_SB_REG_MAX2__W 6 10985#define B_EC_SB_REG_MAX2__W 6
12578#define B_EC_SB_REG_MAX2__M 0x3F 10986#define B_EC_SB_REG_MAX2__M 0x3F
12579#define B_EC_SB_REG_MAX2_INIT 0x3F 10987#define B_EC_SB_REG_MAX2_INIT 0x3F
12580 10988
12581
12582#define B_EC_SB_REG_CSI_DIS__A 0x2010023 10989#define B_EC_SB_REG_CSI_DIS__A 0x2010023
12583#define B_EC_SB_REG_CSI_DIS__W 1 10990#define B_EC_SB_REG_CSI_DIS__W 1
12584#define B_EC_SB_REG_CSI_DIS__M 0x1 10991#define B_EC_SB_REG_CSI_DIS__M 0x1
12585#define B_EC_SB_REG_CSI_DIS_INIT 0x0 10992#define B_EC_SB_REG_CSI_DIS_INIT 0x0
12586 10993
12587
12588
12589#define B_EC_SB_SD_RAM__A 0x2020000 10994#define B_EC_SB_SD_RAM__A 0x2020000
12590 10995
12591
12592
12593#define B_EC_SB_BD0_RAM__A 0x2030000 10996#define B_EC_SB_BD0_RAM__A 0x2030000
12594 10997
12595
12596
12597#define B_EC_SB_BD1_RAM__A 0x2040000 10998#define B_EC_SB_BD1_RAM__A 0x2040000
12598 10999
12599
12600
12601
12602
12603#define B_EC_VD_SID 0x17 11000#define B_EC_VD_SID 0x17
12604 11001
12605
12606
12607
12608
12609#define B_EC_VD_REG_COMM_EXEC__A 0x2090000 11002#define B_EC_VD_REG_COMM_EXEC__A 0x2090000
12610#define B_EC_VD_REG_COMM_EXEC__W 3 11003#define B_EC_VD_REG_COMM_EXEC__W 3
12611#define B_EC_VD_REG_COMM_EXEC__M 0x7 11004#define B_EC_VD_REG_COMM_EXEC__M 0x7
@@ -12653,7 +11046,6 @@ extern "C" {
12653#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 11046#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1
12654#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 11047#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1
12655 11048
12656
12657#define B_EC_VD_REG_FORCE__A 0x2090010 11049#define B_EC_VD_REG_FORCE__A 0x2090010
12658#define B_EC_VD_REG_FORCE__W 2 11050#define B_EC_VD_REG_FORCE__W 2
12659#define B_EC_VD_REG_FORCE__M 0x3 11051#define B_EC_VD_REG_FORCE__M 0x3
@@ -12663,7 +11055,6 @@ extern "C" {
12663#define B_EC_VD_REG_FORCE_FORCED 0x2 11055#define B_EC_VD_REG_FORCE_FORCED 0x2
12664#define B_EC_VD_REG_FORCE_FIXED 0x3 11056#define B_EC_VD_REG_FORCE_FIXED 0x3
12665 11057
12666
12667#define B_EC_VD_REG_SET_CODERATE__A 0x2090011 11058#define B_EC_VD_REG_SET_CODERATE__A 0x2090011
12668#define B_EC_VD_REG_SET_CODERATE__W 3 11059#define B_EC_VD_REG_SET_CODERATE__W 3
12669#define B_EC_VD_REG_SET_CODERATE__M 0x7 11060#define B_EC_VD_REG_SET_CODERATE__M 0x7
@@ -12674,19 +11065,16 @@ extern "C" {
12674#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 11065#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3
12675#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 11066#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4
12676 11067
12677
12678#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 11068#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012
12679#define B_EC_VD_REG_REQ_SMB_CNT__W 16 11069#define B_EC_VD_REG_REQ_SMB_CNT__W 16
12680#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF 11070#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF
12681#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 11071#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1
12682 11072
12683
12684#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 11073#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013
12685#define B_EC_VD_REG_REQ_BIT_CNT__W 16 11074#define B_EC_VD_REG_REQ_BIT_CNT__W 16
12686#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF 11075#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF
12687#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF 11076#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF
12688 11077
12689
12690#define B_EC_VD_REG_RLK_ENA__A 0x2090014 11078#define B_EC_VD_REG_RLK_ENA__A 0x2090014
12691#define B_EC_VD_REG_RLK_ENA__W 1 11079#define B_EC_VD_REG_RLK_ENA__W 1
12692#define B_EC_VD_REG_RLK_ENA__M 0x1 11080#define B_EC_VD_REG_RLK_ENA__M 0x1
@@ -12694,7 +11082,6 @@ extern "C" {
12694#define B_EC_VD_REG_RLK_ENA_OFF 0x0 11082#define B_EC_VD_REG_RLK_ENA_OFF 0x0
12695#define B_EC_VD_REG_RLK_ENA_ON 0x1 11083#define B_EC_VD_REG_RLK_ENA_ON 0x1
12696 11084
12697
12698#define B_EC_VD_REG_VAL__A 0x2090015 11085#define B_EC_VD_REG_VAL__A 0x2090015
12699#define B_EC_VD_REG_VAL__W 2 11086#define B_EC_VD_REG_VAL__W 2
12700#define B_EC_VD_REG_VAL__M 0x3 11087#define B_EC_VD_REG_VAL__M 0x3
@@ -12702,7 +11089,6 @@ extern "C" {
12702#define B_EC_VD_REG_VAL_CODE 0x1 11089#define B_EC_VD_REG_VAL_CODE 0x1
12703#define B_EC_VD_REG_VAL_CNT 0x2 11090#define B_EC_VD_REG_VAL_CNT 0x2
12704 11091
12705
12706#define B_EC_VD_REG_GET_CODERATE__A 0x2090016 11092#define B_EC_VD_REG_GET_CODERATE__A 0x2090016
12707#define B_EC_VD_REG_GET_CODERATE__W 3 11093#define B_EC_VD_REG_GET_CODERATE__W 3
12708#define B_EC_VD_REG_GET_CODERATE__M 0x7 11094#define B_EC_VD_REG_GET_CODERATE__M 0x7
@@ -12713,19 +11099,16 @@ extern "C" {
12713#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 11099#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3
12714#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 11100#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4
12715 11101
12716
12717#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 11102#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017
12718#define B_EC_VD_REG_ERR_BIT_CNT__W 16 11103#define B_EC_VD_REG_ERR_BIT_CNT__W 16
12719#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF 11104#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF
12720#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF 11105#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF
12721 11106
12722
12723#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 11107#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018
12724#define B_EC_VD_REG_IN_BIT_CNT__W 16 11108#define B_EC_VD_REG_IN_BIT_CNT__W 16
12725#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF 11109#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF
12726#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 11110#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0
12727 11111
12728
12729#define B_EC_VD_REG_STS__A 0x2090019 11112#define B_EC_VD_REG_STS__A 0x2090019
12730#define B_EC_VD_REG_STS__W 1 11113#define B_EC_VD_REG_STS__W 1
12731#define B_EC_VD_REG_STS__M 0x1 11114#define B_EC_VD_REG_STS__M 0x1
@@ -12733,43 +11116,23 @@ extern "C" {
12733#define B_EC_VD_REG_STS_NO_LOCK 0x0 11116#define B_EC_VD_REG_STS_NO_LOCK 0x0
12734#define B_EC_VD_REG_STS_IN_LOCK 0x1 11117#define B_EC_VD_REG_STS_IN_LOCK 0x1
12735 11118
12736
12737#define B_EC_VD_REG_RLK_CNT__A 0x209001A 11119#define B_EC_VD_REG_RLK_CNT__A 0x209001A
12738#define B_EC_VD_REG_RLK_CNT__W 16 11120#define B_EC_VD_REG_RLK_CNT__W 16
12739#define B_EC_VD_REG_RLK_CNT__M 0xFFFF 11121#define B_EC_VD_REG_RLK_CNT__M 0xFFFF
12740#define B_EC_VD_REG_RLK_CNT_INIT 0x0 11122#define B_EC_VD_REG_RLK_CNT_INIT 0x0
12741 11123
12742
12743
12744#define B_EC_VD_TB0_RAM__A 0x20A0000 11124#define B_EC_VD_TB0_RAM__A 0x20A0000
12745 11125
12746
12747
12748#define B_EC_VD_TB1_RAM__A 0x20B0000 11126#define B_EC_VD_TB1_RAM__A 0x20B0000
12749 11127
12750
12751
12752#define B_EC_VD_TB2_RAM__A 0x20C0000 11128#define B_EC_VD_TB2_RAM__A 0x20C0000
12753 11129
12754
12755
12756#define B_EC_VD_TB3_RAM__A 0x20D0000 11130#define B_EC_VD_TB3_RAM__A 0x20D0000
12757 11131
12758
12759
12760#define B_EC_VD_RE_RAM__A 0x2100000 11132#define B_EC_VD_RE_RAM__A 0x2100000
12761 11133
12762
12763
12764
12765
12766#define B_EC_OD_SID 0x18 11134#define B_EC_OD_SID 0x18
12767 11135
12768
12769
12770
12771
12772
12773#define B_EC_OD_REG_COMM_EXEC__A 0x2110000 11136#define B_EC_OD_REG_COMM_EXEC__A 0x2110000
12774#define B_EC_OD_REG_COMM_EXEC__W 3 11137#define B_EC_OD_REG_COMM_EXEC__W 3
12775#define B_EC_OD_REG_COMM_EXEC__M 0x7 11138#define B_EC_OD_REG_COMM_EXEC__M 0x7
@@ -12788,7 +11151,6 @@ extern "C" {
12788#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 11151#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1
12789#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 11152#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1
12790 11153
12791
12792#define B_EC_OD_REG_COMM_MB__A 0x2110002 11154#define B_EC_OD_REG_COMM_MB__A 0x2110002
12793#define B_EC_OD_REG_COMM_MB__W 3 11155#define B_EC_OD_REG_COMM_MB__W 3
12794#define B_EC_OD_REG_COMM_MB__M 0x7 11156#define B_EC_OD_REG_COMM_MB__M 0x7
@@ -12828,7 +11190,6 @@ extern "C" {
12828#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 11190#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1
12829#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 11191#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2
12830 11192
12831
12832#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 11193#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008
12833#define B_EC_OD_REG_COMM_INT_MSK__W 2 11194#define B_EC_OD_REG_COMM_INT_MSK__W 2
12834#define B_EC_OD_REG_COMM_INT_MSK__M 0x3 11195#define B_EC_OD_REG_COMM_INT_MSK__M 0x3
@@ -12839,7 +11200,6 @@ extern "C" {
12839#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 11200#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1
12840#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 11201#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2
12841 11202
12842
12843#define B_EC_OD_REG_SYNC__A 0x2110664 11203#define B_EC_OD_REG_SYNC__A 0x2110664
12844#define B_EC_OD_REG_SYNC__W 12 11204#define B_EC_OD_REG_SYNC__W 12
12845#define B_EC_OD_REG_SYNC__M 0xFFF 11205#define B_EC_OD_REG_SYNC__M 0xFFF
@@ -12853,25 +11213,14 @@ extern "C" {
12853#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 11213#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3
12854#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 11214#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00
12855 11215
12856
12857#define B_EC_OD_REG_NOSYNC__A 0x2110004 11216#define B_EC_OD_REG_NOSYNC__A 0x2110004
12858#define B_EC_OD_REG_NOSYNC__W 8 11217#define B_EC_OD_REG_NOSYNC__W 8
12859#define B_EC_OD_REG_NOSYNC__M 0xFF 11218#define B_EC_OD_REG_NOSYNC__M 0xFF
12860 11219
12861
12862
12863#define B_EC_OD_DEINT_RAM__A 0x2120000 11220#define B_EC_OD_DEINT_RAM__A 0x2120000
12864 11221
12865
12866
12867
12868
12869#define B_EC_RS_SID 0x19 11222#define B_EC_RS_SID 0x19
12870 11223
12871
12872
12873
12874
12875#define B_EC_RS_REG_COMM_EXEC__A 0x2130000 11224#define B_EC_RS_REG_COMM_EXEC__A 0x2130000
12876#define B_EC_RS_REG_COMM_EXEC__W 3 11225#define B_EC_RS_REG_COMM_EXEC__W 3
12877#define B_EC_RS_REG_COMM_EXEC__M 0x7 11226#define B_EC_RS_REG_COMM_EXEC__M 0x7
@@ -12919,58 +11268,41 @@ extern "C" {
12919#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 11268#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1
12920#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 11269#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1
12921 11270
12922
12923#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 11271#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010
12924#define B_EC_RS_REG_REQ_PCK_CNT__W 16 11272#define B_EC_RS_REG_REQ_PCK_CNT__W 16
12925#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF 11273#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF
12926#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 11274#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200
12927 11275
12928
12929#define B_EC_RS_REG_VAL__A 0x2130011 11276#define B_EC_RS_REG_VAL__A 0x2130011
12930#define B_EC_RS_REG_VAL__W 1 11277#define B_EC_RS_REG_VAL__W 1
12931#define B_EC_RS_REG_VAL__M 0x1 11278#define B_EC_RS_REG_VAL__M 0x1
12932#define B_EC_RS_REG_VAL_INIT 0x0 11279#define B_EC_RS_REG_VAL_INIT 0x0
12933#define B_EC_RS_REG_VAL_PCK 0x1 11280#define B_EC_RS_REG_VAL_PCK 0x1
12934 11281
12935
12936#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 11282#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012
12937#define B_EC_RS_REG_ERR_PCK_CNT__W 16 11283#define B_EC_RS_REG_ERR_PCK_CNT__W 16
12938#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF 11284#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF
12939#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF 11285#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF
12940 11286
12941
12942#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 11287#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013
12943#define B_EC_RS_REG_ERR_SMB_CNT__W 16 11288#define B_EC_RS_REG_ERR_SMB_CNT__W 16
12944#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF 11289#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF
12945#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF 11290#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF
12946 11291
12947
12948#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 11292#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014
12949#define B_EC_RS_REG_ERR_BIT_CNT__W 16 11293#define B_EC_RS_REG_ERR_BIT_CNT__W 16
12950#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF 11294#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF
12951#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF 11295#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF
12952 11296
12953
12954#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 11297#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015
12955#define B_EC_RS_REG_IN_PCK_CNT__W 16 11298#define B_EC_RS_REG_IN_PCK_CNT__W 16
12956#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF 11299#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF
12957#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 11300#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0
12958 11301
12959
12960
12961#define B_EC_RS_EC_RAM__A 0x2140000 11302#define B_EC_RS_EC_RAM__A 0x2140000
12962 11303
12963
12964
12965
12966
12967#define B_EC_OC_SID 0x1A 11304#define B_EC_OC_SID 0x1A
12968 11305
12969
12970
12971
12972
12973
12974#define B_EC_OC_REG_COMM_EXEC__A 0x2150000 11306#define B_EC_OC_REG_COMM_EXEC__A 0x2150000
12975#define B_EC_OC_REG_COMM_EXEC__W 3 11307#define B_EC_OC_REG_COMM_EXEC__W 3
12976#define B_EC_OC_REG_COMM_EXEC__M 0x7 11308#define B_EC_OC_REG_COMM_EXEC__M 0x7
@@ -13000,7 +11332,6 @@ extern "C" {
13000#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 11332#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0
13001#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 11333#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2
13002 11334
13003
13004#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 11335#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003
13005#define B_EC_OC_REG_COMM_SERVICE0__W 10 11336#define B_EC_OC_REG_COMM_SERVICE0__W 10
13006#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF 11337#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF
@@ -13031,7 +11362,6 @@ extern "C" {
13031#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 11362#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1
13032#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 11363#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20
13033 11364
13034
13035#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 11365#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008
13036#define B_EC_OC_REG_COMM_INT_MSK__W 6 11366#define B_EC_OC_REG_COMM_INT_MSK__W 6
13037#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F 11367#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F
@@ -13054,7 +11384,6 @@ extern "C" {
13054#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 11384#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1
13055#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 11385#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20
13056 11386
13057
13058#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 11387#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010
13059#define B_EC_OC_REG_OC_MODE_LOP__W 16 11388#define B_EC_OC_REG_OC_MODE_LOP__W 16
13060#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF 11389#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF
@@ -13144,7 +11473,6 @@ extern "C" {
13144#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 11473#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0
13145#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 11474#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000
13146 11475
13147
13148#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 11476#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011
13149#define B_EC_OC_REG_OC_MODE_HIP__W 15 11477#define B_EC_OC_REG_OC_MODE_HIP__W 15
13150#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF 11478#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF
@@ -13240,7 +11568,6 @@ extern "C" {
13240#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 11568#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0
13241#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 11569#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000
13242 11570
13243
13244#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 11571#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012
13245#define B_EC_OC_REG_OC_MPG_SIO__W 12 11572#define B_EC_OC_REG_OC_MPG_SIO__W 12
13246#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF 11573#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF
@@ -13318,19 +11645,16 @@ extern "C" {
13318#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 11645#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0
13319#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 11646#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800
13320 11647
13321
13322#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 11648#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014
13323#define B_EC_OC_REG_DTO_INC_LOP__W 16 11649#define B_EC_OC_REG_DTO_INC_LOP__W 16
13324#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF 11650#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF
13325#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 11651#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0
13326 11652
13327
13328#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 11653#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015
13329#define B_EC_OC_REG_DTO_INC_HIP__W 8 11654#define B_EC_OC_REG_DTO_INC_HIP__W 8
13330#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF 11655#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF
13331#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 11656#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0
13332 11657
13333
13334#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 11658#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016
13335#define B_EC_OC_REG_SNC_ISC_LVL__W 12 11659#define B_EC_OC_REG_SNC_ISC_LVL__W 12
13336#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF 11660#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF
@@ -13348,13 +11672,11 @@ extern "C" {
13348#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 11672#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4
13349#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 11673#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00
13350 11674
13351
13352#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 11675#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017
13353#define B_EC_OC_REG_SNC_NSC_LVL__W 8 11676#define B_EC_OC_REG_SNC_NSC_LVL__W 8
13354#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF 11677#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF
13355#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 11678#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0
13356 11679
13357
13358#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 11680#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019
13359#define B_EC_OC_REG_SNC_SNC_MODE__W 2 11681#define B_EC_OC_REG_SNC_SNC_MODE__W 2
13360#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 11682#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3
@@ -13362,7 +11684,6 @@ extern "C" {
13362#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 11684#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1
13363#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 11685#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2
13364 11686
13365
13366#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A 11687#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A
13367#define B_EC_OC_REG_SNC_PCK_NMB__W 16 11688#define B_EC_OC_REG_SNC_PCK_NMB__W 16
13368#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF 11689#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF
@@ -13384,49 +11705,41 @@ extern "C" {
13384#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 11705#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2
13385#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 11706#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3
13386 11707
13387
13388#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E 11708#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E
13389#define B_EC_OC_REG_TMD_TOP_CNT__W 10 11709#define B_EC_OC_REG_TMD_TOP_CNT__W 10
13390#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF 11710#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF
13391#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 11711#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4
13392 11712
13393
13394#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F 11713#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F
13395#define B_EC_OC_REG_TMD_HIL_MAR__W 10 11714#define B_EC_OC_REG_TMD_HIL_MAR__W 10
13396#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF 11715#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF
13397#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 11716#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0
13398 11717
13399
13400#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 11718#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020
13401#define B_EC_OC_REG_TMD_LOL_MAR__W 10 11719#define B_EC_OC_REG_TMD_LOL_MAR__W 10
13402#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF 11720#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF
13403#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 11721#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40
13404 11722
13405
13406#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 11723#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021
13407#define B_EC_OC_REG_TMD_CUR_CNT__W 4 11724#define B_EC_OC_REG_TMD_CUR_CNT__W 4
13408#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF 11725#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF
13409#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 11726#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3
13410 11727
13411
13412#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 11728#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022
13413#define B_EC_OC_REG_TMD_IUR_CNT__W 4 11729#define B_EC_OC_REG_TMD_IUR_CNT__W 4
13414#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF 11730#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF
13415#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 11731#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0
13416 11732
13417
13418#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 11733#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023
13419#define B_EC_OC_REG_AVR_ASH_CNT__W 4 11734#define B_EC_OC_REG_AVR_ASH_CNT__W 4
13420#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF 11735#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF
13421#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 11736#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6
13422 11737
13423
13424#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 11738#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024
13425#define B_EC_OC_REG_AVR_BSH_CNT__W 4 11739#define B_EC_OC_REG_AVR_BSH_CNT__W 4
13426#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF 11740#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF
13427#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 11741#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2
13428 11742
13429
13430#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 11743#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025
13431#define B_EC_OC_REG_AVR_AVE_LOP__W 16 11744#define B_EC_OC_REG_AVR_AVE_LOP__W 16
13432#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF 11745#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF
@@ -13458,43 +11771,36 @@ extern "C" {
13458#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 11771#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4
13459#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 11772#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0
13460 11773
13461
13462#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 11774#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028
13463#define B_EC_OC_REG_RCN_CRA_LOP__W 16 11775#define B_EC_OC_REG_RCN_CRA_LOP__W 16
13464#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF 11776#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF
13465#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 11777#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0
13466 11778
13467
13468#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 11779#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029
13469#define B_EC_OC_REG_RCN_CRA_HIP__W 8 11780#define B_EC_OC_REG_RCN_CRA_HIP__W 8
13470#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF 11781#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF
13471#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 11782#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0
13472 11783
13473
13474#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A 11784#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A
13475#define B_EC_OC_REG_RCN_CST_LOP__W 16 11785#define B_EC_OC_REG_RCN_CST_LOP__W 16
13476#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF 11786#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF
13477#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 11787#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000
13478 11788
13479
13480#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B 11789#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B
13481#define B_EC_OC_REG_RCN_CST_HIP__W 8 11790#define B_EC_OC_REG_RCN_CST_HIP__W 8
13482#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF 11791#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF
13483#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 11792#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0
13484 11793
13485
13486#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C 11794#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C
13487#define B_EC_OC_REG_RCN_SET_LVL__W 9 11795#define B_EC_OC_REG_RCN_SET_LVL__W 9
13488#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF 11796#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF
13489#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF 11797#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF
13490 11798
13491
13492#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D 11799#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D
13493#define B_EC_OC_REG_RCN_GAI_LVL__W 4 11800#define B_EC_OC_REG_RCN_GAI_LVL__W 4
13494#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF 11801#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF
13495#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA 11802#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA
13496 11803
13497
13498#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E 11804#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E
13499#define B_EC_OC_REG_RCN_DRA_LOP__W 16 11805#define B_EC_OC_REG_RCN_DRA_LOP__W 16
13500#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF 11806#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF
@@ -13516,13 +11822,11 @@ extern "C" {
13516#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF 11822#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF
13517#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 11823#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0
13518 11824
13519
13520#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 11825#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033
13521#define B_EC_OC_REG_RCN_CLP_HIP__W 8 11826#define B_EC_OC_REG_RCN_CLP_HIP__W 8
13522#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF 11827#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF
13523#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 11828#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0
13524 11829
13525
13526#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 11830#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034
13527#define B_EC_OC_REG_RCN_MAP_LOP__W 16 11831#define B_EC_OC_REG_RCN_MAP_LOP__W 16
13528#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF 11832#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF
@@ -13608,7 +11912,6 @@ extern "C" {
13608#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 11912#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0
13609#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 11913#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800
13610 11914
13611
13612#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 11915#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037
13613#define B_EC_OC_REG_OCR_MPG_WRI__W 12 11916#define B_EC_OC_REG_OCR_MPG_WRI__W 12
13614#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF 11917#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF
@@ -13674,7 +11977,6 @@ extern "C" {
13674#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 11977#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0
13675#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 11978#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800
13676 11979
13677
13678#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 11980#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
13679#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 11981#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12
13680#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF 11982#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF
@@ -13684,13 +11986,11 @@ extern "C" {
13684#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF 11986#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF
13685#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 11987#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0
13686 11988
13687
13688#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D 11989#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D
13689#define B_EC_OC_REG_OCR_MON_RDX__W 1 11990#define B_EC_OC_REG_OCR_MON_RDX__W 1
13690#define B_EC_OC_REG_OCR_MON_RDX__M 0x1 11991#define B_EC_OC_REG_OCR_MON_RDX__M 0x1
13691#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 11992#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0
13692 11993
13693
13694#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E 11994#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E
13695#define B_EC_OC_REG_OCR_MON_RD0__W 10 11995#define B_EC_OC_REG_OCR_MON_RD0__W 10
13696#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF 11996#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF
@@ -13720,19 +12020,16 @@ extern "C" {
13720#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF 12020#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF
13721#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 12021#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0
13722 12022
13723
13724#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 12023#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045
13725#define B_EC_OC_REG_IPR_INV_MPG__W 12 12024#define B_EC_OC_REG_IPR_INV_MPG__W 12
13726#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF 12025#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF
13727#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 12026#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0
13728 12027
13729
13730#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 12028#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046
13731#define B_EC_OC_REG_IPR_MSR_SNC__W 6 12029#define B_EC_OC_REG_IPR_MSR_SNC__W 6
13732#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F 12030#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F
13733#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 12031#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0
13734 12032
13735
13736#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 12033#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047
13737#define B_EC_OC_REG_DTO_CLKMODE__W 2 12034#define B_EC_OC_REG_DTO_CLKMODE__W 2
13738#define B_EC_OC_REG_DTO_CLKMODE__M 0x3 12035#define B_EC_OC_REG_DTO_CLKMODE__M 0x3
@@ -13750,13 +12047,11 @@ extern "C" {
13750#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 12047#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0
13751#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 12048#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2
13752 12049
13753
13754#define B_EC_OC_REG_DTO_PER__A 0x2150048 12050#define B_EC_OC_REG_DTO_PER__A 0x2150048
13755#define B_EC_OC_REG_DTO_PER__W 8 12051#define B_EC_OC_REG_DTO_PER__W 8
13756#define B_EC_OC_REG_DTO_PER__M 0xFF 12052#define B_EC_OC_REG_DTO_PER__M 0xFF
13757#define B_EC_OC_REG_DTO_PER_INIT 0x6 12053#define B_EC_OC_REG_DTO_PER_INIT 0x6
13758 12054
13759
13760#define B_EC_OC_REG_DTO_BUR__A 0x2150049 12055#define B_EC_OC_REG_DTO_BUR__A 0x2150049
13761#define B_EC_OC_REG_DTO_BUR__W 2 12056#define B_EC_OC_REG_DTO_BUR__W 2
13762#define B_EC_OC_REG_DTO_BUR__M 0x3 12057#define B_EC_OC_REG_DTO_BUR__M 0x3
@@ -13766,7 +12061,6 @@ extern "C" {
13766#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 12061#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2
13767#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 12062#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3
13768 12063
13769
13770#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A 12064#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A
13771#define B_EC_OC_REG_RCR_CLKMODE__W 3 12065#define B_EC_OC_REG_RCR_CLKMODE__W 3
13772#define B_EC_OC_REG_RCR_CLKMODE__M 0x7 12066#define B_EC_OC_REG_RCR_CLKMODE__M 0x7
@@ -13790,20 +12084,10 @@ extern "C" {
13790#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 12084#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0
13791#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 12085#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4
13792 12086
13793
13794
13795#define B_EC_OC_RAM__A 0x2160000 12087#define B_EC_OC_RAM__A 0x2160000
13796 12088
13797
13798
13799
13800
13801#define B_CC_SID 0x1B 12089#define B_CC_SID 0x1B
13802 12090
13803
13804
13805
13806
13807#define B_CC_COMM_EXEC__A 0x2400000 12091#define B_CC_COMM_EXEC__A 0x2400000
13808#define B_CC_COMM_EXEC__W 3 12092#define B_CC_COMM_EXEC__W 3
13809#define B_CC_COMM_EXEC__M 0x7 12093#define B_CC_COMM_EXEC__M 0x7
@@ -13836,12 +12120,6 @@ extern "C" {
13836#define B_CC_COMM_INT_MSK__W 16 12120#define B_CC_COMM_INT_MSK__W 16
13837#define B_CC_COMM_INT_MSK__M 0xFFFF 12121#define B_CC_COMM_INT_MSK__M 0xFFFF
13838 12122
13839
13840
13841
13842
13843
13844
13845#define B_CC_REG_COMM_EXEC__A 0x2410000 12123#define B_CC_REG_COMM_EXEC__A 0x2410000
13846#define B_CC_REG_COMM_EXEC__W 3 12124#define B_CC_REG_COMM_EXEC__W 3
13847#define B_CC_REG_COMM_EXEC__M 0x7 12125#define B_CC_REG_COMM_EXEC__M 0x7
@@ -13881,7 +12159,6 @@ extern "C" {
13881#define B_CC_REG_OSC_MODE_M20 0x1 12159#define B_CC_REG_OSC_MODE_M20 0x1
13882#define B_CC_REG_OSC_MODE_M48 0x2 12160#define B_CC_REG_OSC_MODE_M48 0x2
13883 12161
13884
13885#define B_CC_REG_PLL_MODE__A 0x2410011 12162#define B_CC_REG_PLL_MODE__A 0x2410011
13886#define B_CC_REG_PLL_MODE__W 6 12163#define B_CC_REG_PLL_MODE__W 6
13887#define B_CC_REG_PLL_MODE__M 0x3F 12164#define B_CC_REG_PLL_MODE__M 0x3F
@@ -13907,7 +12184,6 @@ extern "C" {
13907#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 12184#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0
13908#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 12185#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20
13909 12186
13910
13911#define B_CC_REG_REF_DIVIDE__A 0x2410012 12187#define B_CC_REG_REF_DIVIDE__A 0x2410012
13912#define B_CC_REG_REF_DIVIDE__W 4 12188#define B_CC_REG_REF_DIVIDE__W 4
13913#define B_CC_REG_REF_DIVIDE__M 0xF 12189#define B_CC_REG_REF_DIVIDE__M 0xF
@@ -13924,7 +12200,6 @@ extern "C" {
13924#define B_CC_REG_REF_DIVIDE_D09 0x9 12200#define B_CC_REG_REF_DIVIDE_D09 0x9
13925#define B_CC_REG_REF_DIVIDE_D10 0xA 12201#define B_CC_REG_REF_DIVIDE_D10 0xA
13926 12202
13927
13928#define B_CC_REG_REF_DELAY__A 0x2410013 12203#define B_CC_REG_REF_DELAY__A 0x2410013
13929#define B_CC_REG_REF_DELAY__W 3 12204#define B_CC_REG_REF_DELAY__W 3
13930#define B_CC_REG_REF_DELAY__M 0x7 12205#define B_CC_REG_REF_DELAY__M 0x7
@@ -13941,7 +12216,6 @@ extern "C" {
13941#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 12216#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4
13942#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 12217#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6
13943 12218
13944
13945#define B_CC_REG_CLK_DELAY__A 0x2410014 12219#define B_CC_REG_CLK_DELAY__A 0x2410014
13946#define B_CC_REG_CLK_DELAY__W 5 12220#define B_CC_REG_CLK_DELAY__W 5
13947#define B_CC_REG_CLK_DELAY__M 0x1F 12221#define B_CC_REG_CLK_DELAY__M 0x1F
@@ -13970,7 +12244,6 @@ extern "C" {
13970#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 12244#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0
13971#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 12245#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10
13972 12246
13973
13974#define B_CC_REG_PWD_MODE__A 0x2410015 12247#define B_CC_REG_PWD_MODE__A 0x2410015
13975#define B_CC_REG_PWD_MODE__W 2 12248#define B_CC_REG_PWD_MODE__W 2
13976#define B_CC_REG_PWD_MODE__M 0x3 12249#define B_CC_REG_PWD_MODE__M 0x3
@@ -13979,7 +12252,6 @@ extern "C" {
13979#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 12252#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2
13980#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 12253#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3
13981 12254
13982
13983#define B_CC_REG_SOFT_RST__A 0x2410016 12255#define B_CC_REG_SOFT_RST__A 0x2410016
13984#define B_CC_REG_SOFT_RST__W 2 12256#define B_CC_REG_SOFT_RST__W 2
13985#define B_CC_REG_SOFT_RST__M 0x3 12257#define B_CC_REG_SOFT_RST__M 0x3
@@ -13990,76 +12262,58 @@ extern "C" {
13990#define B_CC_REG_SOFT_RST_OSC__W 1 12262#define B_CC_REG_SOFT_RST_OSC__W 1
13991#define B_CC_REG_SOFT_RST_OSC__M 0x2 12263#define B_CC_REG_SOFT_RST_OSC__M 0x2
13992 12264
13993
13994#define B_CC_REG_UPDATE__A 0x2410017 12265#define B_CC_REG_UPDATE__A 0x2410017
13995#define B_CC_REG_UPDATE__W 16 12266#define B_CC_REG_UPDATE__W 16
13996#define B_CC_REG_UPDATE__M 0xFFFF 12267#define B_CC_REG_UPDATE__M 0xFFFF
13997#define B_CC_REG_UPDATE_KEY 0x3973 12268#define B_CC_REG_UPDATE_KEY 0x3973
13998 12269
13999
14000#define B_CC_REG_PLL_LOCK__A 0x2410018 12270#define B_CC_REG_PLL_LOCK__A 0x2410018
14001#define B_CC_REG_PLL_LOCK__W 1 12271#define B_CC_REG_PLL_LOCK__W 1
14002#define B_CC_REG_PLL_LOCK__M 0x1 12272#define B_CC_REG_PLL_LOCK__M 0x1
14003#define B_CC_REG_PLL_LOCK_LOCK 0x1 12273#define B_CC_REG_PLL_LOCK_LOCK 0x1
14004 12274
14005
14006#define B_CC_REG_JTAGID_L__A 0x2410019 12275#define B_CC_REG_JTAGID_L__A 0x2410019
14007#define B_CC_REG_JTAGID_L__W 16 12276#define B_CC_REG_JTAGID_L__W 16
14008#define B_CC_REG_JTAGID_L__M 0xFFFF 12277#define B_CC_REG_JTAGID_L__M 0xFFFF
14009#define B_CC_REG_JTAGID_L_INIT 0x0 12278#define B_CC_REG_JTAGID_L_INIT 0x0
14010 12279
14011
14012#define B_CC_REG_JTAGID_H__A 0x241001A 12280#define B_CC_REG_JTAGID_H__A 0x241001A
14013#define B_CC_REG_JTAGID_H__W 16 12281#define B_CC_REG_JTAGID_H__W 16
14014#define B_CC_REG_JTAGID_H__M 0xFFFF 12282#define B_CC_REG_JTAGID_H__M 0xFFFF
14015#define B_CC_REG_JTAGID_H_INIT 0x0 12283#define B_CC_REG_JTAGID_H_INIT 0x0
14016 12284
14017
14018#define B_CC_REG_DIVERSITY__A 0x241001B 12285#define B_CC_REG_DIVERSITY__A 0x241001B
14019#define B_CC_REG_DIVERSITY__W 1 12286#define B_CC_REG_DIVERSITY__W 1
14020#define B_CC_REG_DIVERSITY__M 0x1 12287#define B_CC_REG_DIVERSITY__M 0x1
14021#define B_CC_REG_DIVERSITY_INIT 0x0 12288#define B_CC_REG_DIVERSITY_INIT 0x0
14022 12289
14023
14024#define B_CC_REG_BACKUP3V__A 0x241001C 12290#define B_CC_REG_BACKUP3V__A 0x241001C
14025#define B_CC_REG_BACKUP3V__W 1 12291#define B_CC_REG_BACKUP3V__W 1
14026#define B_CC_REG_BACKUP3V__M 0x1 12292#define B_CC_REG_BACKUP3V__M 0x1
14027#define B_CC_REG_BACKUP3V_INIT 0x0 12293#define B_CC_REG_BACKUP3V_INIT 0x0
14028 12294
14029
14030#define B_CC_REG_DRV_IO__A 0x241001D 12295#define B_CC_REG_DRV_IO__A 0x241001D
14031#define B_CC_REG_DRV_IO__W 3 12296#define B_CC_REG_DRV_IO__W 3
14032#define B_CC_REG_DRV_IO__M 0x7 12297#define B_CC_REG_DRV_IO__M 0x7
14033#define B_CC_REG_DRV_IO_INIT 0x2 12298#define B_CC_REG_DRV_IO_INIT 0x2
14034 12299
14035
14036#define B_CC_REG_DRV_MPG__A 0x241001E 12300#define B_CC_REG_DRV_MPG__A 0x241001E
14037#define B_CC_REG_DRV_MPG__W 3 12301#define B_CC_REG_DRV_MPG__W 3
14038#define B_CC_REG_DRV_MPG__M 0x7 12302#define B_CC_REG_DRV_MPG__M 0x7
14039#define B_CC_REG_DRV_MPG_INIT 0x2 12303#define B_CC_REG_DRV_MPG_INIT 0x2
14040 12304
14041
14042#define B_CC_REG_DRV_I2C1__A 0x241001F 12305#define B_CC_REG_DRV_I2C1__A 0x241001F
14043#define B_CC_REG_DRV_I2C1__W 3 12306#define B_CC_REG_DRV_I2C1__W 3
14044#define B_CC_REG_DRV_I2C1__M 0x7 12307#define B_CC_REG_DRV_I2C1__M 0x7
14045#define B_CC_REG_DRV_I2C1_INIT 0x2 12308#define B_CC_REG_DRV_I2C1_INIT 0x2
14046 12309
14047
14048#define B_CC_REG_DRV_I2C2__A 0x2410020 12310#define B_CC_REG_DRV_I2C2__A 0x2410020
14049#define B_CC_REG_DRV_I2C2__W 1 12311#define B_CC_REG_DRV_I2C2__W 1
14050#define B_CC_REG_DRV_I2C2__M 0x1 12312#define B_CC_REG_DRV_I2C2__M 0x1
14051#define B_CC_REG_DRV_I2C2_INIT 0x0 12313#define B_CC_REG_DRV_I2C2_INIT 0x0
14052 12314
14053
14054
14055
14056
14057#define B_LC_SID 0x1C 12315#define B_LC_SID 0x1C
14058 12316
14059
14060
14061
14062
14063#define B_LC_COMM_EXEC__A 0x2800000 12317#define B_LC_COMM_EXEC__A 0x2800000
14064#define B_LC_COMM_EXEC__W 3 12318#define B_LC_COMM_EXEC__W 3
14065#define B_LC_COMM_EXEC__M 0x7 12319#define B_LC_COMM_EXEC__M 0x7
@@ -14092,11 +12346,6 @@ extern "C" {
14092#define B_LC_COMM_INT_MSK__W 16 12346#define B_LC_COMM_INT_MSK__W 16
14093#define B_LC_COMM_INT_MSK__M 0xFFFF 12347#define B_LC_COMM_INT_MSK__M 0xFFFF
14094 12348
14095
14096
14097
14098
14099
14100#define B_LC_CT_REG_COMM_EXEC__A 0x2810000 12349#define B_LC_CT_REG_COMM_EXEC__A 0x2810000
14101#define B_LC_CT_REG_COMM_EXEC__W 3 12350#define B_LC_CT_REG_COMM_EXEC__W 3
14102#define B_LC_CT_REG_COMM_EXEC__M 0x7 12351#define B_LC_CT_REG_COMM_EXEC__M 0x7
@@ -14108,7 +12357,6 @@ extern "C" {
14108#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 12357#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
14109#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 12358#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3
14110 12359
14111
14112#define B_LC_CT_REG_COMM_STATE__A 0x2810001 12360#define B_LC_CT_REG_COMM_STATE__A 0x2810001
14113#define B_LC_CT_REG_COMM_STATE__W 10 12361#define B_LC_CT_REG_COMM_STATE__W 10
14114#define B_LC_CT_REG_COMM_STATE__M 0x3FF 12362#define B_LC_CT_REG_COMM_STATE__M 0x3FF
@@ -14122,7 +12370,6 @@ extern "C" {
14122#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 12370#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1
14123#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 12371#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000
14124 12372
14125
14126#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 12373#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007
14127#define B_LC_CT_REG_COMM_INT_STA__W 1 12374#define B_LC_CT_REG_COMM_INT_STA__W 1
14128#define B_LC_CT_REG_COMM_INT_STA__M 0x1 12375#define B_LC_CT_REG_COMM_INT_STA__M 0x1
@@ -14130,7 +12377,6 @@ extern "C" {
14130#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 12377#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1
14131#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 12378#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
14132 12379
14133
14134#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 12380#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008
14135#define B_LC_CT_REG_COMM_INT_MSK__W 1 12381#define B_LC_CT_REG_COMM_INT_MSK__W 1
14136#define B_LC_CT_REG_COMM_INT_MSK__M 0x1 12382#define B_LC_CT_REG_COMM_INT_MSK__M 0x1
@@ -14138,9 +12384,6 @@ extern "C" {
14138#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 12384#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1
14139#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 12385#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
14140 12386
14141
14142
14143
14144#define B_LC_CT_REG_CTL_STK__AX 0x2810010 12387#define B_LC_CT_REG_CTL_STK__AX 0x2810010
14145#define B_LC_CT_REG_CTL_STK__XSZ 4 12388#define B_LC_CT_REG_CTL_STK__XSZ 4
14146#define B_LC_CT_REG_CTL_STK__W 10 12389#define B_LC_CT_REG_CTL_STK__W 10
@@ -14154,10 +12397,6 @@ extern "C" {
14154#define B_LC_CT_REG_CTL_BPT__W 10 12397#define B_LC_CT_REG_CTL_BPT__W 10
14155#define B_LC_CT_REG_CTL_BPT__M 0x3FF 12398#define B_LC_CT_REG_CTL_BPT__M 0x3FF
14156 12399
14157
14158
14159
14160
14161#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 12400#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006
14162#define B_LC_RA_RAM_PROC_DELAY_IF__W 16 12401#define B_LC_RA_RAM_PROC_DELAY_IF__W 16
14163#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF 12402#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF
@@ -14296,10 +12535,6 @@ extern "C" {
14296#define B_LC_RA_RAM_ADJUST_DELAY__W 16 12535#define B_LC_RA_RAM_ADJUST_DELAY__W 16
14297#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF 12536#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF
14298 12537
14299
14300
14301
14302
14303#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 12538#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028
14304#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 12539#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16
14305#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF 12540#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF
@@ -14319,8 +12554,6 @@ extern "C" {
14319#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 12554#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16
14320#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF 12555#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF
14321 12556
14322
14323
14324#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 12557#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030
14325#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 12558#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16
14326#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF 12559#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF
@@ -14340,8 +12573,6 @@ extern "C" {
14340#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 12573#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16
14341#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF 12574#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF
14342 12575
14343
14344
14345#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 12576#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038
14346#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 12577#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16
14347#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF 12578#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF
@@ -14361,10 +12592,6 @@ extern "C" {
14361#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 12592#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16
14362#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF 12593#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF
14363 12594
14364
14365
14366
14367
14368#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 12595#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
14369#define B_LC_RA_RAM_FILTER_CRMM_A__W 16 12596#define B_LC_RA_RAM_FILTER_CRMM_A__W 16
14370#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF 12597#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF
@@ -14386,8 +12613,6 @@ extern "C" {
14386#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 12613#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16
14387#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF 12614#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF
14388 12615
14389
14390
14391#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 12616#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
14392#define B_LC_RA_RAM_FILTER_SRMM_A__W 16 12617#define B_LC_RA_RAM_FILTER_SRMM_A__W 16
14393#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF 12618#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF
@@ -14409,8 +12634,6 @@ extern "C" {
14409#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 12634#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16
14410#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF 12635#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF
14411 12636
14412
14413
14414#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 12637#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070
14415#define B_LC_RA_RAM_FILTER_PHASE_A__W 16 12638#define B_LC_RA_RAM_FILTER_PHASE_A__W 16
14416#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF 12639#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF
@@ -14432,8 +12655,6 @@ extern "C" {
14432#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 12655#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16
14433#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF 12656#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF
14434 12657
14435
14436
14437#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 12658#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078
14438#define B_LC_RA_RAM_FILTER_DELAY_A__W 16 12659#define B_LC_RA_RAM_FILTER_DELAY_A__W 16
14439#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF 12660#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF
@@ -14455,11 +12676,6 @@ extern "C" {
14455#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 12676#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16
14456#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF 12677#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF
14457 12678
14458
14459
14460
14461
14462
14463#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 12679#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000
14464#define B_LC_IF_RAM_TRP_BPT0__XSZ 2 12680#define B_LC_IF_RAM_TRP_BPT0__XSZ 2
14465#define B_LC_IF_RAM_TRP_BPT0__W 12 12681#define B_LC_IF_RAM_TRP_BPT0__W 12
@@ -14475,10 +12691,4 @@ extern "C" {
14475#define B_LC_IF_RAM_TRP_WARM__W 12 12691#define B_LC_IF_RAM_TRP_WARM__W 12
14476#define B_LC_IF_RAM_TRP_WARM__M 0xFFF 12692#define B_LC_IF_RAM_TRP_WARM__M 0xFFF
14477 12693
14478#ifdef __cplusplus
14479}
14480#endif
14481
14482#endif 12694#endif
14483
14484
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 06:20:04 -0400