diff options
Diffstat (limited to 'drivers/media/dvb/frontends/drxd_firm.h')
-rw-r--r-- | drivers/media/dvb/frontends/drxd_firm.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h index fa704cbf766..367930a1142 100644 --- a/drivers/media/dvb/frontends/drxd_firm.h +++ b/drivers/media/dvb/frontends/drxd_firm.h | |||
@@ -40,7 +40,7 @@ typedef unsigned long u32_t; | |||
40 | #define HI_I2C_DELAY 84 | 40 | #define HI_I2C_DELAY 84 |
41 | #define HI_I2C_BRIDGE_DELAY 750 | 41 | #define HI_I2C_BRIDGE_DELAY 750 |
42 | 42 | ||
43 | #define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ | 43 | #define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ |
44 | #define EQ_TD_TPS_PWR_QPSK 0x016a | 44 | #define EQ_TD_TPS_PWR_QPSK 0x016a |
45 | #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 | 45 | #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 |
46 | #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 | 46 | #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 |
@@ -65,7 +65,6 @@ typedef unsigned long u32_t; | |||
65 | 65 | ||
66 | #define DRXD_SCAN_TIMEOUT (650) | 66 | #define DRXD_SCAN_TIMEOUT (650) |
67 | 67 | ||
68 | |||
69 | #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) | 68 | #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) |
70 | #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) | 69 | #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) |
71 | #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) | 70 | #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) |
@@ -78,7 +77,6 @@ typedef unsigned long u32_t; | |||
78 | #define DIFF_TARGET (4) | 77 | #define DIFF_TARGET (4) |
79 | #define DIFF_MARGIN (1) | 78 | #define DIFF_MARGIN (1) |
80 | 79 | ||
81 | |||
82 | extern u8_t DRXD_InitAtomicRead[]; | 80 | extern u8_t DRXD_InitAtomicRead[]; |
83 | extern u8_t DRXD_HiI2cPatch_1[]; | 81 | extern u8_t DRXD_HiI2cPatch_1[]; |
84 | extern u8_t DRXD_HiI2cPatch_3[]; | 82 | extern u8_t DRXD_HiI2cPatch_3[]; |
@@ -95,7 +93,7 @@ extern u8_t DRXD_InitECA2[]; | |||
95 | extern u8_t DRXD_ResetECA2[]; | 93 | extern u8_t DRXD_ResetECA2[]; |
96 | extern u8_t DRXD_ResetECRAM[]; | 94 | extern u8_t DRXD_ResetECRAM[]; |
97 | 95 | ||
98 | extern u8_t DRXD_A2_microcode[]; | 96 | extern u8_t DRXD_A2_microcode[]; |
99 | extern u32_t DRXD_A2_microcode_length; | 97 | extern u32_t DRXD_A2_microcode_length; |
100 | 98 | ||
101 | extern u8_t DRXD_InitFEB1_1[]; | 99 | extern u8_t DRXD_InitFEB1_1[]; |
@@ -114,7 +112,7 @@ extern u8_t DRXD_StartDiversityEnd[]; | |||
114 | extern u8_t DRXD_DiversityDelay8MHZ[]; | 112 | extern u8_t DRXD_DiversityDelay8MHZ[]; |
115 | extern u8_t DRXD_DiversityDelay6MHZ[]; | 113 | extern u8_t DRXD_DiversityDelay6MHZ[]; |
116 | 114 | ||
117 | extern u8_t DRXD_B1_microcode[]; | 115 | extern u8_t DRXD_B1_microcode[]; |
118 | extern u32_t DRXD_B1_microcode_length; | 116 | extern u32_t DRXD_B1_microcode_length; |
119 | 117 | ||
120 | #endif | 118 | #endif |