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authorNicolas Kaiser <nikai@nikai.net>2010-07-11 19:46:57 -0400
committerDave Airlie <airlied@redhat.com>2010-08-01 20:17:36 -0400
commitf2b2cb790ee873b6853ec99478d68dd9cd083132 (patch)
tree3a81896018631229ae130a038904180155efd89b /drivers/gpu/drm/mga/mga_drv.h
parent58c1e85af3645ac8df021dbf14acd215b5687f54 (diff)
drm/mga: fixed brace, macro and spacing coding style issues
Fixed brace, macro and spacing coding style issues. Signed-off-by: Nicolas Kaiser <nikai@nikai.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/mga/mga_drv.h')
-rw-r--r--drivers/gpu/drm/mga/mga_drv.h187
1 files changed, 91 insertions, 96 deletions
diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h
index be6c6b9b0e8..1084fa4d261 100644
--- a/drivers/gpu/drm/mga/mga_drv.h
+++ b/drivers/gpu/drm/mga/mga_drv.h
@@ -164,59 +164,59 @@ extern int mga_dma_reset(struct drm_device *dev, void *data,
164extern int mga_dma_buffers(struct drm_device *dev, void *data, 164extern int mga_dma_buffers(struct drm_device *dev, void *data,
165 struct drm_file *file_priv); 165 struct drm_file *file_priv);
166extern int mga_driver_load(struct drm_device *dev, unsigned long flags); 166extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
167extern int mga_driver_unload(struct drm_device * dev); 167extern int mga_driver_unload(struct drm_device *dev);
168extern void mga_driver_lastclose(struct drm_device * dev); 168extern void mga_driver_lastclose(struct drm_device *dev);
169extern int mga_driver_dma_quiescent(struct drm_device * dev); 169extern int mga_driver_dma_quiescent(struct drm_device *dev);
170 170
171extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); 171extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
172 172
173extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); 173extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
174extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); 174extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
175extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); 175extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
176 176
177extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); 177extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
178 178
179 /* mga_warp.c */ 179 /* mga_warp.c */
180extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); 180extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
181extern int mga_warp_init(drm_mga_private_t * dev_priv); 181extern int mga_warp_init(drm_mga_private_t *dev_priv);
182 182
183 /* mga_irq.c */ 183 /* mga_irq.c */
184extern int mga_enable_vblank(struct drm_device *dev, int crtc); 184extern int mga_enable_vblank(struct drm_device *dev, int crtc);
185extern void mga_disable_vblank(struct drm_device *dev, int crtc); 185extern void mga_disable_vblank(struct drm_device *dev, int crtc);
186extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc); 186extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc);
187extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence); 187extern int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
188extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); 188extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
189extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); 189extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
190extern void mga_driver_irq_preinstall(struct drm_device * dev); 190extern void mga_driver_irq_preinstall(struct drm_device *dev);
191extern int mga_driver_irq_postinstall(struct drm_device *dev); 191extern int mga_driver_irq_postinstall(struct drm_device *dev);
192extern void mga_driver_irq_uninstall(struct drm_device * dev); 192extern void mga_driver_irq_uninstall(struct drm_device *dev);
193extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, 193extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
194 unsigned long arg); 194 unsigned long arg);
195 195
196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
197 197
198#if defined(__linux__) && defined(__alpha__) 198#if defined(__linux__) && defined(__alpha__)
199#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 199#define MGA_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
200#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 200#define MGA_ADDR(reg) (MGA_BASE(reg) + reg)
201 201
202#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 202#define MGA_DEREF(reg) (*(volatile u32 *)MGA_ADDR(reg))
203#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 203#define MGA_DEREF8(reg) (*(volatile u8 *)MGA_ADDR(reg))
204 204
205#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 205#define MGA_READ(reg) (_MGA_READ((u32 *)MGA_ADDR(reg)))
206#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) 206#define MGA_READ8(reg) (_MGA_READ((u8 *)MGA_ADDR(reg)))
207#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 207#define MGA_WRITE(reg, val) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF(reg) = val; } while (0)
208#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 208#define MGA_WRITE8(reg, val) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8(reg) = val; } while (0)
209 209
210static inline u32 _MGA_READ(u32 * addr) 210static inline u32 _MGA_READ(u32 *addr)
211{ 211{
212 DRM_MEMORYBARRIER(); 212 DRM_MEMORYBARRIER();
213 return *(volatile u32 *)addr; 213 return *(volatile u32 *)addr;
214} 214}
215#else 215#else
216#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 216#define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
217#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 217#define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
218#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 218#define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
219#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 219#define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
220#endif 220#endif
221 221
222#define DWGREG0 0x1c00 222#define DWGREG0 0x1c00
@@ -233,40 +233,39 @@ static inline u32 _MGA_READ(u32 * addr)
233 * Helper macross... 233 * Helper macross...
234 */ 234 */
235 235
236#define MGA_EMIT_STATE( dev_priv, dirty ) \ 236#define MGA_EMIT_STATE(dev_priv, dirty) \
237do { \ 237do { \
238 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 238 if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
239 if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \ 239 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
240 mga_g400_emit_state( dev_priv ); \ 240 mga_g400_emit_state(dev_priv); \
241 } else { \ 241 else \
242 mga_g200_emit_state( dev_priv ); \ 242 mga_g200_emit_state(dev_priv); \
243 } \
244 } \ 243 } \
245} while (0) 244} while (0)
246 245
247#define WRAP_TEST_WITH_RETURN( dev_priv ) \ 246#define WRAP_TEST_WITH_RETURN(dev_priv) \
248do { \ 247do { \
249 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 248 if (test_bit(0, &dev_priv->prim.wrapped)) { \
250 if ( mga_is_idle( dev_priv ) ) { \ 249 if (mga_is_idle(dev_priv)) { \
251 mga_do_dma_wrap_end( dev_priv ); \ 250 mga_do_dma_wrap_end(dev_priv); \
252 } else if ( dev_priv->prim.space < \ 251 } else if (dev_priv->prim.space < \
253 dev_priv->prim.high_mark ) { \ 252 dev_priv->prim.high_mark) { \
254 if ( MGA_DMA_DEBUG ) \ 253 if (MGA_DMA_DEBUG) \
255 DRM_INFO( "wrap...\n"); \ 254 DRM_INFO("wrap...\n"); \
256 return -EBUSY; \ 255 return -EBUSY; \
257 } \ 256 } \
258 } \ 257 } \
259} while (0) 258} while (0)
260 259
261#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 260#define WRAP_WAIT_WITH_RETURN(dev_priv) \
262do { \ 261do { \
263 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 262 if (test_bit(0, &dev_priv->prim.wrapped)) { \
264 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ 263 if (mga_do_wait_for_idle(dev_priv) < 0) { \
265 if ( MGA_DMA_DEBUG ) \ 264 if (MGA_DMA_DEBUG) \
266 DRM_INFO( "wrap...\n"); \ 265 DRM_INFO("wrap...\n"); \
267 return -EBUSY; \ 266 return -EBUSY; \
268 } \ 267 } \
269 mga_do_dma_wrap_end( dev_priv ); \ 268 mga_do_dma_wrap_end(dev_priv); \
270 } \ 269 } \
271} while (0) 270} while (0)
272 271
@@ -280,12 +279,12 @@ do { \
280 279
281#define DMA_BLOCK_SIZE (5 * sizeof(u32)) 280#define DMA_BLOCK_SIZE (5 * sizeof(u32))
282 281
283#define BEGIN_DMA( n ) \ 282#define BEGIN_DMA(n) \
284do { \ 283do { \
285 if ( MGA_VERBOSE ) { \ 284 if (MGA_VERBOSE) { \
286 DRM_INFO( "BEGIN_DMA( %d )\n", (n) ); \ 285 DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
287 DRM_INFO( " space=0x%x req=0x%Zx\n", \ 286 DRM_INFO(" space=0x%x req=0x%Zx\n", \
288 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 287 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
289 } \ 288 } \
290 prim = dev_priv->prim.start; \ 289 prim = dev_priv->prim.start; \
291 write = dev_priv->prim.tail; \ 290 write = dev_priv->prim.tail; \
@@ -293,9 +292,9 @@ do { \
293 292
294#define BEGIN_DMA_WRAP() \ 293#define BEGIN_DMA_WRAP() \
295do { \ 294do { \
296 if ( MGA_VERBOSE ) { \ 295 if (MGA_VERBOSE) { \
297 DRM_INFO( "BEGIN_DMA()\n" ); \ 296 DRM_INFO("BEGIN_DMA()\n"); \
298 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 297 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
299 } \ 298 } \
300 prim = dev_priv->prim.start; \ 299 prim = dev_priv->prim.start; \
301 write = dev_priv->prim.tail; \ 300 write = dev_priv->prim.tail; \
@@ -304,72 +303,68 @@ do { \
304#define ADVANCE_DMA() \ 303#define ADVANCE_DMA() \
305do { \ 304do { \
306 dev_priv->prim.tail = write; \ 305 dev_priv->prim.tail = write; \
307 if ( MGA_VERBOSE ) { \ 306 if (MGA_VERBOSE) \
308 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 307 DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
309 write, dev_priv->prim.space ); \ 308 write, dev_priv->prim.space); \
310 } \
311} while (0) 309} while (0)
312 310
313#define FLUSH_DMA() \ 311#define FLUSH_DMA() \
314do { \ 312do { \
315 if ( 0 ) { \ 313 if (0) { \
316 DRM_INFO( "\n" ); \ 314 DRM_INFO("\n"); \
317 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 315 DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
318 dev_priv->prim.tail, \ 316 dev_priv->prim.tail, \
319 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \ 317 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
320 dev_priv->primary->offset)); \ 318 dev_priv->primary->offset)); \
321 } \ 319 } \
322 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 320 if (!test_bit(0, &dev_priv->prim.wrapped)) { \
323 if ( dev_priv->prim.space < \ 321 if (dev_priv->prim.space < dev_priv->prim.high_mark) \
324 dev_priv->prim.high_mark ) { \ 322 mga_do_dma_wrap_start(dev_priv); \
325 mga_do_dma_wrap_start( dev_priv ); \ 323 else \
326 } else { \ 324 mga_do_dma_flush(dev_priv); \
327 mga_do_dma_flush( dev_priv ); \
328 } \
329 } \ 325 } \
330} while (0) 326} while (0)
331 327
332/* Never use this, always use DMA_BLOCK(...) for primary DMA output. 328/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
333 */ 329 */
334#define DMA_WRITE( offset, val ) \ 330#define DMA_WRITE(offset, val) \
335do { \ 331do { \
336 if ( MGA_VERBOSE ) { \ 332 if (MGA_VERBOSE) \
337 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ 333 DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
338 (u32)(val), write + (offset) * sizeof(u32) ); \ 334 (u32)(val), write + (offset) * sizeof(u32)); \
339 } \
340 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 335 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
341} while (0) 336} while (0)
342 337
343#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 338#define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
344do { \ 339do { \
345 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 340 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
346 (DMAREG( reg1 ) << 8) | \ 341 (DMAREG(reg1) << 8) | \
347 (DMAREG( reg2 ) << 16) | \ 342 (DMAREG(reg2) << 16) | \
348 (DMAREG( reg3 ) << 24)) ); \ 343 (DMAREG(reg3) << 24))); \
349 DMA_WRITE( 1, val0 ); \ 344 DMA_WRITE(1, val0); \
350 DMA_WRITE( 2, val1 ); \ 345 DMA_WRITE(2, val1); \
351 DMA_WRITE( 3, val2 ); \ 346 DMA_WRITE(3, val2); \
352 DMA_WRITE( 4, val3 ); \ 347 DMA_WRITE(4, val3); \
353 write += DMA_BLOCK_SIZE; \ 348 write += DMA_BLOCK_SIZE; \
354} while (0) 349} while (0)
355 350
356/* Buffer aging via primary DMA stream head pointer. 351/* Buffer aging via primary DMA stream head pointer.
357 */ 352 */
358 353
359#define SET_AGE( age, h, w ) \ 354#define SET_AGE(age, h, w) \
360do { \ 355do { \
361 (age)->head = h; \ 356 (age)->head = h; \
362 (age)->wrap = w; \ 357 (age)->wrap = w; \
363} while (0) 358} while (0)
364 359
365#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 360#define TEST_AGE(age, h, w) ((age)->wrap < w || \
366 ( (age)->wrap == w && \ 361 ((age)->wrap == w && \
367 (age)->head < h ) ) 362 (age)->head < h))
368 363
369#define AGE_BUFFER( buf_priv ) \ 364#define AGE_BUFFER(buf_priv) \
370do { \ 365do { \
371 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 366 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
372 if ( (buf_priv)->dispatched ) { \ 367 if ((buf_priv)->dispatched) { \
373 entry->age.head = (dev_priv->prim.tail + \ 368 entry->age.head = (dev_priv->prim.tail + \
374 dev_priv->primary->offset); \ 369 dev_priv->primary->offset); \
375 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 370 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
@@ -681,7 +676,7 @@ do { \
681 676
682/* Simple idle test. 677/* Simple idle test.
683 */ 678 */
684static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) 679static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
685{ 680{
686 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; 681 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
687 return (status == MGA_ENDPRDMASTS); 682 return (status == MGA_ENDPRDMASTS);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 14:57:24 -0400