Merge branch 'sh/nommu' into sh-latest

872 files changed, 30562 insertions, 12282 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 3d74801a401..56a4df952fb 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -70,10 +70,6 @@ config GENERIC_ISA_DMA
         bool
         default y
 
-config GENERIC_IOMAP
-        bool
-        default n
-
 source "init/Kconfig"
 source "kernel/Kconfig.freezer"
 
@@ -319,6 +315,7 @@ config ISA_DMA_API
 config PCI
         bool
         depends on !ALPHA_JENSEN
+        select GENERIC_PCI_IOMAP
         default y
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c
index 246100ef07c..04eea4894ef 100644
--- a/arch/alpha/kernel/pci-noop.c
+++ b/arch/alpha/kernel/pci-noop.c
@@ -185,15 +185,3 @@ struct dma_map_ops alpha_noop_ops = {
 
 struct dma_map_ops *dma_ops = &alpha_noop_ops;
 EXPORT_SYMBOL(dma_ops);
-
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        return NULL;
-}
-
-void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
-{
-}
-
-EXPORT_SYMBOL(pci_iomap);
-EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index c9ab94ee1ca..f3cae275d3f 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -508,30 +508,7 @@ sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
         return -EOPNOTSUPP;
 }
 
-/* Create an __iomem token from a PCI BAR.  Copied from lib/iomap.c with
-   no changes, since we don't want the other things in that object file.  */
-
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM) {
-                /* Not checking IORESOURCE_CACHEABLE because alpha does
-                   not distinguish between ioremap and ioremap_nocache.  */
-                return ioremap(start, len);
-        }
-        return NULL;
-}
-
-/* Destroy that token.  Not copied from lib/iomap.c.  */
+/* Destroy an __iomem token.  Not copied from lib/iomap.c.  */
 
 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
 {
@@ -539,7 +516,6 @@ void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
                 iounmap(addr);
 }
 
-EXPORT_SYMBOL(pci_iomap);
 EXPORT_SYMBOL(pci_iounmap);
 
 /* FIXME: Some boxes have multiple ISA bridges! */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f72e1707d46..24626b0419e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
+        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_LZO
@@ -30,6 +31,7 @@ config ARM
         select HAVE_SPARSE_IRQ
         select GENERIC_IRQ_SHOW
         select CPU_PM if (SUSPEND || CPU_IDLE)
+        select GENERIC_PCI_IOMAP
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -447,6 +449,7 @@ config ARCH_MXS
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
+        select HAVE_CLK_PREPARE
         help
           Support for Freescale MXS-based family of processors
 
@@ -597,6 +600,7 @@ config ARCH_MMP
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
+        select GPIO_PXA
         select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select PLAT_PXA
@@ -658,6 +662,7 @@ config ARCH_PICOXCELL
         select HAVE_SCHED_CLOCK
         select HAVE_TCM
         select NO_IOPORT
+        select SPARSE_IRQ
         select USE_OF
         help
           This enables support for systems based on the Picochip picoXcell
@@ -681,6 +686,7 @@ config ARCH_PXA
         select CLKSRC_MMIO
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
+        select GPIO_PXA
         select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select PLAT_PXA
@@ -748,7 +754,7 @@ config ARCH_SA1100
         select ARCH_HAS_CPUFREQ
         select CPU_FREQ
         select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
+        select CLKDEV_LOOKUP
         select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select ARCH_REQUIRE_GPIOLIB
@@ -892,7 +898,6 @@ config ARCH_U300
         select HAVE_MACH_CLKDEV
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
-        select NEED_MACH_MEMORY_H
         help
           Support for ST-Ericsson U300 series mobile platforms.
 
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index c5213e78606..e0d236d7ff7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -100,6 +100,14 @@ choice
                   Note that the system will appear to hang during boot if there
                   is nothing connected to read from the DCC.
 
+        config AT91_DEBUG_LL_DBGU0
+                bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
+                depends on HAVE_AT91_DBGU0
+
+        config AT91_DEBUG_LL_DBGU1
+                bool "Kernel low-level debugging on 9263, 9g45 and cap9"
+                depends on HAVE_AT91_DBGU1
+
         config DEBUG_FOOTBRIDGE_COM1
                 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
                 depends on FOOTBRIDGE
@@ -247,6 +255,43 @@ choice
                   their output to the standard serial port on the RealView
                   PB1176 platform.
 
+        config DEBUG_MSM_UART1
+                bool "Kernel low-level debugging messages via MSM UART1"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the first serial port on MSM devices.
+
+        config DEBUG_MSM_UART2
+                bool "Kernel low-level debugging messages via MSM UART2"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the second serial port on MSM devices.
+
+        config DEBUG_MSM_UART3
+                bool "Kernel low-level debugging messages via MSM UART3"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the third serial port on MSM devices.
+
+        config DEBUG_MSM8660_UART
+                bool "Kernel low-level debugging messages via MSM 8660 UART"
+                depends on ARCH_MSM8X60
+                select MSM_HAS_DEBUG_UART_HS
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on MSM 8660 devices.
+
+        config DEBUG_MSM8960_UART
+                bool "Kernel low-level debugging messages via MSM 8960 UART"
+                depends on ARCH_MSM8960
+                select MSM_HAS_DEBUG_UART_HS
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on MSM 8960 devices.
+
 endchoice
 
 config EARLY_PRINTK
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index aeef04269cf..07603b8c950 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -114,6 +114,13 @@
                                 atmel,use-dma-tx;
                                 status = "disabled";
                         };
+
+                        macb0: ethernet@fffc4000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffc4000 0x100>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index db6a45202f2..fffa005300a 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -101,6 +101,13 @@
                                 atmel,use-dma-tx;
                                 status = "disabled";
                         };
+
+                        macb0: ethernet@fffbc000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffbc000 0x100>;
+                                interrupts = <25>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 85b34f59cd8..a387e7704ce 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -30,6 +30,11 @@
                         usart1: serial@fff90000 {
                                 status = "okay";
                         };
+
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
new file mode 100644
index 00000000000..b8c476384ee
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -0,0 +1,137 @@
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4210";
+        compatible = "insignal,origen", "samsung,exynos4210";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
+        };
+
+        sdhci@12530000 {
+                samsung,sdhci-bus-width = <4>;
+                linux,mmc_cap_4_bit_data;
+                samsung,sdhci-cd-internal;
+                gpio-cd = <&gpk2 2 2 3 3>;
+                gpios = <&gpk2 0 2 0 3>,
+                        <&gpk2 1 2 0 3>,
+                        <&gpk2 3 2 3 3>,
+                        <&gpk2 4 2 3 3>,
+                        <&gpk2 5 2 3 3>,
+                        <&gpk2 6 2 3 3>;
+        };
+
+        sdhci@12510000 {
+                samsung,sdhci-bus-width = <4>;
+                linux,mmc_cap_4_bit_data;
+                samsung,sdhci-cd-internal;
+                gpio-cd = <&gpk0 2 2 3 3>;
+                gpios = <&gpk0 0 2 0 3>,
+                        <&gpk0 1 2 0 3>,
+                        <&gpk0 3 2 3 3>,
+                        <&gpk0 4 2 3 3>,
+                        <&gpk0 5 2 3 3>,
+                        <&gpk0 6 2 3 3>;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                up {
+                        label = "Up";
+                        gpios = <&gpx2 0 0 0 2>;
+                        linux,code = <103>;
+                };
+
+                down {
+                        label = "Down";
+                        gpios = <&gpx2 1 0 0 2>;
+                        linux,code = <108>;
+                };
+
+                back {
+                        label = "Back";
+                        gpios = <&gpx1 7 0 0 2>;
+                        linux,code = <158>;
+                };
+
+                home {
+                        label = "Home";
+                        gpios = <&gpx1 6 0 0 2>;
+                        linux,code = <102>;
+                };
+
+                menu {
+                        label = "Menu";
+                        gpios = <&gpx1 5 0 0 2>;
+                        linux,code = <139>;
+                };
+        };
+
+        keypad@100A0000 {
+                status = "disabled";
+        };
+
+        sdhci@12520000 {
+                status = "disabled";
+        };
+
+        sdhci@12540000 {
+                status = "disabled";
+        };
+
+        i2c@13860000 {
+                status = "disabled";
+        };
+
+        i2c@13870000 {
+                status = "disabled";
+        };
+
+        i2c@13880000 {
+                status = "disabled";
+        };
+
+        i2c@13890000 {
+                status = "disabled";
+        };
+
+        i2c@138A0000 {
+                status = "disabled";
+        };
+
+        i2c@138B0000 {
+                status = "disabled";
+        };
+
+        i2c@138C0000 {
+                status = "disabled";
+        };
+
+        i2c@138D0000 {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
new file mode 100644
index 00000000000..27afc8e535c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -0,0 +1,182 @@
+/*
+ * Samsung's Exynos4210 based SMDKV310 board device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Device tree source file for Samsung's SMDKV310 board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+
+/ {
+        model = "Samsung smdkv310 evaluation board based on Exynos4210";
+        compatible = "samsung,smdkv310", "samsung,exynos4210";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+        };
+
+        sdhci@12530000 {
+                samsung,sdhci-bus-width = <4>;
+                linux,mmc_cap_4_bit_data;
+                samsung,sdhci-cd-internal;
+                gpio-cd = <&gpk2 2 2 3 3>;
+                gpios = <&gpk2 0 2 0 3>,
+                        <&gpk2 1 2 0 3>,
+                        <&gpk2 3 2 3 3>,
+                        <&gpk2 4 2 3 3>,
+                        <&gpk2 5 2 3 3>,
+                        <&gpk2 6 2 3 3>;
+        };
+
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <2>;
+                samsung,keypad-num-columns = <8>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+
+                row-gpios = <&gpx2 0 3 3 0>,
+                            <&gpx2 1 3 3 0>;
+
+                col-gpios = <&gpx1 0 3 0 0>,
+                            <&gpx1 1 3 0 0>,
+                            <&gpx1 2 3 0 0>,
+                            <&gpx1 3 3 0 0>,
+                            <&gpx1 4 3 0 0>,
+                            <&gpx1 5 3 0 0>,
+                            <&gpx1 6 3 0 0>,
+                            <&gpx1 7 3 0 0>;
+
+                key_1 {
+                        keypad,row = <0>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+
+                key_2 {
+                        keypad,row = <0>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+
+                key_3 {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+
+                key_4 {
+                        keypad,row = <0>;
+                        keypad,column = <6>;
+                        linux,code = <5>;
+                };
+
+                key_5 {
+                        keypad,row = <0>;
+                        keypad,column = <7>;
+                        linux,code = <6>;
+                };
+
+                key_a {
+                        keypad,row = <1>;
+                        keypad,column = <3>;
+                        linux,code = <30>;
+                };
+
+                key_b {
+                        keypad,row = <1>;
+                        keypad,column = <4>;
+                        linux,code = <48>;
+                };
+
+                key_c {
+                        keypad,row = <1>;
+                        keypad,column = <5>;
+                        linux,code = <46>;
+                };
+
+                key_d {
+                        keypad,row = <1>;
+                        keypad,column = <6>;
+                        linux,code = <32>;
+                };
+
+                key_e {
+                        keypad,row = <1>;
+                        keypad,column = <7>;
+                        linux,code = <18>;
+                };
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                gpios = <&gpd1 0 2 3 0>,
+                        <&gpd1 1 2 3 0>;
+
+                eeprom@50 {
+                        compatible = "samsung,24ad0xd1";
+                        reg = <0x50>;
+                };
+
+                eeprom@52 {
+                        compatible = "samsung,24ad0xd1";
+                        reg = <0x52>;
+                };
+        };
+
+        sdhci@12510000 {
+                status = "disabled";
+        };
+
+        sdhci@12520000 {
+                status = "disabled";
+        };
+
+        sdhci@12540000 {
+                status = "disabled";
+        };
+
+        i2c@13870000 {
+                status = "disabled";
+        };
+
+        i2c@13880000 {
+                status = "disabled";
+        };
+
+        i2c@13890000 {
+                status = "disabled";
+        };
+
+        i2c@138A0000 {
+                status = "disabled";
+        };
+
+        i2c@138B0000 {
+                status = "disabled";
+        };
+
+        i2c@138C0000 {
+                status = "disabled";
+        };
+
+        i2c@138D0000 {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
new file mode 100644
index 00000000000..63d7578856c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -0,0 +1,397 @@
+/*
+ * Samsung's Exynos4210 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "samsung,exynos4210";
+        interrupt-parent = <&gic>;
+
+        gic:interrupt-controller@10490000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+        };
+
+        watchdog@10060000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 43 0>;
+        };
+
+        rtc@10070000 {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x10070000 0x100>;
+                interrupts = <0 44 0>, <0 45 0>;
+        };
+
+        keypad@100A0000 {
+                compatible = "samsung,s5pv210-keypad";
+                reg = <0x100A0000 0x100>;
+                interrupts = <0 109 0>;
+        };
+
+        sdhci@12510000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12510000 0x100>;
+                interrupts = <0 73 0>;
+        };
+
+        sdhci@12520000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12520000 0x100>;
+                interrupts = <0 74 0>;
+        };
+
+        sdhci@12530000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12530000 0x100>;
+                interrupts = <0 75 0>;
+        };
+
+        sdhci@12540000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12540000 0x100>;
+                interrupts = <0 76 0>;
+        };
+
+        serial@13800000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13800000 0x100>;
+                interrupts = <0 52 0>;
+        };
+
+        serial@13810000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13810000 0x100>;
+                interrupts = <0 53 0>;
+        };
+
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+        };
+
+        serial@13830000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13830000 0x100>;
+                interrupts = <0 55 0>;
+        };
+
+        i2c@13860000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13860000 0x100>;
+                interrupts = <0 58 0>;
+        };
+
+        i2c@13870000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13870000 0x100>;
+                interrupts = <0 59 0>;
+        };
+
+        i2c@13880000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13880000 0x100>;
+                interrupts = <0 60 0>;
+        };
+
+        i2c@13890000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13890000 0x100>;
+                interrupts = <0 61 0>;
+        };
+
+        i2c@138A0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138A0000 0x100>;
+                interrupts = <0 62 0>;
+        };
+
+        i2c@138B0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138B0000 0x100>;
+                interrupts = <0 63 0>;
+        };
+
+        i2c@138C0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138C0000 0x100>;
+                interrupts = <0 64 0>;
+        };
+
+        i2c@138D0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138D0000 0x100>;
+                interrupts = <0 65 0>;
+        };
+
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                pdma0: pdma@12680000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12680000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+
+                pdma1: pdma@12690000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12690000 0x1000>;
+                        interrupts = <0 36 0>;
+                };
+        };
+
+        gpio-controllers {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                gpio-controller;
+                ranges;
+
+                gpa0: gpio-controller@11400000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400000 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpa1: gpio-controller@11400020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400020 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpb: gpio-controller@11400040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400040 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpc0: gpio-controller@11400060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400060 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpc1: gpio-controller@11400080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400080 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpd0: gpio-controller@114000A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpd1: gpio-controller@114000C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe0: gpio-controller@114000E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe1: gpio-controller@11400100 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400100 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe2: gpio-controller@11400120 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400120 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe3: gpio-controller@11400140 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400140 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe4: gpio-controller@11400160 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400160 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpf0: gpio-controller@11400180 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400180 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpf1: gpio-controller@114001A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpf2: gpio-controller@114001C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpf3: gpio-controller@114001E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpj0: gpio-controller@11000000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000000 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpj1: gpio-controller@11000020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000020 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpk0: gpio-controller@11000040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000040 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpk1: gpio-controller@11000060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000060 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpk2: gpio-controller@11000080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000080 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpk3: gpio-controller@110000A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110000A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpl0: gpio-controller@110000C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110000C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpl1: gpio-controller@110000E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110000E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpl2: gpio-controller@11000100 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000100 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy0: gpio-controller@11000120 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000120 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy1: gpio-controller@11000140 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000140 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy2: gpio-controller@11000160 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000160 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy3: gpio-controller@11000180 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000180 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy4: gpio-controller@110001A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110001A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy5: gpio-controller@110001C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110001C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy6: gpio-controller@110001E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110001E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx0: gpio-controller@11000C00 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C00 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx1: gpio-controller@11000C20 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C20 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx2: gpio-controller@11000C40 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C40 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx3: gpio-controller@11000C60 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C60 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpz: gpio-controller@03860000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x03860000 0x20>;
+                        #gpio-cells = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index aeb1a7578fa..305635bd45c 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -194,5 +194,17 @@
                         reg = <0xfff3d000 0x1000>;
                         interrupts = <0 92 4>;
                 };
+
+                ethernet@fff50000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff50000 0x1000>;
+                        interrupts = <0 77 4  0 78 4  0 79 4>;
+                };
+
+                ethernet@fff51000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff51000 0x1000>;
+                        interrupts = <0 80 4  0 81 4  0 82 4>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index f8766af1121..564cb8c19f1 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -35,20 +35,19 @@
                                 };
 
                                 esdhc@70008000 { /* ESDHC2 */
-                                        cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
-                                        wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
+                                        cd-gpios = <&gpio1 6 0>;
+                                        wp-gpios = <&gpio1 5 0>;
                                         status = "okay";
                                 };
 
-                                uart2: uart@7000c000 { /* UART3 */
+                                uart3: uart@7000c000 {
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@70010000 { /* ECSPI1 */
                                         fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
-                                                   <&gpio3 25 0>; /* GPIO4_25 */
+                                        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
                                         status = "okay";
 
                                         pmic: mc13892@0 {
@@ -57,7 +56,7 @@
                                                 compatible = "fsl,mc13892";
                                                 spi-max-frequency = <6000000>;
                                                 reg = <0>;
-                                                mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                                                mc13xxx-irq-gpios = <&gpio1 8 0>;
                                                 fsl,mc13xxx-uses-regulator;
                                         };
 
@@ -91,12 +90,12 @@
                                 reg = <0x73fa8000 0x4000>;
                         };
 
-                        uart0: uart@73fbc000 {
+                        uart1: uart@73fbc000 {
                                 fsl,uart-has-rtscts;
                                 status = "okay";
                         };
 
-                        uart1: uart@73fc0000 {
+                        uart2: uart@73fc0000 {
                                 status = "okay";
                         };
                 };
@@ -127,7 +126,7 @@
 
                 power {
                         label = "Power Button";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio2 21 0>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 327ab8e3a4c..6663986fe1c 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -14,9 +14,9 @@
 
 / {
         aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
         };
 
         tzic: tz-interrupt-controller@e0000000 {
@@ -86,7 +86,7 @@
                                         status = "disabled";
                                 };
 
-                                uart2: uart@7000c000 { /* UART3 */
+                                uart3: uart@7000c000 {
                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                         reg = <0x7000c000 0x4000>;
                                         interrupts = <33>;
@@ -117,7 +117,7 @@
                                 };
                         };
 
-                        gpio0: gpio@73f84000 { /* GPIO1 */
+                        gpio1: gpio@73f84000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f84000 0x4000>;
                                 interrupts = <50 51>;
@@ -127,7 +127,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio1: gpio@73f88000 { /* GPIO2 */
+                        gpio2: gpio@73f88000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f88000 0x4000>;
                                 interrupts = <52 53>;
@@ -137,7 +137,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio2: gpio@73f8c000 { /* GPIO3 */
+                        gpio3: gpio@73f8c000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f8c000 0x4000>;
                                 interrupts = <54 55>;
@@ -147,7 +147,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio3: gpio@73f90000 { /* GPIO4 */
+                        gpio4: gpio@73f90000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f90000 0x4000>;
                                 interrupts = <56 57>;
@@ -171,14 +171,14 @@
                                 status = "disabled";
                         };
 
-                        uart0: uart@73fbc000 {
+                        uart1: uart@73fbc000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fbc000 0x4000>;
                                 interrupts = <31>;
                                 status = "disabled";
                         };
 
-                        uart1: uart@73fc0000 {
+                        uart2: uart@73fc0000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fc0000 0x4000>;
                                 interrupts = <32>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2ab7f80a0a3..2dccce46ed8 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -29,8 +29,8 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
-                                        wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
+                                        cd-gpios = <&gpio1 1 0>;
+                                        wp-gpios = <&gpio1 9 0>;
                                         status = "okay";
                                 };
                         };
@@ -44,7 +44,7 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
                 };
@@ -67,7 +67,7 @@
                         compatible = "smsc,lan9220", "smsc,lan9115";
                         reg = <0xf4000000 0x2000000>;
                         phy-mode = "mii";
-                        interrupt-parent = <&gpio1>;
+                        interrupt-parent = <&gpio2>;
                         interrupts = <31>;
                         reg-io-width = <4>;
                         smsc,irq-push-pull;
@@ -79,34 +79,34 @@
 
                 home {
                         label = "Home";
-                        gpios = <&gpio4 10 0>; /* GPIO5_10 */
+                        gpios = <&gpio5 10 0>;
                         linux,code = <102>; /* KEY_HOME */
                         gpio-key,wakeup;
                 };
 
                 back {
                         label = "Back";
-                        gpios = <&gpio4 11 0>; /* GPIO5_11 */
+                        gpios = <&gpio5 11 0>;
                         linux,code = <158>; /* KEY_BACK */
                         gpio-key,wakeup;
                 };
 
                 program {
                         label = "Program";
-                        gpios = <&gpio4 12 0>; /* GPIO5_12 */
+                        gpios = <&gpio5 12 0>;
                         linux,code = <362>; /* KEY_PROGRAM */
                         gpio-key,wakeup;
                 };
 
                 volume-up {
                         label = "Volume Up";
-                        gpios = <&gpio4 13 0>; /* GPIO5_13 */
+                        gpios = <&gpio5 13 0>;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
-                        gpios = <&gpio3 0 0>; /* GPIO4_0 */
+                        gpios = <&gpio4 0 0>;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 3f3a88185ff..5bac4aa4800 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -29,15 +29,14 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
-                                        wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
+                                        cd-gpios = <&gpio3 13 0>;
+                                        wp-gpios = <&gpio3 14 0>;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
                                         fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
-                                                   <&gpio2 19 0>; /* GPIO3_19 */
+                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
 
                                         flash: at45db321d@1 {
@@ -61,8 +60,8 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
-                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
-                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        cd-gpios = <&gpio3 11 0>;
+                                        wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
@@ -76,7 +75,7 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
                 };
@@ -102,7 +101,7 @@
 
                         fec@63fec000 {
                                 phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
                         };
                 };
@@ -113,7 +112,7 @@
 
                 green {
                         label = "Heartbeat";
-                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        gpios = <&gpio7 7 0>;
                         linux,default-trigger = "heartbeat";
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index ae6de6d0c3f..5c57c8672c3 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -29,13 +29,13 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        cd-gpios = <&gpio3 13 0>;
                                         status = "okay";
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
-                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
-                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        cd-gpios = <&gpio3 11 0>;
+                                        wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
@@ -49,7 +49,7 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
                 };
@@ -84,7 +84,7 @@
 
                         fec@63fec000 {
                                 phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
                         };
                 };
@@ -95,20 +95,20 @@
 
                 power {
                         label = "Power Button";
-                        gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                        gpios = <&gpio1 8 0>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
 
                 volume-up {
                         label = "Volume Up";
-                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        gpios = <&gpio2 14 0>;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
-                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        gpios = <&gpio2 15 0>;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
@@ -118,7 +118,7 @@
 
                 user {
                         label = "Heartbeat";
-                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        gpios = <&gpio7 7 0>;
                         linux,default-trigger = "heartbeat";
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index b1c062eea71..c7ee86c2dfb 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -29,8 +29,8 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
-                                        wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
+                                        cd-gpios = <&gpio3 13 0>;
+                                        wp-gpios = <&gpio4 11 0>;
                                         status = "okay";
                                 };
 
@@ -39,15 +39,14 @@
                                         status = "okay";
                                 };
 
-                                uart2: uart@5000c000 { /* UART3 */
+                                uart3: uart@5000c000 {
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
                                         fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
-                                                   <&gpio2 19 0>; /* GPIO3_19 */
+                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
 
                                         zigbee: mc1323@0 {
@@ -91,11 +90,11 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
 
-                        uart1: uart@53fc0000 { /* UART2 */
+                        uart2: uart@53fc0000 {
                                 status = "okay";
                         };
                 };
@@ -145,7 +144,7 @@
 
                         fec@63fec000 {
                                 phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
                         };
                 };
@@ -156,13 +155,13 @@
 
                 volume-up {
                         label = "Volume Up";
-                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        gpios = <&gpio2 14 0>;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
-                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        gpios = <&gpio2 15 0>;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 099cd84ee37..5dd91b942c9 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -14,11 +14,11 @@
 
 / {
         aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
-                serial3 = &uart3;
-                serial4 = &uart4;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
         };
 
         tzic: tz-interrupt-controller@0fffc000 {
@@ -88,7 +88,7 @@
                                         status = "disabled";
                                 };
 
-                                uart2: uart@5000c000 { /* UART3 */
+                                uart3: uart@5000c000 {
                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                         reg = <0x5000c000 0x4000>;
                                         interrupts = <33>;
@@ -119,7 +119,7 @@
                                 };
                         };
 
-                        gpio0: gpio@53f84000 { /* GPIO1 */
+                        gpio1: gpio@53f84000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f84000 0x4000>;
                                 interrupts = <50 51>;
@@ -129,7 +129,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio1: gpio@53f88000 { /* GPIO2 */
+                        gpio2: gpio@53f88000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f88000 0x4000>;
                                 interrupts = <52 53>;
@@ -139,7 +139,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio2: gpio@53f8c000 { /* GPIO3 */
+                        gpio3: gpio@53f8c000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f8c000 0x4000>;
                                 interrupts = <54 55>;
@@ -149,7 +149,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio3: gpio@53f90000 { /* GPIO4 */
+                        gpio4: gpio@53f90000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f90000 0x4000>;
                                 interrupts = <56 57>;
@@ -173,21 +173,21 @@
                                 status = "disabled";
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fbc000 0x4000>;
                                 interrupts = <31>;
                                 status = "disabled";
                         };
 
-                        uart1: uart@53fc0000 { /* UART2 */
+                        uart2: uart@53fc0000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fc0000 0x4000>;
                                 interrupts = <32>;
                                 status = "disabled";
                         };
 
-                        gpio4: gpio@53fdc000 { /* GPIO5 */
+                        gpio5: gpio@53fdc000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53fdc000 0x4000>;
                                 interrupts = <103 104>;
@@ -197,7 +197,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio5: gpio@53fe0000 { /* GPIO6 */
+                        gpio6: gpio@53fe0000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53fe0000 0x4000>;
                                 interrupts = <105 106>;
@@ -207,7 +207,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio6: gpio@53fe4000 { /* GPIO7 */
+                        gpio7: gpio@53fe4000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53fe4000 0x4000>;
                                 interrupts = <107 108>;
@@ -226,7 +226,7 @@
                                 status = "disabled";
                         };
 
-                        uart3: uart@53ff0000 { /* UART4 */
+                        uart4: uart@53ff0000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53ff0000 0x4000>;
                                 interrupts = <13>;
@@ -241,7 +241,7 @@
                         reg = <0x60000000 0x10000000>;
                         ranges;
 
-                        uart4: uart@63f90000 { /* UART5 */
+                        uart5: uart@63f90000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x63f90000 0x4000>;
                                 interrupts = <86>;
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 072974e443f..c3977e0478b 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -14,8 +14,8 @@
 /include/ "imx6q.dtsi"
 
 / {
-        model = "Freescale i.MX6 Quad SABRE Automotive Board";
-        compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+        model = "Freescale i.MX6 Quad Armadillo2 Board";
+        compatible = "fsl,imx6q-arm2", "fsl,imx6q";
 
         chosen {
                 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
@@ -34,8 +34,8 @@
                         };
 
                         usdhc@02198000 { /* uSDHC3 */
-                                cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
-                                wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
+                                cd-gpios = <&gpio6 11 0>;
+                                wp-gpios = <&gpio6 14 0>;
                                 status = "okay";
                         };
 
@@ -44,7 +44,7 @@
                                 status = "okay";
                         };
 
-                        uart3: uart@021f0000 { /* UART4 */
+                        uart4: uart@021f0000 {
                                 status = "okay";
                         };
                 };
@@ -55,7 +55,7 @@
 
                 debug-led {
                         label = "Heartbeat";
-                        gpios = <&gpio2 25 0>; /* GPIO3_25 */
+                        gpios = <&gpio3 25 0>;
                         linux,default-trigger = "heartbeat";
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
new file mode 100644
index 00000000000..08d920de728
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx6q.dtsi"
+
+/ {
+        model = "Freescale i.MX6 Quad SABRE Lite Board";
+        compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+
+        soc {
+                aips-bus@02100000 { /* AIPS2 */
+                        enet@02188000 {
+                                phy-mode = "rgmii";
+                                phy-reset-gpios = <&gpio3 23 0>;
+                                status = "okay";
+                        };
+
+                        usdhc@02198000 { /* uSDHC3 */
+                                cd-gpios = <&gpio7 0 0>;
+                                wp-gpios = <&gpio7 1 0>;
+                                status = "okay";
+                        };
+
+                        usdhc@0219c000 { /* uSDHC4 */
+                                cd-gpios = <&gpio2 6 0>;
+                                wp-gpios = <&gpio2 7 0>;
+                                status = "okay";
+                        };
+
+                        uart2: uart@021e8000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7dda599558c..263e8f3664b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -14,11 +14,11 @@
 
 / {
         aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
-                serial3 = &uart3;
-                serial4 = &uart4;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
         };
 
         cpus {
@@ -165,7 +165,7 @@
                                         status = "disabled";
                                 };
 
-                                uart0: uart@02020000 { /* UART1 */
+                                uart1: uart@02020000 {
                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02020000 0x4000>;
                                         interrupts = <0 26 0x04>;
@@ -247,7 +247,7 @@
                                 interrupts = <0 55 0x04>;
                         };
 
-                        gpio0: gpio@0209c000 { /* GPIO1 */
+                        gpio1: gpio@0209c000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x0209c000 0x4000>;
                                 interrupts = <0 66 0x04 0 67 0x04>;
@@ -257,7 +257,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio1: gpio@020a0000 { /* GPIO2 */
+                        gpio2: gpio@020a0000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020a0000 0x4000>;
                                 interrupts = <0 68 0x04 0 69 0x04>;
@@ -267,7 +267,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio2: gpio@020a4000 { /* GPIO3 */
+                        gpio3: gpio@020a4000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020a4000 0x4000>;
                                 interrupts = <0 70 0x04 0 71 0x04>;
@@ -277,7 +277,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio3: gpio@020a8000 { /* GPIO4 */
+                        gpio4: gpio@020a8000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020a8000 0x4000>;
                                 interrupts = <0 72 0x04 0 73 0x04>;
@@ -287,7 +287,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio4: gpio@020ac000 { /* GPIO5 */
+                        gpio5: gpio@020ac000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020ac000 0x4000>;
                                 interrupts = <0 74 0x04 0 75 0x04>;
@@ -297,7 +297,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio5: gpio@020b0000 { /* GPIO6 */
+                        gpio6: gpio@020b0000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020b0000 0x4000>;
                                 interrupts = <0 76 0x04 0 77 0x04>;
@@ -307,7 +307,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio6: gpio@020b4000 { /* GPIO7 */
+                        gpio7: gpio@020b4000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020b4000 0x4000>;
                                 interrupts = <0 78 0x04 0 79 0x04>;
@@ -543,28 +543,28 @@
                                 interrupts = <0 18 0x04>;
                         };
 
-                        uart1: uart@021e8000 { /* UART2 */
+                        uart2: uart@021e8000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021e8000 0x4000>;
                                 interrupts = <0 27 0x04>;
                                 status = "disabled";
                         };
 
-                        uart2: uart@021ec000 { /* UART3 */
+                        uart3: uart@021ec000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021ec000 0x4000>;
                                 interrupts = <0 28 0x04>;
                                 status = "disabled";
                         };
 
-                        uart3: uart@021f0000 { /* UART4 */
+                        uart4: uart@021f0000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f0000 0x4000>;
                                 interrupts = <0 29 0x04>;
                                 status = "disabled";
                         };
 
-                        uart4: uart@021f4000 { /* UART5 */
+                        uart5: uart@021f4000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f4000 0x4000>;
                                 interrupts = <0 30 0x04>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
new file mode 100644
index 00000000000..f2ab4ea7cc0
--- /dev/null
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Source for OMAP2 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm1136jf-s";
+                };
+        };
+
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap2-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main";
+
+                intc: interrupt-controller@1 {
+                        compatible = "ti,omap2-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                uart1: serial@4806a000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@4806c000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@4806e000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d202bb5ec7e..216c3317461 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,6 +13,13 @@
 / {
         compatible = "ti,omap3430", "ti,omap3";
 
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+        };
+
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
                         interrupt-controller;
                         #interrupt-cells = <1>;
                 };
+
+                uart1: serial@0x4806a000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@0x4806c000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@0x49020000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+
+                uart4: serial@0x49042000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4c61c829043..e8fe75fac7c 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -21,6 +21,10 @@
         interrupt-parent = <&gic>;
 
         aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
         };
 
         cpus {
@@ -99,5 +103,29 @@
                         reg = <0x48241000 0x1000>,
                               <0x48240100 0x0100>;
                 };
+
+                uart1: serial@0x4806a000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@0x4806c000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@0x48020000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+
+                uart4: serial@0x4806e000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
new file mode 100644
index 00000000000..70c41fc897d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/include/ "tegra30.dtsi"
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu evaluation board";
+        compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+        memory {
+                reg = < 0x80000000 0x40000000 >;
+        };
+
+        serial@70006000 {
+                clock-frequency = < 408000000 >;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c700 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <100000>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 0e225b86b65..80afa1b70b8 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -1,16 +1,11 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra2 Harmony evaluation board";
         compatible = "nvidia,harmony", "nvidia,tegra20";
 
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
-        };
-
         memory@0 {
                 reg = < 0x00000000 0x40000000 >;
         };
@@ -52,16 +47,40 @@
                 ext-mic-en-gpios = <&gpio 185 0>;
         };
 
+        serial@70006000 {
+                status = "disable";
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
         serial@70006300 {
                 clock-frequency = < 216000000 >;
         };
 
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
         sdhci@c8000200 {
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 155 0>; /* gpio PT3 */
         };
 
+        sdhci@c8000400 {
+                status = "disable";
+        };
+
         sdhci@c8000600 {
                 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
new file mode 100644
index 00000000000..1a1d7023b69
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "Toshiba AC100 / Dynabook AZ";
+        compatible = "compal,paz00", "nvidia,tegra20";
+
+        memory@0 {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                status = "disable";
+        };
+
+        nvec@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,nvec";
+                reg = <0x7000C500 0x100>;
+                interrupts = <0 92 0x04>;
+                clock-frequency = <80000>;
+                request-gpios = <&gpio 170 0>;
+                slave-addr = <138>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+
+        serial@70006000 {
+                clock-frequency = <216000000>;
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
+        serial@70006300 {
+                clock-frequency = <216000000>;
+        };
+
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
+                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
+        sdhci@c8000400 {
+                status = "disable";
+        };
+
+        sdhci@c8000600 {
+                support-8bit;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index a72299b8e66..b55a02e34ba 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -1,25 +1,65 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 
 / {
         model = "NVIDIA Seaboard";
         compatible = "nvidia,seaboard", "nvidia,tegra20";
 
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
-        };
-
         memory {
                 device_type = "memory";
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+
+                adt7461@4c {
+                        compatible = "adt7461";
+                        reg = <0x4c>;
+                };
+        };
+
+        serial@70006000 {
+                status = "disable";
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
         serial@70006300 {
                 clock-frequency = < 216000000 >;
         };
 
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
         sdhci@c8000400 {
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
@@ -29,4 +69,28 @@
         sdhci@c8000600 {
                 support-8bit;
         };
+
+        usb@c5000000 {
+                nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+
+                lid {
+                        label = "Lid";
+                        gpios = <&gpio 23 0>; /* gpio PC7 */
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <0>; /* SW_LID */
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
new file mode 100644
index 00000000000..3b3ee7db99f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -0,0 +1,65 @@
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "Compulab TrimSlice board";
+        compatible = "compulab,trimslice", "nvidia,tegra20";
+
+        memory@0 {
+                reg = < 0x00000000 0x40000000 >;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                status = "disable";
+        };
+
+        serial@70006000 {
+                clock-frequency = < 216000000 >;
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
+        serial@70006300 {
+                status = "disable";
+        };
+
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
+        sdhci@c8000400 {
+                status = "disable";
+        };
+
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 121 0>;
+                wp-gpios = <&gpio 122 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 3f9abd6b696..c7d3b87f29d 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -1,24 +1,59 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra2 Ventana evaluation board";
         compatible = "nvidia,ventana", "nvidia,tegra20";
 
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
-        };
-
         memory {
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+
+        serial@70006000 {
+                status = "disable";
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
         serial@70006300 {
                 clock-frequency = < 216000000 >;
         };
 
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
         sdhci@c8000400 {
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 65d7e6a333e..3da7afd4532 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -5,9 +5,9 @@
         interrupt-parent = <&intc>;
 
         intc: interrupt-controller@50041000 {
-                compatible = "nvidia,tegra20-gic";
+                compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
-                #interrupt-cells = <1>;
+                #interrupt-cells = <3>;
                 reg = < 0x50041000 0x1000 >,
                       < 0x50040100 0x0100 >;
         };
@@ -17,7 +17,7 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000C000 0x100>;
-                interrupts = < 70 >;
+                interrupts = < 0 38 0x04 >;
         };
 
         i2c@7000c400 {
@@ -25,7 +25,7 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000C400 0x100>;
-                interrupts = < 116 >;
+                interrupts = < 0 84 0x04 >;
         };
 
         i2c@7000c500 {
@@ -33,38 +33,32 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000C500 0x100>;
-                interrupts = < 124 >;
+                interrupts = < 0 92 0x04 >;
         };
 
         i2c@7000d000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "nvidia,tegra20-i2c";
+                compatible = "nvidia,tegra20-i2c-dvc";
                 reg = <0x7000D000 0x200>;
-                interrupts = < 85 >;
+                interrupts = < 0 53 0x04 >;
         };
 
         i2s@70002800 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
-                interrupts = < 45 >;
+                interrupts = < 0 13 0x04 >;
                 dma-channel = < 2 >;
         };
 
         i2s@70002a00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
-                interrupts = < 35 >;
+                interrupts = < 0 3 0x04 >;
                 dma-channel = < 1 >;
         };
 
         das@70000c00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                 compatible = "nvidia,tegra20-das";
                 reg = <0x70000c00 0x80>;
         };
@@ -72,7 +66,13 @@
         gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra20-gpio";
                 reg = < 0x6000d000 0x1000 >;
-                interrupts = < 64 65 66 67 87 119 121 >;
+                interrupts = < 0 32 0x04
+                               0 33 0x04
+                               0 34 0x04
+                               0 35 0x04
+                               0 55 0x04
+                               0 87 0x04
+                               0 89 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
         };
@@ -89,59 +89,80 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = < 68 >;
+                interrupts = < 0 36 0x04 >;
         };
 
         serial@70006040 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = < 69 >;
+                interrupts = < 0 37 0x04 >;
         };
 
         serial@70006200 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = < 78 >;
+                interrupts = < 0 46 0x04 >;
         };
 
         serial@70006300 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = < 122 >;
+                interrupts = < 0 90 0x04 >;
         };
 
         serial@70006400 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = < 123 >;
+                interrupts = < 0 91 0x04 >;
         };
 
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
-                interrupts = < 46 >;
+                interrupts = < 0 14 0x04 >;
         };
 
         sdhci@c8000200 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000200 0x200>;
-                interrupts = < 47 >;
+                interrupts = < 0 15 0x04 >;
         };
 
         sdhci@c8000400 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000400 0x200>;
-                interrupts = < 51 >;
+                interrupts = < 0 19 0x04 >;
         };
 
         sdhci@c8000600 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000600 0x200>;
-                interrupts = < 63 >;
+                interrupts = < 0 31 0x04 >;
+        };
+
+        usb@c5000000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5000000 0x4000>;
+                interrupts = < 0 20 0x04 >;
+                phy_type = "utmi";
+        };
+
+        usb@c5004000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5004000 0x4000>;
+                interrupts = < 0 21 0x04 >;
+                phy_type = "ulpi";
+        };
+
+        usb@c5008000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5008000 0x4000>;
+                interrupts = < 0 97 0x04 >;
+                phy_type = "utmi";
         };
 };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
new file mode 100644
index 00000000000..ee7db9892e0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -0,0 +1,127 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "nvidia,tegra30";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller@50041000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x50041000 0x1000 >,
+                      < 0x50040100 0x0100 >;
+        };
+
+        i2c@7000c000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C000 0x100>;
+                interrupts = < 0 38 0x04 >;
+        };
+
+        i2c@7000c400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C400 0x100>;
+                interrupts = < 0 84 0x04 >;
+        };
+
+        i2c@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C500 0x100>;
+                interrupts = < 0 92 0x04 >;
+        };
+
+        i2c@7000c700 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000c700 0x100>;
+                interrupts = < 0 120 0x04 >;
+        };
+
+        i2c@7000d000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000D000 0x100>;
+                interrupts = < 0 53 0x04 >;
+        };
+
+        gpio: gpio@6000d000 {
+                compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+                reg = < 0x6000d000 0x1000 >;
+                interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
+                #gpio-cells = <2>;
+                gpio-controller;
+        };
+
+        serial@70006000 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006000 0x40>;
+                reg-shift = <2>;
+                interrupts = < 0 36 0x04 >;
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006040 0x40>;
+                reg-shift = <2>;
+                interrupts = < 0 37 0x04 >;
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006200 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 46 0x04 >;
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006300 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 90 0x04 >;
+        };
+
+        serial@70006400 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006400 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 91 0x04 >;
+        };
+
+        sdhci@78000000 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000000 0x200>;
+                interrupts = < 0 14 0x04 >;
+        };
+
+        sdhci@78000200 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000200 0x200>;
+                interrupts = < 0 15 0x04 >;
+        };
+
+        sdhci@78000400 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000400 0x200>;
+                interrupts = < 0 19 0x04 >;
+        };
+
+        sdhci@78000600 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000600 0x200>;
+                interrupts = < 0 31 0x04 >;
+        };
+
+        pinmux: pinmux@70000000 {
+                compatible = "nvidia,tegra30-pinmux";
+                reg = < 0x70000868 0xd0     /* Pad control registers */
+                        0x70003000 0x3e0 >; /* Mux registers */
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index d66e2c00ac3..f04b535477f 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -25,6 +25,11 @@
                         dbgu: serial@fffff200 {
                                 status = "okay";
                         };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
                 };
         };
 };
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index cf497ce41df..a22e9307906 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -68,7 +68,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 945a34f2a34..dde2a1af7b3 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y
 CONFIG_MACH_NOKIA770=y
 CONFIG_MACH_AMS_DELTA=y
 CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_182MHZ=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_OMAP_CF=y
diff --git a/arch/arm/configs/pcontrol_g20_defconfig b/arch/arm/configs/pcontrol_g20_defconfig
deleted file mode 100644
index c75c9fcede5..00000000000
--- a/arch/arm/configs/pcontrol_g20_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_CROSS_COMPILE="/opt/arm-2010q1/bin/arm-none-linux-gnueabi-"
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_NAMESPACES=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_KALLSYMS is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_DEFAULT_DEADLINE=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
-CONFIG_MACH_PCONTROL_G20=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 mem=128M mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) root=/dev/mmcblk0p1 rootwait rw"
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_VLAN_8021Q=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_TCLIB=y
-CONFIG_EEPROM_AT24=m
-CONFIG_SCSI=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_MACVLAN=m
-CONFIG_TUN=m
-CONFIG_SMSC_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-CONFIG_SMSC911X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_MPPE=m
-CONFIG_INPUT_POLLDEV=y
-CONFIG_INPUT_SPARSEKMAP=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_MATRIX=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_MAX3100=m
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_R3964=m
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=m
-CONFIG_SPI_SPIDEV=m
-CONFIG_GPIO_SYSFS=y
-CONFIG_W1=m
-CONFIG_W1_MASTER_GPIO=m
-CONFIG_W1_SLAVE_DS2431=m
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_LIBUSUAL=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_HID=m
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_AUXDISPLAY=y
-CONFIG_UIO=y
-CONFIG_UIO_PDRV=y
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-CONFIG_IIO=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 195729760ae..fd5d3041d71 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_2x_SOC=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_MACH_HARMONY=y
 CONFIG_MACH_KAEN=y
 CONFIG_MACH_PAZ00=y
@@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_R8169=y
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 065d100fa63..9275828feb3 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -27,6 +27,7 @@
 #include <asm/byteorder.h>
 #include <asm/memory.h>
 #include <asm/system.h>
+#include <asm-generic/pci_iomap.h>
 
 /*
  * ISA I/O bus memory addresses are 1:1 with the physical address.
@@ -306,7 +307,6 @@ extern void ioport_unmap(void __iomem *addr);
 
 struct pci_dev;
 
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 
 /*
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index d111c3e9924..4f991f29528 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,6 +3,12 @@ if ARCH_AT91
 config HAVE_AT91_DATAFLASH_CARD
         bool
 
+config HAVE_AT91_DBGU0
+        bool
+
+config HAVE_AT91_DBGU1
+        bool
+
 config HAVE_AT91_USART3
         bool
 
@@ -21,12 +27,14 @@ config ARCH_AT91RM9200
         bool "AT91RM9200"
         select CPU_ARM920T
         select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
         select HAVE_AT91_USART3
 
 config ARCH_AT91SAM9260
         bool "AT91SAM9260 or AT91SAM9XE"
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
@@ -37,11 +45,13 @@ config ARCH_AT91SAM9261
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU0
 
 config ARCH_AT91SAM9G10
         bool "AT91SAM9G10"
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
         select HAVE_FB_ATMEL
 
 config ARCH_AT91SAM9263
@@ -50,6 +60,7 @@ config ARCH_AT91SAM9263
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
+        select HAVE_AT91_DBGU1
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
@@ -57,11 +68,13 @@ config ARCH_AT91SAM9RL
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_USART3
         select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU0
 
 config ARCH_AT91SAM9G20
         bool "AT91SAM9G20"
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
@@ -74,6 +87,7 @@ config ARCH_AT91SAM9G45
         select HAVE_AT91_USART3
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
+        select HAVE_AT91_DBGU1
 
 config ARCH_AT91CAP9
         bool "AT91CAP9"
@@ -81,6 +95,7 @@ config ARCH_AT91CAP9
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
+        select HAVE_AT91_DBGU1
 
 config ARCH_AT91X40
         bool "AT91x40"
@@ -510,8 +525,13 @@ config AT91_TIMER_HZ
 choice
         prompt "Select a UART for early kernel messages"
 
-config AT91_EARLY_DBGU
-        bool "DBGU"
+config AT91_EARLY_DBGU0
+        bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl"
+        depends on HAVE_AT91_DBGU0
+
+config AT91_EARLY_DBGU1
+        bool "DBGU on 9263, 9g45 and cap9"
+        depends on HAVE_AT91_DBGU1
 
 config AT91_EARLY_USART0
         bool "USART0"
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 29373397d2d..edb879ac04c 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -13,7 +13,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/pm.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -23,11 +22,11 @@
 #include <mach/at91cap9.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -137,7 +136,7 @@ static struct clk pwm_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -210,6 +209,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
@@ -221,6 +222,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioABCD_clk),
+        CLKDEV_CON_ID("pioB", &pioABCD_clk),
+        CLKDEV_CON_ID("pioC", &pioABCD_clk),
+        CLKDEV_CON_ID("pioD", &pioABCD_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -293,23 +298,19 @@ void __init at91cap9_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91cap9_gpio[] = {
+static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
         {
                 .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOA,
-                .clock          = &pioABCD_clk,
+                .regbase        = AT91CAP9_BASE_PIOA,
         }, {
                 .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOB,
-                .clock          = &pioABCD_clk,
+                .regbase        = AT91CAP9_BASE_PIOB,
         }, {
                 .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOC,
-                .clock          = &pioABCD_clk,
+                .regbase        = AT91CAP9_BASE_PIOC,
         }, {
                 .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOD,
-                .clock          = &pioABCD_clk,
+                .regbase        = AT91CAP9_BASE_PIOD,
         }
 };
 
@@ -318,12 +319,6 @@ static void at91cap9_restart(char mode, const char *cmd)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
-static void at91cap9_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
 /* --------------------------------------------------------------------
  *  AT91CAP9 processor initialization
  * -------------------------------------------------------------------- */
@@ -333,10 +328,16 @@ static void __init at91cap9_map_io(void)
         at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
 }
 
+static void __init at91cap9_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
+}
+
 static void __init at91cap9_initialize(void)
 {
         arm_pm_restart = at91cap9_restart;
-        pm_power_off = at91cap9_poweroff;
         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 
         /* Register GPIO subsystem */
@@ -394,6 +395,7 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91cap9_soc = {
         .map_io = at91cap9_map_io,
         .default_irq_priority = at91cap9_default_irq_priority,
+        .ioremap_registers = at91cap9_ioremap_registers,
         .register_clocks = at91cap9_register_clocks,
         .init = at91cap9_initialize,
 };
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index adad70db70e..d298fb7cb21 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -76,7 +76,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 
         /* Enable VBus control for UHP ports */
         for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                         at91_set_gpio_output(data->vbus_pin[i], 0);
         }
 
@@ -179,7 +179,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 
-        if (data && data->vbus_pin > 0) {
+        if (data && gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -200,7 +200,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {}
 
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 
 static struct resource eth_resources[] = {
         [0] = {
@@ -227,12 +227,12 @@ static struct platform_device at91cap9_eth_device = {
         .num_resources  = ARRAY_SIZE(eth_resources),
 };
 
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
         if (!data)
                 return;
 
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                 at91_set_gpio_input(data->phy_irq_pin, 0);
                 at91_set_deglitch(data->phy_irq_pin, 1);
         }
@@ -264,7 +264,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
         platform_device_register(&at91cap9_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
 
 
@@ -332,13 +332,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 return;
 
         /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                 at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
 
         if (mmc_id == 0) {              /* MCI0 */
@@ -398,8 +398,8 @@ static struct resource nand_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .start  = AT91CAP9_BASE_ECC,
+                .end    = AT91CAP9_BASE_ECC + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -425,15 +425,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         nand_data = *data;
@@ -670,8 +670,8 @@ static void __init at91_add_device_tc(void) { }
 
 static struct resource rtt_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .start  = AT91CAP9_BASE_RTT,
+                .end    = AT91CAP9_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -694,10 +694,19 @@ static void __init at91_add_device_rtt(void)
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91CAP9_BASE_WDT,
+                .end    = AT91CAP9_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91cap9_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 
 static void __init at91_add_device_watchdog(void)
@@ -807,7 +816,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
         at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
 
         /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                 at91_set_gpio_output(data->reset_pin, 0);
 
         ac97_data = *data;
@@ -1021,8 +1030,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91CAP9_BASE_DBGU,
+                .end    = AT91CAP9_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 430a9fdc3db..99c3174e24a 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -23,6 +23,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 static struct map_desc at91rm9200_io_desc[] __initdata = {
         {
@@ -195,6 +196,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_ID("pioD", &pioD_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -268,23 +273,19 @@ void __init at91rm9200_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91rm9200_gpio[] = {
+static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
         {
                 .id             = AT91RM9200_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
+                .regbase        = AT91RM9200_BASE_PIOA,
         }, {
                 .id             = AT91RM9200_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
+                .regbase        = AT91RM9200_BASE_PIOB,
         }, {
                 .id             = AT91RM9200_ID_PIOC,
-                .offset         = AT91_PIOC,
-                .clock          = &pioC_clk,
+                .regbase        = AT91RM9200_BASE_PIOC,
         }, {
                 .id             = AT91RM9200_ID_PIOD,
-                .offset         = AT91_PIOD,
-                .clock          = &pioD_clk,
+                .regbase        = AT91RM9200_BASE_PIOD,
         }
 };
 
@@ -307,6 +308,10 @@ static void __init at91rm9200_map_io(void)
         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 }
 
+static void __init at91rm9200_ioremap_registers(void)
+{
+}
+
 static void __init at91rm9200_initialize(void)
 {
         arm_pm_restart = at91rm9200_restart;
@@ -366,6 +371,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91rm9200_soc = {
         .map_io = at91rm9200_map_io,
         .default_irq_priority = at91rm9200_default_irq_priority,
+        .ioremap_registers = at91rm9200_ioremap_registers,
         .register_clocks = at91rm9200_register_clocks,
         .init = at91rm9200_initialize,
 };
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index ad930688358..18bacec2b09 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -114,11 +114,11 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
         if (!data)
                 return;
 
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
         }
-        if (data->pullup_pin)
+        if (gpio_is_valid(data->pullup_pin))
                 at91_set_gpio_output(data->pullup_pin, 0);
 
         udc_data = *data;
@@ -135,7 +135,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 
 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 
 static struct resource eth_resources[] = {
         [0] = {
@@ -162,12 +162,12 @@ static struct platform_device at91rm9200_eth_device = {
         .num_resources  = ARRAY_SIZE(eth_resources),
 };
 
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
         if (!data)
                 return;
 
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                 at91_set_gpio_input(data->phy_irq_pin, 0);
                 at91_set_deglitch(data->phy_irq_pin, 1);
         }
@@ -199,7 +199,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
         platform_device_register(&at91rm9200_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
 
 
@@ -260,7 +260,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         );
 
         /* input/irq */
-        if (data->irq_pin) {
+        if (gpio_is_valid(data->irq_pin)) {
                 at91_set_gpio_input(data->irq_pin, 1);
                 at91_set_deglitch(data->irq_pin, 1);
         }
@@ -268,7 +268,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         at91_set_deglitch(data->det_pin, 1);
 
         /* outputs, initially off */
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
         at91_set_gpio_output(data->rst_pin, 0);
 
@@ -328,13 +328,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 return;
 
         /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                 at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
 
         /* CLK */
@@ -419,15 +419,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         );
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         at91_set_A_periph(AT91_PIN_PC1, 0);             /* SMOE */
@@ -665,10 +665,24 @@ static void __init at91_add_device_tc(void) { }
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_RTC,
+                .end    = AT91RM9200_BASE_RTC + SZ_256 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device at91rm9200_rtc_device = {
         .name           = "at91_rtc",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = rtc_resources,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
 };
 
 static void __init at91_add_device_rtc(void)
@@ -877,8 +891,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91RM9200_BASE_DBGU,
+                .end    = AT91RM9200_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 1dd69c85dfe..a028cdf8f97 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -32,6 +32,8 @@ static unsigned long last_crtr;
 static u32 irqmask;
 static struct clock_event_device clkevt;
 
+#define RM9200_TIMER_LATCH      ((AT91_SLOW_CLOCK + HZ/2) / HZ)
+
 /*
  * The ST_CRTR is updated asynchronously to the master clock ... but
  * the updates as seen by the CPU don't seem to be strictly monotonic.
@@ -74,8 +76,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
         if (sr & AT91_ST_PITS) {
                 u32     crtr = read_CRTR();
 
-                while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) {
-                        last_crtr += LATCH;
+                while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
+                        last_crtr += RM9200_TIMER_LATCH;
                         clkevt.event_handler(&clkevt);
                 }
                 return IRQ_HANDLED;
@@ -116,7 +118,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
         case CLOCK_EVT_MODE_PERIODIC:
                 /* PIT for periodic irqs; fixed rate of 1/HZ */
                 irqmask = AT91_ST_PITS;
-                at91_sys_write(AT91_ST_PIMR, LATCH);
+                at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 /* ALM for oneshot irqs, set by next_event()
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index e76cd49ebc9..5e46e4a9643 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/pm.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -21,11 +20,11 @@
 #include <mach/at91sam9260.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -120,7 +119,7 @@ static struct clk ohci_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -190,6 +189,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
@@ -209,6 +210,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -270,28 +274,19 @@ void __init at91sam9260_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91sam9260_gpio[] = {
+static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
         {
                 .id             = AT91SAM9260_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
+                .regbase        = AT91SAM9260_BASE_PIOA,
         }, {
                 .id             = AT91SAM9260_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
+                .regbase        = AT91SAM9260_BASE_PIOB,
         }, {
                 .id             = AT91SAM9260_ID_PIOC,
-                .offset         = AT91_PIOC,
-                .clock          = &pioC_clk,
+                .regbase        = AT91SAM9260_BASE_PIOC,
         }
 };
 
-static void at91sam9260_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
 /* --------------------------------------------------------------------
  *  AT91SAM9260 processor initialization
  * -------------------------------------------------------------------- */
@@ -325,10 +320,16 @@ static void __init at91sam9260_map_io(void)
         }
 }
 
+static void __init at91sam9260_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
+}
+
 static void __init at91sam9260_initialize(void)
 {
         arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9260_poweroff;
         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                         | (1 << AT91SAM9260_ID_IRQ2);
 
@@ -381,6 +382,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9260_soc = {
         .map_io = at91sam9260_map_io,
         .default_irq_priority = at91sam9260_default_irq_priority,
+        .ioremap_registers = at91sam9260_ioremap_registers,
         .register_clocks = at91sam9260_register_clocks,
         .init = at91sam9260_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 629fa977497..642ccb6d26b 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -115,7 +115,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
         if (!data)
                 return;
 
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
         }
@@ -136,7 +136,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 
 static struct resource eth_resources[] = {
         [0] = {
@@ -163,12 +163,12 @@ static struct platform_device at91sam9260_eth_device = {
         .num_resources  = ARRAY_SIZE(eth_resources),
 };
 
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
         if (!data)
                 return;
 
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                 at91_set_gpio_input(data->phy_irq_pin, 0);
                 at91_set_deglitch(data->phy_irq_pin, 1);
         }
@@ -200,7 +200,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
         platform_device_register(&at91sam9260_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
 
 
@@ -243,13 +243,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 return;
 
         /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                 at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
 
         /* CLK */
@@ -330,11 +330,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
                 if (data->slot[i].bus_width) {
                         /* input/irq */
-                        if (data->slot[i].detect_pin) {
+                        if (gpio_is_valid(data->slot[i].detect_pin)) {
                                 at91_set_gpio_input(data->slot[i].detect_pin, 1);
                                 at91_set_deglitch(data->slot[i].detect_pin, 1);
                         }
-                        if (data->slot[i].wp_pin)
+                        if (gpio_is_valid(data->slot[i].wp_pin))
                                 at91_set_gpio_input(data->slot[i].wp_pin, 1);
 
                         switch (i) {
@@ -399,8 +399,8 @@ static struct resource nand_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .start  = AT91SAM9260_BASE_ECC,
+                .end    = AT91SAM9260_BASE_ECC + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -426,15 +426,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         nand_data = *data;
@@ -714,8 +714,8 @@ static void __init at91_add_device_tc(void) { }
 
 static struct resource rtt_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .start  = AT91SAM9260_BASE_RTT,
+                .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -738,10 +738,19 @@ static void __init at91_add_device_rtt(void)
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9260_BASE_WDT,
+                .end    = AT91SAM9260_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91sam9260_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 
 static void __init at91_add_device_watchdog(void)
@@ -837,8 +846,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91SAM9260_BASE_DBGU,
+                .end    = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -1281,17 +1290,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
 
         at91_sys_write(AT91_MATRIX_EBICSA, csa);
 
-        if (data->rst_pin) {
+        if (gpio_is_valid(data->rst_pin)) {
                 at91_set_multi_drive(data->rst_pin, 0);
                 at91_set_gpio_output(data->rst_pin, 1);
         }
 
-        if (data->irq_pin) {
+        if (gpio_is_valid(data->irq_pin)) {
                 at91_set_gpio_input(data->irq_pin, 0);
                 at91_set_deglitch(data->irq_pin, 1);
         }
 
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 0);
                 at91_set_deglitch(data->det_pin, 1);
         }
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 19ac7c0729a..b85b9ea6017 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/pm.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -20,11 +19,11 @@
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -176,6 +175,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -251,28 +253,19 @@ void __init at91sam9261_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91sam9261_gpio[] = {
+static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
         {
                 .id             = AT91SAM9261_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
+                .regbase        = AT91SAM9261_BASE_PIOA,
         }, {
                 .id             = AT91SAM9261_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
+                .regbase        = AT91SAM9261_BASE_PIOB,
         }, {
                 .id             = AT91SAM9261_ID_PIOC,
-                .offset         = AT91_PIOC,
-                .clock          = &pioC_clk,
+                .regbase        = AT91SAM9261_BASE_PIOC,
         }
 };
 
-static void at91sam9261_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
 /* --------------------------------------------------------------------
  *  AT91SAM9261 processor initialization
  * -------------------------------------------------------------------- */
@@ -285,10 +278,16 @@ static void __init at91sam9261_map_io(void)
                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 }
 
+static void __init at91sam9261_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
+}
+
 static void __init at91sam9261_initialize(void)
 {
         arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9261_poweroff;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                         | (1 << AT91SAM9261_ID_IRQ2);
 
@@ -341,6 +340,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9261_soc = {
         .map_io = at91sam9261_map_io,
         .default_irq_priority = at91sam9261_default_irq_priority,
+        .ioremap_registers = at91sam9261_ioremap_registers,
         .register_clocks = at91sam9261_register_clocks,
         .init = at91sam9261_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index a178b58b0b9..fc59cbdb0e3 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -118,7 +118,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
         if (!data)
                 return;
 
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
         }
@@ -171,13 +171,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 return;
 
         /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                 at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
 
         /* CLK */
@@ -240,15 +240,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         at91_set_A_periph(AT91_PIN_PC0, 0);             /* NANDOE */
@@ -600,8 +600,8 @@ static void __init at91_add_device_tc(void) { }
 
 static struct resource rtt_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .start  = AT91SAM9261_BASE_RTT,
+                .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -624,10 +624,19 @@ static void __init at91_add_device_rtt(void)
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9261_BASE_WDT,
+                .end    = AT91SAM9261_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91sam9261_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 
 static void __init at91_add_device_watchdog(void)
@@ -816,8 +825,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91SAM9261_BASE_DBGU,
+                .end    = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 50d01631003..79e3669b111 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/pm.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -19,11 +18,11 @@
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -118,7 +117,7 @@ static struct clk pwm_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
         .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -182,6 +181,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
@@ -191,6 +192,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioCDE_clk),
+        CLKDEV_CON_ID("pioD", &pioCDE_clk),
+        CLKDEV_CON_ID("pioE", &pioCDE_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -263,36 +269,25 @@ void __init at91sam9263_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91sam9263_gpio[] = {
+static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
         {
                 .id             = AT91SAM9263_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
+                .regbase        = AT91SAM9263_BASE_PIOA,
         }, {
                 .id             = AT91SAM9263_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
+                .regbase        = AT91SAM9263_BASE_PIOB,
         }, {
                 .id             = AT91SAM9263_ID_PIOCDE,
-                .offset         = AT91_PIOC,
-                .clock          = &pioCDE_clk,
+                .regbase        = AT91SAM9263_BASE_PIOC,
         }, {
                 .id             = AT91SAM9263_ID_PIOCDE,
-                .offset         = AT91_PIOD,
-                .clock          = &pioCDE_clk,
+                .regbase        = AT91SAM9263_BASE_PIOD,
         }, {
                 .id             = AT91SAM9263_ID_PIOCDE,
-                .offset         = AT91_PIOE,
-                .clock          = &pioCDE_clk,
+                .regbase        = AT91SAM9263_BASE_PIOE,
         }
 };
 
-static void at91sam9263_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
 /* --------------------------------------------------------------------
  *  AT91SAM9263 processor initialization
  * -------------------------------------------------------------------- */
@@ -303,10 +298,17 @@ static void __init at91sam9263_map_io(void)
         at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
 }
 
+static void __init at91sam9263_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
+        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
+}
+
 static void __init at91sam9263_initialize(void)
 {
         arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9263_poweroff;
         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
         /* Register GPIO subsystem */
@@ -358,6 +360,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9263_soc = {
         .map_io = at91sam9263_map_io,
         .default_irq_priority = at91sam9263_default_irq_priority,
+        .ioremap_registers = at91sam9263_ioremap_registers,
         .register_clocks = at91sam9263_register_clocks,
         .init = at91sam9263_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index d5fbac9ff4f..7b46b278702 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -70,7 +70,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 
         /* Enable VBus control for UHP ports */
         for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                         at91_set_gpio_output(data->vbus_pin[i], 0);
         }
 
@@ -123,7 +123,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
         if (!data)
                 return;
 
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
         }
@@ -144,7 +144,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 
 static struct resource eth_resources[] = {
         [0] = {
@@ -171,12 +171,12 @@ static struct platform_device at91sam9263_eth_device = {
         .num_resources  = ARRAY_SIZE(eth_resources),
 };
 
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
         if (!data)
                 return;
 
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                 at91_set_gpio_input(data->phy_irq_pin, 0);
                 at91_set_deglitch(data->phy_irq_pin, 1);
         }
@@ -208,7 +208,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
         platform_device_register(&at91sam9263_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
 
 
@@ -276,13 +276,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 return;
 
         /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                 at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
 
         if (mmc_id == 0) {              /* MCI0 */
@@ -430,17 +430,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         }
         at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
 
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
 
-        if (data->irq_pin) {
+        if (gpio_is_valid(data->irq_pin)) {
                 at91_set_gpio_input(data->irq_pin, 1);
                 at91_set_deglitch(data->irq_pin, 1);
         }
 
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 /* initially off */
                 at91_set_gpio_output(data->vcc_pin, 0);
 
@@ -473,8 +473,8 @@ static struct resource nand_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC0,
-                .end    = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
+                .start  = AT91SAM9263_BASE_ECC0,
+                .end    = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -500,15 +500,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         nand_data = *data;
@@ -749,7 +749,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
         at91_set_A_periph(AT91_PIN_PB3, 0);     /* AC97RX */
 
         /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                 at91_set_gpio_output(data->reset_pin, 0);
 
         ac97_data = *data;
@@ -956,8 +956,8 @@ static void __init at91_add_device_tc(void) { }
 
 static struct resource rtt0_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT0,
-                .end    = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1,
+                .start  = AT91SAM9263_BASE_RTT0,
+                .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -971,8 +971,8 @@ static struct platform_device at91sam9263_rtt0_device = {
 
 static struct resource rtt1_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT1,
-                .end    = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1,
+                .start  = AT91SAM9263_BASE_RTT1,
+                .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -996,10 +996,19 @@ static void __init at91_add_device_rtt(void)
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9263_BASE_WDT,
+                .end    = AT91SAM9263_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91sam9263_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 
 static void __init at91_add_device_watchdog(void)
@@ -1196,8 +1205,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91SAM9263_BASE_DBGU,
+                .end    = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 4ba85499fa9..d89ead740a9 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -25,7 +25,17 @@
 
 static u32 pit_cycle;           /* write-once */
 static u32 pit_cnt;             /* access only w/system irq blocked */
+static void __iomem *pit_base_addr __read_mostly;
 
+static inline unsigned int pit_read(unsigned int reg_offset)
+{
+        return __raw_readl(pit_base_addr + reg_offset);
+}
+
+static inline void pit_write(unsigned int reg_offset, unsigned long value)
+{
+        __raw_writel(value, pit_base_addr + reg_offset);
+}
 
 /*
  * Clocksource:  just a monotonic counter of MCK/16 cycles.
@@ -39,7 +49,7 @@ static cycle_t read_pit_clk(struct clocksource *cs)
 
         raw_local_irq_save(flags);
         elapsed = pit_cnt;
-        t = at91_sys_read(AT91_PIT_PIIR);
+        t = pit_read(AT91_PIT_PIIR);
         raw_local_irq_restore(flags);
 
         elapsed += PIT_PICNT(t) * pit_cycle;
@@ -64,8 +74,8 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 /* update clocksource counter */
-                pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
-                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+                pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
+                pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
                                 | AT91_PIT_PITIEN);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
@@ -74,7 +84,7 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
         case CLOCK_EVT_MODE_SHUTDOWN:
         case CLOCK_EVT_MODE_UNUSED:
                 /* disable irq, leaving the clocksource active */
-                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+                pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
                 break;
         case CLOCK_EVT_MODE_RESUME:
                 break;
@@ -103,11 +113,11 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 
         /* The PIT interrupt may be disabled, and is shared */
         if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
-                        && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
+                        && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
                 unsigned nr_ticks;
 
                 /* Get number of ticks performed before irq, and ack it */
-                nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+                nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
                 do {
                         pit_cnt += pit_cycle;
                         pit_clkevt.event_handler(&pit_clkevt);
@@ -129,14 +139,14 @@ static struct irqaction at91sam926x_pit_irq = {
 static void at91sam926x_pit_reset(void)
 {
         /* Disable timer and irqs */
-        at91_sys_write(AT91_PIT_MR, 0);
+        pit_write(AT91_PIT_MR, 0);
 
         /* Clear any pending interrupts, wait for PIT to stop counting */
-        while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+        while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
                 cpu_relax();
 
         /* Start PIT but don't enable IRQ */
-        at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
 /*
@@ -178,7 +188,15 @@ static void __init at91sam926x_pit_init(void)
 static void at91sam926x_pit_suspend(void)
 {
         /* Disable timer */
-        at91_sys_write(AT91_PIT_MR, 0);
+        pit_write(AT91_PIT_MR, 0);
+}
+
+void __init at91sam926x_ioremap_pit(u32 addr)
+{
+        pit_base_addr = ioremap(addr, 16);
+
+        if (!pit_base_addr)
+                panic("Impossible to ioremap PIT\n");
 }
 
 struct sys_timer at91sam926x_timer = {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ff21f7a60c6..7032dd32cdf 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <linux/dma-mapping.h>
 
 #include <asm/irq.h>
@@ -20,12 +19,12 @@
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include <mach/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -150,7 +149,7 @@ static struct clk ac97_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
         .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -209,6 +208,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
         /* One additional fake clock for ohci */
         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
@@ -231,6 +232,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_ID("pioD", &pioDE_clk),
+        CLKDEV_CON_ID("pioE", &pioDE_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -293,27 +299,22 @@ void __init at91sam9g45_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91sam9g45_gpio[] = {
+static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
         {
                 .id             = AT91SAM9G45_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
+                .regbase        = AT91SAM9G45_BASE_PIOA,
         }, {
                 .id             = AT91SAM9G45_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
+                .regbase        = AT91SAM9G45_BASE_PIOB,
         }, {
                 .id             = AT91SAM9G45_ID_PIOC,
-                .offset         = AT91_PIOC,
-                .clock          = &pioC_clk,
+                .regbase        = AT91SAM9G45_BASE_PIOC,
         }, {
                 .id             = AT91SAM9G45_ID_PIODE,
-                .offset         = AT91_PIOD,
-                .clock          = &pioDE_clk,
+                .regbase        = AT91SAM9G45_BASE_PIOD,
         }, {
                 .id             = AT91SAM9G45_ID_PIODE,
-                .offset         = AT91_PIOE,
-                .clock          = &pioDE_clk,
+                .regbase        = AT91SAM9G45_BASE_PIOE,
         }
 };
 
@@ -322,12 +323,6 @@ static void at91sam9g45_restart(char mode, const char *cmd)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
-static void at91sam9g45_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
 /* --------------------------------------------------------------------
  *  AT91SAM9G45 processor initialization
  * -------------------------------------------------------------------- */
@@ -338,10 +333,16 @@ static void __init at91sam9g45_map_io(void)
         init_consistent_dma_size(SZ_4M);
 }
 
+static void __init at91sam9g45_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+}
+
 static void __init at91sam9g45_initialize(void)
 {
         arm_pm_restart = at91sam9g45_restart;
-        pm_power_off = at91sam9g45_poweroff;
         at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 
         /* Register GPIO subsystem */
@@ -393,6 +394,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9g45_soc = {
         .map_io = at91sam9g45_map_io,
         .default_irq_priority = at91sam9g45_default_irq_priority,
+        .ioremap_registers = at91sam9g45_ioremap_registers,
         .register_clocks = at91sam9g45_register_clocks,
         .init = at91sam9g45_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 09a16d6bd5c..b7582dd10dc 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -44,8 +44,8 @@ static struct at_dma_platform_data atdma_pdata = {
 
 static struct resource hdmac_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DMA,
-                .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
+                .start  = AT91SAM9G45_BASE_DMA,
+                .end    = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -120,7 +120,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 
         /* Enable VBus control for UHP ports */
         for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                         at91_set_gpio_output(data->vbus_pin[i], 0);
         }
 
@@ -181,7 +181,7 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
 
         /* Enable VBus control for UHP ports */
         for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                         at91_set_gpio_output(data->vbus_pin[i], 0);
         }
 
@@ -263,7 +263,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 
-        if (data && data->vbus_pin > 0) {
+        if (data && gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -284,7 +284,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {}
 
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 
 static struct resource eth_resources[] = {
         [0] = {
@@ -311,12 +311,12 @@ static struct platform_device at91sam9g45_eth_device = {
         .num_resources  = ARRAY_SIZE(eth_resources),
 };
 
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
         if (!data)
                 return;
 
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                 at91_set_gpio_input(data->phy_irq_pin, 0);
                 at91_set_deglitch(data->phy_irq_pin, 1);
         }
@@ -348,7 +348,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
         platform_device_register(&at91sam9g45_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
 
 
@@ -449,11 +449,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 
 
         /* input/irq */
-        if (data->slot[0].detect_pin) {
+        if (gpio_is_valid(data->slot[0].detect_pin)) {
                 at91_set_gpio_input(data->slot[0].detect_pin, 1);
                 at91_set_deglitch(data->slot[0].detect_pin, 1);
         }
-        if (data->slot[0].wp_pin)
+        if (gpio_is_valid(data->slot[0].wp_pin))
                 at91_set_gpio_input(data->slot[0].wp_pin, 1);
 
         if (mmc_id == 0) {              /* MCI0 */
@@ -529,8 +529,8 @@ static struct resource nand_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .start  = AT91SAM9G45_BASE_ECC,
+                .end    = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -556,15 +556,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         nand_data = *data;
@@ -859,7 +859,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
         at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
 
         /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                 at91_set_gpio_output(data->reset_pin, 0);
 
         ac97_data = *data;
@@ -1009,10 +1009,24 @@ static void __init at91_add_device_tc(void) { }
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_RTC,
+                .end    = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device at91sam9g45_rtc_device = {
         .name           = "at91_rtc",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = rtc_resources,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
 };
 
 static void __init at91_add_device_rtc(void)
@@ -1081,8 +1095,8 @@ void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
 
 static struct resource rtt_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .start  = AT91SAM9G45_BASE_RTT,
+                .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -1133,10 +1147,19 @@ static void __init at91_add_device_trng(void) {}
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9G45_BASE_WDT,
+                .end    = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91sam9g45_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 
 static void __init at91_add_device_watchdog(void)
@@ -1332,8 +1355,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91SAM9G45_BASE_DBGU,
+                .end    = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 61cbb46f5b0..d6bcb1da11d 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,7 +10,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/pm.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -20,11 +19,11 @@
 #include <mach/at91sam9rl.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -184,6 +183,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_ID("pioD", &pioD_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -243,32 +246,22 @@ void __init at91sam9rl_set_console_clock(int id)
  *  GPIO
  * -------------------------------------------------------------------- */
 
-static struct at91_gpio_bank at91sam9rl_gpio[] = {
+static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
         {
                 .id             = AT91SAM9RL_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
+                .regbase        = AT91SAM9RL_BASE_PIOA,
         }, {
                 .id             = AT91SAM9RL_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
+                .regbase        = AT91SAM9RL_BASE_PIOB,
         }, {
                 .id             = AT91SAM9RL_ID_PIOC,
-                .offset         = AT91_PIOC,
-                .clock          = &pioC_clk,
+                .regbase        = AT91SAM9RL_BASE_PIOC,
         }, {
                 .id             = AT91SAM9RL_ID_PIOD,
-                .offset         = AT91_PIOD,
-                .clock          = &pioD_clk,
+                .regbase        = AT91SAM9RL_BASE_PIOD,
         }
 };
 
-static void at91sam9rl_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
 /* --------------------------------------------------------------------
  *  AT91SAM9RL processor initialization
  * -------------------------------------------------------------------- */
@@ -290,10 +283,16 @@ static void __init at91sam9rl_map_io(void)
         at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 }
 
+static void __init at91sam9rl_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
+}
+
 static void __init at91sam9rl_initialize(void)
 {
         arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9rl_poweroff;
         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
         /* Register GPIO subsystem */
@@ -345,6 +344,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9rl_soc = {
         .map_io = at91sam9rl_map_io,
         .default_irq_priority = at91sam9rl_default_irq_priority,
+        .ioremap_registers = at91sam9rl_ioremap_registers,
         .register_clocks = at91sam9rl_register_clocks,
         .init = at91sam9rl_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 628eb566d60..61908dce978 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -39,8 +39,8 @@ static struct at_dma_platform_data atdma_pdata = {
 
 static struct resource hdmac_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DMA,
-                .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
+                .start  = AT91SAM9RL_BASE_DMA,
+                .end    = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
@@ -147,7 +147,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 
-        if (data && data->vbus_pin > 0) {
+        if (data && gpio_is_valid(data->vbus_pin)) {
                 at91_set_gpio_input(data->vbus_pin, 0);
                 at91_set_deglitch(data->vbus_pin, 1);
                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -201,13 +201,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 return;
 
         /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
                 at91_set_deglitch(data->det_pin, 1);
         }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                 at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                 at91_set_gpio_output(data->vcc_pin, 0);
 
         /* CLK */
@@ -248,8 +248,8 @@ static struct resource nand_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .start  = AT91SAM9RL_BASE_ECC,
+                .end    = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -275,15 +275,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                 at91_set_gpio_output(data->enable_pin, 1);
 
         /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                 at91_set_gpio_input(data->rdy_pin, 1);
 
         /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                 at91_set_gpio_input(data->det_pin, 1);
 
         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
@@ -483,7 +483,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
         at91_set_A_periph(AT91_PIN_PD4, 0);     /* AC97RX */
 
         /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                 at91_set_gpio_output(data->reset_pin, 0);
 
         ac97_data = *data;
@@ -685,8 +685,8 @@ static void __init at91_add_device_rtc(void) {}
 
 static struct resource rtt_resources[] = {
         {
-                .start  = AT91_BASE_SYS + AT91_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .start  = AT91SAM9RL_BASE_RTT,
+                .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -709,10 +709,19 @@ static void __init at91_add_device_rtt(void)
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9RL_BASE_WDT,
+                .end    = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91sam9rl_wdt_device = {
         .name           = "at91_wdt",
         .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 
 static void __init at91_add_device_watchdog(void)
@@ -908,8 +917,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
         [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .start  = AT91SAM9RL_BASE_DBGU,
+                .end    = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 367d5cd5e36..2628384aaae 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -63,13 +63,15 @@ static void __init onearm_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata onearm_eth_data = {
+static struct macb_platform_data __initdata onearm_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata onearm_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata onearm_udc_data = {
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 4282d96dffa..3bb40694b02 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -75,6 +75,8 @@ static void __init afeb9260_init_early(void)
  */
 static struct at91_usbh_data __initdata afeb9260_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -82,7 +84,7 @@ static struct at91_usbh_data __initdata afeb9260_usbh_data = {
  */
 static struct at91_udc_data __initdata afeb9260_udc_data = {
         .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -103,7 +105,7 @@ static struct spi_board_info afeb9260_spi_devices[] = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata afeb9260_macb_data = {
+static struct macb_platform_data __initdata afeb9260_macb_data = {
         .phy_irq_pin    = AT91_PIN_PA9,
         .is_rmii        = 0,
 };
@@ -138,6 +140,7 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
         .bus_width_16   = 0,
         .parts          = afeb9260_nand_partition,
         .num_parts      = ARRAY_SIZE(afeb9260_nand_partition),
+        .det_pin        = -EINVAL,
 };
 
 
@@ -149,6 +152,7 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = {
         .wp_pin         = AT91_PIN_PC4,
         .slot_b         = 1,
         .wire4          = 1,
+        .vcc_pin        = -EINVAL,
 };
 
 
@@ -169,6 +173,8 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
 static struct at91_cf_data afeb9260_cf_data = {
         .chipselect = 4,
         .irq_pin    = AT91_PIN_PA6,
+        .det_pin        = -EINVAL,
+        .vcc_pin        = -EINVAL,
         .rst_pin    = AT91_PIN_PA7,
         .flags      = AT91_CF_TRUE_IDE,
 };
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index f90cfb32bad..8510e9e5498 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -62,6 +62,8 @@ static void __init cam60_init_early(void)
  */
 static struct at91_usbh_data __initdata cam60_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 
@@ -115,7 +117,7 @@ static struct spi_board_info cam60_spi_devices[] __initdata = {
 /*
  * MACB Ethernet device
  */
-static struct __initdata at91_eth_data cam60_macb_data = {
+static struct __initdata macb_platform_data cam60_macb_data = {
         .phy_irq_pin    = AT91_PIN_PB5,
         .is_rmii        = 0,
 };
@@ -135,7 +137,7 @@ static struct mtd_partition __initdata cam60_nand_partition[] = {
 static struct atmel_nand_data __initdata cam60_nand_data = {
         .ale            = 21,
         .cle            = 22,
-        // .det_pin     = ... not there
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PA9,
         .enable_pin     = AT91_PIN_PA7,
         .parts          = cam60_nand_partition,
@@ -163,7 +165,7 @@ static struct sam9_smc_config __initdata cam60_nand_smc_config = {
 static void __init cam60_add_device_nand(void)
 {
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &cam60_nand_smc_config);
+        sam9_smc_configure(0, 3, &cam60_nand_smc_config);
 
         at91_add_device_nand(&cam60_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 5dffd3be62d..ac3de4f7c31 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -70,6 +70,8 @@ static void __init cap9adk_init_early(void)
  */
 static struct at91_usbh_data __initdata cap9adk_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -144,16 +146,17 @@ static struct spi_board_info cap9adk_spi_devices[] = {
  */
 static struct at91_mmc_data __initdata cap9adk_mmc_data = {
         .wire4          = 1,
-//      .det_pin        = ... not connected
-//      .wp_pin         = ... not connected
-//      .vcc_pin        = ... not connected
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata cap9adk_macb_data = {
+static struct macb_platform_data __initdata cap9adk_macb_data = {
+        .phy_irq_pin    = -EINVAL,
         .is_rmii        = 1,
 };
 
@@ -172,8 +175,8 @@ static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
 static struct atmel_nand_data __initdata cap9adk_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
-//      .rdy_pin        = ... not connected
+        .det_pin        = -EINVAL,
+        .rdy_pin        = -EINVAL,
         .enable_pin     = AT91_PIN_PD15,
         .parts          = cap9adk_nand_partitions,
         .num_parts      = ARRAY_SIZE(cap9adk_nand_partitions),
@@ -212,7 +215,7 @@ static void __init cap9adk_add_device_nand(void)
                 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &cap9adk_nand_smc_config);
+        sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
 
         at91_add_device_nand(&cap9adk_nand_data);
 }
@@ -282,7 +285,7 @@ static __init void cap9adk_add_device_nor(void)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 
         /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, &cap9adk_nor_smc_config);
+        sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
 
         platform_device_register(&cap9adk_nor_flash);
 }
@@ -351,7 +354,7 @@ static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
  * AC97
  */
 static struct ac97c_platform_data cap9adk_ac97_data = {
-//      .reset_pin      = ... not connected
+        .reset_pin      = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 774c87fcbd5..59d9cf99753 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -57,13 +57,15 @@ static void __init carmeva_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata carmeva_eth_data = {
+static struct macb_platform_data __initdata carmeva_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata carmeva_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata carmeva_udc_data = {
@@ -75,8 +77,8 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
 // static struct at91_cf_data __initdata carmeva_cf_data = {
 //      .det_pin        = AT91_PIN_PB0,
 //      .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = ... not connected
-        // .vcc_pin     = ... always powered
+        // .irq_pin     = -EINVAL,
+        // .vcc_pin     = -EINVAL,
 // };
 
 static struct at91_mmc_data __initdata carmeva_mmc_data = {
@@ -84,6 +86,7 @@ static struct at91_mmc_data __initdata carmeva_mmc_data = {
         .wire4          = 1,
         .det_pin        = AT91_PIN_PB10,
         .wp_pin         = AT91_PIN_PC14,
+        .vcc_pin        = -EINVAL,
 };
 
 static struct spi_board_info carmeva_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index fc885a4ce24..9ab3d1ea326 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -86,6 +86,8 @@ static void __init cpu9krea_init_early(void)
  */
 static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -93,13 +95,14 @@ static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
  */
 static struct at91_udc_data __initdata cpu9krea_udc_data = {
         .vbus_pin       = AT91_PIN_PC8,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata cpu9krea_macb_data = {
+static struct macb_platform_data __initdata cpu9krea_macb_data = {
+        .phy_irq_pin    = -EINVAL,
         .is_rmii        = 1,
 };
 
@@ -112,6 +115,7 @@ static struct atmel_nand_data __initdata cpu9krea_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .bus_width_16   = 0,
+        .det_pin        = -EINVAL,
 };
 
 #ifdef CONFIG_MACH_CPU9260
@@ -156,7 +160,7 @@ static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
 
 static void __init cpu9krea_add_device_nand(void)
 {
-        sam9_smc_configure(3, &cpu9krea_nand_smc_config);
+        sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config);
         at91_add_device_nand(&cpu9krea_nand_data);
 }
 
@@ -238,7 +242,7 @@ static __init void cpu9krea_add_device_nor(void)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
 
         /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, &cpu9krea_nor_smc_config);
+        sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
 
         platform_device_register(&cpu9krea_nor_flash);
 }
@@ -337,6 +341,8 @@ static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
         .det_pin        = AT91_PIN_PA29,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 static void __init cpu9krea_board_init(void)
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index d35e65b08cc..368e1427ad9 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -82,12 +82,15 @@ static void __init cpuat91_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata cpuat91_eth_data = {
+static struct macb_platform_data __initdata cpuat91_eth_data = {
+        .phy_irq_pin    = -EINVAL,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata cpuat91_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata cpuat91_udc_data = {
@@ -98,6 +101,8 @@ static struct at91_udc_data __initdata cpuat91_udc_data = {
 static struct at91_mmc_data __initdata cpuat91_mmc_data = {
         .det_pin        = AT91_PIN_PC2,
         .wire4          = 1,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 static struct physmap_flash_data cpuat91_flash_data = {
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index c3936665e64..1a1547b1ce4 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -58,18 +58,20 @@ static void __init csb337_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata csb337_eth_data = {
+static struct macb_platform_data __initdata csb337_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC2,
         .is_rmii        = 0,
 };
 
 static struct at91_usbh_data __initdata csb337_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata csb337_udc_data = {
-        // this has no VBUS sensing pin
         .pullup_pin     = AT91_PIN_PA24,
+        .vbus_pin       = -EINVAL,
 };
 
 static struct i2c_board_info __initdata csb337_i2c_devices[] = {
@@ -98,6 +100,7 @@ static struct at91_mmc_data __initdata csb337_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
         .wp_pin         = AT91_PIN_PD6,
+        .vcc_pin        = -EINVAL,
 };
 
 static struct spi_board_info csb337_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 586100e2acb..f650bf39455 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -52,13 +52,15 @@ static void __init csb637_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata csb637_eth_data = {
+static struct macb_platform_data __initdata csb637_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC0,
         .is_rmii        = 0,
 };
 
 static struct at91_usbh_data __initdata csb637_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata csb637_udc_data = {
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 0b7d3277821..bb6b434ec0c 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -50,6 +50,7 @@ static void __init ek_init_early(void)
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
 };
@@ -82,7 +83,7 @@ static void __init ek_add_device_nand(void)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 45db7a3dbef..d302ca3eeb6 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -60,13 +60,15 @@ static void __init eb9200_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata eb9200_eth_data = {
+static struct macb_platform_data __initdata eb9200_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata eb9200_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata eb9200_udc_data = {
@@ -75,15 +77,18 @@ static struct at91_udc_data __initdata eb9200_udc_data = {
 };
 
 static struct at91_cf_data __initdata eb9200_cf_data = {
+        .irq_pin        = -EINVAL,
         .det_pin        = AT91_PIN_PB0,
+        .vcc_pin        = -EINVAL,
         .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = ... not connected
-        // .vcc_pin     = ... always powered
 };
 
 static struct at91_mmc_data __initdata eb9200_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 2f9c16d2921..69966ce4d77 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -64,18 +64,23 @@ static void __init ecb_at91init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata ecb_at91eth_data = {
+static struct macb_platform_data __initdata ecb_at91eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 0,
 };
 
 static struct at91_usbh_data __initdata ecb_at91usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_mmc_data __initdata ecb_at91mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 8252c722607..07ef35b0ec2 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -47,13 +47,15 @@ static void __init eco920_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata eco920_eth_data = {
+static struct macb_platform_data __initdata eco920_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC2,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata eco920_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata eco920_udc_data = {
@@ -64,6 +66,9 @@ static struct at91_udc_data __initdata eco920_udc_data = {
 static struct at91_mmc_data __initdata eco920_mmc_data = {
         .slot_b         = 0,
         .wire4          = 0,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 static struct physmap_flash_data eco920_flash_data = {
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 4c3f65d9c59..eec02cd57ce 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -52,12 +52,14 @@ static void __init flexibity_init_early(void)
 /* USB Host port */
 static struct at91_usbh_data __initdata flexibity_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /* USB Device port */
 static struct at91_udc_data __initdata flexibity_udc_data = {
         .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 /* SPI devices */
@@ -76,6 +78,7 @@ static struct at91_mmc_data __initdata flexibity_mmc_data = {
         .wire4          = 1,
         .det_pin        = AT91_PIN_PC9,
         .wp_pin         = AT91_PIN_PC4,
+        .vcc_pin        = -EINVAL,
 };
 
 /* LEDs */
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index f27d1a780cf..caf017f0f4e 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -106,6 +106,8 @@ static void __init foxg20_init_early(void)
  */
 static struct at91_usbh_data __initdata foxg20_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -113,7 +115,7 @@ static struct at91_usbh_data __initdata foxg20_usbh_data = {
  */
 static struct at91_udc_data __initdata foxg20_udc_data = {
         .vbus_pin       = AT91_PIN_PC6,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -135,7 +137,7 @@ static struct spi_board_info foxg20_spi_devices[] = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata foxg20_macb_data = {
+static struct macb_platform_data __initdata foxg20_macb_data = {
         .phy_irq_pin    = AT91_PIN_PA7,
         .is_rmii        = 1,
 };
@@ -147,6 +149,9 @@ static struct at91_eth_data __initdata foxg20_macb_data = {
 static struct at91_mmc_data __initdata foxg20_mmc_data = {
         .slot_b         = 1,
         .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 2e95949737e..230e71969fb 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -80,6 +80,8 @@ static void __init gsia18s_init_early(void)
  */
 static struct at91_usbh_data __initdata usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -87,13 +89,13 @@ static struct at91_usbh_data __initdata usbh_data = {
  */
 static struct at91_udc_data __initdata udc_data = {
         .vbus_pin       = AT91_PIN_PA22,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata macb_data = {
+static struct macb_platform_data __initdata macb_data = {
         .phy_irq_pin    = AT91_PIN_PA28,
         .is_rmii        = 1,
 };
@@ -530,6 +532,7 @@ static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
 static struct at91_cf_data __initdata gsia18s_cf1_data = {
         .irq_pin        = AT91_PIN_PA27,
         .det_pin        = AT91_PIN_PB30,
+        .vcc_pin        = -EINVAL,
         .rst_pin        = AT91_PIN_PB31,
         .chipselect     = 5,
         .flags          = AT91_CF_TRUE_IDE,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 3bae73e6363..efde1b2327c 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -61,13 +61,15 @@ static void __init kafa_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata kafa_eth_data = {
+static struct macb_platform_data __initdata kafa_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 0,
 };
 
 static struct at91_usbh_data __initdata kafa_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata kafa_udc_data = {
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index e61351ffad5..d75a4a2ad9c 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -69,13 +69,15 @@ static void __init kb9202_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata kb9202_eth_data = {
+static struct macb_platform_data __initdata kb9202_eth_data = {
         .phy_irq_pin    = AT91_PIN_PB29,
         .is_rmii        = 0,
 };
 
 static struct at91_usbh_data __initdata kb9202_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata kb9202_udc_data = {
@@ -87,6 +89,8 @@ static struct at91_mmc_data __initdata kb9202_mmc_data = {
         .det_pin        = AT91_PIN_PB2,
         .slot_b         = 0,
         .wire4          = 1,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 static struct mtd_partition __initdata kb9202_nand_partition[] = {
@@ -100,7 +104,7 @@ static struct mtd_partition __initdata kb9202_nand_partition[] = {
 static struct atmel_nand_data __initdata kb9202_nand_data = {
         .ale            = 22,
         .cle            = 21,
-        // .det_pin     = ... not there
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC29,
         .enable_pin     = AT91_PIN_PC28,
         .parts          = kb9202_nand_partition,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index ef816c17dc6..3f8617c0e04 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -72,6 +72,7 @@ static void __init neocore926_init_early(void)
 static struct at91_usbh_data __initdata neocore926_usbh_data = {
         .ports          = 2,
         .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -79,7 +80,7 @@ static struct at91_usbh_data __initdata neocore926_usbh_data = {
  */
 static struct at91_udc_data __initdata neocore926_udc_data = {
         .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -149,13 +150,14 @@ static struct at91_mmc_data __initdata neocore926_mmc_data = {
         .wire4          = 1,
         .det_pin        = AT91_PIN_PE18,
         .wp_pin         = AT91_PIN_PE19,
+        .vcc_pin        = -EINVAL,
 };
 
 
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata neocore926_macb_data = {
+static struct macb_platform_data __initdata neocore926_macb_data = {
         .phy_irq_pin    = AT91_PIN_PE31,
         .is_rmii        = 1,
 };
@@ -190,6 +192,7 @@ static struct atmel_nand_data __initdata neocore926_nand_data = {
         .enable_pin             = AT91_PIN_PD15,
         .parts                  = neocore926_nand_partition,
         .num_parts              = ARRAY_SIZE(neocore926_nand_partition),
+        .det_pin                = -EINVAL,
 };
 
 static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
@@ -213,7 +216,7 @@ static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
 static void __init neocore926_add_device_nand(void)
 {
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &neocore926_nand_smc_config);
+        sam9_smc_configure(0, 3, &neocore926_nand_smc_config);
 
         at91_add_device_nand(&neocore926_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 49e3f699b48..b4a12fc184c 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -96,9 +96,9 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
 static void __init add_device_pcontrol(void)
 {
         /* configure chip-select 4 (IO compatible to 8051  X4 ) */
-        sam9_smc_configure(4, &pcontrol_smc_config[0]);
+        sam9_smc_configure(0, 4, &pcontrol_smc_config[0]);
         /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A  D4 ) */
-        sam9_smc_configure(7, &pcontrol_smc_config[1]);
+        sam9_smc_configure(0, 7, &pcontrol_smc_config[1]);
 }
 
 
@@ -107,6 +107,8 @@ static void __init add_device_pcontrol(void)
  */
 static struct at91_usbh_data __initdata usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 
@@ -122,7 +124,7 @@ static struct at91_udc_data __initdata pcontrol_g20_udc_data = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata macb_data = {
+static struct macb_platform_data __initdata macb_data = {
         .phy_irq_pin    = AT91_PIN_PA28,
         .is_rmii        = 1,
 };
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 0a8fe6a1b7c..ab024fa11d5 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -60,13 +60,15 @@ static void __init picotux200_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata picotux200_eth_data = {
+static struct macb_platform_data __initdata picotux200_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata picotux200_usbh_data = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_mmc_data __initdata picotux200_mmc_data = {
@@ -74,6 +76,7 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
         .wp_pin         = AT91_PIN_PA17,
+        .vcc_pin        = -EINVAL,
 };
 
 #define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 07421bdb88e..e029d220cb8 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -77,6 +77,8 @@ static void __init ek_init_early(void)
  */
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -84,7 +86,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 /*
@@ -104,7 +106,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PA31,
         .is_rmii        = 1,
 };
@@ -133,7 +135,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .parts          = ek_nand_partition,
@@ -161,7 +163,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -172,9 +174,9 @@ static void __init ek_add_device_nand(void)
 static struct at91_mmc_data __initdata ek_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
-//      .det_pin        = ... not connected
-//      .wp_pin         = ... not connected
-//      .vcc_pin        = ... not connected
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 /*
@@ -251,7 +253,7 @@ static void __init ek_board_init(void)
         /* LEDs */
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
         /* shutdown controller, wakeup button (5 msec low) */
-        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+        at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
                                 | AT91_SHDW_RTTWKEN);
 }
 
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 80a8c9c6e92..782f37946af 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -65,13 +65,15 @@ static void __init dk_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata dk_eth_data = {
+static struct macb_platform_data __initdata dk_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata dk_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata dk_udc_data = {
@@ -80,16 +82,19 @@ static struct at91_udc_data __initdata dk_udc_data = {
 };
 
 static struct at91_cf_data __initdata dk_cf_data = {
+        .irq_pin        = -EINVAL,
         .det_pin        = AT91_PIN_PB0,
+        .vcc_pin        = -EINVAL,
         .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = ... not connected
-        // .vcc_pin     = ... always powered
 };
 
 #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
 static struct at91_mmc_data __initdata dk_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif
 
@@ -143,7 +148,7 @@ static struct atmel_nand_data __initdata dk_nand_data = {
         .cle            = 21,
         .det_pin        = AT91_PIN_PB1,
         .rdy_pin        = AT91_PIN_PC2,
-        // .enable_pin  = ... not there
+        .enable_pin     = -EINVAL,
         .parts          = dk_nand_partition,
         .num_parts      = ARRAY_SIZE(dk_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 99fd7f8aee0..ef7c12a9224 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -65,13 +65,15 @@ static void __init ek_init_early(void)
         at91_set_serial_console(0);
 }
 
-static struct at91_eth_data __initdata ek_eth_data = {
+static struct macb_platform_data __initdata ek_eth_data = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
 
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata ek_udc_data = {
@@ -85,6 +87,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
         .wp_pin         = AT91_PIN_PA17,
+        .vcc_pin        = -EINVAL,
 };
 #endif
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index e927df0175d..af0750fafa2 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -60,7 +60,7 @@ static void __init rsi_ews_init_early(void)
 /*
  * Ethernet
  */
-static struct at91_eth_data rsi_ews_eth_data __initdata = {
+static struct macb_platform_data rsi_ews_eth_data __initdata = {
         .phy_irq_pin    = AT91_PIN_PC4,
         .is_rmii        = 1,
 };
@@ -70,6 +70,8 @@ static struct at91_eth_data rsi_ews_eth_data __initdata = {
  */
 static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
         .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 072d53af98d..84bce587735 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -72,6 +72,8 @@ static void __init ek_init_early(void)
  */
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -79,7 +81,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -109,7 +111,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PA7,
         .is_rmii        = 0,
 };
@@ -134,7 +136,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .parts          = ek_nand_partition,
@@ -162,7 +164,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -176,7 +178,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
         .wire4          = 1,
         .det_pin        = AT91_PIN_PC8,
         .wp_pin         = AT91_PIN_PC4,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
 
 static void __init ek_board_init(void)
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 4f10181a078..be8233bcabd 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -75,6 +75,8 @@ static void __init ek_init_early(void)
  */
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -82,7 +84,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -151,7 +153,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PA7,
         .is_rmii        = 1,
 };
@@ -176,7 +178,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .parts          = ek_nand_partition,
@@ -211,7 +213,7 @@ static void __init ek_add_device_nand(void)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -223,9 +225,9 @@ static void __init ek_add_device_nand(void)
 static struct at91_mmc_data __initdata ek_mmc_data = {
         .slot_b         = 1,
         .wire4          = 1,
-//      .det_pin        = ... not connected
-//      .wp_pin         = ... not connected
-//      .vcc_pin        = ... not connected
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b005b738e8f..40895072a1a 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -131,7 +131,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
 static void __init ek_add_device_dm9000(void)
 {
         /* Configure chip-select 2 (DM9000) */
-        sam9_smc_configure(2, &dm9000_smc_config);
+        sam9_smc_configure(0, 2, &dm9000_smc_config);
 
         /* Configure Reset signal as output */
         at91_set_gpio_output(AT91_PIN_PC10, 0);
@@ -151,6 +151,8 @@ static void __init ek_add_device_dm9000(void) {}
  */
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 
@@ -159,7 +161,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PB29,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -182,7 +184,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 22,
         .cle            = 21,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC15,
         .enable_pin     = AT91_PIN_PC14,
         .parts          = ek_nand_partition,
@@ -217,7 +219,7 @@ static void __init ek_add_device_nand(void)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -345,6 +347,9 @@ static struct spi_board_info ek_spi_devices[] = {
  */
 static struct at91_mmc_data __initdata ek_mmc_data = {
         .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 #endif /* CONFIG_SPI_ATMEL_* */
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index bccdcf23caa..29f66052fe6 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -74,6 +74,7 @@ static void __init ek_init_early(void)
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
         .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -81,7 +82,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -151,14 +152,14 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
         .wire4          = 1,
         .det_pin        = AT91_PIN_PE18,
         .wp_pin         = AT91_PIN_PE19,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
 
 
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PE31,
         .is_rmii        = 1,
 };
@@ -183,7 +184,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
         .parts          = ek_nand_partition,
@@ -218,7 +219,7 @@ static void __init ek_add_device_nand(void)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -353,6 +354,7 @@ static void __init ek_add_device_buttons(void) {}
  * reset_pin is not connected: NRST
  */
 static struct ac97c_platform_data ek_ac97_data = {
+        .reset_pin      = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 64fc75c9d0a..843d6286c6f 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -86,6 +86,8 @@ static void __init ek_init_early(void)
  */
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -93,7 +95,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
@@ -123,7 +125,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PA7,
         .is_rmii        = 1,
 };
@@ -163,6 +165,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .cle            = 22,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
+        .det_pin        = -EINVAL,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
@@ -195,7 +198,7 @@ static void __init ek_add_device_nand(void)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -210,6 +213,7 @@ static struct mci_platform_data __initdata ek_mmc_data = {
         .slot[1] = {
                 .bus_width      = 4,
                 .detect_pin     = AT91_PIN_PC9,
+                .wp_pin         = -EINVAL,
         },
 
 };
@@ -218,6 +222,8 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
         .slot_b         = 1,    /* Only one slot so use slot B */
         .wire4          = 1,
         .det_pin        = AT91_PIN_PC9,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif
 
@@ -227,6 +233,7 @@ static void __init ek_add_device_mmc(void)
         if (ek_have_2mmc()) {
                 ek_mmc_data.slot[0].bus_width = 4;
                 ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
+                ek_mmc_data.slot[0].wp_pin = -1;
         }
         at91_add_device_mci(0, &ek_mmc_data);
 #else
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 92de9127923..ea0d1b9c2b7 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -69,6 +69,7 @@ static void __init ek_init_early(void)
 static struct at91_usbh_data __initdata ek_usbh_hs_data = {
         .ports          = 2,
         .vbus_pin       = {AT91_PIN_PD1, AT91_PIN_PD3},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 
@@ -100,6 +101,7 @@ static struct mci_platform_data __initdata mci0_data = {
         .slot[0] = {
                 .bus_width      = 4,
                 .detect_pin     = AT91_PIN_PD10,
+                .wp_pin         = -EINVAL,
         },
 };
 
@@ -115,7 +117,7 @@ static struct mci_platform_data __initdata mci1_data = {
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PD5,
         .is_rmii        = 1,
 };
@@ -143,6 +145,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .cle            = 22,
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
+        .det_pin        = -EINVAL,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
@@ -175,7 +178,7 @@ static void __init ek_add_device_nand(void)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -330,6 +333,7 @@ static void __init ek_add_device_buttons(void) {}
  * reset_pin is not connected: NRST
  */
 static struct ac97c_platform_data ek_ac97_data = {
+        .reset_pin      = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index b2b748239f3..c1366d0032b 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -67,8 +67,8 @@ static struct usba_platform_data __initdata ek_usba_udc_data = {
 static struct at91_mmc_data __initdata ek_mmc_data = {
         .wire4          = 1,
         .det_pin        = AT91_PIN_PA15,
-//      .wp_pin         = ... not connected
-//      .vcc_pin        = ... not connected
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 
@@ -91,7 +91,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PD17,
         .enable_pin     = AT91_PIN_PB6,
         .parts          = ek_nand_partition,
@@ -119,7 +119,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -204,6 +204,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
  * reset_pin is not connected: NRST
  */
 static struct ac97c_platform_data ek_ac97_data = {
+        .reset_pin      = -EINVAL,
 };
 
 
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 0df01c6e2d0..4770db08e5a 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -57,15 +57,19 @@ static void __init snapper9260_init_early(void)
 
 static struct at91_usbh_data __initdata snapper9260_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 static struct at91_udc_data __initdata snapper9260_udc_data = {
         .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
         .vbus_active_low        = 1,
         .vbus_polled            = 1,
+        .pullup_pin             = -EINVAL,
 };
 
-static struct at91_eth_data snapper9260_macb_data = {
+static struct macb_platform_data snapper9260_macb_data = {
+        .phy_irq_pin    = -EINVAL,
         .is_rmii        = 1,
 };
 
@@ -104,6 +108,8 @@ static struct atmel_nand_data __initdata snapper9260_nand_data = {
         .parts          = snapper9260_nand_partitions,
         .num_parts      = ARRAY_SIZE(snapper9260_nand_partitions),
         .bus_width_16   = 0,
+        .enable_pin     = -EINVAL,
+        .det_pin        = -EINVAL,
 };
 
 static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
@@ -149,7 +155,7 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
 static void __init snapper9260_add_device_nand(void)
 {
         at91_set_A_periph(AT91_PIN_PC14, 0);
-        sam9_smc_configure(3, &snapper9260_nand_smc_config);
+        sam9_smc_configure(0, 3, &snapper9260_nand_smc_config);
         at91_add_device_nand(&snapper9260_nand_data);
 }
 
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 936e5fd7f40..72eb3b4d9ab 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -85,6 +85,7 @@ static struct atmel_nand_data __initdata nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .bus_width_16   = 0,
+        .det_pin        = -EINVAL,
 };
 
 static struct sam9_smc_config __initdata nand_smc_config = {
@@ -108,7 +109,7 @@ static struct sam9_smc_config __initdata nand_smc_config = {
 static void __init add_device_nand(void)
 {
         /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &nand_smc_config);
+        sam9_smc_configure(0, 3, &nand_smc_config);
 
         at91_add_device_nand(&nand_data);
 }
@@ -122,12 +123,17 @@ static void __init add_device_nand(void)
 static struct mci_platform_data __initdata mmc_data = {
         .slot[0] = {
                 .bus_width      = 4,
+                .detect_pin     = -1,
+                .wp_pin         = -1,
         },
 };
 #else
 static struct at91_mmc_data __initdata mmc_data = {
         .slot_b         = 0,
         .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif
 
@@ -137,6 +143,8 @@ static struct at91_mmc_data __initdata mmc_data = {
  */
 static struct at91_usbh_data __initdata usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 
@@ -145,19 +153,19 @@ static struct at91_usbh_data __initdata usbh_data = {
  */
 static struct at91_udc_data __initdata portuxg20_udc_data = {
         .vbus_pin       = AT91_PIN_PC7,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
         .vbus_pin       = AT91_PIN_PA22,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata macb_data = {
+static struct macb_platform_data __initdata macb_data = {
         .phy_irq_pin    = AT91_PIN_PA28,
         .is_rmii        = 1,
 };
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 0a20bab21f9..26c36fc2d1e 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -66,6 +66,8 @@ static void __init ek_init_early(void)
  */
 static struct at91_usbh_data __initdata ek_usbh_data = {
         .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -73,7 +75,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
  */
 static struct at91_udc_data __initdata ek_udc_data = {
         .vbus_pin       = AT91_PIN_PB11,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
 static void __init ek_add_device_udc(void)
@@ -146,7 +148,7 @@ static void __init ek_add_device_spi(void)
 /*
  * MACB Ethernet device
  */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
         .phy_irq_pin    = AT91_PIN_PE31,
         .is_rmii        = 1,
 };
@@ -193,7 +195,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
         .ale            = 21,
         .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
         .parts          = ek_nand_partition,
@@ -245,9 +247,9 @@ static void __init ek_add_device_nand(void)
 
         /* configure chip-select 3 (NAND) */
         if (machine_is_usb_a9g20())
-                sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
+                sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
         else
-                sam9_smc_configure(3, &usb_a9260_nand_smc_config);
+                sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
 
         at91_add_device_nand(&ek_nand_data);
 }
@@ -344,7 +346,7 @@ static void __init ek_board_init(void)
                 /* I2C */
                 at91_add_device_i2c(NULL, 0);
                 /* shutdown controller, wakeup button (5 msec low) */
-                at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
+                at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
                                 | AT91_SHDW_WKMODE0_LOW
                                 | AT91_SHDW_RTTWKEN);
         }
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 12a3f955162..bbd553e1cd9 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -110,7 +110,7 @@ static struct gpio_led yl9200_leds[] = {
 /*
  * Ethernet
  */
-static struct at91_eth_data __initdata yl9200_eth_data = {
+static struct macb_platform_data __initdata yl9200_eth_data = {
         .phy_irq_pin            = AT91_PIN_PB28,
         .is_rmii                = 1,
 };
@@ -120,6 +120,8 @@ static struct at91_eth_data __initdata yl9200_eth_data = {
  */
 static struct at91_usbh_data __initdata yl9200_usbh_data = {
         .ports                  = 1,    /* PQFP version of AT91RM9200 */
+        .vbus_pin               = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
 /*
@@ -137,8 +139,9 @@ static struct at91_udc_data __initdata yl9200_udc_data = {
  */
 static struct at91_mmc_data __initdata yl9200_mmc_data = {
         .det_pin        = AT91_PIN_PB9,
-        // .wp_pin      = ... not connected
         .wire4          = 1,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 
 /*
@@ -175,7 +178,7 @@ static struct mtd_partition __initdata yl9200_nand_partition[] = {
 static struct atmel_nand_data __initdata yl9200_nand_data = {
         .ale            = 6,
         .cle            = 7,
-        // .det_pin     = ... not connected
+        .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
         .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
         .parts          = yl9200_nand_partition,
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 7f4503bc4cb..4866b8180d6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,6 +29,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
  /* Timer */
 struct sys_timer;
 extern struct sys_timer at91rm9200_timer;
+extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
 extern struct sys_timer at91x40_timer;
 
@@ -59,14 +60,16 @@ extern void at91_irq_resume(void);
 /* reset */
 extern void at91sam9_alt_restart(char, const char *);
 
+/* shutdown */
+extern void at91_ioremap_shdwc(u32 base_addr);
+
  /* GPIO */
 #define AT91RM9200_PQFP         3       /* AT91RM9200 PQFP package has 3 banks */
 #define AT91RM9200_BGA          4       /* AT91RM9200 BGA package has 4 banks */
 
 struct at91_gpio_bank {
         unsigned short id;              /* peripheral ID */
-        unsigned long offset;           /* offset from system peripheral base */
-        struct clk *clock;              /* associated clock */
+        unsigned long regbase;          /* offset from system peripheral base */
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 224e9e2f867..74d6783eeab 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -29,8 +29,9 @@
 struct at91_gpio_chip {
         struct gpio_chip        chip;
         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-        struct at91_gpio_bank   *bank;          /* Bank definition */
+        int                     id;             /* ID of register bank */
         void __iomem            *regbase;       /* Base of register bank */
+        struct clk              *clock;         /* associated clock */
 };
 
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -58,18 +59,17 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
         }
 
 static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
-        AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
-        AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
-        AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
-        AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("pioA", 0x00, 32),
+        AT91_GPIO_CHIP("pioB", 0x20, 32),
+        AT91_GPIO_CHIP("pioC", 0x40, 32),
+        AT91_GPIO_CHIP("pioD", 0x60, 32),
+        AT91_GPIO_CHIP("pioE", 0x80, 32),
 };
 
 static int gpio_banks;
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
-        pin -= PIN_BASE;
         pin /= 32;
         if (likely(pin < gpio_banks))
                 return gpio_chip[pin].regbase;
@@ -79,7 +79,6 @@ static inline void __iomem *pin_to_controller(unsigned pin)
 
 static inline unsigned pin_to_mask(unsigned pin)
 {
-        pin -= PIN_BASE;
         return 1 << (pin % 32);
 }
 
@@ -274,8 +273,9 @@ static u32 backups[MAX_GPIO_BANKS];
 
 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-        unsigned        mask = pin_to_mask(d->irq);
-        unsigned        bank = (d->irq - PIN_BASE) / 32;
+        unsigned        pin = irq_to_gpio(d->irq);
+        unsigned        mask = pin_to_mask(pin);
+        unsigned        bank = pin / 32;
 
         if (unlikely(bank >= MAX_GPIO_BANKS))
                 return -EINVAL;
@@ -285,7 +285,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
         else
                 wakeups[bank] &= ~mask;
 
-        irq_set_irq_wake(gpio_chip[bank].bank->id, state);
+        irq_set_irq_wake(gpio_chip[bank].id, state);
 
         return 0;
 }
@@ -302,7 +302,7 @@ void at91_gpio_suspend(void)
                 __raw_writel(wakeups[i], pio + PIO_IER);
 
                 if (!wakeups[i])
-                        clk_disable(gpio_chip[i].bank->clock);
+                        clk_disable(gpio_chip[i].clock);
                 else {
 #ifdef CONFIG_PM_DEBUG
                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
@@ -319,7 +319,7 @@ void at91_gpio_resume(void)
                 void __iomem    *pio = gpio_chip[i].regbase;
 
                 if (!wakeups[i])
-                        clk_enable(gpio_chip[i].bank->clock);
+                        clk_enable(gpio_chip[i].clock);
 
                 __raw_writel(wakeups[i], pio + PIO_IDR);
                 __raw_writel(backups[i], pio + PIO_IER);
@@ -344,8 +344,9 @@ void at91_gpio_resume(void)
 
 static void gpio_irq_mask(struct irq_data *d)
 {
-        void __iomem    *pio = pin_to_controller(d->irq);
-        unsigned        mask = pin_to_mask(d->irq);
+        unsigned        pin = irq_to_gpio(d->irq);
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IDR);
@@ -353,8 +354,9 @@ static void gpio_irq_mask(struct irq_data *d)
 
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        void __iomem    *pio = pin_to_controller(d->irq);
-        unsigned        mask = pin_to_mask(d->irq);
+        unsigned        pin = irq_to_gpio(d->irq);
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IER);
@@ -382,7 +384,7 @@ static struct irq_chip gpio_irqchip = {
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        unsigned        pin;
+        unsigned        irq_pin;
         struct irq_data *idata = irq_desc_get_irq_data(desc);
         struct irq_chip *chip = irq_data_get_irq_chip(idata);
         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
@@ -405,12 +407,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         continue;
                 }
 
-                pin = at91_gpio->chip.base;
+                irq_pin = gpio_to_irq(at91_gpio->chip.base);
 
                 while (isr) {
                         if (isr & 1)
-                                generic_handle_irq(pin);
-                        pin++;
+                                generic_handle_irq(irq_pin);
+                        irq_pin++;
                         isr >>= 1;
                 }
         }
@@ -438,7 +440,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
                 seq_printf(s, "%i:\t", j);
 
                 for (bank = 0; bank < gpio_banks; bank++) {
-                        unsigned        pin  = PIN_BASE + (32 * bank) + j;
+                        unsigned        pin  = (32 * bank) + j;
                         void __iomem    *pio = pin_to_controller(pin);
                         unsigned        mask = pin_to_mask(pin);
 
@@ -491,27 +493,28 @@ static struct lock_class_key gpio_lock_class;
  */
 void __init at91_gpio_irq_setup(void)
 {
-        unsigned                pioc, pin;
+        unsigned                pioc, irq = gpio_to_irq(0);
         struct at91_gpio_chip   *this, *prev;
 
-        for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
+        for (pioc = 0, this = gpio_chip, prev = NULL;
                         pioc++ < gpio_banks;
                         prev = this, this++) {
-                unsigned        id = this->bank->id;
+                unsigned        id = this->id;
                 unsigned        i;
 
                 __raw_writel(~0, this->regbase + PIO_IDR);
 
-                for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
-                        irq_set_lockdep_class(pin, &gpio_lock_class);
+                for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
+                     i++, irq++) {
+                        irq_set_lockdep_class(irq, &gpio_lock_class);
 
                         /*
                          * Can use the "simple" and not "edge" handler since it's
                          * shorter, and the AIC handles interrupts sanely.
                          */
-                        irq_set_chip_and_handler(pin, &gpio_irqchip,
+                        irq_set_chip_and_handler(irq, &gpio_irqchip,
                                                  handle_simple_irq);
-                        set_irq_flags(pin, IRQF_VALID);
+                        set_irq_flags(irq, IRQF_VALID);
                 }
 
                 /* The toplevel handler handles one bank of GPIOs, except
@@ -524,7 +527,7 @@ void __init at91_gpio_irq_setup(void)
                 irq_set_chip_data(id, this);
                 irq_set_chained_handler(id, gpio_irq_handler);
         }
-        pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
+        pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
 }
 
 /* gpiolib support */
@@ -612,16 +615,26 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
         for (i = 0; i < nr_banks; i++) {
                 at91_gpio = &gpio_chip[i];
 
-                at91_gpio->bank = &data[i];
-                at91_gpio->chip.base = PIN_BASE + i * 32;
-                at91_gpio->regbase = at91_gpio->bank->offset +
-                        (void __iomem *)AT91_VA_BASE_SYS;
+                at91_gpio->id = data[i].id;
+                at91_gpio->chip.base = i * 32;
+
+                at91_gpio->regbase = ioremap(data[i].regbase, 512);
+                if (!at91_gpio->regbase) {
+                        pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
+                        continue;
+                }
+
+                at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+                if (!at91_gpio->clock) {
+                        pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
+                        continue;
+                }
 
                 /* enable PIO controller's clock */
-                clk_enable(at91_gpio->bank->clock);
+                clk_enable(at91_gpio->clock);
 
                 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
-                if (last && last->bank->id == at91_gpio->bank->id)
+                if (last && last->id == at91_gpio->id)
                         last->next = at91_gpio;
                 last = at91_gpio;
 
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 03566799d3b..3045781c473 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -16,7 +16,19 @@
 #ifndef AT91_AIC_H
 #define AT91_AIC_H
 
-#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_aic_base;
+
+#define at91_aic_read(field) \
+        __raw_readl(at91_aic_base + field)
+
+#define at91_aic_write(field, value) \
+        __raw_writel(value, at91_aic_base + field);
+#else
+.extern at91_aic_base
+#endif
+
+#define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
 #define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
 #define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
 #define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
@@ -24,30 +36,30 @@
 #define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
 #define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
 
-#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
-#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
+#define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
 #define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
 
-#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
-#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
-#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
+#define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
+#define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
 #define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
 #define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
 
-#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
-#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
-#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
+#define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR            0x138                   /* Debug Control Register */
 #define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
 #define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
 
-#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
+#define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index dbfe455a4c4..2aa0c5e1349 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -19,7 +19,7 @@
 #define dbgu_readl(dbgu, field) \
         __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
 
-#ifdef AT91_DBGU
+#if !defined(CONFIG_ARCH_AT91X40)
 #define AT91_DBGU_CR            (0x00)  /* Control Register */
 #define AT91_DBGU_MR            (0x04)  /* Mode Register */
 #define AT91_DBGU_IER           (0x08)  /* Interrupt Enable Register */
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 974d0bd05b5..d1f80ad7f4d 100644
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -16,16 +16,16 @@
 #ifndef AT91_PIT_H
 #define AT91_PIT_H
 
-#define AT91_PIT_MR             (AT91_PIT + 0x00)       /* Mode Register */
+#define AT91_PIT_MR             0x00                    /* Mode Register */
 #define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
 #define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
 #define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
 
-#define AT91_PIT_SR             (AT91_PIT + 0x04)       /* Status Register */
+#define AT91_PIT_SR             0x04                    /* Status Register */
 #define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
 
-#define AT91_PIT_PIVR           (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
-#define AT91_PIT_PIIR           (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
+#define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
 #define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
 #define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
 
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
index e56f4701a3e..da1945e5f71 100644
--- a/arch/arm/mach-at91/include/mach/at91_rtc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -16,7 +16,7 @@
 #ifndef AT91_RTC_H
 #define AT91_RTC_H
 
-#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define AT91_RTC_CR             0x00                    /* Control Register */
 #define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
 #define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
 #define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
@@ -29,44 +29,44 @@
 #define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
 #define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
 
-#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define AT91_RTC_MR             0x04                    /* Mode Register */
 #define                 AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
 
-#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define AT91_RTC_TIMR           0x08                    /* Time Register */
 #define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
 #define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
 #define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
 #define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
 
-#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define AT91_RTC_CALR           0x0c                    /* Calendar Register */
 #define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
 #define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
 #define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
 #define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
 #define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
 
-#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define AT91_RTC_TIMALR         0x10                    /* Time Alarm Register */
 #define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
 #define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
 #define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
 
-#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define AT91_RTC_CALALR         0x14                    /* Calendar Alarm Register */
 #define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
 #define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
 
-#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define AT91_RTC_SR             0x18                    /* Status Register */
 #define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
 #define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
 #define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
 #define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
 #define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
 
-#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
-#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
-#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
-#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+#define AT91_RTC_SCCR           0x1c                    /* Status Clear Command Register */
+#define AT91_RTC_IER            0x20                    /* Interrupt Enable Register */
+#define AT91_RTC_IDR            0x24                    /* Interrupt Disable Register */
+#define AT91_RTC_IMR            0x28                    /* Interrupt Mask Register */
 
-#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define AT91_RTC_VER            0x2c                    /* Valid Entry Register */
 #define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
 #define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
 #define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index c4ce07e8a8f..1d4fe822c77 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -16,11 +16,21 @@
 #ifndef AT91_SHDWC_H
 #define AT91_SHDWC_H
 
-#define AT91_SHDW_CR            (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_shdwc_base;
+
+#define at91_shdwc_read(field) \
+        __raw_readl(at91_shdwc_base + field)
+
+#define at91_shdwc_write(field, value) \
+        __raw_writel(value, at91_shdwc_base + field);
+#endif
+
+#define AT91_SHDW_CR            0x00                    /* Shut Down Control Register */
 #define         AT91_SHDW_SHDW          (1    << 0)             /* Shut Down command */
 #define         AT91_SHDW_KEY           (0xa5 << 24)            /* KEY Password */
 
-#define AT91_SHDW_MR            (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
+#define AT91_SHDW_MR            0x04                    /* Shut Down Mode Register */
 #define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
 #define                 AT91_SHDW_WKMODE0_NONE          0
 #define                 AT91_SHDW_WKMODE0_HIGH          1
@@ -30,7 +40,7 @@
 #define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
 #define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
 
-#define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
+#define AT91_SHDW_SR            0x08                    /* Shut Down Status Register */
 #define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
 #define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
 #define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index c5df1e8f195..4c0e2f6011d 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -79,29 +79,28 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
 #define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
 #define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (cpu_is_at91cap9_revB() ?       \
                         (0xfffffd50 - AT91_BASE_SYS) :  \
                         (0xfffffd60 - AT91_BASE_SYS))
 
+#define AT91CAP9_BASE_ECC       0xffffe200
+#define AT91CAP9_BASE_DMA       0xffffec00
+#define AT91CAP9_BASE_SMC       0xffffe800
+#define AT91CAP9_BASE_DBGU      AT91_BASE_DBGU1
+#define AT91CAP9_BASE_PIOA      0xfffff200
+#define AT91CAP9_BASE_PIOB      0xfffff400
+#define AT91CAP9_BASE_PIOC      0xfffff600
+#define AT91CAP9_BASE_PIOD      0xfffff800
+#define AT91CAP9_BASE_SHDWC     0xfffffd10
+#define AT91CAP9_BASE_RTT       0xfffffd20
+#define AT91CAP9_BASE_PIT       0xfffffd30
+#define AT91CAP9_BASE_WDT       0xfffffd40
+
 #define AT91_USART0     AT91CAP9_BASE_US0
 #define AT91_USART1     AT91CAP9_BASE_US1
 #define AT91_USART2     AT91CAP9_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index e4037b50030..bacb5114181 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -79,17 +79,17 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
-#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
 #define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
-#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
 #define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
 
+#define AT91RM9200_BASE_DBGU    AT91_BASE_DBGU0 /* Debug Unit */
+#define AT91RM9200_BASE_PIOA    0xfffff400      /* PIO Controller A */
+#define AT91RM9200_BASE_PIOB    0xfffff600      /* PIO Controller B */
+#define AT91RM9200_BASE_PIOC    0xfffff800      /* PIO Controller C */
+#define AT91RM9200_BASE_PIOD    0xfffffa00      /* PIO Controller D */
+#define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
+
 #define AT91_USART0     AT91RM9200_BASE_US0
 #define AT91_USART1     AT91RM9200_BASE_US1
 #define AT91_USART2     AT91RM9200_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 9a791165913..f937c476bb6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -80,24 +80,23 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
 
+#define AT91SAM9260_BASE_ECC    0xffffe800
+#define AT91SAM9260_BASE_SMC    0xffffec00
+#define AT91SAM9260_BASE_DBGU   AT91_BASE_DBGU0
+#define AT91SAM9260_BASE_PIOA   0xfffff400
+#define AT91SAM9260_BASE_PIOB   0xfffff600
+#define AT91SAM9260_BASE_PIOC   0xfffff800
+#define AT91SAM9260_BASE_SHDWC  0xfffffd10
+#define AT91SAM9260_BASE_RTT    0xfffffd20
+#define AT91SAM9260_BASE_PIT    0xfffffd30
+#define AT91SAM9260_BASE_WDT    0xfffffd40
+
 #define AT91_USART0     AT91SAM9260_BASE_US0
 #define AT91_USART1     AT91SAM9260_BASE_US1
 #define AT91_USART2     AT91SAM9260_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index ce596204cef..175604e261b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -66,21 +66,21 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
 
+#define AT91SAM9261_BASE_SMC    0xffffec00
+#define AT91SAM9261_BASE_DBGU   AT91_BASE_DBGU0
+#define AT91SAM9261_BASE_PIOA   0xfffff400
+#define AT91SAM9261_BASE_PIOB   0xfffff600
+#define AT91SAM9261_BASE_PIOC   0xfffff800
+#define AT91SAM9261_BASE_SHDWC  0xfffffd10
+#define AT91SAM9261_BASE_RTT    0xfffffd20
+#define AT91SAM9261_BASE_PIT    0xfffffd30
+#define AT91SAM9261_BASE_WDT    0xfffffd40
+
 #define AT91_USART0     AT91SAM9261_BASE_US0
 #define AT91_USART1     AT91SAM9261_BASE_US1
 #define AT91_USART2     AT91SAM9261_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index f1b92961a2b..80c915002d8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -74,30 +74,29 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_ECC0       (0xffffe000 - AT91_BASE_SYS)
 #define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SMC0       (0xffffe400 - AT91_BASE_SYS)
-#define AT91_ECC1       (0xffffe600 - AT91_BASE_SYS)
 #define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC1       (0xffffea00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffed10 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT0       (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_RTT1       (0xfffffd50 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
 
+#define AT91SAM9263_BASE_ECC0   0xffffe000
+#define AT91SAM9263_BASE_SMC0   0xffffe400
+#define AT91SAM9263_BASE_ECC1   0xffffe600
+#define AT91SAM9263_BASE_SMC1   0xffffea00
+#define AT91SAM9263_BASE_DBGU   AT91_BASE_DBGU1
+#define AT91SAM9263_BASE_PIOA   0xfffff200
+#define AT91SAM9263_BASE_PIOB   0xfffff400
+#define AT91SAM9263_BASE_PIOC   0xfffff600
+#define AT91SAM9263_BASE_PIOD   0xfffff800
+#define AT91SAM9263_BASE_PIOE   0xfffffa00
+#define AT91SAM9263_BASE_SHDWC  0xfffffd10
+#define AT91SAM9263_BASE_RTT0   0xfffffd20
+#define AT91SAM9263_BASE_PIT    0xfffffd30
+#define AT91SAM9263_BASE_WDT    0xfffffd40
+#define AT91SAM9263_BASE_RTT1   0xfffffd50
+
 #define AT91_USART0     AT91SAM9263_BASE_US0
 #define AT91_USART1     AT91SAM9263_BASE_US1
 #define AT91_USART2     AT91SAM9263_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index 57de6207e57..eb18a70fa64 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,7 +16,9 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
-#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#include <mach/cpu.h>
+
+#define AT91_SMC_SETUP          0x00                            /* Setup Register for CS n */
 #define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
 #define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
 #define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
@@ -26,7 +28,7 @@
 #define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
 #define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
 
-#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define AT91_SMC_PULSE          0x04                            /* Pulse Register for CS n */
 #define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
 #define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
 #define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
@@ -36,13 +38,13 @@
 #define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
 #define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
 
-#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define AT91_SMC_CYCLE          0x08                            /* Cycle Register for CS n */
 #define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
 #define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
 #define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
 #define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
 
-#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define AT91_SMC_MODE           0x0c                            /* Mode Register for CS n */
 #define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
 #define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
 #define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
@@ -66,11 +68,4 @@
 #define                 AT91_SMC_PS_16                  (2 << 28)
 #define                 AT91_SMC_PS_32                  (3 << 28)
 
-#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 406bb649680..f0c23c960de 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -86,27 +86,27 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
 #define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
 #define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC        (0xfffffdb0 - AT91_BASE_SYS)
+
+#define AT91SAM9G45_BASE_ECC    0xffffe200
+#define AT91SAM9G45_BASE_DMA    0xffffec00
+#define AT91SAM9G45_BASE_SMC    0xffffe800
+#define AT91SAM9G45_BASE_DBGU   AT91_BASE_DBGU1
+#define AT91SAM9G45_BASE_PIOA   0xfffff200
+#define AT91SAM9G45_BASE_PIOB   0xfffff400
+#define AT91SAM9G45_BASE_PIOC   0xfffff600
+#define AT91SAM9G45_BASE_PIOD   0xfffff800
+#define AT91SAM9G45_BASE_PIOE   0xfffffa00
+#define AT91SAM9G45_BASE_SHDWC  0xfffffd10
+#define AT91SAM9G45_BASE_RTT    0xfffffd20
+#define AT91SAM9G45_BASE_PIT    0xfffffd30
+#define AT91SAM9G45_BASE_WDT    0xfffffd40
+#define AT91SAM9G45_BASE_RTC    0xfffffdb0
 
 #define AT91_USART0     AT91SAM9G45_BASE_US0
 #define AT91_USART1     AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 1aabacd315d..2bb359e60b9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,27 +69,26 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_DMA        (0xffffe600 - AT91_BASE_SYS)
-#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)
+
+#define AT91SAM9RL_BASE_DMA     0xffffe600
+#define AT91SAM9RL_BASE_ECC     0xffffe800
+#define AT91SAM9RL_BASE_SMC     0xffffec00
+#define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
+#define AT91SAM9RL_BASE_PIOA    0xfffff400
+#define AT91SAM9RL_BASE_PIOB    0xfffff600
+#define AT91SAM9RL_BASE_PIOC    0xfffff800
+#define AT91SAM9RL_BASE_PIOD    0xfffffa00
+#define AT91SAM9RL_BASE_SHDWC   0xfffffd10
+#define AT91SAM9RL_BASE_RTT     0xfffffd20
+#define AT91SAM9RL_BASE_PIT     0xfffffd30
+#define AT91SAM9RL_BASE_WDT     0xfffffd40
+#define AT91SAM9RL_BASE_RTC     0xfffffe00
 
 #define AT91_USART0     AT91SAM9RL_BASE_US0
 #define AT91_USART1     AT91SAM9RL_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a152ff87e68..a57829f4fd1 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -40,7 +40,6 @@
 #define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
 #define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
 #define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
 
 /*
  * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index eac92e995bb..d0b377b21bd 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -40,13 +40,14 @@
 #include <linux/atmel-mci.h>
 #include <sound/atmel-ac97c.h>
 #include <linux/serial.h>
+#include <linux/platform_data/macb.h>
 
  /* USB Device */
 struct at91_udc_data {
-        u8      vbus_pin;               /* high == host powering us */
+        int     vbus_pin;               /* high == host powering us */
         u8      vbus_active_low;        /* vbus polarity */
         u8      vbus_polled;            /* Use polling, not interrupt */
-        u8      pullup_pin;             /* active == D+ pulled up */
+        int     pullup_pin;             /* active == D+ pulled up */
         u8      pullup_active_low;      /* true == pullup_pin is active low */
 };
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
@@ -56,10 +57,10 @@ extern void __init at91_add_device_usba(struct usba_platform_data *data);
 
  /* Compact Flash */
 struct at91_cf_data {
-        u8      irq_pin;                /* I/O IRQ */
-        u8      det_pin;                /* Card detect */
-        u8      vcc_pin;                /* power switching */
-        u8      rst_pin;                /* card reset */
+        int     irq_pin;                /* I/O IRQ */
+        int     det_pin;                /* Card detect */
+        int     vcc_pin;                /* power switching */
+        int     rst_pin;                /* card reset */
         u8      chipselect;             /* EBI Chip Select number */
         u8      flags;
 #define AT91_CF_TRUE_IDE        0x01
@@ -70,37 +71,26 @@ extern void __init at91_add_device_cf(struct at91_cf_data *data);
  /* MMC / SD */
   /* at91_mci platform config */
 struct at91_mmc_data {
-        u8              det_pin;        /* card detect IRQ */
+        int             det_pin;        /* card detect IRQ */
         unsigned        slot_b:1;       /* uses Slot B */
         unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
-        u8              wp_pin;         /* (SD) writeprotect detect */
-        u8              vcc_pin;        /* power switching (high == on) */
+        int             wp_pin;         /* (SD) writeprotect detect */
+        int             vcc_pin;        /* power switching (high == on) */
 };
 extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
 
   /* atmel-mci platform config */
 extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
 
- /* Ethernet (EMAC & MACB) */
-struct at91_eth_data {
-        u32             phy_mask;
-        u8              phy_irq_pin;    /* PHY IRQ */
-        u8              is_rmii;        /* using RMII interface? */
-};
-extern void __init at91_add_device_eth(struct at91_eth_data *data);
-
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
-#define eth_platform_data       at91_eth_data
-#endif
+extern void __init at91_add_device_eth(struct macb_platform_data *data);
 
  /* USB Host */
 struct at91_usbh_data {
         u8              ports;          /* number of ports on root hub */
-        u8              vbus_pin[2];    /* port power-control pin */
+        int             vbus_pin[2];    /* port power-control pin */
         u8              vbus_pin_inverted;
         u8              overcurrent_supported;
-        u8              overcurrent_pin[2];
+        int             overcurrent_pin[2];
         u8              overcurrent_status[2];
         u8              overcurrent_changed[2];
 };
@@ -110,9 +100,9 @@ extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
 
  /* NAND / SmartMedia */
 struct atmel_nand_data {
-        u8              enable_pin;     /* chip enable */
-        u8              det_pin;        /* card detect */
-        u8              rdy_pin;        /* ready/busy */
+        int             enable_pin;     /* chip enable */
+        int             det_pin;        /* card detect */
+        int             rdy_pin;        /* ready/busy */
         u8              rdy_pin_active_low;     /* rdy_pin value is inverted */
         u8              ale;            /* address line number connected to ALE */
         u8              cle;            /* address line number connected to CLE */
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 0ed8648c645..c6bb9e2d9ba 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,9 +14,15 @@
 #include <mach/hardware.h>
 #include <mach/at91_dbgu.h>
 
+#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
+#define AT91_DBGU AT91_BASE_DBGU0
+#else
+#define AT91_DBGU AT91_BASE_DBGU1
+#endif
+
         .macro  addruart, rp, rv, tmp
-        ldr     \rp, =(AT91_BASE_SYS + AT91_DBGU)       @ System peripherals (phys address)
-        ldr     \rv, =(AT91_VA_BASE_SYS + AT91_DBGU)    @ System peripherals (virt address)
+        ldr     \rp, =AT91_DBGU                         @ System peripherals (phys address)
+        ldr     \rv, =AT91_IO_P2V(AT91_DBGU)            @ System peripherals (virt address)
         .endm
 
         .macro  senduart,rd,rx
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
index 7ab68f97222..423eea0ed74 100644
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -17,16 +17,17 @@
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
+        ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
+        ldr     \base, [\base]
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
 
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
-        ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
-        teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
-        streq   \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)]     @ not going to be handled further, then ACK it now.
+        ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
+        ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
+        teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
+        streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
         .endm
 
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 2b9a1f51210..e3fd225121c 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -16,177 +16,175 @@
 #include <linux/kernel.h>
 #include <asm/irq.h>
 
-#define PIN_BASE                NR_AIC_IRQS
-
 #define MAX_GPIO_BANKS          5
-#define NR_BUILTIN_GPIO         (PIN_BASE + (MAX_GPIO_BANKS * 32))
+#define NR_BUILTIN_GPIO         (MAX_GPIO_BANKS * 32)
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
-#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
-#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
-#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
-#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
-#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
-#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
-#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
-#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
-#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
-#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
-#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
-#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
-#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
-#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
-#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
-#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
-#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
-#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
-#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
-#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
-#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
-#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
-#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
-#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
-#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
-#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
-#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
-#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
-#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
-#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
-#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
-#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
-
-#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
-#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
-#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
-#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
-#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
-#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
-#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
-#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
-#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
-#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
-#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
-#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
-#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
-#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
-#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
-#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
-#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
-#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
-#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
-#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
-#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
-#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
-#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
-#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
-#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
-#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
-#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
-#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
-#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
-#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
-#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
-#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
-
-#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
-#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
-#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
-#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
-#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
-#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
-#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
-#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
-#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
-#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
-#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
-#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
-#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
-#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
-#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
-#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
-#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
-#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
-#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
-#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
-#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
-#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
-#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
-#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
-#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
-#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
-#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
-#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
-#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
-#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
-#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
-#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
-
-#define AT91_PIN_PD0    (PIN_BASE + 0x60 + 0)
-#define AT91_PIN_PD1    (PIN_BASE + 0x60 + 1)
-#define AT91_PIN_PD2    (PIN_BASE + 0x60 + 2)
-#define AT91_PIN_PD3    (PIN_BASE + 0x60 + 3)
-#define AT91_PIN_PD4    (PIN_BASE + 0x60 + 4)
-#define AT91_PIN_PD5    (PIN_BASE + 0x60 + 5)
-#define AT91_PIN_PD6    (PIN_BASE + 0x60 + 6)
-#define AT91_PIN_PD7    (PIN_BASE + 0x60 + 7)
-#define AT91_PIN_PD8    (PIN_BASE + 0x60 + 8)
-#define AT91_PIN_PD9    (PIN_BASE + 0x60 + 9)
-#define AT91_PIN_PD10   (PIN_BASE + 0x60 + 10)
-#define AT91_PIN_PD11   (PIN_BASE + 0x60 + 11)
-#define AT91_PIN_PD12   (PIN_BASE + 0x60 + 12)
-#define AT91_PIN_PD13   (PIN_BASE + 0x60 + 13)
-#define AT91_PIN_PD14   (PIN_BASE + 0x60 + 14)
-#define AT91_PIN_PD15   (PIN_BASE + 0x60 + 15)
-#define AT91_PIN_PD16   (PIN_BASE + 0x60 + 16)
-#define AT91_PIN_PD17   (PIN_BASE + 0x60 + 17)
-#define AT91_PIN_PD18   (PIN_BASE + 0x60 + 18)
-#define AT91_PIN_PD19   (PIN_BASE + 0x60 + 19)
-#define AT91_PIN_PD20   (PIN_BASE + 0x60 + 20)
-#define AT91_PIN_PD21   (PIN_BASE + 0x60 + 21)
-#define AT91_PIN_PD22   (PIN_BASE + 0x60 + 22)
-#define AT91_PIN_PD23   (PIN_BASE + 0x60 + 23)
-#define AT91_PIN_PD24   (PIN_BASE + 0x60 + 24)
-#define AT91_PIN_PD25   (PIN_BASE + 0x60 + 25)
-#define AT91_PIN_PD26   (PIN_BASE + 0x60 + 26)
-#define AT91_PIN_PD27   (PIN_BASE + 0x60 + 27)
-#define AT91_PIN_PD28   (PIN_BASE + 0x60 + 28)
-#define AT91_PIN_PD29   (PIN_BASE + 0x60 + 29)
-#define AT91_PIN_PD30   (PIN_BASE + 0x60 + 30)
-#define AT91_PIN_PD31   (PIN_BASE + 0x60 + 31)
-
-#define AT91_PIN_PE0    (PIN_BASE + 0x80 + 0)
-#define AT91_PIN_PE1    (PIN_BASE + 0x80 + 1)
-#define AT91_PIN_PE2    (PIN_BASE + 0x80 + 2)
-#define AT91_PIN_PE3    (PIN_BASE + 0x80 + 3)
-#define AT91_PIN_PE4    (PIN_BASE + 0x80 + 4)
-#define AT91_PIN_PE5    (PIN_BASE + 0x80 + 5)
-#define AT91_PIN_PE6    (PIN_BASE + 0x80 + 6)
-#define AT91_PIN_PE7    (PIN_BASE + 0x80 + 7)
-#define AT91_PIN_PE8    (PIN_BASE + 0x80 + 8)
-#define AT91_PIN_PE9    (PIN_BASE + 0x80 + 9)
-#define AT91_PIN_PE10   (PIN_BASE + 0x80 + 10)
-#define AT91_PIN_PE11   (PIN_BASE + 0x80 + 11)
-#define AT91_PIN_PE12   (PIN_BASE + 0x80 + 12)
-#define AT91_PIN_PE13   (PIN_BASE + 0x80 + 13)
-#define AT91_PIN_PE14   (PIN_BASE + 0x80 + 14)
-#define AT91_PIN_PE15   (PIN_BASE + 0x80 + 15)
-#define AT91_PIN_PE16   (PIN_BASE + 0x80 + 16)
-#define AT91_PIN_PE17   (PIN_BASE + 0x80 + 17)
-#define AT91_PIN_PE18   (PIN_BASE + 0x80 + 18)
-#define AT91_PIN_PE19   (PIN_BASE + 0x80 + 19)
-#define AT91_PIN_PE20   (PIN_BASE + 0x80 + 20)
-#define AT91_PIN_PE21   (PIN_BASE + 0x80 + 21)
-#define AT91_PIN_PE22   (PIN_BASE + 0x80 + 22)
-#define AT91_PIN_PE23   (PIN_BASE + 0x80 + 23)
-#define AT91_PIN_PE24   (PIN_BASE + 0x80 + 24)
-#define AT91_PIN_PE25   (PIN_BASE + 0x80 + 25)
-#define AT91_PIN_PE26   (PIN_BASE + 0x80 + 26)
-#define AT91_PIN_PE27   (PIN_BASE + 0x80 + 27)
-#define AT91_PIN_PE28   (PIN_BASE + 0x80 + 28)
-#define AT91_PIN_PE29   (PIN_BASE + 0x80 + 29)
-#define AT91_PIN_PE30   (PIN_BASE + 0x80 + 30)
-#define AT91_PIN_PE31   (PIN_BASE + 0x80 + 31)
+#define AT91_PIN_PA0    (0x00 + 0)
+#define AT91_PIN_PA1    (0x00 + 1)
+#define AT91_PIN_PA2    (0x00 + 2)
+#define AT91_PIN_PA3    (0x00 + 3)
+#define AT91_PIN_PA4    (0x00 + 4)
+#define AT91_PIN_PA5    (0x00 + 5)
+#define AT91_PIN_PA6    (0x00 + 6)
+#define AT91_PIN_PA7    (0x00 + 7)
+#define AT91_PIN_PA8    (0x00 + 8)
+#define AT91_PIN_PA9    (0x00 + 9)
+#define AT91_PIN_PA10   (0x00 + 10)
+#define AT91_PIN_PA11   (0x00 + 11)
+#define AT91_PIN_PA12   (0x00 + 12)
+#define AT91_PIN_PA13   (0x00 + 13)
+#define AT91_PIN_PA14   (0x00 + 14)
+#define AT91_PIN_PA15   (0x00 + 15)
+#define AT91_PIN_PA16   (0x00 + 16)
+#define AT91_PIN_PA17   (0x00 + 17)
+#define AT91_PIN_PA18   (0x00 + 18)
+#define AT91_PIN_PA19   (0x00 + 19)
+#define AT91_PIN_PA20   (0x00 + 20)
+#define AT91_PIN_PA21   (0x00 + 21)
+#define AT91_PIN_PA22   (0x00 + 22)
+#define AT91_PIN_PA23   (0x00 + 23)
+#define AT91_PIN_PA24   (0x00 + 24)
+#define AT91_PIN_PA25   (0x00 + 25)
+#define AT91_PIN_PA26   (0x00 + 26)
+#define AT91_PIN_PA27   (0x00 + 27)
+#define AT91_PIN_PA28   (0x00 + 28)
+#define AT91_PIN_PA29   (0x00 + 29)
+#define AT91_PIN_PA30   (0x00 + 30)
+#define AT91_PIN_PA31   (0x00 + 31)
+
+#define AT91_PIN_PB0    (0x20 + 0)
+#define AT91_PIN_PB1    (0x20 + 1)
+#define AT91_PIN_PB2    (0x20 + 2)
+#define AT91_PIN_PB3    (0x20 + 3)
+#define AT91_PIN_PB4    (0x20 + 4)
+#define AT91_PIN_PB5    (0x20 + 5)
+#define AT91_PIN_PB6    (0x20 + 6)
+#define AT91_PIN_PB7    (0x20 + 7)
+#define AT91_PIN_PB8    (0x20 + 8)
+#define AT91_PIN_PB9    (0x20 + 9)
+#define AT91_PIN_PB10   (0x20 + 10)
+#define AT91_PIN_PB11   (0x20 + 11)
+#define AT91_PIN_PB12   (0x20 + 12)
+#define AT91_PIN_PB13   (0x20 + 13)
+#define AT91_PIN_PB14   (0x20 + 14)
+#define AT91_PIN_PB15   (0x20 + 15)
+#define AT91_PIN_PB16   (0x20 + 16)
+#define AT91_PIN_PB17   (0x20 + 17)
+#define AT91_PIN_PB18   (0x20 + 18)
+#define AT91_PIN_PB19   (0x20 + 19)
+#define AT91_PIN_PB20   (0x20 + 20)
+#define AT91_PIN_PB21   (0x20 + 21)
+#define AT91_PIN_PB22   (0x20 + 22)
+#define AT91_PIN_PB23   (0x20 + 23)
+#define AT91_PIN_PB24   (0x20 + 24)
+#define AT91_PIN_PB25   (0x20 + 25)
+#define AT91_PIN_PB26   (0x20 + 26)
+#define AT91_PIN_PB27   (0x20 + 27)
+#define AT91_PIN_PB28   (0x20 + 28)
+#define AT91_PIN_PB29   (0x20 + 29)
+#define AT91_PIN_PB30   (0x20 + 30)
+#define AT91_PIN_PB31   (0x20 + 31)
+
+#define AT91_PIN_PC0    (0x40 + 0)
+#define AT91_PIN_PC1    (0x40 + 1)
+#define AT91_PIN_PC2    (0x40 + 2)
+#define AT91_PIN_PC3    (0x40 + 3)
+#define AT91_PIN_PC4    (0x40 + 4)
+#define AT91_PIN_PC5    (0x40 + 5)
+#define AT91_PIN_PC6    (0x40 + 6)
+#define AT91_PIN_PC7    (0x40 + 7)
+#define AT91_PIN_PC8    (0x40 + 8)
+#define AT91_PIN_PC9    (0x40 + 9)
+#define AT91_PIN_PC10   (0x40 + 10)
+#define AT91_PIN_PC11   (0x40 + 11)
+#define AT91_PIN_PC12   (0x40 + 12)
+#define AT91_PIN_PC13   (0x40 + 13)
+#define AT91_PIN_PC14   (0x40 + 14)
+#define AT91_PIN_PC15   (0x40 + 15)
+#define AT91_PIN_PC16   (0x40 + 16)
+#define AT91_PIN_PC17   (0x40 + 17)
+#define AT91_PIN_PC18   (0x40 + 18)
+#define AT91_PIN_PC19   (0x40 + 19)
+#define AT91_PIN_PC20   (0x40 + 20)
+#define AT91_PIN_PC21   (0x40 + 21)
+#define AT91_PIN_PC22   (0x40 + 22)
+#define AT91_PIN_PC23   (0x40 + 23)
+#define AT91_PIN_PC24   (0x40 + 24)
+#define AT91_PIN_PC25   (0x40 + 25)
+#define AT91_PIN_PC26   (0x40 + 26)
+#define AT91_PIN_PC27   (0x40 + 27)
+#define AT91_PIN_PC28   (0x40 + 28)
+#define AT91_PIN_PC29   (0x40 + 29)
+#define AT91_PIN_PC30   (0x40 + 30)
+#define AT91_PIN_PC31   (0x40 + 31)
+
+#define AT91_PIN_PD0    (0x60 + 0)
+#define AT91_PIN_PD1    (0x60 + 1)
+#define AT91_PIN_PD2    (0x60 + 2)
+#define AT91_PIN_PD3    (0x60 + 3)
+#define AT91_PIN_PD4    (0x60 + 4)
+#define AT91_PIN_PD5    (0x60 + 5)
+#define AT91_PIN_PD6    (0x60 + 6)
+#define AT91_PIN_PD7    (0x60 + 7)
+#define AT91_PIN_PD8    (0x60 + 8)
+#define AT91_PIN_PD9    (0x60 + 9)
+#define AT91_PIN_PD10   (0x60 + 10)
+#define AT91_PIN_PD11   (0x60 + 11)
+#define AT91_PIN_PD12   (0x60 + 12)
+#define AT91_PIN_PD13   (0x60 + 13)
+#define AT91_PIN_PD14   (0x60 + 14)
+#define AT91_PIN_PD15   (0x60 + 15)
+#define AT91_PIN_PD16   (0x60 + 16)
+#define AT91_PIN_PD17   (0x60 + 17)
+#define AT91_PIN_PD18   (0x60 + 18)
+#define AT91_PIN_PD19   (0x60 + 19)
+#define AT91_PIN_PD20   (0x60 + 20)
+#define AT91_PIN_PD21   (0x60 + 21)
+#define AT91_PIN_PD22   (0x60 + 22)
+#define AT91_PIN_PD23   (0x60 + 23)
+#define AT91_PIN_PD24   (0x60 + 24)
+#define AT91_PIN_PD25   (0x60 + 25)
+#define AT91_PIN_PD26   (0x60 + 26)
+#define AT91_PIN_PD27   (0x60 + 27)
+#define AT91_PIN_PD28   (0x60 + 28)
+#define AT91_PIN_PD29   (0x60 + 29)
+#define AT91_PIN_PD30   (0x60 + 30)
+#define AT91_PIN_PD31   (0x60 + 31)
+
+#define AT91_PIN_PE0    (0x80 + 0)
+#define AT91_PIN_PE1    (0x80 + 1)
+#define AT91_PIN_PE2    (0x80 + 2)
+#define AT91_PIN_PE3    (0x80 + 3)
+#define AT91_PIN_PE4    (0x80 + 4)
+#define AT91_PIN_PE5    (0x80 + 5)
+#define AT91_PIN_PE6    (0x80 + 6)
+#define AT91_PIN_PE7    (0x80 + 7)
+#define AT91_PIN_PE8    (0x80 + 8)
+#define AT91_PIN_PE9    (0x80 + 9)
+#define AT91_PIN_PE10   (0x80 + 10)
+#define AT91_PIN_PE11   (0x80 + 11)
+#define AT91_PIN_PE12   (0x80 + 12)
+#define AT91_PIN_PE13   (0x80 + 13)
+#define AT91_PIN_PE14   (0x80 + 14)
+#define AT91_PIN_PE15   (0x80 + 15)
+#define AT91_PIN_PE16   (0x80 + 16)
+#define AT91_PIN_PE17   (0x80 + 17)
+#define AT91_PIN_PE18   (0x80 + 18)
+#define AT91_PIN_PE19   (0x80 + 19)
+#define AT91_PIN_PE20   (0x80 + 20)
+#define AT91_PIN_PE21   (0x80 + 21)
+#define AT91_PIN_PE22   (0x80 + 22)
+#define AT91_PIN_PE23   (0x80 + 23)
+#define AT91_PIN_PE24   (0x80 + 24)
+#define AT91_PIN_PE25   (0x80 + 25)
+#define AT91_PIN_PE26   (0x80 + 26)
+#define AT91_PIN_PE27   (0x80 + 27)
+#define AT91_PIN_PE28   (0x80 + 28)
+#define AT91_PIN_PE29   (0x80 + 29)
+#define AT91_PIN_PE30   (0x80 + 30)
+#define AT91_PIN_PE31   (0x80 + 31)
 
 #ifndef __ASSEMBLY__
 /* setup setup routines, called from board init or driver probe() */
@@ -215,8 +213,8 @@ extern void at91_gpio_resume(void);
 
 #include <asm/errno.h>
 
-#define gpio_to_irq(gpio) (gpio)
-#define irq_to_gpio(irq)  (irq)
+#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
+#define irq_to_gpio(irq)  (irq - NR_AIC_IRQS)
 
 #endif  /* __ASSEMBLY__ */
 
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 483478d8be6..2d0e4e99856 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -16,6 +16,12 @@
 
 #include <asm/sizes.h>
 
+/* DBGU base */
+/* rm9200, 9260/9g20, 9261/9g10, 9rl */
+#define AT91_BASE_DBGU0 0xfffff200
+/* 9263, 9g45, cap9 */
+#define AT91_BASE_DBGU1 0xffffee00
+
 #if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200.h>
 #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
@@ -52,6 +58,12 @@
 #endif
 
 /*
+ * On all at91 have the Advanced Interrupt Controller starts at address
+ * 0xfffff000
+ */
+#define AT91_AIC        0xfffff000
+
+/*
  * Peripheral identifiers/interrupts.
  */
 #define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
index 36bd55f3fc6..ac8b7dfc85e 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -31,7 +31,7 @@
  * Acknowledge interrupt with AIC after interrupt has been handled.
  *   (by kernel/irq.c)
  */
-#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
+#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
 
 
 /*
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 85820ad801c..5e917a66edd 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -23,70 +23,15 @@
 
 #include <mach/hardware.h>
 
-#if defined(CONFIG_ARCH_AT91RM9200)
+#ifdef CONFIG_ARCH_AT91X40
 
-#define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
-
-#elif defined(CONFIG_ARCH_AT91SAM9260)
-
-#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
-#define AT91SAM9_MASTER_CLOCK   90000000
-#else
-#define AT91SAM9_MASTER_CLOCK   99300000
-#endif
-
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9261)
-
-#define AT91SAM9_MASTER_CLOCK   99300000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9G10)
-
-#define AT91SAM9_MASTER_CLOCK   133000000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9263)
-
-#if defined(CONFIG_MACH_USB_A9263)
-#define AT91SAM9_MASTER_CLOCK   90000000
-#else
-#define AT91SAM9_MASTER_CLOCK   99959500
-#endif
-
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
-
-#define AT91SAM9_MASTER_CLOCK   100000000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9G20)
+#define AT91X40_MASTER_CLOCK    40000000
+#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 
-#if defined(CONFIG_MACH_USB_A9G20)
-#define AT91SAM9_MASTER_CLOCK   133000000
 #else
-#define AT91SAM9_MASTER_CLOCK   132096000
-#endif
-
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
 
-#define AT91SAM9_MASTER_CLOCK   133333333
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91CAP9)
-
-#define AT91CAP9_MASTER_CLOCK   100000000
-#define CLOCK_TICK_RATE         (AT91CAP9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91X40)
-
-#define AT91X40_MASTER_CLOCK    40000000
-#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
+#define CLOCK_TICK_RATE         12345678
 
 #endif
 
-#endif
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 18bdcdeb474..0234fd9d20d 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -24,8 +24,10 @@
 #include <linux/io.h>
 #include <linux/atmel_serial.h>
 
-#if defined(CONFIG_AT91_EARLY_DBGU)
-#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
+#if defined(CONFIG_AT91_EARLY_DBGU0)
+#define UART_OFFSET AT91_BASE_DBGU0
+#elif defined(CONFIG_AT91_EARLY_DBGU1)
+#define UART_OFFSET AT91_BASE_DBGU1
 #elif defined(CONFIG_AT91_EARLY_USART0)
 #define UART_OFFSET AT91_USART0
 #elif defined(CONFIG_AT91_EARLY_USART1)
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 9665265ec75..be6b639ecd7 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -33,17 +33,18 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
+void __iomem *at91_aic_base;
 
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IDCR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
 }
 
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IECR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
 }
 
 unsigned int at91_extern_irq;
@@ -77,8 +78,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 return -EINVAL;
         }
 
-        smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
-        at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype);
+        smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
+        at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
         return 0;
 }
 
@@ -102,15 +103,15 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 
 void at91_irq_suspend(void)
 {
-        backups = at91_sys_read(AT91_AIC_IMR);
-        at91_sys_write(AT91_AIC_IDCR, backups);
-        at91_sys_write(AT91_AIC_IECR, wakeups);
+        backups = at91_aic_read(AT91_AIC_IMR);
+        at91_aic_write(AT91_AIC_IDCR, backups);
+        at91_aic_write(AT91_AIC_IECR, wakeups);
 }
 
 void at91_irq_resume(void)
 {
-        at91_sys_write(AT91_AIC_IDCR, wakeups);
-        at91_sys_write(AT91_AIC_IECR, backups);
+        at91_aic_write(AT91_AIC_IDCR, wakeups);
+        at91_aic_write(AT91_AIC_IECR, backups);
 }
 
 #else
@@ -133,34 +134,39 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
         unsigned int i;
 
+        at91_aic_base = ioremap(AT91_AIC, 512);
+
+        if (!at91_aic_base)
+                panic("Impossible to ioremap AT91_AIC\n");
+
         /*
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
          */
         for (i = 0; i < NR_AIC_IRQS; i++) {
                 /* Put irq number in Source Vector Register: */
-                at91_sys_write(AT91_AIC_SVR(i), i);
+                at91_aic_write(AT91_AIC_SVR(i), i);
                 /* Active Low interrupt, with the specified priority */
-                at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
+                at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 
                 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 
                 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
                 if (i < 8)
-                        at91_sys_write(AT91_AIC_EOICR, 0);
+                        at91_aic_write(AT91_AIC_EOICR, 0);
         }
 
         /*
          * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
          * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
          */
-        at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
+        at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
 
         /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_sys_write(AT91_AIC_DCR, 0);
+        at91_aic_write(AT91_AIC_DCR, 0);
 
         /* Disable and clear all interrupts initially */
-        at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 7046158109d..62ad95556c3 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,7 +34,7 @@
 /*
  * Show the reason for the previous system reset.
  */
-#if defined(AT91_SHDWC)
+#if defined(AT91_RSTC)
 
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
@@ -58,8 +58,11 @@ static void __init show_reset_status(void)
         char *reason, *r2 = reset;
         u32 reset_type, wake_type;
 
+        if (!at91_shdwc_base)
+                return;
+
         reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
-        wake_type = at91_sys_read(AT91_SHDW_SR);
+        wake_type = at91_shdwc_read(AT91_SHDW_SR);
 
         switch (reset_type) {
         case AT91_RSTC_RSTTYP_GENERAL:
@@ -215,7 +218,7 @@ static int at91_pm_enter(suspend_state_t state)
                                         | (1 << AT91_ID_FIQ)
                                         | (1 << AT91_ID_SYS)
                                         | (at91_extern_irq))
-                                & at91_sys_read(AT91_AIC_IMR),
+                                & at91_aic_read(AT91_AIC_IMR),
                         state);
 
         switch (state) {
@@ -283,7 +286,7 @@ static int at91_pm_enter(suspend_state_t state)
         }
 
         pr_debug("AT91: PM - wakeup %08x\n",
-                        at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
+                        at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
 
 error:
         target_state = PM_SUSPEND_ON;
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 5eab6aa621d..8294783b679 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -10,38 +10,58 @@
 
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 
-void __init sam9_smc_configure(int cs, struct sam9_smc_config* config)
+
+#define AT91_SMC_CS(id, n)      (smc_base_addr[id] + ((n) * 0x10))
+
+static void __iomem *smc_base_addr[2];
+
+static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config)
 {
+
         /* Setup register */
-        at91_sys_write(AT91_SMC_SETUP(cs),
-                  AT91_SMC_NWESETUP_(config->nwe_setup)
-                | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
-                | AT91_SMC_NRDSETUP_(config->nrd_setup)
-                | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup)
-        );
+        __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
+                   | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
+                   | AT91_SMC_NRDSETUP_(config->nrd_setup)
+                   | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
+                   base + AT91_SMC_SETUP);
 
         /* Pulse register */
-        at91_sys_write(AT91_SMC_PULSE(cs),
-                  AT91_SMC_NWEPULSE_(config->nwe_pulse)
-                | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
-                | AT91_SMC_NRDPULSE_(config->nrd_pulse)
-                | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse)
-        );
+        __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
+                   | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
+                   | AT91_SMC_NRDPULSE_(config->nrd_pulse)
+                   | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
+                   base + AT91_SMC_PULSE);
 
         /* Cycle register */
-        at91_sys_write(AT91_SMC_CYCLE(cs),
-                  AT91_SMC_NWECYCLE_(config->write_cycle)
-                | AT91_SMC_NRDCYCLE_(config->read_cycle)
-        );
+        __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
+                   | AT91_SMC_NRDCYCLE_(config->read_cycle),
+                   base + AT91_SMC_CYCLE);
 
         /* Mode register */
-        at91_sys_write(AT91_SMC_MODE(cs),
-                  config->mode
-                | AT91_SMC_TDF_(config->tdf_cycles)
-        );
+        __raw_writel(config->mode
+                   | AT91_SMC_TDF_(config->tdf_cycles),
+                   base + AT91_SMC_MODE);
+}
+
+void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config)
+{
+        sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
+}
+
+void __init at91sam9_ioremap_smc(int id, u32 addr)
+{
+        if (id > 1) {
+                pr_warn("%s: id > 2\n", __func__);
+                return;
+        }
+        smc_base_addr[id] = ioremap(addr, 512);
+        if (!smc_base_addr[id])
+                pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
 }
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
index bf72cfb3455..039c5ce17ae 100644
--- a/arch/arm/mach-at91/sam9_smc.h
+++ b/arch/arm/mach-at91/sam9_smc.h
@@ -30,4 +30,5 @@ struct sam9_smc_config {
         u8 tdf_cycles:4;
 };
 
-extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config);
+extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
+extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index cf98a8f94dc..8bdcc3cb601 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/mm.h>
+#include <linux/pm.h>
 
 #include <asm/mach/map.h>
 
@@ -15,6 +16,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
@@ -73,9 +75,6 @@ static struct map_desc at91_io_desc __initdata = {
         .type           = MT_DEVICE,
 };
 
-#define AT91_DBGU0      0xfffff200
-#define AT91_DBGU1      0xffffee00
-
 static void __init soc_detect(u32 dbgu_base)
 {
         u32 cidr, socid;
@@ -248,9 +247,9 @@ void __init at91_map_io(void)
         at91_soc_initdata.type = AT91_SOC_NONE;
         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 
-        soc_detect(AT91_DBGU0);
+        soc_detect(AT91_BASE_DBGU0);
         if (!at91_soc_is_detected())
-                soc_detect(AT91_DBGU1);
+                soc_detect(AT91_BASE_DBGU1);
 
         if (!at91_soc_is_detected())
                 panic("AT91: Impossible to detect the SOC type");
@@ -267,8 +266,25 @@ void __init at91_map_io(void)
                 at91_boot_soc.map_io();
 }
 
+void __iomem *at91_shdwc_base = NULL;
+
+static void at91sam9_poweroff(void)
+{
+        at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+void __init at91_ioremap_shdwc(u32 base_addr)
+{
+        at91_shdwc_base = ioremap(base_addr, 16);
+        if (!at91_shdwc_base)
+                panic("Impossible to ioremap at91_shdwc_base\n");
+        pm_power_off = at91sam9_poweroff;
+}
+
 void __init at91_initialize(unsigned long main_clock)
 {
+        at91_boot_soc.ioremap_registers();
+
         /* Init clock subsystem */
         at91_clock_init(main_clock);
 
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 21ed8816e6f..4588ae6f7ac 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -7,6 +7,7 @@
 struct at91_init_soc {
         unsigned int *default_irq_priority;
         void (*map_io)(void);
+        void (*ioremap_registers)(void);
         void (*register_clocks)(void);
         void (*init)(void);
 };
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index f8a682f60a4..6b22b543a83 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -127,7 +127,7 @@ static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
         size_t retlen;
 
         if (!strcmp(mtd->name, "MAC-Address")) {
-                mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
+                mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
                 if (retlen == ETH_ALEN)
                         pr_info("Read MAC addr from SPI Flash: %pM\n",
                                 mac_addr);
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 00861139101..008772e3b84 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -31,19 +31,12 @@ static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clockfw_lock);
 
-static unsigned psc_domain(struct clk *clk)
-{
-        return (clk->flags & PSC_DSP)
-                ? DAVINCI_GPSC_DSPDOMAIN
-                : DAVINCI_GPSC_ARMDOMAIN;
-}
-
 static void __clk_enable(struct clk *clk)
 {
         if (clk->parent)
                 __clk_enable(clk->parent);
         if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-                davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
                                 true, clk->flags);
 }
 
@@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk)
                 return;
         if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
             (clk->flags & CLK_PSC))
-                davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
                                 false, clk->flags);
         if (clk->parent)
                 __clk_disable(clk->parent);
@@ -237,7 +230,7 @@ static int __init clk_disable_unused(void)
 
                 pr_debug("Clocks: disable unused %s\n", ck->name);
 
-                davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+                davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
                                 false, ck->flags);
         }
         spin_unlock_irq(&clockfw_lock);
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a705f367a84..46f0f1bf1a4 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -93,6 +93,7 @@ struct clk {
         u8                      usecount;
         u8                      lpsc;
         u8                      gpsc;
+        u8                      domain;
         u32                     flags;
         struct clk              *parent;
         struct list_head        children;       /* list of children */
@@ -107,11 +108,10 @@ struct clk {
 /* Clock flags: SoC-specific flags start at BIT(16) */
 #define ALWAYS_ENABLED          BIT(1)
 #define CLK_PSC                 BIT(2)
-#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
-#define CLK_PLL                 BIT(4) /* PLL-derived clock */
-#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
-#define PSC_SWRSTDISABLE        BIT(6) /* Disable state is SwRstDisable */
-#define PSC_FORCE               BIT(7) /* Force module state transtition */
+#define CLK_PLL                 BIT(3) /* PLL-derived clock */
+#define PRE_PLL                 BIT(4) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLE        BIT(5) /* Disable state is SwRstDisable */
+#define PSC_FORCE               BIT(6) /* Force module state transtition */
 
 #define CLK(dev, con, ck)       \
         {                       \
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 0800f9cf33b..43a48ee1917 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -130,7 +130,7 @@ static struct clk dsp_clk = {
         .name = "dsp",
         .parent = &pll1_sysclk1,
         .lpsc = DAVINCI_LPSC_GEM,
-        .flags = PSC_DSP,
+        .domain = DAVINCI_GPSC_DSPDOMAIN,
         .usecount = 1,                  /* REVISIT how to disable? */
 };
 
@@ -145,7 +145,7 @@ static struct clk vicp_clk = {
         .name = "vicp",
         .parent = &pll1_sysclk2,
         .lpsc = DAVINCI_LPSC_IMCOP,
-        .flags = PSC_DSP,
+        .domain = DAVINCI_GPSC_DSPDOMAIN,
         .usecount = 1,                  /* REVISIT how to disable? */
 };
 
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 2a00fe5ac25..a8ee6c9f0bb 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -16,6 +16,7 @@
 #include <linux/i2c.h>
 #include <linux/videodev2.h>
 #include <linux/davinci_emac.h>
+#include <media/davinci/vpif_types.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
 #define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
@@ -34,58 +35,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv);
 
 void dm646x_video_init(void);
 
-enum vpif_if_type {
-        VPIF_IF_BT656,
-        VPIF_IF_BT1120,
-        VPIF_IF_RAW_BAYER
-};
-
-struct vpif_interface {
-        enum vpif_if_type if_type;
-        unsigned hd_pol:1;
-        unsigned vd_pol:1;
-        unsigned fid_pol:1;
-};
-
-struct vpif_subdev_info {
-        const char *name;
-        struct i2c_board_info board_info;
-        u32 input;
-        u32 output;
-        unsigned can_route:1;
-        struct vpif_interface vpif_if;
-};
-
-struct vpif_display_config {
-        int (*set_clock)(int, int);
-        struct vpif_subdev_info *subdevinfo;
-        int subdev_count;
-        const char **output;
-        int output_count;
-        const char *card_name;
-};
-
-struct vpif_input {
-        struct v4l2_input input;
-        const char *subdev_name;
-};
-
-#define VPIF_CAPTURE_MAX_CHANNELS       2
-
-struct vpif_capture_chan_config {
-        const struct vpif_input *inputs;
-        int input_count;
-};
-
-struct vpif_capture_config {
-        int (*setup_input_channel_mode)(int);
-        int (*setup_input_path)(int, const char *);
-        struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS];
-        struct vpif_subdev_info *subdev_info;
-        int subdev_count;
-        const char *card_name;
-};
-
 void dm646x_setup_vpif(struct vpif_display_config *,
                        struct vpif_capture_config *);
 
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 00be4fc26dd..98b8c83b09a 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
@@ -34,98 +35,72 @@
 #define ATTR_PCIE_MEM           0xe8
 #define ATTR_SCRATCHPAD         0x0
 
-/*
- * CPU Address Decode Windows registers
- */
-#define WIN_CTRL(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
-#define WIN_BASE(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
-#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
-#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
-
-struct mbus_dram_target_info dove_mbus_dram_info;
-
 static inline void __iomem *ddr_map_sc(int i)
 {
         return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
 }
 
-static int cpu_win_can_remap(int win)
-{
-        if (win < 4)
-                return 1;
-
-        return 0;
-}
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        u32 ctrl;
-
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-
-        writel(base, WIN_BASE(win));
-        writel(ctrl, WIN_CTRL(win));
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-                writel(remap & 0xffff0000, WIN_REMAP_LO(win));
-                writel(0, WIN_REMAP_HI(win));
-        }
-}
-
-void __init dove_setup_cpu_mbus(void)
-{
-        int i;
-        int cs;
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 8,
+        .remappable_wins = 4,
+        .bridge_virt_base = BRIDGE_VIRT_BASE,
+};
 
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
         /*
-         * First, disable and clear windows.
+         * Windows for PCIe IO+MEM space.
          */
-        for (i = 0; i < 8; i++) {
-                writel(0, WIN_BASE(i));
-                writel(0, WIN_CTRL(i));
-                if (cpu_win_can_remap(i)) {
-                        writel(0, WIN_REMAP_LO(i));
-                        writel(0, WIN_REMAP_HI(i));
-                }
-        }
-
+        { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
+          TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
+        },
+        { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
+          TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
+        },
+        { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
+          TARGET_PCIE0, ATTR_PCIE_MEM, -1
+        },
+        { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
+          TARGET_PCIE1, ATTR_PCIE_MEM, -1
+        },
         /*
-         * Setup windows for PCIe IO+MEM space.
+         * Window for CESA engine.
          */
-        setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
-                      TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
-        setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
-                      TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
-        setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
-                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
-        setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
-                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
-
+        { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
+          TARGET_CESA, ATTR_CESA, -1
+        },
         /*
-         * Setup window for CESA engine.
+         * Window to the BootROM for Standby and Sleep Resume
          */
-        setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
-                      TARGET_CESA, ATTR_CESA, -1);
-
+        { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
+          TARGET_BOOTROM, ATTR_BOOTROM, -1
+        },
         /*
-         * Setup the Window to the BootROM for Standby and Sleep Resume
+         * Window to the PMU Scratch Pad space
          */
-        setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
-                      TARGET_BOOTROM, ATTR_BOOTROM, -1);
+        { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
+          TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
+
+void __init dove_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
 
         /*
-         * Setup the Window to the PMU Scratch Pad space
+         * Disable, clear and configure windows.
          */
-        setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
-                      TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
+        orion_config_wins(&addr_map_cfg, addr_map_info);
 
         /*
          * Setup MBUS dram target info.
          */
-        dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
         for (i = 0, cs = 0; i < 2; i++) {
                 u32 map = readl(ddr_map_sc(i));
@@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void)
                 if (map & 1) {
                         struct mbus_dram_window *w;
 
-                        w = &dove_mbus_dram_info.cs[cs++];
+                        w = &orion_mbus_dram_info.cs[cs++];
                         w->cs_index = i;
                         w->mbus_attr = 0; /* CS address decoding done inside */
                                           /* the DDR controller, no need to  */
@@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void)
                         w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
                 }
         }
-        dove_mbus_dram_info.num_cs = cs;
+        orion_mbus_dram_info.num_cs = cs;
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 13bb236cd0c..dd1429ae640 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -14,7 +14,6 @@
 #include <linux/platform_device.h>
 #include <linux/pci.h>
 #include <linux/clk.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
 #include <asm/page.h>
@@ -30,6 +29,7 @@
 #include <linux/irq.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 static int get_tclk(void);
@@ -71,8 +71,7 @@ void __init dove_map_io(void)
  ****************************************************************************/
 void __init dove_ehci0_init(void)
 {
-        orion_ehci_init(&dove_mbus_dram_info,
-                        DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
+        orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
 }
 
 /*****************************************************************************
@@ -80,8 +79,7 @@ void __init dove_ehci0_init(void)
  ****************************************************************************/
 void __init dove_ehci1_init(void)
 {
-        orion_ehci_1_init(&dove_mbus_dram_info,
-                          DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
+        orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
 }
 
 /*****************************************************************************
@@ -89,7 +87,7 @@ void __init dove_ehci1_init(void)
  ****************************************************************************/
 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &dove_mbus_dram_info,
+        orion_ge00_init(eth_data,
                         DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
                         0, get_tclk());
 }
@@ -107,8 +105,7 @@ void __init dove_rtc_init(void)
  ****************************************************************************/
 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &dove_mbus_dram_info,
-                        DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
+        orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
 
 }
 
@@ -198,8 +195,7 @@ struct sys_timer dove_timer = {
  ****************************************************************************/
 void __init dove_xor0_init(void)
 {
-        orion_xor0_init(&dove_mbus_dram_info,
-                        DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
+        orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
                         IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
 }
 
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 42027305c10..6432a3ba864 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
 extern struct sys_timer dove_timer;
-extern struct mbus_dram_target_info dove_mbus_dram_info;
 
 /*
  * Basic Dove init functions used early by machine-setup.
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index aa2b3a09a51..6c11a4df717 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -10,7 +10,6 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/mach/pci.h>
 #include <asm/mach/arch.h>
@@ -19,6 +18,7 @@
 #include <plat/pcie.h>
 #include <mach/irqs.h>
 #include <mach/bridge-regs.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 struct pcie_port {
@@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
          */
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
 
-        orion_pcie_setup(pp->base, &dove_mbus_dram_info);
+        orion_pcie_setup(pp->base);
 
         /*
          * IORESOURCE_IO
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e1efbca2a53..5d602f68a0e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -59,6 +59,11 @@ config EXYNOS4_MCT
         help
           Use MCT (Multi Core Timer) as kernel timers
 
+config EXYNOS4_DEV_DMA
+        bool
+        help
+          Compile in amba device definitions for DMA controller
+
 config EXYNOS4_DEV_AHCI
         bool
         help
@@ -84,6 +89,11 @@ config EXYNOS4_DEV_DWMCI
         help
           Compile in platform device definitions for DWMCI
 
+config EXYNOS4_DEV_USB_OHCI
+        bool
+        help
+          Compile in platform device definition for USB OHCI
+
 config EXYNOS4_SETUP_I2C1
         bool
         help
@@ -145,6 +155,11 @@ config EXYNOS4_SETUP_USB_PHY
         help
           Common setup code for USB PHY controller
 
+config EXYNOS4_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations.
+
 # machine support
 
 if ARCH_EXYNOS4
@@ -179,8 +194,10 @@ config MACH_SMDKV310
         select SAMSUNG_DEV_BACKLIGHT
         select EXYNOS4_DEV_AHCI
         select SAMSUNG_DEV_KEYPAD
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_DEV_PD
         select SAMSUNG_DEV_PWM
+        select EXYNOS4_DEV_USB_OHCI
         select EXYNOS4_DEV_SYSMMU
         select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
@@ -199,6 +216,7 @@ config MACH_ARMLEX4210
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select EXYNOS4_DEV_AHCI
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_DEV_SYSMMU
         select EXYNOS4_SETUP_SDHCI
         help
@@ -224,6 +242,7 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_MFC
         select S5P_DEV_ONENAND
         select S5P_DEV_TV
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_DEV_PD
         select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
@@ -257,6 +276,7 @@ config MACH_NURI
         select S5P_DEV_MFC
         select S5P_DEV_USB_EHCI
         select S5P_SETUP_MIPIPHY
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_DEV_PD
         select EXYNOS4_SETUP_FIMC
         select EXYNOS4_SETUP_FIMD0
@@ -289,7 +309,9 @@ config MACH_ORIGEN
         select S5P_DEV_USB_EHCI
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_DEV_PD
+        select EXYNOS4_DEV_USB_OHCI
         select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
@@ -329,6 +351,20 @@ config MACH_SMDK4412
           Machine support for Samsung SMDK4412
 endif
 
+comment "Flattened Device Tree based board for Exynos4 based SoC"
+
+config MACH_EXYNOS4_DT
+        bool "Samsung Exynos4 Machine using device tree"
+        select CPU_EXYNOS4210
+        select USE_OF
+        select ARM_AMBA
+        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+        help
+          Machine support for Samsung Exynos4 machine with device tree enabled.
+          Select this if a fdt blob is available for the Exynos4 SoC based board.
+          Note: This is under development and not all peripherals can be supported
+          with this machine file.
+
 if ARCH_EXYNOS4
 
 comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index bcb9efc576e..5fc202cdfdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)      += dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
@@ -39,6 +39,8 @@ obj-$(CONFIG_MACH_ORIGEN)		+= mach-origen.o
 obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
 
+obj-$(CONFIG_MACH_EXYNOS4_DT)           += mach-exynos4-dt.o
+
 # device support
 
 obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
@@ -46,6 +48,8 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)            += dev-pd.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)        += dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)         += dev-dwmci.o
+obj-$(CONFIG_EXYNOS4_DEV_DMA)           += dma.o
+obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
 
 obj-$(CONFIG_ARCH_EXYNOS4)              += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
@@ -58,6 +62,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5)	+= setup-i2c5.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C6)        += setup-i2c6.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C7)        += setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 83616a039b1..5a8c42e9000 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -554,16 +554,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_dac_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.0",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.1",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
                 .name           = "adc",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 15),
@@ -779,6 +769,20 @@ static struct clk init_clocks[] = {
         }
 };
 
+static struct clk clk_pdma0 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.0",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+
+static struct clk clk_pdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.1",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
+
 struct clk *clkset_group_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = &clk_xusbxti,
@@ -1010,46 +1014,6 @@ static struct clksrc_clk clk_dout_mmc4 = {
 
 static struct clksrc_clk clksrcs[] = {
         {
-                .clk    = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.0",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.1",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.2",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.3",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-        }, {
                 .clk            = {
                         .name           = "sclk_pwm",
                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
@@ -1148,36 +1112,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.2",
-                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
                         .name           = "sclk_fimg2d",
                 },
                 .sources = &clkset_mout_g2d,
@@ -1193,42 +1127,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .parent         = &clk_dout_mmc0.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .parent         = &clk_dout_mmc1.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .parent         = &clk_dout_mmc2.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.3",
-                        .parent         = &clk_dout_mmc3.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-        }, {
-                .clk            = {
                         .name           = "sclk_dwmmc",
                         .parent         = &clk_dout_mmc4.clk,
                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
@@ -1238,6 +1136,134 @@ static struct clksrc_clk clksrcs[] = {
         }
 };
 
+static struct clksrc_clk clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart1 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart2 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart3 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &clk_dout_mmc0.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &clk_dout_mmc1.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &clk_dout_mmc2.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &clk_dout_mmc3.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname                = "s3c64xx-spi.0",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit                = (1 << 16),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname                = "s3c64xx-spi.1",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit                = (1 << 20),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi2 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname                = "s3c64xx-spi.2",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit                = (1 << 24),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -1272,6 +1298,42 @@ static struct clksrc_clk *sysclks[] = {
         &clk_mout_mfc1,
 };
 
+static struct clk *clk_cdev[] = {
+        &clk_pdma0,
+        &clk_pdma1,
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart0,
+        &clk_sclk_uart1,
+        &clk_sclk_uart2,
+        &clk_sclk_uart3,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_mmc3,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_spi2,
+
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
+};
+
 static int xtal_rate;
 
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1479,11 +1541,19 @@ void __init exynos4_register_clocks(void)
         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
                 s3c_register_clksrc(sclk_tv[ptr], 1);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
+
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
 
         register_syscore_ops(&exynos4_clock_syscore_ops);
         s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index b6ac6ee658c..c59e1887100 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -17,8 +17,11 @@
 #include <linux/gpio.h>
 #include <linux/sched.h>
 #include <linux/serial_core.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/proc-fns.h>
+#include <asm/exception.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -43,8 +46,6 @@
 
 #include "common.h"
 
-unsigned int gic_bank_offset __read_mostly;
-
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
@@ -386,27 +387,26 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
         }
 }
 
-static void exynos4_gic_irq_fix_base(struct irq_data *d)
-{
-        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-
-        gic_data->cpu_base = S5P_VA_GIC_CPU +
-                            (gic_bank_offset * smp_processor_id());
-
-        gic_data->dist_base = S5P_VA_GIC_DIST +
-                            (gic_bank_offset * smp_processor_id());
-}
+#ifdef CONFIG_OF
+static const struct of_device_id exynos4_dt_irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {},
+};
+#endif
 
 void __init exynos4_init_irq(void)
 {
         int irq;
+        unsigned int gic_bank_offset;
 
         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 
-        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-        gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
-        gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
-        gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
+        if (!of_have_populated_dt())
+                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
+#ifdef CONFIG_OF
+        else
+                of_irq_init(exynos4_dt_irq_match);
+#endif
 
         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 
@@ -474,15 +474,6 @@ int __init exynos_init(void)
         return device_register(&exynos4_dev);
 }
 
-static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk1",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-
 /* uart registration process */
 
 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -490,16 +481,10 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
         struct s3c2410_uartcfg *tcfg = cfg;
         u32 ucnt;
 
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->has_fracval = 1;
-                        tcfg->clocks = exynos4_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
-                }
-                tcfg->flags |= NO_NEED_CHECK_CLKSRC;
-        }
+        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
+                tcfg->has_fracval = 1;
 
-        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
+        s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
 }
 
 static DEFINE_SPINLOCK(eint_lock);
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
new file mode 100644
index 00000000000..b8e75300c77
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -0,0 +1,52 @@
+/* linux/arch/arm/mach-exynos/dev-ohci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - OHCI support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/ohci.h>
+
+#include <plat/devs.h>
+#include <plat/usb-phy.h>
+
+static struct resource exynos4_ohci_resource[] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
+        [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
+};
+
+static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_ohci = {
+        .name           = "exynos-ohci",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(exynos4_ohci_resource),
+        .resource       = exynos4_ohci_resource,
+        .dev            = {
+                .dma_mask               = &exynos4_ohci_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
+{
+        struct exynos4_ohci_platdata *npd;
+
+        npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
+                        &exynos4_device_ohci);
+
+        if (!npd->phy_init)
+                npd->phy_init = s5p_usb_phy_init;
+        if (!npd->phy_exit)
+                npd->phy_exit = s5p_usb_phy_exit;
+}
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 9667c61e64f..b10fcd270f0 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl330.h>
+#include <linux/of.h>
 
 #include <asm/irq.h>
 #include <plat/devs.h>
@@ -35,95 +36,42 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-struct dma_pl330_peri pdma0_peri[28] = {
-        {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ0,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ2,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART4_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART4_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS4_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS4_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_AC97_MICIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        },
+u8 pdma0_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM2_RX,
+        DMACH_PCM2_TX,
+        DMACH_MSM_REQ0,
+        DMACH_MSM_REQ2,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
 };
 
 struct dma_pl330_platdata exynos4_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri = pdma0_peri,
+        .peri_id = pdma0_peri,
 };
 
 struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +90,37 @@ struct amba_device exynos4_device_pdma0 = {
         .periphid = 0x00041330,
 };
 
-struct dma_pl330_peri pdma1_peri[25] = {
-        {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ1,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ3,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS5_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS5_TX,
-                .rqtype = MEMTODEV,
-        },
+u8 pdma1_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_MSM_REQ1,
+        DMACH_MSM_REQ3,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
 };
 
 struct dma_pl330_platdata exynos4_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri = pdma1_peri,
+        .peri_id = pdma1_peri,
 };
 
 struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +141,15 @@ struct amba_device exynos4_device_pdma1 = {
 
 static int __init exynos4_dma_init(void)
 {
+        if (of_have_populated_dt())
+                return 0;
+
+        dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
         amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+
+        dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
         amba_device_register(&exynos4_device_pdma1, &iomem_resource);
 
         return 0;
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index dfd4b7eecb9..f77bce04789 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -17,13 +17,13 @@
 
 /* PPI: Private Peripheral Interrupt */
 
-#define IRQ_PPI(x)              S5P_IRQ(x+16)
+#define IRQ_PPI(x)              (x+16)
 
 #define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
 
 /* SPI: Shared Peripheral Interrupt */
 
-#define IRQ_SPI(x)              S5P_IRQ(x+32)
+#define IRQ_SPI(x)              (x+32)
 
 #define IRQ_EINT0               IRQ_SPI(16)
 #define IRQ_EINT1               IRQ_SPI(17)
@@ -72,6 +72,9 @@
 #define IRQ_IIC5                IRQ_SPI(63)
 #define IRQ_IIC6                IRQ_SPI(64)
 #define IRQ_IIC7                IRQ_SPI(65)
+#define IRQ_SPI0                IRQ_SPI(66)
+#define IRQ_SPI1                IRQ_SPI(67)
+#define IRQ_SPI2                IRQ_SPI(68)
 
 #define IRQ_USB_HOST            IRQ_SPI(70)
 #define IRQ_USB_HSOTG           IRQ_SPI(71)
@@ -163,7 +166,9 @@
 #define IRQ_GPIO2_NR_GROUPS     9
 #define IRQ_GPIO_END            (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
+#define IRQ_TIMER_BASE          (IRQ_GPIO_END + 64)
+
 /* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_GPIO_END + 64)
+#define NR_IRQS                 (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index d1829860a0e..c754a22a2bb 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -87,6 +87,10 @@
 #define EXYNOS4_PA_SYSMMU_TV            0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
+#define EXYNOS4_PA_SPI0                 0x13920000
+#define EXYNOS4_PA_SPI1                 0x13930000
+#define EXYNOS4_PA_SPI2                 0x13940000
+
 
 #define EXYNOS4_PA_GPIO1                0x11400000
 #define EXYNOS4_PA_GPIO2                0x11000000
@@ -107,6 +111,7 @@
 #define EXYNOS4_PA_SROMC                0x12570000
 
 #define EXYNOS4_PA_EHCI                 0x12580000
+#define EXYNOS4_PA_OHCI                 0x12590000
 #define EXYNOS4_PA_HSPHY                0x125B0000
 #define EXYNOS4_PA_MFC                  0x13400000
 
@@ -148,6 +153,9 @@
 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
 #define S3C_PA_UART                     EXYNOS4_PA_UART
+#define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
+#define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
+#define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
 
 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/include/mach/ohci.h b/arch/arm/mach-exynos/include/mach/ohci.h
new file mode 100644
index 00000000000..c256c595be5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/ohci.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MACH_EXYNOS_OHCI_H
+#define __MACH_EXYNOS_OHCI_H
+
+struct exynos4_ohci_platdata {
+        int (*phy_init)(struct platform_device *pdev, int type);
+        int (*phy_exit)(struct platform_device *pdev, int type);
+};
+
+extern void exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd);
+
+#endif /* __MACH_EXYNOS_OHCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
new file mode 100644
index 00000000000..576efdf6d09
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2011 Samsung Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SPI_CLKS_H
+#define __ASM_ARCH_SPI_CLKS_H __FILE__
+
+/* Must source from SCLK_SPI */
+#define EXYNOS4_SPI_SRCCLK_SCLK         0
+
+#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
new file mode 100644
index 00000000000..85fa02767d6
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -0,0 +1,85 @@
+/*
+ * Samsung's Exynos4210 flattened device tree enabled machine
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the Exynos4 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
+                                "exynos4210-uart.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
+                                "exynos4210-uart.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
+                                "exynos4210-uart.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
+                                "exynos4210-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
+                                "exynos4-sdhci.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
+                                "exynos4-sdhci.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
+                                "exynos4-sdhci.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
+                                "exynos4-sdhci.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
+                                "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+        {},
+};
+
+static void __init exynos4210_dt_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+}
+
+static void __init exynos4210_dt_machine_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                                exynos4210_auxdata_lookup, NULL);
+}
+
+static char const *exynos4210_dt_compat[] __initdata = {
+        "samsung,exynos4210",
+        NULL
+};
+
+DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
+        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
+        .init_irq       = exynos4_init_irq,
+        .map_io         = exynos4210_dt_map_io,
+        .init_machine   = exynos4210_dt_machine_init,
+        .timer          = &exynos4_timer,
+        .dt_compat      = exynos4210_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 635fb97e31a..b895ec03110 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -249,13 +249,8 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 
 static int nuri_bl_init(struct device *dev)
 {
-        int ret, gpio = EXYNOS4_GPE2(3);
-
-        ret = gpio_request(gpio, "LCD_LDO_EN");
-        if (!ret)
-                gpio_direction_output(gpio, 0);
-
-        return ret;
+        return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
+                                "LCD_LD0_EN");
 }
 
 static int nuri_bl_notify(struct device *dev, int brightness)
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 586eb995aa9..2b11e046d39 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -41,6 +41,7 @@
 #include <plat/fb.h>
 #include <plat/mfc.h>
 
+#include <mach/ohci.h>
 #include <mach/map.h>
 
 #include "common.h"
@@ -485,6 +486,16 @@ static void __init origen_ehci_init(void)
         s5p_ehci_set_platdata(pdata);
 }
 
+/* USB OHCI */
+static struct exynos4_ohci_platdata origen_ohci_pdata;
+
+static void __init origen_ohci_init(void)
+{
+        struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
+
+        exynos4_ohci_set_platdata(pdata);
+}
+
 static struct gpio_keys_button origen_gpio_keys_table[] = {
         {
                 .code                   = KEY_MENU,
@@ -608,6 +619,7 @@ static struct platform_device *origen_devices[] __initdata = {
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
         &s5p_device_mixer,
+        &exynos4_device_ohci,
         &exynos4_device_pd[PD_LCD0],
         &exynos4_device_pd[PD_TV],
         &exynos4_device_pd[PD_G3D],
@@ -672,6 +684,7 @@ static void __init origen_machine_init(void)
         s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
 
         origen_ehci_init();
+        origen_ohci_init();
         clk_xusbxti.rate = 24000000;
 
         s5p_tv_setup();
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 5b365613b47..b2c5557f50e 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -42,6 +42,7 @@
 #include <plat/clock.h>
 
 #include <mach/map.h>
+#include <mach/ohci.h>
 
 #include "common.h"
 
@@ -131,9 +132,7 @@ static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
                 gpio_free(EXYNOS4_GPD0(1));
 #endif
                 /* fire nRESET on power up */
-                gpio_request(EXYNOS4_GPX0(6), "GPX0");
-
-                gpio_direction_output(EXYNOS4_GPX0(6), 1);
+                gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
                 mdelay(100);
 
                 gpio_set_value(EXYNOS4_GPX0(6), 0);
@@ -247,6 +246,16 @@ static void __init smdkv310_ehci_init(void)
         s5p_ehci_set_platdata(pdata);
 }
 
+/* USB OHCI */
+static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
+
+static void __init smdkv310_ohci_init(void)
+{
+        struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
+
+        exynos4_ohci_set_platdata(pdata);
+}
+
 static struct platform_device *smdkv310_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
@@ -263,6 +272,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &s5p_device_fimc3,
         &exynos4_device_ac97,
         &exynos4_device_i2s0,
+        &exynos4_device_ohci,
         &samsung_device_keypad,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
@@ -365,6 +375,7 @@ static void __init smdkv310_machine_init(void)
         s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
 
         smdkv310_ehci_init();
+        smdkv310_ohci_init();
         clk_xusbxti.rate = 24000000;
 
         platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 52aea972746..37ac93e8d6d 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -610,8 +610,7 @@ static void __init universal_tsp_init(void)
 
         /* TSP_LDO_ON: XMDMADDR_11 */
         gpio = EXYNOS4_GPE2(3);
-        gpio_request(gpio, "TSP_LDO_ON");
-        gpio_direction_output(gpio, 1);
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
         gpio_export(gpio, 0);
 
         /* TSP_INT: XMDMADDR_7 */
@@ -671,8 +670,7 @@ static void __init universal_touchkey_init(void)
         i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
 
         gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
-        gpio_request(gpio, "3_TOUCH_EN");
-        gpio_direction_output(gpio, 1);
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
 }
 
 static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
@@ -1002,9 +1000,7 @@ static void __init universal_map_io(void)
 void s5p_tv_setup(void)
 {
         /* direct HPD to HDMI chip */
-        gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
-
-        gpio_direction_input(EXYNOS4_GPX3(7));
+        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
         s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
         s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c4f792dcad1..a4f61a43c7b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,6 +23,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/smp_scu.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct device *dev)
         return 0;
 }
 
-/* This function copy from linux/arch/arm/kernel/smp_scu.c */
-
-void exynos4_scu_enable(void __iomem *scu_base)
-{
-        u32 scu_ctrl;
-
-        scu_ctrl = __raw_readl(scu_base);
-        /* already enabled? */
-        if (scu_ctrl & 1)
-                return;
-
-        scu_ctrl |= 1;
-        __raw_writel(scu_ctrl, scu_base);
-
-        /*
-         * Ensure that the data accessed by CPU0 before the SCU was
-         * initialised is visible to the other CPUs.
-         */
-        flush_cache_all();
-}
-
 static unsigned long pll_base_rate;
 
 static void exynos4_restore_pll(void)
@@ -404,7 +384,7 @@ static void exynos4_pm_resume(void)
 
         exynos4_restore_pll();
 
-        exynos4_scu_enable(S5P_VA_SCU);
+        scu_enable(S5P_VA_SCU);
 
 #ifdef CONFIG_CACHE_L2X0
         s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
deleted file mode 100644
index 92937b41090..00000000000
--- a/arch/arm/mach-exynos/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *exynos4_hsmmc_clksrcs[4] = {
-        [0] = NULL,
-        [1] = NULL,
-        [2] = "sclk_mmc",       /* mmc_bus */
-        [3] = NULL,
-};
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
new file mode 100644
index 00000000000..833ff40ee0e
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -0,0 +1,72 @@
+/* linux/arch/arm/mach-exynos4/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *             http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .clk_from_cmu   = true,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .clk_from_cmu   = true,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI2
+struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .clk_from_cmu   = true,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
+        s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
+                              S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 39aca045f66..41743d21e8c 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -19,6 +19,13 @@
 #include <plat/cpu.h>
 #include <plat/usb-phy.h>
 
+static atomic_t host_usage;
+
+static int exynos4_usb_host_phy_is_on(void)
+{
+        return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+}
+
 static int exynos4_usb_phy1_init(struct platform_device *pdev)
 {
         struct clk *otg_clk;
@@ -27,6 +34,8 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
         u32 rstcon;
         int err;
 
+        atomic_inc(&host_usage);
+
         otg_clk = clk_get(&pdev->dev, "otg");
         if (IS_ERR(otg_clk)) {
                 dev_err(&pdev->dev, "Failed to get otg clock\n");
@@ -39,6 +48,9 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
                 return err;
         }
 
+        if (exynos4_usb_host_phy_is_on())
+                return 0;
+
         writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
                         S5P_USBHOST_PHY_CONTROL);
 
@@ -95,6 +107,9 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev)
         struct clk *otg_clk;
         int err;
 
+        if (atomic_dec_return(&host_usage) > 0)
+                return 0;
+
         otg_clk = clk_get(&pdev->dev, "otg");
         if (IS_ERR(otg_clk)) {
                 dev_err(&pdev->dev, "Failed to get otg clock\n");
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 35a218cb5c7..0e6de366c64 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -98,6 +98,7 @@ config MACH_SCB9328
 config MACH_APF9328
         bool "APF9328"
         select SOC_IMX1
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Say Yes here if you are using the Armadeus APF9328 development board
@@ -595,6 +596,7 @@ comment "i.MX6 family:"
 
 config SOC_IMX6Q
         bool "i.MX6 Quad support"
+        select ARM_CPU_SUSPEND if PM
         select ARM_GIC
         select CPU_V7
         select HAVE_ARM_SCU
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d97f409ce98..f5920c24f7d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -70,4 +70,8 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
+
+ifeq ($(CONFIG_PM),y)
+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
+endif
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index cfede5768aa..5f4d06af491 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -25,3 +25,6 @@ initrd_phys-$(CONFIG_SOC_IMX35)	:= 0x80800000
 zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
+
+dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
+                           imx6q-sabrelite.dtb
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
index 6229efbc70c..7e49deb128a 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/head-v7.S
@@ -16,7 +16,6 @@
 #include <asm/hardware/cache-l2x0.h>
 
         .section ".text.head", "ax"
-        __CPUINIT
 
 /*
  * The secondary kernel init calls v7_flush_dcache_all before it enables
@@ -33,6 +32,7 @@
  */
 ENTRY(v7_invalidate_l1)
         mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
         mcr     p15, 2, r0, c0, c0, 0
         mrc     p15, 1, r0, c0, c0, 0
 
@@ -71,6 +71,7 @@ ENTRY(v7_secondary_startup)
 ENDPROC(v7_secondary_startup)
 #endif
 
+#ifdef CONFIG_PM
 /*
  * The following code is located into the .data section.  This is to
  * allow phys_l2x0_saved_regs to be accessed with a relative load
@@ -79,6 +80,7 @@ ENDPROC(v7_secondary_startup)
         .data
         .align
 
+#ifdef CONFIG_CACHE_L2X0
         .macro  pl310_resume
         ldr     r2, phys_l2x0_saved_regs
         ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
@@ -88,12 +90,17 @@ ENDPROC(v7_secondary_startup)
         str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
         .endm
 
+        .globl  phys_l2x0_saved_regs
+phys_l2x0_saved_regs:
+        .long   0
+#else
+        .macro  pl310_resume
+        .endm
+#endif
+
 ENTRY(v7_cpu_resume)
         bl      v7_invalidate_l1
         pl310_resume
         b       cpu_resume
 ENDPROC(v7_cpu_resume)
-
-        .globl  phys_l2x0_saved_regs
-phys_l2x0_saved_regs:
-        .long   0
+#endif
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 146a4f07346..f4a63ee9e21 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/dm9000.h>
+#include <linux/i2c.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +42,9 @@ static const int apf9328_pins[] __initconst = {
         PB29_PF_UART2_RTS,
         PB30_PF_UART2_TXD,
         PB31_PF_UART2_RXD,
+        /* I2C */
+        PA15_PF_I2C_SDA,
+        PA16_PF_I2C_SCL,
 };
 
 /*
@@ -103,6 +107,10 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 static struct platform_device *devices[] __initdata = {
         &apf9328_flash_device,
         &dm9000x_device,
@@ -119,6 +127,8 @@ static void __init apf9328_init(void)
         imx1_add_imx_uart0(NULL);
         imx1_add_imx_uart1(&uart1_pdata);
 
+        imx1_add_imx_i2c(&apf9328_i2c_data);
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 05b49bb5d67..c2572810691 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,8 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/micrel_phy.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
@@ -56,8 +58,27 @@ soft:
         soft_restart(0);
 }
 
+/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
+static int ksz9021rn_phy_fixup(struct phy_device *phydev)
+{
+        /* min rx data delay */
+        phy_write(phydev, 0x0b, 0x8105);
+        phy_write(phydev, 0x0c, 0x0000);
+
+        /* max rx/tx clock delay, min rx/tx control delay */
+        phy_write(phydev, 0x0b, 0x8104);
+        phy_write(phydev, 0x0c, 0xf0f0);
+        phy_write(phydev, 0x0b, 0x104);
+
+        return 0;
+}
+
 static void __init imx6q_init_machine(void)
 {
+        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                                           ksz9021rn_phy_fixup);
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         imx6q_pm_init();
@@ -105,7 +126,8 @@ static struct sys_timer imx6q_timer = {
 };
 
 static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q-sabreauto",
+        "fsl,imx6q-arm2",
+        "fsl,imx6q-sabrelite",
         NULL,
 };
 
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 2b565c38134..89c33258639 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -492,7 +492,7 @@ static struct mc13xxx_platform_data mc13783_pdata = {
                 .regulators = mx31_3ds_regulators,
                 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
         },
-        .flags  = MC13XXX_USE_TOUCHSCREEN,
+        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
 };
 
 /* SPI */
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index f20f191d7cc..f7b0c2b1b90 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -64,7 +64,9 @@ void __init imx6q_pm_init(void)
          * address of the data structure used by l2x0 core to save registers,
          * and later restore the necessary ones in imx6q resume entry.
          */
+#ifdef CONFIG_CACHE_L2X0
         phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
+#endif
 
         suspend_set_ops(&imx6q_pm_ops);
 }
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 8d03bcef518..e9a7180863d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -13,12 +13,12 @@
 #include <linux/mbus.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
  * Generic Address Decode Windows bit settings
  */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_SRAM             3
 #define TARGET_PCIE             4
@@ -36,118 +36,55 @@
 #define ATTR_SRAM               0x01
 
 /*
- * Helpers to get DDR bank info
+ * Description of the windows needed by the platform code
  */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
-
-/*
- * CPU Address Decode Windows registers
- */
-#define WIN_OFF(n)              (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-
-
-struct mbus_dram_target_info kirkwood_mbus_dram_info;
-
-static int __init cpu_win_can_remap(int win)
-{
-        if (win < 4)
-                return 1;
-
-        return 0;
-}
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        void __iomem *addr = (void __iomem *)WIN_OFF(win);
-        u32 ctrl;
-
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-
-        writel(base, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-
-                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
-
-void __init kirkwood_setup_cpu_mbus(void)
-{
-        void __iomem *addr;
-        int i;
-        int cs;
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 8,
+        .remappable_wins = 4,
+        .bridge_virt_base = BRIDGE_VIRT_BASE,
+};
 
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
         /*
-         * First, disable and clear windows.
+         * Windows for PCIe IO+MEM space.
          */
-        for (i = 0; i < 8; i++) {
-                addr = (void __iomem *)WIN_OFF(i);
-
-                writel(0, addr + WIN_BASE_OFF);
-                writel(0, addr + WIN_CTRL_OFF);
-                if (cpu_win_can_remap(i)) {
-                        writel(0, addr + WIN_REMAP_LO_OFF);
-                        writel(0, addr + WIN_REMAP_HI_OFF);
-                }
-        }
-
+        { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
+          TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
+        },
+        { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+          TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
+        },
+        { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+          TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
+        },
+        { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+          TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
+        },
         /*
-         * Setup windows for PCIe IO+MEM space.
+         * Window for NAND controller.
          */
-        setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
-                      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
-        setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
-                      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
-        setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
-                      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
-        setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
-                      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
-
+        { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+          TARGET_DEV_BUS, ATTR_DEV_NAND, -1
+        },
         /*
-         * Setup window for NAND controller.
+         * Window for SRAM.
          */
-        setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
-                      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
+        { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+          TARGET_SRAM, ATTR_SRAM, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
 
+void __init kirkwood_setup_cpu_mbus(void)
+{
         /*
-         * Setup window for SRAM.
+         * Disable, clear and configure windows.
          */
-        setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
-                      TARGET_SRAM, ATTR_SRAM, -1);
+        orion_config_wins(&addr_map_cfg, addr_map_info);
 
         /*
          * Setup MBUS dram target info.
          */
-        kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
-        addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
-
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
-
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-
-                        w = &kirkwood_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        kirkwood_mbus_dram_info.num_cs = cs;
+        orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0bff4a91623..cc15426787b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
@@ -30,6 +29,7 @@
 #include <plat/orion_nand.h>
 #include <plat/common.h>
 #include <plat/time.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
 void __init kirkwood_ehci_init(void)
 {
         kirkwood_clk_ctrl |= CGC_USB0;
-        orion_ehci_init(&kirkwood_mbus_dram_info,
-                        USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
+        orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
 }
 
 
@@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
         kirkwood_clk_ctrl |= CGC_GE0;
 
-        orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
+        orion_ge00_init(eth_data,
                         GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
                         IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
 }
@@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 
         kirkwood_clk_ctrl |= CGC_GE1;
 
-        orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
+        orion_ge01_init(eth_data,
                         GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
                         IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
 }
@@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
         if (sata_data->n_ports > 1)
                 kirkwood_clk_ctrl |= CGC_SATA1;
 
-        orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
-                        SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
+        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 }
 
 
@@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
                 mvsdio_data->clock = 100000000;
         else
                 mvsdio_data->clock = 200000000;
-        mvsdio_data->dram = &kirkwood_mbus_dram_info;
         kirkwood_clk_ctrl |= CGC_SDIO;
         kirkwood_sdio.dev.platform_data = mvsdio_data;
         platform_device_register(&kirkwood_sdio);
@@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR0;
 
-        orion_xor0_init(&kirkwood_mbus_dram_info,
-                        XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
+        orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
                         IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 }
 
@@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = {
 };
 
 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
-        .dram        = &kirkwood_mbus_dram_info,
         .burst       = 128,
 };
 
@@ -430,6 +425,8 @@ static char * __init kirkwood_id(void)
         } else if (dev == MV88F6282_DEV_ID) {
                 if (rev == MV88F6282_REV_A0)
                         return "MV88F6282-Rev-A0";
+                else if (rev == MV88F6282_REV_A1)
+                        return "MV88F6282-Rev-A1";
                 else
                         return "MV88F6282-Rev-Unsupported";
         } else {
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 1529280246d..9071a397136 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,7 +30,6 @@ void kirkwood_init(void);
 void kirkwood_init_early(void);
 void kirkwood_init_irq(void);
 
-extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
 
 void kirkwood_enable_pcie(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 010bdeb4ac5..fede3d503ef 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -135,4 +135,5 @@
 
 #define MV88F6282_DEV_ID        0x6282
 #define MV88F6282_REV_A0        0
+#define MV88F6282_REV_A1        1
 #endif
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index cc431fa22cc..0c6ad63f10c 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -10,7 +10,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <plat/mpp.h>
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index ac787957e2d..e8fda45c073 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -102,6 +102,7 @@
 #define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
 
 #define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_GPIO              MPP( 12, 0x0, 1, 1, 0,   0,   0,   1,   0 )
 #define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
 #define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
 #define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 74b992d810e..fb451bfe478 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,12 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/slab.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <mach/bridge-regs.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 void kirkwood_enable_pcie(void)
@@ -208,7 +208,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
          */
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
 
-        orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
+        orion_pcie_setup(pp->base);
 
         return 1;
 }
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 3e6dfab59ef..17cb7606012 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -120,8 +120,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(27),
-                .end    = gpio_to_irq(27),
+                .start  = MMP_GPIO_TO_IRQ(27),
+                .end    = MMP_GPIO_TO_IRQ(27),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
@@ -232,6 +232,7 @@ static void __init common_init(void)
         pxa168_add_nand(&aspenite_nand_info);
         pxa168_add_fb(&aspenite_lcd_info);
         pxa168_add_keypad(&aspenite_keypad_info);
+        platform_device_register(&pxa168_device_gpio);
 
         /* off-chip devices */
         platform_device_register(&smc91x_device);
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 8de3dc6131a..b148a9dc5a4 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -38,6 +38,7 @@ static void __init avengers_lite_init(void)
 
         /* on-chip devices */
         pxa168_add_uart(2);
+        platform_device_register(&pxa168_device_gpio);
 }
 
 MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index e16f04b39b1..d839fe6421e 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -202,6 +202,7 @@ static void __init brownstone_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(3);
+        platform_device_register(&mmp2_device_gpio);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
         mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
         mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index 5a6a27a6cfd..2ee8cd7829d 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(155),
-                .end    = gpio_to_irq(155),
+                .start  = MMP_GPIO_TO_IRQ(155),
+                .end    = MMP_GPIO_TO_IRQ(155),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
@@ -110,6 +110,7 @@ static void __init flint_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(2);
+        platform_device_register(&mmp2_device_gpio);
 
         /* off-chip devices */
         platform_device_register(&smc91x_device);
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 1e3abbe37ca..87765467de6 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -184,6 +184,7 @@ static void __init gplugd_init(void)
         pxa168_add_uart(3);
         pxa168_add_ssp(1);
         pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
+        platform_device_register(&pxa168_device_gpio);
 
         pxa168_add_eth(&gplugd_eth_platform_data);
 }
diff --git a/arch/arm/mach-mmp/include/mach/gpio-pxa.h b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
index 99b4ce1b656..0e135a599f3 100644
--- a/arch/arm/mach-mmp/include/mach/gpio-pxa.h
+++ b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
@@ -2,6 +2,7 @@
 #define __ASM_MACH_GPIO_PXA_H
 
 #include <mach/addr-map.h>
+#include <mach/cputype.h>
 #include <mach/irqs.h>
 
 #define GPIO_REGS_VIRT  (APB_VIRT_BASE + 0x19000)
@@ -9,8 +10,6 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
 
-#define NR_BUILTIN_GPIO         IRQ_GPIO_NUM
-
 #define gpio_to_bank(gpio)      ((gpio) >> 5)
 
 /* NOTE: these macros are defined here to make optimization of
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index 681262359d1..13219ebf512 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -3,11 +3,6 @@
 
 #include <asm-generic/gpio.h>
 
-#define gpio_to_irq(gpio)       (IRQ_GPIO_START + (gpio))
-#define irq_to_gpio(irq)        ((irq) - IRQ_GPIO_START)
+#include <mach/cputype.h>
 
-#define __gpio_is_inverted(gpio)        (0)
-#define __gpio_is_occupied(gpio)        (0)
-
-#include <plat/gpio.h>
 #endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index a09d328e2dd..34635a0bbb5 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -219,10 +219,10 @@
 #define IRQ_MMP2_MUX_END                (IRQ_MMP2_SSP_BASE + 2)
 
 #define IRQ_GPIO_START                  128
-#define IRQ_GPIO_NUM                    192
-#define IRQ_GPIO(x)                     (IRQ_GPIO_START + (x))
+#define MMP_NR_BUILTIN_GPIO             192
+#define MMP_GPIO_TO_IRQ(gpio)           (IRQ_GPIO_START + (gpio))
 
-#define IRQ_BOARD_START                 (IRQ_GPIO_START + IRQ_GPIO_NUM)
+#define IRQ_BOARD_START                 (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
 
 #define NR_IRQS                         (IRQ_BOARD_START)
 
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index 2f7b2d3c2b1..cba22fed226 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -32,6 +32,8 @@ extern struct pxa_device_desc mmp2_device_sdh3;
 extern struct pxa_device_desc mmp2_device_asram;
 extern struct pxa_device_desc mmp2_device_isram;
 
+extern struct platform_device mmp2_device_gpio;
+
 static inline int mmp2_add_uart(int id)
 {
         struct pxa_device_desc *d = NULL;
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index a677aa732c2..dc03d580a06 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -43,6 +43,8 @@ struct pxa168_usb_pdata {
 /* pdata can be NULL */
 int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata);
 
+extern struct platform_device pxa168_device_gpio;
+
 static inline int pxa168_add_uart(int id)
 {
         struct pxa_device_desc *d = NULL;
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 91be7559139..4de13abef7b 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -21,6 +21,8 @@ extern struct pxa_device_desc pxa910_device_pwm3;
 extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
 
+extern struct platform_device pxa910_device_gpio;
+
 static inline int pxa910_add_uart(int id)
 {
         struct pxa_device_desc *d = NULL;
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 5dd1d4a6aeb..617c60a170a 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 
 #include <asm/hardware/cache-tauros2.h>
 
@@ -24,7 +25,6 @@
 #include <mach/irqs.h>
 #include <mach/dma.h>
 #include <mach/mfp.h>
-#include <mach/gpio-pxa.h>
 #include <mach/devices.h>
 #include <mach/mmp2.h>
 
@@ -33,8 +33,6 @@
 
 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
 
-#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
-
 static struct mfp_addr_map mmp2_addr_map[] __initdata = {
 
         MFP_ADDR_X(GPIO0, GPIO58, 0x54),
@@ -95,24 +93,9 @@ void mmp2_clear_pmic_int(void)
         __raw_writel(data, mfpr_pmic);
 }
 
-static void __init mmp2_init_gpio(void)
-{
-        int i;
-
-        /* enable GPIO clock */
-        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO);
-
-        /* unmask GPIO edge detection for all 6 banks -- APMASKx */
-        for (i = 0; i < 6; i++)
-                __raw_writel(0xffffffff, APMASK(i));
-
-        pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL);
-}
-
 void __init mmp2_init_irq(void)
 {
         mmp2_init_icu();
-        mmp2_init_gpio();
 }
 
 static void sdhc_clk_enable(struct clk *clk)
@@ -149,6 +132,7 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
 static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
 static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
+static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
 
 static APMU_CLK(nand, NAND, 0xbf, 100000000);
 static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
@@ -168,6 +152,7 @@ static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
         INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
         INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
         INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
         INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
@@ -230,3 +215,21 @@ MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
 /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
 MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
 
+struct resource mmp2_resource_gpio[] = {
+        {
+                .start  = 0xd4019000,
+                .end    = 0xd4019fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MMP2_GPIO,
+                .end    = IRQ_MMP2_GPIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mmp2_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mmp2_resource_gpio),
+        .resource       = mmp2_resource_gpio,
+};
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 13f23867a86..7bc17eaa12e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -13,6 +13,7 @@
 #include <linux/list.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
@@ -20,7 +21,6 @@
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/irqs.h>
-#include <mach/gpio-pxa.h>
 #include <mach/dma.h>
 #include <mach/devices.h>
 #include <mach/mfp.h>
@@ -43,26 +43,9 @@ static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
         MFP_ADDR_END,
 };
 
-#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
-
-static void __init pxa168_init_gpio(void)
-{
-        int i;
-
-        /* enable GPIO clock */
-        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO);
-
-        /* unmask GPIO edge detection for all 4 banks - APMASKx */
-        for (i = 0; i < 4; i++)
-                __raw_writel(0xffffffff, APMASK(i));
-
-        pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL);
-}
-
 void __init pxa168_init_irq(void)
 {
         icu_init_irq();
-        pxa168_init_gpio();
 }
 
 /* APB peripheral clocks */
@@ -80,6 +63,7 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
 static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
+static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
@@ -105,6 +89,7 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
         INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
         INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
@@ -174,6 +159,25 @@ PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
 PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
 PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
 
+struct resource pxa168_resource_gpio[] = {
+        {
+                .start  = 0xd4019000,
+                .end    = 0xd4019fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PXA168_GPIOX,
+                .end    = IRQ_PXA168_GPIOX,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa168_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa168_resource_gpio),
+        .resource       = pxa168_resource_gpio,
+};
+
 struct resource pxa168_usb_host_resources[] = {
         /* USB Host conroller register base */
         [0] = {
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 4ebbfbba39f..3241a25784d 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
@@ -19,7 +20,6 @@
 #include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
-#include <mach/gpio-pxa.h>
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
@@ -77,26 +77,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
         MFP_ADDR_END,
 };
 
-#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
-
-static void __init pxa910_init_gpio(void)
-{
-        int i;
-
-        /* enable GPIO clock */
-        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO);
-
-        /* unmask GPIO edge detection for all 4 banks - APMASKx */
-        for (i = 0; i < 4; i++)
-                __raw_writel(0xffffffff, APMASK(i));
-
-        pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL);
-}
-
 void __init pxa910_init_irq(void)
 {
         icu_init_irq();
-        pxa910_init_gpio();
 }
 
 /* APB peripheral clocks */
@@ -108,6 +91,7 @@ static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
 static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
+static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(u2o, USB, 0x1b, 480000000);
@@ -123,6 +107,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
         INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
         INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
 };
 
@@ -179,3 +164,22 @@ PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
 PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
+
+struct resource pxa910_resource_gpio[] = {
+        {
+                .start  = 0xd4019000,
+                .end    = 0xd4019fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PXA910_AP_GPIO,
+                .end    = IRQ_PXA910_AP_GPIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa910_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa910_resource_gpio),
+        .resource       = pxa910_resource_gpio,
+};
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index 257a21283ec..8e3b5af04a5 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -19,6 +19,7 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
+#include <mach/irqs.h>
 
 #include "common.h"
 
@@ -71,8 +72,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(80),
-                .end    = gpio_to_irq(80),
+                .start  = MMP_GPIO_TO_IRQ(80),
+                .end    = MMP_GPIO_TO_IRQ(80),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
@@ -93,6 +94,7 @@ static void __init tavorevb_init(void)
 
         /* on-chip devices */
         pxa910_add_uart(1);
+        platform_device_register(&pxa910_device_gpio);
 
         /* off-chip devices */
         platform_device_register(&smc91x_device);
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index 8ac22a62bf1..0523e422990 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
 static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
         {
                 I2C_BOARD_INFO("ds1337", 0x68),
-                .irq = gpio_to_irq(RTC_INT_GPIO)
+                .irq = MMP_GPIO_TO_IRQ(RTC_INT_GPIO)
         },
 };
 
@@ -78,6 +78,7 @@ static void __init teton_bga_init(void)
         pxa168_add_uart(1);
         pxa168_add_keypad(&teton_bga_keypad_info);
         pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+        platform_device_register(&pxa168_device_gpio);
 }
 
 MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index f0265882557..5ac5d5832e4 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -24,12 +24,13 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
+#include <mach/irqs.h>
 
 #include "common.h"
 
-#define TTCDKB_GPIO_EXT0(x)     (NR_BUILTIN_GPIO + ((x < 0) ? 0 :       \
+#define TTCDKB_GPIO_EXT0(x)     (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 :   \
                                 ((x < 16) ? x : 15)))
-#define TTCDKB_GPIO_EXT1(x)     (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 :  \
+#define TTCDKB_GPIO_EXT1(x)     (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
                                 ((x < 16) ? x : 15)))
 
 /*
@@ -122,6 +123,7 @@ static struct platform_device ttc_dkb_device_onenand = {
 };
 
 static struct platform_device *ttc_dkb_devices[] = {
+        &pxa910_device_gpio,
         &ttc_dkb_device_onenand,
 };
 
@@ -136,7 +138,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = {
         {
                 .type           = "max7312",
                 .addr           = 0x23,
-                .irq            = IRQ_GPIO(80),
+                .irq            = MMP_GPIO_TO_IRQ(80),
                 .platform_data  = &max7312_data,
         },
 };
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index e6beaff7621..1cd40ad301d 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -13,7 +13,6 @@ config ARCH_MSM7X00A
         select CPU_V6
         select GPIO_MSM_V1
         select MSM_PROC_COMM
-        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_MSM7X30
         bool "MSM7x30"
@@ -25,7 +24,6 @@ config ARCH_MSM7X30
         select MSM_GPIOMUX
         select GPIO_MSM_V1
         select MSM_PROC_COMM
-        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_QSD8X50
         bool "QSD8X50"
@@ -37,7 +35,6 @@ config ARCH_QSD8X50
         select MSM_GPIOMUX
         select GPIO_MSM_V1
         select MSM_PROC_COMM
-        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_MSM8X60
         bool "MSM8X60"
@@ -63,6 +60,9 @@ config ARCH_MSM8960
 
 endchoice
 
+config MSM_HAS_DEBUG_UART_HS
+        bool
+
 config MSM_SOC_REV_A
         bool
 config  ARCH_MSM_SCORPIONMP
@@ -74,9 +74,6 @@ config  ARCH_MSM_ARM11
 config  ARCH_MSM_SCORPION
         bool
 
-config HAS_MSM_DEBUG_UART_PHYS
-        bool
-
 config  MSM_VIC
         bool
 
@@ -153,32 +150,6 @@ config MACH_MSM8960_RUMI3
 
 endmenu
 
-config MSM_DEBUG_UART
-        int
-        default 1 if MSM_DEBUG_UART1
-        default 2 if MSM_DEBUG_UART2
-        default 3 if MSM_DEBUG_UART3
-
-if HAS_MSM_DEBUG_UART_PHYS
-choice
-        prompt "Debug UART"
-
-        default MSM_DEBUG_UART_NONE
-
-        config MSM_DEBUG_UART_NONE
-                bool "None"
-
-        config MSM_DEBUG_UART1
-                bool "UART1"
-
-        config MSM_DEBUG_UART2
-                bool "UART2"
-
-        config MSM_DEBUG_UART3
-                bool "UART3"
-endchoice
-endif
-
 config MSM_SMD_PKG3
         bool
 
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 2dc73ccddb1..3ffd8668c9a 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -1,6 +1,7 @@
-/* arch/arm/mach-msm7200/include/mach/debug-macro.S
+/*
  *
  * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -14,40 +15,52 @@
  *
  */
 
-
-
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
-#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
         .macro  addruart, rp, rv, tmp
+#ifdef MSM_DEBUG_UART_PHYS
         ldr     \rp, =MSM_DEBUG_UART_PHYS
         ldr     \rv, =MSM_DEBUG_UART_BASE
+#endif
         .endm
 
-        .macro  senduart,rd,rx
+        .macro  senduart, rd, rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        @ Write the 1 character to UARTDM_TF
+        str     \rd, [\rx, #0x70]
+#else
         teq     \rx, #0
         strne   \rd, [\rx, #0x0C]
+#endif
         .endm
 
-        .macro  waituart,rd,rx
+        .macro  waituart, rd, rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        @ check for TX_EMT in UARTDM_SR
+        ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x08
+        bne     1002f
+        @ wait for TXREADY in UARTDM_ISR
+1001:   ldr     \rd, [\rx, #0x14]
+        tst     \rd, #0x80
+        beq     1001b
+1002:
+        @ Clear TX_READY by writing to the UARTDM_CR register
+        mov     \rd, #0x300
+        str     \rd, [\rx, #0x10]
+        @ Write 0x1 to NCF register
+        mov     \rd, #0x1
+        str     \rd, [\rx, #0x40]
+        @ UARTDM reg. Read to induce delay
+        ldr     \rd, [\rx, #0x08]
+#else
         @ wait for TX_READY
 1001:   ldr     \rd, [\rx, #0x08]
         tst     \rd, #0x04
         beq     1001b
-        .endm
-#else
-        .macro  addruart, rp, rv, tmp
-        mov     \rv, #0xff000000
-        orr     \rv, \rv, #0x00f00000
-        .endm
-
-        .macro  senduart,rd,rx
-        .endm
-
-        .macro  waituart,rd,rx
-        .endm
 #endif
+        .endm
 
-        .macro  busyuart,rd,rx
+        .macro  busyuart, rd, rx
         .endm
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 94fe9fe6feb..8af46123dab 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -78,18 +78,6 @@
 #define MSM_UART3_PHYS        0xA9C00000
 #define MSM_UART3_SIZE        SZ_4K
 
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE   0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE   SZ_4K
-#endif
-
 #define MSM_SDC1_PHYS         0xA0400000
 #define MSM_SDC1_SIZE         SZ_4K
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 37694442d1b..198202c267c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -89,18 +89,6 @@
 #define MSM_UART3_PHYS        0xACC00000
 #define MSM_UART3_SIZE        SZ_4K
 
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE   0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE   SZ_4K
-#endif
-
 #define MSM_MDC_BASE          IOMEM(0xE0200000)
 #define MSM_MDC_PHYS          0xAA500000
 #define MSM_MDC_SIZE          SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 3c9d9602a31..800b55767e6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -45,4 +45,9 @@
 #define MSM8960_TMR0_PHYS       0x0208A000
 #define MSM8960_TMR0_SIZE       SZ_4K
 
+#ifdef CONFIG_DEBUG_MSM8960_UART
+#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_PHYS     0x16440000
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index d67cd73316f..0faa894729b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -83,18 +83,6 @@
 #define MSM_UART3_PHYS        0xA9C00000
 #define MSM_UART3_SIZE        SZ_4K
 
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE   0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE   SZ_4K
-#endif
-
 #define MSM_MDC_BASE          IOMEM(0xE0200000)
 #define MSM_MDC_PHYS          0xAA500000
 #define MSM_MDC_SIZE          SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 3b19b8f244b..54e12caa8d8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -62,4 +62,9 @@
 #define MSM8X60_TMR0_PHYS       0x02040000
 #define MSM8X60_TMR0_SIZE       SZ_4K
 
+#ifdef CONFIG_DEBUG_MSM8660_UART
+#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_PHYS     0x19C40000
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 4ded15238b6..90682f4599d 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,18 @@
 
 #include "msm_iomap-8960.h"
 
+#define MSM_DEBUG_UART_SIZE     SZ_4K
+#if defined(CONFIG_DEBUG_MSM_UART1)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART1_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART2)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART2_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART3)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART3_PHYS
+#endif
+
 /* Virtual addresses shared across all MSM targets. */
 #define MSM_CSR_BASE            IOMEM(0xE0001000)
 #define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index d94292c29d8..169a8400745 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -1,6 +1,6 @@
-/* arch/arm/mach-msm/include/mach/uncompress.h
- *
+/*
  * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -14,17 +14,40 @@
  */
 
 #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+#define __ASM_ARCH_MSM_UNCOMPRESS_H
+
+#include <asm/processor.h>
+#include <mach/msm_iomap.h>
+
+#define UART_CSR      (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
+#define UART_TF       (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
 
-#include "hardware.h"
-#include "linux/io.h"
-#include "mach/msm_iomap.h"
+#define UART_DM_SR    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
+#define UART_DM_CR    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
+#define UART_DM_ISR   (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
+#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
+#define UART_DM_TF    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
 
 static void putc(int c)
 {
 #if defined(MSM_DEBUG_UART_PHYS)
-        unsigned base = MSM_DEBUG_UART_PHYS;
-        while (!(readl(base + 0x08) & 0x04)) ;
-        writel(c, base + 0x0c);
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        /*
+         * Wait for TX_READY to be set; but skip it if we have a
+         * TX underrun.
+         */
+        if (UART_DM_SR & 0x08)
+                while (!(UART_DM_ISR & 0x80))
+                        cpu_relax();
+
+        UART_DM_CR = 0x300;
+        UART_DM_NCHAR = 0x1;
+        UART_DM_TF = c;
+#else
+        while (!(UART_CSR & 0x04))
+                cpu_relax();
+        UART_TF = c;
+#endif
 #endif
 }
 
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 8759ecf7454..578b04e42de 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -47,7 +47,8 @@ static struct map_desc msm_io_desc[] __initdata = {
         MSM_CHIP_DEVICE(GPIO1, MSM7X00),
         MSM_CHIP_DEVICE(GPIO2, MSM7X00),
         MSM_DEVICE(CLK_CTL),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+        defined(CONFIG_DEBUG_MSM_UART3)
         MSM_DEVICE(DEBUG_UART),
 #endif
 #ifdef CONFIG_ARCH_MSM7X30
@@ -84,7 +85,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
         MSM_DEVICE(SCPLL),
         MSM_DEVICE(AD5),
         MSM_DEVICE(MDC),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+        defined(CONFIG_DEBUG_MSM_UART3)
         MSM_DEVICE(DEBUG_UART),
 #endif
         {
@@ -109,6 +111,9 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
         MSM_CHIP_DEVICE(TMR0, MSM8X60),
         MSM_DEVICE(ACC),
         MSM_DEVICE(GCC),
+#ifdef CONFIG_DEBUG_MSM8660_UART
+        MSM_DEVICE(DEBUG_UART),
+#endif
 };
 
 void __init msm_map_msm8x60_io(void)
@@ -123,6 +128,9 @@ static struct map_desc msm8960_io_desc[] __initdata = {
         MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
         MSM_CHIP_DEVICE(TMR, MSM8960),
         MSM_CHIP_DEVICE(TMR0, MSM8960),
+#ifdef CONFIG_DEBUG_MSM8960_UART
+        MSM_DEVICE(DEBUG_UART),
+#endif
 };
 
 void __init msm_map_msm8960_io(void)
@@ -146,7 +154,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
         MSM_DEVICE(SAW),
         MSM_DEVICE(GCC),
         MSM_DEVICE(TCSR),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+        defined(CONFIG_DEBUG_MSM_UART3)
         MSM_DEVICE(DEBUG_UART),
 #endif
         {
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index fdec58aaa35..0b3e357c4c8 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -79,7 +79,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
         ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
                                 SCM_FLAG_COLDBOOT_CPU1);
         if (ret == 0) {
-                void *sc1_base_ptr;
+                void __iomem *sc1_base_ptr;
                 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
                 if (sc1_base_ptr) {
                         writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index afeeca52fc6..11d0d8f2656 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,6 +1,7 @@
-/* linux/arch/arm/mach-msm/timer.c
+/*
  *
  * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -13,306 +14,207 @@
  *
  */
 
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <linux/init.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/delay.h>
 #include <linux/io.h>
 
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
+#include <asm/localtimer.h>
 
 #include <mach/msm_iomap.h>
 #include <mach/cpu.h>
+#include <mach/board.h>
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
 #define TIMER_ENABLE            0x0008
-#define TIMER_ENABLE_CLR_ON_MATCH_EN    2
-#define TIMER_ENABLE_EN                 1
+#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
+#define TIMER_ENABLE_EN                 BIT(0)
 #define TIMER_CLEAR             0x000C
 #define DGT_CLK_CTL             0x0034
-enum {
-        DGT_CLK_CTL_DIV_1 = 0,
-        DGT_CLK_CTL_DIV_2 = 1,
-        DGT_CLK_CTL_DIV_3 = 2,
-        DGT_CLK_CTL_DIV_4 = 3,
-};
-#define CSR_PROTECTION          0x0020
-#define CSR_PROTECTION_EN               1
+#define DGT_CLK_CTL_DIV_4       0x3
 
 #define GPT_HZ 32768
 
-enum timer_location {
-        LOCAL_TIMER = 0,
-        GLOBAL_TIMER = 1,
-};
-
-#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
-
-/* TODO: Remove these ifdefs */
-#if defined(CONFIG_ARCH_QSD8X50)
-#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
-#define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30)
-#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
-#define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
-#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
-#define MSM_DGT_SHIFT (0)
-#else
-#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
-#define MSM_DGT_SHIFT (5)
-#endif
+#define MSM_DGT_SHIFT 5
 
-struct msm_clock {
-        struct clock_event_device   clockevent;
-        struct clocksource          clocksource;
-        unsigned int                irq;
-        void __iomem                *regbase;
-        uint32_t                    freq;
-        uint32_t                    shift;
-        void __iomem                *global_counter;
-        void __iomem                *local_counter;
-        union {
-                struct clock_event_device               *evt;
-                struct clock_event_device __percpu      **percpu_evt;
-        };              
-};
-
-enum {
-        MSM_CLOCK_GPT,
-        MSM_CLOCK_DGT,
-        NR_TIMERS,
-};
-
-
-static struct msm_clock msm_clocks[];
+static void __iomem *event_base;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        if (evt->event_handler == NULL)
-                return IRQ_HANDLED;
+        /* Stop the timer tick */
+        if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
+                u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
+                ctrl &= ~TIMER_ENABLE_EN;
+                writel_relaxed(ctrl, event_base + TIMER_ENABLE);
+        }
         evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
-static cycle_t msm_read_timer_count(struct clocksource *cs)
-{
-        struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
-
-        /*
-         * Shift timer count down by a constant due to unreliable lower bits
-         * on some targets.
-         */
-        return readl(clk->global_counter) >> clk->shift;
-}
-
-static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
-{
-#ifdef CONFIG_SMP
-        int i;
-        for (i = 0; i < NR_TIMERS; i++)
-                if (evt == &(msm_clocks[i].clockevent))
-                        return &msm_clocks[i];
-        return &msm_clocks[MSM_GLOBAL_TIMER];
-#else
-        return container_of(evt, struct msm_clock, clockevent);
-#endif
-}
-
 static int msm_timer_set_next_event(unsigned long cycles,
                                     struct clock_event_device *evt)
 {
-        struct msm_clock *clock = clockevent_to_clock(evt);
-        uint32_t now = readl(clock->local_counter);
-        uint32_t alarm = now + (cycles << clock->shift);
+        u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 
-        writel(alarm, clock->regbase + TIMER_MATCH_VAL);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
+        writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
+        writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
         return 0;
 }
 
 static void msm_timer_set_mode(enum clock_event_mode mode,
                               struct clock_event_device *evt)
 {
-        struct msm_clock *clock = clockevent_to_clock(evt);
+        u32 ctrl;
+
+        ctrl = readl_relaxed(event_base + TIMER_ENABLE);
+        ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
 
         switch (mode) {
         case CLOCK_EVT_MODE_RESUME:
         case CLOCK_EVT_MODE_PERIODIC:
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
-                writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
+                /* Timer is enabled in set_next_event */
                 break;
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
-                writel(0, clock->regbase + TIMER_ENABLE);
                 break;
         }
+        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 }
 
-static struct msm_clock msm_clocks[] = {
-        [MSM_CLOCK_GPT] = {
-                .clockevent = {
-                        .name           = "gp_timer",
-                        .features       = CLOCK_EVT_FEAT_ONESHOT,
-                        .shift          = 32,
-                        .rating         = 200,
-                        .set_next_event = msm_timer_set_next_event,
-                        .set_mode       = msm_timer_set_mode,
-                },
-                .clocksource = {
-                        .name           = "gp_timer",
-                        .rating         = 200,
-                        .read           = msm_read_timer_count,
-                        .mask           = CLOCKSOURCE_MASK(32),
-                        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-                },
-                .irq = INT_GP_TIMER_EXP,
-                .freq = GPT_HZ,
-        },
-        [MSM_CLOCK_DGT] = {
-                .clockevent = {
-                        .name           = "dg_timer",
-                        .features       = CLOCK_EVT_FEAT_ONESHOT,
-                        .shift          = 32 + MSM_DGT_SHIFT,
-                        .rating         = 300,
-                        .set_next_event = msm_timer_set_next_event,
-                        .set_mode       = msm_timer_set_mode,
-                },
-                .clocksource = {
-                        .name           = "dg_timer",
-                        .rating         = 300,
-                        .read           = msm_read_timer_count,
-                        .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
-                        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-                },
-                .irq = INT_DEBUG_TIMER_EXP,
-                .freq = DGT_HZ >> MSM_DGT_SHIFT,
-                .shift = MSM_DGT_SHIFT,
-        }
+static struct clock_event_device msm_clockevent = {
+        .name           = "gp_timer",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 200,
+        .set_next_event = msm_timer_set_next_event,
+        .set_mode       = msm_timer_set_mode,
+};
+
+static union {
+        struct clock_event_device *evt;
+        struct clock_event_device __percpu **percpu_evt;
+} msm_evt;
+
+static void __iomem *source_base;
+
+static cycle_t msm_read_timer_count(struct clocksource *cs)
+{
+        return readl_relaxed(source_base + TIMER_COUNT_VAL);
+}
+
+static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
+{
+        /*
+         * Shift timer count down by a constant due to unreliable lower bits
+         * on some targets.
+         */
+        return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
+}
+
+static struct clocksource msm_clocksource = {
+        .name   = "dg_timer",
+        .rating = 300,
+        .read   = msm_read_timer_count,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
 static void __init msm_timer_init(void)
 {
-        int i;
+        struct clock_event_device *ce = &msm_clockevent;
+        struct clocksource *cs = &msm_clocksource;
         int res;
-        int global_offset = 0;
+        u32 dgt_hz;
 
         if (cpu_is_msm7x01()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+                event_base = MSM_CSR_BASE;
+                source_base = MSM_CSR_BASE + 0x10;
+                dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
+                cs->read = msm_read_timer_count_shift;
+                cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
         } else if (cpu_is_msm7x30()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
+                event_base = MSM_CSR_BASE + 0x04;
+                source_base = MSM_CSR_BASE + 0x24;
+                dgt_hz = 24576000 / 4;
         } else if (cpu_is_qsd8x50()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+                event_base = MSM_CSR_BASE;
+                source_base = MSM_CSR_BASE + 0x10;
+                dgt_hz = 19200000 / 4;
         } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
-
-                /* Use CPU0's timer as the global timer. */
-                global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
+                event_base = MSM_TMR_BASE + 0x04;
+                /* Use CPU0's timer as the global clock source. */
+                source_base = MSM_TMR0_BASE + 0x24;
+                dgt_hz = 27000000 / 4;
+                writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
         } else
                 BUG();
 
-#ifdef CONFIG_ARCH_MSM_SCORPIONMP
-        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-#endif
-
-        for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
-                struct msm_clock *clock = &msm_clocks[i];
-                struct clock_event_device *ce = &clock->clockevent;
-                struct clocksource *cs = &clock->clocksource;
-
-                clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
-                clock->global_counter = clock->local_counter + global_offset;
-
-                writel(0, clock->regbase + TIMER_ENABLE);
-                writel(0, clock->regbase + TIMER_CLEAR);
-                writel(~0, clock->regbase + TIMER_MATCH_VAL);
-
-                ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
-                /* allow at least 10 seconds to notice that the timer wrapped */
-                ce->max_delta_ns =
-                        clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
-                /* 4 gets rounded down to 3 */
-                ce->min_delta_ns = clockevent_delta2ns(4, ce);
-                ce->cpumask = cpumask_of(0);
-
-                res = clocksource_register_hz(cs, clock->freq);
-                if (res)
-                        printk(KERN_ERR "msm_timer_init: clocksource_register "
-                               "failed for %s\n", cs->name);
-
-                ce->irq = clock->irq;
-                if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                        clock->percpu_evt = alloc_percpu(struct clock_event_device *);
-                        if (!clock->percpu_evt) {
-                                pr_err("msm_timer_init: memory allocation "
-                                       "failed for %s\n", ce->name);
-                                continue;
-                        }
-
-                        *__this_cpu_ptr(clock->percpu_evt) = ce;
-                        res = request_percpu_irq(ce->irq, msm_timer_interrupt,
-                                                 ce->name, clock->percpu_evt);
-                        if (!res)
-                                enable_percpu_irq(ce->irq, 0);
-                } else {
-                        clock->evt = ce;
-                        res = request_irq(ce->irq, msm_timer_interrupt,
-                                          IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
-                                          ce->name, &clock->evt);
+        writel_relaxed(0, event_base + TIMER_ENABLE);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
+        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
+        ce->cpumask = cpumask_of(0);
+
+        ce->irq = INT_GP_TIMER_EXP;
+        clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
+        if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+                msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
+                if (!msm_evt.percpu_evt) {
+                        pr_err("memory allocation failed for %s\n", ce->name);
+                        goto err;
                 }
-
-                if (res)
-                        pr_err("msm_timer_init: request_irq failed for %s\n",
-                               ce->name);
-
-                clockevents_register_device(ce);
+                *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
+                res = request_percpu_irq(ce->irq, msm_timer_interrupt,
+                                         ce->name, msm_evt.percpu_evt);
+                if (!res)
+                        enable_percpu_irq(ce->irq, 0);
+        } else {
+                msm_evt.evt = ce;
+                res = request_irq(ce->irq, msm_timer_interrupt,
+                                  IRQF_TIMER | IRQF_NOBALANCING |
+                                  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
         }
+
+        if (res)
+                pr_err("request_irq failed for %s\n", ce->name);
+err:
+        writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
+        res = clocksource_register_hz(cs, dgt_hz);
+        if (res)
+                pr_err("clocksource_register failed\n");
 }
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_LOCAL_TIMERS
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-        static bool local_timer_inited;
-        struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
-
         /* Use existing clock_event for cpu 0 */
         if (!smp_processor_id())
                 return 0;
 
-        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-
-        if (!local_timer_inited) {
-                writel(0, clock->regbase  + TIMER_ENABLE);
-                writel(0, clock->regbase + TIMER_CLEAR);
-                writel(~0, clock->regbase + TIMER_MATCH_VAL);
-                local_timer_inited = true;
-        }
-        evt->irq = clock->irq;
+        writel_relaxed(0, event_base + TIMER_ENABLE);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
+        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
+        evt->irq = msm_clockevent.irq;
         evt->name = "local_timer";
-        evt->features = CLOCK_EVT_FEAT_ONESHOT;
-        evt->rating = clock->clockevent.rating;
+        evt->features = msm_clockevent.features;
+        evt->rating = msm_clockevent.rating;
         evt->set_mode = msm_timer_set_mode;
         evt->set_next_event = msm_timer_set_next_event;
-        evt->shift = clock->clockevent.shift;
-        evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
-        evt->max_delta_ns =
-                clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
+        evt->shift = msm_clockevent.shift;
+        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
+        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 
-        *__this_cpu_ptr(clock->percpu_evt) = evt;
-        enable_percpu_irq(evt->irq, 0);
-
+        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
         clockevents_register_device(evt);
+        enable_percpu_irq(evt->irq, 0);
         return 0;
 }
 
@@ -321,8 +223,7 @@ void local_timer_stop(struct clock_event_device *evt)
         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
         disable_percpu_irq(evt->irq);
 }
-
-#endif
+#endif /* CONFIG_LOCAL_TIMERS */
 
 struct sys_timer msm_timer = {
         .init = msm_timer_init
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 311d5b0e9bc..62b53d710ef 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -12,12 +12,12 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
  * Generic Address Decode Windows bit settings
  */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCIE0            4
 #define TARGET_PCIE1            8
@@ -32,23 +32,10 @@
 #define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
 
 /*
- * Helpers to get DDR bank info
- */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
-
-/*
  * CPU Address Decode Windows registers
  */
 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-
-
-struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 
 static void __init __iomem *win_cfg_base(int win)
 {
@@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win)
         return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
 }
 
-static int __init cpu_win_can_remap(int win)
-{
-        if (win < 8)
-                return 1;
-
-        return 0;
-}
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        void __iomem *addr = win_cfg_base(win);
-        u32 ctrl;
-
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-
-        writel(base, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-
-                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 14,
+        .remappable_wins = 8,
+        .win_cfg_base = win_cfg_base,
+};
 
 void __init mv78xx0_setup_cpu_mbus(void)
 {
-        void __iomem *addr;
-        int i;
-        int cs;
-
         /*
-         * First, disable and clear windows.
+         * Disable, clear and configure windows.
          */
-        for (i = 0; i < 14; i++) {
-                addr = win_cfg_base(i);
-
-                writel(0, addr + WIN_BASE_OFF);
-                writel(0, addr + WIN_CTRL_OFF);
-                if (cpu_win_can_remap(i)) {
-                        writel(0, addr + WIN_REMAP_LO_OFF);
-                        writel(0, addr + WIN_REMAP_HI_OFF);
-                }
-        }
+        orion_config_wins(&addr_map_cfg, NULL);
 
         /*
          * Setup MBUS dram target info.
          */
-        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
         if (mv78xx0_core_index() == 0)
-                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            DDR_WINDOW_CPU0_BASE);
         else
-                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
-
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
-
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-
-                        w = &mv78xx0_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        mv78xx0_mbus_dram_info.num_cs = cs;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                       int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
-                      ATTR_PCIE_IO(min), -1);
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
+                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
 }
 
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
                                        int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
-                      ATTR_PCIE_MEM(min), -1);
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
+                            TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
 }
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 5b9632b0116..0cdd41004ad 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/ethtool.h>
 #include <asm/mach/map.h>
@@ -23,6 +22,7 @@
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 static int get_tclk(void);
@@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void)
  ****************************************************************************/
 void __init mv78xx0_ehci0_init(void)
 {
-        orion_ehci_init(&mv78xx0_mbus_dram_info,
-                        USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
+        orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
 }
 
 
@@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void)
  ****************************************************************************/
 void __init mv78xx0_ehci1_init(void)
 {
-        orion_ehci_1_init(&mv78xx0_mbus_dram_info,
-                          USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
+        orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 }
 
 
@@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void)
  ****************************************************************************/
 void __init mv78xx0_ehci2_init(void)
 {
-        orion_ehci_2_init(&mv78xx0_mbus_dram_info,
-                          USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
+        orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 }
 
 
@@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void)
  ****************************************************************************/
 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge00_init(eth_data,
                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
                         IRQ_MV78XX0_GE_ERR, get_tclk());
 }
@@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
  ****************************************************************************/
 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge01_init(eth_data,
                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
                         NO_IRQ, get_tclk());
 }
@@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge10_init(eth_data,
                         GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
                         NO_IRQ, get_tclk());
 }
@@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge11_init(eth_data,
                         GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
                         NO_IRQ, get_tclk());
 }
@@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void)
  ****************************************************************************/
 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
-                        SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
+        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 }
 
 
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 07d5f8f6be7..507c767d49e 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -23,7 +23,6 @@ void mv78xx0_init(void);
 void mv78xx0_init_early(void);
 void mv78xx0_init_irq(void);
 
-extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 void mv78xx0_setup_cpu_mbus(void);
 void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                int maj, int min);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index cf4e494d44b..df50342179e 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -10,7 +10,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <plat/mpp.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index c51af1cac30..12fcb108b0e 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 struct pcie_port {
@@ -153,7 +153,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
          * Generic PCIe unit setup.
          */
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-        orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
+        orion_pcie_setup(pp->base);
 
         sys->resource[0] = &pp->res[0];
         sys->resource[1] = &pp->res[1];
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index df4a508f240..bc17dfea381 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -13,6 +13,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 
 #include <asm/mach/map.h>
 
@@ -21,10 +22,26 @@
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
 
+static struct clk *gpc_dvfs_clk;
+
 static void imx5_idle(void)
 {
-        if (!need_resched())
+        if (!need_resched()) {
+                /* gpc clock is needed for SRPG */
+                if (gpc_dvfs_clk == NULL) {
+                        gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+                        if (IS_ERR(gpc_dvfs_clk))
+                                goto err0;
+                }
+                clk_enable(gpc_dvfs_clk);
                 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+                if (tzic_enable_wake())
+                        goto err1;
+                cpu_do_idle();
+err1:
+                clk_disable(gpc_dvfs_clk);
+        }
+err0:
         local_irq_enable();
 }
 
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 144ebebc4a6..5eebfaad122 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -55,9 +55,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
                         stop_mode = 1;
                 }
                 arm_srpgcr |= MXC_SRPGCR_PCR;
-
-                if (tzic_enable_wake(1) != 0)
-                        return;
                 break;
         case STOP_POWER_ON:
                 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index 0163b6d8377..e12e11231dc 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -545,11 +545,11 @@ int __init mx23_clocks_init(void)
          */
         clk_set_parent(&ssp_clk, &ref_io_clk);
 
-        clk_enable(&cpu_clk);
-        clk_enable(&hbus_clk);
-        clk_enable(&xbus_clk);
-        clk_enable(&emi_clk);
-        clk_enable(&uart_clk);
+        clk_prepare_enable(&cpu_clk);
+        clk_prepare_enable(&hbus_clk);
+        clk_prepare_enable(&xbus_clk);
+        clk_prepare_enable(&emi_clk);
+        clk_prepare_enable(&uart_clk);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index da6e4aad177..5d68e415222 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/jiffies.h>
 #include <linux/clkdev.h>
+#include <linux/spinlock.h>
 
 #include <asm/clkdev.h>
 #include <asm/div64.h>
@@ -29,6 +30,7 @@
 #include <mach/mx28.h>
 #include <mach/common.h>
 #include <mach/clock.h>
+#include <mach/digctl.h>
 
 #include "regs-clkctrl-mx28.h"
 
@@ -43,6 +45,33 @@ static struct clk emi_clk;
 static struct clk saif0_clk;
 static struct clk saif1_clk;
 static struct clk clk32k_clk;
+static DEFINE_SPINLOCK(clkmux_lock);
+
+/*
+ * HW_SAIF_CLKMUX_SEL:
+ *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
+ *              clock pins selected for SAIF1 input clocks.
+ *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
+ *              SAIF0 clock inputs selected for SAIF1 input clocks.
+ *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
+ *              clocks.
+ *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
+ *              clocks.
+ */
+int mxs_saif_clkmux_select(unsigned int clkmux)
+{
+        if (clkmux > 0x3)
+                return -EINVAL;
+
+        spin_lock(&clkmux_lock);
+        __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
+                        DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
+        __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
+                        DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
+        spin_unlock(&clkmux_lock);
+
+        return 0;
+}
 
 static int _raw_clk_enable(struct clk *clk)
 {
@@ -775,16 +804,25 @@ int __init mx28_clocks_init(void)
         clk_set_parent(&ssp0_clk, &ref_io0_clk);
         clk_set_parent(&ssp1_clk, &ref_io0_clk);
 
-        clk_enable(&cpu_clk);
-        clk_enable(&hbus_clk);
-        clk_enable(&xbus_clk);
-        clk_enable(&emi_clk);
-        clk_enable(&uart_clk);
+        clk_prepare_enable(&cpu_clk);
+        clk_prepare_enable(&hbus_clk);
+        clk_prepare_enable(&xbus_clk);
+        clk_prepare_enable(&emi_clk);
+        clk_prepare_enable(&uart_clk);
 
         clk_set_parent(&lcdif_clk, &ref_pix_clk);
         clk_set_parent(&saif0_clk, &pll0_clk);
         clk_set_parent(&saif1_clk, &pll0_clk);
 
+        /*
+         * Set an initial clock rate for the saif internal logic to work
+         * properly. This is important when working in EXTMASTER mode that
+         * uses the other saif's BITCLK&LRCLK but it still needs a basic
+         * clock which should be fast enough for the internal logic.
+         */
+        clk_set_rate(&saif0_clk, 24000000);
+        clk_set_rate(&saif1_clk, 24000000);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
index a7093c88e6a..97a6f4acc6c 100644
--- a/arch/arm/mach-mxs/clock.c
+++ b/arch/arm/mach-mxs/clock.c
@@ -74,10 +74,15 @@ static int __clk_enable(struct clk *clk)
         return 0;
 }
 
-/* This function increments the reference count on the clock and enables the
- * clock if not already enabled. The parent clock tree is recursively enabled
+/*
+ * The clk_enable/clk_disable could be called by drivers in atomic context,
+ * so they should not really hold mutex.  Instead, clk_prepare/clk_unprepare
+ * can hold a mutex, as the pair will only be called in non-atomic context.
+ * Before migrating to common clk framework, we can have __clk_enable and
+ * __clk_disable called in clk_prepare/clk_unprepare with mutex held and
+ * leave clk_enable/clk_disable as the dummy functions.
  */
-int clk_enable(struct clk *clk)
+int clk_prepare(struct clk *clk)
 {
         int ret = 0;
 
@@ -90,13 +95,9 @@ int clk_enable(struct clk *clk)
 
         return ret;
 }
-EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_prepare);
 
-/* This function decrements the reference count on the clock and disables
- * the clock when reference count is 0. The parent clock tree is
- * recursively disabled
- */
-void clk_disable(struct clk *clk)
+void clk_unprepare(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
                 return;
@@ -105,6 +106,18 @@ void clk_disable(struct clk *clk)
         __clk_disable(clk);
         mutex_unlock(&clocks_mutex);
 }
+EXPORT_SYMBOL(clk_unprepare);
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        /* nothing to do */
+}
 EXPORT_SYMBOL(clk_disable);
 
 /* Retrieve the *current* clock rate. If the clock itself
@@ -166,7 +179,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
                 return ret;
 
         if (clk->usecount)
-                clk_enable(parent);
+                clk_prepare_enable(parent);
 
         mutex_lock(&clocks_mutex);
         ret = clk->set_parent(clk, parent);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index c8887103f0e..4f50094e293 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -47,6 +47,7 @@ struct platform_device *__init mx28_add_mxsfb(
                 const struct mxsfb_platform_data *pdata);
 
 extern const struct mxs_saif_data mx28_saif_data[] __initconst;
-#define mx28_add_saif(id)              mxs_add_saif(&mx28_saif_data[id])
+#define mx28_add_saif(id, pdata) \
+        mxs_add_saif(&mx28_saif_data[id], pdata)
 
 struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
index 1ec965e9fe9..f6e3a60b420 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
@@ -32,7 +32,8 @@ const struct mxs_saif_data mx28_saif_data[] __initconst = {
 };
 #endif
 
-struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data)
+struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data,
+                                const struct mxs_saif_platform_data *pdata)
 {
         struct resource res[] = {
                 {
@@ -56,5 +57,5 @@ struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data)
         };
 
         return mxs_add_platform_device("mxs-saif", data->id, res,
-                                        ARRAY_SIZE(res), NULL, 0);
+                                ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 1388485414c..e1237ab2586 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -17,6 +17,7 @@ extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
 extern void mxs_timer_init(struct clk *, int);
 extern void mxs_restart(char, const char *);
+extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
 extern int mx23_register_gpios(void);
 extern int mx23_clocks_init(void);
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index a8080f44c03..dc369c1239f 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -94,6 +94,7 @@ struct platform_device *__init mxs_add_mxs_pwm(
                 resource_size_t iobase, int id);
 
 /* saif */
+#include <sound/saif.h>
 struct mxs_saif_data {
         int id;
         resource_size_t iobase;
@@ -103,4 +104,5 @@ struct mxs_saif_data {
 };
 
 struct platform_device *__init mxs_add_saif(
-                const struct mxs_saif_data *data);
+                const struct mxs_saif_data *data,
+                const struct mxs_saif_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
new file mode 100644
index 00000000000..49a888c65d6
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/digctl.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_DIGCTL_H__
+#define __MACH_DIGCTL_H__
+
+/* MXS DIGCTL SAIF CLKMUX */
+#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
+#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
+
+#define HW_DIGCTL_CTRL                  0x0
+#define  BP_DIGCTL_CTRL_SAIF_CLKMUX     10
+#define  BM_DIGCTL_CTRL_SAIF_CLKMUX     (0x3 << 10)
+#endif
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index d0cc37fd23a..fdb0a5664dd 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -27,6 +27,7 @@
 
 #include <mach/common.h>
 #include <mach/iomux-mx28.h>
+#include <mach/digctl.h>
 
 #include "devices-mx28.h"
 
@@ -228,7 +229,7 @@ static void __init mx28evk_fec_reset(void)
         /* Enable fec phy clock */
         clk = clk_get_sys("pll2", NULL);
         if (!IS_ERR(clk))
-                clk_enable(clk);
+                clk_prepare_enable(clk);
 
         /* Power up fec phy */
         ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
@@ -421,6 +422,18 @@ static struct gpio mx28evk_lcd_gpios[] = {
         { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
 };
 
+static const struct mxs_saif_platform_data
+                        mx28evk_mxs_saif_pdata[] __initconst = {
+        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
+        {
+                .master_mode = 1,
+                .master_id = 0,
+        }, {
+                .master_mode = 0,
+                .master_id = 0,
+        },
+};
+
 static void __init mx28evk_init(void)
 {
         int ret;
@@ -454,8 +467,9 @@ static void __init mx28evk_init(void)
         else
                 mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 
-        mx28_add_saif(0);
-        mx28_add_saif(1);
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
+        mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
+        mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]);
 
         mx28_add_mxs_i2c(0);
         i2c_register_board_info(0, mxs_i2c0_board_info,
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index b936633b768..54f91ad1c96 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -66,7 +66,7 @@ static int __init mxs_arch_reset_init(void)
 
         clk = clk_get_sys("rtc", NULL);
         if (!IS_ERR(clk))
-                clk_enable(clk);
+                clk_prepare_enable(clk);
 
         return 0;
 }
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index cace0d2e5a5..564a63279f1 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -245,7 +245,7 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
 
 void __init mxs_timer_init(struct clk *timer_clk, int irq)
 {
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
 
         /*
          * Initialize timers to a known state
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 73f287d6429..4f8d66f044e 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC
           custom OMAP boards. Say Y here if you have a custom
           board.
 
-comment "OMAP CPU Speed"
-        depends on ARCH_OMAP1
-
-config OMAP_ARM_216MHZ
-        bool "OMAP ARM 216 MHz CPU (1710 only)"
-        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        help
-          Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
-
-config OMAP_ARM_195MHZ
-        bool "OMAP ARM 195 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 195MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_192MHZ
-        bool "OMAP ARM 192 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        help
-          Enable 192MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_182MHZ
-        bool "OMAP ARM 182 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 182MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_168MHZ
-        bool "OMAP ARM 168 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 168MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_150MHZ
-        bool "OMAP ARM 150 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP15XX
-        help
-          Enable 150MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_120MHZ
-        bool "OMAP ARM 120 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 120MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_96MHZ
-        bool "OMAP ARM 96 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 96MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_60MHZ
-        bool "OMAP ARM 60 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        default y
-        help
-          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
-
-config OMAP_ARM_30MHZ
-        bool "OMAP ARM 30 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 30MHz clock for OMAP CPU. If unsure, say N.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 84ef70476b5..0c50df05d13 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         ref_rate = ck_ref_p->rate;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ref_rate)
+                if (!(ptr->flags & cpu_mask))
                         continue;
 
-                /* DPLL1 cannot be reprogrammed without risking system crash */
-                if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 /* Can check only after xtal frequency check */
@@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         /*
          * In most cases we should not need to reprogram DPLL.
          * Reprogramming the DPLL is tricky, it must be done from SRAM.
-         * (on 730, bit 13 must always be 1)
          */
-        if (cpu_is_omap7xx())
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
-        else
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
+        omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 
         /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
         ck_dpll1_p->rate = ptr->pll_rate;
@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
         highest_rate = -EINVAL;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+
                 if (ptr->xtal != ref_rate)
                         continue;
 
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 16b1423b454..3d04f4f6767 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy;
 extern const struct clkops clkops_uart_16xx;
 extern const struct clkops clkops_generic;
 
+/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
+extern u32 cpu_mask;
+
 #endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 9ff90a744a2..94699a82a73 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,6 +25,7 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
+#include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <plat/usb.h>   /* for OTG_BASE */
 
 #include "clock.h"
@@ -778,12 +779,14 @@ static void __init omap1_show_rates(void)
                 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
 
+u32 cpu_mask;
+
 int __init omap1_clk_init(void)
 {
         struct omap_clk *c;
         const struct omap_clock_config *info;
         int crystal_type = 0; /* Default 12 MHz */
-        u32 reg, cpu_mask;
+        u32 reg;
 
 #ifdef CONFIG_DEBUG_LL
         /*
@@ -808,6 +811,8 @@ int __init omap1_clk_init(void)
                 clk_preinit(c->lk.clk);
 
         cpu_mask = 0;
+        if (cpu_is_omap1710())
+                cpu_mask |= CK_1710;
         if (cpu_is_omap16xx())
                 cpu_mask |= CK_16XX;
         if (cpu_is_omap1510())
@@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void)
 {
         unsigned long rate = ck_dpll1.rate;
 
-        if (rate >= OMAP1_DPLL1_SANE_VALUE)
-                return;
-
-        /* System booting at unusable rate, force reprogramming of DPLL1 */
-        ck_dpll1_p->rate = 0;
-
         /* Find the highest supported frequency and enable it */
         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
                 pr_err("System frequencies not set, using default. Check your config.\n");
-                omap_writew(0x2290, DPLL_CTL);
-                omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
+                /*
+                 * Reprogramming the DPLL is tricky, it must be done from SRAM.
+                 */
+                omap_sram_reprogram_clock(0x2290, 0x0005);
                 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
         }
         propagate_rate(&ck_dpll1);
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
index 07074d79adc..79a683864a5 100644
--- a/arch/arm/mach-omap1/opp.h
+++ b/arch/arm/mach-omap1/opp.h
@@ -21,6 +21,7 @@ struct mpu_rate {
         unsigned long           pll_rate;
         __u16                   ckctl_val;
         __u16                   dpllctl_val;
+        u32                     flags;
 };
 
 extern struct mpu_rate omap1_rate_table[];
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 75a54651499..9cd4ddb5139 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -10,6 +10,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <plat/clkdev_omap.h>
 #include "opp.h"
 
 /*-------------------------------------------------------------------------
@@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = {
          * NOTE: Comment order here is different from bits in CKCTL value:
          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
          */
-#if defined(CONFIG_OMAP_ARM_216MHZ)
-        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_195MHZ)
-        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_192MHZ)
-        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
-        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
-        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
-        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
-        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_182MHZ)
-        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_168MHZ)
-        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_150MHZ)
-        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_120MHZ)
-        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
-        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_60MHZ)
-        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
-        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
+        { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
+                        CK_1710 },
+        { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
+                        CK_7XX },
+        { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
+                        CK_16XX },
+        { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
+                        CK_16XX },
+        {  96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
+                        CK_16XX },
+        {  48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
+                        CK_16XX },
+        {  24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
+                        CK_16XX },
+        { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
+                        CK_7XX },
+        { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
+                        CK_16XX|CK_7XX },
+        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
+                        CK_1510 },
+        { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
+        {  96000000, 12000000,  96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
+        {  60000000, 12000000,  60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
+        {  30000000, 12000000,  60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
         { 0, 0, 0, 0, 0 },
 };
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4f01533083c..904bd1dfcd2 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -78,8 +78,13 @@ config SOC_OMAP3430
         default y
         select ARCH_OMAP_OTG
 
-config SOC_OMAPTI816X
-        bool "TI816X support"
+config SOC_OMAPTI81XX
+        bool "TI81XX support"
+        depends on ARCH_OMAP3
+        default y
+
+config SOC_OMAPAM33XX
+        bool "AM33XX support"
         depends on ARCH_OMAP3
         default y
 
@@ -316,7 +321,12 @@ config MACH_OMAP_3630SDP
 
 config MACH_TI8168EVM
         bool "TI8168 Evaluation Module"
-        depends on SOC_OMAPTI816X
+        depends on SOC_OMAPTI81XX
+        default y
+
+config MACH_TI8148EVM
+        bool "TI8148 Evaluation Module"
+        depends on SOC_OMAPTI81XX
         default y
 
 config MACH_OMAP_4430SDP
@@ -355,6 +365,27 @@ config OMAP3_SDRC_AC_TIMING
           wish to say no.  Selecting yes without understanding what is
           going on could result in system crashes;
 
+config OMAP4_ERRATA_I688
+        bool "OMAP4 errata: Async Bridge Corruption"
+        depends on ARCH_OMAP4
+        select ARCH_HAS_BARRIERS
+        help
+          If a data is stalled inside asynchronous bridge because of back
+          pressure, it may be accepted multiple times, creating pointer
+          misalignment that will corrupt next transfers on that data path
+          until next reset of the system (No recovery procedure once the
+          issue is hit, the path remains consistently broken). Async bridge
+          can be found on path between MPU to EMIF and MPU to L3 interconnect.
+          This situation can happen only when the idle is initiated by a
+          Master Request Disconnection (which is trigged by software when
+          executing WFI on CPU).
+          The work-around for this errata needs all the initiators connected
+          through async bridge must ensure that data path is properly drained
+          before issuing WFI. This condition will be met if one Strongly ordered
+          access is performed to the target right before executing the WFI.
+          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+          IO barrier ensure that there is no synchronisation loss on initiators
+          operating on both interconnect port simultaneously.
 endmenu
 
 endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b009f17dee5..fc9b238cbc1 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,10 +11,11 @@ hwmod-common				= omap_hwmod.o \
                                           omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
                                           clkt_dpll.o clkt_clksel.o
+secure-common                          = omap-smc.o omap-secure.o
 
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -24,11 +25,13 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap44xx-smc.o omap4-common.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o \
+                                           sleep44xx.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
-AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap-smc.o                       :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep44xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
 
 # Functions loaded to SRAM
 obj-$(CONFIG_SOC_OMAP2420)              += sram242x.o
@@ -62,7 +65,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o \
                                            cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o \
+                                           cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
@@ -77,6 +81,7 @@ endif
 endif
 
 # PRCM
+obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
                                            vc3xxx_data.o vp3xxx_data.o
@@ -86,7 +91,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
 obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cm2xxx_3xxx.o cminst44xx.o \
                                            cm44xx.o prcm_mpu44xx.o \
                                            prminst44xx.o vc44xx_data.o \
-                                           vp44xx_data.o
+                                           vp44xx_data.o prm44xx.o
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -232,6 +237,7 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
+obj-$(CONFIG_MACH_TI8148EVM)            += board-ti8168evm.o
 
 # Platform specific device init code
 
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 9996334cb68..383717ba63b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-
-static struct omap_device_pad serial1_pads[] __initdata = {
-        /*
-         * Note that off output enable is an active low
-         * signal. So setting this means pin is a
-         * input enabled in off mode
-         */
-        OMAP_MUX_STATIC("uart1_cts.uart1_cts",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_rts.uart1_rts",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_rx.uart1_rx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_tx.uart1_tx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLDOWN |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-
-static struct omap_board_data serial1_data __initdata = {
-        .id             = 0,
-        .pads           = serial1_pads,
-        .pads_cnt       = ARRAY_SIZE(serial1_pads),
-};
-
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-
-static inline void board_serial_init(void)
-{
-        omap_serial_init_port(&serial1_data);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-}
 #else
 #define board_mux       NULL
-
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 
 /*
@@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void)
         else
                 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
         omap_ads7846_init(1, gpio_pendown, 310, NULL);
-        board_serial_init();
+        omap_serial_init();
         omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
         usb_musb_init(NULL);
         board_smc91x_init();
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index bad5d5a5ef7..2ceb75d21eb 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -372,11 +372,17 @@ static struct platform_device sdp4430_vbat = {
         },
 };
 
+static struct platform_device sdp4430_dmic_codec = {
+        .name   = "dmic-codec",
+        .id     = -1,
+};
+
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
         &sdp4430_leds_pwm,
         &sdp4430_vbat,
+        &sdp4430_dmic_codec,
 };
 
 static struct omap_musb_board_data musb_board_data = {
@@ -404,6 +410,7 @@ static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 5,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .pm_caps        = MMC_PM_KEEP_POWER,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .ocr_mask       = MMC_VDD_165_195,
@@ -837,74 +844,8 @@ static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial4_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-
-static struct omap_board_data serial4_data __initdata = {
-        .id             = 3,
-        .pads           = serial4_pads,
-        .pads_cnt       = ARRAY_SIZE(serial4_pads),
-};
-
-static inline void board_serial_init(void)
-{
-        struct omap_board_data bdata;
-        bdata.flags     = 0;
-        bdata.pads      = NULL;
-        bdata.pads_cnt  = 0;
-        bdata.id        = 0;
-        /* pass dummy data for UART1 */
-        omap_serial_init_port(&bdata);
-
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-        omap_serial_init_port(&serial4_data);
-}
 #else
 #define board_mux       NULL
-
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
  #endif
 
 static void omap4_sdp4430_wifi_mux_init(void)
@@ -954,7 +895,7 @@ static void __init omap_4430sdp_init(void)
         omap4_i2c_init();
         omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-        board_serial_init();
+        omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         omap4_sdp4430_wifi_init();
         omap4_twl6030_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index f5a3a3f1173..4b1cfe32e6b 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -24,6 +24,7 @@
 #include <linux/i2c/pca953x.h>
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <mach/am35xx.h>
@@ -40,6 +41,7 @@
 
 #include "mux.h"
 #include "control.h"
+#include "hsmmc.h"
 
 #define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
 
@@ -455,6 +457,23 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
 static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
 };
 
+static struct omap2_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = 127,
+                .gpio_wp        = 126,
+        },
+        {
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = 128,
+                .gpio_wp        = 129,
+        },
+        {}      /* Terminator */
+};
+
+
 static void __init am3517_evm_init(void)
 {
         omap_board_config = am3517_evm_config;
@@ -483,6 +502,9 @@ static void __init am3517_evm_init(void)
 
         /* MUSB */
         am3517_evm_musb_init();
+
+        /* MMC init function */
+        omap2_hsmmc_init(mmc);
 }
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 1545102d1f9..e921e3be24a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -53,7 +53,8 @@
 #include "hsmmc.h"
 #include "common-board-devices.h"
 
-#define CM_T35_GPIO_PENDOWN     57
+#define CM_T35_GPIO_PENDOWN             57
+#define SB_T35_USB_HUB_RESET_GPIO       167
 
 #define CM_T35_SMSC911X_CS      5
 #define CM_T35_SMSC911X_GPIO    163
@@ -339,8 +340,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
         REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
-        REGULATOR_SUPPLY("vdvi", "omapdss"),
+static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -373,6 +376,19 @@ static struct regulator_init_data cm_t35_vsim = {
         .consumer_supplies      = cm_t35_vsim_supply,
 };
 
+static struct regulator_init_data cm_t35_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(cm_t35_vio_supplies),
+        .consumer_supplies      = cm_t35_vio_supplies,
+};
+
 static uint32_t cm_t35_keymap[] = {
         KEY(0, 0, KEY_A),       KEY(0, 1, KEY_B),       KEY(0, 2, KEY_LEFT),
         KEY(1, 0, KEY_UP),      KEY(1, 1, KEY_ENTER),   KEY(1, 2, KEY_DOWN),
@@ -421,6 +437,23 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+static void cm_t35_init_usbh(void)
+{
+        int err;
+
+        err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
+                               GPIOF_OUT_INIT_LOW, "usb hub rst");
+        if (err) {
+                pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
+        } else {
+                udelay(10);
+                gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
+                msleep(1);
+        }
+
+        usbhs_init(&usbhs_bdata);
+}
+
 static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
                                  unsigned ngpio)
 {
@@ -456,17 +489,14 @@ static struct twl4030_platform_data cm_t35_twldata = {
         .gpio           = &cm_t35_gpio_data,
         .vmmc1          = &cm_t35_vmmc1,
         .vsim           = &cm_t35_vsim,
+        .vio            = &cm_t35_vio,
 };
 
 static void __init cm_t35_init_i2c(void)
 {
         omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-
-        cm_t35_twldata.vpll2->constraints.name = "VDVI";
-        cm_t35_twldata.vpll2->num_consumer_supplies =
-                                                ARRAY_SIZE(cm_t35_vdvi_supply);
-        cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
+                              TWL_COMMON_REGULATOR_VDAC |
+                              TWL_COMMON_PDATA_AUDIO);
 
         omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
@@ -570,24 +600,28 @@ static void __init cm_t3x_common_dss_mux_init(int mux_mode)
 
 static void __init cm_t35_init_mux(void)
 {
-        omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
+
+        omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
+        omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
+        omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
+        omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
+        omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
+        omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
+        cm_t3x_common_dss_mux_init(mux_mode);
 }
 
 static void __init cm_t3730_init_mux(void)
 {
-        omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
+
+        omap_mux_init_signal("sys_boot0", mux_mode);
+        omap_mux_init_signal("sys_boot1", mux_mode);
+        omap_mux_init_signal("sys_boot3", mux_mode);
+        omap_mux_init_signal("sys_boot4", mux_mode);
+        omap_mux_init_signal("sys_boot5", mux_mode);
+        omap_mux_init_signal("sys_boot6", mux_mode);
+        cm_t3x_common_dss_mux_init(mux_mode);
 }
 #else
 static inline void cm_t35_init_mux(void) {}
@@ -612,7 +646,7 @@ static void __init cm_t3x_common_init(void)
         cm_t35_init_display();
 
         usb_musb_init(NULL);
-        usbhs_init(&usbhs_bdata);
+        cm_t35_init_usbh();
 }
 
 static void __init cm_t35_init(void)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index f8c5b2cc7c9..d5875606048 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -69,7 +69,6 @@ static void __init omap_generic_init(void)
         if (node)
                 irq_domain_add_simple(node, 0);
 
-        omap_serial_init();
         omap_sdrc_init(NULL, NULL);
 
         of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index cef2cf1c0b8..42a4d11fad2 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -46,7 +46,7 @@ static struct device *mmc_device;
 #define TUSB6010_GPIO_ENABLE    0
 #define TUSB6010_DMACHAN        0x3f
 
-#ifdef CONFIG_USB_MUSB_TUSB6010
+#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 /*
  * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
  * 1.5 V voltage regulators of PM companion chip. Companion chip will then
@@ -644,15 +644,15 @@ static inline void board_serial_init(void)
         bdata.pads_cnt = 0;
 
         bdata.id = 0;
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
 
         bdata.id = 1;
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
 
         bdata.id = 2;
         bdata.pads = serial2_pads;
         bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
 }
 
 #else
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 8b06c6a60d0..e96a2e7ad36 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -364,74 +364,8 @@ static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial4_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-
-static struct omap_board_data serial4_data __initdata = {
-        .id             = 3,
-        .pads           = serial4_pads,
-        .pads_cnt       = ARRAY_SIZE(serial4_pads),
-};
-
-static inline void board_serial_init(void)
-{
-        struct omap_board_data bdata;
-        bdata.flags     = 0;
-        bdata.pads      = NULL;
-        bdata.pads_cnt  = 0;
-        bdata.id        = 0;
-        /* pass dummy data for UART1 */
-        omap_serial_init_port(&bdata);
-
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-        omap_serial_init_port(&serial4_data);
-}
 #else
 #define board_mux       NULL
-
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 
 /* Display DVI */
@@ -562,7 +496,7 @@ static void __init omap4_panda_init(void)
         omap4_panda_i2c_init();
         platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
         platform_device_register(&omap_vwlan_device);
-        board_serial_init();
+        omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         omap4_twl6030_hsmmc_init(mmc);
         omap4_ehci_init();
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 108fee6146f..d67bcdf724d 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -15,6 +15,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/wl12xx.h>
+#include <linux/spi/tsc2005.h>
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/clk.h>
@@ -58,6 +59,9 @@
 
 #define RX51_USB_TRANSCEIVER_RST_GPIO   67
 
+#define RX51_TSC2005_RESET_GPIO         104
+#define RX51_TSC2005_IRQ_GPIO           100
+
 /* list all spi devices here */
 enum {
         RX51_SPI_WL1251,
@@ -66,6 +70,7 @@ enum {
 };
 
 static struct wl12xx_platform_data wl1251_pdata;
+static struct tsc2005_platform_data tsc2005_pdata;
 
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
 static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
@@ -167,10 +172,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
                 .modalias               = "tsc2005",
                 .bus_num                = 1,
                 .chip_select            = 0,
-                /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/
+                .irq                    = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
                 .max_speed_hz           = 6000000,
                 .controller_data        = &tsc2005_mcspi_config,
-                /* .platform_data = &tsc2005_config,*/
+                .platform_data          = &tsc2005_pdata,
         },
 };
 
@@ -1086,6 +1091,42 @@ error:
          */
 }
 
+static struct tsc2005_platform_data tsc2005_pdata = {
+        .ts_pressure_max        = 2048,
+        .ts_pressure_fudge      = 2,
+        .ts_x_max               = 4096,
+        .ts_x_fudge             = 4,
+        .ts_y_max               = 4096,
+        .ts_y_fudge             = 7,
+        .ts_x_plate_ohm         = 280,
+        .esd_timeout_ms         = 8000,
+};
+
+static void rx51_tsc2005_set_reset(bool enable)
+{
+        gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
+}
+
+static void __init rx51_init_tsc2005(void)
+{
+        int r;
+
+        r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
+        if (r < 0) {
+                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
+                rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
+        }
+
+        r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
+                "tsc2005 reset");
+        if (r >= 0) {
+                tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+        } else {
+                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
+                tsc2005_pdata.esd_timeout_ms = 0;
+        }
+}
+
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
@@ -1094,6 +1135,7 @@ void __init rx51_peripherals_init(void)
         board_smc91x_init();
         rx51_add_gpio_keys();
         rx51_init_wl1251();
+        rx51_init_tsc2005();
         rx51_init_si4713();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 74713e3993e..ab9a7a9e9d6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -1,5 +1,5 @@
 /*
- * Code for TI8168 EVM.
+ * Code for TI8168/TI8148 EVM.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
  *
@@ -23,30 +23,45 @@
 #include <plat/irqs.h>
 #include <plat/board.h>
 #include "common.h"
+#include <plat/usb.h>
 
-static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+static struct omap_musb_board_data musb_board_data = {
+        .set_phy_power  = ti81xx_musb_phy_power,
+        .interface_type = MUSB_INTERFACE_ULPI,
+        .mode           = MUSB_OTG,
+        .power          = 500,
 };
 
-static void __init ti8168_evm_init(void)
+static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
+};
+
+static void __init ti81xx_evm_init(void)
 {
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
-        omap_board_config = ti8168_evm_config;
-        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
-}
-
-static void __init ti8168_evm_map_io(void)
-{
-        omapti816x_map_common_io();
+        omap_board_config = ti81xx_evm_config;
+        omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
+        usb_musb_init(&musb_board_data);
 }
 
 MACHINE_START(TI8168EVM, "ti8168evm")
         /* Maintainer: Texas Instruments */
         .atag_offset    = 0x100,
-        .map_io         = ti8168_evm_map_io,
-        .init_early     = ti816x_init_early,
-        .init_irq       = ti816x_init_irq,
+        .map_io         = ti81xx_map_io,
+        .init_early     = ti81xx_init_early,
+        .init_irq       = ti81xx_init_irq,
+        .timer          = &omap3_timer,
+        .init_machine   = ti81xx_evm_init,
+        .restart        = omap_prcm_restart,
+MACHINE_END
+
+MACHINE_START(TI8148EVM, "ti8148evm")
+        /* Maintainer: Texas Instruments */
+        .atag_offset    = 0x100,
+        .map_io         = ti81xx_map_io,
+        .init_early     = ti81xx_init_early,
+        .init_irq       = ti81xx_init_irq,
         .timer          = &omap3_timer,
-        .init_machine   = ti8168_evm_init,
+        .init_machine   = ti81xx_evm_init,
         .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f8d69..f57ed5baecc 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-u8 cpu_mask;
+u16 cpu_mask;
 
 /*
  * clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2311bc21722..b8c2a686481 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                                const char *core_ck_name,
                                const char *mpu_ck_name);
 
-extern u8 cpu_mask;
+extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 5d0064a4fb5..d75e5f6b8a0 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2480,6 +2480,16 @@ static struct clk uart4_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_fck_am35xx = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt2_fck = {
         .name           = "gpt2_fck",
         .ops            = &clkops_omap2_dflt_wait,
@@ -3287,7 +3297,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
@@ -3323,7 +3333,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
@@ -3369,20 +3379,18 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
@@ -3403,6 +3411,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3517,6 +3526,10 @@ int __init omap3xxx_clk_init(void)
         } else if (cpu_is_ti816x()) {
                 cpu_mask = RATE_IN_TI816X;
                 cpu_clkflg = CK_TI816X;
+        } else if (cpu_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+        } else if (cpu_is_ti814x()) {
+                cpu_mask = RATE_IN_TI814X;
         } else if (cpu_is_omap34xx()) {
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
                         cpu_mask = RATE_IN_3430ES1;
@@ -3600,7 +3613,7 @@ int __init omap3xxx_clk_init(void)
          * Lock DPLL5 -- here only until other device init code can
          * handle this
          */
-        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
                 omap3_clk_lock_dpll5();
 
         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 0798a802497..08e86d793a1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = {
         { .parent = NULL },
 };
 
+static struct clk mpu_periphclk = {
+        .name           = "mpu_periphclk",
+        .parent         = &dpll_mpu_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
 static struct clk ocp_abe_iclk = {
         .name           = "ocp_abe_iclk",
         .parent         = &aess_fclk,
@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
+        CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
@@ -3295,7 +3304,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
@@ -3306,7 +3315,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
+        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
@@ -3314,7 +3323,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
@@ -3374,8 +3383,8 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
-        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
-        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
         CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 684b8a7cd40..aaf421178c9 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -110,23 +110,49 @@ void __init omap3_map_io(void)
 
 /*
  * Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
  */
-#define TI816X_TAP_BASE         (TI816X_CTRL_BASE + \
-                                TI816X_CONTROL_DEVICE_ID - 0x204)
+#define TI81XX_TAP_BASE         (TI81XX_CTRL_BASE + \
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
 
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
         .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
 };
 
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
 {
-        __omap2_set_globals(&ti816x_globals);
+        __omap2_set_globals(&ti81xx_globals);
+}
+
+void __init ti81xx_map_io(void)
+{
+        omapti81xx_map_common_io();
+}
+
+#define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + \
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+        .class  = AM335X_CLASS,
+        .tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+        .ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        .prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+        .cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+        __omap2_set_globals(&am33xx_globals);
+}
+
+void __init am33xx_map_io(void)
+{
+        omapam33xx_map_common_io();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index cda888a2e63..febffde2ff1 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -24,9 +24,11 @@
 
 #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#ifndef __ASSEMBLER__
 
 #include <linux/delay.h>
 #include <plat/common.h>
+#include <asm/proc-fns.h>
 
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
@@ -52,10 +54,18 @@ static inline void omap34xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI816X
-extern void omapti816x_map_common_io(void);
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
 #else
-static inline void omapti816x_map_common_io(void)
+static inline void omapti81xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
 {
 }
 #endif
@@ -82,7 +92,7 @@ void omap35xx_init_early(void);
 void omap3630_init_early(void);
 void omap3_init_early(void);    /* Do not use this one */
 void am35xx_init_early(void);
-void ti816x_init_early(void);
+void ti81xx_init_early(void);
 void omap4430_init_early(void);
 void omap_prcm_restart(char, const char *);
 
@@ -107,7 +117,8 @@ void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
-void omap2_set_globals_ti816x(void);
+void omap2_set_globals_ti81xx(void);
+void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
@@ -118,7 +129,9 @@ void omap2_set_globals_prcm(struct omap_globals *);
 void omap242x_map_io(void);
 void omap243x_map_io(void);
 void omap3_map_io(void);
+void am33xx_map_io(void);
 void omap4_map_io(void);
+void ti81xx_map_io(void);
 
 /**
  * omap_test_timeout - busy-loop, testing a condition
@@ -147,7 +160,7 @@ extern struct device *omap4_get_dsp_device(void);
 
 void omap2_init_irq(void);
 void omap3_init_irq(void);
-void ti816x_init_irq(void);
+void ti81xx_init_irq(void);
 extern int omap_irq_pending(void);
 void omap_intc_save_context(void);
 void omap_intc_restore_context(void);
@@ -157,23 +170,23 @@ void omap3_intc_resume_idle(void);
 void omap2_intc_handle_irq(struct pt_regs *regs);
 void omap3_intc_handle_irq(struct pt_regs *regs);
 
-/*
- * wfi used in low power code. Directly opcode is used instead
- * of instruction to avoid mulit-omap build break
- */
-#ifdef CONFIG_THUMB2_KERNEL
-#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
-#else
-#define do_wfi()                        \
-                __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
+#ifdef CONFIG_CACHE_L2X0
+extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 
-#ifdef CONFIG_CACHE_L2X0
-extern void __iomem *l2cache_base;
+#ifdef CONFIG_SMP
+extern void __iomem *omap4_get_scu_base(void);
+#else
+static inline void __iomem *omap4_get_scu_base(void)
+{
+        return NULL;
+}
 #endif
 
 extern void __init gic_init_irq(void);
 extern void omap_smc1(u32 fn, u32 arg);
+extern void __iomem *omap4_get_sar_ram_base(void);
+extern void omap_do_wfi(void);
 
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
@@ -183,4 +196,44 @@ extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
 #endif
 
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+extern int omap4_mpuss_init(void);
+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern int omap4_finish_suspend(unsigned long cpu_state);
+extern void omap4_cpu_resume(void);
+extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+extern u32 omap4_mpuss_read_prev_context_state(void);
+#else
+static inline int omap4_enter_lowpower(unsigned int cpu,
+                                        unsigned int power_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+
+static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+
+static inline int omap4_mpuss_init(void)
+{
+        return 0;
+}
+
+static inline int omap4_finish_suspend(unsigned long cpu_state)
+{
+        return 0;
+}
+
+static inline void omap4_cpu_resume(void)
+{}
+
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+        return 0;
+}
+#endif
+#endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d5a38..0ba68d3764b 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
 
-/* TI816X spefic control submodules */
-#define TI816X_CONTROL_DEVCONF          0x600
+/* TI81XX spefic control submodules */
+#define TI81XX_CONTROL_DEVCONF          0x600
 
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
 
@@ -244,8 +244,8 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
-/* TI816X CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID        (TI816X_CONTROL_DEVCONF + 0x000)
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index e20332f4abd..464cffde58f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -25,12 +25,12 @@
 #include <linux/sched.h>
 #include <linux/cpuidle.h>
 #include <linux/export.h>
+#include <linux/cpu_pm.h>
 
 #include <plat/prcm.h>
 #include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/serial.h>
 
 #include "pm.h"
 #include "control.h"
@@ -124,9 +124,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
         }
 
+        /*
+         * Call idle CPU PM enter notifier chain so that
+         * VFP context is saved.
+         */
+        if (mpu_state == PWRDM_POWER_OFF)
+                cpu_pm_enter();
+
         /* Execute ARM wfi */
         omap_sram_idle();
 
+        /*
+         * Call idle CPU PM enter notifier chain to restore
+         * VFP context.
+         */
+        if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+                cpu_pm_exit();
+
         /* Re-allow idle for C1 */
         if (index == 0) {
                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
@@ -245,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
         struct omap3_idle_statedata *cx;
         int ret;
 
-        if (!omap3_can_sleep()) {
-                new_state_idx = drv->safe_state_index;
-                goto select_state;
-        }
-
         /*
          * Prevent idle completely if CAM is active.
          * CAM does not have wakeup capability in OMAP3.
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
new file mode 100644
index 00000000000..cfdbb86bc84
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -0,0 +1,245 @@
+/*
+ * OMAP4 CPU idle Routines
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/sched.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/export.h>
+#include <linux/clockchips.h>
+
+#include <asm/proc-fns.h>
+
+#include "common.h"
+#include "pm.h"
+#include "prm.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+/* Machine specific information to be recorded in the C-state driver_data */
+struct omap4_idle_statedata {
+        u32 cpu_state;
+        u32 mpu_logic_state;
+        u32 mpu_state;
+        u8 valid;
+};
+
+static struct cpuidle_params cpuidle_params_table[] = {
+        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
+        /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
+        {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
+        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+};
+
+#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
+
+struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
+static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+
+/**
+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * @dev: cpuidle device
+ * @drv: cpuidle driver
+ * @index: the index of state to be entered
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified low power state selected by the governor.
+ * Returns the amount of time spent in the low power state.
+ */
+static int omap4_enter_idle(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        struct omap4_idle_statedata *cx =
+                        cpuidle_get_statedata(&dev->states_usage[index]);
+        struct timespec ts_preidle, ts_postidle, ts_idle;
+        u32 cpu1_state;
+        int idle_time;
+        int new_state_idx;
+        int cpu_id = smp_processor_id();
+
+        /* Used to keep track of the total time in idle */
+        getnstimeofday(&ts_preidle);
+
+        local_irq_disable();
+        local_fiq_disable();
+
+        /*
+         * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+         * This is necessary to honour hardware recommondation
+         * of triggeing all the possible low power modes once CPU1 is
+         * out of coherency and in OFF mode.
+         * Update dev->last_state so that governor stats reflects right
+         * data.
+         */
+        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
+        if (cpu1_state != PWRDM_POWER_OFF) {
+                new_state_idx = drv->safe_state_index;
+                cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
+        }
+
+        if (index > 0)
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+
+        /*
+         * Call idle CPU PM enter notifier chain so that
+         * VFP and per CPU interrupt context is saved.
+         */
+        if (cx->cpu_state == PWRDM_POWER_OFF)
+                cpu_pm_enter();
+
+        pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+        omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+
+        /*
+         * Call idle CPU cluster PM enter notifier chain
+         * to save GIC and wakeupgen context.
+         */
+        if ((cx->mpu_state == PWRDM_POWER_RET) &&
+                (cx->mpu_logic_state == PWRDM_POWER_OFF))
+                        cpu_cluster_pm_enter();
+
+        omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+
+        /*
+         * Call idle CPU PM exit notifier chain to restore
+         * VFP and per CPU IRQ context. Only CPU0 state is
+         * considered since CPU1 is managed by CPU hotplug.
+         */
+        if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
+                cpu_pm_exit();
+
+        /*
+         * Call idle CPU cluster PM exit notifier chain
+         * to restore GIC and wakeupgen context.
+         */
+        if (omap4_mpuss_read_prev_context_state())
+                cpu_cluster_pm_exit();
+
+        if (index > 0)
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+
+        getnstimeofday(&ts_postidle);
+        ts_idle = timespec_sub(ts_postidle, ts_preidle);
+
+        local_irq_enable();
+        local_fiq_enable();
+
+        idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
+                                                                USEC_PER_SEC;
+
+        /* Update cpuidle counters */
+        dev->last_residency = idle_time;
+
+        return index;
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
+
+struct cpuidle_driver omap4_idle_driver = {
+        .name =         "omap4_idle",
+        .owner =        THIS_MODULE,
+};
+
+static inline void _fill_cstate(struct cpuidle_driver *drv,
+                                        int idx, const char *descr)
+{
+        struct cpuidle_state *state = &drv->states[idx];
+
+        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
+        state->target_residency = cpuidle_params_table[idx].target_residency;
+        state->flags            = CPUIDLE_FLAG_TIME_VALID;
+        state->enter            = omap4_enter_idle;
+        sprintf(state->name, "C%d", idx + 1);
+        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
+}
+
+static inline struct omap4_idle_statedata *_fill_cstate_usage(
+                                        struct cpuidle_device *dev,
+                                        int idx)
+{
+        struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
+        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
+
+        cx->valid               = cpuidle_params_table[idx].valid;
+        cpuidle_set_statedata(state_usage, cx);
+
+        return cx;
+}
+
+
+
+/**
+ * omap4_idle_init - Init routine for OMAP4 idle
+ *
+ * Registers the OMAP4 specific cpuidle driver to the cpuidle
+ * framework with the valid set of states.
+ */
+int __init omap4_idle_init(void)
+{
+        struct omap4_idle_statedata *cx;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &omap4_idle_driver;
+        unsigned int cpu_id = 0;
+
+        mpu_pd = pwrdm_lookup("mpu_pwrdm");
+        cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
+        cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
+        if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+                return -ENODEV;
+
+
+        drv->safe_state_index = -1;
+        dev = &per_cpu(omap4_idle_dev, cpu_id);
+        dev->cpu = cpu_id;
+
+        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        _fill_cstate(drv, 0, "MPUSS ON");
+        drv->safe_state_index = 0;
+        cx = _fill_cstate_usage(dev, 0);
+        cx->valid = 1;  /* C1 is always valid */
+        cx->cpu_state = PWRDM_POWER_ON;
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->mpu_logic_state = PWRDM_POWER_RET;
+
+        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+        _fill_cstate(drv, 1, "MPUSS CSWR");
+        cx = _fill_cstate_usage(dev, 1);
+        cx->cpu_state = PWRDM_POWER_OFF;
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->mpu_logic_state = PWRDM_POWER_RET;
+
+        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        _fill_cstate(drv, 2, "MPUSS OSWR");
+        cx = _fill_cstate_usage(dev, 2);
+        cx->cpu_state = PWRDM_POWER_OFF;
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->mpu_logic_state = PWRDM_POWER_OFF;
+
+        drv->state_count = OMAP4_NUM_STATES;
+        cpuidle_register_driver(&omap4_idle_driver);
+
+        dev->state_count = OMAP4_NUM_STATES;
+        if (cpuidle_register_device(dev)) {
+                pr_err("%s: CPUidle register device failed\n", __func__);
+                        return -EIO;
+                }
+
+        return 0;
+}
+#else
+int __init omap4_idle_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c15cfada5f1..46dfd1ae8f7 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -28,6 +28,7 @@
 #include <plat/board.h>
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
+#include <plat/iommu.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -211,9 +212,15 @@ static struct platform_device omap3isp_device = {
         .resource       = omap3isp_resources,
 };
 
+static struct omap_iommu_arch_data omap3_isp_iommu = {
+        .name = "isp",
+};
+
 int omap3_init_camera(struct isp_platform_data *pdata)
 {
         omap3isp_device.dev.platform_data = pdata;
+        omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;
+
         return platform_device_register(&omap3isp_device);
 }
 
@@ -336,6 +343,27 @@ static void omap_init_mcpdm(void)
 static inline void omap_init_mcpdm(void) {}
 #endif
 
+#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
+                defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
+
+static void omap_init_dmic(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("dmic");
+        if (!oh) {
+                printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+                return;
+        }
+
+        pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
+}
+#else
+static inline void omap_init_dmic(void) {}
+#endif
+
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
 #include <plat/mcspi.h>
@@ -681,6 +709,7 @@ static int __init omap2_init_devices(void)
          */
         omap_init_audio();
         omap_init_mcpdm();
+        omap_init_dmic();
         omap_init_camera();
         omap_init_mbox();
         omap_init_mcspi();
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index f4a1020559a..bd844af13af 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -171,6 +171,17 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
         }
 }
 
+static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
+{
+        u32 reg;
+
+        if (mmc->slots[0].internal_clock) {
+                reg = omap_ctrl_readl(control_devconf1_offset);
+                reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+                omap_ctrl_writel(reg, control_devconf1_offset);
+        }
+}
+
 static void hsmmc23_before_set_reg(struct device *dev, int slot,
                                    int power_on, int vdd)
 {
@@ -179,16 +190,19 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot,
         if (mmc->slots[0].remux)
                 mmc->slots[0].remux(dev, slot, power_on);
 
-        if (power_on) {
-                /* Only MMC2 supports a CLKIN */
-                if (mmc->slots[0].internal_clock) {
-                        u32 reg;
+        if (power_on)
+                hsmmc2_select_input_clk_src(mmc);
+}
 
-                        reg = omap_ctrl_readl(control_devconf1_offset);
-                        reg |= OMAP2_MMCSDIO2ADPCLKISEL;
-                        omap_ctrl_writel(reg, control_devconf1_offset);
-                }
-        }
+static int am35x_hsmmc2_set_power(struct device *dev, int slot,
+                                  int power_on, int vdd)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        if (power_on)
+                hsmmc2_select_input_clk_src(mmc);
+
+        return 0;
 }
 
 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
@@ -200,10 +214,12 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                         int controller_nr)
 {
-        if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
+        if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
+                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
                                         OMAP_PIN_INPUT_PULLUP);
-        if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
+        if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
+                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
                                         OMAP_PIN_INPUT_PULLUP);
         if (cpu_is_omap34xx()) {
@@ -296,6 +312,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         mmc->slots[0].name = hc_name;
         mmc->nr_slots = 1;
         mmc->slots[0].caps = c->caps;
+        mmc->slots[0].pm_caps = c->pm_caps;
         mmc->slots[0].internal_clock = !c->ext_clock;
         mmc->dma_mask = 0xffffffff;
         if (cpu_is_omap44xx())
@@ -336,11 +353,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
          *
          * temporary HACK: ocr_mask instead of fixed supply
          */
-        mmc->slots[0].ocr_mask = c->ocr_mask;
-
-        if (cpu_is_omap3517() || cpu_is_omap3505())
-                mmc->slots[0].set_power = nop_mmc_set_power;
+        if (cpu_is_omap3505() || cpu_is_omap3517())
+                mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
+                                         MMC_VDD_26_27 |
+                                         MMC_VDD_27_28 |
+                                         MMC_VDD_29_30 |
+                                         MMC_VDD_30_31 |
+                                         MMC_VDD_31_32;
         else
+                mmc->slots[0].ocr_mask = c->ocr_mask;
+
+        if (!cpu_is_omap3517() && !cpu_is_omap3505())
                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
@@ -363,6 +386,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                         }
                 }
 
+                if (cpu_is_omap3517() || cpu_is_omap3505())
+                        mmc->slots[0].set_power = nop_mmc_set_power;
+
                 /* OMAP3630 HSMMC1 supports only 4-bit */
                 if (cpu_is_omap3630() &&
                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
@@ -372,6 +398,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                 }
                 break;
         case 2:
+                if (cpu_is_omap3517() || cpu_is_omap3505())
+                        mmc->slots[0].set_power = am35x_hsmmc2_set_power;
+
                 if (c->ext_clock)
                         c->transceiver = 1;
                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index f757e78d4d4..c4409730c4b 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -12,6 +12,7 @@ struct omap2_hsmmc_info {
         u8      mmc;            /* controller 1/2/3 */
         u32     caps;           /* 4/8 wires and any additional host
                                  * capabilities OR'd (ref. linux/mmc/host.h) */
+        u32     pm_caps;        /* PM capabilities */
         bool    transceiver;    /* MMC-2 option */
         bool    ext_clock;      /* use external pin for input clock */
         bool    cover_only;     /* No card detect - just cover switch */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 27ad722df63..6c5826605ea 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -226,7 +226,7 @@ static void __init omap4_check_features(void)
         }
 }
 
-static void __init ti816x_check_features(void)
+static void __init ti81xx_check_features(void)
 {
         omap_features = OMAP3_HAS_NEON;
 }
@@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
                         break;
                 }
                 break;
+        case 0xb944:
+                omap_revision = AM335X_REV_ES1_0;
+                *cpu_rev = "1.0";
+        case 0xb8f2:
+                switch (rev) {
+                case 0:
+                /* FALLTHROUGH */
+                case 1:
+                        omap_revision = TI8148_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 2:
+                        omap_revision = TI8148_REV_ES2_0;
+                        *cpu_rev = "2.0";
+                        break;
+                case 3:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8148_REV_ES2_1;
+                        *cpu_rev = "2.1";
+                        break;
+                }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default */
                 omap_revision = OMAP3630_REV_ES1_2;
@@ -367,7 +390,7 @@ static void __init omap4_check_revision(void)
          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
          * Use ARM register to detect the correct ES version
          */
-        if (!rev && (hawkeye != 0xb94e)) {
+        if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
                 idcode = read_cpuid(CPUID_ID);
                 rev = (idcode & 0xf) - 1;
         }
@@ -389,8 +412,11 @@ static void __init omap4_check_revision(void)
                         omap_revision = OMAP4430_REV_ES2_1;
                         break;
                 case 4:
-                default:
                         omap_revision = OMAP4430_REV_ES2_2;
+                        break;
+                case 6:
+                default:
+                        omap_revision = OMAP4430_REV_ES2_3;
                 }
                 break;
         case 0xb94e:
@@ -401,9 +427,17 @@ static void __init omap4_check_revision(void)
                         break;
                 }
                 break;
+        case 0xb975:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP4470_REV_ES1_0;
+                        break;
+                }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default */
-                omap_revision = OMAP4430_REV_ES2_2;
+                omap_revision = OMAP4430_REV_ES2_3;
         }
 
         pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
         } else if (cpu_is_ti816x()) {
                 cpu_name = "TI816X";
+        } else if (cpu_is_am335x()) {
+                cpu_name =  "AM335X";
+        } else if (cpu_is_ti814x()) {
+                cpu_name = "TI814X";
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                 cpu_name = "OMAP3430/3530";
@@ -472,11 +510,11 @@ void __init omap2_check_revision(void)
         } else if (cpu_is_omap34xx()) {
                 omap3_check_revision(&cpu_rev);
 
-                /* TI816X doesn't have feature register */
-                if (!cpu_is_ti816x())
+                /* TI81XX doesn't have feature register */
+                if (!cpu_is_ti81xx())
                         omap3_check_features();
                 else
-                        ti816x_check_features();
+                        ti81xx_check_features();
 
                 omap3_cpuinfo(cpu_rev);
                 return;
diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h
new file mode 100644
index 00000000000..4fa72c7cc7c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/barriers.h
@@ -0,0 +1,31 @@
+/*
+ * OMAP memory barrier header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *  Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_BARRIERS_H
+#define __MACH_BARRIERS_H
+
+extern void omap_bus_sync(void);
+
+#define rmb()           dsb()
+#define wmb()           do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
+#define mb()            wmb()
+
+#endif  /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 13f98e59cfe..cdfc2a1f0e7 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -66,11 +66,11 @@ omap_uart_lsr:	.word	0
                 beq     34f                     @ configure OMAP3UART4
                 cmp     \rp, #OMAP4UART4        @ only on 44xx
                 beq     44f                     @ configure OMAP4UART4
-                cmp     \rp, #TI816XUART1       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
                 beq     81f                     @ configure UART1
-                cmp     \rp, #TI816XUART2       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
                 beq     82f                     @ configure UART2
-                cmp     \rp, #TI816XUART3       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
                 beq     83f                     @ configure UART3
                 cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
@@ -94,11 +94,11 @@ omap_uart_lsr:	.word	0
                 b       98f
 44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                 b       98f
-81:             mov     \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81:             mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
                 b       98f
-82:             mov     \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82:             mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
                 b       98f
-83:             mov     \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                 b       98f
 
 95:             ldr     \rp, =ZOOM_UART_BASE
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/include/mach/omap-secure.h
new file mode 100644
index 00000000000..c90a43589ab
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-secure.h
@@ -0,0 +1,57 @@
+/*
+ * omap-secure.h: OMAP Secure infrastructure header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP_SECURE_H
+#define OMAP_ARCH_OMAP_SECURE_H
+
+/* Monitor error code */
+#define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR        0xFFFFFFFE
+#define  API_HAL_RET_VALUE_SERVICE_UNKNWON              0xFFFFFFFF
+
+/* HAL API error codes */
+#define  API_HAL_RET_VALUE_OK           0x00
+#define  API_HAL_RET_VALUE_FAIL         0x01
+
+/* Secure HAL API flags */
+#define FLAG_START_CRITICAL             0x4
+#define FLAG_IRQFIQ_MASK                0x3
+#define FLAG_IRQ_ENABLE                 0x2
+#define FLAG_FIQ_ENABLE                 0x1
+#define NO_FLAG                         0x0
+
+/* Maximum Secure memory storage size */
+#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
+
+/* Secure low power HAL API index */
+#define OMAP4_HAL_SAVESECURERAM_INDEX   0x1a
+#define OMAP4_HAL_SAVEHW_INDEX          0x1b
+#define OMAP4_HAL_SAVEALL_INDEX         0x1c
+#define OMAP4_HAL_SAVEGIC_INDEX         0x1d
+
+/* Secure Monitor mode APIs */
+#define OMAP4_MON_SCU_PWR_INDEX         0x108
+#define OMAP4_MON_L2X0_DBG_CTRL_INDEX   0x100
+#define OMAP4_MON_L2X0_CTRL_INDEX       0x102
+#define OMAP4_MON_L2X0_AUXCTRL_INDEX    0x109
+#define OMAP4_MON_L2X0_PREFETCH_INDEX   0x113
+
+/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_L2_POR_INDEX          0x23
+#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX   0x25
+
+#ifndef __ASSEMBLER__
+
+extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
+                                u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
+extern phys_addr_t omap_secure_ram_mempool_base(void);
+
+#endif /* __ASSEMBLER__ */
+#endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
new file mode 100644
index 00000000000..d79321b0f2a
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -0,0 +1,39 @@
+/*
+ * OMAP WakeupGen header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_ARCH_WAKEUPGEN_H
+
+#define OMAP_WKG_CONTROL_0                      0x00
+#define OMAP_WKG_ENB_A_0                        0x10
+#define OMAP_WKG_ENB_B_0                        0x14
+#define OMAP_WKG_ENB_C_0                        0x18
+#define OMAP_WKG_ENB_D_0                        0x1c
+#define OMAP_WKG_ENB_SECURE_A_0                 0x20
+#define OMAP_WKG_ENB_SECURE_B_0                 0x24
+#define OMAP_WKG_ENB_SECURE_C_0                 0x28
+#define OMAP_WKG_ENB_SECURE_D_0                 0x2c
+#define OMAP_WKG_ENB_A_1                        0x410
+#define OMAP_WKG_ENB_B_1                        0x414
+#define OMAP_WKG_ENB_C_1                        0x418
+#define OMAP_WKG_ENB_D_1                        0x41c
+#define OMAP_WKG_ENB_SECURE_A_1                 0x420
+#define OMAP_WKG_ENB_SECURE_B_1                 0x424
+#define OMAP_WKG_ENB_SECURE_C_1                 0x428
+#define OMAP_WKG_ENB_SECURE_D_1                 0x42c
+#define OMAP_AUX_CORE_BOOT_0                    0x800
+#define OMAP_AUX_CORE_BOOT_1                    0x804
+#define OMAP_PTMSYNCREQ_MASK                    0xc00
+#define OMAP_PTMSYNCREQ_EN                      0xc04
+#define OMAP_TIMESTAMPCYCLELO                   0xc08
+#define OMAP_TIMESTAMPCYCLEHI                   0xc0c
+
+extern int __init omap_wakeupgen_init(void);
+#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3f565dd2ea8..3f174d51f67 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI816X
-static struct map_desc omapti816x_io_desc[] __initdata = {
+#ifdef CONFIG_SOC_OMAPTI81XX
+static struct map_desc omapti81xx_io_desc[] __initdata = {
+        {
+                .virtual        = L4_34XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
+                .length         = L4_34XX_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
         {
                 .virtual        = L4_34XX_VIRT,
                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
                 .length         = L4_34XX_SIZE,
                 .type           = MT_DEVICE
         },
+        {
+                .virtual        = L4_WK_AM33XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
+                .length         = L4_WK_AM33XX_SIZE,
+                .type           = MT_DEVICE
+        }
 };
 #endif
 
@@ -237,6 +254,15 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
                 .length         = L4_EMU_44XX_SIZE,
                 .type           = MT_DEVICE,
         },
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        {
+                .virtual        = OMAP4_SRAM_VA,
+                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
+                .length         = PAGE_SIZE,
+                .type           = MT_MEMORY_SO,
+        },
+#endif
+
 };
 #endif
 
@@ -263,10 +289,17 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI816X
-void __init omapti816x_map_common_io(void)
+#ifdef CONFIG_SOC_OMAPTI81XX
+void __init omapti81xx_map_common_io(void)
+{
+        iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
 {
-        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+        iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 }
 #endif
 
@@ -418,9 +451,9 @@ void __init am35xx_init_early(void)
         omap3_init_early();
 }
 
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
 {
-        omap2_set_globals_ti816x();
+        omap2_set_globals_ti81xx();
         omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 42b1d659191..1fef061f792 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -193,7 +193,7 @@ void __init omap3_init_irq(void)
         omap_init_irq(OMAP34XX_IC_BASE, 96);
 }
 
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
 {
         omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 655e9480eb9..e1cc75d1a57 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -32,6 +32,8 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/uaccess.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
 
 #include <asm/system.h>
 
@@ -39,6 +41,7 @@
 
 #include "control.h"
 #include "mux.h"
+#include "prm.h"
 
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ                0x5ca
@@ -306,7 +309,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
                 pad->idle = bpad->idle;
                 pad->off = bpad->off;
 
-                if (pad->flags & OMAP_DEVICE_PAD_REMUX)
+                if (pad->flags &
+                    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
                         nr_pads_dynamic++;
 
                 pr_debug("%s: Initialized %s\n", __func__, pad->name);
@@ -331,7 +335,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
         for (i = 0; i < hmux->nr_pads; i++) {
                 struct omap_device_pad *pad = &hmux->pads[i];
 
-                if (pad->flags & OMAP_DEVICE_PAD_REMUX) {
+                if (pad->flags &
+                    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
                         pr_debug("%s: pad %s tagged dynamic\n",
                                         __func__, pad->name);
                         hmux->pads_dynamic[nr_pads_dynamic] = pad;
@@ -351,6 +356,78 @@ err1:
         return NULL;
 }
 
+/**
+ * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
+ * @hmux: Pads for a hwmod
+ * @mpu_irqs: MPU irq array for a hwmod
+ *
+ * Scans the wakeup status of pads for a single hwmod.  If an irq
+ * array is defined for this mux, the parser will call the registered
+ * ISRs for corresponding pads, otherwise the parser will stop at the
+ * first wakeup active pad and return.  Returns true if there is a
+ * pending and non-served wakeup event for the mux, otherwise false.
+ */
+static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
+                struct omap_hwmod_irq_info *mpu_irqs)
+{
+        int i, irq;
+        unsigned int val;
+        u32 handled_irqs = 0;
+
+        for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+                struct omap_device_pad *pad = hmux->pads_dynamic[i];
+
+                if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
+                    !(pad->idle & OMAP_WAKEUP_EN))
+                        continue;
+
+                val = omap_mux_read(pad->partition, pad->mux->reg_offset);
+                if (!(val & OMAP_WAKEUP_EVENT))
+                        continue;
+
+                if (!hmux->irqs)
+                        return true;
+
+                irq = hmux->irqs[i];
+                /* make sure we only handle each irq once */
+                if (handled_irqs & 1 << irq)
+                        continue;
+
+                handled_irqs |= 1 << irq;
+
+                generic_handle_irq(mpu_irqs[irq].irq);
+        }
+
+        return false;
+}
+
+/**
+ * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
+ *
+ * Checks a single hwmod for every wakeup capable pad to see if there is an
+ * active wakeup event. If this is the case, call the corresponding ISR.
+ */
+static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
+{
+        if (!oh->mux || !oh->mux->enabled)
+                return 0;
+        if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
+                generic_handle_irq(oh->mpu_irqs[0].irq);
+        return 0;
+}
+
+/**
+ * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
+ *
+ * Calls a function for each registered omap_hwmod to check
+ * pad wakeup statuses.
+ */
+static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
+{
+        omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
+        return IRQ_HANDLED;
+}
+
 /* Assumes the calling function takes care of locking */
 void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
 {
@@ -715,6 +792,7 @@ static void __init omap_mux_free_names(struct omap_mux *m)
 static int __init omap_mux_late_init(void)
 {
         struct omap_mux_partition *partition;
+        int ret;
 
         list_for_each_entry(partition, &mux_partitions, node) {
                 struct omap_mux_entry *e, *tmp;
@@ -735,6 +813,13 @@ static int __init omap_mux_late_init(void)
                 }
         }
 
+        ret = request_irq(omap_prcm_event_to_irq("io"),
+                omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
+                        "hwmod_io", omap_mux_late_init);
+
+        if (ret)
+                pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
+
         omap_mux_dbg_init();
 
         return 0;
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4ee6aeca885..b13ef7ef5ef 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,11 +18,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-/* Physical address needed since MMU not enabled yet on secondary core */
-#define OMAP4_AUX_CORE_BOOT1_PA                 0x48281804
-
-        __INIT
-
 /*
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index e5a1c3f40a8..adbe4d8c7ca 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -22,6 +22,8 @@
 
 #include "common.h"
 
+#include "powerdomain.h"
+
 int platform_cpu_kill(unsigned int cpu)
 {
         return 1;
@@ -33,6 +35,8 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
+        unsigned int this_cpu;
+
         flush_cache_all();
         dsb();
 
@@ -40,15 +44,15 @@ void platform_cpu_die(unsigned int cpu)
          * we're ready for shutdown now, so do it
          */
         if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-                printk(KERN_CRIT "Secure clear status failed\n");
+                pr_err("Secure clear status failed\n");
 
         for (;;) {
                 /*
-                 * Execute WFI
+                 * Enter into low power state
                  */
-                do_wfi();
-
-                if (omap_read_auxcoreboot0() == cpu) {
+                omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
+                this_cpu = smp_processor_id();
+                if (omap_read_auxcoreboot0() == this_cpu) {
                         /*
                          * OK, proper wakeup, we're done
                          */
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
new file mode 100644
index 00000000000..1d5d0105655
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -0,0 +1,398 @@
+/*
+ * OMAP MPUSS low power code
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
+ * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
+ * CPU0 and CPU1 LPRM modules.
+ * CPU0, CPU1 and MPUSS each have there own power domain and
+ * hence multiple low power combinations of MPUSS are possible.
+ *
+ * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
+ * because the mode is not supported by hw constraints of dormant
+ * mode. While waking up from the dormant mode, a reset  signal
+ * to the Cortex-A9 processor must be asserted by the external
+ * power controller.
+ *
+ * With architectural inputs and hardware recommendations, only
+ * below modes are supported from power gain vs latency point of view.
+ *
+ *      CPU0            CPU1            MPUSS
+ *      ----------------------------------------------
+ *      ON              ON              ON
+ *      ON(Inactive)    OFF             ON(Inactive)
+ *      OFF             OFF             CSWR
+ *      OFF             OFF             OSWR
+ *      OFF             OFF             OFF(Device OFF *TBD)
+ *      ----------------------------------------------
+ *
+ * Note: CPU0 is the master core and it is the last CPU to go down
+ * and first to wake-up when MPUSS low power states are excercised
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/linkage.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/pgalloc.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <plat/omap44xx.h>
+
+#include "common.h"
+#include "omap4-sar-layout.h"
+#include "pm.h"
+#include "prcm_mpu44xx.h"
+#include "prminst44xx.h"
+#include "prcm44xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+
+#ifdef CONFIG_SMP
+
+struct omap4_cpu_pm_info {
+        struct powerdomain *pwrdm;
+        void __iomem *scu_sar_addr;
+        void __iomem *wkup_sar_addr;
+        void __iomem *l2x0_sar_addr;
+};
+
+static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
+static struct powerdomain *mpuss_pd;
+static void __iomem *sar_base;
+
+/*
+ * Program the wakeup routine address for the CPU0 and CPU1
+ * used for OFF or DORMANT wakeup.
+ */
+static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+        __raw_writel(addr, pm_info->wkup_sar_addr);
+}
+
+/*
+ * Set the CPUx powerdomain's previous power state
+ */
+static inline void set_cpu_next_pwrst(unsigned int cpu_id,
+                                unsigned int power_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+}
+
+/*
+ * Read CPU's previous power state
+ */
+static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+        return pwrdm_read_prev_pwrst(pm_info->pwrdm);
+}
+
+/*
+ * Clear the CPUx powerdomain's previous power state
+ */
+static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+}
+
+/*
+ * Store the SCU power status value to scratchpad memory
+ */
+static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        u32 scu_pwr_st;
+
+        switch (cpu_state) {
+        case PWRDM_POWER_RET:
+                scu_pwr_st = SCU_PM_DORMANT;
+                break;
+        case PWRDM_POWER_OFF:
+                scu_pwr_st = SCU_PM_POWEROFF;
+                break;
+        case PWRDM_POWER_ON:
+        case PWRDM_POWER_INACTIVE:
+        default:
+                scu_pwr_st = SCU_PM_NORMAL;
+                break;
+        }
+
+        __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+}
+
+/* Helper functions for MPUSS OSWR */
+static inline void mpuss_clear_prev_logic_pwrst(void)
+{
+        u32 reg;
+
+        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+        omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+}
+
+static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
+{
+        u32 reg;
+
+        if (cpu_id) {
+                reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
+                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+                omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
+                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+        } else {
+                reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
+                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+                omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
+                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+        }
+}
+
+/**
+ * omap4_mpuss_read_prev_context_state:
+ * Function returns the MPUSS previous context state
+ */
+u32 omap4_mpuss_read_prev_context_state(void)
+{
+        u32 reg;
+
+        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+        reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
+        return reg;
+}
+
+/*
+ * Store the CPU cluster state for L2X0 low power operations.
+ */
+static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+        __raw_writel(save_state, pm_info->l2x0_sar_addr);
+}
+
+/*
+ * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
+ * in every restore MPUSS OFF path.
+ */
+#ifdef CONFIG_CACHE_L2X0
+static void save_l2x0_context(void)
+{
+        u32 val;
+        void __iomem *l2x0_base = omap4_get_l2cache_base();
+
+        val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+        __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+        val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+        __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+}
+#else
+static void save_l2x0_context(void)
+{}
+#endif
+
+/**
+ * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
+ * The purpose of this function is to manage low power programming
+ * of OMAP4 MPUSS subsystem
+ * @cpu : CPU ID
+ * @power_state: Low power state.
+ *
+ * MPUSS states for the context save:
+ * save_state =
+ *      0 - Nothing lost and no need to save: MPUSS INACTIVE
+ *      1 - CPUx L1 and logic lost: MPUSS CSWR
+ *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
+ */
+int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
+{
+        unsigned int save_state = 0;
+        unsigned int wakeup_cpu;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+
+        switch (power_state) {
+        case PWRDM_POWER_ON:
+        case PWRDM_POWER_INACTIVE:
+                save_state = 0;
+                break;
+        case PWRDM_POWER_OFF:
+                save_state = 1;
+                break;
+        case PWRDM_POWER_RET:
+        default:
+                /*
+                 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
+                 * doesn't make much scense, since logic is lost and $L1
+                 * needs to be cleaned because of coherency. This makes
+                 * CPUx OSWR equivalent to CPUX OFF and hence not supported
+                 */
+                WARN_ON(1);
+                return -ENXIO;
+        }
+
+        pwrdm_pre_transition();
+
+        /*
+         * Check MPUSS next state and save interrupt controller if needed.
+         * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
+         */
+        mpuss_clear_prev_logic_pwrst();
+        pwrdm_clear_all_prev_pwrst(mpuss_pd);
+        if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
+                (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
+                save_state = 2;
+
+        clear_cpu_prev_pwrst(cpu);
+        cpu_clear_prev_logic_pwrst(cpu);
+        set_cpu_next_pwrst(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
+        scu_pwrst_prepare(cpu, power_state);
+        l2x0_pwrst_prepare(cpu, save_state);
+
+        /*
+         * Call low level function  with targeted low power state.
+         */
+        cpu_suspend(save_state, omap4_finish_suspend);
+
+        /*
+         * Restore the CPUx power state to ON otherwise CPUx
+         * power domain can transitions to programmed low power
+         * state while doing WFI outside the low powe code. On
+         * secure devices, CPUx does WFI which can result in
+         * domain transition
+         */
+        wakeup_cpu = smp_processor_id();
+        set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
+
+        pwrdm_post_transition();
+
+        return 0;
+}
+
+/**
+ * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
+ * @cpu : CPU ID
+ * @power_state: CPU low power state.
+ */
+int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+        unsigned int cpu_state = 0;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+
+        if (power_state == PWRDM_POWER_OFF)
+                cpu_state = 1;
+
+        clear_cpu_prev_pwrst(cpu);
+        set_cpu_next_pwrst(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
+        scu_pwrst_prepare(cpu, power_state);
+
+        /*
+         * CPU never retuns back if targetted power state is OFF mode.
+         * CPU ONLINE follows normal CPU ONLINE ptah via
+         * omap_secondary_startup().
+         */
+        omap4_finish_suspend(cpu_state);
+
+        set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
+        return 0;
+}
+
+
+/*
+ * Initialise OMAP4 MPUSS
+ */
+int __init omap4_mpuss_init(void)
+{
+        struct omap4_cpu_pm_info *pm_info;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+
+        sar_base = omap4_get_sar_ram_base();
+
+        /* Initilaise per CPU PM information */
+        pm_info = &per_cpu(omap4_pm_info, 0x0);
+        pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+        pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+        pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
+        if (!pm_info->pwrdm) {
+                pr_err("Lookup failed for CPU0 pwrdm\n");
+                return -ENODEV;
+        }
+
+        /* Clear CPU previous power domain state */
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+        cpu_clear_prev_logic_pwrst(0);
+
+        /* Initialise CPU0 power domain state to ON */
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+
+        pm_info = &per_cpu(omap4_pm_info, 0x1);
+        pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+        pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+        pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
+        if (!pm_info->pwrdm) {
+                pr_err("Lookup failed for CPU1 pwrdm\n");
+                return -ENODEV;
+        }
+
+        /* Clear CPU previous power domain state */
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+        cpu_clear_prev_logic_pwrst(1);
+
+        /* Initialise CPU1 power domain state to ON */
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+
+        mpuss_pd = pwrdm_lookup("mpu_pwrdm");
+        if (!mpuss_pd) {
+                pr_err("Failed to lookup MPUSS power domain\n");
+                return -ENODEV;
+        }
+        pwrdm_clear_all_prev_pwrst(mpuss_pd);
+        mpuss_clear_prev_logic_pwrst();
+
+        /* Save device type on scratchpad for low level code to use */
+        if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+                __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+        else
+                __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+
+        save_l2x0_context();
+
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
new file mode 100644
index 00000000000..69f3c72d959
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -0,0 +1,81 @@
+/*
+ * OMAP Secure API infrastructure.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/omap-secure.h>
+
+static phys_addr_t omap_secure_memblock_base;
+
+/**
+ * omap_sec_dispatcher: Routine to dispatch low power secure
+ * service routines
+ * @idx: The HAL API index
+ * @flag: The flag indicating criticality of operation
+ * @nargs: Number of valid arguments out of four.
+ * @arg1, arg2, arg3 args4: Parameters passed to secure API
+ *
+ * Return the non-zero error value on failure.
+ */
+u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
+                                                         u32 arg3, u32 arg4)
+{
+        u32 ret;
+        u32 param[5];
+
+        param[0] = nargs;
+        param[1] = arg1;
+        param[2] = arg2;
+        param[3] = arg3;
+        param[4] = arg4;
+
+        /*
+         * Secure API needs physical address
+         * pointer for the parameters
+         */
+        flush_cache_all();
+        outer_clean_range(__pa(param), __pa(param + 5));
+        ret = omap_smc2(idx, flag, __pa(param));
+
+        return ret;
+}
+
+/* Allocate the memory to save secure ram */
+int __init omap_secure_ram_reserve_memblock(void)
+{
+        phys_addr_t paddr;
+        u32 size = OMAP_SECURE_RAM_STORAGE;
+
+        size = ALIGN(size, SZ_1M);
+        paddr = memblock_alloc(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve %x bytes\n",
+                                __func__, size);
+                return -ENOMEM;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+
+        omap_secure_memblock_base = paddr;
+
+        return 0;
+}
+
+phys_addr_t omap_secure_ram_mempool_base(void)
+{
+        return omap_secure_memblock_base;
+}
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap-smc.S
index e69d37d9520..f6441c13cd8 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap-smc.S
@@ -31,6 +31,29 @@ ENTRY(omap_smc1)
         ldmfd   sp!, {r2-r12, pc}
 ENDPROC(omap_smc1)
 
+/**
+ * u32 omap_smc2(u32 id, u32 falg, u32 pargs)
+ * Low level common routine for secure HAL and PPA APIs.
+ * @id: Application ID of HAL APIs
+ * @flag: Flag to indicate the criticality of operation
+ * @pargs: Physical address of parameter list starting
+ *          with number of parametrs
+ */
+ENTRY(omap_smc2)
+        stmfd   sp!, {r4-r12, lr}
+        mov     r3, r2
+        mov     r2, r1
+        mov     r1, #0x0        @ Process ID
+        mov     r6, #0xff
+        mov     r12, #0x00      @ Secure Service ID
+        mov     r7, #0
+        mcr     p15, 0, r7, c7, c5, 6
+        dsb
+        dmb
+        smc     #0
+        ldmfd   sp!, {r4-r12, pc}
+ENDPROC(omap_smc2)
+
 ENTRY(omap_modify_auxcoreboot0)
         stmfd   sp!, {r1-r12, lr}
         ldr     r12, =0x104
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index e99bc6cd471..c1bf3ef0ba0 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,17 +24,37 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
+#include <mach/omap-secure.h>
 
 #include "common.h"
 
+#include "clockdomain.h"
+
 /* SCU base address */
 static void __iomem *scu_base;
 
 static DEFINE_SPINLOCK(boot_lock);
 
+void __iomem *omap4_get_scu_base(void)
+{
+        return scu_base;
+}
+
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
         /*
+         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
+         * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
+         * init and for CPU1, a secure PPA API provided. CPU0 must be ON
+         * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
+         * OMAP443X GP devices- SMP bit isn't accessible.
+         * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
+         */
+        if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
+                                                        4, 0, 0, 0, 0, 0);
+
+        /*
          * If any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
@@ -50,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        static struct clockdomain *cpu1_clkdm;
+        static bool booted;
         /*
          * Set synchronisation state between this boot processor
          * and the secondary one
@@ -65,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         omap_modify_auxcoreboot0(0x200, 0xfffffdff);
         flush_cache_all();
         smp_wmb();
+
+        if (!cpu1_clkdm)
+                cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+
+        /*
+         * The SGI(Software Generated Interrupts) are not wakeup capable
+         * from low power states. This is known limitation on OMAP4 and
+         * needs to be worked around by using software forced clockdomain
+         * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
+         * software force wakeup. The clockdomain is then put back to
+         * hardware supervised mode.
+         * More details can be found in OMAP4430 TRM - Version J
+         * Section :
+         *      4.3.4.2 Power States of CPU0 and CPU1
+         */
+        if (booted) {
+                clkdm_wakeup(cpu1_clkdm);
+                clkdm_allow_idle(cpu1_clkdm);
+        } else {
+                dsb_sev();
+                booted = true;
+        }
+
         gic_raise_softirq(cpumask_of(cpu), 1);
 
         /*
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
new file mode 100644
index 00000000000..d3d8971d7f3
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -0,0 +1,389 @@
+/*
+ * OMAP WakeupGen Source file
+ *
+ * OMAP WakeupGen is the interrupt controller extension used along
+ * with ARM GIC to wake the CPU out from low power states on
+ * external interrupts. It is responsible for generating wakeup
+ * event from the incoming interrupts and enable bits. It is
+ * implemented in MPU always ON power domain. During normal operation,
+ * WakeupGen delivers external interrupts directly to the GIC.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/cpu.h>
+#include <linux/notifier.h>
+#include <linux/cpu_pm.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/omap-wakeupgen.h>
+#include <mach/omap-secure.h>
+
+#include "omap4-sar-layout.h"
+#include "common.h"
+
+#define NR_REG_BANKS            4
+#define MAX_IRQS                128
+#define WKG_MASK_ALL            0x00000000
+#define WKG_UNMASK_ALL          0xffffffff
+#define CPU_ENA_OFFSET          0x400
+#define CPU0_ID                 0x0
+#define CPU1_ID                 0x1
+
+static void __iomem *wakeupgen_base;
+static void __iomem *sar_base;
+static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_SPINLOCK(wakeupgen_lock);
+static unsigned int irq_target_cpu[NR_IRQS];
+
+/*
+ * Static helper functions.
+ */
+static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
+{
+        return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+
+static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
+{
+        __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+
+static inline void sar_writel(u32 val, u32 offset, u8 idx)
+{
+        __raw_writel(val, sar_base + offset + (idx * 4));
+}
+
+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(reg, i, cpu);
+}
+
+static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
+{
+        unsigned int spi_irq;
+
+        /*
+         * PPIs and SGIs are not supported.
+         */
+        if (irq < OMAP44XX_IRQ_GIC_START)
+                return -EINVAL;
+
+        /*
+         * Subtract the GIC offset.
+         */
+        spi_irq = irq - OMAP44XX_IRQ_GIC_START;
+        if (spi_irq > MAX_IRQS) {
+                pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
+                return -EINVAL;
+        }
+
+        /*
+         * Each WakeupGen register controls 32 interrupt.
+         * i.e. 1 bit per SPI IRQ
+         */
+        *reg_index = spi_irq >> 5;
+        *bit_posn = spi_irq %= 32;
+
+        return 0;
+}
+
+static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
+{
+        u32 val, bit_number;
+        u8 i;
+
+        if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+                return;
+
+        val = wakeupgen_readl(i, cpu);
+        val &= ~BIT(bit_number);
+        wakeupgen_writel(val, i, cpu);
+}
+
+static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
+{
+        u32 val, bit_number;
+        u8 i;
+
+        if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+                return;
+
+        val = wakeupgen_readl(i, cpu);
+        val |= BIT(bit_number);
+        wakeupgen_writel(val, i, cpu);
+}
+
+static void _wakeupgen_save_masks(unsigned int cpu)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
+}
+
+static void _wakeupgen_restore_masks(unsigned int cpu)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
+}
+
+/*
+ * Architecture specific Mask extension
+ */
+static void wakeupgen_mask(struct irq_data *d)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+
+/*
+ * Architecture specific Unmask extension
+ */
+static void wakeupgen_unmask(struct irq_data *d)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+
+/*
+ * Mask or unmask all interrupts on given CPU.
+ *      0 = Mask all interrupts on the 'cpu'
+ *      1 = Unmask all interrupts on the 'cpu'
+ * Ensure that the initial mask is maintained. This is faster than
+ * iterating through GIC registers to arrive at the correct masks.
+ */
+static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        if (set) {
+                _wakeupgen_save_masks(cpu);
+                _wakeupgen_set_all(cpu, WKG_MASK_ALL);
+        } else {
+                _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
+                _wakeupgen_restore_masks(cpu);
+        }
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+
+#ifdef CONFIG_CPU_PM
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+        u32 i, val;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return;
+
+        if (!sar_base)
+                sar_base = omap4_get_sar_ram_base();
+
+        for (i = 0; i < NR_REG_BANKS; i++) {
+                /* Save the CPUx interrupt mask for IRQ 0 to 127 */
+                val = wakeupgen_readl(i, 0);
+                sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
+                val = wakeupgen_readl(i, 1);
+                sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
+
+                /*
+                 * Disable the secure interrupts for CPUx. The restore
+                 * code blindly restores secure and non-secure interrupt
+                 * masks from SAR RAM. Secure interrupts are not suppose
+                 * to be enabled from HLOS. So overwrite the SAR location
+                 * so that the secure interrupt remains disabled.
+                 */
+                sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+                sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+        }
+
+        /* Save AuxBoot* registers */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+
+        /* Save SyncReq generation logic */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+
+        /* Save SyncReq generation logic */
+        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+        __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+        __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+
+        /* Set the Backup Bit Mask status */
+        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+
+/*
+ * Clear WakeupGen SAR backup status.
+ */
+void irq_sar_clear(void)
+{
+        u32 val;
+        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+
+/*
+ * Save GIC and Wakeupgen interrupt context using secure API
+ * for HS/EMU devices.
+ */
+static void irq_save_secure_context(void)
+{
+        u32 ret;
+        ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
+                                FLAG_START_CRITICAL,
+                                0, 0, 0, 0, 0);
+        if (ret != API_HAL_RET_VALUE_OK)
+                pr_err("GIC and Wakeupgen context save failed\n");
+}
+#endif
+
+#ifdef CONFIG_HOTPLUG_CPU
+static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
+                                         unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned int)hcpu;
+
+        switch (action) {
+        case CPU_ONLINE:
+                wakeupgen_irqmask_all(cpu, 0);
+                break;
+        case CPU_DEAD:
+                wakeupgen_irqmask_all(cpu, 1);
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __refdata irq_hotplug_notifier = {
+        .notifier_call = irq_cpu_hotplug_notify,
+};
+
+static void __init irq_hotplug_init(void)
+{
+        register_hotcpu_notifier(&irq_hotplug_notifier);
+}
+#else
+static void __init irq_hotplug_init(void)
+{}
+#endif
+
+#ifdef CONFIG_CPU_PM
+static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+        switch (cmd) {
+        case CPU_CLUSTER_PM_ENTER:
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                        irq_save_context();
+                else
+                        irq_save_secure_context();
+                break;
+        case CPU_CLUSTER_PM_EXIT:
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                        irq_sar_clear();
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block irq_notifier_block = {
+        .notifier_call = irq_notifier,
+};
+
+static void __init irq_pm_init(void)
+{
+        cpu_pm_register_notifier(&irq_notifier_block);
+}
+#else
+static void __init irq_pm_init(void)
+{}
+#endif
+
+/*
+ * Initialise the wakeupgen module.
+ */
+int __init omap_wakeupgen_init(void)
+{
+        int i;
+        unsigned int boot_cpu = smp_processor_id();
+
+        /* Not supported on OMAP4 ES1.0 silicon */
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
+                return -EPERM;
+        }
+
+        /* Static mapping, never released */
+        wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+        if (WARN_ON(!wakeupgen_base))
+                return -ENOMEM;
+
+        /* Clear all IRQ bitmasks at wakeupGen level */
+        for (i = 0; i < NR_REG_BANKS; i++) {
+                wakeupgen_writel(0, i, CPU0_ID);
+                wakeupgen_writel(0, i, CPU1_ID);
+        }
+
+        /*
+         * Override GIC architecture specific functions to add
+         * OMAP WakeupGen interrupt controller along with GIC
+         */
+        gic_arch_extn.irq_mask = wakeupgen_mask;
+        gic_arch_extn.irq_unmask = wakeupgen_unmask;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
+
+        /*
+         * FIXME: Add support to set_smp_affinity() once the core
+         * GIC code has necessary hooks in place.
+         */
+
+        /* Associate all the IRQs to boot CPU like GIC init does. */
+        for (i = 0; i < NR_IRQS; i++)
+                irq_target_cpu[i] = boot_cpu;
+
+        irq_hotplug_init();
+        irq_pm_init();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index beecfdd56ea..bc16c818c6b 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -15,18 +15,73 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/memblock.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/map.h>
 
 #include <plat/irqs.h>
+#include <plat/sram.h>
 
 #include <mach/hardware.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
+#include "omap4-sar-layout.h"
 
 #ifdef CONFIG_CACHE_L2X0
-void __iomem *l2cache_base;
+static void __iomem *l2cache_base;
+#endif
+
+static void __iomem *sar_ram_base;
+
+#ifdef CONFIG_OMAP4_ERRATA_I688
+/* Used to implement memory barrier on DRAM path */
+#define OMAP4_DRAM_BARRIER_VA                   0xfe600000
+
+void __iomem *dram_sync, *sram_sync;
+
+void omap_bus_sync(void)
+{
+        if (dram_sync && sram_sync) {
+                writel_relaxed(readl_relaxed(dram_sync), dram_sync);
+                writel_relaxed(readl_relaxed(sram_sync), sram_sync);
+                isb();
+        }
+}
+
+static int __init omap_barriers_init(void)
+{
+        struct map_desc dram_io_desc[1];
+        phys_addr_t paddr;
+        u32 size;
+
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        size = ALIGN(PAGE_SIZE, SZ_1M);
+        paddr = memblock_alloc(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
+                return -ENOMEM;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
+        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
+        dram_io_desc[0].length = size;
+        dram_io_desc[0].type = MT_MEMORY_SO;
+        iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
+        dram_sync = (void __iomem *) dram_io_desc[0].virtual;
+        sram_sync = (void __iomem *) OMAP4_SRAM_VA;
+
+        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
+                (long long) paddr, dram_io_desc[0].virtual);
+
+        return 0;
+}
+core_initcall(omap_barriers_init);
 #endif
 
 void __init gic_init_irq(void)
@@ -42,11 +97,18 @@ void __init gic_init_irq(void)
         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
         BUG_ON(!omap_irq_base);
 
+        omap_wakeupgen_init();
+
         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
 
 #ifdef CONFIG_CACHE_L2X0
 
+void __iomem *omap4_get_l2cache_base(void)
+{
+        return l2cache_base;
+}
+
 static void omap4_l2x0_disable(void)
 {
         /* Disable PL310 L2 Cache controller */
@@ -72,7 +134,8 @@ static int __init omap_l2_cache_init(void)
 
         /* Static mapping, never released */
         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
-        BUG_ON(!l2cache_base);
+        if (WARN_ON(!l2cache_base))
+                return -ENOMEM;
 
         /*
          * 16-way associativity, parity disabled
@@ -112,3 +175,30 @@ static int __init omap_l2_cache_init(void)
 }
 early_initcall(omap_l2_cache_init);
 #endif
+
+void __iomem *omap4_get_sar_ram_base(void)
+{
+        return sar_ram_base;
+}
+
+/*
+ * SAR RAM used to save and restore the HW
+ * context in low power modes
+ */
+static int __init omap4_sar_ram_init(void)
+{
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENOMEM;
+
+        /* Static mapping, never released */
+        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
+        if (WARN_ON(!sar_ram_base))
+                return -ENOMEM;
+
+        return 0;
+}
+early_initcall(omap4_sar_ram_init);
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
new file mode 100644
index 00000000000..fe5b545ad44
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -0,0 +1,50 @@
+/*
+ * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+
+/*
+ * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ */
+#define SAR_BANK1_OFFSET                0x0000
+#define SAR_BANK2_OFFSET                0x1000
+#define SAR_BANK3_OFFSET                0x2000
+#define SAR_BANK4_OFFSET                0x3000
+
+/* Scratch pad memory offsets from SAR_BANK1 */
+#define SCU_OFFSET0                             0xd00
+#define SCU_OFFSET1                             0xd04
+#define OMAP_TYPE_OFFSET                        0xd10
+#define L2X0_SAVE_OFFSET0                       0xd14
+#define L2X0_SAVE_OFFSET1                       0xd18
+#define L2X0_AUXCTRL_OFFSET                     0xd1c
+#define L2X0_PREFETCH_CTRL_OFFSET               0xd20
+
+/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
+#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
+#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET           0xa08
+
+#define SAR_BACKUP_STATUS_OFFSET                (SAR_BANK3_OFFSET + 0x500)
+#define SAR_SECURE_RAM_SIZE_OFFSET              (SAR_BANK3_OFFSET + 0x504)
+#define SAR_SECRAM_SAVED_AT_OFFSET              (SAR_BANK3_OFFSET + 0x508)
+
+/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
+#define WAKEUPGENENB_OFFSET_CPU0                (SAR_BANK3_OFFSET + 0x684)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU0         (SAR_BANK3_OFFSET + 0x694)
+#define WAKEUPGENENB_OFFSET_CPU1                (SAR_BANK3_OFFSET + 0x6a4)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU1         (SAR_BANK3_OFFSET + 0x6b4)
+#define AUXCOREBOOT0_OFFSET                     (SAR_BANK3_OFFSET + 0x6c4)
+#define AUXCOREBOOT1_OFFSET                     (SAR_BANK3_OFFSET + 0x6c8)
+#define PTMSYNCREQ_MASK_OFFSET                  (SAR_BANK3_OFFSET + 0x6cc)
+#define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
+#define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
+
+#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 529142aff76..5192cabb40e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -136,6 +136,7 @@
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
 
 #include "common.h"
 #include <plat/cpu.h>
@@ -381,6 +382,51 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
 }
 
 /**
+ * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
+ * @oh: struct omap_hwmod *
+ * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
+ *
+ * Set or clear the I/O pad wakeup flag in the mux entries for the
+ * hwmod @oh.  This function changes the @oh->mux->pads_dynamic array
+ * in memory.  If the hwmod is currently idled, and the new idle
+ * values don't match the previous ones, this function will also
+ * update the SCM PADCTRL registers.  Otherwise, if the hwmod is not
+ * currently idled, this function won't touch the hardware: the new
+ * mux settings are written to the SCM PADCTRL registers when the
+ * hwmod is idled.  No return value.
+ */
+static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
+{
+        struct omap_device_pad *pad;
+        bool change = false;
+        u16 prev_idle;
+        int j;
+
+        if (!oh->mux || !oh->mux->enabled)
+                return;
+
+        for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
+                pad = oh->mux->pads_dynamic[j];
+
+                if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
+                        continue;
+
+                prev_idle = pad->idle;
+
+                if (set_wake)
+                        pad->idle |= OMAP_WAKEUP_EN;
+                else
+                        pad->idle &= ~OMAP_WAKEUP_EN;
+
+                if (prev_idle != pad->idle)
+                        change = true;
+        }
+
+        if (change && oh->_state == _HWMOD_STATE_IDLE)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+}
+
+/**
  * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
  * @oh: struct omap_hwmod *
  *
@@ -706,27 +752,65 @@ static void _enable_module(struct omap_hwmod *oh)
 }
 
 /**
- * _disable_module - enable CLKCTRL modulemode on OMAP4
+ * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _omap4_wait_target_disable(struct omap_hwmod *oh)
+{
+        if (!cpu_is_omap44xx())
+                return 0;
+
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+                                             oh->clkdm->cm_inst,
+                                             oh->clkdm->clkdm_offs,
+                                             oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
  * @oh: struct omap_hwmod *
  *
  * Disable the PRCM module mode related to the hwmod @oh.
- * No return value.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
  */
-static void _disable_module(struct omap_hwmod *oh)
+static int _omap4_disable_module(struct omap_hwmod *oh)
 {
+        int v;
+
         /* The module mode does not exist prior OMAP4 */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return;
+        if (!cpu_is_omap44xx())
+                return -EINVAL;
 
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-                return;
+                return -EINVAL;
 
-        pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
 
         omap4_cminst_module_disable(oh->clkdm->prcm_partition,
                                     oh->clkdm->cm_inst,
                                     oh->clkdm->clkdm_offs,
                                     oh->prcm.omap4.clkctrl_offs);
+
+        v = _omap4_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+
+        return 0;
 }
 
 /**
@@ -1153,36 +1237,6 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
- * _wait_target_disable - wait for a module to be disabled
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to enter slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully enters
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_idle() function.
- */
-static int _wait_target_disable(struct omap_hwmod *oh)
-{
-        /* TODO: For now just handle OMAP4+ */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return 0;
-
-        if (!oh)
-                return -EINVAL;
-
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
-                return 0;
-
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-
-        return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
-                                             oh->clkdm->cm_inst,
-                                             oh->clkdm->clkdm_offs,
-                                             oh->prcm.omap4.clkctrl_offs);
-}
-
-/**
  * _lookup_hardreset - fill register bit info for this hwmod/reset line
  * @oh: struct omap_hwmod *
  * @name: name of the reset line in the context of this hwmod
@@ -1441,6 +1495,25 @@ static int _enable(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
+        /*
+         * hwmods with HWMOD_INIT_NO_IDLE flag set are left
+         * in enabled state at init.
+         * Now that someone is really trying to enable them,
+         * just ensure that the hwmod mux is set.
+         */
+        if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
+                /*
+                 * If the caller has mux data populated, do the mux'ing
+                 * which wouldn't have been done as part of the _enable()
+                 * done during setup.
+                 */
+                if (oh->mux)
+                        omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+
+                oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
+                return 0;
+        }
+
         if (oh->_state != _HWMOD_STATE_INITIALIZED &&
             oh->_state != _HWMOD_STATE_IDLE &&
             oh->_state != _HWMOD_STATE_DISABLED) {
@@ -1524,8 +1597,6 @@ static int _enable(struct omap_hwmod *oh)
  */
 static int _idle(struct omap_hwmod *oh)
 {
-        int ret;
-
         pr_debug("omap_hwmod: %s: idling\n", oh->name);
 
         if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1537,11 +1608,9 @@ static int _idle(struct omap_hwmod *oh)
         if (oh->class->sysc)
                 _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
-        _disable_module(oh);
-        ret = _wait_target_disable(oh);
-        if (ret)
-                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                        oh->name);
+
+        _omap4_disable_module(oh);
+
         /*
          * The module must be in idle mode before disabling any parents
          * clocks. Otherwise, the parent clock might be disabled before
@@ -1642,11 +1711,7 @@ static int _shutdown(struct omap_hwmod *oh)
         if (oh->_state == _HWMOD_STATE_ENABLED) {
                 _del_initiator_dep(oh, mpu_oh);
                 /* XXX what about the other system initiators here? dma, dsp */
-                _disable_module(oh);
-                ret = _wait_target_disable(oh);
-                if (ret)
-                        pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                                oh->name);
+                _omap4_disable_module(oh);
                 _disable_clocks(oh);
                 if (oh->clkdm)
                         clkdm_hwmod_disable(oh->clkdm, oh);
@@ -1744,8 +1809,10 @@ static int _setup(struct omap_hwmod *oh, void *data)
          * it should be set by the core code as a runtime flag during startup
          */
         if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
-            (postsetup_state == _HWMOD_STATE_IDLE))
+            (postsetup_state == _HWMOD_STATE_IDLE)) {
+                oh->_int_flags |= _HWMOD_SKIP_ENABLE;
                 postsetup_state = _HWMOD_STATE_ENABLED;
+        }
 
         if (postsetup_state == _HWMOD_STATE_IDLE)
                 _idle(oh);
@@ -2416,6 +2483,7 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
         v = oh->_sysc_cache;
         _enable_wakeup(oh, &v);
         _write_sysconfig(v, oh);
+        _set_idle_ioring_wakeup(oh, true);
         spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
@@ -2446,6 +2514,7 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
         v = oh->_sysc_cache;
         _disable_wakeup(oh, &v);
         _write_sysconfig(v, oh);
+        _set_idle_ioring_wakeup(oh, false);
         spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
@@ -2662,3 +2731,57 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
 
         return 0;
 }
+
+/**
+ * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
+ * @oh: struct omap_hwmod * containing hwmod mux entries
+ * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
+ * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
+ *
+ * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
+ * entry number @pad_idx for the hwmod @oh, trigger the interrupt
+ * service routine for the hwmod's mpu_irqs array index @irq_idx.  If
+ * this function is not called for a given pad_idx, then the ISR
+ * associated with @oh's first MPU IRQ will be triggered when an I/O
+ * pad wakeup occurs on that pad.  Note that @pad_idx is the index of
+ * the _dynamic or wakeup_ entry: if there are other entries not
+ * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
+ * entries are NOT COUNTED in the dynamic pad index.  This function
+ * must be called separately for each pad that requires its interrupt
+ * to be re-routed this way.  Returns -EINVAL if there is an argument
+ * problem or if @oh does not have hwmod mux entries or MPU IRQs;
+ * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
+ *
+ * XXX This function interface is fragile.  Rather than using array
+ * indexes, which are subject to unpredictable change, it should be
+ * using hwmod IRQ names, and some other stable key for the hwmod mux
+ * pad records.
+ */
+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
+{
+        int nr_irqs;
+
+        might_sleep();
+
+        if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
+            pad_idx >= oh->mux->nr_pads_dynamic)
+                return -EINVAL;
+
+        /* Check the number of available mpu_irqs */
+        for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
+                ;
+
+        if (irq_idx >= nr_irqs)
+                return -EINVAL;
+
+        if (!oh->mux->irqs) {
+                /* XXX What frees this? */
+                oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
+                        GFP_KERNEL);
+                if (!oh->mux->irqs)
+                        return -ENOMEM;
+        }
+        oh->mux->irqs[pad_idx] = irq_idx;
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index eef43e2e163..5324e8d93bc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -84,6 +84,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -164,6 +166,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
 static struct omap_hwmod omap3xxx_uart2_hwmod;
 static struct omap_hwmod omap3xxx_uart3_hwmod;
 static struct omap_hwmod omap3xxx_uart4_hwmod;
+static struct omap_hwmod am35xx_uart4_hwmod;
 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 
 /* l3_core -> usbhsotg interface */
@@ -299,6 +302,23 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* AM35xx: L4 CORE -> UART4 interface */
+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_AM35XX_BASE,
+                .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = am35xx_uart4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* L4 CORE -> I2C1 interface */
 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
         .master         = &omap3xxx_l4_core_hwmod,
@@ -1162,6 +1182,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .clockact       = CLOCKACT_TEST_ICLK,
         .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
@@ -1309,6 +1330,39 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
         .class          = &omap2_uart_class,
 };
 
+static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
+        { .irq = INT_35XX_UART4_IRQ, },
+};
+
+static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
+        { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
+        { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+};
+
+static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
+        &am35xx_l4_core__uart4,
+};
+
+static struct omap_hwmod am35xx_uart4_hwmod = {
+        .name           = "uart4",
+        .mpu_irqs       = am35xx_uart4_mpu_irqs,
+        .sdma_reqs      = am35xx_uart4_sdma_reqs,
+        .main_clk       = "uart4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
+                },
+        },
+        .slaves         = am35xx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(am35xx_uart4_slaves),
+        .class          = &omap2_uart_class,
+};
+
+
 static struct omap_hwmod_class i2c_class = {
         .name   = "i2c",
         .sysc   = &i2c_sysc,
@@ -1636,7 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
         .name           = "i2c1",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap2_i2c1_mpu_irqs,
         .sdma_reqs      = omap2_i2c1_sdma_reqs,
         .main_clk       = "i2c1_fck",
@@ -1670,7 +1724,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
         .name           = "i2c2",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap2_i2c2_mpu_irqs,
         .sdma_reqs      = omap2_i2c2_sdma_reqs,
         .main_clk       = "i2c2_fck",
@@ -1715,7 +1769,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
         .name           = "i2c3",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = i2c3_mpu_irqs,
         .sdma_reqs      = i2c3_sdma_reqs,
         .main_clk       = "i2c3_fck",
@@ -3072,7 +3126,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
 
-static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+/* See 35xx errata 2.1.1.128 in SPRZ278F */
+static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
+        .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
+                  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
+};
+
+static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
+        .name           = "mmc1",
+        .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
+        .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
+        .opt_clks       = omap34xx_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_pre_es3_dev_attr,
+        .slaves         = omap3xxx_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
+        .class          = &omap34xx_mmc_class,
+};
+
+static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
         .name           = "mmc1",
         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
@@ -3115,7 +3197,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
         &omap3xxx_l4_core__mmc2,
 };
 
-static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+/* See 35xx errata 2.1.1.128 in SPRZ278F */
+static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
+        .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
+};
+
+static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
+        .name           = "mmc2",
+        .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
+        .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
+        .opt_clks       = omap34xx_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc2_pre_es3_dev_attr,
+        .slaves         = omap3xxx_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
+        .class          = &omap34xx_mmc_class,
+};
+
+static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
         .name           = "mmc2",
         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
@@ -3177,13 +3286,223 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
         .class          = &omap34xx_mmc_class,
 };
 
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
+        .master         = &omap3xxx_usb_host_hs_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
+        .name = "usb_host_hs",
+        .sysc = &omap3xxx_usb_host_hs_sysc,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
+        &omap3xxx_usb_host_hs__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
+        {
+                .name           = "uhh",
+                .pa_start       = 0x48064000,
+                .pa_end         = 0x480643ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "ohci",
+                .pa_start       = 0x48064400,
+                .pa_end         = 0x480647ff,
+        },
+        {
+                .name           = "ehci",
+                .pa_start       = 0x48064800,
+                .pa_end         = 0x48064cff,
+        },
+        {}
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usb_host_hs_hwmod,
+        .clk            = "usbhost_ick",
+        .addr           = omap3xxx_usb_host_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
+        &omap3xxx_l4_core__usb_host_hs,
+};
+
+static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
+          { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
+};
+
+static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
+        { .name = "ohci-irq", .irq = 76 },
+        { .name = "ehci-irq", .irq = 77 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap3xxx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
+        .main_clk       = "usbhost_48m_fck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430ES2_USBHOST_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
+                        .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
+                },
+        },
+        .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
+        .slaves         = omap3xxx_usb_host_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
+        .masters        = omap3xxx_usb_host_hs_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
+
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
+};
+
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
+        .name = "usb_tll_hs",
+        .sysc = &omap3xxx_usb_tll_hs_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
+        { .name = "tll-irq", .irq = 78 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
+        {
+                .name           = "tll",
+                .pa_start       = 0x48062000,
+                .pa_end         = 0x48062fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {}
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usb_tll_hs_hwmod,
+        .clk            = "usbtll_ick",
+        .addr           = omap3xxx_usb_tll_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
+        &omap3xxx_l4_core__usb_tll_hs,
+};
+
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap3xxx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
+        .main_clk       = "usbtll_fck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+                        .idlest_reg_id = 3,
+                        .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_usb_tll_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
         &omap3xxx_l4_per_hwmod,
         &omap3xxx_l4_wkup_hwmod,
-        &omap3xxx_mmc1_hwmod,
-        &omap3xxx_mmc2_hwmod,
         &omap3xxx_mmc3_hwmod,
         &omap3xxx_mpu_hwmod,
 
@@ -3198,12 +3517,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_timer9_hwmod,
         &omap3xxx_timer10_hwmod,
         &omap3xxx_timer11_hwmod,
-        &omap3xxx_timer12_hwmod,
 
         &omap3xxx_wd_timer2_hwmod,
         &omap3xxx_uart1_hwmod,
         &omap3xxx_uart2_hwmod,
         &omap3xxx_uart3_hwmod,
+
         /* dss class */
         &omap3xxx_dss_dispc_hwmod,
         &omap3xxx_dss_dsi1_hwmod,
@@ -3245,6 +3564,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         NULL,
 };
 
+/* GP-only hwmods */
+static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
+        &omap3xxx_timer12_hwmod,
+        NULL
+};
+
 /* 3430ES1-only hwmods */
 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
         &omap3430es1_dss_core_hwmod,
@@ -3255,6 +3580,22 @@ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
         &omap3xxx_dss_core_hwmod,
         &omap3xxx_usbhsotg_hwmod,
+        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usb_tll_hs_hwmod,
+        NULL
+};
+
+/* <= 3430ES3-only hwmods */
+static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
+        &omap3xxx_pre_es3_mmc1_hwmod,
+        &omap3xxx_pre_es3_mmc2_hwmod,
+        NULL
+};
+
+/* 3430ES3+-only hwmods */
+static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
+        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_es3plus_mmc2_hwmod,
         NULL
 };
 
@@ -3276,12 +3617,21 @@ static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
         &omap36xx_sr2_hwmod,
         &omap3xxx_usbhsotg_hwmod,
         &omap3xxx_mailbox_hwmod,
+        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usb_tll_hs_hwmod,
+        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_es3plus_mmc2_hwmod,
         NULL
 };
 
 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
         &omap3xxx_dss_core_hwmod, /* XXX ??? */
         &am35xx_usbhsotg_hwmod,
+        &am35xx_uart4_hwmod,
+        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usb_tll_hs_hwmod,
+        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_es3plus_mmc2_hwmod,
         NULL
 };
 
@@ -3296,6 +3646,13 @@ int __init omap3xxx_hwmod_init(void)
         if (r < 0)
                 return r;
 
+        /* Register GP-only hwmods. */
+        if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
+                r = omap_hwmod_register(omap3xxx_gp_hwmods);
+                if (r < 0)
+                        return r;
+        }
+
         rev = omap_rev();
 
         /*
@@ -3334,6 +3691,21 @@ int __init omap3xxx_hwmod_init(void)
                 h = omap3430es2plus_hwmods;
         };
 
+        if (h) {
+                r = omap_hwmod_register(h);
+                if (r < 0)
+                        return r;
+        }
+
+        h = NULL;
+        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
+            rev == OMAP3430_REV_ES2_1) {
+                h = omap3430_pre_es3_hwmods;
+        } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
+                   rev == OMAP3430_REV_ES3_1_2) {
+                h = omap3430_es3plus_hwmods;
+        };
+
         if (h)
                 r = omap_hwmod_register(h);
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index daaf165af69..f9f15108176 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -70,6 +70,8 @@ static struct omap_hwmod omap44xx_mmc2_hwmod;
 static struct omap_hwmod omap44xx_mpu_hwmod;
 static struct omap_hwmod omap44xx_mpu_private_hwmod;
 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
 
 /*
  * Interconnects omap_hwmod structures
@@ -2246,6 +2248,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
                            SIDLE_SMART_WKUP),
+        .clockact       = CLOCKACT_TEST_ICLK,
         .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
@@ -2300,7 +2303,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
         .name           = "i2c1",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c1_irqs,
         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
         .main_clk       = "i2c1_fck",
@@ -2356,7 +2359,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
         .name           = "i2c2",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c2_irqs,
         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
         .main_clk       = "i2c2_fck",
@@ -2412,7 +2415,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
         .name           = "i2c3",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c3_irqs,
         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
         .main_clk       = "i2c3_fck",
@@ -2468,7 +2471,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
         .name           = "i2c4",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .mpu_irqs       = omap44xx_i2c4_irqs,
         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
         .main_clk       = "i2c4_fck",
@@ -5276,6 +5279,207 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
 };
 
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_host_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
+        .name = "usb_host_hs",
+        .sysc = &omap44xx_usb_host_hs_sysc,
+};
+
+static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
+        &omap44xx_usb_host_hs__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
+        {
+                .name           = "uhh",
+                .pa_start       = 0x4a064000,
+                .pa_end         = 0x4a0647ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "ohci",
+                .pa_start       = 0x4a064800,
+                .pa_end         = 0x4a064bff,
+        },
+        {
+                .name           = "ehci",
+                .pa_start       = 0x4a064c00,
+                .pa_end         = 0x4a064fff,
+        },
+        {}
+};
+
+static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
+        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
+        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_host_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_host_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
+        &omap44xx_l4_cfg__usb_host_hs,
+};
+
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap44xx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "usb_host_hs_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
+        .slaves         = omap44xx_usb_host_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
+        .masters        = omap44xx_usb_host_hs_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
+
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
+};
+
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
+        .name = "usb_tll_hs",
+        .sysc = &omap44xx_usb_tll_hs_sysc,
+};
+
+static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
+        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
+        {
+                .name           = "tll",
+                .pa_start       = 0x4a062000,
+                .pa_end         = 0x4a063fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {}
+};
+
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_tll_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_tll_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
+        &omap44xx_l4_cfg__usb_tll_hs,
+};
+
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap44xx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "usb_tll_hs_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
+        .slaves         = omap44xx_usb_tll_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
         /* dmm class */
@@ -5415,13 +5619,16 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
         &omap44xx_uart3_hwmod,
         &omap44xx_uart4_hwmod,
 
+        /* usb host class */
+        &omap44xx_usb_host_hs_hwmod,
+        &omap44xx_usb_tll_hs_hwmod,
+
         /* usb_otg_hs class */
         &omap44xx_usb_otg_hs_hwmod,
 
         /* wd_timer class */
         &omap44xx_wd_timer2_hwmod,
         &omap44xx_wd_timer3_hwmod,
-
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 58775e3c847..4c90477e6f8 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -260,3 +260,38 @@ void am35x_set_mode(u8 musb_mode)
 
         omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 }
+
+void ti81xx_musb_phy_power(u8 on)
+{
+        void __iomem *scm_base = NULL;
+        u32 usbphycfg;
+
+        scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
+        if (!scm_base) {
+                pr_err("system control module ioremap failed\n");
+                return;
+        }
+
+        usbphycfg = __raw_readl(scm_base + USBCTRL0);
+
+        if (on) {
+                if (cpu_is_ti816x()) {
+                        usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
+                        usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
+                } else if (cpu_is_ti814x()) {
+                        usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
+                                | USBPHY_DPINPUT | USBPHY_DMINPUT);
+                        usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
+                                | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
+                }
+        } else {
+                if (cpu_is_ti816x())
+                        usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
+                else if (cpu_is_ti814x())
+                        usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
+
+        }
+        __raw_writel(usbphycfg, scm_base + USBCTRL0);
+
+        iounmap(scm_base);
+}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66a92c..8fae534eb15 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
+        unsigned short flags;
 };
 
 
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 4e166add2f3..b737b11e449 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -21,6 +21,7 @@ extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
+extern int omap4_idle_init(void);
 
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index ef8595c8029..b8822f8b289 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -30,7 +30,6 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
-#include <linux/console.h>
 
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -127,27 +126,11 @@ static void omap2_enter_full_retention(void)
         if (omap_irq_pending())
                 goto no_sleep;
 
-        /* Block console output in case it is on one of the OMAP UARTs */
-        if (!is_suspending())
-                if (!console_trylock())
-                        goto no_sleep;
-
-        omap_uart_prepare_idle(0);
-        omap_uart_prepare_idle(1);
-        omap_uart_prepare_idle(2);
-
         /* Jump to SRAM suspend code */
         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
                            OMAP_SDRC_REGADDR(SDRC_POWER));
 
-        omap_uart_resume_idle(2);
-        omap_uart_resume_idle(1);
-        omap_uart_resume_idle(0);
-
-        if (!is_suspending())
-                console_unlock();
-
 no_sleep:
         omap2_gpio_resume_after_idle();
 
@@ -239,8 +222,6 @@ static int omap2_can_sleep(void)
 {
         if (omap2_fclks_active())
                 return 0;
-        if (!omap_uart_can_sleep())
-                return 0;
         if (osc_ck->usecount > 1)
                 return 0;
         if (omap_dma_running())
@@ -291,7 +272,6 @@ static int omap2_pm_suspend(void)
         mir1 = omap_readl(0x480fe0a4);
         omap_writel(1 << 5, 0x480fe0ac);
 
-        omap_uart_prepare_suspend();
         omap2_enter_full_retention();
 
         omap_writel(mir1, 0x480fe0a4);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fa637dfdda5..fc698757892 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
-#include <linux/console.h>
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
@@ -36,7 +35,6 @@
 #include <plat/sram.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
@@ -54,15 +52,6 @@
 
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
-static inline bool is_suspending(void)
-{
-        return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
-}
-#else
-static inline bool is_suspending(void)
-{
-        return false;
-}
 #endif
 
 /* pm34xx errata defined in pm.h */
@@ -195,7 +184,7 @@ static void omap3_save_secure_ram_context(void)
  * that any peripheral wake-up events occurring while attempting to
  * clear the PM_WKST_x are detected and cleared.
  */
-static int prcm_clear_mod_irqs(s16 module, u8 regs)
+static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 {
         u32 wkst, fclk, iclk, clken;
         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -207,6 +196,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
 
         wkst = omap2_prm_read_mod_reg(module, wkst_off);
         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
+        wkst &= ~ignore_bits;
         if (wkst) {
                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -222,6 +212,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
+                        wkst &= ~ignore_bits;
                         c++;
                 }
                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -231,76 +222,35 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
         return c;
 }
 
-static int _prcm_int_handle_wakeup(void)
+static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
         int c;
 
-        c = prcm_clear_mod_irqs(WKUP_MOD, 1);
-        c += prcm_clear_mod_irqs(CORE_MOD, 1);
-        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += prcm_clear_mod_irqs(CORE_MOD, 3);
-                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
-        }
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
+                ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
 
-        return c;
+        return c ? IRQ_HANDLED : IRQ_NONE;
 }
 
-/*
- * PRCM Interrupt Handler
- *
- * The PRM_IRQSTATUS_MPU register indicates if there are any pending
- * interrupts from the PRCM for the MPU. These bits must be cleared in
- * order to clear the PRCM interrupt. The PRCM interrupt handler is
- * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
- * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
- * register indicates that a wake-up event is pending for the MPU and
- * this bit can only be cleared if the all the wake-up events latched
- * in the various PM_WKST_x registers have been cleared. The interrupt
- * handler is implemented using a do-while loop so that if a wake-up
- * event occurred during the processing of the prcm interrupt handler
- * (setting a bit in the corresponding PM_WKST_x register and thus
- * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
- * this would be handled.
- */
-static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 {
-        u32 irqenable_mpu, irqstatus_mpu;
-        int c = 0;
-
-        irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        irqstatus_mpu &= irqenable_mpu;
-
-        do {
-                if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
-                                     OMAP3430_IO_ST_MASK)) {
-                        c = _prcm_int_handle_wakeup();
-
-                        /*
-                         * Is the MPU PRCM interrupt handler racing with the
-                         * IVA2 PRCM interrupt handler ?
-                         */
-                        WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
-                             "but no wakeup sources are marked\n");
-                } else {
-                        /* XXX we need to expand our PRCM interrupt handler */
-                        WARN(1, "prcm: WARNING: PRCM interrupt received, but "
-                             "no code to handle it (%08x)\n", irqstatus_mpu);
-                }
-
-                omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
-                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-
-                irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-                irqstatus_mpu &= irqenable_mpu;
+        int c;
 
-        } while (irqstatus_mpu);
+        /*
+         * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
+         * these are handled in a separate handler to avoid acking
+         * IO events before parsing in mux code
+         */
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
+                OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
+        c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
+        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
+                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+        }
 
-        return IRQ_HANDLED;
+        return c ? IRQ_HANDLED : IRQ_NONE;
 }
 
 static void omap34xx_save_context(u32 *save)
@@ -376,20 +326,11 @@ void omap_sram_idle(void)
                         omap3_enable_io_chain();
         }
 
-        /* Block console output in case it is on one of the OMAP UARTs */
-        if (!is_suspending())
-                if (per_next_state < PWRDM_POWER_ON ||
-                    core_next_state < PWRDM_POWER_ON)
-                        if (!console_trylock())
-                                goto console_still_active;
-
         pwrdm_pre_transition();
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
-                omap_uart_prepare_idle(2);
-                omap_uart_prepare_idle(3);
                 omap2_gpio_prepare_for_idle(per_going_off);
                 if (per_next_state == PWRDM_POWER_OFF)
                                 omap3_per_save_context();
@@ -397,8 +338,6 @@ void omap_sram_idle(void)
 
         /* CORE */
         if (core_next_state < PWRDM_POWER_ON) {
-                omap_uart_prepare_idle(0);
-                omap_uart_prepare_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF) {
                         omap3_core_save_context();
                         omap3_cm_save_context();
@@ -447,8 +386,6 @@ void omap_sram_idle(void)
                         omap3_sram_restore_context();
                         omap2_sms_restore_context();
                 }
-                omap_uart_resume_idle(0);
-                omap_uart_resume_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF)
                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
@@ -464,14 +401,8 @@ void omap_sram_idle(void)
                 omap2_gpio_resume_after_idle();
                 if (per_prev_state == PWRDM_POWER_OFF)
                         omap3_per_restore_context();
-                omap_uart_resume_idle(2);
-                omap_uart_resume_idle(3);
         }
 
-        if (!is_suspending())
-                console_unlock();
-
-console_still_active:
         /* Disable IO-PAD and IO-CHAIN wakeup */
         if (omap3_has_io_wakeup() &&
             (per_next_state < PWRDM_POWER_ON ||
@@ -485,21 +416,11 @@ console_still_active:
         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
-int omap3_can_sleep(void)
-{
-        if (!omap_uart_can_sleep())
-                return 0;
-        return 1;
-}
-
 static void omap3_pm_idle(void)
 {
         local_irq_disable();
         local_fiq_disable();
 
-        if (!omap3_can_sleep())
-                goto out;
-
         if (omap_irq_pending() || need_resched())
                 goto out;
 
@@ -533,7 +454,6 @@ static int omap3_pm_suspend(void)
                         goto restore;
         }
 
-        omap_uart_prepare_suspend();
         omap3_intc_suspend();
 
         omap_sram_idle();
@@ -580,22 +500,27 @@ static int omap3_pm_begin(suspend_state_t state)
 {
         disable_hlt();
         suspend_state = state;
-        omap_uart_enable_irqs(0);
+        omap_prcm_irq_prepare();
         return 0;
 }
 
 static void omap3_pm_end(void)
 {
         suspend_state = PM_SUSPEND_ON;
-        omap_uart_enable_irqs(1);
         enable_hlt();
         return;
 }
 
+static void omap3_pm_finish(void)
+{
+        omap_prcm_irq_complete();
+}
+
 static const struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap3_pm_begin,
         .end            = omap3_pm_end,
         .enter          = omap3_pm_enter,
+        .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -701,10 +626,6 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_GRPSEL_GPT1_MASK |
                           OMAP3430_GRPSEL_GPT12_MASK,
                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
-        /* For some reason IO doesn't generate wakeup event even if
-         * it is selected to mpu wakeup goup */
-        omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
-                          OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
         /* Enable PM_WKEN to support DSS LPR */
         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
@@ -881,12 +802,21 @@ static int __init omap3_pm_init(void)
          * supervised mode for powerdomains */
         prcm_setup_regs();
 
-        ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
-                          (irq_handler_t)prcm_interrupt_handler,
-                          IRQF_DISABLED, "prcm", NULL);
+        ret = request_irq(omap_prcm_event_to_irq("wkup"),
+                _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
+
+        if (ret) {
+                pr_err("pm: Failed to request pm_wkup irq\n");
+                goto err1;
+        }
+
+        /* IO interrupt is shared with mux code */
+        ret = request_irq(omap_prcm_event_to_irq("io"),
+                _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
+                omap3_pm_init);
+
         if (ret) {
-                printk(KERN_ERR "request_irq failed to register for 0x%x\n",
-                       INT_34XX_PRCM_MPU_IRQ);
+                pr_err("pm: Failed to request pm_io irq\n");
                 goto err1;
         }
 
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 8edb015f561..c264ef7219c 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,8 +1,9 @@
 /*
  * OMAP4 Power Management Routines
  *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Rajendra Nayak <rnayak@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,13 +18,16 @@
 #include <linux/slab.h>
 
 #include "common.h"
+#include "clockdomain.h"
 #include "powerdomain.h"
+#include "pm.h"
 
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
 #ifdef CONFIG_SUSPEND
         u32 saved_state;
+        u32 saved_logic_state;
 #endif
         struct list_head node;
 };
@@ -33,7 +37,50 @@ static LIST_HEAD(pwrst_list);
 #ifdef CONFIG_SUSPEND
 static int omap4_pm_suspend(void)
 {
-        do_wfi();
+        struct power_state *pwrst;
+        int state, ret = 0;
+        u32 cpu_id = smp_processor_id();
+
+        /* Save current powerdomain state */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+                pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
+        }
+
+        /* Set targeted power domain states by suspend */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+                pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
+        }
+
+        /*
+         * For MPUSS to hit power domain retention(CSWR or OSWR),
+         * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
+         * since CPU power domain CSWR is not supported by hardware
+         * Only master CPU follows suspend path. All other CPUs follow
+         * CPU hotplug path in system wide suspend. On OMAP4, CPU power
+         * domain CSWR is not supported by hardware.
+         * More details can be found in OMAP4430 TRM section 4.3.4.2.
+         */
+        omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+
+        /* Restore next powerdomain state */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+                if (state > pwrst->next_state) {
+                        pr_info("Powerdomain (%s) didn't enter "
+                               "target state %d\n",
+                               pwrst->pwrdm->name, pwrst->next_state);
+                        ret = -1;
+                }
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
+        }
+        if (ret)
+                pr_crit("Could not enter target state in pm_suspend\n");
+        else
+                pr_info("Successfully put all powerdomains to target state\n");
+
         return 0;
 }
 
@@ -73,6 +120,22 @@ static const struct platform_suspend_ops omap_pm_ops = {
 };
 #endif /* CONFIG_SUSPEND */
 
+/*
+ * Enable hardware supervised mode for all clockdomains if it's
+ * supported. Initiate sleep transition for other clockdomains, if
+ * they are not used
+ */
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+{
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                        atomic_read(&clkdm->usecount) == 0)
+                clkdm_sleep(clkdm);
+        return 0;
+}
+
+
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
         struct power_state *pwrst;
@@ -80,14 +143,48 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
         if (!pwrdm->pwrsts)
                 return 0;
 
+        /*
+         * Skip CPU0 and CPU1 power domains. CPU1 is programmed
+         * through hotplug path and CPU0 explicitly programmed
+         * further down in the code path
+         */
+        if (!strncmp(pwrdm->name, "cpu", 3))
+                return 0;
+
+        /*
+         * FIXME: Remove this check when core retention is supported
+         * Only MPUSS power domain is added in the list.
+         */
+        if (strcmp(pwrdm->name, "mpu_pwrdm"))
+                return 0;
+
         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
         if (!pwrst)
                 return -ENOMEM;
+
         pwrst->pwrdm = pwrdm;
-        pwrst->next_state = PWRDM_POWER_ON;
+        pwrst->next_state = PWRDM_POWER_RET;
         list_add(&pwrst->node, &pwrst_list);
 
-        return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
+        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+}
+
+/**
+ * omap_default_idle - OMAP4 default ilde routine.'
+ *
+ * Implements OMAP4 memory, IO ordering requirements which can't be addressed
+ * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
+ * by secondary CPU with CONFIG_CPUIDLE.
+ */
+static void omap_default_idle(void)
+{
+        local_irq_disable();
+        local_fiq_disable();
+
+        omap_do_wfi();
+
+        local_fiq_enable();
+        local_irq_enable();
 }
 
 /**
@@ -99,10 +196,17 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 static int __init omap4_pm_init(void)
 {
         int ret;
+        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
 
         if (!cpu_is_omap44xx())
                 return -ENODEV;
 
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+
         pr_err("Power Management for TI OMAP4.\n");
 
         ret = pwrdm_for_each(pwrdms_setup, NULL);
@@ -111,10 +215,51 @@ static int __init omap4_pm_init(void)
                 goto err2;
         }
 
+        /*
+         * The dynamic dependency between MPUSS -> MEMIF and
+         * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
+         * expected. The hardware recommendation is to enable static
+         * dependencies for these to avoid system lock ups or random crashes.
+         */
+        mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
+        emif_clkdm = clkdm_lookup("l3_emif_clkdm");
+        l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
+        l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
+        l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
+        ducati_clkdm = clkdm_lookup("ducati_clkdm");
+        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+                (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
+                goto err2;
+
+        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
+        ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
+        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
+        if (ret) {
+                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
+                                "wakeup dependency\n");
+                goto err2;
+        }
+
+        ret = omap4_mpuss_init();
+        if (ret) {
+                pr_err("Failed to initialise OMAP4 MPUSS\n");
+                goto err2;
+        }
+
+        (void) clkdm_for_each(clkdms_setup, NULL);
+
 #ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
 #endif /* CONFIG_SUSPEND */
 
+        /* Overwrite the default arch_idle() */
+        pm_idle = omap_default_idle;
+
+        omap4_idle_init();
+
 err2:
         return ret;
 }
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0363dcb0ef9..5aa5435e3ff 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -4,7 +4,7 @@
 /*
  * OMAP2/3 PRCM base and module definitions
  *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -201,6 +201,8 @@
 #define OMAP3430_EN_MMC2_SHIFT                          25
 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
 #define OMAP3430_EN_MMC1_SHIFT                          24
+#define OMAP3430_EN_UART4_MASK                          (1 << 23)
+#define OMAP3430_EN_UART4_SHIFT                         23
 #define OMAP3430_EN_MCSPI4_MASK                         (1 << 21)
 #define OMAP3430_EN_MCSPI4_SHIFT                        21
 #define OMAP3430_EN_MCSPI3_MASK                         (1 << 20)
@@ -408,6 +410,79 @@
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
+
+/**
+ * struct omap_prcm_irq - describes a PRCM interrupt bit
+ * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
+ * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
+ * @priority: should this interrupt be handled before @priority=false IRQs?
+ *
+ * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
+ * On systems with multiple PRM MPU IRQ registers, the bitfields read from
+ * the registers are concatenated, so @offset could be > 31 on these systems -
+ * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
+ * have @priority set to true.
+ */
+struct omap_prcm_irq {
+        const char *name;
+        unsigned int offset;
+        bool priority;
+};
+
+/**
+ * struct omap_prcm_irq_setup - PRCM interrupt controller details
+ * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
+ * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
+ * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
+ * @nr_irqs: number of entries in the @irqs array
+ * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
+ * @irq: MPU IRQ asserted when a PRCM interrupt arrives
+ * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
+ * @ocp_barrier: fn ptr to force buffered PRM writes to complete
+ * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
+ * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @saved_mask: IRQENABLE regs are saved here during suspend
+ * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
+ * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
+ * @suspended: set to true after Linux suspend code has called our ->prepare()
+ * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
+ *
+ * @saved_mask, @priority_mask, @base_irq, @suspended, and
+ * @suspend_save_flag are populated dynamically, and are not to be
+ * specified in static initializers.
+ */
+struct omap_prcm_irq_setup {
+        u16 ack;
+        u16 mask;
+        u8 nr_regs;
+        u8 nr_irqs;
+        const struct omap_prcm_irq *irqs;
+        int irq;
+        void (*read_pending_irqs)(unsigned long *events);
+        void (*ocp_barrier)(void);
+        void (*save_and_clear_irqen)(u32 *saved_mask);
+        void (*restore_irqen)(u32 *saved_mask);
+        u32 *saved_mask;
+        u32 *priority_mask;
+        int base_irq;
+        bool suspended;
+        bool suspend_save_flag;
+};
+
+/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
+#define OMAP_PRCM_IRQ(_name, _offset, _priority) {      \
+        .name = _name,                                  \
+        .offset = _offset,                              \
+        .priority = _priority                           \
+        }
+
+extern void omap_prcm_irq_cleanup(void);
+extern int omap_prcm_register_chain_handler(
+        struct omap_prcm_irq_setup *irq_setup);
+extern int omap_prcm_event_to_irq(const char *event);
+extern void omap_prcm_irq_prepare(void);
+extern void omap_prcm_irq_complete(void);
+
 # endif
 
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9a08ba39732..c1c4d86a79a 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -1,7 +1,7 @@
 /*
  * OMAP2/3 PRM module functions
  *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Copyright (C) 2010 Nokia Corporation
  * Benoît Cousson
  * Paul Walmsley
@@ -27,6 +27,24 @@
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-34xx.h"
 
+static const struct omap_prcm_irq omap3_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+
+static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
+        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 1,
+        .irqs                   = omap3_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
+        .irq                    = INT_34XX_PRCM_MPU_IRQ,
+        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap3xxx_prm_restore_irqen,
+};
+
 u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
 {
         return __raw_readl(prm_base + module + idx);
@@ -212,3 +230,80 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 {
         return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 }
+
+/**
+ * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to a u32, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the u32 pointed to by @events.
+ * No return value.
+ */
+void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+{
+        u32 mask, st;
+
+        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
+        events[0] = mask & st;
+}
+
+/**
+ * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap3xxx_prm_ocp_barrier(void)
+{
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+
+/**
+ * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
+ * must be allocated by the caller.  Intended to be used in the PRM
+ * interrupt handler suspend callback.  The OCP barrier is needed to
+ * ensure the write to disable PRM interrupts reaches the PRM before
+ * returning; otherwise, spurious interrupts might occur.  No return
+ * value.
+ */
+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+
+/**
+ * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
+ * to be used in the PRM interrupt handler resume callback to restore
+ * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
+ * barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+}
+
+static int __init omap3xxx_prcm_init(void)
+{
+        if (cpu_is_omap34xx())
+                return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+        return 0;
+}
+subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index cef533df086..70ac2a19dc5 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP2/3 Power/Reset Management (PRM) register definitions
  *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
  * Copyright (C) 2008-2010 Nokia Corporation
  * Paul Walmsley
  *
@@ -314,6 +314,13 @@ void omap3_prm_vp_clear_txdone(u8 vp_id);
 extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+/* PRM interrupt-related functions */
+extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+extern void omap3xxx_prm_ocp_barrier(void);
+extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+
 #endif  /* CONFIG_ARCH_OMAP4 */
 
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index dd885eecf22..33dd655e6aa 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -27,6 +27,24 @@
 #include "prcm44xx.h"
 #include "prminst44xx.h"
 
+static const struct omap_prcm_irq omap4_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+
+static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
+        .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 2,
+        .irqs                   = omap4_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
+        .irq                    = OMAP44XX_IRQ_PRCM,
+        .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap44xx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap44xx_prm_restore_irqen,
+};
+
 /* PRM low-level functions */
 
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -121,3 +139,101 @@ u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
                                                OMAP4430_PRM_DEVICE_INST,
                                                offset);
 }
+
+static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
+{
+        u32 mask, st;
+
+        /* XXX read mask from RAM? */
+        mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
+        st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
+
+        return mask & st;
+}
+
+/**
+ * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to two consecutive u32s, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the two u32s pointed to by @events.
+ * No return value.
+ */
+void omap44xx_prm_read_pending_irqs(unsigned long *events)
+{
+        events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
+                                          OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+
+        events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
+                                          OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+}
+
+/**
+ * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap44xx_prm_ocp_barrier(void)
+{
+        omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                OMAP4_REVISION_PRM_OFFSET);
+}
+
+/**
+ * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
+ * @saved_mask.  @saved_mask must be allocated by the caller.
+ * Intended to be used in the PRM interrupt handler suspend callback.
+ * The OCP barrier is needed to ensure the write to disable PRM
+ * interrupts reaches the PRM before returning; otherwise, spurious
+ * interrupts might occur.  No return value.
+ */
+void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] =
+                omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                        OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+        saved_mask[1] =
+                omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                        OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+
+        omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+        omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
+
+        /* OCP barrier */
+        omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                OMAP4_REVISION_PRM_OFFSET);
+}
+
+/**
+ * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
+ * @saved_mask.  Intended to be used in the PRM interrupt handler resume
+ * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
+ * No OCP barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap44xx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+        omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
+}
+
+static int __init omap4xxx_prcm_init(void)
+{
+        if (cpu_is_omap44xx())
+                return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        return 0;
+}
+subsys_initcall(omap4xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 3d66ccd849d..7978092946d 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP44xx PRM instance offset macros
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
@@ -763,6 +763,12 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
 # endif
 
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
new file mode 100644
index 00000000000..860118ab43e
--- /dev/null
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -0,0 +1,320 @@
+/*
+ * OMAP2+ common Power & Reset Management (PRM) IP block functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * For historical purposes, the API used to configure the PRM
+ * interrupt handler refers to it as the "PRCM interrupt."  The
+ * underlying registers are located in the PRM on OMAP3/4.
+ *
+ * XXX This code should eventually be moved to a PRM driver.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+
+#include <mach/system.h>
+#include <plat/common.h>
+#include <plat/prcm.h>
+#include <plat/irqs.h>
+
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+
+/*
+ * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
+ * XXX this is technically not needed, since
+ * omap_prcm_register_chain_handler() could allocate this based on the
+ * actual amount of memory needed for the SoC
+ */
+#define OMAP_PRCM_MAX_NR_PENDING_REG            2
+
+/*
+ * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
+ * by the PRCM interrupt handler code.  There will be one 'chip' per
+ * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
+ * one "chip" and OMAP4 will have two.)
+ */
+static struct irq_chip_generic **prcm_irq_chips;
+
+/*
+ * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
+ * is currently running on.  Defined and passed by initialization code
+ * that calls omap_prcm_register_chain_handler().
+ */
+static struct omap_prcm_irq_setup *prcm_irq_setup;
+
+/* Private functions */
+
+/*
+ * Move priority events from events to priority_events array
+ */
+static void omap_prcm_events_filter_priority(unsigned long *events,
+        unsigned long *priority_events)
+{
+        int i;
+
+        for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
+                priority_events[i] =
+                        events[i] & prcm_irq_setup->priority_mask[i];
+                events[i] ^= priority_events[i];
+        }
+}
+
+/*
+ * PRCM Interrupt Handler
+ *
+ * This is a common handler for the OMAP PRCM interrupts. Pending
+ * interrupts are detected by a call to prcm_pending_events and
+ * dispatched accordingly. Clearing of the wakeup events should be
+ * done by the SoC specific individual handlers.
+ */
+static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+        unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        unsigned int virtirq;
+        int nr_irqs = prcm_irq_setup->nr_regs * 32;
+
+        /*
+         * If we are suspended, mask all interrupts from PRCM level,
+         * this does not ack them, and they will be pending until we
+         * re-enable the interrupts, at which point the
+         * omap_prcm_irq_handler will be executed again.  The
+         * _save_and_clear_irqen() function must ensure that the PRM
+         * write to disable all IRQs has reached the PRM before
+         * returning, or spurious PRCM interrupts may occur during
+         * suspend.
+         */
+        if (prcm_irq_setup->suspended) {
+                prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
+                prcm_irq_setup->suspend_save_flag = true;
+        }
+
+        /*
+         * Loop until all pending irqs are handled, since
+         * generic_handle_irq() can cause new irqs to come
+         */
+        while (!prcm_irq_setup->suspended) {
+                prcm_irq_setup->read_pending_irqs(pending);
+
+                /* No bit set, then all IRQs are handled */
+                if (find_first_bit(pending, nr_irqs) >= nr_irqs)
+                        break;
+
+                omap_prcm_events_filter_priority(pending, priority_pending);
+
+                /*
+                 * Loop on all currently pending irqs so that new irqs
+                 * cannot starve previously pending irqs
+                 */
+
+                /* Serve priority events first */
+                for_each_set_bit(virtirq, priority_pending, nr_irqs)
+                        generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
+
+                /* Serve normal events next */
+                for_each_set_bit(virtirq, pending, nr_irqs)
+                        generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
+        }
+        if (chip->irq_ack)
+                chip->irq_ack(&desc->irq_data);
+        if (chip->irq_eoi)
+                chip->irq_eoi(&desc->irq_data);
+        chip->irq_unmask(&desc->irq_data);
+
+        prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
+}
+
+/* Public functions */
+
+/**
+ * omap_prcm_event_to_irq - given a PRCM event name, returns the
+ * corresponding IRQ on which the handler should be registered
+ * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
+ *
+ * Returns the Linux internal IRQ ID corresponding to @name upon success,
+ * or -ENOENT upon failure.
+ */
+int omap_prcm_event_to_irq(const char *name)
+{
+        int i;
+
+        if (!prcm_irq_setup || !name)
+                return -ENOENT;
+
+        for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
+                if (!strcmp(prcm_irq_setup->irqs[i].name, name))
+                        return prcm_irq_setup->base_irq +
+                                prcm_irq_setup->irqs[i].offset;
+
+        return -ENOENT;
+}
+
+/**
+ * omap_prcm_irq_cleanup - reverses memory allocated and other steps
+ * done by omap_prcm_register_chain_handler()
+ *
+ * No return value.
+ */
+void omap_prcm_irq_cleanup(void)
+{
+        int i;
+
+        if (!prcm_irq_setup) {
+                pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
+                return;
+        }
+
+        if (prcm_irq_chips) {
+                for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
+                        if (prcm_irq_chips[i])
+                                irq_remove_generic_chip(prcm_irq_chips[i],
+                                        0xffffffff, 0, 0);
+                        prcm_irq_chips[i] = NULL;
+                }
+                kfree(prcm_irq_chips);
+                prcm_irq_chips = NULL;
+        }
+
+        kfree(prcm_irq_setup->saved_mask);
+        prcm_irq_setup->saved_mask = NULL;
+
+        kfree(prcm_irq_setup->priority_mask);
+        prcm_irq_setup->priority_mask = NULL;
+
+        irq_set_chained_handler(prcm_irq_setup->irq, NULL);
+
+        if (prcm_irq_setup->base_irq > 0)
+                irq_free_descs(prcm_irq_setup->base_irq,
+                        prcm_irq_setup->nr_regs * 32);
+        prcm_irq_setup->base_irq = 0;
+}
+
+void omap_prcm_irq_prepare(void)
+{
+        prcm_irq_setup->suspended = true;
+}
+
+void omap_prcm_irq_complete(void)
+{
+        prcm_irq_setup->suspended = false;
+
+        /* If we have not saved the masks, do not attempt to restore */
+        if (!prcm_irq_setup->suspend_save_flag)
+                return;
+
+        prcm_irq_setup->suspend_save_flag = false;
+
+        /*
+         * Re-enable all masked PRCM irq sources, this causes the PRCM
+         * interrupt to fire immediately if the events were masked
+         * previously in the chain handler
+         */
+        prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
+}
+
+/**
+ * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
+ * handler based on provided parameters
+ * @irq_setup: hardware data about the underlying PRM/PRCM
+ *
+ * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
+ * one generic IRQ chip per PRM interrupt status/enable register pair.
+ * Returns 0 upon success, -EINVAL if called twice or if invalid
+ * arguments are passed, or -ENOMEM on any other error.
+ */
+int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
+{
+        int nr_regs = irq_setup->nr_regs;
+        u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
+        int offset, i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        if (!irq_setup)
+                return -EINVAL;
+
+        if (prcm_irq_setup) {
+                pr_err("PRCM: already initialized; won't reinitialize\n");
+                return -EINVAL;
+        }
+
+        if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
+                pr_err("PRCM: nr_regs too large\n");
+                return -EINVAL;
+        }
+
+        prcm_irq_setup = irq_setup;
+
+        prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
+        prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
+        prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
+                GFP_KERNEL);
+
+        if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
+            !prcm_irq_setup->priority_mask) {
+                pr_err("PRCM: kzalloc failed\n");
+                goto err;
+        }
+
+        memset(mask, 0, sizeof(mask));
+
+        for (i = 0; i < irq_setup->nr_irqs; i++) {
+                offset = irq_setup->irqs[i].offset;
+                mask[offset >> 5] |= 1 << (offset & 0x1f);
+                if (irq_setup->irqs[i].priority)
+                        irq_setup->priority_mask[offset >> 5] |=
+                                1 << (offset & 0x1f);
+        }
+
+        irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
+
+        irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
+                0);
+
+        if (irq_setup->base_irq < 0) {
+                pr_err("PRCM: failed to allocate irq descs: %d\n",
+                        irq_setup->base_irq);
+                goto err;
+        }
+
+        for (i = 0; i <= irq_setup->nr_regs; i++) {
+                gc = irq_alloc_generic_chip("PRCM", 1,
+                        irq_setup->base_irq + i * 32, prm_base,
+                        handle_level_irq);
+
+                if (!gc) {
+                        pr_err("PRCM: failed to allocate generic chip\n");
+                        goto err;
+                }
+                ct = gc->chip_types;
+                ct->chip.irq_ack = irq_gc_ack_set_bit;
+                ct->chip.irq_mask = irq_gc_mask_clr_bit;
+                ct->chip.irq_unmask = irq_gc_mask_set_bit;
+
+                ct->regs.ack = irq_setup->ack + i * 4;
+                ct->regs.mask = irq_setup->mask + i * 4;
+
+                irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
+                prcm_irq_chips[i] = gc;
+        }
+
+        return 0;
+
+err:
+        omap_prcm_irq_cleanup();
+        return -ENOMEM;
+}
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index ee3a8ad304c..7479d7ea137 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -1,7 +1,7 @@
 /*
  * SDRC register values for Nokia boards
  *
- * Copyright (C) 2008, 2010 Nokia Corporation
+ * Copyright (C) 2008, 2010-2011 Nokia Corporation
  *
  * Lauri Leukkunen <lauri.leukkunen@nokia.com>
  *
@@ -107,14 +107,37 @@ static const struct sdram_timings nokia_195dot2mhz_timings[] = {
         },
 };
 
+static const struct sdram_timings nokia_200mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30000,
+                .tDPL = 15000,
+                .tRRD = 10000,
+                .tRCD = 20000,
+                .tRP = 15000,
+                .tRAS = 40000,
+                .tRC = 55000,
+                .tRFC = 140000,
+                .tXSR = 200000,
+
+                .tREF = 7800,
+
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2
+        },
+};
+
 static const struct {
         long rate;
         struct sdram_timings const *data;
 } nokia_timings[] = {
         { 83000000, nokia_166mhz_timings },
         { 97600000, nokia_97dot6mhz_timings },
+        { 100000000, nokia_200mhz_timings },
         { 166000000, nokia_166mhz_timings },
         { 195200000, nokia_195dot2mhz_timings },
+        { 200000000, nokia_200mhz_timings },
 };
 static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 42c326732a2..247d89478f2 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,26 +19,21 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <linux/serial_8250.h>
 #include <linux/pm_runtime.h>
 #include <linux/console.h>
 
-#ifdef CONFIG_SERIAL_OMAP
 #include <plat/omap-serial.h>
-#endif
-
 #include "common.h"
 #include <plat/board.h>
-#include <plat/clock.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap-pm.h>
 
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
@@ -47,603 +42,226 @@
 #include "control.h"
 #include "mux.h"
 
-#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
-#define UART_OMAP_WER           0x17    /* Wake-up enable register */
-
-#define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
-#define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
-
 /*
- * NOTE: By default the serial timeout is disabled as it causes lost characters
- * over the serial ports. This means that the UART clocks will stay on until
- * disabled via sysfs. This also causes that any deeper omap sleep states are
- * blocked. 
+ * NOTE: By default the serial auto_suspend timeout is disabled as it causes
+ * lost characters over the serial ports. This means that the UART clocks will
+ * stay on until power/autosuspend_delay is set for the uart from sysfs.
+ * This also causes that any deeper omap sleep states are blocked.
  */
-#define DEFAULT_TIMEOUT 0
+#define DEFAULT_AUTOSUSPEND_DELAY       -1
 
 #define MAX_UART_HWMOD_NAME_LEN         16
 
 struct omap_uart_state {
         int num;
         int can_sleep;
-        struct timer_list timer;
-        u32 timeout;
-
-        void __iomem *wk_st;
-        void __iomem *wk_en;
-        u32 wk_mask;
-        u32 padconf;
-        u32 dma_enabled;
-
-        struct clk *ick;
-        struct clk *fck;
-        int clocked;
-
-        int irq;
-        int regshift;
-        int irqflags;
-        void __iomem *membase;
-        resource_size_t mapbase;
 
         struct list_head node;
         struct omap_hwmod *oh;
         struct platform_device *pdev;
-
-        u32 errata;
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
-        int context_valid;
-
-        /* Registers to be saved/restored for OFF-mode */
-        u16 dll;
-        u16 dlh;
-        u16 ier;
-        u16 sysc;
-        u16 scr;
-        u16 wer;
-        u16 mcr;
-#endif
 };
 
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
+static u8 console_uart_id = -1;
+static u8 no_console_suspend;
+static u8 uart_debug;
+
+#define DEFAULT_RXDMA_POLLRATE          1       /* RX DMA polling rate (us) */
+#define DEFAULT_RXDMA_BUFSIZE           4096    /* RX DMA buffer size */
+#define DEFAULT_RXDMA_TIMEOUT           (3 * HZ)/* RX DMA timeout (jiffies) */
+
+static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
+        {
+                .dma_enabled    = false,
+                .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
+                .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
+                .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
+                .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
+        },
+};
 
-static inline unsigned int __serial_read_reg(struct uart_port *up,
-                                             int offset)
-{
-        offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
-}
-
-static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
-                                           int offset)
+#ifdef CONFIG_PM
+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
 {
-        offset <<= uart->regshift;
-        return (unsigned int)__raw_readb(uart->membase + offset);
-}
+        struct omap_device *od = to_omap_device(pdev);
 
-static inline void __serial_write_reg(struct uart_port *up, int offset,
-                int value)
-{
-        offset <<= up->regshift;
-        __raw_writeb(value, up->membase + offset);
-}
+        if (!od)
+                return;
 
-static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
-                                    int value)
-{
-        offset <<= uart->regshift;
-        __raw_writeb(value, uart->membase + offset);
+        if (enable)
+                omap_hwmod_enable_wakeup(od->hwmods[0]);
+        else
+                omap_hwmod_disable_wakeup(od->hwmods[0]);
 }
 
 /*
- * Internal UARTs need to be initialized for the 8250 autoconfig to work
- * properly. Note that the TX watermark initialization may not be needed
- * once the 8250.c watermark handling code is merged.
+ * Errata i291: [UART]:Cannot Acknowledge Idle Requests
+ * in Smartidle Mode When Configured for DMA Operations.
+ * WA: configure uart in force idle mode.
  */
-
-static inline void __init omap_uart_reset(struct omap_uart_state *uart)
+static void omap_uart_set_noidle(struct platform_device *pdev)
 {
-        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-        serial_write_reg(uart, UART_OMAP_SCR, 0x08);
-        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
-}
-
-#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+        struct omap_device *od = to_omap_device(pdev);
 
-/*
- * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
- * The access to uart register after MDR1 Access
- * causes UART to corrupt data.
- *
- * Need a delay =
- * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
- * give 10 times as much
- */
-static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
-                u8 fcr_val)
-{
-        u8 timeout = 255;
-
-        serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
-        udelay(2);
-        serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
-                        UART_FCR_CLEAR_RCVR);
-        /*
-         * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
-         * TX_FIFO_E bit is 1.
-         */
-        while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
-                                (UART_LSR_THRE | UART_LSR_DR))) {
-                timeout--;
-                if (!timeout) {
-                        /* Should *never* happen. we warn and carry on */
-                        dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
-                        serial_read_reg(uart, UART_LSR));
-                        break;
-                }
-                udelay(1);
-        }
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
 }
 
-static void omap_uart_save_context(struct omap_uart_state *uart)
+static void omap_uart_set_forceidle(struct platform_device *pdev)
 {
-        u16 lcr = 0;
+        struct omap_device *od = to_omap_device(pdev);
 
-        if (!enable_off_mode)
-                return;
-
-        lcr = serial_read_reg(uart, UART_LCR);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        uart->dll = serial_read_reg(uart, UART_DLL);
-        uart->dlh = serial_read_reg(uart, UART_DLM);
-        serial_write_reg(uart, UART_LCR, lcr);
-        uart->ier = serial_read_reg(uart, UART_IER);
-        uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
-        uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
-        uart->wer = serial_read_reg(uart, UART_OMAP_WER);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
-        uart->mcr = serial_read_reg(uart, UART_MCR);
-        serial_write_reg(uart, UART_LCR, lcr);
-
-        uart->context_valid = 1;
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
 }
 
-static void omap_uart_restore_context(struct omap_uart_state *uart)
-{
-        u16 efr = 0;
-
-        if (!enable_off_mode)
-                return;
-
-        if (!uart->context_valid)
-                return;
-
-        uart->context_valid = 0;
-
-        if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
-        else
-                serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        efr = serial_read_reg(uart, UART_EFR);
-        serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
-        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(uart, UART_IER, 0x0);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        serial_write_reg(uart, UART_DLL, uart->dll);
-        serial_write_reg(uart, UART_DLM, uart->dlh);
-        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(uart, UART_IER, uart->ier);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
-        serial_write_reg(uart, UART_MCR, uart->mcr);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        serial_write_reg(uart, UART_EFR, efr);
-        serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
-        serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
-        serial_write_reg(uart, UART_OMAP_WER, uart->wer);
-        serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
-
-        if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
-        else
-                /* UART 16x mode */
-                serial_write_reg(uart, UART_OMAP_MDR1,
-                                UART_OMAP_MDR1_16X_MODE);
-}
 #else
-static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
-static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
-#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
-
-static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
-{
-        if (uart->clocked)
-                return;
-
-        omap_device_enable(uart->pdev);
-        uart->clocked = 1;
-        omap_uart_restore_context(uart);
-}
-
-#ifdef CONFIG_PM
-
-static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
-{
-        if (!uart->clocked)
-                return;
-
-        omap_uart_save_context(uart);
-        uart->clocked = 0;
-        omap_device_idle(uart->pdev);
-}
-
-static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
-{
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                u32 v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-}
-
-static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
-{
-        /* Clear wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                u32 v = __raw_readl(uart->wk_en);
-                v &= ~uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-
-        /* Ensure IOPAD wake-enables are cleared */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v = omap_ctrl_readw(uart->padconf);
-                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-}
-
-static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
-                                               int enable)
-{
-        u8 idlemode;
-
-        if (enable) {
-                /**
-                 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
-                 * in Smartidle Mode When Configured for DMA Operations.
-                 */
-                if (uart->dma_enabled)
-                        idlemode = HWMOD_IDLEMODE_FORCE;
-                else
-                        idlemode = HWMOD_IDLEMODE_SMART;
-        } else {
-                idlemode = HWMOD_IDLEMODE_NO;
-        }
-
-        omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
-}
-
-static void omap_uart_block_sleep(struct omap_uart_state *uart)
-{
-        omap_uart_enable_clocks(uart);
-
-        omap_uart_smart_idle_enable(uart, 0);
-        uart->can_sleep = 0;
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        else
-                del_timer(&uart->timer);
-}
-
-static void omap_uart_allow_sleep(struct omap_uart_state *uart)
-{
-        if (device_may_wakeup(&uart->pdev->dev))
-                omap_uart_enable_wakeup(uart);
-        else
-                omap_uart_disable_wakeup(uart);
-
-        if (!uart->clocked)
-                return;
-
-        omap_uart_smart_idle_enable(uart, 1);
-        uart->can_sleep = 1;
-        del_timer(&uart->timer);
-}
-
-static void omap_uart_idle_timer(unsigned long data)
-{
-        struct omap_uart_state *uart = (struct omap_uart_state *)data;
-
-        omap_uart_allow_sleep(uart);
-}
-
-void omap_uart_prepare_idle(int num)
-{
-        struct omap_uart_state *uart;
-
-        list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num && uart->can_sleep) {
-                        omap_uart_disable_clocks(uart);
-                        return;
-                }
-        }
-}
-
-void omap_uart_resume_idle(int num)
-{
-        struct omap_uart_state *uart;
-
-        list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num && uart->can_sleep) {
-                        omap_uart_enable_clocks(uart);
-
-                        /* Check for IO pad wakeup */
-                        if (cpu_is_omap34xx() && uart->padconf) {
-                                u16 p = omap_ctrl_readw(uart->padconf);
-
-                                if (p & OMAP3_PADCONF_WAKEUPEVENT0)
-                                        omap_uart_block_sleep(uart);
-                        }
-
-                        /* Check for normal UART wakeup */
-                        if (__raw_readl(uart->wk_st) & uart->wk_mask)
-                                omap_uart_block_sleep(uart);
-                        return;
-                }
-        }
-}
-
-void omap_uart_prepare_suspend(void)
-{
-        struct omap_uart_state *uart;
-
-        list_for_each_entry(uart, &uart_list, node) {
-                omap_uart_allow_sleep(uart);
-        }
-}
-
-int omap_uart_can_sleep(void)
-{
-        struct omap_uart_state *uart;
-        int can_sleep = 1;
-
-        list_for_each_entry(uart, &uart_list, node) {
-                if (!uart->clocked)
-                        continue;
-
-                if (!uart->can_sleep) {
-                        can_sleep = 0;
-                        continue;
-                }
-
-                /* This UART can now safely sleep. */
-                omap_uart_allow_sleep(uart);
-        }
-
-        return can_sleep;
-}
+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+{}
+static void omap_uart_set_noidle(struct platform_device *pdev) {}
+static void omap_uart_set_forceidle(struct platform_device *pdev) {}
+#endif /* CONFIG_PM */
 
-/**
- * omap_uart_interrupt()
- *
- * This handler is used only to detect that *any* UART interrupt has
- * occurred.  It does _nothing_ to handle the interrupt.  Rather,
- * any UART interrupt will trigger the inactivity timer so the
- * UART will not idle or sleep for its timeout period.
- *
- **/
-/* static int first_interrupt; */
-static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
-{
-        struct omap_uart_state *uart = dev_id;
+#ifdef CONFIG_OMAP_MUX
+static struct omap_device_pad default_uart1_pads[] __initdata = {
+        {
+                .name   = "uart1_cts.uart1_cts",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart1_rts.uart1_rts",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart1_tx.uart1_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart1_rx.uart1_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+};
 
-        omap_uart_block_sleep(uart);
+static struct omap_device_pad default_uart2_pads[] __initdata = {
+        {
+                .name   = "uart2_cts.uart2_cts",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_rts.uart2_rts",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_tx.uart2_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_rx.uart2_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+};
 
-        return IRQ_NONE;
-}
+static struct omap_device_pad default_uart3_pads[] __initdata = {
+        {
+                .name   = "uart3_cts_rctx.uart3_cts_rctx",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_rts_sd.uart3_rts_sd",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_tx_irtx.uart3_tx_irtx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_rx_irrx.uart3_rx_irrx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+        },
+};
 
-static void omap_uart_idle_init(struct omap_uart_state *uart)
-{
-        int ret;
-
-        uart->can_sleep = 0;
-        uart->timeout = DEFAULT_TIMEOUT;
-        setup_timer(&uart->timer, omap_uart_idle_timer,
-                    (unsigned long) uart);
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        omap_uart_smart_idle_enable(uart, 0);
-
-        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
-                u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
-                u32 wk_mask = 0;
-                u32 padconf = 0;
-
-                /* XXX These PRM accesses do not belong here */
-                uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
-                uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
-                switch (uart->num) {
-                case 0:
-                        wk_mask = OMAP3430_ST_UART1_MASK;
-                        padconf = 0x182;
-                        break;
-                case 1:
-                        wk_mask = OMAP3430_ST_UART2_MASK;
-                        padconf = 0x17a;
-                        break;
-                case 2:
-                        wk_mask = OMAP3430_ST_UART3_MASK;
-                        padconf = 0x19e;
-                        break;
-                case 3:
-                        wk_mask = OMAP3630_ST_UART4_MASK;
-                        padconf = 0x0d2;
-                        break;
-                }
-                uart->wk_mask = wk_mask;
-                uart->padconf = padconf;
-        } else if (cpu_is_omap24xx()) {
-                u32 wk_mask = 0;
-                u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
-
-                switch (uart->num) {
-                case 0:
-                        wk_mask = OMAP24XX_ST_UART1_MASK;
-                        break;
-                case 1:
-                        wk_mask = OMAP24XX_ST_UART2_MASK;
-                        break;
-                case 2:
-                        wk_en = OMAP24XX_PM_WKEN2;
-                        wk_st = OMAP24XX_PM_WKST2;
-                        wk_mask = OMAP24XX_ST_UART3_MASK;
-                        break;
-                }
-                uart->wk_mask = wk_mask;
-                if (cpu_is_omap2430()) {
-                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
-                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
-                } else if (cpu_is_omap2420()) {
-                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
-                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
-                }
-        } else {
-                uart->wk_en = NULL;
-                uart->wk_st = NULL;
-                uart->wk_mask = 0;
-                uart->padconf = 0;
-        }
+static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
+        {
+                .name   = "gpmc_wait2.uart4_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "gpmc_wait3.uart4_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
+        },
+};
 
-        uart->irqflags |= IRQF_SHARED;
-        ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
-                                   IRQF_SHARED, "serial idle", (void *)uart);
-        WARN_ON(ret);
-}
+static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
+        {
+                .name   = "uart4_tx.uart4_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart4_rx.uart4_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+        },
+};
 
-void omap_uart_enable_irqs(int enable)
+static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 {
-        int ret;
-        struct omap_uart_state *uart;
-
-        list_for_each_entry(uart, &uart_list, node) {
-                if (enable) {
-                        pm_runtime_put_sync(&uart->pdev->dev);
-                        ret = request_threaded_irq(uart->irq, NULL,
-                                                   omap_uart_interrupt,
-                                                   IRQF_SHARED,
-                                                   "serial idle",
-                                                   (void *)uart);
-                } else {
-                        pm_runtime_get_noresume(&uart->pdev->dev);
-                        free_irq(uart->irq, (void *)uart);
+        switch (bdata->id) {
+        case 0:
+                bdata->pads = default_uart1_pads;
+                bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
+                break;
+        case 1:
+                bdata->pads = default_uart2_pads;
+                bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
+                break;
+        case 2:
+                bdata->pads = default_uart3_pads;
+                bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
+                break;
+        case 3:
+                if (cpu_is_omap44xx()) {
+                        bdata->pads = default_omap4_uart4_pads;
+                        bdata->pads_cnt =
+                                ARRAY_SIZE(default_omap4_uart4_pads);
+                } else if (cpu_is_omap3630()) {
+                        bdata->pads = default_omap36xx_uart4_pads;
+                        bdata->pads_cnt =
+                                ARRAY_SIZE(default_omap36xx_uart4_pads);
                 }
+                break;
+        default:
+                break;
         }
 }
-
-static ssize_t sleep_timeout_show(struct device *dev,
-                                  struct device_attribute *attr,
-                                  char *buf)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct omap_device *odev = to_omap_device(pdev);
-        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
-
-        return sprintf(buf, "%u\n", uart->timeout / HZ);
-}
-
-static ssize_t sleep_timeout_store(struct device *dev,
-                                   struct device_attribute *attr,
-                                   const char *buf, size_t n)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct omap_device *odev = to_omap_device(pdev);
-        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
-        unsigned int value;
-
-        if (sscanf(buf, "%u", &value) != 1) {
-                dev_err(dev, "sleep_timeout_store: Invalid value\n");
-                return -EINVAL;
-        }
-
-        uart->timeout = value * HZ;
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        else
-                /* A zero value means disable timeout feature */
-                omap_uart_block_sleep(uart);
-
-        return n;
-}
-
-static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
-                sleep_timeout_store);
-#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
-static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
-static void omap_uart_block_sleep(struct omap_uart_state *uart)
-{
-        /* Needed to enable UART clocks when built without CONFIG_PM */
-        omap_uart_enable_clocks(uart);
-}
-#define DEV_CREATE_FILE(dev, attr)
-#endif /* CONFIG_PM */
-
-#ifndef CONFIG_SERIAL_OMAP
-/*
- * Override the default 8250 read handler: mem_serial_in()
- * Empty RX fifo read causes an abort on omap3630 and omap4
- * This function makes sure that an empty rx fifo is not read on these silicons
- * (OMAP1/2/3430 are not affected)
- */
-static unsigned int serial_in_override(struct uart_port *up, int offset)
-{
-        if (UART_RX == offset) {
-                unsigned int lsr;
-                lsr = __serial_read_reg(up, UART_LSR);
-                if (!(lsr & UART_LSR_DR))
-                        return -EPERM;
-        }
-
-        return __serial_read_reg(up, offset);
-}
+static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
+#endif
 
-static void serial_out_override(struct uart_port *up, int offset, int value)
+char *cmdline_find_option(char *str)
 {
-        unsigned int status, tmout = 10000;
+        extern char *saved_command_line;
 
-        status = __serial_read_reg(up, UART_LSR);
-        while (!(status & UART_LSR_THRE)) {
-                /* Wait up to 10ms for the character(s) to be sent. */
-                if (--tmout == 0)
-                        break;
-                udelay(1);
-                status = __serial_read_reg(up, UART_LSR);
-        }
-        __serial_write_reg(up, offset, value);
+        return strstr(saved_command_line, str);
 }
-#endif
 
 static int __init omap_serial_early_init(void)
 {
-        int i = 0;
-
         do {
                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
                 struct omap_hwmod *oh;
                 struct omap_uart_state *uart;
+                char uart_name[MAX_UART_HWMOD_NAME_LEN];
 
                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
-                         "uart%d", i + 1);
+                         "uart%d", num_uarts + 1);
                 oh = omap_hwmod_lookup(oh_name);
                 if (!oh)
                         break;
@@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void)
                         return -ENODEV;
 
                 uart->oh = oh;
-                uart->num = i++;
+                uart->num = num_uarts++;
                 list_add_tail(&uart->node, &uart_list);
-                num_uarts++;
-
-                /*
-                 * NOTE: omap_hwmod_setup*() has not yet been called,
-                 *       so no hwmod functions will work yet.
-                 */
-
-                /*
-                 * During UART early init, device need to be probed
-                 * to determine SoC specific init before omap_device
-                 * is ready.  Therefore, don't allow idle here
-                 */
-                uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+                snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
+                                "%s%d", OMAP_SERIAL_NAME, uart->num);
+
+                if (cmdline_find_option(uart_name)) {
+                        console_uart_id = uart->num;
+
+                        if (console_loglevel >= 10) {
+                                uart_debug = true;
+                                pr_info("%s used as console in debug mode"
+                                                " uart%d clocks will not be"
+                                                " gated", uart_name, uart->num);
+                        }
+
+                        if (cmdline_find_option("no_console_suspend"))
+                                no_console_suspend = true;
+
+                        /*
+                         * omap-uart can be used for earlyprintk logs
+                         * So if omap-uart is used as console then prevent
+                         * uart reset and idle to get logs from omap-uart
+                         * until uart console driver is available to take
+                         * care for console messages.
+                         * Idling or resetting omap-uart while printing logs
+                         * early boot logs can stall the boot-up.
+                         */
+                        oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+                }
         } while (1);
 
         return 0;
@@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init);
 /**
  * omap_serial_init_port() - initialize single serial port
  * @bdata: port specific board data pointer
+ * @info: platform specific data pointer
  *
  * This function initialies serial driver for given port only.
  * Platforms can call this function instead of omap_serial_init()
@@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init);
  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
  * use only one of the two.
  */
-void __init omap_serial_init_port(struct omap_board_data *bdata)
+void __init omap_serial_init_port(struct omap_board_data *bdata,
+                        struct omap_uart_port_info *info)
 {
         struct omap_uart_state *uart;
         struct omap_hwmod *oh;
@@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         void *pdata = NULL;
         u32 pdata_size = 0;
         char *name;
-#ifndef CONFIG_SERIAL_OMAP
-        struct plat_serial8250_port ports[2] = {
-                {},
-                {.flags = 0},
-        };
-        struct plat_serial8250_port *p = &ports[0];
-#else
         struct omap_uart_port_info omap_up;
-#endif
 
         if (WARN_ON(!bdata))
                 return;
@@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         list_for_each_entry(uart, &uart_list, node)
                 if (bdata->id == uart->num)
                         break;
+        if (!info)
+                info = omap_serial_default_info;
 
         oh = uart->oh;
-        uart->dma_enabled = 0;
-#ifndef CONFIG_SERIAL_OMAP
-        name = "serial8250";
-
-        /*
-         * !! 8250 driver does not use standard IORESOURCE* It
-         * has it's own custom pdata that can be taken from
-         * the hwmod resource data.  But, this needs to be
-         * done after the build.
-         *
-         * ?? does it have to be done before the register ??
-         * YES, because platform_device_data_add() copies
-         * pdata, it does not use a pointer.
-         */
-        p->flags = UPF_BOOT_AUTOCONF;
-        p->iotype = UPIO_MEM;
-        p->regshift = 2;
-        p->uartclk = OMAP24XX_BASE_BAUD * 16;
-        p->irq = oh->mpu_irqs[0].irq;
-        p->mapbase = oh->slaves[0]->addr->pa_start;
-        p->membase = omap_hwmod_get_mpu_rt_va(oh);
-        p->irqflags = IRQF_SHARED;
-        p->private_data = uart;
-
-        /*
-         * omap44xx, ti816x: Never read empty UART fifo
-         * omap3xxx: Never read empty UART fifo on UARTs
-         * with IP rev >=0x52
-         */
-        uart->regshift = p->regshift;
-        uart->membase = p->membase;
-        if (cpu_is_omap44xx() || cpu_is_ti816x())
-                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
-                        >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
-                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-
-        if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
-                p->serial_in = serial_in_override;
-                p->serial_out = serial_out_override;
-        }
-
-        pdata = &ports[0];
-        pdata_size = 2 * sizeof(struct plat_serial8250_port);
-#else
-
         name = DRIVER_NAME;
 
-        omap_up.dma_enabled = uart->dma_enabled;
+        omap_up.dma_enabled = info->dma_enabled;
         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
-        omap_up.mapbase = oh->slaves[0]->addr->pa_start;
-        omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
-        omap_up.irqflags = IRQF_SHARED;
-        omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        omap_up.flags = UPF_BOOT_AUTOCONF;
+        omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
+        omap_up.set_forceidle = omap_uart_set_forceidle;
+        omap_up.set_noidle = omap_uart_set_noidle;
+        omap_up.enable_wakeup = omap_uart_enable_wakeup;
+        omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
+        omap_up.dma_rx_timeout = info->dma_rx_timeout;
+        omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
+        omap_up.autosuspend_timeout = info->autosuspend_timeout;
+
+        /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
+        if (!cpu_is_omap2420() && !cpu_is_ti816x())
+                omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
+
+        /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
+        if (cpu_is_omap34xx() || cpu_is_omap3630())
+                omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
 
         pdata = &omap_up;
         pdata_size = sizeof(struct omap_uart_port_info);
-#endif
 
         if (WARN_ON(!oh))
                 return;
@@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
              name, oh->name);
 
-        omap_device_disable_idle_on_suspend(pdev);
+        if ((console_uart_id == bdata->id) && no_console_suspend)
+                omap_device_disable_idle_on_suspend(pdev);
+
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
-        uart->irq = oh->mpu_irqs[0].irq;
-        uart->regshift = 2;
-        uart->mapbase = oh->slaves[0]->addr->pa_start;
-        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
         uart->pdev = pdev;
 
         oh->dev_attr = uart;
 
-        console_lock(); /* in case the earlycon is on the UART */
-
-        /*
-         * Because of early UART probing, UART did not get idled
-         * on init.  Now that omap_device is ready, ensure full idle
-         * before doing omap_device_enable().
-         */
-        omap_hwmod_idle(uart->oh);
-
-        omap_device_enable(uart->pdev);
-        omap_uart_idle_init(uart);
-        omap_uart_reset(uart);
-        omap_hwmod_enable_wakeup(uart->oh);
-        omap_device_idle(uart->pdev);
-
-        /*
-         * Need to block sleep long enough for interrupt driven
-         * driver to start.  Console driver is in polling mode
-         * so device needs to be kept enabled while polling driver
-         * is in use.
-         */
-        if (uart->timeout)
-                uart->timeout = (30 * HZ);
-        omap_uart_block_sleep(uart);
-        uart->timeout = DEFAULT_TIMEOUT;
-
-        console_unlock();
-
-        if ((cpu_is_omap34xx() && uart->padconf) ||
-            (uart->wk_en && uart->wk_mask)) {
+        if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
+                        && !uart_debug)
                 device_init_wakeup(&pdev->dev, true);
-                DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
-        }
-
-        /* Enable the MDR1 errata for OMAP3 */
-        if (cpu_is_omap34xx() && !cpu_is_ti816x())
-                uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 
 /**
- * omap_serial_init() - initialize all supported serial ports
+ * omap_serial_board_init() - initialize all supported serial ports
+ * @info: platform specific data pointer
  *
  * Initializes all available UARTs as serial ports. Platforms
  * can call this function when they want to have default behaviour
  * for serial ports (e.g initialize them all as serial ports).
  */
-void __init omap_serial_init(void)
+void __init omap_serial_board_init(struct omap_uart_port_info *info)
 {
         struct omap_uart_state *uart;
         struct omap_board_data bdata;
@@ -849,7 +408,25 @@ void __init omap_serial_init(void)
                 bdata.flags = 0;
                 bdata.pads = NULL;
                 bdata.pads_cnt = 0;
-                omap_serial_init_port(&bdata);
 
+                if (cpu_is_omap44xx() || cpu_is_omap34xx())
+                        omap_serial_fill_default_pads(&bdata);
+
+                if (!info)
+                        omap_serial_init_port(&bdata, NULL);
+                else
+                        omap_serial_init_port(&bdata, &info[uart->num]);
         }
 }
+
+/**
+ * omap_serial_init() - initialize all supported serial ports
+ *
+ * Initializes all available UARTs.
+ * Platforms can call this function when they want to have default behaviour
+ * for serial ports (e.g initialize them all as serial ports).
+ */
+void __init omap_serial_init(void)
+{
+        omap_serial_board_init(NULL);
+}
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
new file mode 100644
index 00000000000..abd28340049
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -0,0 +1,379 @@
+/*
+ * OMAP44xx sleep code.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/smp_scu.h>
+#include <asm/memory.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <plat/omap44xx.h>
+#include <mach/omap-secure.h>
+
+#include "common.h"
+#include "omap4-sar-layout.h"
+
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+
+.macro  DO_SMC
+        dsb
+        smc     #0
+        dsb
+.endm
+
+ppa_zero_params:
+        .word           0x0
+
+ppa_por_params:
+        .word           1, 0
+
+/*
+ * =============================
+ * == CPU suspend finisher ==
+ * =============================
+ *
+ * void omap4_finish_suspend(unsigned long cpu_state)
+ *
+ * This function code saves the CPU context and performs the CPU
+ * power down sequence. Calling WFI effectively changes the CPU
+ * power domains states to the desired target power state.
+ *
+ * @cpu_state : contains context save state (r0)
+ *      0 - No context lost
+ *      1 - CPUx L1 and logic lost: MPUSS CSWR
+ *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *      3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
+ * @return: This function never returns for CPU OFF and DORMANT power states.
+ * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
+ * from this follows a full CPU reset path via ROM code to CPU restore code.
+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
+ * It returns to the caller for CPU INACTIVE and ON power states or in case
+ * CPU failed to transition to targeted OFF/DORMANT state.
+ */
+ENTRY(omap4_finish_suspend)
+        stmfd   sp!, {lr}
+        cmp     r0, #0x0
+        beq     do_WFI                          @ No lowpower state, jump to WFI
+
+        /*
+         * Flush all data from the L1 data cache before disabling
+         * SCTLR.C bit.
+         */
+        bl      omap4_get_sar_ram_base
+        ldr     r9, [r0, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     skip_secure_l1_clean
+        mov     r0, #SCU_PM_NORMAL
+        mov     r1, #0xFF                       @ clean seucre L1
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+skip_secure_l1_clean:
+        bl      v7_flush_dcache_all
+
+        /*
+         * Clear the SCTLR.C bit to prevent further data cache
+         * allocation. Clearing SCTLR.C would make all the data accesses
+         * strongly ordered and would not hit the cache.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        bic     r0, r0, #(1 << 2)               @ Disable the C bit
+        mcr     p15, 0, r0, c1, c0, 0
+        isb
+
+        /*
+         * Invalidate L1 data cache. Even though only invalidate is
+         * necessary exported flush API is used here. Doing clean
+         * on already clean cache would be almost NOP.
+         */
+        bl      v7_flush_dcache_all
+
+        /*
+         * Switch the CPU from Symmetric Multiprocessing (SMP) mode
+         * to AsymmetricMultiprocessing (AMP) mode by programming
+         * the SCU power status to DORMANT or OFF mode.
+         * This enables the CPU to be taken out of coherency by
+         * preventing the CPU from receiving cache, TLB, or BTB
+         * maintenance operations broadcast by other CPUs in the cluster.
+         */
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     scu_gp_set
+        mrc     p15, 0, r0, c0, c0, 5           @ Read MPIDR
+        ands    r0, r0, #0x0f
+        ldreq   r0, [r8, #SCU_OFFSET0]
+        ldrne   r0, [r8, #SCU_OFFSET1]
+        mov     r1, #0x00
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+        b       skip_scu_gp_set
+scu_gp_set:
+        mrc     p15, 0, r0, c0, c0, 5           @ Read MPIDR
+        ands    r0, r0, #0x0f
+        ldreq   r1, [r8, #SCU_OFFSET0]
+        ldrne   r1, [r8, #SCU_OFFSET1]
+        bl      omap4_get_scu_base
+        bl      scu_power_mode
+skip_scu_gp_set:
+        mrc     p15, 0, r0, c1, c1, 2           @ Read NSACR data
+        tst     r0, #(1 << 18)
+        mrcne   p15, 0, r0, c1, c0, 1
+        bicne   r0, r0, #(1 << 6)               @ Disable SMP bit
+        mcrne   p15, 0, r0, c1, c0, 1
+        isb
+        dsb
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * Clean and invalidate the L2 cache.
+         * Common cache-l2x0.c functions can't be used here since it
+         * uses spinlocks. We are out of coherency here with data cache
+         * disabled. The spinlock implementation uses exclusive load/store
+         * instruction which can fail without data cache being enabled.
+         * OMAP4 hardware doesn't support exclusive monitor which can
+         * overcome exclusive access issue. Because of this, CPU can
+         * lead to deadlock.
+         */
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        mrc     p15, 0, r5, c0, c0, 5           @ Read MPIDR
+        ands    r5, r5, #0x0f
+        ldreq   r0, [r8, #L2X0_SAVE_OFFSET0]    @ Retrieve L2 state from SAR
+        ldrne   r0, [r8, #L2X0_SAVE_OFFSET1]    @ memory.
+        cmp     r0, #3
+        bne     do_WFI
+#ifdef CONFIG_PL310_ERRATA_727915
+        mov     r0, #0x03
+        mov     r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+        DO_SMC
+#endif
+        bl      omap4_get_l2cache_base
+        mov     r2, r0
+        ldr     r0, =0xffff
+        str     r0, [r2, #L2X0_CLEAN_INV_WAY]
+wait:
+        ldr     r0, [r2, #L2X0_CLEAN_INV_WAY]
+        ldr     r1, =0xffff
+        ands    r0, r0, r1
+        bne     wait
+#ifdef CONFIG_PL310_ERRATA_727915
+        mov     r0, #0x00
+        mov     r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+        DO_SMC
+#endif
+l2x_sync:
+        bl      omap4_get_l2cache_base
+        mov     r2, r0
+        mov     r0, #0x0
+        str     r0, [r2, #L2X0_CACHE_SYNC]
+sync:
+        ldr     r0, [r2, #L2X0_CACHE_SYNC]
+        ands    r0, r0, #0x1
+        bne     sync
+#endif
+
+do_WFI:
+        bl      omap_do_wfi
+
+        /*
+         * CPU is here when it failed to enter OFF/DORMANT or
+         * no low power state was attempted.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        tst     r0, #(1 << 2)                   @ Check C bit enabled?
+        orreq   r0, r0, #(1 << 2)               @ Enable the C bit
+        mcreq   p15, 0, r0, c1, c0, 0
+        isb
+
+        /*
+         * Ensure the CPU power state is set to NORMAL in
+         * SCU power state so that CPU is back in coherency.
+         * In non-coherent mode CPU can lock-up and lead to
+         * system deadlock.
+         */
+        mrc     p15, 0, r0, c1, c0, 1
+        tst     r0, #(1 << 6)                   @ Check SMP bit enabled?
+        orreq   r0, r0, #(1 << 6)
+        mcreq   p15, 0, r0, c1, c0, 1
+        isb
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     scu_gp_clear
+        mov     r0, #SCU_PM_NORMAL
+        mov     r1, #0x00
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+        b       skip_scu_gp_clear
+scu_gp_clear:
+        bl      omap4_get_scu_base
+        mov     r1, #SCU_PM_NORMAL
+        bl      scu_power_mode
+skip_scu_gp_clear:
+        isb
+        dsb
+        ldmfd   sp!, {pc}
+ENDPROC(omap4_finish_suspend)
+
+/*
+ * ============================
+ * == CPU resume entry point ==
+ * ============================
+ *
+ * void omap4_cpu_resume(void)
+ *
+ * ROM code jumps to this function while waking up from CPU
+ * OFF or DORMANT state. Physical address of the function is
+ * stored in the SAR RAM while entering to OFF or DORMANT mode.
+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
+ */
+ENTRY(omap4_cpu_resume)
+        /*
+         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
+         * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
+         * init and for CPU1, a secure PPA API provided. CPU0 must be ON
+         * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
+         * OMAP443X GP devices- SMP bit isn't accessible.
+         * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
+         */
+        ldr     r8, =OMAP44XX_SAR_RAM_BASE
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Skip if GP device
+        bne     skip_ns_smp_enable
+        mrc     p15, 0, r0, c0, c0, 5
+        ands    r0, r0, #0x0f
+        beq     skip_ns_smp_enable
+ppa_actrl_retry:
+        mov     r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
+        adr     r3, ppa_zero_params             @ Pointer to parameters
+        mov     r1, #0x0                        @ Process ID
+        mov     r2, #0x4                        @ Flag
+        mov     r6, #0xff
+        mov     r12, #0x00                      @ Secure Service ID
+        DO_SMC
+        cmp     r0, #0x0                        @ API returns 0 on success.
+        beq     enable_smp_bit
+        b       ppa_actrl_retry
+enable_smp_bit:
+        mrc     p15, 0, r0, c1, c0, 1
+        tst     r0, #(1 << 6)                   @ Check SMP bit enabled?
+        orreq   r0, r0, #(1 << 6)
+        mcreq   p15, 0, r0, c1, c0, 1
+        isb
+skip_ns_smp_enable:
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * Restore the L2 AUXCTRL and enable the L2 cache.
+         * OMAP4_MON_L2X0_AUXCTRL_INDEX =  Program the L2X0 AUXCTRL
+         * OMAP4_MON_L2X0_CTRL_INDEX =  Enable the L2 using L2X0 CTRL
+         * register r0 contains value to be programmed.
+         * L2 cache is already invalidate by ROM code as part
+         * of MPUSS OFF wakeup path.
+         */
+        ldr     r2, =OMAP44XX_L2CACHE_BASE
+        ldr     r0, [r2, #L2X0_CTRL]
+        and     r0, #0x0f
+        cmp     r0, #1
+        beq     skip_l2en                       @ Skip if already enabled
+        ldr     r3, =OMAP44XX_SAR_RAM_BASE
+        ldr     r1, [r3, #OMAP_TYPE_OFFSET]
+        cmp     r1, #0x1                        @ Check for HS device
+        bne     set_gp_por
+        ldr     r0, =OMAP4_PPA_L2_POR_INDEX
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+        adr     r3, ppa_por_params
+        str     r4, [r3, #0x04]
+        mov     r1, #0x0                        @ Process ID
+        mov     r2, #0x4                        @ Flag
+        mov     r6, #0xff
+        mov     r12, #0x00                      @ Secure Service ID
+        DO_SMC
+        b       set_aux_ctrl
+set_gp_por:
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+        ldr     r12, =OMAP4_MON_L2X0_PREFETCH_INDEX     @ Setup L2 PREFETCH
+        DO_SMC
+set_aux_ctrl:
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r0, [r1, #L2X0_AUXCTRL_OFFSET]
+        ldr     r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX      @ Setup L2 AUXCTRL
+        DO_SMC
+        mov     r0, #0x1
+        ldr     r12, =OMAP4_MON_L2X0_CTRL_INDEX         @ Enable L2 cache
+        DO_SMC
+skip_l2en:
+#endif
+
+        b       cpu_resume                      @ Jump to generic resume
+ENDPROC(omap4_cpu_resume)
+#endif
+
+#ifndef CONFIG_OMAP4_ERRATA_I688
+ENTRY(omap_bus_sync)
+        mov     pc, lr
+ENDPROC(omap_bus_sync)
+#endif
+
+ENTRY(omap_do_wfi)
+        stmfd   sp!, {lr}
+        /* Drain interconnect write buffers. */
+        bl omap_bus_sync
+
+        /*
+         * Execute an ISB instruction to ensure that all of the
+         * CP15 register changes have been committed.
+         */
+        isb
+
+        /*
+         * Execute a barrier instruction to ensure that all cache,
+         * TLB and branch predictor maintenance operations issued
+         * by any CPU in the cluster have completed.
+         */
+        dsb
+        dmb
+
+        /*
+         * Execute a WFI instruction and wait until the
+         * STANDBYWFI output is asserted to indicate that the
+         * CPU is in idle and low power state. CPU can specualatively
+         * prefetch the instructions so add NOPs after WFI. Sixteen
+         * NOPs as per Cortex-A9 pipeline.
+         */
+        wfi                                     @ Wait For Interrupt
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+
+        ldmfd   sp!, {pc}
+ENDPROC(omap_do_wfi)
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 89ae29847c5..771dc781b74 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,51 +28,28 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <plat/usb.h>
+#include <plat/omap_device.h>
 
 #include "mux.h"
 
 #ifdef CONFIG_MFD_OMAP_USB_HOST
 
-#define OMAP_USBHS_DEVICE       "usbhs-omap"
-
-static struct resource usbhs_resources[] = {
-        {
-                .name   = "uhh",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "tll",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "ehci",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "ehci-irq",
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .name   = "ohci",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "ohci-irq",
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device usbhs_device = {
-        .name           = OMAP_USBHS_DEVICE,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(usbhs_resources),
-        .resource       = usbhs_resources,
-};
+#define OMAP_USBHS_DEVICE       "usbhs_omap"
+#define USBHS_UHH_HWMODNAME     "usb_host_hs"
+#define USBHS_TLL_HWMODNAME     "usb_tll_hs"
 
 static struct usbhs_omap_platform_data          usbhs_data;
 static struct ehci_hcd_omap_platform_data       ehci_data;
 static struct ohci_hcd_omap_platform_data       ohci_data;
 
+static struct omap_device_pm_latency omap_uhhtll_latency[] = {
+          {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+          },
+};
+
 /* MUX settings for EHCI pins */
 /*
  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
@@ -508,7 +485,10 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
-        int     i;
+        struct omap_hwmod       *oh[2];
+        struct omap_device      *od;
+        int                     bus_id = -1;
+        int                     i;
 
         for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
                 usbhs_data.port_mode[i] = pdata->port_mode[i];
@@ -523,44 +503,34 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
         usbhs_data.ohci_data = &ohci_data;
 
         if (cpu_is_omap34xx()) {
-                usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE;
-                usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1;
-                usbhs_resources[1].start = OMAP34XX_USBTLL_BASE;
-                usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1;
-                usbhs_resources[2].start        = OMAP34XX_EHCI_BASE;
-                usbhs_resources[2].end  = OMAP34XX_EHCI_BASE + SZ_1K - 1;
-                usbhs_resources[3].start = INT_34XX_EHCI_IRQ;
-                usbhs_resources[4].start        = OMAP34XX_OHCI_BASE;
-                usbhs_resources[4].end  = OMAP34XX_OHCI_BASE + SZ_1K - 1;
-                usbhs_resources[5].start = INT_34XX_OHCI_IRQ;
                 setup_ehci_io_mux(pdata->port_mode);
                 setup_ohci_io_mux(pdata->port_mode);
         } else if (cpu_is_omap44xx()) {
-                usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE;
-                usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1;
-                usbhs_resources[1].start = OMAP44XX_USBTLL_BASE;
-                usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1;
-                usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE;
-                usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1;
-                usbhs_resources[3].start = OMAP44XX_IRQ_EHCI;
-                usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE;
-                usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1;
-                usbhs_resources[5].start = OMAP44XX_IRQ_OHCI;
                 setup_4430ehci_io_mux(pdata->port_mode);
                 setup_4430ohci_io_mux(pdata->port_mode);
         }
 
-        if (platform_device_add_data(&usbhs_device,
-                                &usbhs_data, sizeof(usbhs_data)) < 0) {
-                printk(KERN_ERR "USBHS platform_device_add_data failed\n");
-                goto init_end;
+        oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
+        if (!oh[0]) {
+                pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
+                return;
         }
 
-        if (platform_device_register(&usbhs_device) < 0)
-                printk(KERN_ERR "USBHS platform_device_register failed\n");
+        oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
+        if (!oh[1]) {
+                pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
+                return;
+        }
 
-init_end:
-        return;
+        od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
+                                (void *)&usbhs_data, sizeof(usbhs_data),
+                                omap_uhhtll_latency,
+                                ARRAY_SIZE(omap_uhhtll_latency), false);
+        if (IS_ERR(od)) {
+                pr_err("Could not build hwmod devices %s,%s\n",
+                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+                return;
+        }
 }
 
 #else
@@ -570,5 +540,3 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 }
 
 #endif
-
-
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 267975086a7..8d5ed775dd5 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -93,6 +93,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
         if (cpu_is_omap3517() || cpu_is_omap3505()) {
                 oh_name = "am35x_otg_hs";
                 name = "musb-am35x";
+        } else if (cpu_is_ti81xx()) {
+                oh_name = "usb_otg_hs";
+                name = "musb-ti81xx";
         } else {
                 oh_name = "usb_otg_hs";
                 name = "musb-omap2430";
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 474559d5b07..c005e2f5e38 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -31,6 +31,14 @@
  * VDD data
  */
 
+/* OMAP3-common voltagedomain data */
+
+static struct voltagedomain omap3_voltdm_wkup = {
+        .name = "wakeup",
+};
+
+/* 34xx/36xx voltagedomain data */
+
 static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
         .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
         .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
@@ -63,10 +71,6 @@ static struct voltagedomain omap3_voltdm_core = {
         .vp = &omap3_vp_core,
 };
 
-static struct voltagedomain omap3_voltdm_wkup = {
-        .name = "wakeup",
-};
-
 static struct voltagedomain *voltagedomains_omap3[] __initdata = {
         &omap3_voltdm_mpu,
         &omap3_voltdm_core,
@@ -74,11 +78,30 @@ static struct voltagedomain *voltagedomains_omap3[] __initdata = {
         NULL,
 };
 
+/* AM35xx voltagedomain data */
+
+static struct voltagedomain am35xx_voltdm_mpu = {
+        .name = "mpu_iva",
+};
+
+static struct voltagedomain am35xx_voltdm_core = {
+        .name = "core",
+};
+
+static struct voltagedomain *voltagedomains_am35xx[] __initdata = {
+        &am35xx_voltdm_mpu,
+        &am35xx_voltdm_core,
+        &omap3_voltdm_wkup,
+        NULL,
+};
+
+
 static const char *sys_clk_name __initdata = "sys_ck";
 
 void __init omap3xxx_voltagedomains_init(void)
 {
         struct voltagedomain *voltdm;
+        struct voltagedomain **voltdms;
         int i;
 
         /*
@@ -93,8 +116,13 @@ void __init omap3xxx_voltagedomains_init(void)
                 omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
         }
 
-        for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)
+        if (cpu_is_omap3517() || cpu_is_omap3505())
+                voltdms = voltagedomains_am35xx;
+        else
+                voltdms = voltagedomains_omap3;
+
+        for (i = 0; voltdm = voltdms[i], voltdm; i++)
                 voltdm->sys_clk.name = sys_clk_name;
 
-        voltdm_init(voltagedomains_omap3);
+        voltdm_init(voltdms);
 };
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 5ceafdccc45..3638e5c12b7 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,8 +14,8 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
-#include <linux/errno.h>
 #include <mach/hardware.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
@@ -41,7 +41,6 @@
 /*
  * Generic Address Decode Windows bit settings
  */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCI              3
 #define TARGET_PCIE             4
@@ -57,27 +56,10 @@
 #define ATTR_DEV_BOOT           0xf
 #define ATTR_SRAM               0x0
 
-/*
- * Helpers to get DDR bank info
- */
-#define ORION5X_DDR_REG(x)      (ORION5X_DDR_VIRT_BASE | (x))
-#define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) << 3))
-#define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) << 3))
-
-/*
- * CPU Address Decode Windows registers
- */
-#define ORION5X_BRIDGE_REG(x)   (ORION5X_BRIDGE_VIRT_BASE | (x))
-#define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
-
-
-struct mbus_dram_target_info orion5x_mbus_dram_info;
 static int __initdata win_alloc_count;
 
-static int __init orion5x_cpu_win_can_remap(int win)
+static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
+                  const int win)
 {
         u32 dev, rev;
 
@@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win)
         return 0;
 }
 
-static int __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        if (win >= 8) {
-                printk(KERN_ERR "setup_cpu_win: trying to allocate "
-                                "window %d\n", win);
-                return -ENOSPC;
-        }
-
-        writel(base & 0xffff0000, CPU_WIN_BASE(win));
-        writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
-                CPU_WIN_CTRL(win));
-
-        if (orion5x_cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-
-                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
-                writel(0, CPU_WIN_REMAP_HI(win));
-        }
-        return 0;
-}
-
-void __init orion5x_setup_cpu_mbus_bridge(void)
-{
-        int i;
-        int cs;
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 8,
+        .cpu_win_can_remap = cpu_win_can_remap,
+        .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
+};
 
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
         /*
-         * First, disable and clear windows.
+         * Setup windows for PCI+PCIe IO+MEM space.
          */
-        for (i = 0; i < 8; i++) {
-                writel(0, CPU_WIN_BASE(i));
-                writel(0, CPU_WIN_CTRL(i));
-                if (orion5x_cpu_win_can_remap(i)) {
-                        writel(0, CPU_WIN_REMAP_LO(i));
-                        writel(0, CPU_WIN_REMAP_HI(i));
-                }
-        }
+        { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+          TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
+        },
+        { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
+          TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
+        },
+        { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
+          TARGET_PCIE, ATTR_PCIE_MEM, -1
+        },
+        { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
+          TARGET_PCI, ATTR_PCI_MEM, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
 
+void __init orion5x_setup_cpu_mbus_bridge(void)
+{
         /*
-         * Setup windows for PCI+PCIe IO+MEM space.
+         * Disable, clear and configure windows.
          */
-        setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
-                TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
-        setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
-                TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
-        setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
-                TARGET_PCIE, ATTR_PCIE_MEM, -1);
-        setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
-                TARGET_PCI, ATTR_PCI_MEM, -1);
+        orion_config_wins(&addr_map_cfg, addr_map_info);
         win_alloc_count = 4;
 
         /*
          * Setup MBUS dram target info.
          */
-        orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(DDR_BASE_CS(i));
-                u32 size = readl(DDR_SIZE_CS(i));
-
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-
-                        w = &orion5x_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        orion5x_mbus_dram_info.num_cs = cs;
+        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 }
 
 void __init orion5x_setup_dev0_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 }
 
 void __init orion5x_setup_dev1_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 }
 
 void __init orion5x_setup_dev2_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 }
 
 void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
-                      TARGET_PCIE, ATTR_PCIE_WA, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
+                            TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
 
-int __init orion5x_setup_sram_win(void)
+void __init orion5x_setup_sram_win(void)
 {
-        return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
-                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
+                            ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
+                            TARGET_SRAM, ATTR_SRAM, -1);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 41127e80cc1..0e28bae20bd 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -15,7 +15,6 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/delay.h>
@@ -32,6 +31,7 @@
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -72,8 +72,7 @@ void __init orion5x_map_io(void)
  ****************************************************************************/
 void __init orion5x_ehci0_init(void)
 {
-        orion_ehci_init(&orion5x_mbus_dram_info,
-                        ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
+        orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
 }
 
 
@@ -82,8 +81,7 @@ void __init orion5x_ehci0_init(void)
  ****************************************************************************/
 void __init orion5x_ehci1_init(void)
 {
-        orion_ehci_1_init(&orion5x_mbus_dram_info,
-                          ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
+        orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
 }
 
 
@@ -92,7 +90,7 @@ void __init orion5x_ehci1_init(void)
  ****************************************************************************/
 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
+        orion_ge00_init(eth_data,
                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
                         IRQ_ORION5X_ETH_ERR, orion5x_tclk);
 }
@@ -122,8 +120,7 @@ void __init orion5x_i2c_init(void)
  ****************************************************************************/
 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &orion5x_mbus_dram_info,
-                        ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
+        orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 }
 
 
@@ -159,8 +156,7 @@ void __init orion5x_uart1_init(void)
  ****************************************************************************/
 void __init orion5x_xor_init(void)
 {
-        orion_xor0_init(&orion5x_mbus_dram_info,
-                        ORION5X_XOR_PHYS_BASE,
+        orion_xor0_init(ORION5X_XOR_PHYS_BASE,
                         ORION5X_XOR_PHYS_BASE + 0x200,
                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 }
@@ -170,12 +166,7 @@ void __init orion5x_xor_init(void)
  ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-        int ret;
-
-        ret = orion5x_setup_sram_win();
-        if (ret)
-                return;
-
+        orion5x_setup_sram_win();
         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                           SZ_8K, IRQ_ORION5X_CESA);
 }
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 37ef18de61b..d2513ac79ff 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer;
  * functions to map its interfaces and by the machine-setup to map its on-
  * board devices. Details in /mach-orion/addr-map.c
  */
-extern struct mbus_dram_target_info orion5x_mbus_dram_info;
 void orion5x_setup_cpu_mbus_bridge(void);
 void orion5x_setup_dev_boot_win(u32 base, u32 size);
 void orion5x_setup_dev0_win(u32 base, u32 size);
 void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
-int orion5x_setup_sram_win(void);
+void orion5x_setup_sram_win(void);
 
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 0a28bbc7689..2745f5d95b3 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -69,7 +69,7 @@
  ******************************************************************************/
 
 #define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
-
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index b6ddd7a5db6..5b70026f478 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -10,7 +10,6 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <plat/mpp.h>
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index bc4a920e26e..a494c470e3e 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -18,6 +18,7 @@
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         /*
          * Generic PCIe unit setup.
          */
-        orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
+        orion_pcie_setup(PCIE_BASE);
 
         /*
          * Check whether to apply Orion-1/Orion-NAS PCIe config
@@ -477,7 +478,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
         /*
          * Point PCI unit MBUS decode windows to DRAM space.
          */
-        orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
+        orion5x_setup_pci_wins(&orion_mbus_dram_info);
 
         /*
          * Master + Slave enable
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index c550b636348..e5ec4a8d9bc 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,3 +1,2 @@
 obj-y   := common.o
 obj-y   += time.o
-obj-y   += io.o
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index ad871bd7b1a..a2e8ae8b582 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -7,6 +7,7 @@
  *
  * All enquiries to support@picochip.com
  */
+#include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
@@ -16,15 +17,49 @@
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
+#include <asm/mach/map.h>
 
 #include <mach/map.h>
 #include <mach/picoxcell_soc.h>
 
 #include "common.h"
 
+#define WDT_CTRL_REG_EN_MASK    (1 << 0)
+#define WDT_CTRL_REG_OFFS       (0x00)
+#define WDT_TIMEOUT_REG_OFFS    (0x04)
+static void __iomem *wdt_regs;
+
+/*
+ * The machine restart method can be called from an atomic context so we won't
+ * be able to ioremap the regs then.
+ */
+static void picoxcell_setup_restart(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                                         "snps,dw-apb-wdg");
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+
+        wdt_regs = of_iomap(np, 0);
+        WARN(!wdt_regs, "failed to remap watchdog regs");
+}
+
+static struct map_desc io_map __initdata = {
+        .virtual        = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
+        .pfn            = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
+        .length         = PICOXCELL_PERIPH_LENGTH,
+        .type           = MT_DEVICE,
+};
+
+static void __init picoxcell_map_io(void)
+{
+        iotable_init(&io_map, 1);
+}
+
 static void __init picoxcell_init_machine(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        picoxcell_setup_restart();
 }
 
 static const char *picoxcell_dt_match[] = {
@@ -43,12 +78,27 @@ static void __init picoxcell_init_irq(void)
         of_irq_init(vic_of_match);
 }
 
+static void picoxcell_wdt_restart(char mode, const char *cmd)
+{
+        /*
+         * Configure the watchdog to reset with the shortest possible timeout
+         * and give it chance to do the reset.
+         */
+        if (wdt_regs) {
+                writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS);
+                writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS);
+                /* No sleeping, possibly atomic. */
+                mdelay(500);
+        }
+}
+
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
         .map_io         = picoxcell_map_io,
-        .nr_irqs        = ARCH_NR_IRQS,
+        .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = picoxcell_init_irq,
         .handle_irq     = vic_handle_irq,
         .timer          = &picoxcell_timer,
         .init_machine   = picoxcell_init_machine,
         .dt_compat      = picoxcell_dt_match,
+        .restart        = picoxcell_wdt_restart,
 MACHINE_END
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
index 5263f0fa095..83d55ab956a 100644
--- a/arch/arm/mach-picoxcell/common.h
+++ b/arch/arm/mach-picoxcell/common.h
@@ -13,6 +13,5 @@
 #include <asm/mach/time.h>
 
 extern struct sys_timer picoxcell_timer;
-extern void picoxcell_map_io(void);
 
 #endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
index 4d13ed97091..59eac1ee282 100644
--- a/arch/arm/mach-picoxcell/include/mach/irqs.h
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -1,8 +1,6 @@
 /*
  * Copyright (c) 2011 Picochip Ltd., Jamie Iles
  *
- * This file contains the hardware definitions of the picoXcell SoC devices.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -16,10 +14,7 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-#define ARCH_NR_IRQS                    64
-#define NR_IRQS                         (128 + ARCH_NR_IRQS)
-
-#define IRQ_VIC0_BASE                   0
-#define IRQ_VIC1_BASE                   32
+/* We dynamically allocate our irq_desc's. */
+#define NR_IRQS                         0
 
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
deleted file mode 100644
index 40a8c178f10..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/memory.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
deleted file mode 100644
index 39e9b9e8cc3..00000000000
--- a/arch/arm/mach-picoxcell/io.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * All enquiries to support@picochip.com
- */
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/of.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/map.h>
-#include <mach/picoxcell_soc.h>
-
-#include "common.h"
-
-void __init picoxcell_map_io(void)
-{
-        struct map_desc io_map = {
-                .virtual        = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
-                .pfn            = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
-                .length         = PICOXCELL_PERIPH_LENGTH,
-                .type           = MT_DEVICE,
-        };
-
-        iotable_init(&io_map, 1);
-}
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index 4cb069fd9af..ccdac4b6a46 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -138,7 +138,7 @@ static void am200_cleanup(struct metronomefb_par *par)
 {
         int i;
 
-        free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
+        free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
 
         for (i = 0; i < ARRAY_SIZE(gpios); i++)
                 gpio_free(gpios[i]);
@@ -292,7 +292,7 @@ static int am200_setup_irq(struct fb_info *info)
 {
         int ret;
 
-        ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am200_handle_irq,
+        ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq,
                                 IRQF_DISABLED|IRQF_TRIGGER_FALLING,
                                 "AM200", info->par);
         if (ret)
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index fa8bad235d9..76c4b949403 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -176,7 +176,7 @@ static void am300_cleanup(struct broadsheetfb_par *par)
 {
         int i;
 
-        free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
+        free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
 
         for (i = 0; i < ARRAY_SIZE(gpios); i++)
                 gpio_free(gpios[i]);
@@ -240,7 +240,7 @@ static int am300_setup_irq(struct fb_info *info)
         int ret;
         struct broadsheetfb_par *par = info->par;
 
-        ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am300_handle_irq,
+        ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq,
                                 IRQF_DISABLED|IRQF_TRIGGER_RISING,
                                 "AM300", par);
         if (ret)
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 82514f5c38f..c35456f02ac 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -13,6 +13,7 @@
  *  published by the Free Software Foundation.
  */
 
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
@@ -179,7 +180,7 @@ static unsigned long balloon3_ac97_pin_config[] __initdata = {
 };
 
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
-        .irq            = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ),
+        .irq            = PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ),
 };
 
 
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index c2f0be040d2..c91727d1fe0 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -50,8 +50,8 @@ static struct resource capc7117_ide_resources[] = {
                .flags = IORESOURCE_MEM
         },
         [2] = {
-               .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)),
-               .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)),
+               .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)),
+               .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)),
                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING
         }
 };
@@ -80,7 +80,7 @@ static void __init capc7117_ide_init(void)
 static struct plat_serial8250_port ti16c752_platform_data[] = {
         [0] = {
                .mapbase = 0x14000000,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO78)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO78)),
                .irqflags = IRQF_TRIGGER_RISING,
                .flags = TI16C752_FLAGS,
                .iotype = UPIO_MEM,
@@ -89,7 +89,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = {
         },
         [1] = {
                .mapbase = 0x14000040,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO79)),
                .irqflags = IRQF_TRIGGER_RISING,
                .flags = TI16C752_FLAGS,
                .iotype = UPIO_MEM,
@@ -98,7 +98,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = {
         },
         [2] = {
                .mapbase = 0x14000080,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO80)),
                .irqflags = IRQF_TRIGGER_RISING,
                .flags = TI16C752_FLAGS,
                .iotype = UPIO_MEM,
@@ -107,7 +107,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = {
         },
         [3] = {
                .mapbase = 0x140000c0,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO81)),
                .irqflags = IRQF_TRIGGER_RISING,
                .flags = TI16C752_FLAGS,
                .iotype = UPIO_MEM,
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 13518a70539..431ef56700c 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -33,7 +33,7 @@
 /* GPIO IRQ usage */
 #define GPIO83_MMC_IRQ          (83)
 
-#define CMX270_MMC_IRQ          IRQ_GPIO(GPIO83_MMC_IRQ)
+#define CMX270_MMC_IRQ          PXA_GPIO_TO_IRQ(GPIO83_MMC_IRQ)
 
 /* MMC power enable */
 #define GPIO105_MMC_POWER       (105)
@@ -380,7 +380,7 @@ static struct spi_board_info cm_x270_spi_devices[] __initdata = {
                 .modalias               = "libertas_spi",
                 .max_speed_hz           = 13000000,
                 .bus_num                = 2,
-                .irq                    = gpio_to_irq(95),
+                .irq                    = PXA_GPIO_TO_IRQ(95),
                 .chip_select            = 0,
                 .controller_data        = &cm_x270_libertas_chip,
                 .platform_data          = &cm_x270_libertas_pdata,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index ec170a552c2..8fa4ad27edf 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -58,8 +58,8 @@ extern void cmx270_init(void);
 #define CMX255_GPIO_IT8152_IRQ  (0)
 #define CMX270_GPIO_IT8152_IRQ  (22)
 
-#define CMX255_ETHIRQ           IRQ_GPIO(GPIO22_ETHIRQ)
-#define CMX270_ETHIRQ           IRQ_GPIO(GPIO10_ETHIRQ)
+#define CMX255_ETHIRQ           PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ)
+#define CMX270_ETHIRQ           PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ)
 
 #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
 static struct resource cmx255_dm9000_resource[] = {
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 7236974da0b..4b981b82d2a 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -64,7 +64,7 @@
 #define GPIO82_MMC_IRQ          (82)
 #define GPIO85_MMC_WP           (85)
 
-#define CM_X300_MMC_IRQ         IRQ_GPIO(GPIO82_MMC_IRQ)
+#define CM_X300_MMC_IRQ         PXA_GPIO_TO_IRQ(GPIO82_MMC_IRQ)
 
 #define GPIO95_RTC_CS           (95)
 #define GPIO96_RTC_WR           (96)
@@ -229,8 +229,8 @@ static struct resource dm9000_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
-                .end    = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 6a685165c9f..29d5d541f60 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -218,8 +218,8 @@ static struct resource colibri_pxa270_dm9000_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ),
-                .end    = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ),
                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
         },
 };
@@ -249,7 +249,7 @@ static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = {
 };
 
 static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = {
-        .irq            = gpio_to_irq(GPIO113_COLIBRI_PXA270_TS_IRQ),
+        .irq            = PXA_GPIO_TO_IRQ(GPIO113_COLIBRI_PXA270_TS_IRQ),
 };
 
 static struct platform_device colibri_pxa270_ucb1400_device = {
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index c01059a61f3..0846d210cb0 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -78,8 +78,8 @@ static struct resource colibri_asix_resource[] = {
                 .flags = IORESOURCE_MEM,
         },
         [1] = {
-                .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
-                .end   = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
                 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
         }
 };
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index 5028f2300d5..6ad3359063a 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -115,8 +115,8 @@ static struct resource colibri_asix_resource[] = {
                 .flags = IORESOURCE_MEM,
         },
         [1] = {
-                .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
-                .end   = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
                 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
         }
 };
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 9d4dc5970b9..66600f05e43 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -531,7 +531,7 @@ static struct spi_board_info corgi_spi_devices[] = {
                 .chip_select    = 0,
                 .platform_data  = &corgi_ads7846_info,
                 .controller_data= &corgi_ads7846_chip,
-                .irq            = gpio_to_irq(CORGI_GPIO_TP_INT),
+                .irq            = PXA_GPIO_TO_IRQ(CORGI_GPIO_TP_INT),
         }, {
                 .modalias       = "corgi-lcd",
                 .max_speed_hz   = 50000,
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 29034778bfd..39e265cfc86 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
@@ -40,7 +41,9 @@ static struct gpio charger_gpios[] = {
         { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
         { CORGI_GPIO_CHRG_ON,     GPIOF_OUT_INIT_LOW, "Charger On" },
         { CORGI_GPIO_CHRG_UKN,    GPIOF_OUT_INIT_LOW, "Charger Unknown" },
+        { CORGI_GPIO_AC_IN,       GPIOF_IN, "Charger Detection" },
         { CORGI_GPIO_KEY_INT,     GPIOF_IN, "Key Interrupt" },
+        { CORGI_GPIO_WAKEUP,      GPIOF_IN, "System wakeup notification" },
 };
 
 static void corgi_charger_init(void)
@@ -90,7 +93,12 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm)
 {
         int is_resume = 0;
 
-        dev_dbg(sharpsl_pm.dev, "GPLR0 = %x,%x\n", GPLR0, PEDR);
+        dev_dbg(sharpsl_pm.dev, "PEDR = %x, GPIO_AC_IN = %d, "
+                "GPIO_CHRG_FULL = %d, GPIO_KEY_INT = %d, GPIO_WAKEUP = %d\n",
+                PEDR, gpio_get_value(CORGI_GPIO_AC_IN),
+                gpio_get_value(CORGI_GPIO_CHRG_FULL),
+                gpio_get_value(CORGI_GPIO_KEY_INT),
+                gpio_get_value(CORGI_GPIO_WAKEUP));
 
         if ((PEDR & GPIO_bit(CORGI_GPIO_AC_IN))) {
                 if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
@@ -124,14 +132,21 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm)
 
 static unsigned long corgi_charger_wakeup(void)
 {
-        return ~GPLR0 & ( GPIO_bit(CORGI_GPIO_AC_IN) | GPIO_bit(CORGI_GPIO_KEY_INT) | GPIO_bit(CORGI_GPIO_WAKEUP) );
+        unsigned long ret;
+
+        ret = (!gpio_get_value(CORGI_GPIO_AC_IN) << GPIO_bit(CORGI_GPIO_AC_IN))
+                | (!gpio_get_value(CORGI_GPIO_KEY_INT)
+                << GPIO_bit(CORGI_GPIO_KEY_INT))
+                | (!gpio_get_value(CORGI_GPIO_WAKEUP)
+                << GPIO_bit(CORGI_GPIO_WAKEUP));
+        return ret;
 }
 
 unsigned long corgipm_read_devdata(int type)
 {
         switch(type) {
         case SHARPSL_STATUS_ACIN:
-                return ((GPLR(CORGI_GPIO_AC_IN) & GPIO_bit(CORGI_GPIO_AC_IN)) != 0);
+                return !gpio_get_value(CORGI_GPIO_AC_IN);
         case SHARPSL_STATUS_LOCK:
                 return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
         case SHARPSL_STATUS_CHRGFULL:
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 2e0425404de..18fd177073f 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -415,9 +415,29 @@ static struct resource pxa_rtc_resources[] = {
         },
 };
 
+static struct resource sa1100_rtc_resources[] = {
+        [0] = {
+                .start  = 0x40900000,
+                .end    = 0x409000ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 struct platform_device sa1100_device_rtc = {
         .name           = "sa1100-rtc",
         .id             = -1,
+        .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
+        .resource       = sa1100_rtc_resources,
 };
 
 struct platform_device pxa_device_rtc = {
@@ -1051,6 +1071,36 @@ struct platform_device pxa3xx_device_ssp4 = {
 };
 #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
 
+struct resource pxa_resource_gpio[] = {
+        {
+                .start  = 0x40e00000,
+                .end    = 0x40e0ffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_GPIO0,
+                .end    = IRQ_GPIO0,
+                .name   = "gpio0",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_GPIO1,
+                .end    = IRQ_GPIO1,
+                .name   = "gpio1",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_GPIO_2_x,
+                .end    = IRQ_GPIO_2_x,
+                .name   = "gpio_mux",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
 void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 2fd5a8b3575..1475db10725 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -16,6 +16,7 @@ extern struct platform_device pxa_device_ficp;
 extern struct platform_device sa1100_device_rtc;
 extern struct platform_device pxa_device_rtc;
 extern struct platform_device pxa_device_ac97;
+extern struct platform_device pxa_device_gpio;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index bd396ba67af..d80c0ba9a09 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -70,7 +70,7 @@
 /* common  GPIOs */
 #define GPIO11_NAND_CS          (11)
 #define GPIO41_ETHIRQ           (41)
-#define EM_X270_ETHIRQ          IRQ_GPIO(GPIO41_ETHIRQ)
+#define EM_X270_ETHIRQ          PXA_GPIO_TO_IRQ(GPIO41_ETHIRQ)
 #define GPIO115_WLAN_PWEN       (115)
 #define GPIO19_WLAN_STRAP       (19)
 #define GPIO9_USB_VBUS_EN       (9)
@@ -805,7 +805,7 @@ static struct spi_board_info em_x270_spi_devices[] __initdata = {
                 .modalias               = "libertas_spi",
                 .max_speed_hz           = 13000000,
                 .bus_num                = 2,
-                .irq                    = IRQ_GPIO(116),
+                .irq                    = PXA_GPIO_TO_IRQ(116),
                 .chip_select            = 0,
                 .controller_data        = &em_x270_libertas_chip,
                 .platform_data          = &em_x270_libertas_pdata,
@@ -1203,7 +1203,7 @@ static struct da903x_platform_data em_x270_da9030_info = {
 
 static struct i2c_board_info em_x270_i2c_pmic_info = {
         I2C_BOARD_INFO("da9030", 0x49),
-        .irq = IRQ_GPIO(0),
+        .irq = PXA_GPIO_TO_IRQ(0),
         .platform_data = &em_x270_da9030_info,
 };
 
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 69473db9775..f79a610c62f 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -119,8 +119,8 @@ struct resource eseries_tmio_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ),
-                .end    = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ),
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index ce16bdae96d..fb9b62dcf4c 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -252,8 +252,8 @@ static struct resource asic3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ),
-                .end    = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ),
                 .flags  = IORESOURCE_IRQ,
         },
         /* SD part */
@@ -263,8 +263,8 @@ static struct resource asic3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [3] = {
-                .start  = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
-                .end    = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -587,7 +587,7 @@ static struct spi_board_info tsc2046_board_info[] __initdata = {
                 .modalias        = "ads7846",
                 .bus_num         = 2,
                 .max_speed_hz    = 2600000, /* 100 kHz sample rate */
-                .irq             = gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ),
+                .irq             = PXA_GPIO_TO_IRQ(GPIO58_HX4700_TSC2046_nPENIRQ),
                 .platform_data   = &tsc2046_info,
                 .controller_data = &tsc2046_chip,
         },
@@ -635,15 +635,15 @@ static struct resource power_supply_resources[] = {
                 .name  = "ac",
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                          IORESOURCE_IRQ_LOWEDGE,
-                .start = gpio_to_irq(GPIOD9_nAC_IN),
-                .end   = gpio_to_irq(GPIOD9_nAC_IN),
+                .start = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN),
+                .end   = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN),
         },
         [1] = {
                 .name  = "usb",
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                          IORESOURCE_IRQ_LOWEDGE,
-                .start = gpio_to_irq(GPIOD14_nUSBC_DETECT),
-                .end   = gpio_to_irq(GPIOD14_nUSBC_DETECT),
+                .start = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT),
+                .end   = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT),
         },
 };
 
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index e239b82c99d..67400192ed3 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -86,7 +86,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                 .chip_select     = 0,
                 .platform_data   = &mcp251x_info,
                 .controller_data = &mcp251x_chip_info1,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ1)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1)
         },
         {
                 .modalias        = "mcp2515",
@@ -95,7 +95,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                 .chip_select     = 1,
                 .platform_data   = &mcp251x_info,
                 .controller_data = &mcp251x_chip_info2,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ2)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
         },
         {
                 .modalias        = "mcp2515",
@@ -104,7 +104,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                 .chip_select     = 0,
                 .platform_data   = &mcp251x_info,
                 .controller_data = &mcp251x_chip_info3,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ3)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
         },
         {
                 .modalias        = "mcp2515",
@@ -113,7 +113,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                 .chip_select     = 1,
                 .platform_data   = &mcp251x_info,
                 .controller_data = &mcp251x_chip_info4,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ4)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
         }
 };
 
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index fbabd84e110..8af1840e12c 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -75,8 +75,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_GPIO(4),
-                .end    = IRQ_GPIO(4),
+                .start  = PXA_GPIO_TO_IRQ(4),
+                .end    = PXA_GPIO_TO_IRQ(4),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 6d7eab3d086..f02fa1e6ba8 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -172,9 +172,9 @@ enum balloon3_features {
 /* Balloon3 Interrupts */
 #define BALLOON3_IRQ(x)         (IRQ_BOARD_START + (x))
 
-#define BALLOON3_AUX_NIRQ       IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
-#define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
-#define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
+#define BALLOON3_AUX_NIRQ       PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
+#define BALLOON3_CODEC_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
+#define BALLOON3_S0_CD_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD)
 
 #define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 16)
 
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 5dfd1195a5a..f3c3493b468 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -66,18 +66,18 @@
 /*
  * Corgi Interrupts
  */
-#define CORGI_IRQ_GPIO_KEY_INT          IRQ_GPIO(0)
-#define CORGI_IRQ_GPIO_AC_IN            IRQ_GPIO(1)
-#define CORGI_IRQ_GPIO_WAKEUP           IRQ_GPIO(3)
-#define CORGI_IRQ_GPIO_AK_INT           IRQ_GPIO(4)
-#define CORGI_IRQ_GPIO_TP_INT           IRQ_GPIO(5)
-#define CORGI_IRQ_GPIO_nSD_DETECT       IRQ_GPIO(9)
-#define CORGI_IRQ_GPIO_nSD_INT          IRQ_GPIO(10)
-#define CORGI_IRQ_GPIO_MAIN_BAT_LOW     IRQ_GPIO(11)
-#define CORGI_IRQ_GPIO_CF_CD            IRQ_GPIO(14)
-#define CORGI_IRQ_GPIO_CHRG_FULL        IRQ_GPIO(16)    /* Battery fully charged */
-#define CORGI_IRQ_GPIO_CF_IRQ           IRQ_GPIO(17)
-#define CORGI_IRQ_GPIO_KEY_SENSE(a)     IRQ_GPIO(58+(a))        /* Keyboard Sense lines */
+#define CORGI_IRQ_GPIO_KEY_INT          PXA_GPIO_TO_IRQ(0)
+#define CORGI_IRQ_GPIO_AC_IN            PXA_GPIO_TO_IRQ(1)
+#define CORGI_IRQ_GPIO_WAKEUP           PXA_GPIO_TO_IRQ(3)
+#define CORGI_IRQ_GPIO_AK_INT           PXA_GPIO_TO_IRQ(4)
+#define CORGI_IRQ_GPIO_TP_INT           PXA_GPIO_TO_IRQ(5)
+#define CORGI_IRQ_GPIO_nSD_DETECT       PXA_GPIO_TO_IRQ(9)
+#define CORGI_IRQ_GPIO_nSD_INT          PXA_GPIO_TO_IRQ(10)
+#define CORGI_IRQ_GPIO_MAIN_BAT_LOW     PXA_GPIO_TO_IRQ(11)
+#define CORGI_IRQ_GPIO_CF_CD            PXA_GPIO_TO_IRQ(14)
+#define CORGI_IRQ_GPIO_CHRG_FULL        PXA_GPIO_TO_IRQ(16)     /* Battery fully charged */
+#define CORGI_IRQ_GPIO_CF_IRQ           PXA_GPIO_TO_IRQ(17)
+#define CORGI_IRQ_GPIO_KEY_SENSE(a)     PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */
 
 
 /*
@@ -98,7 +98,7 @@
                         CORGI_SCP_MIC_BIAS )
 #define CORGI_SCOOP_IO_OUT      ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
 
-#define CORGI_SCOOP_GPIO_BASE           (NR_BUILTIN_GPIO)
+#define CORGI_SCOOP_GPIO_BASE           (PXA_NR_BUILTIN_GPIO)
 #define CORGI_GPIO_LED_GREEN            (CORGI_SCOOP_GPIO_BASE + 0)
 #define CORGI_GPIO_SWA                  (CORGI_SCOOP_GPIO_BASE + 1)  /* Hinge Switch A */
 #define CORGI_GPIO_SWB                  (CORGI_SCOOP_GPIO_BASE + 2)  /* Hinge Switch B */
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h
index 747ab1a71f2..2628e7b7211 100644
--- a/arch/arm/mach-pxa/include/mach/csb726.h
+++ b/arch/arm/mach-pxa/include/mach/csb726.h
@@ -19,8 +19,8 @@
 #define CSB726_FLASH_SIZE       (64 * 1024 * 1024)
 #define CSB726_FLASH_uMON       (8 * 1024 * 1024)
 
-#define CSB726_IRQ_LAN          gpio_to_irq(CSB726_GPIO_IRQ_LAN)
-#define CSB726_IRQ_SM501        gpio_to_irq(CSB726_GPIO_IRQ_SM501)
+#define CSB726_IRQ_LAN          PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN)
+#define CSB726_IRQ_SM501        PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501)
 
 #endif
 
diff --git a/arch/arm/mach-pxa/include/mach/gpio-pxa.h b/arch/arm/mach-pxa/include/mach/gpio-pxa.h
deleted file mode 100644
index 41b4c93a96c..00000000000
--- a/arch/arm/mach-pxa/include/mach/gpio-pxa.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __MACH_PXA_GPIO_PXA_H
-#define __MACH_PXA_GPIO_PXA_H
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#define GPIO_REGS_VIRT  io_p2v(0x40E00000)
-
-#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-#define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
-
-/* GPIO Pin Level Registers */
-#define GPLR0           GPIO_REG(BANK_OFF(0) + 0x00)
-#define GPLR1           GPIO_REG(BANK_OFF(1) + 0x00)
-#define GPLR2           GPIO_REG(BANK_OFF(2) + 0x00)
-#define GPLR3           GPIO_REG(BANK_OFF(3) + 0x00)
-
-/* GPIO Pin Direction Registers */
-#define GPDR0           GPIO_REG(BANK_OFF(0) + 0x0c)
-#define GPDR1           GPIO_REG(BANK_OFF(1) + 0x0c)
-#define GPDR2           GPIO_REG(BANK_OFF(2) + 0x0c)
-#define GPDR3           GPIO_REG(BANK_OFF(3) + 0x0c)
-
-/* GPIO Pin Output Set Registers */
-#define GPSR0           GPIO_REG(BANK_OFF(0) + 0x18)
-#define GPSR1           GPIO_REG(BANK_OFF(1) + 0x18)
-#define GPSR2           GPIO_REG(BANK_OFF(2) + 0x18)
-#define GPSR3           GPIO_REG(BANK_OFF(3) + 0x18)
-
-/* GPIO Pin Output Clear Registers */
-#define GPCR0           GPIO_REG(BANK_OFF(0) + 0x24)
-#define GPCR1           GPIO_REG(BANK_OFF(1) + 0x24)
-#define GPCR2           GPIO_REG(BANK_OFF(2) + 0x24)
-#define GPCR3           GPIO_REG(BANK_OFF(3) + 0x24)
-
-/* GPIO Rising Edge Detect Registers */
-#define GRER0           GPIO_REG(BANK_OFF(0) + 0x30)
-#define GRER1           GPIO_REG(BANK_OFF(1) + 0x30)
-#define GRER2           GPIO_REG(BANK_OFF(2) + 0x30)
-#define GRER3           GPIO_REG(BANK_OFF(3) + 0x30)
-
-/* GPIO Falling Edge Detect Registers */
-#define GFER0           GPIO_REG(BANK_OFF(0) + 0x3c)
-#define GFER1           GPIO_REG(BANK_OFF(1) + 0x3c)
-#define GFER2           GPIO_REG(BANK_OFF(2) + 0x3c)
-#define GFER3           GPIO_REG(BANK_OFF(3) + 0x3c)
-
-/* GPIO Edge Detect Status Registers */
-#define GEDR0           GPIO_REG(BANK_OFF(0) + 0x48)
-#define GEDR1           GPIO_REG(BANK_OFF(1) + 0x48)
-#define GEDR2           GPIO_REG(BANK_OFF(2) + 0x48)
-#define GEDR3           GPIO_REG(BANK_OFF(3) + 0x48)
-
-/* GPIO Alternate Function Select Registers */
-#define GAFR0_L         GPIO_REG(0x0054)
-#define GAFR0_U         GPIO_REG(0x0058)
-#define GAFR1_L         GPIO_REG(0x005C)
-#define GAFR1_U         GPIO_REG(0x0060)
-#define GAFR2_L         GPIO_REG(0x0064)
-#define GAFR2_U         GPIO_REG(0x0068)
-#define GAFR3_L         GPIO_REG(0x006C)
-#define GAFR3_U         GPIO_REG(0x0070)
-
-/* More handy macros.  The argument is a literal GPIO number. */
-
-#define GPIO_bit(x)     (1 << ((x) & 0x1f))
-
-#define GPLR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
-#define GPDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
-#define GPSR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
-#define GPCR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
-#define GRER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
-#define GFER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
-#define GEDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
-#define GAFR(x)         GPIO_REG(0x54 + (((x) & 0x70) >> 2))
-
-
-#define NR_BUILTIN_GPIO         PXA_GPIO_IRQ_NUM
-
-#define gpio_to_bank(gpio)      ((gpio) >> 5)
-
-#ifdef CONFIG_CPU_PXA26x
-/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
- * as well as their Alternate Function value being '1' for GPIO in GAFRx.
- */
-static inline int __gpio_is_inverted(unsigned gpio)
-{
-        return cpu_is_pxa25x() && gpio > 85;
-}
-#else
-static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
-#endif
-
-/*
- * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
- * function of a GPIO, and GPDRx cannot be altered once configured. It
- * is attributed as "occupied" here (I know this terminology isn't
- * accurate, you are welcome to propose a better one :-)
- */
-static inline int __gpio_is_occupied(unsigned gpio)
-{
-        if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
-                int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
-                int dir = GPDR(gpio) & GPIO_bit(gpio);
-
-                if (__gpio_is_inverted(gpio))
-                        return af != 1 || dir == 0;
-                else
-                        return af != 0 || dir != 0;
-        } else
-                return GPDR(gpio) & GPIO_bit(gpio);
-}
-
-#include <plat/gpio-pxa.h>
-#endif /* __MACH_PXA_GPIO_PXA_H */
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index 004cade7bb1..0248e433bc9 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -25,24 +25,8 @@
 #define __ASM_ARCH_PXA_GPIO_H
 
 #include <asm-generic/gpio.h>
-/* The defines for the driver are needed for the accelerated accessors */
-#include "gpio-pxa.h"
 
-#define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
+#include <mach/irqs.h>
+#include <mach/hardware.h>
 
-static inline int irq_to_gpio(unsigned int irq)
-{
-        int gpio;
-
-        if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1)
-                return irq - IRQ_GPIO0;
-
-        gpio = irq - PXA_GPIO_IRQ_BASE;
-        if (gpio >= 2 && gpio < NR_BUILTIN_GPIO)
-                return gpio;
-
-        return -1;
-}
-
-#include <plat/gpio.h>
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 9b898680b20..dba14b6503a 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -24,7 +24,7 @@ has detected a cable insertion; driven low otherwise. */
 #define GPIO_GUMSTIX_USB_GPIOx          41
 
 /* usb state change */
-#define GUMSTIX_USB_INTR_IRQ            IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
+#define GUMSTIX_USB_INTR_IRQ            PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
 
 #define GPIO_GUMSTIX_USB_GPIOn_MD       (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
 #define GPIO_GUMSTIX_USB_GPIOx_CON_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
@@ -35,7 +35,7 @@ has detected a cable insertion; driven low otherwise. */
  */
 #define GUMSTIX_GPIO_nSD_WP             22 /* SD Write Protect */
 #define GUMSTIX_GPIO_nSD_DETECT         11 /* MMC/SD Card Detect */
-#define GUMSTIX_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
+#define GUMSTIX_IRQ_GPIO_nSD_DETECT     PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT)
 
 /*
  * SMC Ethernet definitions
@@ -49,10 +49,10 @@ has detected a cable insertion; driven low otherwise. */
 
 #define GPIO_GUMSTIX_ETH0               36
 #define GPIO_GUMSTIX_ETH0_MD            (GPIO_GUMSTIX_ETH0 | GPIO_IN)
-#define GUMSTIX_ETH0_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH0)
+#define GUMSTIX_ETH0_IRQ                PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
 #define GPIO_GUMSTIX_ETH1               27
 #define GPIO_GUMSTIX_ETH1_MD            (GPIO_GUMSTIX_ETH1 | GPIO_IN)
-#define GUMSTIX_ETH1_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH1)
+#define GUMSTIX_ETH1_IRQ                PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
 
 
 /* CF reset line */
@@ -63,18 +63,18 @@ has detected a cable insertion; driven low otherwise. */
 #define GPIO4_nSTSCHG                   GPIO4_nBVD1
 #define GPIO11_nCD                      11
 #define GPIO26_PRDY_nBSY                26
-#define GUMSTIX_S0_nSTSCHG_IRQ          IRQ_GPIO(GPIO4_nSTSCHG)
-#define GUMSTIX_S0_nCD_IRQ              IRQ_GPIO(GPIO11_nCD)
-#define GUMSTIX_S0_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO26_PRDY_nBSY)
+#define GUMSTIX_S0_nSTSCHG_IRQ          PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
+#define GUMSTIX_S0_nCD_IRQ              PXA_GPIO_TO_IRQ(GPIO11_nCD)
+#define GUMSTIX_S0_PRDY_nBSY_IRQ        PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
 
 /* CF slot 1 */
 #define GPIO18_nBVD1                    18
 #define GPIO18_nSTSCHG                  GPIO18_nBVD1
 #define GPIO36_nCD                      36
 #define GPIO27_PRDY_nBSY                27
-#define GUMSTIX_S1_nSTSCHG_IRQ          IRQ_GPIO(GPIO18_nSTSCHG)
-#define GUMSTIX_S1_nCD_IRQ              IRQ_GPIO(GPIO36_nCD)
-#define GUMSTIX_S1_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO27_PRDY_nBSY)
+#define GUMSTIX_S1_nSTSCHG_IRQ          PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
+#define GUMSTIX_S1_nCD_IRQ              PXA_GPIO_TO_IRQ(GPIO36_nCD)
+#define GUMSTIX_S1_PRDY_nBSY_IRQ        PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
 
 /* CF GPIO line modes */
 #define GPIO4_nSTSCHG_MD                (GPIO4_nSTSCHG | GPIO_IN)
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
index 37408449ec2..8bc02913517 100644
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -15,7 +15,7 @@
 #include <linux/gpio.h>
 #include <linux/mfd/asic3.h>
 
-#define HX4700_ASIC3_GPIO_BASE  NR_BUILTIN_GPIO
+#define HX4700_ASIC3_GPIO_BASE  PXA_NR_BUILTIN_GPIO
 #define HX4700_EGPIO_BASE       (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
 #define HX4700_NR_IRQS          (IRQ_BOARD_START + 70)
 
diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h
index 5eff96fcc94..22a96f87232 100644
--- a/arch/arm/mach-pxa/include/mach/idp.h
+++ b/arch/arm/mach-pxa/include/mach/idp.h
@@ -131,28 +131,26 @@
 #define PCC_VS2         (1 << 1)
 #define PCC_VS1         (1 << 0)
 
-#define PCC_DETECT(x)   (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
-
 /* A listing of interrupts used by external hardware devices */
 
-#define TOUCH_PANEL_IRQ                 IRQ_GPIO(5)
-#define IDE_IRQ                         IRQ_GPIO(21)
+#define TOUCH_PANEL_IRQ                 PXA_GPIO_TO_IRQ(5)
+#define IDE_IRQ                         PXA_GPIO_TO_IRQ(21)
 
 #define TOUCH_PANEL_IRQ_EDGE            IRQ_TYPE_EDGE_FALLING
 
-#define ETHERNET_IRQ                    IRQ_GPIO(4)
+#define ETHERNET_IRQ                    PXA_GPIO_TO_IRQ(4)
 #define ETHERNET_IRQ_EDGE               IRQ_TYPE_EDGE_RISING
 
 #define IDE_IRQ_EDGE                    IRQ_TYPE_EDGE_RISING
 
-#define PCMCIA_S0_CD_VALID              IRQ_GPIO(7)
+#define PCMCIA_S0_CD_VALID              PXA_GPIO_TO_IRQ(7)
 #define PCMCIA_S0_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
 
-#define PCMCIA_S1_CD_VALID              IRQ_GPIO(8)
+#define PCMCIA_S1_CD_VALID              PXA_GPIO_TO_IRQ(8)
 #define PCMCIA_S1_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
 
-#define PCMCIA_S0_RDYINT                IRQ_GPIO(19)
-#define PCMCIA_S1_RDYINT                IRQ_GPIO(22)
+#define PCMCIA_S0_RDYINT                PXA_GPIO_TO_IRQ(19)
+#define PCMCIA_S1_RDYINT                PXA_GPIO_TO_IRQ(22)
 
 
 /*
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 7cc5a781e99..32975adf3ca 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -88,10 +88,8 @@
 #define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
 
 #define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
-#define PXA_GPIO_IRQ_NUM        (192)
-
-#define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
-#define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
+#define PXA_NR_BUILTIN_GPIO     (192)
+#define PXA_GPIO_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
 
 /*
  * The following interrupts are for board specific purposes. Since
@@ -100,7 +98,7 @@
  * By default, no board IRQ is reserved. It should be finished in
  * custom board since sparse IRQ is already enabled.
  */
-#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
+#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO)
 
 #define NR_IRQS                 (IRQ_BOARD_START)
 
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index b6238cbd8ae..8066be54e9f 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -1,13 +1,11 @@
 #ifndef __ASM_ARCH_LITTLETON_H
 #define __ASM_ARCH_LITTLETON_H
 
-#include <mach/gpio-pxa.h>
-
 #define LITTLETON_ETH_PHYS      0x30000000
 
 #define LITTLETON_GPIO_LCD_CS   (17)
 
-#define EXT0_GPIO_BASE  (NR_BUILTIN_GPIO)
+#define EXT0_GPIO_BASE  (PXA_NR_BUILTIN_GPIO)
 #define EXT0_GPIO(x)    (EXT0_GPIO_BASE + (x))
 
 #define LITTLETON_NR_IRQS       (IRQ_BOARD_START + 8)
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 7cbfc5d3f9d..ba6a6e1d29e 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -78,7 +78,7 @@
  * CPLD EGPIOs
  */
 
-#define MAGICIAN_EGPIO_BASE                     NR_BUILTIN_GPIO
+#define MAGICIAN_EGPIO_BASE                     PXA_NR_BUILTIN_GPIO
 #define MAGICIAN_EGPIO(reg,bit) \
         (MAGICIAN_EGPIO_BASE + 8*reg + bit)
 
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
index ae536e86d8e..2c447133657 100644
--- a/arch/arm/mach-pxa/include/mach/palmld.h
+++ b/arch/arm/mach-pxa/include/mach/palmld.h
@@ -68,10 +68,10 @@
 /* 20, 53 and 86 are usb related too */
 
 /* INTERRUPTS */
-#define IRQ_GPIO_PALMLD_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET)
-#define IRQ_GPIO_PALMLD_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N)
-#define IRQ_GPIO_PALMLD_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ)
-#define IRQ_GPIO_PALMLD_IDE_IRQ         IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ)
+#define IRQ_GPIO_PALMLD_GPIO_RESET      PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET)
+#define IRQ_GPIO_PALMLD_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N)
+#define IRQ_GPIO_PALMLD_WM9712_IRQ      PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ)
+#define IRQ_GPIO_PALMLD_IDE_IRQ         PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ)
 
 
 /** HERE ARE INIT VALUES **/
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h
index 6baf7469d4e..0bd4f036c72 100644
--- a/arch/arm/mach-pxa/include/mach/palmt5.h
+++ b/arch/arm/mach-pxa/include/mach/palmt5.h
@@ -48,10 +48,10 @@
 #define GPIO_NR_PALMT5_BT_RESET                 83
 
 /* INTERRUPTS */
-#define IRQ_GPIO_PALMT5_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N)
-#define IRQ_GPIO_PALMT5_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ)
-#define IRQ_GPIO_PALMT5_USB_DETECT      IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT)
-#define IRQ_GPIO_PALMT5_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET)
+#define IRQ_GPIO_PALMT5_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N)
+#define IRQ_GPIO_PALMT5_WM9712_IRQ      PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ)
+#define IRQ_GPIO_PALMT5_USB_DETECT      PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT)
+#define IRQ_GPIO_PALMT5_GPIO_RESET      PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET)
 
 /** HERE ARE INIT VALUES **/
 
diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h
index 3f9dd3fd463..c383a21680b 100644
--- a/arch/arm/mach-pxa/include/mach/palmtc.h
+++ b/arch/arm/mach-pxa/include/mach/palmtc.h
@@ -52,8 +52,8 @@
 #define GPIO_NR_PALMTC_IR_DISABLE       45
 
 /* IRQs */
-#define IRQ_GPIO_PALMTC_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N)
-#define IRQ_GPIO_PALMTC_WLAN_READY      IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY)
+#define IRQ_GPIO_PALMTC_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N)
+#define IRQ_GPIO_PALMTC_WLAN_READY      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY)
 
 /* UCB1400 GPIOs */
 #define GPIO_NR_PALMTC_POWER_DETECT     (0x80 | 0x00)
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index 7074a6ed46c..f2e53038025 100644
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
@@ -62,10 +62,10 @@
 #define GPIO_NR_PALMTX_NAND_BUFFER_DIR          79
 
 /* INTERRUPTS */
-#define IRQ_GPIO_PALMTX_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
-#define IRQ_GPIO_PALMTX_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
-#define IRQ_GPIO_PALMTX_USB_DETECT      IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
-#define IRQ_GPIO_PALMTX_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
+#define IRQ_GPIO_PALMTX_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N)
+#define IRQ_GPIO_PALMTX_WM9712_IRQ      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ)
+#define IRQ_GPIO_PALMTX_USB_DETECT      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT)
+#define IRQ_GPIO_PALMTX_GPIO_RESET      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET)
 
 /** HERE ARE INIT VALUES **/
 
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 4bac588478a..6bf28de228b 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -34,7 +34,7 @@
 
 /* I2C RTC */
 #define PCM027_RTC_IRQ_GPIO     0
-#define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
+#define PCM027_RTC_IRQ          PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO)
 #define PCM027_RTC_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
 #define ADR_PCM027_RTC          0x51    /* I2C address */
 
@@ -43,21 +43,21 @@
 
 /* Ethernet chip (SMSC91C111) */
 #define PCM027_ETH_IRQ_GPIO     52
-#define PCM027_ETH_IRQ          IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
+#define PCM027_ETH_IRQ          PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO)
 #define PCM027_ETH_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
 #define PCM027_ETH_PHYS         PXA_CS5_PHYS
 #define PCM027_ETH_SIZE         (1*1024*1024)
 
 /* CAN controller SJA1000 (unsupported yet) */
 #define PCM027_CAN_IRQ_GPIO     114
-#define PCM027_CAN_IRQ          IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
+#define PCM027_CAN_IRQ          PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO)
 #define PCM027_CAN_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
 #define PCM027_CAN_PHYS         0x22000000
 #define PCM027_CAN_SIZE         0x100
 
 /* SPI GPIO expander (unsupported yet) */
 #define PCM027_EGPIO_IRQ_GPIO   27
-#define PCM027_EGPIO_IRQ        IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
+#define PCM027_EGPIO_IRQ        PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO)
 #define PCM027_EGPIO_IRQ_EDGE   IRQ_TYPE_EDGE_FALLING
 #define PCM027_EGPIO_CS         24
 /*
diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
index 8a4383b776d..d72791695b2 100644
--- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
+++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
@@ -28,14 +28,14 @@
 
 /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
 #define PCM990_CTRL_INT_IRQ_GPIO        9
-#define PCM990_CTRL_INT_IRQ             IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
+#define PCM990_CTRL_INT_IRQ             PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
 #define PCM990_CTRL_INT_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
 #define PCM990_CTRL_PHYS                PXA_CS1_PHYS    /* 16-Bit */
 #define PCM990_CTRL_BASE                0xea000000
 #define PCM990_CTRL_SIZE                (1*1024*1024)
 
 #define PCM990_CTRL_PWR_IRQ_GPIO        14
-#define PCM990_CTRL_PWR_IRQ             IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
+#define PCM990_CTRL_PWR_IRQ             PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO)
 #define PCM990_CTRL_PWR_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
 
 /* visible CPLD (U7) registers */
@@ -132,7 +132,7 @@
  * IDE
  */
 #define PCM990_IDE_IRQ_GPIO     13
-#define PCM990_IDE_IRQ          IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
+#define PCM990_IDE_IRQ          PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO)
 #define PCM990_IDE_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
 #define PCM990_IDE_PLD_PHYS     0x20000000      /* 16 bit wide */
 #define PCM990_IDE_PLD_BASE     0xee000000
@@ -188,11 +188,11 @@
  * Compact Flash
  */
 #define PCM990_CF_IRQ_GPIO      11
-#define PCM990_CF_IRQ           IRQ_GPIO(PCM990_CF_IRQ_GPIO)
+#define PCM990_CF_IRQ           PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO)
 #define PCM990_CF_IRQ_EDGE      IRQ_TYPE_EDGE_RISING
 
 #define PCM990_CF_CD_GPIO       12
-#define PCM990_CF_CD            IRQ_GPIO(PCM990_CF_CD_GPIO)
+#define PCM990_CF_CD            PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO)
 #define PCM990_CF_CD_EDGE       IRQ_TYPE_EDGE_RISING
 
 #define PCM990_CF_PLD_PHYS      0x30000000      /* 16 bit wide */
@@ -258,14 +258,14 @@
  * Wolfson AC97 Touch
  */
 #define PCM990_AC97_IRQ_GPIO    10
-#define PCM990_AC97_IRQ         IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
+#define PCM990_AC97_IRQ         PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO)
 #define PCM990_AC97_IRQ_EDGE    IRQ_TYPE_EDGE_RISING
 
 /*
  * MMC phyCORE
  */
 #define PCM990_MMC0_IRQ_GPIO    9
-#define PCM990_MMC0_IRQ         IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
+#define PCM990_MMC0_IRQ         PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO)
 #define PCM990_MMC0_IRQ_EDGE    IRQ_TYPE_EDGE_FALLING
 
 /*
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 83d1cfd00fc..f32ff75dcca 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -47,18 +47,18 @@
 #define POODLE_GPIO_DISCHARGE_ON        (42) /* Enable battery discharge */
 
 /* PXA GPIOs */
-#define POODLE_IRQ_GPIO_ON_KEY          IRQ_GPIO(0)
-#define POODLE_IRQ_GPIO_AC_IN           IRQ_GPIO(1)
-#define POODLE_IRQ_GPIO_HP_IN           IRQ_GPIO(4)
-#define POODLE_IRQ_GPIO_CO              IRQ_GPIO(16)
-#define POODLE_IRQ_GPIO_TP_INT          IRQ_GPIO(5)
-#define POODLE_IRQ_GPIO_WAKEUP          IRQ_GPIO(11)
-#define POODLE_IRQ_GPIO_GA_INT          IRQ_GPIO(10)
-#define POODLE_IRQ_GPIO_CF_IRQ          IRQ_GPIO(17)
-#define POODLE_IRQ_GPIO_CF_CD           IRQ_GPIO(14)
-#define POODLE_IRQ_GPIO_nSD_INT         IRQ_GPIO(8)
-#define POODLE_IRQ_GPIO_nSD_DETECT      IRQ_GPIO(9)
-#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO(13)
+#define POODLE_IRQ_GPIO_ON_KEY          PXA_GPIO_TO_IRQ(0)
+#define POODLE_IRQ_GPIO_AC_IN           PXA_GPIO_TO_IRQ(1)
+#define POODLE_IRQ_GPIO_HP_IN           PXA_GPIO_TO_IRQ(4)
+#define POODLE_IRQ_GPIO_CO              PXA_GPIO_TO_IRQ(16)
+#define POODLE_IRQ_GPIO_TP_INT          PXA_GPIO_TO_IRQ(5)
+#define POODLE_IRQ_GPIO_WAKEUP          PXA_GPIO_TO_IRQ(11)
+#define POODLE_IRQ_GPIO_GA_INT          PXA_GPIO_TO_IRQ(10)
+#define POODLE_IRQ_GPIO_CF_IRQ          PXA_GPIO_TO_IRQ(17)
+#define POODLE_IRQ_GPIO_CF_CD           PXA_GPIO_TO_IRQ(14)
+#define POODLE_IRQ_GPIO_nSD_INT         PXA_GPIO_TO_IRQ(8)
+#define POODLE_IRQ_GPIO_nSD_DETECT      PXA_GPIO_TO_IRQ(9)
+#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    PXA_GPIO_TO_IRQ(13)
 
 /* SCOOP GPIOs */
 #define POODLE_SCOOP_CHARGE_ON  SCOOP_GPCR_PA11
@@ -71,7 +71,7 @@
 #define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
 #define POODLE_SCOOP_IO_OUT     ( 0 )
 
-#define POODLE_SCOOP_GPIO_BASE  (NR_BUILTIN_GPIO)
+#define POODLE_SCOOP_GPIO_BASE  (PXA_NR_BUILTIN_GPIO)
 #define POODLE_GPIO_CHARGE_ON   (POODLE_SCOOP_GPIO_BASE + 0)
 #define POODLE_GPIO_CP401       (POODLE_SCOOP_GPIO_BASE + 2)
 #define POODLE_GPIO_VPEN        (POODLE_SCOOP_GPIO_BASE + 7)
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index 685749a51c4..0bfe6507c95 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -108,7 +108,7 @@
 #define SPITZ_SCP_SUS_CLR     (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
 #define SPITZ_SCP_SUS_SET     0
 
-#define SPITZ_SCP_GPIO_BASE     (NR_BUILTIN_GPIO)
+#define SPITZ_SCP_GPIO_BASE     (PXA_NR_BUILTIN_GPIO)
 #define SPITZ_GPIO_LED_GREEN    (SPITZ_SCP_GPIO_BASE + 0)
 #define SPITZ_GPIO_JK_B         (SPITZ_SCP_GPIO_BASE + 1)
 #define SPITZ_GPIO_CHRG_ON      (SPITZ_SCP_GPIO_BASE + 2)
@@ -140,7 +140,7 @@
                              SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
 #define SPITZ_SCP2_SUS_SET  (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
 
-#define SPITZ_SCP2_GPIO_BASE            (NR_BUILTIN_GPIO + 12)
+#define SPITZ_SCP2_GPIO_BASE            (PXA_NR_BUILTIN_GPIO + 12)
 #define SPITZ_GPIO_IR_ON                (SPITZ_SCP2_GPIO_BASE + 0)
 #define SPITZ_GPIO_AKIN_PULLUP          (SPITZ_SCP2_GPIO_BASE + 1)
 #define SPITZ_GPIO_RESERVED_1           (SPITZ_SCP2_GPIO_BASE + 2)
@@ -152,7 +152,7 @@
 #define SPITZ_GPIO_MIC_BIAS             (SPITZ_SCP2_GPIO_BASE + 8)
 
 /* Akita IO Expander GPIOs */
-#define AKITA_IOEXP_GPIO_BASE           (NR_BUILTIN_GPIO + 12)
+#define AKITA_IOEXP_GPIO_BASE           (PXA_NR_BUILTIN_GPIO + 12)
 #define AKITA_GPIO_RESERVED_0           (AKITA_IOEXP_GPIO_BASE + 0)
 #define AKITA_GPIO_RESERVED_1           (AKITA_IOEXP_GPIO_BASE + 1)
 #define AKITA_GPIO_MIC_BIAS             (AKITA_IOEXP_GPIO_BASE + 2)
@@ -164,23 +164,23 @@
 
 /* Spitz IRQ Definitions */
 
-#define SPITZ_IRQ_GPIO_KEY_INT        IRQ_GPIO(SPITZ_GPIO_KEY_INT)
-#define SPITZ_IRQ_GPIO_AC_IN          IRQ_GPIO(SPITZ_GPIO_AC_IN)
-#define SPITZ_IRQ_GPIO_AK_INT         IRQ_GPIO(SPITZ_GPIO_AK_INT)
-#define SPITZ_IRQ_GPIO_HP_IN          IRQ_GPIO(SPITZ_GPIO_HP_IN)
-#define SPITZ_IRQ_GPIO_TP_INT         IRQ_GPIO(SPITZ_GPIO_TP_INT)
-#define SPITZ_IRQ_GPIO_SYNC           IRQ_GPIO(SPITZ_GPIO_SYNC)
-#define SPITZ_IRQ_GPIO_ON_KEY         IRQ_GPIO(SPITZ_GPIO_ON_KEY)
-#define SPITZ_IRQ_GPIO_SWA            IRQ_GPIO(SPITZ_GPIO_SWA)
-#define SPITZ_IRQ_GPIO_SWB            IRQ_GPIO(SPITZ_GPIO_SWB)
-#define SPITZ_IRQ_GPIO_BAT_COVER      IRQ_GPIO(SPITZ_GPIO_BAT_COVER)
-#define SPITZ_IRQ_GPIO_FATAL_BAT      IRQ_GPIO(SPITZ_GPIO_FATAL_BAT)
-#define SPITZ_IRQ_GPIO_CO             IRQ_GPIO(SPITZ_GPIO_CO)
-#define SPITZ_IRQ_GPIO_CF_IRQ         IRQ_GPIO(SPITZ_GPIO_CF_IRQ)
-#define SPITZ_IRQ_GPIO_CF_CD          IRQ_GPIO(SPITZ_GPIO_CF_CD)
-#define SPITZ_IRQ_GPIO_CF2_IRQ        IRQ_GPIO(SPITZ_GPIO_CF2_IRQ)
-#define SPITZ_IRQ_GPIO_nSD_INT        IRQ_GPIO(SPITZ_GPIO_nSD_INT)
-#define SPITZ_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(SPITZ_GPIO_nSD_DETECT)
+#define SPITZ_IRQ_GPIO_KEY_INT        PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT)
+#define SPITZ_IRQ_GPIO_AC_IN          PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN)
+#define SPITZ_IRQ_GPIO_AK_INT         PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT)
+#define SPITZ_IRQ_GPIO_HP_IN          PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN)
+#define SPITZ_IRQ_GPIO_TP_INT         PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT)
+#define SPITZ_IRQ_GPIO_SYNC           PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC)
+#define SPITZ_IRQ_GPIO_ON_KEY         PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY)
+#define SPITZ_IRQ_GPIO_SWA            PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA)
+#define SPITZ_IRQ_GPIO_SWB            PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB)
+#define SPITZ_IRQ_GPIO_BAT_COVER      PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER)
+#define SPITZ_IRQ_GPIO_FATAL_BAT      PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT)
+#define SPITZ_IRQ_GPIO_CO             PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO)
+#define SPITZ_IRQ_GPIO_CF_IRQ         PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ)
+#define SPITZ_IRQ_GPIO_CF_CD          PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD)
+#define SPITZ_IRQ_GPIO_CF2_IRQ        PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ)
+#define SPITZ_IRQ_GPIO_nSD_INT        PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT)
+#define SPITZ_IRQ_GPIO_nSD_DETECT     PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT)
 
 /*
  * Shared data structures
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 1272c4b56ce..2bb0e862598 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -24,7 +24,7 @@
 /*
  * SCOOP2 internal GPIOs
  */
-#define TOSA_SCOOP_GPIO_BASE            NR_BUILTIN_GPIO
+#define TOSA_SCOOP_GPIO_BASE            PXA_NR_BUILTIN_GPIO
 #define TOSA_SCOOP_PXA_VCORE1           SCOOP_GPCR_PA11
 #define TOSA_GPIO_TC6393XB_REST_IN      (TOSA_SCOOP_GPIO_BASE + 1)
 #define TOSA_GPIO_IR_POWERDWN           (TOSA_SCOOP_GPIO_BASE + 2)
@@ -42,7 +42,7 @@
 /*
  * SCOOP2 jacket GPIOs
  */
-#define TOSA_SCOOP_JC_GPIO_BASE         (NR_BUILTIN_GPIO + 12)
+#define TOSA_SCOOP_JC_GPIO_BASE         (PXA_NR_BUILTIN_GPIO + 12)
 #define TOSA_GPIO_BT_LED                (TOSA_SCOOP_JC_GPIO_BASE + 0)
 #define TOSA_GPIO_NOTE_LED              (TOSA_SCOOP_JC_GPIO_BASE + 1)
 #define TOSA_GPIO_CHRG_ERR_LED          (TOSA_SCOOP_JC_GPIO_BASE + 2)
@@ -59,7 +59,7 @@
 /*
  * TC6393XB GPIOs
  */
-#define TOSA_TC6393XB_GPIO_BASE         (NR_BUILTIN_GPIO + 2 * 12)
+#define TOSA_TC6393XB_GPIO_BASE         (PXA_NR_BUILTIN_GPIO + 2 * 12)
 
 #define TOSA_GPIO_TG_ON                 (TOSA_TC6393XB_GPIO_BASE + 0)
 #define TOSA_GPIO_L_MUTE                (TOSA_TC6393XB_GPIO_BASE + 1)
@@ -141,30 +141,30 @@
 /*
  * Interrupts
  */
-#define TOSA_IRQ_GPIO_WAKEUP            IRQ_GPIO(TOSA_GPIO_WAKEUP)
-#define TOSA_IRQ_GPIO_AC_IN             IRQ_GPIO(TOSA_GPIO_AC_IN)
-#define TOSA_IRQ_GPIO_RECORD_BTN        IRQ_GPIO(TOSA_GPIO_RECORD_BTN)
-#define TOSA_IRQ_GPIO_SYNC              IRQ_GPIO(TOSA_GPIO_SYNC)
-#define TOSA_IRQ_GPIO_USB_IN            IRQ_GPIO(TOSA_GPIO_USB_IN)
-#define TOSA_IRQ_GPIO_JACKET_DETECT     IRQ_GPIO(TOSA_GPIO_JACKET_DETECT)
-#define TOSA_IRQ_GPIO_nSD_INT           IRQ_GPIO(TOSA_GPIO_nSD_INT)
-#define TOSA_IRQ_GPIO_nSD_DETECT        IRQ_GPIO(TOSA_GPIO_nSD_DETECT)
-#define TOSA_IRQ_GPIO_BAT1_CRG          IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
-#define TOSA_IRQ_GPIO_CF_CD             IRQ_GPIO(TOSA_GPIO_CF_CD)
-#define TOSA_IRQ_GPIO_BAT0_CRG          IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
-#define TOSA_IRQ_GPIO_TC6393XB_INT      IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
-#define TOSA_IRQ_GPIO_BAT0_LOW          IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
-#define TOSA_IRQ_GPIO_EAR_IN            IRQ_GPIO(TOSA_GPIO_EAR_IN)
-#define TOSA_IRQ_GPIO_CF_IRQ            IRQ_GPIO(TOSA_GPIO_CF_IRQ)
-#define TOSA_IRQ_GPIO_ON_KEY            IRQ_GPIO(TOSA_GPIO_ON_KEY)
-#define TOSA_IRQ_GPIO_VGA_LINE          IRQ_GPIO(TOSA_GPIO_VGA_LINE)
-#define TOSA_IRQ_GPIO_TP_INT            IRQ_GPIO(TOSA_GPIO_TP_INT)
-#define TOSA_IRQ_GPIO_JC_CF_IRQ         IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ)
-#define TOSA_IRQ_GPIO_BAT_LOCKED        IRQ_GPIO(TOSA_GPIO_BAT_LOCKED)
-#define TOSA_IRQ_GPIO_BAT1_LOW          IRQ_GPIO(TOSA_GPIO_BAT1_LOW)
-#define TOSA_IRQ_GPIO_KEY_SENSE(a)      IRQ_GPIO(69+(a))
-
-#define TOSA_IRQ_GPIO_MAIN_BAT_LOW      IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
+#define TOSA_IRQ_GPIO_WAKEUP            PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP)
+#define TOSA_IRQ_GPIO_AC_IN             PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN)
+#define TOSA_IRQ_GPIO_RECORD_BTN        PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN)
+#define TOSA_IRQ_GPIO_SYNC              PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC)
+#define TOSA_IRQ_GPIO_USB_IN            PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN)
+#define TOSA_IRQ_GPIO_JACKET_DETECT     PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT)
+#define TOSA_IRQ_GPIO_nSD_INT           PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT)
+#define TOSA_IRQ_GPIO_nSD_DETECT        PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT)
+#define TOSA_IRQ_GPIO_BAT1_CRG          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG)
+#define TOSA_IRQ_GPIO_CF_CD             PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD)
+#define TOSA_IRQ_GPIO_BAT0_CRG          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG)
+#define TOSA_IRQ_GPIO_TC6393XB_INT      PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT)
+#define TOSA_IRQ_GPIO_BAT0_LOW          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW)
+#define TOSA_IRQ_GPIO_EAR_IN            PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN)
+#define TOSA_IRQ_GPIO_CF_IRQ            PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ)
+#define TOSA_IRQ_GPIO_ON_KEY            PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY)
+#define TOSA_IRQ_GPIO_VGA_LINE          PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE)
+#define TOSA_IRQ_GPIO_TP_INT            PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT)
+#define TOSA_IRQ_GPIO_JC_CF_IRQ         PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ)
+#define TOSA_IRQ_GPIO_BAT_LOCKED        PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED)
+#define TOSA_IRQ_GPIO_BAT1_LOW          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW)
+#define TOSA_IRQ_GPIO_KEY_SENSE(a)      PXA_GPIO_TO_IRQ(69+(a))
+
+#define TOSA_IRQ_GPIO_MAIN_BAT_LOW      PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW)
 
 #define TOSA_KEY_SYNC           KEY_102ND /* ??? */
 
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 903e1a2e664..d2ca01053f6 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -43,30 +43,30 @@
 
 /* Ethernet Controller Davicom DM9000 */
 #define GPIO_DM9000             101
-#define TRIZEPS4_ETH_IRQ        IRQ_GPIO(GPIO_DM9000)
+#define TRIZEPS4_ETH_IRQ        PXA_GPIO_TO_IRQ(GPIO_DM9000)
 
 /* UCB1400 audio / TS-controller */
 #define GPIO_UCB1400            1
-#define TRIZEPS4_UCB1400_IRQ    IRQ_GPIO(GPIO_UCB1400)
+#define TRIZEPS4_UCB1400_IRQ    PXA_GPIO_TO_IRQ(GPIO_UCB1400)
 
 /* PCMCIA socket Compact Flash */
 #define GPIO_PCD                11              /* PCMCIA Card Detect */
-#define TRIZEPS4_CD_IRQ         IRQ_GPIO(GPIO_PCD)
+#define TRIZEPS4_CD_IRQ         PXA_GPIO_TO_IRQ(GPIO_PCD)
 #define GPIO_PRDY               13              /* READY / nINT */
-#define TRIZEPS4_READY_NINT     IRQ_GPIO(GPIO_PRDY)
+#define TRIZEPS4_READY_NINT     PXA_GPIO_TO_IRQ(GPIO_PRDY)
 
 /* MMC socket */
 #define GPIO_MMC_DET            12
-#define TRIZEPS4_MMC_IRQ        IRQ_GPIO(GPIO_MMC_DET)
+#define TRIZEPS4_MMC_IRQ        PXA_GPIO_TO_IRQ(GPIO_MMC_DET)
 
 /* DOC NAND chip */
 #define GPIO_DOC_LOCK           94
 #define GPIO_DOC_IRQ            93
-#define TRIZEPS4_DOC_IRQ        IRQ_GPIO(GPIO_DOC_IRQ)
+#define TRIZEPS4_DOC_IRQ        PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ)
 
 /* SPI interface */
 #define GPIO_SPI                53
-#define TRIZEPS4_SPI_IRQ        IRQ_GPIO(GPIO_SPI)
+#define TRIZEPS4_SPI_IRQ        PXA_GPIO_TO_IRQ(GPIO_SPI)
 
 /* LEDS using tx2 / rx2 */
 #define GPIO_SYS_BUSY_LED       46
@@ -74,7 +74,7 @@
 
 /* Off-module PIC on ConXS board */
 #define GPIO_PIC                0
-#define TRIZEPS4_PIC_IRQ        IRQ_GPIO(GPIO_PIC)
+#define TRIZEPS4_PIC_IRQ        PXA_GPIO_TO_IRQ(GPIO_PIC)
 
 #ifdef CONFIG_MACH_TRIZEPS_CONXS
 /* for CONXS base board define these registers */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 532c5d3a97d..5dae15ea671 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -22,7 +22,6 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/gpio-pxa.h>
 
 #include "generic.h"
 
@@ -92,44 +91,6 @@ static struct irq_chip pxa_internal_irq_chip = {
         .irq_unmask     = pxa_unmask_irq,
 };
 
-/*
- * GPIO IRQs for GPIO 0 and 1
- */
-static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
-{
-        int gpio = d->irq - IRQ_GPIO0;
-
-        if (__gpio_is_occupied(gpio)) {
-                pr_err("%s failed: GPIO is configured\n", __func__);
-                return -EINVAL;
-        }
-
-        if (type & IRQ_TYPE_EDGE_RISING)
-                GRER0 |= GPIO_bit(gpio);
-        else
-                GRER0 &= ~GPIO_bit(gpio);
-
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                GFER0 |= GPIO_bit(gpio);
-        else
-                GFER0 &= ~GPIO_bit(gpio);
-
-        return 0;
-}
-
-static void pxa_ack_low_gpio(struct irq_data *d)
-{
-        GEDR0 = (1 << (d->irq - IRQ_GPIO0));
-}
-
-static struct irq_chip pxa_low_gpio_chip = {
-        .name           = "GPIO-l",
-        .irq_ack        = pxa_ack_low_gpio,
-        .irq_mask       = pxa_mask_irq,
-        .irq_unmask     = pxa_unmask_irq,
-        .irq_set_type   = pxa_set_low_gpio_type,
-};
-
 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
 {
         uint32_t icip, icmr, mask;
@@ -160,26 +121,7 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
         } while (1);
 }
 
-static void __init pxa_init_low_gpio_irq(set_wake_t fn)
-{
-        int irq;
-
-        /* clear edge detection on GPIO 0 and 1 */
-        GFER0 &= ~0x3;
-        GRER0 &= ~0x3;
-        GEDR0 = 0x3;
-
-        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-                irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
-                                         handle_edge_irq);
-                irq_set_chip_data(irq, irq_base(0));
-                set_irq_flags(irq, IRQF_VALID);
-        }
-
-        pxa_low_gpio_chip.irq_set_wake = fn;
-}
-
-void __init pxa_init_irq(int irq_nr, set_wake_t fn)
+void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
 {
         int irq, i, n;
 
@@ -209,7 +151,6 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
         __raw_writel(1, irq_base(0) + ICCR);
 
         pxa_internal_irq_chip.irq_set_wake = fn;
-        pxa_init_low_gpio_irq(fn);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index c337c7eed51..1fb86edb857 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -124,8 +124,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
-                .end    = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         }
 };
@@ -396,7 +396,7 @@ static struct i2c_board_info littleton_i2c_info[] = {
                 .type           = "da9034",
                 .addr           = 0x34,
                 .platform_data  = &littleton_da9034_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO18)),
         },
         [1] = {
                 .type           = "max7320",
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 6119c015f39..cee9ce2fc0b 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -152,8 +152,8 @@ static void __init lpd270_init_irq(void)
                                          handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
-        irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
-        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
+        irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
 }
 
 
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 4b7a5287165..6ebd276aebe 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -170,8 +170,8 @@ static void __init lubbock_init_irq(void)
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
-        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler);
+        irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 4e6774fff42..3d6baf91396 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -184,8 +184,8 @@ static struct resource egpio_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         [1] = {
-                .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
-                .end   = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .start = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ),
+                .end   = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -468,8 +468,8 @@ static struct resource pasic3_resources[] = {
         },
         /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */
         [1] = {
-                .start  = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
-                .end    = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index ca14555d5e1..1aebaf71946 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -178,8 +178,8 @@ static void __init mainstone_init_irq(void)
         MST_INTMSKENA = 0;
         MST_INTSETCLR = 0;
 
-        irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
-        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler);
+        irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 43a5f6861ca..f14775536b8 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -13,6 +13,7 @@
  *  published by the Free Software Foundation.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -20,7 +21,6 @@
 
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa2xx.h>
-#include <mach/gpio-pxa.h>
 
 #include "generic.h"
 
@@ -29,6 +29,10 @@
 #define GAFR_L(x)       __GAFR(0, x)
 #define GAFR_U(x)       __GAFR(1, x)
 
+#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
+#define GPLR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5))
+#define GPDR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
+
 #define PWER_WE35       (1 << 24)
 
 struct gpio_desc {
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 924a3b5f8da..e80a3db735c 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -53,6 +53,7 @@
 #include <mach/pxa27x-udc.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 #include <media/soc_camera.h>
 
 #include <mach/mioa701.h>
@@ -390,24 +391,19 @@ static struct pxamci_platform_data mioa701_mci_info = {
 };
 
 /* FlashRAM */
-static struct resource strataflash_resource = {
+static struct resource docg3_resource = {
         .start = PXA_CS0_PHYS,
-        .end   = PXA_CS0_PHYS + SZ_64M - 1,
+        .end   = PXA_CS0_PHYS + SZ_8K - 1,
         .flags = IORESOURCE_MEM,
 };
 
-static struct physmap_flash_data strataflash_data = {
-        .width = 2,
-        /* .set_vpp = mioa701_set_vpp, */
-};
-
-static struct platform_device strataflash = {
-        .name          = "physmap-flash",
+static struct platform_device docg3 = {
+        .name          = "docg3",
         .id            = -1,
-        .resource      = &strataflash_resource,
+        .resource      = &docg3_resource,
         .num_resources = 1,
         .dev = {
-                .platform_data = &strataflash_data,
+                .platform_data = NULL,
         },
 };
 
@@ -541,15 +537,15 @@ static struct pda_power_pdata power_pdata = {
 static struct resource power_resources[] = {
         [0] = {
                 .name   = "ac",
-                .start  = gpio_to_irq(GPIO96_AC_DETECT),
-                .end    = gpio_to_irq(GPIO96_AC_DETECT),
+                .start  = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT),
+                .end    = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                 IORESOURCE_IRQ_LOWEDGE,
         },
         [1] = {
                 .name   = "usb",
-                .start  = gpio_to_irq(GPIO13_nUSB_DETECT),
-                .end    = gpio_to_irq(GPIO13_nUSB_DETECT),
+                .start  = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT),
+                .end    = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                 IORESOURCE_IRQ_LOWEDGE,
         },
@@ -685,7 +681,7 @@ static struct platform_device *devices[] __initdata = {
         &pxa2xx_pcm,
         &mioa701_sound,
         &power_dev,
-        &strataflash,
+        &docg3,
         &gpio_vbus,
         &mioa701_camera,
         &mioa701_board,
@@ -720,6 +716,15 @@ static void __init mioa701_machine_init(void)
         RTTR = 32768 - 1; /* Reset crazy WinCE value */
         UP2OCR = UP2OCR_HXOE;
 
+        /*
+         * Set up the flash memory : DiskOnChip G3 on first static memory bank
+         */
+        __raw_writel(0x7ff02dd8, MSC0);
+        __raw_writel(0x0001c391, MCMEM0);
+        __raw_writel(0x0001c391, MCATT0);
+        __raw_writel(0x0001c391, MCIO0);
+
+
         pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 90928d6e1a5..83570a79e7d 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -417,8 +417,8 @@ static struct resource dm9k_resources[] = {
                .flags = IORESOURCE_MEM
         },
         [2] = {
-               .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)),
-               .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)),
+               .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)),
+               .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)),
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
         }
 };
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 6d38c6548b3..abab4e2b122 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -378,7 +378,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
 #include <linux/i2c/pca953x.h>
 
 static struct pca953x_platform_data pca9536_data = {
-        .gpio_base      = NR_BUILTIN_GPIO,
+        .gpio_base      = PXA_NR_BUILTIN_GPIO,
 };
 
 static int gpio_bus_switch = -EINVAL;
@@ -406,9 +406,9 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
         int ret;
 
         if (gpio_bus_switch < 0) {
-                ret = gpio_request(NR_BUILTIN_GPIO, "camera");
+                ret = gpio_request(PXA_NR_BUILTIN_GPIO, "camera");
                 if (!ret) {
-                        gpio_bus_switch = NR_BUILTIN_GPIO;
+                        gpio_bus_switch = PXA_NR_BUILTIN_GPIO;
                         gpio_direction_output(gpio_bus_switch, 0);
                 }
         }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index b260ce872d2..69036e42ca3 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -166,8 +166,8 @@ static struct resource locomo_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = IRQ_GPIO(10),
-                .end            = IRQ_GPIO(10),
+                .start          = PXA_GPIO_TO_IRQ(10),
+                .end            = PXA_GPIO_TO_IRQ(10),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -212,7 +212,7 @@ static struct spi_board_info poodle_spi_devices[] = {
                 .bus_num        = 1,
                 .platform_data  = &poodle_ads7846_info,
                 .controller_data= &poodle_ads7846_chip,
-                .irq            = gpio_to_irq(POODLE_GPIO_TP_INT),
+                .irq            = PXA_GPIO_TO_IRQ(POODLE_GPIO_TP_INT),
         },
 };
 
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index f05f9486b0c..adf058fa97e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -17,6 +17,7 @@
  * need be.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -208,6 +209,8 @@ static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
         INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 static struct clk_lookup pxa25x_hwuart_clkreg =
@@ -287,7 +290,7 @@ static inline void pxa25x_init_pm(void) {}
 
 static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         uint32_t mask = 0;
 
         if (gpio >= 0 && gpio < 85)
@@ -312,14 +315,12 @@ set_pwer:
 void __init pxa25x_init_irq(void)
 {
         pxa_init_irq(32, pxa25x_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
 }
 
 #ifdef CONFIG_CPU_PXA26x
 void __init pxa26x_init_irq(void)
 {
         pxa_init_irq(32, pxa25x_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
 }
 #endif
 
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index bc5a98ebaa7..180bd8675d4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -229,6 +230,8 @@ static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 #ifdef CONFIG_PM
@@ -355,7 +358,7 @@ static inline void pxa27x_init_pm(void) {}
  */
 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         uint32_t mask;
 
         if (gpio >= 0 && gpio < 128)
@@ -386,7 +389,6 @@ static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 void __init pxa27x_init_irq(void)
 {
         pxa_init_irq(34, pxa27x_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 }
 
 static struct map_desc pxa27x_io_desc[] __initdata = {
@@ -422,6 +424,7 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 
 static struct platform_device *devices[] __initdata = {
+        &pxa_device_gpio,
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 40bb16501d8..0388eda7878 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -89,6 +89,7 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
 static struct clk_lookup common_clkregs[] = {
         INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 8d614ecd8e9..d487e1ff4c9 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -83,6 +83,7 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
 static struct clk_lookup pxa320_clkregs[] = {
         INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 static int __init pxa320_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 0737c59b88a..f107c71c758 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -25,7 +25,6 @@
 #include <asm/mach/map.h>
 #include <asm/suspend.h>
 #include <mach/hardware.h>
-#include <mach/gpio-pxa.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/reset.h>
 #include <mach/ohci.h>
@@ -56,6 +55,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
 
 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
@@ -67,6 +67,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
         /* Power I2C clock is always on */
         INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
@@ -88,6 +89,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
+        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
 };
 
 #ifdef CONFIG_PM
@@ -365,7 +367,8 @@ static struct irq_chip pxa_ext_wakeup_chip = {
         .irq_set_type   = pxa_set_ext_wakeup_type,
 };
 
-static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
+static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
+                                           unsigned int))
 {
         int irq;
 
@@ -388,7 +391,6 @@ void __init pxa3xx_init_irq(void)
 
         pxa_init_irq(56, pxa3xx_set_wake);
         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 
 static struct map_desc pxa3xx_io_desc[] __initdata = {
@@ -417,6 +419,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 
 static struct platform_device *devices[] __initdata = {
+        &pxa_device_gpio,
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index 51371b39d2a..fccc644702e 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -20,7 +20,6 @@
 #include <linux/syscore_ops.h>
 
 #include <mach/hardware.h>
-#include <mach/gpio-pxa.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/pxa930.h>
 #include <mach/reset.h>
@@ -212,11 +211,13 @@ static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0);
 
 static struct clk_lookup pxa95x_clkregs[] = {
         INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
         /* Power I2C clock is always on */
         INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
         INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
         INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
         INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
@@ -230,12 +231,12 @@ static struct clk_lookup pxa95x_clkregs[] = {
         INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
         INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
         INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
 };
 
 void __init pxa95x_init_irq(void)
 {
         pxa_init_irq(96, NULL);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 
 /*
@@ -248,6 +249,7 @@ void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 
 static struct platform_device *devices[] __initdata = {
+        &pxa_device_gpio,
         &sa1100_device_rtc,
         &pxa_device_rtc,
         &pxa27x_device_ssp1,
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 4962b167662..22818c7694a 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -292,8 +292,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = gpio_to_irq(GPIO_ETH_IRQ),
-                .end    = gpio_to_irq(GPIO_ETH_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ),
                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
         }
 };
@@ -672,7 +672,7 @@ static struct lis3lv02d_platform_data lis3_pdata = {
         .chip_select    = 1,                    \
         .controller_data = (void *) GPIO_ACCEL_CS,      \
         .platform_data  = &lis3_pdata,          \
-        .irq            = gpio_to_irq(GPIO_ACCEL_IRQ),  \
+        .irq            = PXA_GPIO_TO_IRQ(GPIO_ACCEL_IRQ),      \
 }
 
 #define SPI_DAC7512     \
@@ -956,7 +956,7 @@ static struct eeti_ts_platform_data eeti_ts_pdata = {
 static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
         .type   = "eeti_ts",
         .addr   = 0x0a,
-        .irq    = gpio_to_irq(GPIO_TOUCH_IRQ),
+        .irq    = PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
         .platform_data = &eeti_ts_pdata,
 };
 
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 878707056e6..0fe354efb93 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -96,8 +96,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)),
-                .end    = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
@@ -502,7 +502,7 @@ static struct i2c_board_info saar_i2c_info[] = {
                 .type           = "da9034",
                 .addr           = 0x34,
                 .platform_data  = &saar_da9034_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
         },
 };
 
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index b6dbaca460c..febc809ed5a 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -92,7 +92,7 @@ static struct i2c_board_info saarb_i2c_info[] = {
                 .type           = "88PM860x",
                 .addr           = 0x34,
                 .platform_data  = &saarb_pm8607_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
         },
 };
 
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 785880f67b6..8d5168d253a 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -907,24 +907,24 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev)
         gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
 
         /* Register interrupt handlers */
-        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin));
+        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin));
         }
 
-        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock));
+        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock));
         }
 
         if (sharpsl_pm.machinfo->gpio_fatal) {
-                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal));
+                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal));
                 }
         }
 
         if (sharpsl_pm.machinfo->batfull_irq) {
                 /* Register interrupt handler. */
-                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
+                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull));
                 }
         }
 
@@ -953,14 +953,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev)
 
         led_trigger_unregister_simple(sharpsl_charge_led_trigger);
 
-        free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
-        free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
+        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
+        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
 
         if (sharpsl_pm.machinfo->gpio_fatal)
-                free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
+                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
 
         if (sharpsl_pm.machinfo->batfull_irq)
-                free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
+                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
 
         gpio_free(sharpsl_pm.machinfo->gpio_batlock);
         gpio_free(sharpsl_pm.machinfo->gpio_batfull);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index a7f81a3fd13..abf355d0c92 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -552,7 +552,7 @@ static struct spi_board_info spitz_spi_devices[] = {
                 .chip_select            = 0,
                 .platform_data          = &spitz_ads7846_info,
                 .controller_data        = &spitz_ads7846_chip,
-                .irq                    = gpio_to_irq(SPITZ_GPIO_TP_INT),
+                .irq                    = PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT),
         }, {
                 .modalias               = "corgi-lcd",
                 .max_speed_hz           = 50000,
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 094279aefe9..34cbdac5152 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
@@ -41,6 +42,7 @@ static int spitz_last_ac_status;
 static struct gpio spitz_charger_gpios[] = {
         { SPITZ_GPIO_KEY_INT,   GPIOF_IN, "Keyboard Interrupt" },
         { SPITZ_GPIO_SYNC,      GPIOF_IN, "Sync" },
+        { SPITZ_GPIO_AC_IN,     GPIOF_IN, "Charger Detection" },
         { SPITZ_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
         { SPITZ_GPIO_JK_B,        GPIOF_OUT_INIT_LOW, "JK B" },
         { SPITZ_GPIO_CHRG_ON,     GPIOF_OUT_INIT_LOW, "Charger On" },
@@ -169,14 +171,19 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
 
 static unsigned long spitz_charger_wakeup(void)
 {
-        return (~GPLR0 & GPIO_bit(SPITZ_GPIO_KEY_INT)) | (GPLR0 & GPIO_bit(SPITZ_GPIO_SYNC));
+        unsigned long ret;
+        ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT)
+                << GPIO_bit(SPITZ_GPIO_KEY_INT))
+                | (!gpio_get_value(SPITZ_GPIO_SYNC)
+                << GPIO_bit(SPITZ_GPIO_SYNC));
+        return ret;
 }
 
 unsigned long spitzpm_read_devdata(int type)
 {
         switch (type) {
         case SHARPSL_STATUS_ACIN:
-                return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0);
+                return !gpio_get_value(SPITZ_GPIO_AC_IN);
         case SHARPSL_STATUS_LOCK:
                 return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
         case SHARPSL_STATUS_CHRGFULL:
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 80d7f23ad0f..d8a2467de92 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -376,7 +376,7 @@ static struct spi_board_info spi_board_info[] __initdata = {
                 .bus_num = 1,
                 .chip_select = 0,
                 .controller_data = &staccel_chip_info,
-                .irq = IRQ_GPIO(96),
+                .irq = PXA_GPIO_TO_IRQ(96),
         }, {
                 .modalias = "cc2420",
                 .max_speed_hz = 6500000,
@@ -546,7 +546,7 @@ static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = {
                 .type = "da9030",
                 .addr = 0x49,
                 .platform_data = &imote2_da9030_pdata,
-                .irq = gpio_to_irq(1),
+                .irq = PXA_GPIO_TO_IRQ(1),
         },
 };
 
@@ -560,18 +560,18 @@ static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
                 /* Through a nand gate - Also beware, on V2 sensor board the
                  * pull up resistors are missing.
                  */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
         }, { /* ITS400 Sensor board only */
                 .type = "tsl2561",
                 .addr = 0x49,
                 /* Through a nand gate - Also beware, on V2 sensor board the
                  * pull up resistors are missing.
                  */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
         }, { /* ITS400 Sensor board only */
                 .type = "tmp175",
                 .addr = 0x4A,
-                .irq = IRQ_GPIO(96),
+                .irq = PXA_GPIO_TO_IRQ(96),
         }, { /* IMB400 Multimedia board */
                 .type = "wm8940",
                 .addr = 0x1A,
@@ -661,8 +661,8 @@ static struct resource smc91x_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         [1] = {
-                .start = IRQ_GPIO(40),
-                .end = IRQ_GPIO(40),
+                .start = PXA_GPIO_TO_IRQ(40),
+                .end = PXA_GPIO_TO_IRQ(40),
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
@@ -707,7 +707,7 @@ static int stargate2_mci_init(struct device *dev,
         }
         gpio_direction_input(SG2_GPIO_nSD_DETECT);
 
-        err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT),
+        err = request_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT),
                           stargate2_detect_int,
                           IRQ_TYPE_EDGE_BOTH,
                           "MMC card detect",
@@ -738,7 +738,7 @@ static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
 
 static void stargate2_mci_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), data);
+        free_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), data);
         gpio_free(SG2_SD_POWER_ENABLE);
         gpio_free(SG2_GPIO_nSD_DETECT);
 }
@@ -913,7 +913,7 @@ static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = {
                 .type = "da9030",
                 .addr = 0x49,
                 .platform_data = &stargate2_da9030_pdata,
-                .irq = gpio_to_irq(1),
+                .irq = PXA_GPIO_TO_IRQ(1),
         },
 };
 
@@ -938,18 +938,18 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {
                 /* Through a nand gate - Also beware, on V2 sensor board the
                  * pull up resistors are missing.
                  */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
         }, { /* ITS400 Sensor board only */
                 .type = "tsl2561",
                 .addr = 0x49,
                 /* Through a nand gate - Also beware, on V2 sensor board the
                  * pull up resistors are missing.
                  */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
         }, { /* ITS400 Sensor board only */
                 .type = "tmp175",
                 .addr = 0x4A,
-                .irq = IRQ_GPIO(96),
+                .irq = PXA_GPIO_TO_IRQ(96),
         },
 };
 
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 4fa36a3e383..9fb38e80e07 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -85,8 +85,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)),
-                .end    = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index 8a22879f0bb..f7d9305cfd7 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -101,7 +101,7 @@ static struct i2c_board_info evb3_i2c_info[] = {
                 .type           = "88PM860x",
                 .addr           = 0x34,
                 .platform_data  = &evb3_pm8607_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
         },
 };
 
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index dfe40f8705a..7ce5c436cc4 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -404,8 +404,8 @@ static struct pda_power_pdata tosa_power_data = {
 static struct resource tosa_power_resource[] = {
         {
                 .name           = "ac",
-                .start          = gpio_to_irq(TOSA_GPIO_AC_IN),
-                .end            = gpio_to_irq(TOSA_GPIO_AC_IN),
+                .start          = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN),
+                .end            = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN),
                 .flags          = IORESOURCE_IRQ |
                                   IORESOURCE_IRQ_HIGHEDGE |
                                   IORESOURCE_IRQ_LOWEDGE,
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index afe2b749552..023d6ca789d 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -422,8 +422,8 @@ static struct resource smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gpio_to_irq(VIPER_ETH_GPIO),
-                .end    = gpio_to_irq(VIPER_ETH_GPIO),
+                .start  = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
+                .end    = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         },
         [2] = {
@@ -546,7 +546,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         /* External UARTs */
         {
                 .mapbase        = VIPER_UARTA_PHYS,
-                .irq            = gpio_to_irq(VIPER_UARTA_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(VIPER_UARTA_GPIO),
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .uartclk        = 1843200,
                 .regshift       = 1,
@@ -556,7 +556,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         {
                 .mapbase        = VIPER_UARTB_PHYS,
-                .irq            = gpio_to_irq(VIPER_UARTB_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(VIPER_UARTB_GPIO),
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .uartclk        = 1843200,
                 .regshift       = 1,
@@ -596,8 +596,8 @@ static struct resource isp116x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = gpio_to_irq(VIPER_USB_GPIO),
-                .end    = gpio_to_irq(VIPER_USB_GPIO),
+                .start  = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
+                .end    = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         },
 };
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index fed5fb08871..1f5cfa96f6d 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -395,8 +395,8 @@ static struct resource vpac270_dm9000_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ),
-                .end    = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         },
 };
@@ -433,7 +433,7 @@ static pxa2xx_audio_ops_t vpac270_ac97_pdata = {
 };
 
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
-        .irq            = IRQ_GPIO(GPIO113_VPAC270_TS_IRQ),
+        .irq            = PXA_GPIO_TO_IRQ(GPIO113_VPAC270_TS_IRQ),
 };
 
 static struct platform_device vpac270_ucb1400_device = {
@@ -610,8 +610,8 @@ static struct resource vpac270_ide_resources[] = {
                .flags   = IORESOURCE_DMA
         },
         [3] = { /* IDE IRQ pin */
-               .start   = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ),
-               .end     = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ),
+               .start   = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ),
+               .end     = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ),
                .flags   = IORESOURCE_IRQ
         }
 };
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index d75f66ab8c3..b6476848b56 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -573,7 +573,7 @@ static struct spi_board_info spi_board_info[] __initdata = {
         .modalias               = "libertas_spi",
         .platform_data          = &z2_lbs_pdata,
         .controller_data        = &z2_lbs_chip_info,
-        .irq                    = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ),
+        .irq                    = PXA_GPIO_TO_IRQ(GPIO36_ZIPITZ2_WIFI_IRQ),
         .max_speed_hz           = 13000000,
         .bus_num                = 1,
         .chip_select            = 0,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 9db35a7fcfc..a4dd1c34705 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -233,7 +233,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
         { /* COM1 */
                 .mapbase        = 0x10000000,
-                .irq            = gpio_to_irq(ZEUS_UARTA_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .uartclk        = 14745600,
                 .regshift       = 1,
@@ -242,7 +242,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         { /* COM2 */
                 .mapbase        = 0x10800000,
-                .irq            = gpio_to_irq(ZEUS_UARTB_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .uartclk        = 14745600,
                 .regshift       = 1,
@@ -251,7 +251,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         { /* COM3 */
                 .mapbase        = 0x11000000,
-                .irq            = gpio_to_irq(ZEUS_UARTC_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .uartclk        = 14745600,
                 .regshift       = 1,
@@ -260,7 +260,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         },
         { /* COM4 */
                 .mapbase        = 0x11800000,
-                .irq            = gpio_to_irq(ZEUS_UARTD_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .uartclk        = 14745600,
                 .regshift       = 1,
@@ -321,8 +321,8 @@ static struct resource zeus_dm9k0_resource[] = {
                 .flags = IORESOURCE_MEM
         },
         [2] = {
-                .start = gpio_to_irq(ZEUS_ETH0_GPIO),
-                .end   = gpio_to_irq(ZEUS_ETH0_GPIO),
+                .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         },
 };
@@ -339,8 +339,8 @@ static struct resource zeus_dm9k1_resource[] = {
                 .flags = IORESOURCE_MEM,
         },
         [2] = {
-                .start = gpio_to_irq(ZEUS_ETH1_GPIO),
-                .end   = gpio_to_irq(ZEUS_ETH1_GPIO),
+                .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         },
 };
@@ -423,7 +423,7 @@ static struct spi_board_info zeus_spi_board_info[] = {
         [0] = {
                 .modalias       = "mcp2515",
                 .platform_data  = &zeus_mcp2515_pdata,
-                .irq            = gpio_to_irq(ZEUS_CAN_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
                 .max_speed_hz   = 1*1000*1000,
                 .bus_num        = 3,
                 .mode           = SPI_MODE_0,
@@ -753,7 +753,7 @@ static struct i2c_board_info __initdata zeus_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("pca9535",       0x20),
                 .platform_data  = &zeus_pca953x_pdata[2],
-                .irq            = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
         },
         { I2C_BOARD_INFO("lm75a",       0x48) },
         { I2C_BOARD_INFO("24c01",       0x50) },
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 7678b1bf790..98eec80623e 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -408,8 +408,8 @@ static void __init zylonite_init(void)
          * Note: We depend that the bootloader set
          * the correct value to MSC register for SMC91x.
          */
-        smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq);
-        smc91x_resources[1].end   = gpio_to_irq(gpio_eth_irq);
+        smc91x_resources[1].start = PXA_GPIO_TO_IRQ(gpio_eth_irq);
+        smc91x_resources[1].end   = PXA_GPIO_TO_IRQ(gpio_eth_irq);
         platform_device_register(&smc91x_device);
 
         pxa_set_ac97_info(NULL);
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 93c64d8d7de..86e59c043de 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -231,12 +231,12 @@ static struct i2c_board_info zylonite_i2c_board_info[] = {
                 .type           = "pca9539",
                 .addr           = 0x74,
                 .platform_data  = &gpio_exp[0],
-                .irq            = IRQ_GPIO(18),
+                .irq            = PXA_GPIO_TO_IRQ(18),
         }, {
                 .type           = "pca9539",
                 .addr           = 0x75,
                 .platform_data  = &gpio_exp[1],
-                .irq            = IRQ_GPIO(19),
+                .irq            = PXA_GPIO_TO_IRQ(19),
         },
 };
 
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index c6133c6ec18..feeaf73933d 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -165,22 +165,6 @@ static struct map_desc bast_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
-
-
 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
@@ -188,8 +172,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = bast_serial_clocks,
-                .clocks_size = ARRAY_SIZE(bast_serial_clocks),
         },
         [1] = {
                 .hwport      = 1,
@@ -197,8 +179,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = bast_serial_clocks,
-                .clocks_size = ARRAY_SIZE(bast_serial_clocks),
         },
         /* port 2 is not actually used */
         [2] = {
@@ -207,8 +187,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = bast_serial_clocks,
-                .clocks_size = ARRAY_SIZE(bast_serial_clocks),
         }
 };
 
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index cc7032b5c65..dbe668a803e 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -110,23 +110,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-/* uart clock source(s) */
-
-static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0.
-        }
-};
-
 static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
@@ -134,8 +117,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = vr1000_serial_clocks,
-                .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
         },
         [1] = {
                 .hwport      = 1,
@@ -143,8 +124,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = vr1000_serial_clocks,
-                .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
         },
         /* port 2 is not actually used */
         [2] = {
@@ -153,9 +132,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = vr1000_serial_clocks,
-                .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
-
         }
 };
 
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index eea559ec7a5..061b6bb1a55 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -124,12 +124,18 @@ static struct clk s3c2410_armclk = {
         .id     = -1,
 };
 
+static struct clk_lookup s3c2410_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+};
+
 void __init s3c2410_init_clocks(int xtal)
 {
         s3c24xx_register_baseclocks(xtal);
         s3c2410_setup_clocks();
         s3c2410_baseclk_add();
         s3c24xx_register_clock(&s3c2410_armclk);
+        clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
 }
 
 struct bus_type s3c2410_subsys = {
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 51688164080..d10b695a906 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = {
         &clk_armclk,
 };
 
+static struct clk_lookup s3c2412_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
+};
+
 int __init s3c2412_baseclk_add(void)
 {
         unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
@@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void)
                 s3c2412_clkcon_enable(clkp, 0);
         }
 
+        clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
         s3c_pwmclk_init();
         return 0;
 }
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b279ca..ca0cd227f87 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM)	+= pm.o
 #obj-$(CONFIG_S3C2416_DMA)      += dma.o
 
 # Device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
 obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
 
 # Machine support
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d..59f54d1d7f8 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
         },
 };
 
-static struct clksrc_clk hsmmc_mux[] = {
-        [0] = {
-                .clk    = {
-                        .name   = "hsmmc-if",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit = (1 << 6),
-                        .enable = s3c2443_clkcon_enable_s,
-                },
-                .sources = &(struct clksrc_sources) {
-                        .nr_sources = 2,
-                        .sources = (struct clk *[]) {
-                                [0] = &hsmmc_div[0].clk,
-                                [1] = NULL, /* to fix */
-                        },
-                },
-                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+static struct clksrc_clk hsmmc_mux0 = {
+        .clk    = {
+                .name           = "hsmmc-if",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 6),
+                .enable         = s3c2443_clkcon_enable_s,
         },
-        [1] = {
-                .clk    = {
-                        .name   = "hsmmc-if",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit = (1 << 12),
-                        .enable = s3c2443_clkcon_enable_s,
+        .sources        = &(struct clksrc_sources) {
+                .nr_sources     = 2,
+                .sources        = (struct clk * []) {
+                        [0]     = &hsmmc_div[0].clk,
+                        [1]     = NULL, /* to fix */
                 },
-                .sources = &(struct clksrc_sources) {
-                        .nr_sources = 2,
-                        .sources = (struct clk *[]) {
-                                [0] = &hsmmc_div[1].clk,
-                                [1] = NULL, /* to fix */
-                        },
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+};
+
+static struct clksrc_clk hsmmc_mux1 = {
+        .clk    = {
+                .name           = "hsmmc-if",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 12),
+                .enable         = s3c2443_clkcon_enable_s,
+        },
+        .sources        = &(struct clksrc_sources) {
+                .nr_sources     = 2,
+                .sources        = (struct clk * []) {
+                        [0]     = &hsmmc_div[1].clk,
+                        [1]     = NULL, /* to fix */
                 },
-                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
         },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 };
 
 static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
         &hsspi_mux,
         &hsmmc_div[0],
         &hsmmc_div[1],
-        &hsmmc_mux[0],
-        &hsmmc_mux[1],
+        &hsmmc_mux0,
+        &hsmmc_mux1,
+};
+
+static struct clk_lookup s3c2416_clk_lookup[] = {
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
                 s3c_register_clksrc(clksrcs[ptr], 1);
 
         s3c24xx_register_clock(&hsmmc0_clk);
+        clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
 
         s3c_pwmclk_init();
 
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 66b71736609..eebe1e72b93 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -50,6 +50,7 @@
 #include <plat/nand.h>
 #include <plat/sdhci.h>
 #include <plat/udc.h>
+#include <linux/platform_data/s3c-hsudc.h>
 
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee53955eb0..00000000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
- *
- * Copyright 2010 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c64xx/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c2416_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",
-        [1] = "hsmmc",
-        [2] = "hsmmc-if",
-        /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index d8957592fdc..bedbc87a342 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -33,6 +33,7 @@
 #include <linux/mutex.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/serial_core.h>
 
 #include <mach/hardware.h>
 #include <linux/atomic.h>
@@ -42,6 +43,7 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/regs-serial.h>
 
 /* S3C2440 extended clock support */
 
@@ -107,6 +109,46 @@ static struct clk s3c2440_clk_ac97 = {
         .ctrlbit        = S3C2440_CLKCON_CAMERA,
 };
 
+static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
+{
+        unsigned long ucon0, ucon1, ucon2, divisor;
+
+        /* the fun of calculating the uart divisors on the s3c2440 */
+        ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
+        ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
+        ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
+
+        ucon0 &= S3C2440_UCON0_DIVMASK;
+        ucon1 &= S3C2440_UCON1_DIVMASK;
+        ucon2 &= S3C2440_UCON2_DIVMASK;
+
+        if (ucon0 != 0)
+                divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
+        else if (ucon1 != 0)
+                divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
+        else if (ucon2 != 0)
+                divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
+        else
+                /* manual calims 44, seems to be 9 */
+                divisor = 9;
+
+        return clk_get_rate(clk->parent) / divisor;
+}
+
+static struct clk s3c2440_clk_fclk_n = {
+        .name           = "fclk_n",
+        .parent         = &clk_f,
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2440_fclk_n_getrate,
+        },
+};
+
+static struct clk_lookup s3c2440_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
+};
+
 static int s3c2440_clk_add(struct device *dev)
 {
         struct clk *clock_upll;
@@ -125,10 +167,12 @@ static int s3c2440_clk_add(struct device *dev)
         s3c2440_clk_cam.parent = clock_h;
         s3c2440_clk_ac97.parent = clock_p;
         s3c2440_clk_cam_upll.parent = clock_upll;
+        s3c24xx_register_clock(&s3c2440_clk_fclk_n);
 
         s3c24xx_register_clock(&s3c2440_clk_ac97);
         s3c24xx_register_clock(&s3c2440_clk_cam);
         s3c24xx_register_clock(&s3c2440_clk_cam_upll);
+        clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
 
         clk_disable(&s3c2440_clk_ac97);
         clk_disable(&s3c2440_clk_cam);
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 121ff8d2c88..24569550de1 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -98,22 +98,6 @@ static struct map_desc anubis_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
-
-
 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
@@ -121,8 +105,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = anubis_serial_clocks,
-                .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         },
         [1] = {
                 .hwport      = 2,
@@ -130,8 +113,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = anubis_serial_clocks,
-                .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         },
 };
 
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index b7e334f07da..d6a9763110c 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -59,22 +59,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = {
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
 
-static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
-
-
 static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
@@ -82,8 +66,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = at2440evb_serial_clocks,
-                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         },
         [1] = {
                 .hwport      = 1,
@@ -91,8 +74,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = at2440evb_serial_clocks,
-                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         },
 };
 
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 437322ffd88..adbbb85bc4c 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -169,6 +169,24 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
                                    S3C2410_LCDCON5_HWSWP),
         },
+        /* mini2440 + 3.5" TFT (LCD-W35i, LQ035Q1DG06 type) + touchscreen*/
+        [3] = {
+                _LCD_DECLARE(
+                        /* clock */
+                        7,
+                        /* xres, margin_right, margin_left, hsync */
+                        320, 68, 66, 4,
+                        /* yres, margin_top, margin_bottom, vsync */
+                        240, 4, 4, 9,
+                        /* refresh rate */
+                        60),
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVCLK |
+                                   S3C2410_LCDCON5_HWSWP),
+        },
 };
 
 /* todo - put into gpio header */
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index e795715fba3..4c480ef734f 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -102,21 +102,6 @@ static struct map_desc osiris_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
-
 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
@@ -124,8 +109,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = osiris_serial_clocks,
-                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         },
         [1] = {
                 .hwport      = 1,
@@ -133,8 +117,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = osiris_serial_clocks,
-                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         },
         [2] = {
                 .hwport      = 2,
@@ -142,8 +125,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON,
                 .ufcon       = UFCON,
-                .clocks      = osiris_serial_clocks,
-                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
         }
 };
 
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 332d7533bd9..80077f6472e 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -70,15 +70,6 @@
 static struct map_desc rx1950_iodesc[] __initdata = {
 };
 
-static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
-        [0] = {
-               .name = "fclk",
-               .divisor = 0x0a,
-               .min_baud = 0,
-               .max_baud = 0,
-        },
-};
-
 static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
         [0] = {
                .hwport = 0,
@@ -86,8 +77,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
                .ucon = 0x3c5,
                .ulcon = 0x03,
                .ufcon = 0x51,
-               .clocks = rx1950_serial_clocks,
-               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+                .clk_sel = S3C2410_UCON_CLKSEL3,
         },
         [1] = {
                .hwport = 1,
@@ -95,8 +85,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
                .ucon = 0x3c5,
                .ulcon = 0x03,
                .ufcon = 0x51,
-               .clocks = rx1950_serial_clocks,
-               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+                .clk_sel = S3C2410_UCON_CLKSEL3,
         },
         /* IR port */
         [2] = {
@@ -105,8 +94,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
                .ucon = 0x3c5,
                .ulcon = 0x43,
                .ufcon = 0xf1,
-               .clocks = rx1950_serial_clocks,
-               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+                .clk_sel = S3C2410_UCON_CLKSEL3,
         },
 };
 
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 80a0972873c..20103bafbd4 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -69,16 +69,6 @@ static struct map_desc rx3715_iodesc[] __initdata = {
         },
 };
 
-
-static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
-        [0] = {
-                .name           = "fclk",
-                .divisor        = 0,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
-
 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
         [0] = {
                 .hwport      = 0,
@@ -86,8 +76,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
                 .ucon        = 0x3c5,
                 .ulcon       = 0x03,
                 .ufcon       = 0x51,
-                .clocks      = rx3715_serial_clocks,
-                .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL3,
         },
         [1] = {
                 .hwport      = 1,
@@ -95,8 +84,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
                 .ucon        = 0x3c5,
                 .ulcon       = 0x03,
                 .ufcon       = 0x00,
-                .clocks      = rx3715_serial_clocks,
-                .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL3,
         },
         /* IR port */
         [2] = {
@@ -105,8 +93,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
                 .ucon        = 0x3c5,
                 .ulcon       = 0x43,
                 .ufcon       = 0x51,
-                .clocks      = rx3715_serial_clocks,
-                .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+                .clk_sel        = S3C2410_UCON_CLKSEL3,
         }
 };
 
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 381586c7b1b..dd20c66cd70 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -78,6 +78,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
         help
           Common setup code for S3C64XX SDHCI GPIO configurations
 
+config S3C64XX_SETUP_SPI
+        bool
+        help
+         Common setup code for SPI GPIO configurations
+
 # S36400 Macchine support
 
 config MACH_SMDK6400
@@ -189,7 +194,7 @@ config SMDK6410_WM1190_EV1
         depends on MACH_SMDK6410
         select REGULATOR
         select REGULATOR_WM8350
-        select S3C24XX_GPIO_EXTRA64
+        select SAMSUNG_GPIO_EXTRA64
         select MFD_WM8350_I2C
         select MFD_WM8350_CONFIG_MODE_0
         select MFD_WM8350_CONFIG_MODE_3
@@ -207,7 +212,7 @@ config SMDK6410_WM1192_EV1
         depends on MACH_SMDK6410
         select REGULATOR
         select REGULATOR_WM831X
-        select S3C24XX_GPIO_EXTRA64
+        select SAMSUNG_GPIO_EXTRA64
         select MFD_WM831X
         select MFD_WM831X_I2C
         help
@@ -277,6 +282,7 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_SETUP_IDE
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
+        select S3C64XX_SETUP_SPI
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_KEYPAD
         select S3C_DEV_USB_HOST
@@ -287,8 +293,8 @@ config MACH_WLF_CRAGG_6410
         select S3C_DEV_I2C1
         select S3C_DEV_WDT
         select S3C_DEV_RTC
-        select S3C64XX_DEV_SPI
-        select S3C24XX_GPIO_EXTRA128
+        select S3C64XX_DEV_SPI0
+        select SAMSUNG_GPIO_EXTRA128
         select I2C
         help
           Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index f37016cebbe..1822ac2eba3 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,8 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0)	+= setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_IDE)         += setup-ide.o
 obj-$(CONFIG_S3C64XX_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S3C64XX_SETUP_SPI)         += setup-spi.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 625219b9cef..31bb27dc4ae 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
         }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
-        }, {
                 .name           = "48m",
                 .devname        = "s3c-sdhci.0",
                 .parent         = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
         },
 };
 
+static struct clk clk_48m_spi0 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.0",
+        .parent         = &clk_48m,
+        .enable         = s3c64xx_sclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
+};
+
+static struct clk clk_48m_spi1 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.1",
+        .parent         = &clk_48m,
+        .enable         = s3c64xx_sclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
+};
+
 static struct clk init_clocks[] = {
         {
                 .name           = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
                 .enable         = s3c64xx_hclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
-        }, {
                 .name           = "otg",
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
         }
 };
 
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
+};
+
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
+};
 
 static struct clk clk_fout_apll = {
         .name           = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                         .name           = "usb-bus-host",
                         .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
                         .enable         = s3c64xx_sclk_ctrl,
@@ -617,35 +596,6 @@ static struct clksrc_clk clksrcs[] = {
                 .sources        = &clkset_uhost,
         }, {
                 .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_UART,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
-                .sources        = &clkset_uart,
-        }, {
-/* Where does UCLK0 come from? */
-                .clk    = {
-                        .name           = "spi-bus",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "spi-bus",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                         .name           = "audio-bus",
                         .devname        = "samsung-i2s.0",
                         .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
@@ -695,6 +645,78 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+/* Where does UCLK0 come from? */
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = S3C_CLKCON_SCLK_UART,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
+        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
+        .sources        = &clkset_uart,
+};
+
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "spi-bus",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
+        .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "spi-bus",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
+        .sources = &clkset_spi_mmc,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -703,6 +725,39 @@ static struct clksrc_clk *init_parents[] = {
         &clk_mout_mpll,
 };
 
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_48m_spi0,
+        &clk_48m_spi1,
+};
+
+static struct clk_lookup s3c64xx_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+};
+
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 void __init_or_cpufreq s3c64xx_setup_clocks(void)
@@ -811,6 +866,8 @@ static struct clk *clks[] __initdata = {
 void __init s3c64xx_register_clocks(unsigned long xtal, 
                                     unsigned armclk_divlimit)
 {
+        unsigned int cnt;
+
         armclk_mask = armclk_divlimit;
 
         s3c24xx_register_baseclocks(xtal);
@@ -821,7 +878,15 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
+                s3c_disable_clocks(clk_cdev[cnt], 1);
+
         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
+                s3c_register_clksrc(clksrc_cdev[cnt], 1);
+        clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
+
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd11872..00000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/dev-spi.c
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/spi-clocks.h>
-#include <mach/irqs.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-
-static char *spi_src_clks[] = {
-        [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
-        [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
-        [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        switch (pdev->id) {
-        case 0:
-                base = S3C64XX_GPC(0);
-                break;
-
-        case 1:
-                base = S3C64XX_GPC(4);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-
-        return 0;
-}
-
-static struct resource s3c64xx_spi0_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_SPI0,
-                .end   = S3C64XX_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-        .cfg_gpio = s3c64xx_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .tx_st_done = 21,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s3c64xx_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s3c64xx_spi0_resource),
-        .resource         = s3c64xx_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s3c64xx_spi0_pdata,
-        },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi0);
-
-static struct resource s3c64xx_spi1_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_SPI1,
-                .end   = S3C64XX_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-        .cfg_gpio = s3c64xx_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .tx_st_done = 21,
-};
-
-struct platform_device s3c64xx_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s3c64xx_spi1_resource),
-        .resource         = s3c64xx_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s3c64xx_spi1_pdata,
-        },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi1);
-
-void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s3c64xx_spi0_pdata;
-                break;
-        case 1:
-                pd = &s3c64xx_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
index be9074e17df..5d55ab018b6 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -15,9 +15,11 @@
 
 #define BANFF_PMIC_IRQ_BASE             IRQ_BOARD_START
 #define GLENFARCLAS_PMIC_IRQ_BASE       (IRQ_BOARD_START + 64)
+#define CODEC_IRQ_BASE                  (IRQ_BOARD_START + 128)
 
 #define PCA935X_GPIO_BASE               GPIO_BOARD_START
-#define CODEC_GPIO_BASE         (GPIO_BOARD_START + 8)
-#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 16)
+#define CODEC_GPIO_BASE                 (GPIO_BOARD_START + 8)
+#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 32)
+#define BANFF_PMIC_GPIO_BASE            (GPIO_BOARD_START + 64)
 
 #endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
index 6e34c2f6e67..8b540c42d5d 100644
--- a/arch/arm/mach-s3c64xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -88,6 +88,6 @@ enum s3c_gpio_number {
 /* define the number of gpios we need to the one after the GPQ() range */
 #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
 
-#define BOARD_NR_GPIOS 16
+#define BOARD_NR_GPIOS  (16 + CONFIG_SAMSUNG_GPIO_EXTRA)
 
 #define ARCH_NR_GPIOS   (GPIO_BOARD_START + BOARD_NR_GPIOS)
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 443f85b3c20..96d60e0d937 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -169,7 +169,7 @@
 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 
 #ifdef CONFIG_MACH_WLF_CRAGG_6410
-#define IRQ_BOARD_NR 128
+#define IRQ_BOARD_NR 160
 #elif defined(CONFIG_SMDK6410_WM1190_EV1)
 #define IRQ_BOARD_NR 64
 #elif defined(CONFIG_SMDK6410_WM1192_EV1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d5..8e2097bb208 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
 #define S3C_PA_RTC              S3C64XX_PA_RTC
 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
+#define S3C_PA_SPI0             S3C64XX_PA_SPI0
+#define S3C_PA_SPI1             S3C64XX_PA_SPI1
 
 #define SAMSUNG_PA_ADC          S3C64XX_PA_ADC
 #define SAMSUNG_PA_CFCON        S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index f208154b138..cd3c97e2ee7 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -14,13 +14,43 @@
 
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
+#include <linux/mfd/wm8994/pdata.h>
 
+#include <sound/wm5100.h>
 #include <sound/wm8996.h>
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 
 #include <mach/crag6410.h>
 
+static struct wm5100_pdata wm5100_pdata = {
+        .ldo_ena = S3C64XX_GPN(7),
+        .irq_flags = IRQF_TRIGGER_HIGH,
+        .gpio_base = CODEC_GPIO_BASE,
+
+        .in_mode = {
+                WM5100_IN_DIFF,
+                WM5100_IN_DIFF,
+                WM5100_IN_DIFF,
+                WM5100_IN_SE,
+        },
+
+        .hp_pol = CODEC_GPIO_BASE + 3,
+        .jack_modes = {
+                { WM5100_MICDET_MICBIAS3, 0, 0 },
+                { WM5100_MICDET_MICBIAS2, 1, 1 },
+        },
+
+        .gpio_defaults = {
+                0,
+                0,
+                0,
+                0,
+                0x2, /* IRQ: CMOS output */
+                0x3, /* CLKOUT: CMOS output */
+        },
+};
+
 static struct wm8996_retune_mobile_config wm8996_retune[] = {
         {
                 .name = "Sub LPF",
@@ -72,7 +102,6 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
                 0x8000 | WM8962_GPIO_FN_DMICDAT,
                 WM8962_GPIO_FN_IRQ,    /* Open drain mode */
         },
-        .irq_active_low = true,
 };
 
 static struct wm9081_pdata wm9081_pdata __initdata = {
@@ -91,6 +120,7 @@ static const struct i2c_board_info wm1254_devs[] = {
 
 static const struct i2c_board_info wm1255_devs[] = {
         { I2C_BOARD_INFO("wm5100", 0x1a),
+          .platform_data = &wm5100_pdata,
           .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
         },
         { I2C_BOARD_INFO("wm9081", 0x6c),
@@ -104,6 +134,24 @@ static const struct i2c_board_info wm1259_devs[] = {
         },
 };
 
+static struct wm8994_pdata wm8994_pdata = {
+        .gpio_base = CODEC_GPIO_BASE,
+        .gpio_defaults = {
+                0x3,          /* IRQ out, active high, CMOS */
+        },
+        .irq_base = CODEC_IRQ_BASE,
+        .ldo = {
+                { .supply = "WALLVDD" },
+                { .supply = "WALLVDD" },
+        },
+};
+
+static const struct i2c_board_info wm1277_devs[] = {
+        { I2C_BOARD_INFO("wm8958", 0x1a),  /* WM8958 is the superset */
+          .platform_data = &wm8994_pdata,
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+        },
+};
 
 static __devinitdata const struct {
         u8 id;
@@ -125,6 +173,8 @@ static __devinitdata const struct {
         { .id = 0x3b, .name = "1255-EV1 Kilchoman",
           .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
         { .id = 0x3c, .name = "1273-EV1 Longmorn" },
+        { .id = 0x3d, .name = "1277-EV1 Littlemill",
+          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
 };
 
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
@@ -154,8 +204,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
                                         "Failed to register dev: %d\n", ret);
                 }
         } else {
-                dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
-                         id, rev);
+                dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
+                         id, rev + 1);
         }
 
         return 0;
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index fb786b6a2ea..680fd758ff2 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -37,6 +37,8 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
 
+#include <sound/wm1250-ev1.h>
+
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -289,6 +291,11 @@ static struct platform_device speyside_wm8962_device = {
         .id             = -1,
 };
 
+static struct platform_device littlemill_device = {
+        .name           = "littlemill",
+        .id             = -1,
+};
+
 static struct regulator_consumer_supply wallvdd_consumers[] = {
         REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
@@ -341,6 +348,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &crag6410_backlight_device,
         &speyside_device,
         &speyside_wm8962_device,
+        &littlemill_device,
         &lowland_device,
         &wallvdd_device,
 };
@@ -374,6 +382,10 @@ static struct regulator_init_data vddarm __initdata = {
         .driver_data = &vddarm_pdata,
 };
 
+static struct regulator_consumer_supply vddint_consumers[] __initdata = {
+        REGULATOR_SUPPLY("vddint", NULL),
+};
+
 static struct regulator_init_data vddint __initdata = {
         .constraints = {
                 .name = "VDDINT",
@@ -382,6 +394,9 @@ static struct regulator_init_data vddint __initdata = {
                 .always_on = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
         },
+        .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
+        .consumer_supplies = vddint_consumers,
+        .supply_regulator = "WALLVDD",
 };
 
 static struct regulator_init_data vddmem __initdata = {
@@ -502,7 +517,8 @@ static struct wm831x_touch_pdata touch_pdata __initdata = {
 static struct wm831x_pdata crag_pmic_pdata __initdata = {
         .wm831x_num = 1,
         .irq_base = BANFF_PMIC_IRQ_BASE,
-        .gpio_base = GPIO_BOARD_START + 8,
+        .gpio_base = BANFF_PMIC_GPIO_BASE,
+        .soft_shutdown = true,
 
         .backup = &banff_backup_pdata,
 
@@ -607,6 +623,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
         .wm831x_num = 2,
         .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
         .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
+        .soft_shutdown = true,
 
         .gpio_defaults = {
                 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
@@ -624,6 +641,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
         .disable_touch = true,
 };
 
+static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
+        .gpios = {
+                [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
+                [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
+                [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
+                [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
+                [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
+        },
+};
+
 static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("wm8311", 0x34),
           .irq = S3C_EINT(0),
@@ -633,7 +660,13 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
         { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
 
-        { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
+        { I2C_BOARD_INFO("wm1250-ev1", 0x27),
+          .platform_data = &wm1250_ev1_pdata },
+};
+
+static struct s3c2410_platform_i2c i2c1_pdata = {
+        .frequency = 400000,
+        .bus_num = 1,
 };
 
 static void __init crag6410_map_io(void)
@@ -694,7 +727,7 @@ static void __init crag6410_machine_init(void)
         s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
 
         s3c_i2c0_set_platdata(&i2c0_pdata);
-        s3c_i2c1_set_platdata(NULL);
+        s3c_i2c1_set_platdata(&i2c1_pdata);
         s3c_fb_set_platdata(&crag6410_lcd_pdata);
 
         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 7d3e81b9dd0..055dac90e0e 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -346,10 +346,23 @@ int __init s3c64xx_pm_init(void)
 
 static __init int s3c64xx_pm_initcall(void)
 {
+        u32 val;
+
         pm_cpu_prep = s3c64xx_pm_prepare;
         pm_cpu_sleep = s3c64xx_cpu_suspend;
         pm_uart_udivslot = 1;
 
+        /*
+         * Unconditionally disable power domains that contain only
+         * blocks which have no mainline driver support.
+         */
+        val = __raw_readl(S3C64XX_NORMAL_CFG);
+        val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
+                 S3C64XX_NORMALCFG_DOMAIN_V_ON |
+                 S3C64XX_NORMALCFG_DOMAIN_I_ON |
+                 S3C64XX_NORMALCFG_DOMAIN_P_ON);
+        __raw_writel(val, S3C64XX_NORMAL_CFG);
+
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
         gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
         gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b2116..00000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
- *
- * Copyright 2008 Simtec Electronics
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c64xx_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",
-        [1] = "hsmmc",
-        [2] = "mmc_bus",
-        /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 00000000000..d9592ad7a82
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
+/* linux/arch/arm/mach-s3c64xx/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 18690c5f99e..c87f6108eeb 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,16 @@ config S5P64X0_SETUP_I2C1
         help
           Common setup code for i2c bus 1.
 
+config S5P64X0_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations
+
+config S5P64X0_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
 # machine support
 
 config MACH_SMDK6440
@@ -45,13 +55,16 @@ config MACH_SMDK6440
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
-        select S3C64XX_DEV_SPI
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
+        select S5P64X0_SETUP_SDHCI_GPIO
         help
           Machine support for the Samsung SMDK6440
 
@@ -62,14 +75,28 @@ config MACH_SMDK6450
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
-        select S3C64XX_DEV_SPI
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
+        select S5P64X0_SETUP_SDHCI_GPIO
         help
           Machine support for the Samsung SMDK6450
 
+menu "Use 8-bit SDHCI bus width"
+
+config S5P64X0_SD_CH1_8BIT
+        bool "SDHCI Channel 1 (Slot 1)"
+        depends on MACH_SMDK6450 || MACH_SMDK6440
+        help
+          Support SDHCI Channel 1 8-bit bus.
+          If selected, Channel 2 is disabled.
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index d3f7409999f..12bb951187a 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -28,8 +28,9 @@ obj-$(CONFIG_MACH_SMDK6450)	+= mach-smdk6450.o
 # device support
 
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 obj-y                                   += setup-i2c0.o
 obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP)    += setup-fb-24bpp.o
+obj-$(CONFIG_S5P64X0_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index eb4ffe331e1..ee1e8e7f563 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -269,18 +269,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 31),
         }, {
-                .name           = "sclk_spi_48",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "sclk_spi_48",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
                 .name           = "mmc_48m",
                 .devname        = "s3c-sdhci.0",
                 .parent         = &clk_48m,
@@ -392,65 +380,6 @@ static struct clksrc_sources clkset_audio = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 24),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 25),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 26),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = (1 << 5),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = (1 << 20),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .ctrlbit        = (1 << 21),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_post",
                         .ctrlbit        = (1 << 10),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -488,6 +417,77 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 24),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 25),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 26),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = (1 << 5),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = (1 << 20),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = (1 << 21),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -506,6 +506,26 @@ static struct clk dummy_apb_pclk = {
         .id             = -1,
 };
 
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2
+};
+
+static struct clk_lookup s5p6440_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
+
 void __init_or_cpufreq s5p6440_setup_clocks(void)
 {
         struct clk *xtal_clk;
@@ -584,9 +604,12 @@ void __init s5p6440_register_clocks(void)
 
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
 
         s3c24xx_register_clock(&dummy_apb_pclk);
 
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index bb7ee912090..dae6a13f43b 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -414,65 +414,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 24),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 25),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 26),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = (1 << 5),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = (1 << 20),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .ctrlbit        = (1 << 21),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_fimc",
                         .ctrlbit        = (1 << 10),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -537,6 +478,97 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 24),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 25),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 26),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = (1 << 5),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = (1 << 20),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = (1 << 21),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+};
+
+static struct clk_lookup s5p6450_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -635,9 +667,12 @@ void __init s5p6450_register_clocks(void)
 
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
 
         s3c24xx_register_clock(&dummy_apb_pclk);
 
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 28d0b918cd4..52b89a37644 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -40,6 +40,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
+#include <plat/sdhci.h>
 #include <plat/adc-core.h>
 #include <plat/fb-core.h>
 #include <plat/gpio-cfg.h>
@@ -181,6 +182,10 @@ void __init s5p6440_map_io(void)
         s3c_adc_setname("s3c64xx-adc");
         s3c_fb_setname("s5p64x0-fb");
 
+        s5p64x0_default_sdhci0();
+        s5p64x0_default_sdhci1();
+        s5p6440_default_sdhci2();
+
         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
         init_consistent_dma_size(SZ_8M);
 }
@@ -191,6 +196,10 @@ void __init s5p6450_map_io(void)
         s3c_adc_setname("s3c64xx-adc");
         s3c_fb_setname("s5p64x0-fb");
 
+        s5p64x0_default_sdhci0();
+        s5p64x0_default_sdhci1();
+        s5p6450_default_sdhci2();
+
         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
         init_consistent_dma_size(SZ_8M);
 }
@@ -282,36 +291,7 @@ int __init s5p64x0_init(void)
         return device_register(&s5p64x0_dev);
 }
 
-static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk_low",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "uclk1",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-
 /* uart registration process */
-
-void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5p64x0_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
-                }
-        }
-}
-
 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
         int uart;
@@ -321,13 +301,11 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
         }
 
-        s5p64x0_common_init_uarts(cfg, no);
         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
-        s5p64x0_common_init_uarts(cfg, no);
         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 1fd9c79c7db..00000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/dev-spi.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-clock.h>
-#include <mach/spi-clocks.h>
-
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-
-static char *s5p64x0_spi_src_clks[] = {
-        [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
-        [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        switch (pdev->id) {
-        case 0:
-                base = S5P6440_GPC(0);
-                break;
-
-        case 1:
-                base = S5P6440_GPC(4);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-
-        return 0;
-}
-
-static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        switch (pdev->id) {
-        case 0:
-                base = S5P6450_GPC(0);
-                break;
-
-        case 1:
-                base = S5P6450_GPC(4);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-
-        return 0;
-}
-
-static struct resource s5p64x0_spi0_resource[] = {
-        [0] = {
-                .start  = S5P64X0_PA_SPI0,
-                .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPI0_TX,
-                .end    = DMACH_SPI0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_SPI0_RX,
-                .end    = DMACH_SPI0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = IRQ_SPI0,
-                .end    = IRQ_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
-        .cfg_gpio       = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
-        .cfg_gpio       = s5p6450_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5p64x0_device_spi0 = {
-        .name           = "s3c64xx-spi",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
-        .resource       = s5p64x0_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource s5p64x0_spi1_resource[] = {
-        [0] = {
-                .start  = S5P64X0_PA_SPI1,
-                .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPI1_TX,
-                .end    = DMACH_SPI1_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_SPI1_RX,
-                .end    = DMACH_SPI1_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = IRQ_SPI1,
-                .end    = IRQ_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
-        .cfg_gpio       = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
-        .cfg_gpio       = s5p6450_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-struct platform_device s5p64x0_device_spi1 = {
-        .name           = "s3c64xx-spi",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
-        .resource       = s5p64x0_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                if (soc_is_s5p6450())
-                        pd = &s5p6450_spi0_pdata;
-                else
-                        pd = &s5p6440_spi0_pdata;
-
-                s5p64x0_device_spi0.dev.platform_data = pd;
-                break;
-        case 1:
-                if (soc_is_s5p6450())
-                        pd = &s5p6450_spi1_pdata;
-                else
-                        pd = &s5p6440_spi1_pdata;
-
-                s5p64x0_device_spi1.dev.platform_data = pd;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 442dd4ad12d..f820c074440 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,176 +38,74 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-struct dma_pl330_peri s5p6440_pdma_peri[22] = {
-        {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = DMACH_MAX,
-        }, {
-                .peri_id = DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        },
+u8 s5p6440_pdma_peri[] = {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_PCM0_TX,
+        DMACH_PCM0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI0_RX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_SPI1_TX,
+        DMACH_SPI1_RX,
 };
 
 struct dma_pl330_platdata s5p6440_pdma_pdata = {
         .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
-        .peri = s5p6440_pdma_peri,
+        .peri_id = s5p6440_pdma_peri,
 };
 
-struct dma_pl330_peri s5p6450_pdma_peri[32] = {
-        {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART4_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART4_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_USI_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_USI_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PWM,
-        }, {
-                .peri_id = (u8)DMACH_UART5_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART5_TX,
-                .rqtype = MEMTODEV,
-        },
+u8 s5p6450_pdma_peri[] = {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_PCM0_TX,
+        DMACH_PCM0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI0_RX,
+        DMACH_PCM1_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM2_TX,
+        DMACH_PCM2_RX,
+        DMACH_SPI1_TX,
+        DMACH_SPI1_RX,
+        DMACH_USI_TX,
+        DMACH_USI_RX,
+        DMACH_MAX,
+        DMACH_I2S1_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S2_TX,
+        DMACH_I2S2_RX,
+        DMACH_PWM,
+        DMACH_UART5_RX,
+        DMACH_UART5_TX,
 };
 
 struct dma_pl330_platdata s5p6450_pdma_pdata = {
         .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
-        .peri = s5p6450_pdma_peri,
+        .peri_id = s5p6450_pdma_peri,
 };
 
 struct amba_device s5p64x0_device_pdma = {
@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = {
 
 static int __init s5p64x0_dma_init(void)
 {
-        if (soc_is_s5p6450())
+        if (soc_is_s5p6450()) {
+                dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
+                dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
                 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
-        else
+        } else {
+                dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
+                dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
                 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+        }
 
         amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
 
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 53982db9d25..5b845e849b3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,6 +141,8 @@
 
 #define IRQ_EINT_GROUP(grp, x)  (IRQ_EINT_GROUP##grp##_BASE + (x))
 
+#define IRQ_TIMER_BASE          (11)
+
 /* Set the default NR_IRQS */
 
 #define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 4d3ac8a3709..0c0175dbfa3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -67,6 +67,8 @@
 #define S3C_PA_RTC              S5P64X0_PA_RTC
 #define S3C_PA_WDT              S5P64X0_PA_WDT
 #define S3C_PA_FB               S5P64X0_PA_FB
+#define S3C_PA_SPI0             S5P64X0_PA_SPI0
+#define S3C_PA_SPI1             S5P64X0_PA_SPI1
 
 #define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
 #define S5P_PA_SROMC            S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 34d98a1dae5..a40e325d62c 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -24,6 +24,7 @@
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/fb.h>
+#include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
 
@@ -52,6 +53,7 @@
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/regs-fb.h>
+#include <plat/sdhci.h>
 
 #include "common.h"
 
@@ -163,6 +165,25 @@ static struct platform_device *smdk6440_devices[] __initdata = {
         &s5p6440_device_iis,
         &s3c_device_fb,
         &smdk6440_lcd_lte480wv,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_INTERNAL,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+        .max_width      = 8,
+        .host_caps      = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
 };
 
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -236,6 +257,10 @@ static void __init smdk6440_machine_init(void)
         s5p6440_set_lcd_interface();
         s3c_fb_set_platdata(&smdk6440_lcd_pdata);
 
+        s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
+
         platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 135cf5d8473..efb69e2f2af 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -24,6 +24,7 @@
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/fb.h>
+#include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
 
@@ -52,6 +53,7 @@
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/regs-fb.h>
+#include <plat/sdhci.h>
 
 #include "common.h"
 
@@ -181,10 +183,28 @@ static struct platform_device *smdk6450_devices[] __initdata = {
         &s5p6450_device_iis0,
         &s3c_device_fb,
         &smdk6450_lcd_lte480wv,
-
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
         /* s5p6450_device_spi0 will be added */
 };
 
+static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+        .max_width      = 8,
+        .host_caps      = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+
 static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
         .flags          = 0,
         .slave_addr     = 0x10,
@@ -256,6 +276,10 @@ static void __init smdk6450_machine_init(void)
         s5p6450_set_lcd_interface();
         s3c_fb_set_platdata(&smdk6450_lcd_pdata);
 
+        s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
+
         platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 00000000000..8410af0d12b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
+/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/sdhci.h>
+#include <plat/cpu.h>
+
+void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+
+        /* Set all the necessary GPG pins to special-function 2 */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
+                                         S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
+                                         S3C_GPIO_SFN(2));
+
+        /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                if (soc_is_s5p6450()) {
+                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
+                } else {
+                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
+                }
+        }
+}
+
+void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+
+        /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
+
+        switch (width) {
+        case 8:
+                /* Set data pins GPH[6:9] special-function 2 */
+                if (soc_is_s5p6450())
+                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
+                                                 S3C_GPIO_SFN(2));
+                else
+                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
+                                                 S3C_GPIO_SFN(2));
+        case 4:
+                /* set data pins GPH[2:5] special-function 2 */
+                if (soc_is_s5p6450())
+                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
+                                                 S3C_GPIO_SFN(2));
+                else
+                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
+                                                 S3C_GPIO_SFN(2));
+        default:
+                break;
+        }
+
+        /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                if (soc_is_s5p6450()) {
+                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
+                } else {
+                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
+                }
+        }
+}
+
+void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
+        s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
+
+        /* Set data pins GPH[6:9] pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
+}
+
+void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        /* Set all the necessary GPG pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
+}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
new file mode 100644
index 00000000000..e9b84124035
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -0,0 +1,55 @@
+/* linux/arch/arm/mach-s5p64x0/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        else
+                s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        else
+                s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index e538a4c67e9..75a26eaf263 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
         help
           Common setup code for SDHCI gpio.
 
+config S5PC100_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations.
+
 config MACH_SMDKC100
         bool "SMDKC100"
         select CPU_S5PC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index c3166c4d2ac..118c711f74e 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -22,12 +22,11 @@ obj-$(CONFIG_MACH_SMDKC100)	+= mach-smdkc100.o
 # device support
 
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 obj-y                                   += setup-i2c0.o
 obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)    += setup-fb-24bpp.o
 obj-$(CONFIG_S5PC100_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5PC100_SETUP_IDE)         += setup-ide.o
 obj-$(CONFIG_S5PC100_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S5PC100_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index c4c74893f53..247194dd366 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -427,24 +427,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pc100_d0_2_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
                 .name           = "modemif",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_0_ctrl,
@@ -674,24 +656,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.2",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
                 .name           = "mmc_48m",
                 .devname        = "s3c-sdhci.0",
                 .parent         = &clk_mout_48m.clk,
@@ -712,6 +676,54 @@ static struct clk init_clocks_off[] = {
         },
 };
 
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 7),
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 6),
+};
+
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 5),
+};
+
+static struct clk clk_48m_spi0 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.0",
+        .parent         = &clk_mout_48m.clk,
+        .enable         = s5pc100_sclk0_ctrl,
+        .ctrlbit        = (1 << 7),
+};
+
+static struct clk clk_48m_spi1 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.1",
+        .parent         = &clk_mout_48m.clk,
+        .enable         = s5pc100_sclk0_ctrl,
+        .ctrlbit        = (1 << 8),
+};
+
+static struct clk clk_48m_spi2 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.2",
+        .parent         = &clk_mout_48m.clk,
+        .enable         = s5pc100_sclk0_ctrl,
+        .ctrlbit        = (1 << 9),
+};
+
 static struct clk clk_vclk54m = {
         .name           = "vclk_54m",
         .rate           = 54000000,
@@ -930,49 +942,6 @@ static struct clksrc_clk clk_sclk_spdif = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = (1 << 4),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .ctrlbit        = (1 << 5),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.2",
-                        .ctrlbit        = (1 << 6),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = (1 << 3),
-                        .enable         = s5pc100_sclk0_ctrl,
-
-                },
-                .sources = &clk_src_group2,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_mixer",
                         .ctrlbit        = (1 << 6),
                         .enable         = s5pc100_sclk0_ctrl,
@@ -1025,39 +994,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
         }, {
                 .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 12),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_mmc0,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 13),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 14),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_irda",
                         .ctrlbit        = (1 << 10),
                         .enable         = s5pc100_sclk0_ctrl,
@@ -1099,6 +1035,89 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+static struct clksrc_clk clk_sclk_uart = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = (1 << 3),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group2,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 12),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc0,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 13),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc12,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 14),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc12,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = (1 << 4),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group1,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = (1 << 5),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group1,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.2",
+                .ctrlbit        = (1 << 6),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group1,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
+};
+
 /* Clock initialisation code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -1128,6 +1147,25 @@ static struct clksrc_clk *sysclks[] = {
         &clk_sclk_spdif,
 };
 
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_48m_spi0,
+        &clk_48m_spi1,
+        &clk_48m_spi2,
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_spi2,
+};
+
 void __init_or_cpufreq s5pc100_setup_clocks(void)
 {
         unsigned long xtal;
@@ -1267,6 +1305,24 @@ static struct clk *clks[] __initdata = {
         &clk_pcmcdclk1,
 };
 
+static struct clk_lookup s5pc100_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+};
+
 void __init s5pc100_register_clocks(void)
 {
         int ptr;
@@ -1278,9 +1334,16 @@ void __init s5pc100_register_clocks(void)
 
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
+
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
 
         s3c24xx_register_clock(&dummy_apb_pclk);
 
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index e5d6c4dceb5..00000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/spi-clocks.h>
-#include <mach/irqs.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-#include <plat/irqs.h>
-
-static char *spi_src_clks[] = {
-        [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
-        [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
-        [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
-                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-                break;
-
-        case 1:
-                s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
-                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-                break;
-
-        case 2:
-                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
-                                      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct resource s5pc100_spi0_resource[] = {
-        [0] = {
-                .start = S5PC100_PA_SPI0,
-                .end   = S5PC100_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
-        .cfg_gpio = s5pc100_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .high_speed = 1,
-        .tx_st_done = 21,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5pc100_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
-        .resource         = s5pc100_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_spi0_pdata,
-        },
-};
-
-static struct resource s5pc100_spi1_resource[] = {
-        [0] = {
-                .start = S5PC100_PA_SPI1,
-                .end   = S5PC100_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
-        .cfg_gpio = s5pc100_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .high_speed = 1,
-        .tx_st_done = 21,
-};
-
-struct platform_device s5pc100_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
-        .resource         = s5pc100_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_spi1_pdata,
-        },
-};
-
-static struct resource s5pc100_spi2_resource[] = {
-        [0] = {
-                .start = S5PC100_PA_SPI2,
-                .end   = S5PC100_PA_SPI2 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI2_TX,
-                .end   = DMACH_SPI2_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI2_RX,
-                .end   = DMACH_SPI2_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI2,
-                .end   = IRQ_SPI2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
-        .cfg_gpio = s5pc100_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .high_speed = 1,
-        .tx_st_done = 21,
-};
-
-struct platform_device s5pc100_device_spi2 = {
-        .name             = "s3c64xx-spi",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
-        .resource         = s5pc100_spi2_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_spi2_pdata,
-        },
-};
-
-void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s5pc100_spi0_pdata;
-                break;
-        case 1:
-                pd = &s5pc100_spi1_pdata;
-                break;
-        case 2:
-                pd = &s5pc100_spi2_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 065a087f5a8..c841f4d313f 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,100 +35,42 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-struct dma_pl330_peri pdma0_peri[30] = {
-        {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = DMACH_IRDA,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_AC97_MICIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_EXTERNAL,
-        }, {
-                .peri_id = (u8)DMACH_PWM,
-        }, {
-                .peri_id = (u8)DMACH_SPDIF,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_HSI_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_HSI_TX,
-                .rqtype = MEMTODEV,
-        },
+u8 pdma0_peri[] = {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_IRDA,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_EXTERNAL,
+        DMACH_PWM,
+        DMACH_SPDIF,
+        DMACH_HSI_RX,
+        DMACH_HSI_TX,
 };
 
 struct dma_pl330_platdata s5pc100_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri = pdma0_peri,
+        .peri_id = pdma0_peri,
 };
 
 struct amba_device s5pc100_device_pdma0 = {
@@ -147,98 +89,42 @@ struct amba_device s5pc100_device_pdma0 = {
         .periphid = 0x00041330,
 };
 
-struct dma_pl330_peri pdma1_peri[30] = {
-        {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = DMACH_IRDA,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ0,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ1,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ2,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ3,
-        },
+u8 pdma1_peri[] = {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_IRDA,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_MSM_REQ0,
+        DMACH_MSM_REQ1,
+        DMACH_MSM_REQ2,
+        DMACH_MSM_REQ3,
 };
 
 struct dma_pl330_platdata s5pc100_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri = pdma1_peri,
+        .peri_id = pdma1_peri,
 };
 
 struct amba_device s5pc100_device_pdma1 = {
@@ -259,7 +145,12 @@ struct amba_device s5pc100_device_pdma1 = {
 
 static int __init s5pc100_dma_init(void)
 {
+        dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
         amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
+
+        dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
         amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
 
         return 0;
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index d2eb4757381..2870f12c792 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -97,6 +97,8 @@
 #define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
 #define IRQ_VIC_END             S5P_IRQ_VIC2(31)
 
+#define IRQ_TIMER_BASE          (11)
+
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index ccbe6b767f7..54bc4f82e17 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -100,6 +100,9 @@
 #define S3C_PA_USB_HSOTG                S5PC100_PA_USB_HSOTG
 #define S3C_PA_USB_HSPHY                S5PC100_PA_USB_HSPHY
 #define S3C_PA_WDT                      S5PC100_PA_WATCHDOG
+#define S3C_PA_SPI0                     S5PC100_PA_SPI0
+#define S3C_PA_SPI1                     S5PC100_PA_SPI1
+#define S3C_PA_SPI2                     S5PC100_PA_SPI2
 
 #define S5P_PA_CHIPID                   S5PC100_PA_CHIPID
 #define S5P_PA_FIMC0                    S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e8a7b..00000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
- *
- * Copyright 2008 Samsung Electronics
- *
- * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c6410/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s5pc100_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",          /* HCLK */
-        /* [1] = "hsmmc",       - duplicate HCLK entry */
-        [2] = "sclk_mmc",       /* mmc_bus */
-        /* [3] = "48m",         - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
new file mode 100644
index 00000000000..431a6f747ca
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-s5pc100/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .high_speed     = 1,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .high_speed     = 1,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI2
+struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .high_speed     = 1,
+        .tx_st_done     = 21,
+};
+
+int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
+        s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
+                                S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 646057ab2e4..2cdc42e838b 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC
         help
           Common setup code for the camera interfaces.
 
+config S5PV210_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations.
+
 menu "S5PC110 Machines"
 
 config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 4c59186de95..76a121dd52b 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_MACH_TORBRECK)	+= mach-torbreck.o
 # device support
 
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 obj-y                                   += setup-i2c0.o
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
@@ -38,5 +37,5 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2)        += setup-i2c2.o
 obj-$(CONFIG_S5PV210_SETUP_IDE)         += setup-ide.o
 obj-$(CONFIG_S5PV210_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S5PV210_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 04c9b578e62..c78dfddd77f 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -400,30 +400,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip1_ctrl,
                 .ctrlbit        = (1<<25),
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<16),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<17),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<18),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<19),
-        }, {
                 .name           = "systimer",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
@@ -560,6 +536,38 @@ static struct clk init_clocks[] = {
         },
 };
 
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<16),
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<17),
+};
+
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<18),
+};
+
+static struct clk clk_hsmmc3 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.3",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<19),
+};
+
 static struct clk *clkset_uart_list[] = {
         [6] = &clk_mout_mpll.clk,
         [7] = &clk_mout_epll.clk,
@@ -810,46 +818,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
         }, {
                 .clk    = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 13),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.2",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 14),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.3",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 15),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_fimc",
                         .devname        = "s5pv210-fimc.0",
                         .enable         = s5pv210_clk_mask1_ctrl,
@@ -907,46 +875,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 9),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 10),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.3",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 11),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
                         .name           = "sclk_mfc",
                         .devname        = "s5p-mfc",
                         .enable         = s5pv210_clk_ip0_ctrl,
@@ -984,26 +912,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 17),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
                         .name           = "sclk_pwi",
                         .enable         = s5pv210_clk_mask0_ctrl,
                         .ctrlbit        = (1 << 29),
@@ -1023,6 +931,147 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+static struct clksrc_clk clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart1 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 13),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart2 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.2",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 14),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart3 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.3",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 15),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 9),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 10),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 11),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
+        };
+
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 17),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
+        };
+
+
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart0,
+        &clk_sclk_uart1,
+        &clk_sclk_uart2,
+        &clk_sclk_uart3,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_mmc3,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_hsmmc3,
+};
+
 /* Clock initialisation code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -1262,6 +1311,25 @@ static struct clk *clks[] __initdata = {
         &clk_pcmcdclk2,
 };
 
+static struct clk_lookup s5pv210_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
+        CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
+        CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
+        CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
+        CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+};
+
 void __init s5pv210_register_clocks(void)
 {
         int ptr;
@@ -1274,11 +1342,19 @@ void __init s5pv210_register_clocks(void)
         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
                 s3c_register_clksrc(sclk_tv[ptr], 1);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
+
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
 
         s3c24xx_register_clock(&dummy_apb_pclk);
         s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 0ec393305d7..9c1bcdcc12c 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -254,28 +254,9 @@ int __init s5pv210_init(void)
         return device_register(&s5pv210_dev);
 }
 
-static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-
 /* uart registration process */
 
 void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5pv210_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
-                }
-        }
-
         s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
 }
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
deleted file mode 100644
index eaf9a7bff7a..00000000000
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/spi-clocks.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-
-static char *spi_src_clks[] = {
-        [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
-        [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        switch (pdev->id) {
-        case 0:
-                base = S5PV210_GPB(0);
-                break;
-
-        case 1:
-                base = S5PV210_GPB(4);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-
-        return 0;
-}
-
-static struct resource s5pv210_spi0_resource[] = {
-        [0] = {
-                .start = S5PV210_PA_SPI0,
-                .end   = S5PV210_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
-        .cfg_gpio = s5pv210_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x1ff,
-        .rx_lvl_offset = 15,
-        .high_speed = 1,
-        .tx_st_done = 25,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5pv210_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5pv210_spi0_resource),
-        .resource         = s5pv210_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_spi0_pdata,
-        },
-};
-
-static struct resource s5pv210_spi1_resource[] = {
-        [0] = {
-                .start = S5PV210_PA_SPI1,
-                .end   = S5PV210_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
-        .cfg_gpio = s5pv210_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 15,
-        .high_speed = 1,
-        .tx_st_done = 25,
-};
-
-struct platform_device s5pv210_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pv210_spi1_resource),
-        .resource         = s5pv210_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_spi1_pdata,
-        },
-};
-
-void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s5pv210_spi0_pdata;
-                break;
-        case 1:
-                pd = &s5pv210_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 86b749c18b7..a6113e0267f 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,90 +35,40 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-struct dma_pl330_peri pdma0_peri[28] = {
-        {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_AC97_MICIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_PWM,
-        }, {
-                .peri_id = (u8)DMACH_SPDIF,
-                .rqtype = MEMTODEV,
-        },
+u8 pdma0_peri[] = {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_MAX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_MAX,
+        DMACH_PWM,
+        DMACH_SPDIF,
 };
 
 struct dma_pl330_platdata s5pv210_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri = pdma0_peri,
+        .peri_id = pdma0_peri,
 };
 
 struct amba_device s5pv210_device_pdma0 = {
@@ -137,102 +87,44 @@ struct amba_device s5pv210_device_pdma0 = {
         .periphid = 0x00041330,
 };
 
-struct dma_pl330_peri pdma1_peri[32] = {
-        {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ0,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ1,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ2,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ3,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_TX,
-                .rqtype = MEMTODEV,
-        },
+u8 pdma1_peri[] = {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_MAX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_MAX,
+        DMACH_MAX,
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_MSM_REQ0,
+        DMACH_MSM_REQ1,
+        DMACH_MSM_REQ2,
+        DMACH_MSM_REQ3,
+        DMACH_PCM2_RX,
+        DMACH_PCM2_TX,
 };
 
 struct dma_pl330_platdata s5pv210_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri = pdma1_peri,
+        .peri_id = pdma1_peri,
 };
 
 struct amba_device s5pv210_device_pdma1 = {
@@ -253,7 +145,12 @@ struct amba_device s5pv210_device_pdma1 = {
 
 static int __init s5pv210_dma_init(void)
 {
+        dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
         amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
+
+        dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
         amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
 
         return 0;
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 5e0de3a31f3..e777e010ed2 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,6 +118,8 @@
 #define IRQ_MDNIE3              S5P_IRQ_VIC3(8)
 #define IRQ_VIC_END             S5P_IRQ_VIC3(31)
 
+#define IRQ_TIMER_BASE          (11)
+
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 7ff609f1568..89c34b8f73b 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -109,6 +109,8 @@
 #define S3C_PA_RTC                      S5PV210_PA_RTC
 #define S3C_PA_USB_HSOTG                S5PV210_PA_HSOTG
 #define S3C_PA_WDT                      S5PV210_PA_WATCHDOG
+#define S3C_PA_SPI0                     S5PV210_PA_SPI0
+#define S3C_PA_SPI1                     S5PV210_PA_SPI1
 
 #define S5P_PA_CHIPID                   S5PV210_PA_CHIPID
 #define S5P_PA_FIMC0                    S5PV210_PA_FIMC0
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 6f7dfe993c1..5e734d025a6 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -597,8 +597,7 @@ static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
 
 static void aquila_setup_sdhci(void)
 {
-        gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN");
-        gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
+        gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
 
         s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
         s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 12c69371739..ff915261043 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -229,8 +229,7 @@ static void __init goni_radio_init(void)
         i2c1_devs[0].irq = gpio_to_irq(gpio);
 
         gpio = S5PV210_GPJ2(5);                 /* XMSMDATA_5 */
-        gpio_request(gpio, "FM_RST");
-        gpio_direction_output(gpio, 1);
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
 }
 
 /* TSP */
@@ -266,8 +265,7 @@ static void __init goni_tsp_init(void)
         int gpio;
 
         gpio = S5PV210_GPJ1(3);         /* XMSMADDR_11 */
-        gpio_request(gpio, "TSP_LDO_ON");
-        gpio_direction_output(gpio, 1);
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
         gpio_export(gpio, 0);
 
         gpio = S5PV210_GPJ0(5);         /* XMSMADDR_5 */
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index b4021dd802a..dff9ea7b5bb 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -155,15 +155,12 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
 {
         if (power) {
 #if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request(S5PV210_GPD0(3), "GPD0");
-                gpio_direction_output(S5PV210_GPD0(3), 1);
+                gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
                 gpio_free(S5PV210_GPD0(3));
 #endif
 
                 /* fire nRESET on power up */
-                gpio_request(S5PV210_GPH0(6), "GPH0");
-
-                gpio_direction_output(S5PV210_GPH0(6), 1);
+                gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
 
                 gpio_set_value(S5PV210_GPH0(6), 0);
                 mdelay(10);
@@ -174,8 +171,7 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
                 gpio_free(S5PV210_GPH0(6));
         } else {
 #if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request(S5PV210_GPD0(3), "GPD0");
-                gpio_direction_output(S5PV210_GPD0(3), 0);
+                gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
                 gpio_free(S5PV210_GPD0(3));
 #endif
         }
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4d35f..00000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s5pv210_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",          /* HCLK */
-        /* [1] = "hsmmc",       - duplicate HCLK entry */
-        [2] = "sclk_mmc",       /* mmc_bus */
-        /* [3] = NULL,          - reserved */
-};
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
new file mode 100644
index 00000000000..f43c5048a37
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -0,0 +1,51 @@
+/* linux/arch/arm/mach-s5pv210/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .tx_st_done     = 25,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index dab3c6347a8..d6df9f6c9f7 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,17 +11,39 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
 
-/*
- * Very simple clock implementation - we only have one clock to deal with.
- */
+struct clkops {
+        void                    (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        unsigned long           (*getrate)(struct clk *);
+};
+
 struct clk {
+        const struct clkops     *ops;
+        unsigned long           rate;
         unsigned int            enabled;
 };
 
-static void clk_gpio27_enable(void)
+#define INIT_CLKREG(_clk, _devname, _conname)           \
+        {                                               \
+                .clk            = _clk,                 \
+                .dev_id         = _devname,             \
+                .con_id         = _conname,             \
+        }
+
+#define DEFINE_CLK(_name, _ops, _rate)                  \
+struct clk clk_##_name = {                              \
+                .ops    = _ops,                         \
+                .rate   = _rate,                        \
+        }
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+static void clk_gpio27_enable(struct clk *clk)
 {
         /*
          * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -32,38 +54,22 @@ static void clk_gpio27_enable(void)
         TUCR = TUCR_3_6864MHz;
 }
 
-static void clk_gpio27_disable(void)
+static void clk_gpio27_disable(struct clk *clk)
 {
         TUCR = 0;
         GPDR &= ~GPIO_32_768kHz;
         GAFR &= ~GPIO_32_768kHz;
 }
 
-static struct clk clk_gpio27;
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        const char *devname = dev_name(dev);
-
-        return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
 
         spin_lock_irqsave(&clocks_lock, flags);
         if (clk->enabled++ == 0)
-                clk_gpio27_enable();
+                clk->ops->enable(clk);
         spin_unlock_irqrestore(&clocks_lock, flags);
+
         return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -76,13 +82,48 @@ void clk_disable(struct clk *clk)
 
         spin_lock_irqsave(&clocks_lock, flags);
         if (--clk->enabled == 0)
-                clk_gpio27_disable();
+                clk->ops->disable(clk);
         spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
-        return 3686400;
+        unsigned long rate;
+
+        rate = clk->rate;
+        if (clk->ops->getrate)
+                rate = clk->ops->getrate(clk);
+
+        return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
+
+const struct clkops clk_gpio27_ops = {
+        .enable         = clk_gpio27_enable,
+        .disable        = clk_gpio27_disable,
+};
+
+static void clk_dummy_enable(struct clk *clk) { }
+static void clk_dummy_disable(struct clk *clk) { }
+
+const struct clkops clk_dummy_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+};
+
+static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400);
+static DEFINE_CLK(dummy, &clk_dummy_ops, 0);
+
+static struct clk_lookup sa11xx_clkregs[] = {
+        INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
+};
+
+static int __init sa11xx_clk_init(void)
+{
+        clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
+        return 0;
+}
+
+postcore_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index bb10ee2cb89..480d2ea46b0 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -345,9 +345,29 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
         sa11x0_register_device(&sa11x0ir_device, irda);
 }
 
+static struct resource sa11x0rtc_resources[] = {
+        [0] = {
+                .start  = 0x90010000,
+                .end    = 0x900100ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device sa11x0rtc_device = {
         .name           = "sa1100-rtc",
         .id             = -1,
+        .resource       = sa11x0rtc_resources,
+        .num_resources  = ARRAY_SIZE(sa11x0rtc_resources),
 };
 
 static struct platform_device *sa11x0_devices[] __initdata = {
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 91aff7cb828..373652d76b9 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,11 +2,8 @@ if ARCH_TEGRA
 
 comment "NVIDIA Tegra options"
 
-choice
-        prompt "Select Tegra processor family for target system"
-
 config ARCH_TEGRA_2x_SOC
-        bool "Tegra 2 family"
+        bool "Enable support for Tegra20 family"
         select CPU_V7
         select ARM_GIC
         select ARCH_REQUIRE_GPIOLIB
@@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
-endchoice
+config ARCH_TEGRA_3x_SOC
+        bool "Enable support for Tegra30 family"
+        select CPU_V7
+        select ARM_GIC
+        select ARCH_REQUIRE_GPIOLIB
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
+        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select USE_OF
+        help
+          Support for NVIDIA Tegra T30 processor family, based on the
+          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
 config TEGRA_PCI
         bool "PCI Express support"
+        depends on ARCH_TEGRA_2x_SOC
         select PCI
 
 comment "Tegra board type"
 
 config MACH_HARMONY
        bool "Harmony board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Harmony development platform
 
 config MACH_KAEN
        bool "Kaen board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
@@ -40,11 +51,13 @@ config MACH_KAEN
 
 config MACH_PAZ00
        bool "Paz00 board"
+       depends on ARCH_TEGRA_2x_SOC
        help
          Support for the Toshiba AC100/Dynabook AZ netbook
 
 config MACH_SEABOARD
        bool "Seaboard board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Seaboard development platform. It will
@@ -52,25 +65,29 @@ config MACH_SEABOARD
          have large similarities with the seaboard design.
 
 config MACH_TEGRA_DT
-        bool "Generic Tegra board (FDT support)"
+        bool "Generic Tegra20 board (FDT support)"
+        depends on ARCH_TEGRA_2x_SOC
         select USE_OF
         help
-          Support for generic nVidia Tegra boards using Flattened Device Tree
+          Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
 
 config MACH_TRIMSLICE
        bool "TrimSlice board"
+       depends on ARCH_TEGRA_2x_SOC
        select TEGRA_PCI
        help
          Support for CompuLab TrimSlice platform
 
 config MACH_WARIO
        bool "Wario board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
        help
          Support for the Wario version of Seaboard
 
 config MACH_VENTANA
        bool "Ventana board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_TEGRA_DT
        help
          Support for the nVidia Ventana development platform
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 91a07e18720..e120ff54f66 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,4 @@
+obj-y                                   += board-pinmux.o
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
@@ -5,12 +6,13 @@ obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += pinmux.o
-obj-y                                   += powergate.o
 obj-y                                   += fuse.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-t2-tables.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
@@ -18,20 +20,22 @@ obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 
-obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
-obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
-obj-${CONFIG_MACH_HARMONY}              += board-harmony-pcie.o
-obj-${CONFIG_MACH_HARMONY}              += board-harmony-power.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
 
-obj-${CONFIG_MACH_PAZ00}                += board-paz00.o
-obj-${CONFIG_MACH_PAZ00}                += board-paz00-pinmux.o
+obj-$(CONFIG_MACH_PAZ00)                += board-paz00.o
+obj-$(CONFIG_MACH_PAZ00)                += board-paz00-pinmux.o
 
-obj-${CONFIG_MACH_SEABOARD}             += board-seaboard.o
-obj-${CONFIG_MACH_SEABOARD}             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard.o
+obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard-pinmux.o
 
-obj-${CONFIG_MACH_TEGRA_DT}             += board-dt.o
-obj-${CONFIG_MACH_TEGRA_DT}             += board-harmony-pinmux.o
-obj-${CONFIG_MACH_TEGRA_DT}             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-dt-tegra20.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-harmony-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-paz00-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-trimslice-pinmux.o
 
-obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice.o
-obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice-pinmux.o
+obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
+obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index bd12c9fb81e..9a82094092d 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
 
 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
+dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
 dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
+dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
 dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e417a8383db..7a95e0bc4ab 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -37,6 +37,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/irqs.h>
@@ -47,10 +48,14 @@
 #include "devices.h"
 
 void harmony_pinmux_init(void);
+void paz00_pinmux_init(void);
 void seaboard_pinmux_init(void);
+void trimslice_pinmux_init(void);
 void ventana_pinmux_init(void);
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -58,16 +63,30 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
+                       &tegra_ehci1_device.dev.platform_data),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
+                       &tegra_ehci2_device.dev.platform_data),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
+                       &tegra_ehci3_device.dev.platform_data),
         {}
 };
 
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "uartd",      "pll_p",        216000000,      true },
+        { "usbd",       "clk_m",        12000000,       false },
+        { "usb2",       "clk_m",        12000000,       false },
+        { "usb3",       "clk_m",        12000000,       false },
+        { "pll_a",      "pll_p_out1",   56448000,       true },
+        { "pll_a_out0", "pll_a",        11289600,       true },
+        { "cdev1",      NULL,           0,              true },
+        { "i2s1",       "pll_a_out0",   11289600,       false},
+        { "i2s2",       "pll_a_out0",   11289600,       false},
         { NULL,         NULL,           0,              0},
 };
 
@@ -76,39 +95,23 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
         {}
 };
 
-static struct of_device_id tegra_dt_gic_match[] __initdata = {
-        { .compatible = "nvidia,tegra20-gic", },
-        {}
-};
-
 static struct {
         char *machine;
         void (*init)(void);
 } pinmux_configs[] = {
+        { "compulab,trimslice", trimslice_pinmux_init },
         { "nvidia,harmony", harmony_pinmux_init },
+        { "compal,paz00", paz00_pinmux_init },
         { "nvidia,seaboard", seaboard_pinmux_init },
         { "nvidia,ventana", ventana_pinmux_init },
 };
 
 static void __init tegra_dt_init(void)
 {
-        struct device_node *node;
         int i;
 
-        node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
-                                                TEGRA_ARM_INT_DIST_BASE);
-        if (node)
-                irq_domain_add_simple(node, INT_GIC_BASE);
-
         tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-        /*
-         * Finished with the static registrations now; fill in the missing
-         * devices
-         */
-        of_platform_populate(NULL, tegra_dt_match_table,
-                                tegra20_auxdata_lookup, NULL);
-
         for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
                 if (of_machine_is_compatible(pinmux_configs[i].machine)) {
                         pinmux_configs[i].init();
@@ -118,22 +121,31 @@ static void __init tegra_dt_init(void)
 
         WARN(i == ARRAY_SIZE(pinmux_configs),
                 "Unknown platform! Pinmuxing not initialized\n");
+
+        /*
+         * Finished with the static registrations now; fill in the missing
+         * devices
+         */
+        of_platform_populate(NULL, tegra_dt_match_table,
+                                tegra20_auxdata_lookup, NULL);
 }
 
-static const char * tegra_dt_board_compat[] = {
+static const char *tegra20_dt_board_compat[] = {
+        "compulab,trimslice",
         "nvidia,harmony",
+        "compal,paz00",
         "nvidia,seaboard",
         "nvidia,ventana",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
-        .init_irq       = tegra_init_irq,
+        .init_early     = tegra20_init_early,
+        .init_irq       = tegra_dt_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_dt_init,
         .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra_dt_board_compat,
+        .dt_compat      = tegra20_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
new file mode 100644
index 00000000000..3c197e2440b
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-tegra/board-dt-tegra30.c
+ *
+ * NVIDIA Tegra30 device tree board support
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * Derived from:
+ *
+ * arch/arm/mach-tegra/board-dt-tegra20.c
+ *
+ * Copyright (C) 2010 Secret Lab Technologies, Ltd.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include "board.h"
+
+static struct of_device_id tegra_dt_match_table[] __initdata = {
+        { .compatible = "simple-bus", },
+        {}
+};
+
+static void __init tegra30_dt_init(void)
+{
+        of_platform_populate(NULL, tegra_dt_match_table,
+                                NULL, NULL);
+}
+
+static const char *tegra30_dt_board_compat[] = {
+        "nvidia,cardhu",
+        NULL
+};
+
+DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
+        .map_io         = tegra_map_common_io,
+        .init_early     = tegra30_init_early,
+        .init_irq       = tegra_dt_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .timer          = &tegra_timer,
+        .init_machine   = tegra30_dt_init,
+        .restart        = tegra_assert_system_reset,
+        .dt_compat      = tegra30_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 6db7d699ef1..33c4fedab84 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -22,7 +22,6 @@
 
 #include <asm/mach-types.h>
 
-#include <mach/pinmux.h>
 #include "board.h"
 #include "board-harmony.h"
 
@@ -48,10 +47,6 @@ static int __init harmony_pcie_init(void)
 
         regulator_enable(regulator);
 
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
-
         err = tegra_pcie_init(true, true);
         if (err)
                 goto err_pcie;
@@ -59,10 +54,6 @@ static int __init harmony_pcie_init(void)
         return 0;
 
 err_pcie:
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
-
         regulator_disable(regulator);
         regulator_put(regulator);
 err_reg:
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 7a4a26d5174..465808c8ac0 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -19,10 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
 #include "board-harmony.h"
-#include "devices.h"
+#include "board-pinmux.h"
 
 static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -143,11 +144,6 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true  },
         { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true  },
@@ -161,13 +157,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_EXT_MIC_EN,        .enable = true  },
 };
 
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = harmony_pinmux,
+        .pg_count = ARRAY_SIZE(harmony_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
 void harmony_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-
-        tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
-
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 70ee674131f..a0f9634f672 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony")
         .atag_offset    = 0x100,
         .fixup          = tegra_harmony_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index be30e215f4b..c775572dcea 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -19,10 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
 #include "board-paz00.h"
-#include "devices.h"
+#include "board-pinmux.h"
 
 static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -30,7 +31,7 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_PLLC_OUT1,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@@ -143,11 +144,6 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
         { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
@@ -158,13 +154,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_WIFI_LED,       .enable = true },
 };
 
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = paz00_pinmux,
+        .pg_count = ARRAY_SIZE(paz00_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
 void paz00_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-
-        tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux));
-
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 33d6205ad30..fcf4f377b1d 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -23,8 +23,10 @@
 #include <linux/serial_8250.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/gpio_keys.h>
 #include <linux/pda_power.h>
 #include <linux/io.h>
+#include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
@@ -115,12 +117,37 @@ static struct platform_device leds_gpio = {
         },
 };
 
+static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = TEGRA_GPIO_POWERKEY,
+                .active_low     = 1,
+                .desc           = "Power",
+                .type           = EV_KEY,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data paz00_gpio_keys = {
+        .buttons        = paz00_gpio_keys_buttons,
+        .nbuttons       = ARRAY_SIZE(paz00_gpio_keys_buttons),
+};
+
+static struct platform_device gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &paz00_gpio_keys,
+        },
+};
+
 static struct platform_device *paz00_devices[] __initdata = {
         &debug_uart,
         &tegra_sdhci_device4,
         &tegra_sdhci_device1,
         &wifi_rfkill_device,
         &leds_gpio,
+        &gpio_keys_device,
 };
 
 static void paz00_i2c_init(void)
@@ -189,7 +216,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
         .atag_offset    = 0x100,
         .fixup          = tegra_paz00_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 8aff06eb58c..ffa83f580db 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -32,6 +32,9 @@
 #define TEGRA_WIFI_RST                  TEGRA_GPIO_PD1
 #define TEGRA_WIFI_LED                  TEGRA_GPIO_PD0
 
+/* WakeUp */
+#define TEGRA_GPIO_POWERKEY     TEGRA_GPIO_PJ7
+
 void paz00_pinmux_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
new file mode 100644
index 00000000000..adc3efe979b
--- /dev/null
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/notifier.h>
+#include <linux/of.h>
+#include <linux/string.h>
+
+#include <mach/gpio-tegra.h>
+#include <mach/pinmux.h>
+
+#include "board-pinmux.h"
+#include "devices.h"
+
+struct tegra_board_pinmux_conf *confs[2];
+
+static void tegra_board_pinmux_setup_gpios(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+                if (!confs[i])
+                        continue;
+
+                tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
+        }
+}
+
+static void tegra_board_pinmux_setup_pinmux(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+                if (!confs[i])
+                        continue;
+
+                tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
+
+                if (confs[i]->drives)
+                        tegra_drive_pinmux_config_table(confs[i]->drives,
+                                                        confs[i]->drive_count);
+        }
+}
+
+static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
+                                         unsigned long event, void *vdev)
+{
+        static bool had_gpio;
+        static bool had_pinmux;
+
+        struct device *dev = vdev;
+        const char *devname;
+
+        if (event != BUS_NOTIFY_BOUND_DRIVER)
+                return NOTIFY_DONE;
+
+        devname = dev_name(dev);
+
+        if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
+                tegra_board_pinmux_setup_gpios();
+                had_gpio = true;
+        } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
+                tegra_board_pinmux_setup_pinmux();
+                had_pinmux = true;
+        }
+
+        if (had_gpio && had_pinmux)
+                return NOTIFY_STOP_MASK;
+        else
+                return NOTIFY_DONE;
+}
+
+static struct notifier_block nb = {
+        .notifier_call = tegra_board_pinmux_bus_notify,
+};
+
+static struct platform_device *devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
+
+void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
+                             struct tegra_board_pinmux_conf *conf_b)
+{
+        confs[0] = conf_a;
+        confs[1] = conf_b;
+
+        bus_register_notifier(&platform_bus_type, &nb);
+
+        if (!of_machine_is_compatible("nvidia,tegra20"))
+                platform_add_devices(devices, ARRAY_SIZE(devices));
+}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
new file mode 100644
index 00000000000..4aac73546f5
--- /dev/null
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_BOARD_PINMUX_H
+#define __MACH_TEGRA_BOARD_PINMUX_H
+
+#define GPIO_DEV "tegra-gpio"
+#define PINMUX_DEV "tegra-pinmux"
+
+struct tegra_pingroup_config;
+struct tegra_gpio_table;
+
+struct tegra_board_pinmux_conf {
+        struct tegra_pingroup_config *pgs;
+        int pg_count;
+
+        struct tegra_drive_pingroup_config *drives;
+        int drive_count;
+
+        struct tegra_gpio_table *gpios;
+        int gpio_count;
+};
+
+void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
+                             struct tegra_board_pinmux_conf *conf_b);
+
+#endif
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index b1c2972f62f..55e7e43a14a 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -19,11 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
-#include <mach/pinmux-t2.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
+#include "board-pinmux.h"
 #include "board-seaboard.h"
-#include "devices.h"
 
 #define DEFAULT_DRIVE(_name)                                    \
         {                                                       \
@@ -37,11 +37,11 @@
                 .slew_falling = TEGRA_SLEW_SLOWEST,             \
         }
 
-static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
+static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
         DEFAULT_DRIVE(SDIO1),
 };
 
-static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
+static struct tegra_pingroup_config common_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -55,7 +55,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
@@ -65,7 +64,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -108,13 +106,8 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_LM0,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LM1,   TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
@@ -122,25 +115,19 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
@@ -160,13 +147,24 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
-        {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+static struct tegra_pingroup_config seaboard_pinmux[] = {
+        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+};
+
+static struct tegra_pingroup_config ventana_pinmux[] = {
         {TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTB,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTC,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTD,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -181,65 +179,59 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
         {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table common_gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true },
         { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true },
         { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true },
+        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
+};
+
+static struct tegra_gpio_table seaboard_gpio_table[] = {
         { .gpio = TEGRA_GPIO_LIDSWITCH,         .enable = true },
         { .gpio = TEGRA_GPIO_POWERKEY,          .enable = true },
         { .gpio = TEGRA_GPIO_HP_DET,            .enable = true },
         { .gpio = TEGRA_GPIO_ISL29018_IRQ,      .enable = true },
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
         { .gpio = TEGRA_GPIO_USB1,              .enable = true },
 };
 
-static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
-{
-        int i, j;
-        struct tegra_pingroup_config *new_pingroup, *base_pingroup;
-
-        /* Update base seaboard pinmux table with secondary board
-         * specific pinmux table table.
-         */
-        for (i = 0; i < size; i++) {
-                new_pingroup = &newtbl[i];
-                for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
-                        base_pingroup = &seaboard_pinmux[j];
-                        if (new_pingroup->pingroup == base_pingroup->pingroup) {
-                                *base_pingroup = *new_pingroup;
-                                break;
-                        }
-                }
-        }
-}
-
-void __init seaboard_common_pinmux_init(void)
-{
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
+static struct tegra_gpio_table ventana_gpio_table[] = {
+        /* hp_det */
+        { .gpio = TEGRA_GPIO_PW2,               .enable = true },
+        /* int_mic_en */
+        { .gpio = TEGRA_GPIO_PX0,               .enable = true },
+        /* ext_mic_en */
+        { .gpio = TEGRA_GPIO_PX1,               .enable = true },
+};
 
-        tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
+static struct tegra_board_pinmux_conf common_conf = {
+        .pgs = common_pinmux,
+        .pg_count = ARRAY_SIZE(common_pinmux),
+        .gpios = common_gpio_table,
+        .gpio_count = ARRAY_SIZE(common_gpio_table),
+};
 
-        tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
-                                        ARRAY_SIZE(seaboard_drive_pinmux));
+static struct tegra_board_pinmux_conf seaboard_conf = {
+        .pgs = seaboard_pinmux,
+        .pg_count = ARRAY_SIZE(seaboard_pinmux),
+        .drives = seaboard_drive_pinmux,
+        .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
+        .gpios = seaboard_gpio_table,
+        .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
+};
 
-        tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
-}
+static struct tegra_board_pinmux_conf ventana_conf = {
+        .pgs = ventana_pinmux,
+        .pg_count = ARRAY_SIZE(ventana_pinmux),
+        .gpios = ventana_gpio_table,
+        .gpio_count = ARRAY_SIZE(ventana_gpio_table),
+};
 
-void __init seaboard_pinmux_init(void)
+void seaboard_pinmux_init(void)
 {
-        seaboard_common_pinmux_init();
+        tegra_board_pinmux_init(&common_conf, &seaboard_conf);
 }
 
-void __init ventana_pinmux_init(void)
+void ventana_pinmux_init(void)
 {
-        update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
-        seaboard_common_pinmux_init();
+        tegra_board_pinmux_init(&common_conf, &ventana_conf);
 }
-
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index c1599eb8e0c..cfc74d46a09 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -283,7 +283,7 @@ static void __init tegra_wario_init(void)
 MACHINE_START(SEABOARD, "seaboard")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
@@ -294,7 +294,7 @@ MACHINE_END
 MACHINE_START(KAEN, "kaen")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
@@ -305,7 +305,7 @@ MACHINE_END
 MACHINE_START(WARIO, "wario")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index 7ab719d46da..a21a2be57cb 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -19,12 +19,13 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
+#include "board-pinmux.h"
 #include "board-trimslice.h"
-#include "devices.h"
 
-static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
+static struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
@@ -105,7 +106,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_RSVD3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
@@ -143,11 +144,6 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
         { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
@@ -156,11 +152,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
 };
 
-void __init trimslice_pinmux_init(void)
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = trimslice_pinmux,
+        .pg_count = ARRAY_SIZE(trimslice_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
+void trimslice_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-        tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux));
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index c242314a1db..cd52820a3e3 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
         .atag_offset    = 0x100,
         .fixup          = tegra_trimslice_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1d14df7eb7d..75d1543d77c 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -25,10 +25,11 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra_init_early(void);
+void __init tegra20_init_early(void);
+void __init tegra30_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
-void __init tegra_init_clock(void);
+void __init tegra_dt_init_irq(void);
 int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 extern struct sys_timer tegra_timer;
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f8d41ffc0ca..8337068a4ab 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
 
 void tegra_periph_reset_deassert(struct clk *c)
 {
-        tegra2_periph_reset_deassert(c);
+        BUG_ON(!c->ops->reset);
+        c->ops->reset(c, false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
-        tegra2_periph_reset_assert(c);
+        BUG_ON(!c->ops->reset);
+        c->ops->reset(c, true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
-void __init tegra_init_clock(void)
-{
-        tegra2_init_clocks();
-}
-
-/*
- * The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB.
- */
-void tegra_sdmmc_tap_delay(struct clk *c, int delay)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-        tegra2_sdmmc_tap_delay(c, delay);
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
 #ifdef CONFIG_DEBUG_FS
 
 static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 688316abc64..5c44106616c 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -146,15 +146,11 @@ struct tegra_clk_init_table {
 };
 
 void tegra2_init_clocks(void);
-void tegra2_periph_reset_deassert(struct clk *c);
-void tegra2_periph_reset_assert(struct clk *c);
 void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-unsigned long clk_measure_input_freq(void);
 int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 unsigned long clk_get_rate_locked(struct clk *c);
 int clk_set_rate_locked(struct clk *c, unsigned long rate);
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 20f396d740f..a2eb90169ae 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-tegra/board-harmony.c
+ * arch/arm/mach-tegra/common.c
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -21,8 +21,10 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/of_irq.h>
 
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/system.h>
@@ -31,18 +33,31 @@
 #include "clock.h"
 #include "fuse.h"
 
+#ifdef CONFIG_OF
+static const struct of_device_id tegra_dt_irq_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+        { }
+};
+
+void __init tegra_dt_init_irq(void)
+{
+        tegra_init_irq();
+        of_irq_init(tegra_dt_irq_match);
+}
+#endif
+
 void tegra_assert_system_reset(char mode, const char *cmd)
 {
-        void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+        void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
         u32 reg;
 
-        /* use *_related to avoid spinlock since caches are off */
         reg = readl_relaxed(reset);
-        reg |= 0x04;
+        reg |= 0x10;
         writel_relaxed(reg, reset);
 }
 
-static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "clk_m",      NULL,           0,              true },
         { "pll_p",      "clk_m",        216000000,      true },
@@ -58,24 +73,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         { "cpu",        NULL,           0,              true },
         { NULL,         NULL,           0,              0},
 };
+#endif
 
-static void __init tegra_init_cache(void)
+static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 {
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+        u32 aux_ctrl, cache_type;
+
+        writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
 
-        writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
-        writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
+        cache_type = readl(p + L2X0_CACHE_TYPE);
+        aux_ctrl = (cache_type & 0x700) << (17-8);
+        aux_ctrl |= 0x6C000001;
 
-        l2x0_init(p, 0x6C080001, 0x8200c3fe);
+        l2x0_init(p, aux_ctrl, 0x8200c3fe);
 #endif
 
 }
 
-void __init tegra_init_early(void)
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra20_init_early(void)
 {
         tegra_init_fuse();
-        tegra_init_clock();
-        tegra_clk_init_from_table(common_clk_init_table);
-        tegra_init_cache();
+        tegra2_init_clocks();
+        tegra_clk_init_from_table(tegra20_clk_init_table);
+        tegra_init_cache(0x331, 0x441);
+}
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void __init tegra30_init_early(void)
+{
+        tegra_init_cache(0x441, 0x551);
 }
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index c8baf8f80d2..fc3ecb66de0 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
 unsigned long clk_get_rate_all_locked(struct clk *c);
-void tegra_sdmmc_tap_delay(struct clk *c, int delay);
+void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index ac11262149c..e577cfe27e7 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -18,21 +18,3 @@
 
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
-
-#if !defined(CONFIG_ARM_GIC)
-        /* legacy interrupt controller for AP16 */
-
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        @ EVP base at 0xf010f000
-        mov \base, #0xf0000000
-        orr \base, #0x00100000
-        orr \base, #0x0000f000
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr \irqnr, [\base, #0x20]      @ EVT_IRQ_STS
-        cmp \irqnr, #0x80
-        .endm
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 73265af4dda..a2146cd6867 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,7 +25,6 @@
 
 #define IRQ_LOCALTIMER                  29
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /* Primary Interrupt Controller */
 #define INT_PRI_BASE                    (INT_GIC_BASE + 32)
 #define INT_TMR1                        (INT_PRI_BASE + 0)
@@ -178,6 +177,5 @@
 #define NR_BOARD_IRQS                   32
 
 #define NR_IRQS                         (INT_BOARD_BASE + NR_BOARD_IRQS)
-#endif
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 4f3572a1c68..20bb0545f99 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -53,6 +53,7 @@ struct tegra_kbc_platform_data {
         struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
         const struct matrix_keymap_data *keymap_data;
 
+        u32 wakeup_key;
         bool wakeup;
         bool use_fn_map;
         bool use_ghost_filter;
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
index 4c262634726..6a40c1dbab1 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -14,8 +14,8 @@
  *
  */
 
-#ifndef __MACH_TEGRA_PINMUX_T2_H
-#define __MACH_TEGRA_PINMUX_T2_H
+#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
+#define __MACH_TEGRA_PINMUX_TEGRA20_H
 
 enum tegra_pingroup {
         TEGRA_PINGROUP_ATA = 0,
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
new file mode 100644
index 00000000000..c1aee3eb2df
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
@@ -0,0 +1,320 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Nvidia, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
+#define __MACH_TEGRA_PINMUX_TEGRA30_H
+
+enum tegra_pingroup {
+        TEGRA_PINGROUP_ULPI_DATA0 = 0,
+        TEGRA_PINGROUP_ULPI_DATA1,
+        TEGRA_PINGROUP_ULPI_DATA2,
+        TEGRA_PINGROUP_ULPI_DATA3,
+        TEGRA_PINGROUP_ULPI_DATA4,
+        TEGRA_PINGROUP_ULPI_DATA5,
+        TEGRA_PINGROUP_ULPI_DATA6,
+        TEGRA_PINGROUP_ULPI_DATA7,
+        TEGRA_PINGROUP_ULPI_CLK,
+        TEGRA_PINGROUP_ULPI_DIR,
+        TEGRA_PINGROUP_ULPI_NXT,
+        TEGRA_PINGROUP_ULPI_STP,
+        TEGRA_PINGROUP_DAP3_FS,
+        TEGRA_PINGROUP_DAP3_DIN,
+        TEGRA_PINGROUP_DAP3_DOUT,
+        TEGRA_PINGROUP_DAP3_SCLK,
+        TEGRA_PINGROUP_GPIO_PV0,
+        TEGRA_PINGROUP_GPIO_PV1,
+        TEGRA_PINGROUP_SDMMC1_CLK,
+        TEGRA_PINGROUP_SDMMC1_CMD,
+        TEGRA_PINGROUP_SDMMC1_DAT3,
+        TEGRA_PINGROUP_SDMMC1_DAT2,
+        TEGRA_PINGROUP_SDMMC1_DAT1,
+        TEGRA_PINGROUP_SDMMC1_DAT0,
+        TEGRA_PINGROUP_GPIO_PV2,
+        TEGRA_PINGROUP_GPIO_PV3,
+        TEGRA_PINGROUP_CLK2_OUT,
+        TEGRA_PINGROUP_CLK2_REQ,
+        TEGRA_PINGROUP_LCD_PWR1,
+        TEGRA_PINGROUP_LCD_PWR2,
+        TEGRA_PINGROUP_LCD_SDIN,
+        TEGRA_PINGROUP_LCD_SDOUT,
+        TEGRA_PINGROUP_LCD_WR_N,
+        TEGRA_PINGROUP_LCD_CS0_N,
+        TEGRA_PINGROUP_LCD_DC0,
+        TEGRA_PINGROUP_LCD_SCK,
+        TEGRA_PINGROUP_LCD_PWR0,
+        TEGRA_PINGROUP_LCD_PCLK,
+        TEGRA_PINGROUP_LCD_DE,
+        TEGRA_PINGROUP_LCD_HSYNC,
+        TEGRA_PINGROUP_LCD_VSYNC,
+        TEGRA_PINGROUP_LCD_D0,
+        TEGRA_PINGROUP_LCD_D1,
+        TEGRA_PINGROUP_LCD_D2,
+        TEGRA_PINGROUP_LCD_D3,
+        TEGRA_PINGROUP_LCD_D4,
+        TEGRA_PINGROUP_LCD_D5,
+        TEGRA_PINGROUP_LCD_D6,
+        TEGRA_PINGROUP_LCD_D7,
+        TEGRA_PINGROUP_LCD_D8,
+        TEGRA_PINGROUP_LCD_D9,
+        TEGRA_PINGROUP_LCD_D10,
+        TEGRA_PINGROUP_LCD_D11,
+        TEGRA_PINGROUP_LCD_D12,
+        TEGRA_PINGROUP_LCD_D13,
+        TEGRA_PINGROUP_LCD_D14,
+        TEGRA_PINGROUP_LCD_D15,
+        TEGRA_PINGROUP_LCD_D16,
+        TEGRA_PINGROUP_LCD_D17,
+        TEGRA_PINGROUP_LCD_D18,
+        TEGRA_PINGROUP_LCD_D19,
+        TEGRA_PINGROUP_LCD_D20,
+        TEGRA_PINGROUP_LCD_D21,
+        TEGRA_PINGROUP_LCD_D22,
+        TEGRA_PINGROUP_LCD_D23,
+        TEGRA_PINGROUP_LCD_CS1_N,
+        TEGRA_PINGROUP_LCD_M1,
+        TEGRA_PINGROUP_LCD_DC1,
+        TEGRA_PINGROUP_HDMI_INT,
+        TEGRA_PINGROUP_DDC_SCL,
+        TEGRA_PINGROUP_DDC_SDA,
+        TEGRA_PINGROUP_CRT_HSYNC,
+        TEGRA_PINGROUP_CRT_VSYNC,
+        TEGRA_PINGROUP_VI_D0,
+        TEGRA_PINGROUP_VI_D1,
+        TEGRA_PINGROUP_VI_D2,
+        TEGRA_PINGROUP_VI_D3,
+        TEGRA_PINGROUP_VI_D4,
+        TEGRA_PINGROUP_VI_D5,
+        TEGRA_PINGROUP_VI_D6,
+        TEGRA_PINGROUP_VI_D7,
+        TEGRA_PINGROUP_VI_D8,
+        TEGRA_PINGROUP_VI_D9,
+        TEGRA_PINGROUP_VI_D10,
+        TEGRA_PINGROUP_VI_D11,
+        TEGRA_PINGROUP_VI_PCLK,
+        TEGRA_PINGROUP_VI_MCLK,
+        TEGRA_PINGROUP_VI_VSYNC,
+        TEGRA_PINGROUP_VI_HSYNC,
+        TEGRA_PINGROUP_UART2_RXD,
+        TEGRA_PINGROUP_UART2_TXD,
+        TEGRA_PINGROUP_UART2_RTS_N,
+        TEGRA_PINGROUP_UART2_CTS_N,
+        TEGRA_PINGROUP_UART3_TXD,
+        TEGRA_PINGROUP_UART3_RXD,
+        TEGRA_PINGROUP_UART3_CTS_N,
+        TEGRA_PINGROUP_UART3_RTS_N,
+        TEGRA_PINGROUP_GPIO_PU0,
+        TEGRA_PINGROUP_GPIO_PU1,
+        TEGRA_PINGROUP_GPIO_PU2,
+        TEGRA_PINGROUP_GPIO_PU3,
+        TEGRA_PINGROUP_GPIO_PU4,
+        TEGRA_PINGROUP_GPIO_PU5,
+        TEGRA_PINGROUP_GPIO_PU6,
+        TEGRA_PINGROUP_GEN1_I2C_SDA,
+        TEGRA_PINGROUP_GEN1_I2C_SCL,
+        TEGRA_PINGROUP_DAP4_FS,
+        TEGRA_PINGROUP_DAP4_DIN,
+        TEGRA_PINGROUP_DAP4_DOUT,
+        TEGRA_PINGROUP_DAP4_SCLK,
+        TEGRA_PINGROUP_CLK3_OUT,
+        TEGRA_PINGROUP_CLK3_REQ,
+        TEGRA_PINGROUP_GMI_WP_N,
+        TEGRA_PINGROUP_GMI_IORDY,
+        TEGRA_PINGROUP_GMI_WAIT,
+        TEGRA_PINGROUP_GMI_ADV_N,
+        TEGRA_PINGROUP_GMI_CLK,
+        TEGRA_PINGROUP_GMI_CS0_N,
+        TEGRA_PINGROUP_GMI_CS1_N,
+        TEGRA_PINGROUP_GMI_CS2_N,
+        TEGRA_PINGROUP_GMI_CS3_N,
+        TEGRA_PINGROUP_GMI_CS4_N,
+        TEGRA_PINGROUP_GMI_CS6_N,
+        TEGRA_PINGROUP_GMI_CS7_N,
+        TEGRA_PINGROUP_GMI_AD0,
+        TEGRA_PINGROUP_GMI_AD1,
+        TEGRA_PINGROUP_GMI_AD2,
+        TEGRA_PINGROUP_GMI_AD3,
+        TEGRA_PINGROUP_GMI_AD4,
+        TEGRA_PINGROUP_GMI_AD5,
+        TEGRA_PINGROUP_GMI_AD6,
+        TEGRA_PINGROUP_GMI_AD7,
+        TEGRA_PINGROUP_GMI_AD8,
+        TEGRA_PINGROUP_GMI_AD9,
+        TEGRA_PINGROUP_GMI_AD10,
+        TEGRA_PINGROUP_GMI_AD11,
+        TEGRA_PINGROUP_GMI_AD12,
+        TEGRA_PINGROUP_GMI_AD13,
+        TEGRA_PINGROUP_GMI_AD14,
+        TEGRA_PINGROUP_GMI_AD15,
+        TEGRA_PINGROUP_GMI_A16,
+        TEGRA_PINGROUP_GMI_A17,
+        TEGRA_PINGROUP_GMI_A18,
+        TEGRA_PINGROUP_GMI_A19,
+        TEGRA_PINGROUP_GMI_WR_N,
+        TEGRA_PINGROUP_GMI_OE_N,
+        TEGRA_PINGROUP_GMI_DQS,
+        TEGRA_PINGROUP_GMI_RST_N,
+        TEGRA_PINGROUP_GEN2_I2C_SCL,
+        TEGRA_PINGROUP_GEN2_I2C_SDA,
+        TEGRA_PINGROUP_SDMMC4_CLK,
+        TEGRA_PINGROUP_SDMMC4_CMD,
+        TEGRA_PINGROUP_SDMMC4_DAT0,
+        TEGRA_PINGROUP_SDMMC4_DAT1,
+        TEGRA_PINGROUP_SDMMC4_DAT2,
+        TEGRA_PINGROUP_SDMMC4_DAT3,
+        TEGRA_PINGROUP_SDMMC4_DAT4,
+        TEGRA_PINGROUP_SDMMC4_DAT5,
+        TEGRA_PINGROUP_SDMMC4_DAT6,
+        TEGRA_PINGROUP_SDMMC4_DAT7,
+        TEGRA_PINGROUP_SDMMC4_RST_N,
+        TEGRA_PINGROUP_CAM_MCLK,
+        TEGRA_PINGROUP_GPIO_PCC1,
+        TEGRA_PINGROUP_GPIO_PBB0,
+        TEGRA_PINGROUP_CAM_I2C_SCL,
+        TEGRA_PINGROUP_CAM_I2C_SDA,
+        TEGRA_PINGROUP_GPIO_PBB3,
+        TEGRA_PINGROUP_GPIO_PBB4,
+        TEGRA_PINGROUP_GPIO_PBB5,
+        TEGRA_PINGROUP_GPIO_PBB6,
+        TEGRA_PINGROUP_GPIO_PBB7,
+        TEGRA_PINGROUP_GPIO_PCC2,
+        TEGRA_PINGROUP_JTAG_RTCK,
+        TEGRA_PINGROUP_PWR_I2C_SCL,
+        TEGRA_PINGROUP_PWR_I2C_SDA,
+        TEGRA_PINGROUP_KB_ROW0,
+        TEGRA_PINGROUP_KB_ROW1,
+        TEGRA_PINGROUP_KB_ROW2,
+        TEGRA_PINGROUP_KB_ROW3,
+        TEGRA_PINGROUP_KB_ROW4,
+        TEGRA_PINGROUP_KB_ROW5,
+        TEGRA_PINGROUP_KB_ROW6,
+        TEGRA_PINGROUP_KB_ROW7,
+        TEGRA_PINGROUP_KB_ROW8,
+        TEGRA_PINGROUP_KB_ROW9,
+        TEGRA_PINGROUP_KB_ROW10,
+        TEGRA_PINGROUP_KB_ROW11,
+        TEGRA_PINGROUP_KB_ROW12,
+        TEGRA_PINGROUP_KB_ROW13,
+        TEGRA_PINGROUP_KB_ROW14,
+        TEGRA_PINGROUP_KB_ROW15,
+        TEGRA_PINGROUP_KB_COL0,
+        TEGRA_PINGROUP_KB_COL1,
+        TEGRA_PINGROUP_KB_COL2,
+        TEGRA_PINGROUP_KB_COL3,
+        TEGRA_PINGROUP_KB_COL4,
+        TEGRA_PINGROUP_KB_COL5,
+        TEGRA_PINGROUP_KB_COL6,
+        TEGRA_PINGROUP_KB_COL7,
+        TEGRA_PINGROUP_CLK_32K_OUT,
+        TEGRA_PINGROUP_SYS_CLK_REQ,
+        TEGRA_PINGROUP_CORE_PWR_REQ,
+        TEGRA_PINGROUP_CPU_PWR_REQ,
+        TEGRA_PINGROUP_PWR_INT_N,
+        TEGRA_PINGROUP_CLK_32K_IN,
+        TEGRA_PINGROUP_OWR,
+        TEGRA_PINGROUP_DAP1_FS,
+        TEGRA_PINGROUP_DAP1_DIN,
+        TEGRA_PINGROUP_DAP1_DOUT,
+        TEGRA_PINGROUP_DAP1_SCLK,
+        TEGRA_PINGROUP_CLK1_REQ,
+        TEGRA_PINGROUP_CLK1_OUT,
+        TEGRA_PINGROUP_SPDIF_IN,
+        TEGRA_PINGROUP_SPDIF_OUT,
+        TEGRA_PINGROUP_DAP2_FS,
+        TEGRA_PINGROUP_DAP2_DIN,
+        TEGRA_PINGROUP_DAP2_DOUT,
+        TEGRA_PINGROUP_DAP2_SCLK,
+        TEGRA_PINGROUP_SPI2_MOSI,
+        TEGRA_PINGROUP_SPI2_MISO,
+        TEGRA_PINGROUP_SPI2_CS0_N,
+        TEGRA_PINGROUP_SPI2_SCK,
+        TEGRA_PINGROUP_SPI1_MOSI,
+        TEGRA_PINGROUP_SPI1_SCK,
+        TEGRA_PINGROUP_SPI1_CS0_N,
+        TEGRA_PINGROUP_SPI1_MISO,
+        TEGRA_PINGROUP_SPI2_CS1_N,
+        TEGRA_PINGROUP_SPI2_CS2_N,
+        TEGRA_PINGROUP_SDMMC3_CLK,
+        TEGRA_PINGROUP_SDMMC3_CMD,
+        TEGRA_PINGROUP_SDMMC3_DAT0,
+        TEGRA_PINGROUP_SDMMC3_DAT1,
+        TEGRA_PINGROUP_SDMMC3_DAT2,
+        TEGRA_PINGROUP_SDMMC3_DAT3,
+        TEGRA_PINGROUP_SDMMC3_DAT4,
+        TEGRA_PINGROUP_SDMMC3_DAT5,
+        TEGRA_PINGROUP_SDMMC3_DAT6,
+        TEGRA_PINGROUP_SDMMC3_DAT7,
+        TEGRA_PINGROUP_PEX_L0_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L0_RST_N,
+        TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_WAKE_N,
+        TEGRA_PINGROUP_PEX_L1_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L1_RST_N,
+        TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_L2_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L2_RST_N,
+        TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
+        TEGRA_PINGROUP_HDMI_CEC,
+        TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+        TEGRA_DRIVE_PINGROUP_AO1 = 0,
+        TEGRA_DRIVE_PINGROUP_AO2,
+        TEGRA_DRIVE_PINGROUP_AT1,
+        TEGRA_DRIVE_PINGROUP_AT2,
+        TEGRA_DRIVE_PINGROUP_AT3,
+        TEGRA_DRIVE_PINGROUP_AT4,
+        TEGRA_DRIVE_PINGROUP_AT5,
+        TEGRA_DRIVE_PINGROUP_CDEV1,
+        TEGRA_DRIVE_PINGROUP_CDEV2,
+        TEGRA_DRIVE_PINGROUP_CSUS,
+        TEGRA_DRIVE_PINGROUP_DAP1,
+        TEGRA_DRIVE_PINGROUP_DAP2,
+        TEGRA_DRIVE_PINGROUP_DAP3,
+        TEGRA_DRIVE_PINGROUP_DAP4,
+        TEGRA_DRIVE_PINGROUP_DBG,
+        TEGRA_DRIVE_PINGROUP_LCD1,
+        TEGRA_DRIVE_PINGROUP_LCD2,
+        TEGRA_DRIVE_PINGROUP_SDIO2,
+        TEGRA_DRIVE_PINGROUP_SDIO3,
+        TEGRA_DRIVE_PINGROUP_SPI,
+        TEGRA_DRIVE_PINGROUP_UAA,
+        TEGRA_DRIVE_PINGROUP_UAB,
+        TEGRA_DRIVE_PINGROUP_UART2,
+        TEGRA_DRIVE_PINGROUP_UART3,
+        TEGRA_DRIVE_PINGROUP_VI1,
+        TEGRA_DRIVE_PINGROUP_SDIO1,
+        TEGRA_DRIVE_PINGROUP_CRT,
+        TEGRA_DRIVE_PINGROUP_DDC,
+        TEGRA_DRIVE_PINGROUP_GMA,
+        TEGRA_DRIVE_PINGROUP_GMB,
+        TEGRA_DRIVE_PINGROUP_GMC,
+        TEGRA_DRIVE_PINGROUP_GMD,
+        TEGRA_DRIVE_PINGROUP_GME,
+        TEGRA_DRIVE_PINGROUP_GMF,
+        TEGRA_DRIVE_PINGROUP_GMG,
+        TEGRA_DRIVE_PINGROUP_GMH,
+        TEGRA_DRIVE_PINGROUP_OWR,
+        TEGRA_DRIVE_PINGROUP_UAD,
+        TEGRA_DRIVE_PINGROUP_GPV,
+        TEGRA_DRIVE_PINGROUP_DEV3,
+        TEGRA_DRIVE_PINGROUP_CEC,
+        TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index bb7dfdb6120..055f1792c8f 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -2,6 +2,7 @@
  * linux/arch/arm/mach-tegra/include/mach/pinmux.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Nvidia, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,18 +18,13 @@
 #ifndef __MACH_TEGRA_PINMUX_H
 #define __MACH_TEGRA_PINMUX_H
 
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
-#include "pinmux-t2.h"
-#else
-#error "Undefined Tegra architecture"
-#endif
-
 enum tegra_mux_func {
         TEGRA_MUX_RSVD = 0x8000,
         TEGRA_MUX_RSVD1 = 0x8000,
         TEGRA_MUX_RSVD2 = 0x8001,
         TEGRA_MUX_RSVD3 = 0x8002,
         TEGRA_MUX_RSVD4 = 0x8003,
+        TEGRA_MUX_INVALID = 0x4000,
         TEGRA_MUX_NONE = -1,
         TEGRA_MUX_AHB_CLK,
         TEGRA_MUX_APB_CLK,
@@ -90,6 +86,49 @@ enum tegra_mux_func {
         TEGRA_MUX_VI,
         TEGRA_MUX_VI_SENSOR_CLK,
         TEGRA_MUX_XIO,
+        TEGRA_MUX_BLINK,
+        TEGRA_MUX_CEC,
+        TEGRA_MUX_CLK12,
+        TEGRA_MUX_DAP,
+        TEGRA_MUX_DAPSDMMC2,
+        TEGRA_MUX_DDR,
+        TEGRA_MUX_DEV3,
+        TEGRA_MUX_DTV,
+        TEGRA_MUX_VI_ALT1,
+        TEGRA_MUX_VI_ALT2,
+        TEGRA_MUX_VI_ALT3,
+        TEGRA_MUX_EMC_DLL,
+        TEGRA_MUX_EXTPERIPH1,
+        TEGRA_MUX_EXTPERIPH2,
+        TEGRA_MUX_EXTPERIPH3,
+        TEGRA_MUX_GMI_ALT,
+        TEGRA_MUX_HDA,
+        TEGRA_MUX_HSI,
+        TEGRA_MUX_I2C4,
+        TEGRA_MUX_I2C5,
+        TEGRA_MUX_I2CPWR,
+        TEGRA_MUX_I2S0,
+        TEGRA_MUX_I2S1,
+        TEGRA_MUX_I2S2,
+        TEGRA_MUX_I2S3,
+        TEGRA_MUX_I2S4,
+        TEGRA_MUX_NAND_ALT,
+        TEGRA_MUX_POPSDIO4,
+        TEGRA_MUX_POPSDMMC4,
+        TEGRA_MUX_PWM0,
+        TEGRA_MUX_PWM1,
+        TEGRA_MUX_PWM2,
+        TEGRA_MUX_PWM3,
+        TEGRA_MUX_SATA,
+        TEGRA_MUX_SPI5,
+        TEGRA_MUX_SPI6,
+        TEGRA_MUX_SYSCLK,
+        TEGRA_MUX_VGP1,
+        TEGRA_MUX_VGP2,
+        TEGRA_MUX_VGP3,
+        TEGRA_MUX_VGP4,
+        TEGRA_MUX_VGP5,
+        TEGRA_MUX_VGP6,
         TEGRA_MUX_SAFE,
         TEGRA_MAX_MUX,
 };
@@ -105,6 +144,11 @@ enum tegra_tristate {
         TEGRA_TRI_TRISTATE = 1,
 };
 
+enum tegra_pin_io {
+        TEGRA_PIN_OUTPUT = 0,
+        TEGRA_PIN_INPUT = 1,
+};
+
 enum tegra_vddio {
         TEGRA_VDDIO_BB = 0,
         TEGRA_VDDIO_LCD,
@@ -115,10 +159,16 @@ enum tegra_vddio {
         TEGRA_VDDIO_SYS,
         TEGRA_VDDIO_AUDIO,
         TEGRA_VDDIO_SD,
+        TEGRA_VDDIO_CAM,
+        TEGRA_VDDIO_GMI,
+        TEGRA_VDDIO_PEXCTL,
+        TEGRA_VDDIO_SDMMC1,
+        TEGRA_VDDIO_SDMMC3,
+        TEGRA_VDDIO_SDMMC4,
 };
 
 struct tegra_pingroup_config {
-        enum tegra_pingroup     pingroup;
+        int pingroup;
         enum tegra_mux_func     func;
         enum tegra_pullupdown   pupd;
         enum tegra_tristate     tristate;
@@ -187,7 +237,7 @@ enum tegra_schmitt {
 };
 
 struct tegra_drive_pingroup_config {
-        enum tegra_drive_pingroup pingroup;
+        int pingroup;
         enum tegra_hsm hsm;
         enum tegra_schmitt schmitt;
         enum tegra_drive drive;
@@ -208,6 +258,7 @@ struct tegra_pingroup_desc {
         int funcs[4];
         int func_safe;
         int vddio;
+        enum tegra_pin_io io_default;
         s16 tri_bank;   /* Register bank the tri_reg exists within */
         s16 mux_bank;   /* Register bank the mux_reg exists within */
         s16 pupd_bank;  /* Register bank the pupd_reg exists within */
@@ -217,15 +268,23 @@ struct tegra_pingroup_desc {
         s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
         s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
         s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
+        s8 lock_bit;    /* offset of the LOCK bit into mux register bit */
+        s8 od_bit;      /* offset of the OD bit into mux register bit */
+        s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
 };
 
-extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
-extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
+typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
+        int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+        int *pgdrive_max);
 
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
-        enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
-        enum tegra_pullupdown pupd);
+void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
+
+void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
+
+int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
+int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
 
 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
         int len);
@@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
         int len, enum tegra_pullupdown pupd);
 #endif
-
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4956c3cea73..4e1afcd54fa 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -21,6 +21,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 
 #include <asm/hardware/gic.h>
 
@@ -28,10 +29,6 @@
 
 #include "board.h"
 
-#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
 #define ICTLR_CPU_IEP_VFIQ      0x08
 #define ICTLR_CPU_IEP_FIR       0x14
 #define ICTLR_CPU_IEP_FIR_SET   0x18
@@ -129,6 +126,11 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
 
-        gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
-                 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+        /*
+         * Check if there is a devicetree present, since the GIC will be
+         * initialized elsewhere under DT.
+         */
+        if (!of_have_populated_dt())
+                gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+                        IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 }
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 97ef3e55dfd..ec63c6b2b6b 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -37,7 +37,6 @@
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
 
-#include <mach/pinmux.h>
 #include <mach/iomap.h>
 #include <mach/clk.h>
 #include <mach/powergate.h>
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
index a0dc2bc28ed..734add1280b 100644
--- a/arch/arm/mach-tegra/pinmux-t2-tables.c
+++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
@@ -1,7 +1,7 @@
 /*
- * linux/arch/arm/mach-tegra/pinmux-t2-tables.c
+ * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
  *
- * Common pinmux configurations for Tegra 2 SoCs
+ * Common pinmux configurations for Tegra20 SoCs
  *
  * Copyright (C) 2010 NVIDIA Corporation
  *
@@ -29,6 +29,7 @@
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 #include <mach/suspend.h>
 
 #define TRISTATE_REG_A          0x14
@@ -43,7 +44,7 @@
                 .reg = ((r) - PINGROUP_REG_A)                   \
         }
 
-const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
         DRIVE_PINGROUP(AO1,             0x868),
         DRIVE_PINGROUP(AO2,             0x86c),
         DRIVE_PINGROUP(AT1,             0x870),
@@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
                 .pupd_bank = 2,                         \
                 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
                 .pupd_bit = pupd_b,                             \
+                .lock_bit = -1,                                 \
+                .od_bit = -1,                                   \
+                .ioreset_bit = -1,                              \
+                .io_default = -1,                               \
         }
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
         PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
         PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
         PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
@@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
         PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
         PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
 };
+
+void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
+                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+                int *pgdrive_max)
+{
+        *pg = tegra_soc_pingroups;
+        *pg_max = TEGRA_MAX_PINGROUP;
+        *pgdrive = tegra_soc_drive_pingroups;
+        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+}
+
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
new file mode 100644
index 00000000000..14fc0e4c1c4
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
@@ -0,0 +1,376 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+ *
+ * Common pinmux configurations for Tegra30 SoCs
+ *
+ * Copyright (C) 2010,2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-tegra30.h>
+#include <mach/suspend.h>
+
+#define PINGROUP_REG_A  0x868
+#define MUXCTL_REG_A    0x3000
+
+#define DRIVE_PINGROUP(pg_name, r)              \
+        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {  \
+                .name = #pg_name,               \
+                .reg_bank = 0,                  \
+                .reg = ((r) - PINGROUP_REG_A)   \
+        }
+
+static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+        DRIVE_PINGROUP(AO1,             0x868),
+        DRIVE_PINGROUP(AO2,             0x86c),
+        DRIVE_PINGROUP(AT1,             0x870),
+        DRIVE_PINGROUP(AT2,             0x874),
+        DRIVE_PINGROUP(AT3,             0x878),
+        DRIVE_PINGROUP(AT4,             0x87c),
+        DRIVE_PINGROUP(AT5,             0x880),
+        DRIVE_PINGROUP(CDEV1,           0x884),
+        DRIVE_PINGROUP(CDEV2,           0x888),
+        DRIVE_PINGROUP(CSUS,            0x88c),
+        DRIVE_PINGROUP(DAP1,            0x890),
+        DRIVE_PINGROUP(DAP2,            0x894),
+        DRIVE_PINGROUP(DAP3,            0x898),
+        DRIVE_PINGROUP(DAP4,            0x89c),
+        DRIVE_PINGROUP(DBG,             0x8a0),
+        DRIVE_PINGROUP(LCD1,            0x8a4),
+        DRIVE_PINGROUP(LCD2,            0x8a8),
+        DRIVE_PINGROUP(SDIO2,           0x8ac),
+        DRIVE_PINGROUP(SDIO3,           0x8b0),
+        DRIVE_PINGROUP(SPI,             0x8b4),
+        DRIVE_PINGROUP(UAA,             0x8b8),
+        DRIVE_PINGROUP(UAB,             0x8bc),
+        DRIVE_PINGROUP(UART2,           0x8c0),
+        DRIVE_PINGROUP(UART3,           0x8c4),
+        DRIVE_PINGROUP(VI1,             0x8c8),
+        DRIVE_PINGROUP(SDIO1,           0x8ec),
+        DRIVE_PINGROUP(CRT,             0x8f8),
+        DRIVE_PINGROUP(DDC,             0x8fc),
+        DRIVE_PINGROUP(GMA,             0x900),
+        DRIVE_PINGROUP(GMB,             0x904),
+        DRIVE_PINGROUP(GMC,             0x908),
+        DRIVE_PINGROUP(GMD,             0x90c),
+        DRIVE_PINGROUP(GME,             0x910),
+        DRIVE_PINGROUP(GMF,             0x914),
+        DRIVE_PINGROUP(GMG,             0x918),
+        DRIVE_PINGROUP(GMH,             0x91c),
+        DRIVE_PINGROUP(OWR,             0x920),
+        DRIVE_PINGROUP(UAD,             0x924),
+        DRIVE_PINGROUP(GPV,             0x928),
+        DRIVE_PINGROUP(DEV3,            0x92c),
+        DRIVE_PINGROUP(CEC,             0x938),
+};
+
+#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg)    \
+        [TEGRA_PINGROUP_ ## pg_name] = {                        \
+                .name = #pg_name,                               \
+                .vddio = TEGRA_VDDIO_ ## vdd,                   \
+                .funcs = {                                      \
+                        TEGRA_MUX_ ## f0,                       \
+                        TEGRA_MUX_ ## f1,                       \
+                        TEGRA_MUX_ ## f2,                       \
+                        TEGRA_MUX_ ## f3,                       \
+                },                                              \
+                .func_safe = TEGRA_MUX_ ## fs,                  \
+                .tri_bank = 1,                                  \
+                .tri_reg = ((reg) - MUXCTL_REG_A),              \
+                .tri_bit = 4,                                   \
+                .mux_bank = 1,                                  \
+                .mux_reg = ((reg) - MUXCTL_REG_A),              \
+                .mux_bit = 0,                                   \
+                .pupd_bank = 1,                                 \
+                .pupd_reg = ((reg) - MUXCTL_REG_A),             \
+                .pupd_bit = 2,                                  \
+                .io_default = TEGRA_PIN_ ## iod,                \
+                .od_bit = 6,                                    \
+                .lock_bit = 7,                                  \
+                .ioreset_bit = 8,                               \
+        }
+
+static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+        /*       NAME             VDD       f0          f1          f2          f3          fSafe       io      reg */
+        PINGROUP(ULPI_DATA0,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),
+        PINGROUP(ULPI_DATA1,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),
+        PINGROUP(ULPI_DATA2,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3008),
+        PINGROUP(ULPI_DATA3,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x300c),
+        PINGROUP(ULPI_DATA4,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3010),
+        PINGROUP(ULPI_DATA5,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3014),
+        PINGROUP(ULPI_DATA6,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3018),
+        PINGROUP(ULPI_DATA7,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x301c),
+        PINGROUP(ULPI_CLK,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3020),
+        PINGROUP(ULPI_DIR,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3024),
+        PINGROUP(ULPI_NXT,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3028),
+        PINGROUP(ULPI_STP,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x302c),
+        PINGROUP(DAP3_FS,         BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3030),
+        PINGROUP(DAP3_DIN,        BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3034),
+        PINGROUP(DAP3_DOUT,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3038),
+        PINGROUP(DAP3_SCLK,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x303c),
+        PINGROUP(GPIO_PV0,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3040),
+        PINGROUP(GPIO_PV1,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3044),
+        PINGROUP(SDMMC1_CLK,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x3048),
+        PINGROUP(SDMMC1_CMD,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x304c),
+        PINGROUP(SDMMC1_DAT3,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3050),
+        PINGROUP(SDMMC1_DAT2,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3054),
+        PINGROUP(SDMMC1_DAT1,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3058),
+        PINGROUP(SDMMC1_DAT0,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x305c),
+        PINGROUP(GPIO_PV2,        SDMMC1,   OWR,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3060),
+        PINGROUP(GPIO_PV3,        SDMMC1,   INVALID,    RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3064),
+        PINGROUP(CLK2_OUT,        SDMMC1,   EXTPERIPH2, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3068),
+        PINGROUP(CLK2_REQ,        SDMMC1,   DAP,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x306c),
+        PINGROUP(LCD_PWR1,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3070),
+        PINGROUP(LCD_PWR2,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3074),
+        PINGROUP(LCD_SDIN,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3078),
+        PINGROUP(LCD_SDOUT,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x307c),
+        PINGROUP(LCD_WR_N,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3080),
+        PINGROUP(LCD_CS0_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3084),
+        PINGROUP(LCD_DC0,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3088),
+        PINGROUP(LCD_SCK,         LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x308c),
+        PINGROUP(LCD_PWR0,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3090),
+        PINGROUP(LCD_PCLK,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3094),
+        PINGROUP(LCD_DE,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3098),
+        PINGROUP(LCD_HSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x309c),
+        PINGROUP(LCD_VSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a0),
+        PINGROUP(LCD_D0,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a4),
+        PINGROUP(LCD_D1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a8),
+        PINGROUP(LCD_D2,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ac),
+        PINGROUP(LCD_D3,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b0),
+        PINGROUP(LCD_D4,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b4),
+        PINGROUP(LCD_D5,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b8),
+        PINGROUP(LCD_D6,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30bc),
+        PINGROUP(LCD_D7,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c0),
+        PINGROUP(LCD_D8,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c4),
+        PINGROUP(LCD_D9,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c8),
+        PINGROUP(LCD_D10,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30cc),
+        PINGROUP(LCD_D11,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d0),
+        PINGROUP(LCD_D12,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d4),
+        PINGROUP(LCD_D13,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d8),
+        PINGROUP(LCD_D14,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30dc),
+        PINGROUP(LCD_D15,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e0),
+        PINGROUP(LCD_D16,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e4),
+        PINGROUP(LCD_D17,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e8),
+        PINGROUP(LCD_D18,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ec),
+        PINGROUP(LCD_D19,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f0),
+        PINGROUP(LCD_D20,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f4),
+        PINGROUP(LCD_D21,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f8),
+        PINGROUP(LCD_D22,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30fc),
+        PINGROUP(LCD_D23,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3100),
+        PINGROUP(LCD_CS1_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD2,      RSVD,       OUTPUT, 0x3104),
+        PINGROUP(LCD_M1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3108),
+        PINGROUP(LCD_DC1,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x310c),
+        PINGROUP(HDMI_INT,        LCD,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3110),
+        PINGROUP(DDC_SCL,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3114),
+        PINGROUP(DDC_SDA,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3118),
+        PINGROUP(CRT_HSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x311c),
+        PINGROUP(CRT_VSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3120),
+        PINGROUP(VI_D0,           VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3124),
+        PINGROUP(VI_D1,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3128),
+        PINGROUP(VI_D2,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x312c),
+        PINGROUP(VI_D3,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3130),
+        PINGROUP(VI_D4,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3134),
+        PINGROUP(VI_D5,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3138),
+        PINGROUP(VI_D6,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x313c),
+        PINGROUP(VI_D7,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3140),
+        PINGROUP(VI_D8,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3144),
+        PINGROUP(VI_D9,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3148),
+        PINGROUP(VI_D10,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x314c),
+        PINGROUP(VI_D11,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3150),
+        PINGROUP(VI_PCLK,         VI,       RSVD1,      SDIO2,      VI,         RSVD2,      RSVD,       INPUT,  0x3154),
+        PINGROUP(VI_MCLK,         VI,       VI,         INVALID,    INVALID,    INVALID,    RSVD,       INPUT,  0x3158),
+        PINGROUP(VI_VSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x315c),
+        PINGROUP(VI_HSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3160),
+        PINGROUP(UART2_RXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3164),
+        PINGROUP(UART2_TXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3168),
+        PINGROUP(UART2_RTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x316c),
+        PINGROUP(UART2_CTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x3170),
+        PINGROUP(UART3_TXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3174),
+        PINGROUP(UART3_RXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3178),
+        PINGROUP(UART3_CTS_N,     UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x317c),
+        PINGROUP(UART3_RTS_N,     UART,     UARTC,      PWM0,       GMI,        RSVD2,      RSVD,       INPUT,  0x3180),
+        PINGROUP(GPIO_PU0,        UART,     OWR,        UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3184),
+        PINGROUP(GPIO_PU1,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x3188),
+        PINGROUP(GPIO_PU2,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x318c),
+        PINGROUP(GPIO_PU3,        UART,     PWM0,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3190),
+        PINGROUP(GPIO_PU4,        UART,     PWM1,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3194),
+        PINGROUP(GPIO_PU5,        UART,     PWM2,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3198),
+        PINGROUP(GPIO_PU6,        UART,     PWM3,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x319c),
+        PINGROUP(GEN1_I2C_SDA,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a0),
+        PINGROUP(GEN1_I2C_SCL,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a4),
+        PINGROUP(DAP4_FS,         UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31a8),
+        PINGROUP(DAP4_DIN,        UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31ac),
+        PINGROUP(DAP4_DOUT,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b0),
+        PINGROUP(DAP4_SCLK,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b4),
+        PINGROUP(CLK3_OUT,        UART,     EXTPERIPH3, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b8),
+        PINGROUP(CLK3_REQ,        UART,     DEV3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31bc),
+        PINGROUP(GMI_WP_N,        GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31c0),
+        PINGROUP(GMI_IORDY,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c4),
+        PINGROUP(GMI_WAIT,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c8),
+        PINGROUP(GMI_ADV_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31cc),
+        PINGROUP(GMI_CLK,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31d0),
+        PINGROUP(GMI_CS0_N,       GMI,      RSVD1,      NAND,       GMI,        INVALID,    RSVD,       INPUT,  0x31d4),
+        PINGROUP(GMI_CS1_N,       GMI,      RSVD1,      NAND,       GMI,        DTV,        RSVD,       INPUT,  0x31d8),
+        PINGROUP(GMI_CS2_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31dc),
+        PINGROUP(GMI_CS3_N,       GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31e0),
+        PINGROUP(GMI_CS4_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31e4),
+        PINGROUP(GMI_CS6_N,       GMI,      NAND,       NAND_ALT,   GMI,        SATA,       RSVD,       INPUT,  0x31e8),
+        PINGROUP(GMI_CS7_N,       GMI,      NAND,       NAND_ALT,   GMI,        GMI_ALT,    RSVD,       INPUT,  0x31ec),
+        PINGROUP(GMI_AD0,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f0),
+        PINGROUP(GMI_AD1,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f4),
+        PINGROUP(GMI_AD2,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f8),
+        PINGROUP(GMI_AD3,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31fc),
+        PINGROUP(GMI_AD4,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3200),
+        PINGROUP(GMI_AD5,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3204),
+        PINGROUP(GMI_AD6,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3208),
+        PINGROUP(GMI_AD7,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x320c),
+        PINGROUP(GMI_AD8,         GMI,      PWM0,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3210),
+        PINGROUP(GMI_AD9,         GMI,      PWM1,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3214),
+        PINGROUP(GMI_AD10,        GMI,      PWM2,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3218),
+        PINGROUP(GMI_AD11,        GMI,      PWM3,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x321c),
+        PINGROUP(GMI_AD12,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3220),
+        PINGROUP(GMI_AD13,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3224),
+        PINGROUP(GMI_AD14,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3228),
+        PINGROUP(GMI_AD15,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x322c),
+        PINGROUP(GMI_A16,         GMI,      UARTD,      SPI4,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x3230),
+        PINGROUP(GMI_A17,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3234),
+        PINGROUP(GMI_A18,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3238),
+        PINGROUP(GMI_A19,         GMI,      UARTD,      SPI4,       GMI,        RSVD3,      RSVD,       INPUT,  0x323c),
+        PINGROUP(GMI_WR_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3240),
+        PINGROUP(GMI_OE_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3244),
+        PINGROUP(GMI_DQS,         GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3248),
+        PINGROUP(GMI_RST_N,       GMI,      NAND,       NAND_ALT,   GMI,        RSVD3,      RSVD,       INPUT,  0x324c),
+        PINGROUP(GEN2_I2C_SCL,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3250),
+        PINGROUP(GEN2_I2C_SDA,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3254),
+        PINGROUP(SDMMC4_CLK,      SDMMC4,   INVALID,    NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x3258),
+        PINGROUP(SDMMC4_CMD,      SDMMC4,   I2C3,       NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x325c),
+        PINGROUP(SDMMC4_DAT0,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3260),
+        PINGROUP(SDMMC4_DAT1,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3264),
+        PINGROUP(SDMMC4_DAT2,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3268),
+        PINGROUP(SDMMC4_DAT3,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x326c),
+        PINGROUP(SDMMC4_DAT4,     SDMMC4,   I2C3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3270),
+        PINGROUP(SDMMC4_DAT5,     SDMMC4,   VGP3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3274),
+        PINGROUP(SDMMC4_DAT6,     SDMMC4,   VGP4,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3278),
+        PINGROUP(SDMMC4_DAT7,     SDMMC4,   VGP5,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x327c),
+        PINGROUP(SDMMC4_RST_N,    SDMMC4,   VGP6,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3280),
+        PINGROUP(CAM_MCLK,        CAM,      VI,         INVALID,    VI_ALT2,    POPSDMMC4,  RSVD,       INPUT,  0x3284),
+        PINGROUP(GPIO_PCC1,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3288),
+        PINGROUP(GPIO_PBB0,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x328c),
+        PINGROUP(CAM_I2C_SCL,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3290),
+        PINGROUP(CAM_I2C_SDA,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3294),
+        PINGROUP(GPIO_PBB3,       CAM,      VGP3,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x3298),
+        PINGROUP(GPIO_PBB4,       CAM,      VGP4,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x329c),
+        PINGROUP(GPIO_PBB5,       CAM,      VGP5,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a0),
+        PINGROUP(GPIO_PBB6,       CAM,      VGP6,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a4),
+        PINGROUP(GPIO_PBB7,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x32a8),
+        PINGROUP(GPIO_PCC2,       CAM,      I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32ac),
+        PINGROUP(JTAG_RTCK,       SYS,      RTCK,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b0),
+        PINGROUP(PWR_I2C_SCL,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b4),
+        PINGROUP(PWR_I2C_SDA,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b8),
+        PINGROUP(KB_ROW0,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32bc),
+        PINGROUP(KB_ROW1,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c0),
+        PINGROUP(KB_ROW2,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c4),
+        PINGROUP(KB_ROW3,         SYS,      KBC,        INVALID,    RSVD2,      INVALID,    RSVD,       INPUT,  0x32c8),
+        PINGROUP(KB_ROW4,         SYS,      KBC,        INVALID,    TRACE,      RSVD3,      RSVD,       INPUT,  0x32cc),
+        PINGROUP(KB_ROW5,         SYS,      KBC,        INVALID,    TRACE,      OWR,        RSVD,       INPUT,  0x32d0),
+        PINGROUP(KB_ROW6,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d4),
+        PINGROUP(KB_ROW7,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d8),
+        PINGROUP(KB_ROW8,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32dc),
+        PINGROUP(KB_ROW9,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e0),
+        PINGROUP(KB_ROW10,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e4),
+        PINGROUP(KB_ROW11,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e8),
+        PINGROUP(KB_ROW12,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32ec),
+        PINGROUP(KB_ROW13,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f0),
+        PINGROUP(KB_ROW14,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f4),
+        PINGROUP(KB_ROW15,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f8),
+        PINGROUP(KB_COL0,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x32fc),
+        PINGROUP(KB_COL1,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3300),
+        PINGROUP(KB_COL2,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3304),
+        PINGROUP(KB_COL3,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3308),
+        PINGROUP(KB_COL4,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x330c),
+        PINGROUP(KB_COL5,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3310),
+        PINGROUP(KB_COL6,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3314),
+        PINGROUP(KB_COL7,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3318),
+        PINGROUP(CLK_32K_OUT,     SYS,      BLINK,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x331c),
+        PINGROUP(SYS_CLK_REQ,     SYS,      SYSCLK,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3320),
+        PINGROUP(CORE_PWR_REQ,    SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3324),
+        PINGROUP(CPU_PWR_REQ,     SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3328),
+        PINGROUP(PWR_INT_N,       SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x332c),
+        PINGROUP(CLK_32K_IN,      SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3330),
+        PINGROUP(OWR,             SYS,      OWR,        RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3334),
+        PINGROUP(DAP1_FS,         AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3338),
+        PINGROUP(DAP1_DIN,        AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x333c),
+        PINGROUP(DAP1_DOUT,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3340),
+        PINGROUP(DAP1_SCLK,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3344),
+        PINGROUP(CLK1_REQ,        AUDIO,    DAP,        HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x3348),
+        PINGROUP(CLK1_OUT,        AUDIO,    EXTPERIPH1, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x334c),
+        PINGROUP(SPDIF_IN,        AUDIO,    SPDIF,      HDA,        INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3350),
+        PINGROUP(SPDIF_OUT,       AUDIO,    SPDIF,      RSVD1,      INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3354),
+        PINGROUP(DAP2_FS,         AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3358),
+        PINGROUP(DAP2_DIN,        AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x335c),
+        PINGROUP(DAP2_DOUT,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3360),
+        PINGROUP(DAP2_SCLK,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3364),
+        PINGROUP(SPI2_MOSI,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3368),
+        PINGROUP(SPI2_MISO,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x336c),
+        PINGROUP(SPI2_CS0_N,      AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3370),
+        PINGROUP(SPI2_SCK,        AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3374),
+        PINGROUP(SPI1_MOSI,       AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3378),
+        PINGROUP(SPI1_SCK,        AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x337c),
+        PINGROUP(SPI1_CS0_N,      AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3380),
+        PINGROUP(SPI1_MISO,       AUDIO,    INVALID,    SPI1,       INVALID,    RSVD3,      RSVD,       INPUT,  0x3384),
+        PINGROUP(SPI2_CS1_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x3388),
+        PINGROUP(SPI2_CS2_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x338c),
+        PINGROUP(SDMMC3_CLK,      SDMMC3,   UARTA,      PWM2,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3390),
+        PINGROUP(SDMMC3_CMD,      SDMMC3,   UARTA,      PWM3,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3394),
+        PINGROUP(SDMMC3_DAT0,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x3398),
+        PINGROUP(SDMMC3_DAT1,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x339c),
+        PINGROUP(SDMMC3_DAT2,     SDMMC3,   RSVD,       PWM1,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a0),
+        PINGROUP(SDMMC3_DAT3,     SDMMC3,   RSVD,       PWM0,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a4),
+        PINGROUP(SDMMC3_DAT4,     SDMMC3,   PWM1,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33a8),
+        PINGROUP(SDMMC3_DAT5,     SDMMC3,   PWM0,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33ac),
+        PINGROUP(SDMMC3_DAT6,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b0),
+        PINGROUP(SDMMC3_DAT7,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b4),
+        PINGROUP(PEX_L0_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33b8),
+        PINGROUP(PEX_L0_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33bc),
+        PINGROUP(PEX_L0_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c0),
+        PINGROUP(PEX_WAKE_N,      PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c4),
+        PINGROUP(PEX_L1_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c8),
+        PINGROUP(PEX_L1_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33cc),
+        PINGROUP(PEX_L1_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d0),
+        PINGROUP(PEX_L2_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d4),
+        PINGROUP(PEX_L2_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d8),
+        PINGROUP(PEX_L2_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33dc),
+        PINGROUP(HDMI_CEC,        SYS,      CEC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e0),
+};
+
+void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
+                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+                int *pgdrive_max)
+{
+        *pg = tegra_soc_pingroups;
+        *pg_max = TEGRA_MAX_PINGROUP;
+        *pgdrive = tegra_soc_drive_pingroups;
+        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+}
+
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 1d201650d7a..ac35d2b7685 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -21,6 +21,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of_device.h>
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
@@ -33,8 +34,10 @@
 #define SLWR(reg)       (((reg) >> 28) & 0x3)
 #define SLWF(reg)       (((reg) >> 30) & 0x3)
 
-static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
-static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
+static const struct tegra_pingroup_desc *pingroups;
+static const struct tegra_drive_pingroup_desc *drive_pingroups;
+static int pingroup_max;
+static int drive_max;
 
 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -97,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_VI] = "VI",
         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
         [TEGRA_MUX_XIO] = "XIO",
+        [TEGRA_MUX_BLINK] = "BLINK",
+        [TEGRA_MUX_CEC] = "CEC",
+        [TEGRA_MUX_CLK12] = "CLK12",
+        [TEGRA_MUX_DAP] = "DAP",
+        [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
+        [TEGRA_MUX_DDR] = "DDR",
+        [TEGRA_MUX_DEV3] = "DEV3",
+        [TEGRA_MUX_DTV] = "DTV",
+        [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
+        [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
+        [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
+        [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
+        [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
+        [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
+        [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
+        [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
+        [TEGRA_MUX_HDA] = "HDA",
+        [TEGRA_MUX_HSI] = "HSI",
+        [TEGRA_MUX_I2C4] = "I2C4",
+        [TEGRA_MUX_I2C5] = "I2C5",
+        [TEGRA_MUX_I2CPWR] = "I2CPWR",
+        [TEGRA_MUX_I2S0] = "I2S0",
+        [TEGRA_MUX_I2S1] = "I2S1",
+        [TEGRA_MUX_I2S2] = "I2S2",
+        [TEGRA_MUX_I2S3] = "I2S3",
+        [TEGRA_MUX_I2S4] = "I2S4",
+        [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
+        [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
+        [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
+        [TEGRA_MUX_PWM0] = "PWM0",
+        [TEGRA_MUX_PWM1] = "PWM2",
+        [TEGRA_MUX_PWM2] = "PWM2",
+        [TEGRA_MUX_PWM3] = "PWM3",
+        [TEGRA_MUX_SATA] = "SATA",
+        [TEGRA_MUX_SPI5] = "SPI5",
+        [TEGRA_MUX_SPI6] = "SPI6",
+        [TEGRA_MUX_SYSCLK] = "SYSCLK",
+        [TEGRA_MUX_VGP1] = "VGP1",
+        [TEGRA_MUX_VGP2] = "VGP2",
+        [TEGRA_MUX_VGP3] = "VGP3",
+        [TEGRA_MUX_VGP4] = "VGP4",
+        [TEGRA_MUX_VGP5] = "VGP5",
+        [TEGRA_MUX_VGP6] = "VGP6",
         [TEGRA_MUX_SAFE] = "<safe>",
 };
 
@@ -116,9 +162,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
 
 static DEFINE_SPINLOCK(mux_lock);
 
-static const char *pingroup_name(enum tegra_pingroup pg)
+static const char *pingroup_name(int pg)
 {
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return "<UNKNOWN>";
 
         return pingroups[pg].name;
@@ -189,10 +235,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
         int i;
         unsigned long reg;
         unsigned long flags;
-        enum tegra_pingroup pg = config->pingroup;
+        int pg = config->pingroup;
         enum tegra_mux_func func = config->func;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].mux_reg < 0)
@@ -230,13 +276,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
         return 0;
 }
 
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
-        enum tegra_tristate tristate)
+int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
 {
         unsigned long reg;
         unsigned long flags;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].tri_reg < 0)
@@ -255,13 +300,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
         return 0;
 }
 
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
-        enum tegra_pullupdown pupd)
+int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
 {
         unsigned long reg;
         unsigned long flags;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].pupd_reg < 0)
@@ -287,7 +331,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
 
 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
 {
-        enum tegra_pingroup pingroup = config->pingroup;
+        int pingroup = config->pingroup;
         enum tegra_mux_func func     = config->func;
         enum tegra_pullupdown pupd   = config->pupd;
         enum tegra_tristate tristate = config->tristate;
@@ -323,9 +367,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l
                 tegra_pinmux_config_pingroup(&config[i]);
 }
 
-static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
+static const char *drive_pinmux_name(int pg)
 {
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return "<UNKNOWN>";
 
         return drive_pingroups[pg].name;
@@ -352,12 +396,11 @@ static const char *slew_name(unsigned long val)
         return tegra_slew_names[val];
 }
 
-static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
-        enum tegra_hsm hsm)
+static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
@@ -377,12 +420,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
-        enum tegra_schmitt schmitt)
+static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
@@ -402,12 +444,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
-        enum tegra_drive drive)
+static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
@@ -425,12 +466,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_pull_down(int pg,
         enum tegra_pull_strength pull_down)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
@@ -448,12 +489,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_pull_up(int pg,
         enum tegra_pull_strength pull_up)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
@@ -471,12 +512,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_slew_rising(int pg,
         enum tegra_slew slew_rising)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
@@ -494,12 +535,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_slew_falling(int pg,
         enum tegra_slew slew_falling)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
@@ -517,7 +558,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
+static void tegra_drive_pinmux_config_pingroup(int pingroup,
                                           enum tegra_hsm hsm,
                                           enum tegra_schmitt schmitt,
                                           enum tegra_drive drive,
@@ -596,7 +637,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf
         for (i = 0; i < len; i++) {
                 int err;
                 c = config[i];
-                if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
+                if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
                         WARN_ON(1);
                         continue;
                 }
@@ -617,7 +658,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config
         for (i = 0; i < len; i++) {
                 int err;
                 if (config[i].pingroup < 0 ||
-                    config[i].pingroup >= TEGRA_MAX_PINGROUP) {
+                    config[i].pingroup >= pingroup_max) {
                         WARN_ON(1);
                         continue;
                 }
@@ -635,7 +676,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 {
         int i;
         int err;
-        enum tegra_pingroup pingroup;
+        int pingroup;
 
         for (i = 0; i < len; i++) {
                 pingroup = config[i].pingroup;
@@ -654,7 +695,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
 {
         int i;
         int err;
-        enum tegra_pingroup pingroup;
+        int pingroup;
 
         for (i = 0; i < len; i++) {
                 pingroup = config[i].pingroup;
@@ -668,11 +709,36 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
         }
 }
 
+static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
+#endif
+        { },
+};
+
 static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int i;
         int config_bad = 0;
+        const struct of_device_id *match;
+
+        match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
+
+        if (match)
+                ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
+                        &drive_pingroups, &drive_max);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        else
+                /* no device tree available, so we must be on tegra20 */
+                tegra20_pinmux_init(&pingroups, &pingroup_max,
+                                        &drive_pingroups, &drive_max);
+#else
+        pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
+#endif
 
         for (i = 0; ; i++) {
                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -681,7 +747,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
         }
         nbanks = i;
 
-        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+        for (i = 0; i < pingroup_max; i++) {
                 if (pingroups[i].tri_bank >= nbanks) {
                         dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
                         config_bad = 1;
@@ -698,7 +764,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
                 }
         }
 
-        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+        for (i = 0; i < drive_max; i++) {
                 if (drive_pingroups[i].reg_bank >= nbanks) {
                         dev_err(&pdev->dev,
                                 "drive pingroup %d: bad reg_bank\n", i);
@@ -741,11 +807,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
         return 0;
 }
 
-static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
-        { .compatible = "nvidia,tegra20-pinmux", },
-        { },
-};
-
 static struct platform_driver tegra_pinmux_driver = {
         .driver         = {
                 .name   = "tegra-pinmux",
@@ -779,7 +840,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
         int i;
         int len;
 
-        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+        for (i = 0; i < pingroup_max; i++) {
                 unsigned long reg;
                 unsigned long tri;
                 unsigned long mux;
@@ -850,7 +911,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
         int i;
         int len;
 
-        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+        for (i = 0; i < drive_max; i++) {
                 u32 reg;
 
                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 371869d8ea0..ff9e6b6c046 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];
 #define pmc_readl(reg) \
         __raw_readl(reg_pmc_base + (reg))
 
-unsigned long clk_measure_input_freq(void)
+static unsigned long clk_measure_input_freq(void)
 {
         u32 clock_autodetect;
         clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {
         .disable        = tegra2_clk_m_disable,
 };
 
-void tegra2_periph_reset_assert(struct clk *c)
-{
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, true);
-}
-
-void tegra2_periph_reset_deassert(struct clk *c)
-{
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, false);
-}
-
 /* super clock functions */
 /* "super clocks" on tegra have two-stage muxes and a clock skipping
  * super divider.  We will ignore the clock skipping divider, since we
@@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = {
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
 {
         u32 reg;
+        unsigned long flags;
+
+        spin_lock_irqsave(&c->spinlock, flags);
 
         delay = clamp(delay, 0, 15);
         reg = clk_readl(c->reg);
@@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
         reg |= SDMMC_CLK_INT_FB_SEL;
         reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
         clk_writel(reg, c->reg);
+
+        spin_unlock_irqrestore(&c->spinlock, flags);
 }
 
 /* External memory controller clock ops */
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 732c724008b..1d1acda4f3e 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -165,20 +165,28 @@ static struct irqaction tegra_timer_irq = {
 static void __init tegra_init_timer(void)
 {
         struct clk *clk;
-        unsigned long rate = clk_measure_input_freq();
+        unsigned long rate;
         int ret;
 
         clk = clk_get_sys("timer", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        if (IS_ERR(clk)) {
+                pr_warn("Unable to get timer clock."
+                        " Assuming 12Mhz input clock.\n");
+                rate = 12000000;
+        } else {
+                clk_enable(clk);
+                rate = clk_get_rate(clk);
+        }
 
         /*
          * rtc registers are used by read_persistent_clock, keep the rtc clock
          * enabled
          */
         clk = clk_get_sys("rtc-tegra", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        if (IS_ERR(clk))
+                pr_warn("Unable to get rtc-tegra clock\n");
+        else
+                clk_enable(clk);
 
 #ifdef CONFIG_HAVE_ARM_TWD
         twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1cbcd4fc1e1..54d8f34fdee 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -7,8 +7,8 @@ comment "ST-Ericsson Mobile Platform Products"
 config MACH_U300
         bool "U300"
         select PINCTRL
-        select PINMUX_U300
-        select GPIO_U300
+        select PINCTRL_U300
+        select PINCTRL_COH901
 
 comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
 
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 697930761b3..b4c6926a700 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1605,15 +1605,15 @@ static struct platform_device pinmux_device = {
 };
 
 /* Pinmux settings */
-static struct pinmux_map u300_pinmux_map[] = {
+static struct pinmux_map __initdata u300_pinmux_map[] = {
         /* anonymous maps for chip power and EMIFs */
-        PINMUX_MAP_PRIMARY_SYS_HOG("POWER", "power"),
-        PINMUX_MAP_PRIMARY_SYS_HOG("EMIF0", "emif0"),
-        PINMUX_MAP_PRIMARY_SYS_HOG("EMIF1", "emif1"),
+        PINMUX_MAP_SYS_HOG("POWER", "pinmux-u300", "power"),
+        PINMUX_MAP_SYS_HOG("EMIF0", "pinmux-u300", "emif0"),
+        PINMUX_MAP_SYS_HOG("EMIF1", "pinmux-u300", "emif1"),
         /* per-device maps for MMC/SD, SPI and UART */
-        PINMUX_MAP_PRIMARY("MMCSD", "mmc0", "mmci"),
-        PINMUX_MAP_PRIMARY("SPI", "spi0", "pl022"),
-        PINMUX_MAP_PRIMARY("UART0", "uart0", "uart0"),
+        PINMUX_MAP("MMCSD", "pinmux-u300", "mmc0", "mmci"),
+        PINMUX_MAP("SPI", "pinmux-u300", "spi0", "pl022"),
+        PINMUX_MAP("UART0", "pinmux-u300", "uart0", "uart0"),
 };
 
 struct u300_mux_hog {
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
index 0c2b2021951..bf4c7935aec 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/arch/arm/mach-u300/include/mach/gpio-u300.h
@@ -9,121 +9,6 @@
 #ifndef __MACH_U300_GPIO_U300_H
 #define __MACH_U300_GPIO_U300_H
 
-/*
- * Individual pin assignments for the B26/S26. Notice that the
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
-#define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP         4
-#define U300_GPIO_PIN_CAM_REG_EN        5
-#define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
-#define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-#endif
-
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
-    defined(CONFIG_MACH_U300_BS335)
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_UART_CTS          2
-#define U300_GPIO_PIN_UART_RTS          3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
-
-#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-
-#ifdef CONFIG_MACH_U300_BS335
-
-#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
-#endif
-
-#endif
-
 /**
  * enum u300_gpio_variant - the type of U300 GPIO employed
  */
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index db3fbfa1d6e..ee78a26707e 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -110,7 +110,7 @@
 #endif
 
 /* Maximum 8*7 GPIO lines */
-#ifdef CONFIG_GPIO_U300
+#ifdef CONFIG_PINCTRL_COH901
 #define IRQ_U300_GPIO_BASE              (U300_VIC_IRQS_END)
 #define IRQ_U300_GPIO_END               (IRQ_U300_GPIO_BASE + 56)
 #else
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
deleted file mode 100644
index c808f347a08..00000000000
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/memory.h
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Memory virtual/physical mapping constants.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-#define PLAT_PHYS_OFFSET        UL(0x48000000)
-#define BOOT_PARAMS_OFFSET      0x100
-
-#endif
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 4d482aacc27..05abd6ad9fa 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -18,8 +18,8 @@
 #include <linux/slab.h>
 #include <mach/coh901318.h>
 #include <mach/dma_channels.h>
-#include <mach/gpio-u300.h>
 
+#include "u300-gpio.h"
 #include "mmc.h"
 
 static struct mmci_platform_data mmc0_plat_data = {
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
new file mode 100644
index 00000000000..847dc25300c
--- /dev/null
+++ b/arch/arm/mach-u300/u300-gpio.h
@@ -0,0 +1,114 @@
+/*
+ * Individual pin assignments for the B26/S26. Notice that the
+ * actual usage of these pins depends on the PAD MUX settings, that
+ * is why the same number can potentially appear several times.
+ * In the reference design each pin is only used for one purpose.
+ * These were determined by inspecting the B26/S26 schematic:
+ * 2/1911-ROA 128 1603
+ */
+#ifdef CONFIG_MACH_U300_BS2X
+#define U300_GPIO_PIN_UART_RX           0
+#define U300_GPIO_PIN_UART_TX           1
+#define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
+#define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
+#define U300_GPIO_PIN_CAM_SLEEP         4
+#define U300_GPIO_PIN_CAM_REG_EN        5
+#define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
+#define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
+
+#define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
+#define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
+#define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
+#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
+#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
+#define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
+#define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
+#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
+
+#define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
+#define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
+#define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
+#define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
+#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
+#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
+#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
+#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
+#endif
+
+/*
+ * Individual pin assignments for the B330/S330 and B365/S365.
+ * Notice that the actual usage of these pins depends on the
+ * PAD MUX settings, that is why the same number can potentially
+ * appear several times. In the reference design each pin is only
+ * used for one purpose. These were determined by inspecting the
+ * S365 schematic.
+ */
+#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
+    defined(CONFIG_MACH_U300_BS335)
+#define U300_GPIO_PIN_UART_RX           0
+#define U300_GPIO_PIN_UART_TX           1
+#define U300_GPIO_PIN_UART_CTS          2
+#define U300_GPIO_PIN_UART_RTS          3
+#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
+#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
+#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
+#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
+
+#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
+#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
+#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
+#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
+#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
+#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
+#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
+#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
+
+#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
+#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
+#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
+#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
+#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
+#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
+#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
+#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
+
+#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
+#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
+#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
+#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
+#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
+#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
+#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
+#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
+
+#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
+#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
+#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
+#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
+#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
+#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
+#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
+#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
+
+#ifdef CONFIG_MACH_U300_BS335
+
+#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
+#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
+#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
+#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
+#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
+#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
+#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
+#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
+
+#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
+#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
+#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
+#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
+#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
+#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
+#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
+#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
+#endif
+
+#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index def45bda293..f30c69d91d9 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -47,7 +47,7 @@ static void __init u300_init_machine(void)
 
 MACHINE_START(U300, MACH_U300_STRING)
         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = BOOT_PARAMS_OFFSET,
+        .atag_offset    = 0x100,
         .map_io         = u300_map_io,
         .init_irq       = u300_init_irq,
         .handle_irq     = vic_handle_irq,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 6826faeecc6..23be34b3bb6 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -22,6 +22,12 @@
 #include "ste-dma40-db8500.h"
 
 /*
+ * v2 has a new version of this block that need to be forced, the number found
+ * in hardware is incorrect
+ */
+#define U8500_SDI_V2_PERIPHID 0x10480180
+
+/*
  * SDI 0 (MicroSD slot)
  */
 
@@ -117,10 +123,7 @@ static void sdi0_configure(void)
         gpio_direction_output(sdi0_en, 1);
 
         /* Add the device, force v2 to subrevision 1 */
-        if (cpu_is_u8500v2())
-                db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
-        else
-                db8500_add_sdi0(&mop500_sdi0_data, 0);
+        db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
 }
 
 void mop500_sdi_tc35892_init(void)
@@ -132,6 +135,42 @@ void mop500_sdi_tc35892_init(void)
 }
 
 /*
+ * SDI1 (SDIO WLAN)
+ */
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+
+static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
+
+static struct mmci_platform_data mop500_sdi1_data = {
+        .ocr_mask       = MMC_VDD_29_30,
+        .f_max          = 50000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &sdi1_dma_cfg_rx,
+        .dma_tx_param   = &sdi1_dma_cfg_tx,
+#endif
+};
+
+/*
  * SDI 2 (POP eMMC, not on DB8500ed)
  */
 
@@ -158,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 static struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
         .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_MMC_HIGHSPEED,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -208,20 +248,10 @@ static struct mmci_platform_data mop500_sdi4_data = {
 
 void __init mop500_sdi_init(void)
 {
-        u32 periphid = 0;
-
-        /* v2 has a new version of this block that need to be forced */
-        if (cpu_is_u8500v2())
-                periphid = 0x10480180;
-        /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
-        if (!cpu_is_u8500v10())
-                mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-
-        db8500_add_sdi2(&mop500_sdi2_data, periphid);
-
+        /* PoP:ed eMMC */
+        db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data, periphid);
-
+        db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
         /*
          * On boards with the TC35892 GPIO expander, sdi0 will finally
          * be added when the TC35892 initializes and calls
@@ -231,13 +261,9 @@ void __init mop500_sdi_init(void)
 
 void __init snowball_sdi_init(void)
 {
-        u32 periphid = 0x10480180;
-
-        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data, periphid);
-
+        db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
+        /* External Micro SD slot */
         mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
         mop500_sdi0_data.cd_invert = true;
         sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
@@ -247,17 +273,15 @@ void __init snowball_sdi_init(void)
 
 void __init hrefv60_sdi_init(void)
 {
-        u32 periphid = 0x10480180;
-
-        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-
-        db8500_add_sdi2(&mop500_sdi2_data, periphid);
-
+        /* PoP:ed eMMC */
+        db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data, periphid);
-
+        db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
+        /* External Micro SD slot */
         mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
         sdi0_en = HREFV60_SDMMC_EN_GPIO;
         sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
         sdi0_configure();
+        /* WLAN SDIO channel */
+        db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
 }
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index de1f5f8f733..9361a529017 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
                         ARRAY_SIZE(mop500_platform_devs));
 
         mop500_i2c_init();
-        mop500_sdi_init();
+        hrefv60_sdi_init();
         mop500_spi_init();
         mop500_uart_init();
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index de18a2a23e6..f926d3db620 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,40 +7,77 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
 
-/* snowball GPIO for MMC card */
-#define SNOWBALL_SDMMC_EN_GPIO 217
-#define SNOWBALL_SDMMC_1V8_3V_GPIO 228
-#define SNOWBALL_SDMMC_CD_GPIO 218
+/* Snowball specific GPIO assignments, this board has no GPIO expander */
+#define SNOWBALL_ACCEL_INT1_GPIO        163
+#define SNOWBALL_ACCEL_INT2_GPIO        164
+#define SNOWBALL_MAGNET_DRDY_GPIO       165
+#define SNOWBALL_SDMMC_EN_GPIO          217
+#define SNOWBALL_SDMMC_1V8_3V_GPIO      228
+#define SNOWBALL_SDMMC_CD_GPIO          218
 
 /* HREFv60-specific GPIO assignments, this board has no GPIO expander */
-#define HREFV60_TOUCH_RST_GPIO          143
-#define HREFV60_PROX_SENSE_GPIO         217
-#define HREFV60_HAL_SW_GPIO             145
-#define HREFV60_SDMMC_EN_GPIO           169
 #define HREFV60_SDMMC_1V8_3V_GPIO       5
-#define HREFV60_SDMMC_CD_GPIO           95
-#define HREFV60_ACCEL_INT1_GPIO         82
-#define HREFV60_ACCEL_INT2_GPIO         83
+#define HREFV60_CAMERA_FLASH_ENABLE     21
 #define HREFV60_MAGNET_DRDY_GPIO        32
 #define HREFV60_DISP1_RST_GPIO          65
 #define HREFV60_DISP2_RST_GPIO          66
+#define HREFV60_ACCEL_INT1_GPIO         82
+#define HREFV60_ACCEL_INT2_GPIO         83
+#define HREFV60_SDMMC_CD_GPIO           95
+#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140
+#define HREFV60_TOUCH_RST_GPIO          143
+#define HREFV60_HAL_SW_GPIO             145
+#define HREFV60_SDMMC_EN_GPIO           169
+#define HREFV60_MMIO_XENON_CHARGE       170
+#define HREFV60_PROX_SENSE_GPIO         217
+
+/* MOP500 generic GPIOs */
+#define CAMERA_FLASH_INT_PIN            7
+#define CYPRESS_TOUCH_INT_PIN           84
+#define XSHUTDOWN_PRIMARY_SENSOR        141
+#define XSHUTDOWN_SECONDARY_SENSOR      142
+#define CYPRESS_TOUCH_RST_GPIO          143
+#define MOP500_HDMI_RST_GPIO            196
+#define CYPRESS_SLAVE_SELECT_GPIO       216
 
 /* GPIOs on the TC35892 expander */
 #define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
+#define GPIO_MAGNET_DRDY                MOP500_EGPIO(1)
 #define GPIO_SDMMC_CD                   MOP500_EGPIO(3)
+#define GPIO_CAMERA_FLASH_ENABLE        MOP500_EGPIO(4)
+#define GPIO_MMIO_XENON_CHARGE          MOP500_EGPIO(5)
 #define GPIO_PROX_SENSOR                MOP500_EGPIO(7)
+#define GPIO_HAL_SENSOR                 MOP500_EGPIO(8)
+#define GPIO_ACCEL_INT1                 MOP500_EGPIO(10)
+#define GPIO_ACCEL_INT2                 MOP500_EGPIO(11)
 #define GPIO_BU21013_CS                 MOP500_EGPIO(13)
+#define MOP500_DISP2_RST_GPIO           MOP500_EGPIO(14)
+#define MOP500_DISP1_RST_GPIO           MOP500_EGPIO(15)
 #define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
 #define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
 #define MOP500_EGPIO_END                MOP500_EGPIO(24)
 
-/* GPIOs on the AB8500 mixed-signals circuit */
-#define MOP500_AB8500_GPIO(x)           (MOP500_EGPIO_END + (x))
+/*
+ * GPIOs on the AB8500 mixed-signals circuit
+ * Notice that we subtract 1 from the number passed into the macro, this is
+ * because the AB8500 GPIO pins are enumbered starting from 1, so the value in
+ * parens matches the GPIO pin number in the data sheet.
+ */
+#define MOP500_AB8500_GPIO(x)           (MOP500_EGPIO_END + (x) - 1)
+/*Snowball AB8500 GPIO */
+#define SNOWBALL_VSMPS2_1V8_GPIO        MOP500_AB8500_PIN_GPIO(1)       /* SYSCLKREQ2/GPIO1 */
+#define SNOWBALL_PM_GPIO1_GPIO          MOP500_AB8500_PIN_GPIO(2)       /* SYSCLKREQ3/GPIO2 */
+#define SNOWBALL_WLAN_CLK_REQ_GPIO      MOP500_AB8500_PIN_GPIO(3)       /* SYSCLKREQ4/GPIO3 */
+#define SNOWBALL_PM_GPIO4_GPIO          MOP500_AB8500_PIN_GPIO(4)       /* SYSCLKREQ6/GPIO4 */
+#define SNOWBALL_EN_3V6_GPIO            MOP500_AB8500_PIN_GPIO(16)      /* PWMOUT3/GPIO16 */
+#define SNOWBALL_PME_ETH_GPIO           MOP500_AB8500_PIN_GPIO(24)      /* SYSCLKREQ7/GPIO24 */
+#define SNOWBALL_EN_3V3_ETH_GPIO        MOP500_AB8500_PIN_GPIO(26)      /* GPIO26 */
 
 struct i2c_board_info;
 
 extern void mop500_sdi_init(void);
 extern void snowball_sdi_init(void);
+extern void hrefv60_sdi_init(void);
 extern void mop500_sdi_tc35892_init(void);
 void __init mop500_u8500uib_init(void);
 void __init mop500_stuib_init(void);
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index e832664d1bd..73790753700 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk)
         writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
 }
 
-/* ED doesn't have the combined set/clr registers */
-static void clk_prcmu_ed_enable(struct clk *clk)
-{
-        void __iomem *addr = __io_address(U8500_PRCMU_BASE)
-                             + clk->prcmu_cg_mgt;
-
-        writel(readl(addr) | PRCM_MGT_ENABLE, addr);
-}
-
-static void clk_prcmu_ed_disable(struct clk *clk)
-{
-        void __iomem *addr = __io_address(U8500_PRCMU_BASE)
-                             + clk->prcmu_cg_mgt;
-
-        writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
-}
-
 static struct clkops clk_prcmu_ops = {
         .enable = clk_prcmu_enable,
         .disable = clk_prcmu_disable,
@@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = {
         [3] = U8500_CLKRST3_BASE,
         [5] = U8500_CLKRST5_BASE,
         [6] = U8500_CLKRST6_BASE,
-        [7] = U8500_CLKRST7_BASE_ED,
 };
 
 static void clk_prcc_enable(struct clk *clk)
@@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk,	0x0, 12, PER2CLK);
 static DEFINE_PRCMU_CLK(per3clk,        0x0, 13, PER3CLK);
 static DEFINE_PRCMU_CLK(per5clk,        0x0, 14, PER5CLK);
 static DEFINE_PRCMU_CLK_RATE(per6clk,   0x0, 15, PER6CLK, 133330000);
-static DEFINE_PRCMU_CLK_RATE(per7clk,   0x0, 16, PER7CLK, 100000000);
 static DEFINE_PRCMU_CLK(lcdclk,         0x0, 17, LCDCLK);
 static DEFINE_PRCMU_CLK(bmlclk,         0x0, 18, BMLCLK);
 static DEFINE_PRCMU_CLK(hsitxclk,       0x0, 19, HSITXCLK);
@@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
 static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
 static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3_ed,      7,  7, NULL);
-static DEFINE_PRCC_CLK(1, spi3_v1,      7, -1, NULL);
+static DEFINE_PRCC_CLK(1, spi3,         7, -1, NULL);
 static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, sdi0,         5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1_ed,      4,  4, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, msp1_v1,      4,  4, &clk_msp1clk);
+static DEFINE_PRCC_CLK(1, msp1,         4,  4, &clk_msp1clk);
 static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
 static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
 static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
 
 /* Peripheral Cluster #2 */
-
-static DEFINE_PRCC_CLK(2, gpio1_ed,     12, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx_ed,     11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssirx_ed,     10, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi0_ed,       9, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3_ed,       8,  6, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1_ed,       7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2_ed,       6,  4, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4_ed,       4,  2, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, pwl_ed,        3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1_ed,       2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2_ed,       1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3_ed,       0,  0, &clk_i2cclk);
-
-static DEFINE_PRCC_CLK(2, gpio1_v1,     11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx_v1,     10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx_v1,      9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0_v1,       8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3_v1,       7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1_v1,       6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2_v1,       5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4_v1,       4,  2, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, pwl_v1,        3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1_v1,       2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2_v1,       1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3_v1,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(2, gpio1,        11, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssitx,        10,  7, NULL);
+static DEFINE_PRCC_CLK(2, ssirx,         9,  6, NULL);
+static DEFINE_PRCC_CLK(2, spi0,         8, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3,         7,  5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1,         6,  4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2,         5,  3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4,         4,  2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, pwl,          3,  1, NULL);
+static DEFINE_PRCC_CLK(2, spi1,         2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2,         1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3,         0,  0, &clk_i2cclk);
 
 /* Peripheral Cluster #3 */
 static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
@@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2,	6,  6, &clk_uartclk);
 static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
 static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1_ed,      2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp0_ed,      1,  1, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1_v1,      2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0_v1,      1,  1, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, ssp1,         2,  2, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, ssp0,         1,  1, &clk_sspclk);
 static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
 
 /* Peripheral Cluster #4 is in the always on domain */
 
 /* Peripheral Cluster #5 */
 static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb_ed,       0,  0, &clk_i2cclk);
-static DEFINE_PRCC_CLK(5, usb_v1,       0,  0, NULL);
+static DEFINE_PRCC_CLK(5, usb,          0,  0, NULL);
 
 /* Peripheral Cluster #6 */
 
 /* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg_v1,    6,  6, NULL);
-static DEFINE_PRCC_CLK(6, dmc_ed,       6,  6, NULL);
+static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
+static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
+static DEFINE_PRCC_CLK(6, cfgreg,       6,  6, NULL);
 static DEFINE_PRCC_CLK(6, hash1,        5, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro_v1,    4,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, cryp1_ed,     4, -1, NULL);
+static DEFINE_PRCC_CLK(6, unipro,       4,  1, &clk_uniproclk);
 static DEFINE_PRCC_CLK(6, pka,          3, -1, NULL);
 static DEFINE_PRCC_CLK(6, hash0,        2, -1, NULL);
 static DEFINE_PRCC_CLK(6, cryp0,        1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng_ed,       0,  0, &clk_i2cclk);
-static DEFINE_PRCC_CLK(6, rng_v1,       0,  0, &clk_rngclk);
-
-/* Peripheral Cluster #7 */
-
-static DEFINE_PRCC_CLK(7, tzpc0_ed,     4, -1, NULL);
-/* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
-static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
+static DEFINE_PRCC_CLK(6, rng,  0,  0, &clk_rngclk);
 
 static struct clk clk_dummy_apb_pclk = {
         .name = "apb_pclk",
 };
 
-static struct clk_lookup u8500_common_clks[] = {
+static struct clk_lookup u8500_clks[] = {
         CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
 
         /* Peripheral Cluster #1 */
@@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = {
         CLK(dmaclk,     "dma40.0",      NULL),
         CLK(b2r2clk,    "b2r2",         NULL),
         CLK(tvclk,      "tv",           NULL),
-};
 
-static struct clk_lookup u8500_ed_clks[] = {
-        /* Peripheral Cluster #1 */
-        CLK(spi3_ed,    "spi3",         NULL),
-        CLK(msp1_ed,    "msp1",         NULL),
-
-        /* Peripheral Cluster #2 */
-        CLK(gpio1_ed,   "gpio.6",       NULL),
-        CLK(gpio1_ed,   "gpio.7",       NULL),
-        CLK(ssitx_ed,   "ssitx",        NULL),
-        CLK(ssirx_ed,   "ssirx",        NULL),
-        CLK(spi0_ed,    "spi0",         NULL),
-        CLK(sdi3_ed,    "sdi3",         NULL),
-        CLK(sdi1_ed,    "sdi1",         NULL),
-        CLK(msp2_ed,    "msp2",         NULL),
-        CLK(sdi4_ed,    "sdi4",         NULL),
-        CLK(pwl_ed,     "pwl",          NULL),
-        CLK(spi1_ed,    "spi1",         NULL),
-        CLK(spi2_ed,    "spi2",         NULL),
-        CLK(i2c3_ed,    "nmk-i2c.3",    NULL),
-
-        /* Peripheral Cluster #3 */
-        CLK(ssp1_ed,    "ssp1",         NULL),
-        CLK(ssp0_ed,    "ssp0",         NULL),
-
-        /* Peripheral Cluster #5 */
-        CLK(usb_ed,     "musb-ux500.0", "usb"),
-
-        /* Peripheral Cluster #6 */
-        CLK(dmc_ed,     "dmc",          NULL),
-        CLK(cryp1_ed,   "cryp1",        NULL),
-        CLK(rng_ed,     "rng",          NULL),
-
-        /* Peripheral Cluster #7 */
-        CLK(tzpc0_ed,   "tzpc0",        NULL),
-        CLK(mtu1_ed,    "mtu1",         NULL),
-        CLK(mtu0_ed,    "mtu0",         NULL),
-        CLK(wdg_ed,     "wdg",          NULL),
-        CLK(cfgreg_ed,  "cfgreg",       NULL),
-};
-
-static struct clk_lookup u8500_v1_clks[] = {
         /* Peripheral Cluster #1 */
         CLK(i2c4,       "nmk-i2c.4",    NULL),
-        CLK(spi3_v1,    "spi3",         NULL),
-        CLK(msp1_v1,    "msp1",         NULL),
+        CLK(spi3,       "spi3",         NULL),
+        CLK(msp1,       "msp1",         NULL),
 
         /* Peripheral Cluster #2 */
-        CLK(gpio1_v1,   "gpio.6",       NULL),
-        CLK(gpio1_v1,   "gpio.7",       NULL),
-        CLK(ssitx_v1,   "ssitx",        NULL),
-        CLK(ssirx_v1,   "ssirx",        NULL),
-        CLK(spi0_v1,    "spi0",         NULL),
-        CLK(sdi3_v1,    "sdi3",         NULL),
-        CLK(sdi1_v1,    "sdi1",         NULL),
-        CLK(msp2_v1,    "msp2",         NULL),
-        CLK(sdi4_v1,    "sdi4",         NULL),
-        CLK(pwl_v1,     "pwl",          NULL),
-        CLK(spi1_v1,    "spi1",         NULL),
-        CLK(spi2_v1,    "spi2",         NULL),
-        CLK(i2c3_v1,    "nmk-i2c.3",    NULL),
+        CLK(gpio1,      "gpio.6",       NULL),
+        CLK(gpio1,      "gpio.7",       NULL),
+        CLK(ssitx,      "ssitx",        NULL),
+        CLK(ssirx,      "ssirx",        NULL),
+        CLK(spi0,       "spi0",         NULL),
+        CLK(sdi3,       "sdi3",         NULL),
+        CLK(sdi1,       "sdi1",         NULL),
+        CLK(msp2,       "msp2",         NULL),
+        CLK(sdi4,       "sdi4",         NULL),
+        CLK(pwl,        "pwl",          NULL),
+        CLK(spi1,       "spi1",         NULL),
+        CLK(spi2,       "spi2",         NULL),
+        CLK(i2c3,       "nmk-i2c.3",    NULL),
 
         /* Peripheral Cluster #3 */
-        CLK(ssp1_v1,    "ssp1",         NULL),
-        CLK(ssp0_v1,    "ssp0",         NULL),
+        CLK(ssp1,       "ssp1",         NULL),
+        CLK(ssp0,       "ssp0",         NULL),
 
         /* Peripheral Cluster #5 */
-        CLK(usb_v1,     "musb-ux500.0", "usb"),
+        CLK(usb,        "musb-ux500.0", "usb"),
 
         /* Peripheral Cluster #6 */
-        CLK(mtu1_v1,    "mtu1",         NULL),
-        CLK(mtu0_v1,    "mtu0",         NULL),
-        CLK(cfgreg_v1,  "cfgreg",       NULL),
+        CLK(mtu1,       "mtu1",         NULL),
+        CLK(mtu0,       "mtu0",         NULL),
+        CLK(cfgreg,     "cfgreg",       NULL),
         CLK(hash1,      "hash1",        NULL),
-        CLK(unipro_v1,  "unipro",       NULL),
-        CLK(rng_v1,     "rng",          NULL),
+        CLK(unipro,     "unipro",       NULL),
+        CLK(rng,        "rng",          NULL),
 
         /* PRCMU level clock gating */
 
@@ -743,7 +651,7 @@ err_out:
 late_initcall(clk_debugfs_init);
 #endif /* defined(CONFIG_DEBUG_FS) */
 
-unsigned long clk_smp_twd_rate = 400000000;
+unsigned long clk_smp_twd_rate = 500000000;
 
 unsigned long clk_smp_twd_get_rate(struct clk *clk)
 {
@@ -769,7 +677,7 @@ static int clk_twd_cpufreq_transition(struct notifier_block *nb,
 
         if (state == CPUFREQ_PRECHANGE) {
                 /* Save frequency in simple Hz */
-                clk_smp_twd_rate = f->new * 1000;
+                clk_smp_twd_rate = (f->new * 1000) / 2;
         }
 
         return NOTIFY_OK;
@@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq);
 
 int __init clk_init(void)
 {
-        if (cpu_is_u8500ed()) {
-                clk_prcmu_ops.enable = clk_prcmu_ed_enable;
-                clk_prcmu_ops.disable = clk_prcmu_ed_disable;
-                clk_per6clk.rate = 100000000;
-        } else if (cpu_is_u5500()) {
+        if (cpu_is_u5500()) {
                 /* Clock tree for U5500 not implemented yet */
                 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
                 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
@@ -802,20 +706,11 @@ int __init clk_init(void)
                 clk_sdmmcclk.rate = 99900000;
         }
 
-        clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
-        if (cpu_is_u8500ed())
-                clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
-        else
-                clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
-
+        clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
         clkdev_add(&clk_smp_twd_lookup);
 
 #ifdef CONFIG_DEBUG_FS
-        clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
-        if (cpu_is_u8500ed())
-                clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
-        else
-                clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
+        clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
 #endif
         return 0;
 }
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 5323286b265..18aa5c05c69 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -46,26 +46,6 @@ static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
 };
 
-static struct resource db5500_pmu_resources[] = {
-        [0] = {
-                .start          = IRQ_DB5500_PMU0,
-                .end            = IRQ_DB5500_PMU0,
-                .flags          = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start          = IRQ_DB5500_PMU1,
-                .end            = IRQ_DB5500_PMU1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device db5500_pmu_device = {
-        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
-        .num_resources          = ARRAY_SIZE(db5500_pmu_resources),
-        .resource               = db5500_pmu_resources,
-};
-
 static struct resource mbox0_resources[] = {
         {
                 .name = "mbox_peer",
@@ -151,7 +131,6 @@ static struct platform_device mbox2_device = {
 };
 
 static struct platform_device *db5500_platform_devs[] __initdata = {
-        &db5500_pmu_device,
         &mbox0_device,
         &mbox1_device,
         &mbox2_device,
@@ -192,6 +171,25 @@ void __init u5500_map_io(void)
         _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
 }
 
+static void __init db5500_pmu_init(void)
+{
+        struct resource res[] = {
+                [0] = {
+                        .start          = IRQ_DB5500_PMU0,
+                        .end            = IRQ_DB5500_PMU0,
+                        .flags          = IORESOURCE_IRQ,
+                },
+                [1] = {
+                        .start          = IRQ_DB5500_PMU1,
+                        .end            = IRQ_DB5500_PMU1,
+                        .flags          = IORESOURCE_IRQ,
+                },
+        };
+
+        platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU,
+                                        res, ARRAY_SIZE(res));
+}
+
 static int usb_db5500_rx_dma_cfg[] = {
         DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
         DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
@@ -217,6 +215,7 @@ static int usb_db5500_tx_dma_cfg[] = {
 void __init u5500_init_devices(void)
 {
         db5500_add_gpios();
+        db5500_pmu_init();
         db5500_dma_init();
         db5500_add_rtc();
         db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7f2729c05db..7176ee7491a 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008-2009 ST-Ericsson
+ * Copyright (C) 2008-2009 ST-Ericsson SA
  *
  * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
  *
@@ -53,19 +53,6 @@ static struct map_desc u8500_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
-};
-
-static struct map_desc u8500_ed_io_desc[] __initdata = {
-        __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
-        __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
-};
-
-static struct map_desc u8500_v1_io_desc[] __initdata = {
-        __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
-        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
-};
-
-static struct map_desc u8500_v2_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
 };
 
@@ -80,13 +67,6 @@ void __init u8500_map_io(void)
 
         iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
 
-        if (cpu_is_u8500ed())
-                iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
-        else if (cpu_is_u8500v1())
-                iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
-        else if (cpu_is_u8500v2())
-                iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
-
         _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
 }
 
@@ -155,12 +135,9 @@ static resource_size_t __initdata db8500_gpio_base[] = {
 static void __init db8500_add_gpios(void)
 {
         struct nmk_gpio_platform_data pdata = {
-                /* No custom data yet */
+                .supports_sleepmode = true,
         };
 
-        if (cpu_is_u8500v2())
-                pdata.supports_sleepmode = true;
-
         dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
                          IRQ_DB8500_GPIO0, &pdata);
 }
@@ -192,9 +169,6 @@ static int usb_db8500_tx_dma_cfg[] = {
  */
 void __init u8500_init_devices(void)
 {
-        if (cpu_is_u8500ed())
-                dma40_u8500ed_fixup();
-
         db8500_add_rtc();
         db8500_add_gpios();
         db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 73b17404b19..a7c6cdc9b11 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = {
         .resource = dma40_resources
 };
 
-void dma40_u8500ed_fixup(void)
-{
-        dma40_plat_data.memcpy = NULL;
-        dma40_plat_data.memcpy_len = 0;
-        dma40_resources[0].start = U8500_DMA_BASE_ED;
-        dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
-        dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;
-        dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;
-}
-
 struct resource keypad_resources[] = {
         [0] = {
                 .start = U8500_SKE_BASE,
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index d35122ebc67..15a0f63b2e2 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -65,6 +65,7 @@ static unsigned int partnumber(unsigned int asicid)
  * DB8500v1     0x411fc091      0x9001FFF4              0x008500A0
  * DB8500v1.1   0x411fc091      0x9001FFF4              0x008500A1
  * DB8500v2     0x412fc091      0x9001DBF4              0x008500B0
+ * DB8520v2.2   0x412fc091      0x9001DBF4              0x008500B2
  * DB5500v1     0x412fc091      0x9001FFF4              0x005500A0
  */
 
@@ -80,9 +81,10 @@ void __init ux500_map_io(void)
                 addr = 0x9001FFF4;
                 break;
 
-        case 0x412fc091: /* DB8500v2 / DB5500v1 */
+        case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */
                 asicid = ux500_read_asicid(0x9001DBF4);
-                if (partnumber(asicid) == 0x8500)
+                if (partnumber(asicid) == 0x8500 ||
+                    partnumber(asicid) == 0x8520)
                         /* DB8500v2 */
                         break;
 
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 994b5fe6f85..8e714bcb099 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -65,8 +65,11 @@
 #define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
 #define U5500_MSP1_BASE         (U5500_PER4_BASE + 0x9000)
 #define U5500_GPIO2_BASE        (U5500_PER4_BASE + 0xA000)
+#define U5500_MTIMER_BASE       (U5500_PER4_BASE + 0xC000)
 #define U5500_CDETECT_BASE      (U5500_PER4_BASE + 0xF000)
 #define U5500_PRCMU_TCDM_BASE   (U5500_PER4_BASE + 0x18000)
+#define U5500_PRCMU_TCPM_BASE   (U5500_PER4_BASE + 0x10000)
+#define U5500_TPIU_BASE         (U5500_PER4_BASE + 0x50000)
 
 #define U5500_SPI0_BASE         (U5500_PER5_BASE + 0x0000)
 #define U5500_SPI1_BASE         (U5500_PER5_BASE + 0x1000)
@@ -125,6 +128,7 @@
 #define U5500_ACCCON_BASE               (0xBFFF1000)
 #define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
 #define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
+#define U5500_INTCON_MBOX1_INT_RESET_ADDR       (0xBFFD31A4)
 
 #define U5500_ESRAM_BASE                0x40000000
 #define U5500_ESRAM_DMA_LCPA_OFFSET     0x10000
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 751b0e6938d..80e10f50282 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -22,7 +22,9 @@
 #define U8500_ESRAM_DMA_LCPA_OFFSET     0x10000
 
 #define U8500_DMA_LCPA_BASE    (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
-#define U8500_DMA_LCPA_BASE_ED  (U8500_ESRAM_BANK4 + 0x4000)
+
+/* This address fulfills the 256k alignment requirement of the lcla base */
+#define U8500_DMA_LCLA_BASE     U8500_ESRAM_BANK4
 
 #define U8500_PER3_BASE         0x80000000
 #define U8500_STM_BASE          0x80100000
@@ -40,15 +42,14 @@
 #define U8500_ASIC_ID_BASE      0x9001D000
 
 #define U8500_PER6_BASE         0xa03c0000
+#define U8500_PER7_BASE         0xa03d0000
 #define U8500_PER5_BASE         0xa03e0000
-#define U8500_PER7_BASE_ED      0xa03d0000
 
 #define U8500_SVA_BASE          0xa0100000
 #define U8500_SIA_BASE          0xa0200000
 
 #define U8500_SGA_BASE          0xa0300000
 #define U8500_MCDE_BASE         0xa0350000
-#define U8500_DMA_BASE_ED       0xa0362000
 #define U8500_DMA_BASE          0x801C0000      /* v1 */
 
 #define U8500_SBAG_BASE         0xa0390000
@@ -66,13 +67,6 @@
 #define U8500_GPIO2_BASE        (U8500_PER2_BASE + 0xE000)
 #define U8500_GPIO3_BASE        (U8500_PER5_BASE + 0x1E000)
 
-/* per7 base addresses */
-#define U8500_CR_BASE_ED        (U8500_PER7_BASE_ED + 0x8000)
-#define U8500_MTU0_BASE_ED      (U8500_PER7_BASE_ED + 0xa000)
-#define U8500_MTU1_BASE_ED      (U8500_PER7_BASE_ED + 0xb000)
-#define U8500_TZPC0_BASE_ED     (U8500_PER7_BASE_ED + 0xc000)
-#define U8500_CLKRST7_BASE_ED   (U8500_PER7_BASE_ED + 0xf000)
-
 #define U8500_UART0_BASE        (U8500_PER1_BASE + 0x0000)
 #define U8500_UART1_BASE        (U8500_PER1_BASE + 0x1000)
 
@@ -102,12 +96,10 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
-#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
-#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
-
+#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
+#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
 
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 020b6369a30..5f6cb71fc62 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device;
 extern struct platform_device u8500_dma40_device;
 extern struct platform_device ux500_ske_keypad_device;
 
-void dma40_u8500ed_fixup(void);
-
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 470ac52663d..b6ba26a1367 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -10,20 +10,21 @@
 #ifndef __MACH_HARDWARE_H
 #define __MACH_HARDWARE_H
 
-/* macros to get at IO space when running virtually
+/*
+ * Macros to get at IO space when running virtually
  * We dont map all the peripherals, let ioremap do
  * this for us. We map only very basic peripherals here.
  */
 #define U8500_IO_VIRTUAL        0xf0000000
 #define U8500_IO_PHYSICAL       0xa0000000
 
-/* this macro is used in assembly, so no cast */
+/* This macro is used in assembly, so no cast */
 #define IO_ADDRESS(x)           \
         (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
 
 /* typesafe io address */
 #define __io_address(n)         __io(IO_ADDRESS(n))
-/* used by some plat-nomadik code */
+/* Used by some plat-nomadik code */
 #define io_p2v(n)               __io_address(n)
 
 #include <mach/db8500-regs.h>
@@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE;
 
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
-#endif
-
+#endif                          /* __ASSEMBLY__ */
 #endif                          /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index 02b541a37ee..833d6a6edc9 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -47,6 +47,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void)
 }
 
 /*
+ * 5500 revisions
+ */
+
+static inline bool __attribute_const__ cpu_is_u5500v1(void)
+{
+        return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
+}
+
+static inline bool __attribute_const__ cpu_is_u5500v2(void)
+{
+        return (dbx500_id.revision & 0xf0) == 0xB0;
+}
+
+static inline bool __attribute_const__ cpu_is_u5500v20(void)
+{
+        return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
+}
+
+static inline bool __attribute_const__ cpu_is_u5500v21(void)
+{
+        return cpu_is_u5500() && (dbx500_revision() == 0xB1);
+}
+
+/*
  * 8500 revisions
  */
 
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index 430df1a5978..e62956e1203 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -35,27 +35,6 @@ EXPORT_SYMBOL(pcibios_min_mem);
 unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
 EXPORT_SYMBOL(pci_flags);
 
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len   = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM) {
-                if (flags & IORESOURCE_CACHEABLE)
-                        return ioremap(start, len);
-                return ioremap_nocache(start, len);
-        }
-        return NULL;
-}
-EXPORT_SYMBOL(pci_iomap);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
         if ((unsigned long)addr >= VMALLOC_START &&
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 83cca9bcfc9..1bf0df81bdc 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -131,6 +131,12 @@ extern void imx53_evk_common_init(void);
 extern void imx53_qsb_common_init(void);
 extern void imx53_smd_common_init(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-extern void imx6q_pm_init(void);
 extern void imx6q_clock_map_io(void);
+
+#ifdef CONFIG_PM
+extern void imx6q_pm_init(void);
+#else
+static inline void imx6q_pm_init(void) {}
+#endif
+
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index bf64e1e594e..f0726d48df2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -265,16 +265,20 @@
 #define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__CSPI3_MOSI     IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D3__CSPI3_MISO     IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__CSPI3_SCLK     IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D5__CSPI3_RDY      IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a4d36d601d5..d78298366a9 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -168,7 +168,7 @@ struct cpu_op {
         u32 cpu_rate;
 };
 
-int tzic_enable_wake(int is_idle);
+int tzic_enable_wake(void);
 
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index a3c164c7ba8..98308ec1f32 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -73,7 +73,28 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 #define tzic_set_irq_fiq NULL
 #endif
 
-static unsigned int *wakeup_intr[4];
+#ifdef CONFIG_PM
+static void tzic_irq_suspend(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        int idx = gc->irq_base >> 5;
+
+        __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
+}
+
+static void tzic_irq_resume(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        int idx = gc->irq_base >> 5;
+
+        __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
+                     tzic_base + TZIC_WAKEUP0(idx));
+}
+
+#else
+#define tzic_irq_suspend NULL
+#define tzic_irq_resume NULL
+#endif
 
 static struct mxc_extra_irq tzic_extra_irq = {
 #ifdef CONFIG_FIQ
@@ -91,12 +112,13 @@ static __init void tzic_init_gc(unsigned int irq_start)
                                     handle_level_irq);
         gc->private = &tzic_extra_irq;
         gc->wake_enabled = IRQ_MSK(32);
-        wakeup_intr[idx] = &gc->wake_active;
 
         ct = gc->chip_types;
         ct->chip.irq_mask = irq_gc_mask_disable_reg;
         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
         ct->chip.irq_set_wake = irq_gc_set_wake;
+        ct->chip.irq_suspend = tzic_irq_suspend;
+        ct->chip.irq_resume = tzic_irq_resume;
         ct->regs.disable = TZIC_ENCLEAR0(idx);
         ct->regs.enable = TZIC_ENSET0(idx);
 
@@ -167,23 +189,19 @@ void __init tzic_init_irq(void __iomem *irqbase)
 /**
  * tzic_enable_wake() - enable wakeup interrupt
  *
- * @param is_idle               1 if called in idle loop (ENSET0 register);
- *                              0 to be used when called from low power entry
  * @return                      0 if successful; non-zero otherwise
  */
-int tzic_enable_wake(int is_idle)
+int tzic_enable_wake(void)
 {
-        unsigned int i, v;
+        unsigned int i;
 
         __raw_writel(1, tzic_base + TZIC_DSMINT);
         if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
                 return -EAGAIN;
 
-        for (i = 0; i < 4; i++) {
-                v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
-                        *wakeup_intr[i];
-                __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
-        }
+        for (i = 0; i < 4; i++)
+                __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
+                             tzic_base + TZIC_WAKEUP0(i));
 
         return 0;
 }
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 3df04d944e4..9a584614e7e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
-obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 2ee6341fffd..06383b51e65 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -22,6 +22,8 @@
 #include <plat/vram.h>
 #include <plat/dsp.h>
 
+#include <plat/omap-secure.h>
+
 
 #define NO_LENGTH_CHECK 0xffffffff
 
@@ -66,6 +68,7 @@ void __init omap_reserve(void)
         omapfb_reserve_sdram_memblock();
         omap_vram_reserve_sdram_memblock();
         omap_dsp_reserve_sdram_memblock();
+        omap_secure_ram_reserve_memblock();
 }
 
 void __init omap_init_consistent_dma_size(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c22217c2ee5..002fb4d96bb 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1034,6 +1034,18 @@ dma_addr_t omap_get_dma_src_pos(int lch)
         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
                 offset = p->dma_read(CSAC, lch);
 
+        if (!cpu_is_omap15xx()) {
+                /*
+                 * CDAC == 0 indicates that the DMA transfer on the channel has
+                 * not been started (no data has been transferred so far).
+                 * Return the programmed source start address in this case.
+                 */
+                if (likely(p->dma_read(CDAC, lch)))
+                        offset = p->dma_read(CSAC, lch);
+                else
+                        offset = p->dma_read(CSSA, lch);
+        }
+
         if (cpu_class_is_omap1())
                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 
@@ -1062,8 +1074,16 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
          * read before the DMA controller finished disabling the channel.
          */
-        if (!cpu_is_omap15xx() && offset == 0)
+        if (!cpu_is_omap15xx() && offset == 0) {
                 offset = p->dma_read(CDAC, lch);
+                /*
+                 * CDAC == 0 indicates that the DMA transfer on the channel has
+                 * not been started (no data has been transferred so far).
+                 * Return the programmed destination start address in this case.
+                 */
+                if (unlikely(!offset))
+                        offset = p->dma_read(CDSA, lch);
+        }
 
         if (cpu_class_is_omap1())
                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
new file mode 100644
index 00000000000..06c19bb7bca
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/am33xx.h
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE     0x48000000
+
+#define AM33XX_SCM_BASE         0x44E10000
+#define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE        0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 387a9638991..b299b8d201c 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -40,6 +40,7 @@ struct omap_clk {
 #define CK_443X         (1 << 11)
 #define CK_TI816X       (1 << 12)
 #define CK_446X         (1 << 13)
+#define CK_1710         (1 << 15)       /* 1710 extra for rate selection */
 
 
 #define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index eb73ab40e95..240a7b9fd94 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -59,6 +59,8 @@ struct clkops {
 #define RATE_IN_4430            (1 << 5)
 #define RATE_IN_TI816X          (1 << 6)
 #define RATE_IN_4460            (1 << 7)
+#define RATE_IN_AM33XX          (1 << 8)
+#define RATE_IN_TI814X          (1 << 9)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -84,7 +86,7 @@ struct clkops {
 struct clksel_rate {
         u32                     val;
         u8                      div;
-        u8                      flags;
+        u16                     flags;
 };
 
 /**
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 408a12f7920..6b51086fce1 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -69,6 +69,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap343x():   True for OMAP3430
  * cpu_is_omap443x():   True for OMAP4430
  * cpu_is_omap446x():   True for OMAP4460
+ * cpu_is_omap447x():   True for OMAP4470
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -78,6 +79,22 @@ static inline int is_omap ##class (void)		\
         return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
 
+#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
+
+#define IS_AM_CLASS(class, id)                          \
+static inline int is_am ##class (void)                  \
+{                                                       \
+        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
+}
+
+#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
+
+#define IS_TI_CLASS(class, id)                  \
+static inline int is_ti ##class (void)          \
+{                                                       \
+        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
+}
+
 #define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
 
 #define IS_OMAP_SUBCLASS(subclass, id)                  \
@@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void)		\
         return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
 }
 
+#define IS_AM_SUBCLASS(subclass, id)                    \
+static inline int is_am ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
+IS_AM_CLASS(33xx, 0x33)
+
+IS_TI_CLASS(81xx, 0x81)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
@@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
+IS_OMAP_SUBCLASS(447x, 0x447)
 
 IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
+IS_AM_SUBCLASS(335x, 0x335)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_ti81xx()                 0
 #define cpu_is_ti816x()                 0
+#define cpu_is_ti814x()                 0
+#define cpu_is_am33xx()                 0
+#define cpu_is_am335x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
+#define cpu_is_omap447x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3530
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
+# undef cpu_is_ti81xx
 # undef cpu_is_ti816x
+# undef cpu_is_ti814x
+# undef cpu_is_am33xx
+# undef cpu_is_am335x
 # define cpu_is_omap3430()              is_omap3430()
 # define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
                                                 (!omap3_has_iva()) &&   \
@@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                 !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti81xx()                is_ti81xx()
 # define cpu_is_ti816x()                is_ti816x()
+# define cpu_is_ti814x()                is_ti814x()
+# define cpu_is_am33xx()                is_am33xx()
+# define cpu_is_am335x()                is_am335x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
 # undef cpu_is_omap446x
+# undef cpu_is_omap447x
 # define cpu_is_omap44xx()              is_omap44xx()
 # define cpu_is_omap443x()              is_omap443x()
 # define cpu_is_omap446x()              is_omap446x()
+# define cpu_is_omap447x()              is_omap447x()
 # endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -386,15 +430,27 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
 
+#define TI814X_CLASS            0x81400034
+#define TI8148_REV_ES1_0        TI814X_CLASS
+#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
+
+#define AM335X_CLASS            0x33500034
+#define AM335X_REV_ES1_0        AM335X_CLASS
+
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
 #define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
 #define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
+#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
 
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
 
+#define OMAP447X_CLASS          0x44700044
+#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
+
 void omap2_check_revision(void);
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e87efe1499b..e897978371c 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,6 +286,7 @@
 #include <plat/omap24xx.h>
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
-#include <plat/ti816x.h>
+#include <plat/ti81xx.h>
+#include <plat/am33xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 1234944a4da..0696bae1818 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET      0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
 
+#define AM33XX_L4_WK_IO_OFFSET  0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)     IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
+
 #define OMAP4_L3_PER_IO_OFFSET  0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
 
@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
+ * ----------------------------------------------------------------------------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L4_WK_AM33XX_PHYS       L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT       (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+#define L4_WK_AM33XX_SIZE       SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+
+/*
  * Need to look at the Size 4M for L4.
  * VPOM3430 was not working for Int controller
  */
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index a1d79ee1925..88be3e628b3 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -111,6 +111,32 @@ struct iommu_platform_data {
         u32 da_end;
 };
 
+/**
+ * struct iommu_arch_data - omap iommu private data
+ * @name: name of the iommu device
+ * @iommu_dev: handle of the iommu device
+ *
+ * This is an omap iommu private data object, which binds an iommu user
+ * to its iommu device. This object should be placed at the iommu user's
+ * dev_archdata so generic IOMMU API can be used without having to
+ * utilize omap-specific plumbing anymore.
+ */
+struct omap_iommu_arch_data {
+        const char *name;
+        struct omap_iommu *iommu_dev;
+};
+
+/**
+ * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
+ * @dev: iommu client device
+ */
+static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
+{
+        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
+
+        return arch_data->iommu_dev;
+}
+
 /* IOMMU errors */
 #define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
 #define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
@@ -163,8 +189,8 @@ extern int omap_iommu_set_isr(const char *name,
                                     void *priv),
                          void *isr_priv);
 
-extern void omap_iommu_save_ctx(struct omap_iommu *obj);
-extern void omap_iommu_restore_ctx(struct omap_iommu *obj);
+extern void omap_iommu_save_ctx(struct device *dev);
+extern void omap_iommu_restore_ctx(struct device *dev);
 
 extern int omap_install_iommu_arch(const struct iommu_functions *ops);
 extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
@@ -176,6 +202,5 @@ extern ssize_t
 omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
 extern size_t
 omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
-struct device *omap_find_iommu_device(const char *name);
 
 #endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index 6af1a91c0f3..498e57cda6c 100644
--- a/arch/arm/plat-omap/include/plat/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
@@ -72,18 +72,18 @@ struct iovm_struct {
 #define IOVMF_DA_FIXED          (1 << (4 + IOVMF_SW_SHIFT))
 
 
-extern struct iovm_struct *omap_find_iovm_area(struct omap_iommu *obj, u32 da);
+extern struct iovm_struct *omap_find_iovm_area(struct device *dev, u32 da);
 extern u32
-omap_iommu_vmap(struct iommu_domain *domain, struct omap_iommu *obj, u32 da,
+omap_iommu_vmap(struct iommu_domain *domain, struct device *dev, u32 da,
                         const struct sg_table *sgt, u32 flags);
 extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain,
-                                struct omap_iommu *obj, u32 da);
+                                struct device *dev, u32 da);
 extern u32
-omap_iommu_vmalloc(struct iommu_domain *domain, struct omap_iommu *obj,
+omap_iommu_vmalloc(struct iommu_domain *domain, struct device *dev,
                                 u32 da, size_t bytes, u32 flags);
 extern void
-omap_iommu_vfree(struct iommu_domain *domain, struct omap_iommu *obj,
+omap_iommu_vfree(struct iommu_domain *domain, struct device *dev,
                                 const u32 da);
-extern void *omap_da_to_va(struct omap_iommu *obj, u32 da);
+extern void *omap_da_to_va(struct device *dev, u32 da);
 
 #endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index ebda7382c65..2efd6454bce 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -357,7 +357,7 @@
 #define INT_35XX_EMAC_C0_TX_PULSE_IRQ   69
 #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
 #define INT_35XX_USBOTG_IRQ             71
-#define INT_35XX_UART4                  84
+#define INT_35XX_UART4_IRQ              84
 #define INT_35XX_CCDC_VD0_IRQ           88
 #define INT_35XX_CCDC_VD1_IRQ           92
 #define INT_35XX_CCDC_VD2_IRQ           93
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 94cf70afb23..f75946c3293 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -96,6 +96,7 @@ struct omap_mmc_platform_data {
                  */
                 u8  wires;      /* Used for the MMC driver on omap1 and 2420 */
                 u32 caps;       /* Used for the MMC driver on 2430 and later */
+                u32 pm_caps;    /* PM capabilities of the mmc */
 
                 /*
                  * nomux means "standard" muxing is wrong on this board, and
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
new file mode 100644
index 00000000000..64f9d1c7f1b
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -0,0 +1,13 @@
+#ifndef __OMAP_SECURE_H__
+#define __OMAP_SECURE_H__
+
+#include <linux/types.h>
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
+extern int omap_secure_ram_reserve_memblock(void);
+#else
+static inline void omap_secure_ram_reserve_memblock(void)
+{ }
+#endif
+
+#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 2682043f5a5..9ff444469f3 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -19,6 +19,7 @@
 
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/pm_qos.h>
 
 #include <plat/mux.h>
 
@@ -33,6 +34,8 @@
 
 #define OMAP_MODE13X_SPEED      230400
 
+#define OMAP_UART_SCR_TX_EMPTY  0x08
+
 /* WER = 0x7F
  * Enable module level wakeup in WER reg
  */
@@ -51,18 +54,27 @@
 
 #define OMAP_UART_DMA_CH_FREE   -1
 
-#define RX_TIMEOUT              (3 * HZ)
 #define OMAP_MAX_HSUART_PORTS   4
 
 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
 
+#define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
+#define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
+
 struct omap_uart_port_info {
         bool                    dma_enabled;    /* To specify DMA Mode */
         unsigned int            uartclk;        /* UART clock rate */
-        void __iomem            *membase;       /* ioremap cookie or NULL */
-        resource_size_t         mapbase;        /* resource base */
-        unsigned long           irqflags;       /* request_irq flags */
         upf_t                   flags;          /* UPF_* flags */
+        u32                     errata;
+        unsigned int            dma_rx_buf_size;
+        unsigned int            dma_rx_timeout;
+        unsigned int            autosuspend_timeout;
+        unsigned int            dma_rx_poll_rate;
+
+        int (*get_context_loss_count)(struct device *);
+        void (*set_forceidle)(struct platform_device *);
+        void (*set_noidle)(struct platform_device *);
+        void (*enable_wakeup)(struct platform_device *, bool);
 };
 
 struct uart_omap_dma {
@@ -86,8 +98,9 @@ struct uart_omap_dma {
         spinlock_t              rx_lock;
         /* timer to poll activity on rx dma */
         struct timer_list       rx_timer;
-        int                     rx_buf_size;
-        int                     rx_timeout;
+        unsigned int            rx_buf_size;
+        unsigned int            rx_poll_rate;
+        unsigned int            rx_timeout;
 };
 
 struct uart_omap_port {
@@ -100,6 +113,10 @@ struct uart_omap_port {
         unsigned char           mcr;
         unsigned char           fcr;
         unsigned char           efr;
+        unsigned char           dll;
+        unsigned char           dlh;
+        unsigned char           mdr1;
+        unsigned char           scr;
 
         int                     use_dma;
         /*
@@ -111,6 +128,14 @@ struct uart_omap_port {
         unsigned char           msr_saved_flags;
         char                    name[20];
         unsigned long           port_activity;
+        u32                     context_loss_cnt;
+        u32                     errata;
+        u8                      wakeups_enabled;
+
+        struct pm_qos_request   pm_qos_request;
+        u32                     latency;
+        u32                     calc_latency;
+        struct work_struct      qos_work;
 };
 
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index b9e85886b9d..0d818acf391 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE        0x54000000
 #define L3_34XX_BASE            0x68000000
 
+#define L4_WK_AM33XX_BASE       0x44C00000
+
 #define OMAP3430_32KSYNCT_BASE  0x48320000
 #define OMAP3430_CM_BASE        0x48004800
 #define OMAP3430_PRM_BASE       0x48306800
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index ea2b8a6306e..c0d478e55c8 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -45,6 +45,7 @@
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
 #define OMAP44XX_MCPDM_BASE             0x40132000
 #define OMAP44XX_MCPDM_L3_BASE          0x49032000
+#define OMAP44XX_SAR_RAM_BASE           0x4a326000
 
 #define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
 #define OMAP44XX_HSUSB_OTG_BASE         (L4_44XX_BASE + 0xAB000)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8b372ede17c..647010109af 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -97,6 +97,7 @@ struct omap_hwmod_mux_info {
         struct omap_device_pad          *pads;
         int                             nr_pads_dynamic;
         struct omap_device_pad          **pads_dynamic;
+        int                             *irqs;
         bool                            enabled;
 };
 
@@ -416,10 +417,13 @@ struct omap_hwmod_omap4_prcm {
  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
  * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
+ * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
+ *     causes the first call to _enable() to only update the pinmux
  */
 #define _HWMOD_NO_MPU_PORT                      (1 << 0)
 #define _HWMOD_WAKEUP_ENABLED                   (1 << 1)
 #define _HWMOD_SYSCONFIG_LOADED                 (1 << 2)
+#define _HWMOD_SKIP_ENABLE                      (1 << 3)
 
 /*
  * omap_hwmod._state definitions
@@ -604,6 +608,8 @@ int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
 
 int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
 
+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index ac44bde5d36..198d1e6a4a6 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -44,6 +44,7 @@
 #define OMAP3_UART2_BASE        OMAP2_UART2_BASE
 #define OMAP3_UART3_BASE        0x49020000
 #define OMAP3_UART4_BASE        0x49042000      /* Only on 36xx */
+#define OMAP3_UART4_AM35XX_BASE 0x4809E000      /* Only on AM35xx */
 
 /* OMAP4 serial ports */
 #define OMAP4_UART1_BASE        OMAP2_UART1_BASE
@@ -51,10 +52,10 @@
 #define OMAP4_UART3_BASE        0x48020000
 #define OMAP4_UART4_BASE        0x4806e000
 
-/* TI816X serial ports */
-#define TI816X_UART1_BASE       0x48020000
-#define TI816X_UART2_BASE       0x48022000
-#define TI816X_UART3_BASE       0x48024000
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE       0x48020000
+#define TI81XX_UART2_BASE       0x48022000
+#define TI81XX_UART3_BASE       0x48024000
 
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
@@ -89,9 +90,9 @@
 #define OMAP4UART2              OMAP2UART2
 #define OMAP4UART3              43
 #define OMAP4UART4              44
-#define TI816XUART1             81
-#define TI816XUART2             82
-#define TI816XUART3             83
+#define TI81XXUART1             81
+#define TI81XXUART2             82
+#define TI81XXUART3             83
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
@@ -106,15 +107,13 @@
 #ifndef __ASSEMBLER__
 
 struct omap_board_data;
+struct omap_uart_port_info;
 
 extern void omap_serial_init(void);
-extern void omap_serial_init_port(struct omap_board_data *bdata);
 extern int omap_uart_can_sleep(void);
-extern void omap_uart_check_wakeup(void);
-extern void omap_uart_prepare_suspend(void);
-extern void omap_uart_prepare_idle(int num);
-extern void omap_uart_resume_idle(int num);
-extern void omap_uart_enable_irqs(int enable);
+extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
+extern void omap_serial_init_port(struct omap_board_data *bdata,
+                struct omap_uart_port_info *platform_data);
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index f500fc34d06..75aa1b2bef5 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -95,6 +95,10 @@ static inline void omap_push_sram_idle(void) {}
  */
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP3_SRAM_PA           0x40200000
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PA           0x40304000
+#define OMAP4_SRAM_VA           0xfe404000
+#else
 #define OMAP4_SRAM_PA           0x40300000
-
+#endif
 #endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h
index 50510f5dda1..8f9843f7842 100644
--- a/arch/arm/plat-omap/include/plat/ti816x.h
+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
@@ -1,5 +1,5 @@
 /*
- * This file contains the address data for various TI816X modules.
+ * This file contains the address data for various TI81XX modules.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
  *
@@ -13,15 +13,15 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __ASM_ARCH_TI816X_H
-#define __ASM_ARCH_TI816X_H
+#ifndef __ASM_ARCH_TI81XX_H
+#define __ASM_ARCH_TI81XX_H
 
-#define L4_SLOW_TI816X_BASE     0x48000000
+#define L4_SLOW_TI81XX_BASE     0x48000000
 
-#define TI816X_SCM_BASE         0x48140000
-#define TI816X_CTRL_BASE        TI816X_SCM_BASE
-#define TI816X_PRCM_BASE        0x48180000
+#define TI81XX_SCM_BASE         0x48140000
+#define TI81XX_CTRL_BASE        TI81XX_SCM_BASE
+#define TI81XX_PRCM_BASE        0x48180000
 
-#define TI816X_ARM_INTC_BASE    0x48200000
+#define TI81XX_ARM_INTC_BASE    0x48200000
 
-#endif /* __ASM_ARCH_TI816X_H */
+#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 2f472e989ec..6ee90495ca4 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -99,9 +99,9 @@ static inline void flush(void)
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
 
-#define DEBUG_LL_TI816X(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI816XUART##p)
+#define DEBUG_LL_TI81XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI81XXUART##p)
 
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -177,7 +177,10 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_ZOOM(omap_zoom3);
 
                 /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI816X(3, ti8168evm);
+                DEBUG_LL_TI81XX(3, ti8168evm);
+
+                /* TI8148 base boards using UART1 */
+                DEBUG_LL_TI81XX(1, ti8148evm);
 
         } while (0);
 }
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 17d3c939775..dc864b580da 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -100,9 +100,6 @@ extern void usb_musb_init(struct omap_musb_board_data *board_data);
 
 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
 
-extern int omap_usbhs_enable(struct device *dev);
-extern void omap_usbhs_disable(struct device *dev);
-
 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 extern int omap4430_phy_set_clk(struct device *dev, int on);
 extern int omap4430_phy_init(struct device *dev);
@@ -114,6 +111,7 @@ extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
 extern void am35x_musb_clear_irq(void);
 extern void am35x_set_mode(u8 musb_mode);
+extern void ti81xx_musb_phy_power(u8 on);
 
 /*
  * FIXME correct answer depends on hmc_mode,
@@ -273,6 +271,37 @@ static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
 #define CONF2_OTGPWRDN          (1 << 2)
 #define CONF2_DATPOL            (1 << 1)
 
+/* TI81XX specific definitions */
+#define USBCTRL0        0x620
+#define USBSTAT0        0x624
+
+/* TI816X PHY controls bits */
+#define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
+#define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
+
+/* TI814X PHY controls bits */
+#define USBPHY_CM_PWRDN         (1 << 0)
+#define USBPHY_OTG_PWRDN        (1 << 1)
+#define USBPHY_CHGDET_DIS       (1 << 2)
+#define USBPHY_CHGDET_RSTRT     (1 << 3)
+#define USBPHY_SRCONDM          (1 << 4)
+#define USBPHY_SINKONDP         (1 << 5)
+#define USBPHY_CHGISINK_EN      (1 << 6)
+#define USBPHY_CHGVSRC_EN       (1 << 7)
+#define USBPHY_DMPULLUP         (1 << 8)
+#define USBPHY_DPPULLUP         (1 << 9)
+#define USBPHY_CDET_EXTCTL      (1 << 10)
+#define USBPHY_GPIO_MODE        (1 << 12)
+#define USBPHY_DPOPBUFCTL       (1 << 13)
+#define USBPHY_DMOPBUFCTL       (1 << 14)
+#define USBPHY_DPINPUT          (1 << 15)
+#define USBPHY_DMINPUT          (1 << 16)
+#define USBPHY_DPGPIO_PD        (1 << 17)
+#define USBPHY_DMGPIO_PD        (1 << 18)
+#define USBPHY_OTGVDET_EN       (1 << 19)
+#define USBPHY_OTGSESSEND_EN    (1 << 20)
+#define USBPHY_DATA_POLARITY    (1 << 23)
+
 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
 u32 omap1_usb1_init(unsigned nwires);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 8b28664d1c6..4243bdcc87b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -40,7 +40,11 @@
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
+#else
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#endif
 
 #if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -141,11 +145,9 @@ static void __init omap_detect_sram(void)
                         omap_sram_size = 0x32000;       /* 200K */
                 else if (cpu_is_omap15xx())
                         omap_sram_size = 0x30000;       /* 192K */
-                else if (cpu_is_omap1610() || cpu_is_omap1621() ||
-                     cpu_is_omap1710())
+                else if (cpu_is_omap1610() || cpu_is_omap1611() ||
+                                cpu_is_omap1621() || cpu_is_omap1710())
                         omap_sram_size = 0x4000;        /* 16K */
-                else if (cpu_is_omap1611())
-                        omap_sram_size = SZ_256K;
                 else {
                         pr_err("Could not detect SRAM size\n");
                         omap_sram_size = 0x4000;
@@ -163,6 +165,10 @@ static void __init omap_map_sram(void)
         if (omap_sram_size == 0)
                 return;
 
+#ifdef CONFIG_OMAP4_ERRATA_I688
+                omap_sram_start += PAGE_SIZE;
+                omap_sram_size -= SZ_16K;
+#endif
         if (cpu_is_omap34xx()) {
                 /*
                  * SRAM must be marked as non-cached on OMAP3 since the
@@ -224,6 +230,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 {
         BUG_ON(!_omap_sram_reprogram_clock);
+        /* On 730, bit 13 must always be 1 */
+        if (cpu_is_omap7xx())
+                ckctl |= 0x2000;
         _omap_sram_reprogram_clock(dpllctl, ckctl);
 }
 
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 95a5fc53b6d..c20ce0f5ce3 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y   := irq.o pcie.o time.o common.o mpp.o
+obj-y   := irq.o pcie.o time.o common.o mpp.o addr-map.o
 obj-m   :=
 obj-n   :=
 obj-    :=
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
new file mode 100644
index 00000000000..367ca89ac40
--- /dev/null
+++ b/arch/arm/plat-orion/addr-map.c
@@ -0,0 +1,174 @@
+/*
+ * arch/arm/plat-orion/addr-map.c
+ *
+ * Address map functions for Marvell Orion based SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <plat/addr-map.h>
+
+struct mbus_dram_target_info orion_mbus_dram_info;
+
+const struct mbus_dram_target_info *mv_mbus_dram_info(void)
+{
+        return &orion_mbus_dram_info;
+}
+EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
+
+/*
+ * DDR target is the same on all Orion platforms.
+ */
+#define TARGET_DDR              0
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN_CTRL_OFF            0x0000
+#define WIN_BASE_OFF            0x0004
+#define WIN_REMAP_LO_OFF        0x0008
+#define WIN_REMAP_HI_OFF        0x000c
+
+/*
+ * Default implementation
+ */
+static void __init __iomem *
+orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+        return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+}
+
+/*
+ * Default implementation
+ */
+static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
+                                          const int win)
+{
+        if (win < cfg->remappable_wins)
+                return 1;
+
+        return 0;
+}
+
+void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
+                                const int win, const u32 base,
+                                const u32 size, const u8 target,
+                                const u8 attr, const int remap)
+{
+        void __iomem *addr = cfg->win_cfg_base(cfg, win);
+        u32 ctrl, base_high, remap_addr;
+
+        if (win >= cfg->num_wins) {
+                printk(KERN_ERR "setup_cpu_win: trying to allocate window "
+                       "%d when only %d allowed\n", win, cfg->num_wins);
+        }
+
+        base_high = base & 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+
+        writel(base_high, addr + WIN_BASE_OFF);
+        writel(ctrl, addr + WIN_CTRL_OFF);
+        if (cfg->cpu_win_can_remap(cfg, win)) {
+                if (remap < 0)
+                        remap_addr = base;
+                else
+                        remap_addr = remap;
+                writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
+                writel(0, addr + WIN_REMAP_HI_OFF);
+        }
+}
+
+/*
+ * Configure a number of windows.
+ */
+static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
+                                        const struct orion_addr_map_info *info)
+{
+        while (info->win != -1) {
+                orion_setup_cpu_win(cfg, info->win, info->base, info->size,
+                                    info->target, info->attr, info->remap);
+                info++;
+        }
+}
+
+static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
+{
+        void __iomem *addr;
+        int i;
+
+        for (i = 0; i < cfg->num_wins; i++) {
+                addr = cfg->win_cfg_base(cfg, i);
+
+                writel(0, addr + WIN_BASE_OFF);
+                writel(0, addr + WIN_CTRL_OFF);
+                if (cfg->cpu_win_can_remap(cfg, i)) {
+                        writel(0, addr + WIN_REMAP_LO_OFF);
+                        writel(0, addr + WIN_REMAP_HI_OFF);
+                }
+        }
+}
+
+/*
+ * Disable, clear and configure windows.
+ */
+void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
+                              const struct orion_addr_map_info *info)
+{
+        if (!cfg->cpu_win_can_remap)
+                cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
+
+        if (!cfg->win_cfg_base)
+                cfg->win_cfg_base = orion_win_cfg_base;
+
+        orion_disable_wins(cfg);
+
+        if (info)
+                orion_setup_cpu_wins(cfg, info);
+}
+
+/*
+ * Setup MBUS dram target info.
+ */
+void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
+                                        const u32 ddr_window_cpu_base)
+{
+        void __iomem *addr;
+        int i;
+        int cs;
+
+        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        addr = (void __iomem *)ddr_window_cpu_base;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
+                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &orion_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        orion_mbus_dram_info.num_cs = cs;
+}
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 9e5451b3c8e..e5a2fde29b1 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -13,7 +13,6 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
@@ -203,13 +202,12 @@ void __init orion_rtc_init(unsigned long mapbase,
  ****************************************************************************/
 static __init void ge_complete(
         struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
-        struct mbus_dram_target_info *mbus_dram_info, int tclk,
+        int tclk,
         struct resource *orion_ge_resource, unsigned long irq,
         struct platform_device *orion_ge_shared,
         struct mv643xx_eth_platform_data *eth_data,
         struct platform_device *orion_ge)
 {
-        orion_ge_shared_data->dram = mbus_dram_info;
         orion_ge_shared_data->t_clk = tclk;
         orion_ge_resource->start = irq;
         orion_ge_resource->end = irq;
@@ -259,7 +257,6 @@ static struct platform_device orion_ge00 = {
 };
 
 void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
@@ -267,7 +264,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
 {
         fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
                        mapbase + 0x2000, SZ_16K - 1, irq_err);
-        ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
+        ge_complete(&orion_ge00_shared_data, tclk,
                     orion_ge00_resources, irq, &orion_ge00_shared,
                     eth_data, &orion_ge00);
 }
@@ -313,7 +310,6 @@ static struct platform_device orion_ge01 = {
 };
 
 void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
@@ -321,7 +317,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
 {
         fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
                        mapbase + 0x2000, SZ_16K - 1, irq_err);
-        ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
+        ge_complete(&orion_ge01_shared_data, tclk,
                     orion_ge01_resources, irq, &orion_ge01_shared,
                     eth_data, &orion_ge01);
 }
@@ -367,7 +363,6 @@ static struct platform_device orion_ge10 = {
 };
 
 void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
@@ -375,7 +370,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
 {
         fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
                        mapbase + 0x2000, SZ_16K - 1, irq_err);
-        ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
+        ge_complete(&orion_ge10_shared_data, tclk,
                     orion_ge10_resources, irq, &orion_ge10_shared,
                     eth_data, &orion_ge10);
 }
@@ -421,7 +416,6 @@ static struct platform_device orion_ge11 = {
 };
 
 void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
@@ -429,7 +423,7 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
 {
         fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
                        mapbase + 0x2000, SZ_16K - 1, irq_err);
-        ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
+        ge_complete(&orion_ge11_shared_data, tclk,
                     orion_ge11_resources, irq, &orion_ge11_shared,
                     eth_data, &orion_ge11);
 }
@@ -592,8 +586,6 @@ void __init orion_wdt_init(unsigned long tclk)
 /*****************************************************************************
  * XOR
  ****************************************************************************/
-static struct mv_xor_platform_shared_data orion_xor_shared_data;
-
 static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
 
 void __init orion_xor_init_channels(
@@ -632,9 +624,6 @@ static struct resource orion_xor0_shared_resources[] = {
 static struct platform_device orion_xor0_shared = {
         .name           = MV_XOR_SHARED_NAME,
         .id             = 0,
-        .dev            = {
-                .platform_data = &orion_xor_shared_data,
-        },
         .num_resources  = ARRAY_SIZE(orion_xor0_shared_resources),
         .resource       = orion_xor0_shared_resources,
 };
@@ -687,14 +676,11 @@ static struct platform_device orion_xor01_channel = {
         },
 };
 
-void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
-                            unsigned long mapbase_low,
+void __init orion_xor0_init(unsigned long mapbase_low,
                             unsigned long mapbase_high,
                             unsigned long irq_0,
                             unsigned long irq_1)
 {
-        orion_xor_shared_data.dram = mbus_dram_info;
-
         orion_xor0_shared_resources[0].start = mapbase_low;
         orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
         orion_xor0_shared_resources[1].start = mapbase_high;
@@ -727,9 +713,6 @@ static struct resource orion_xor1_shared_resources[] = {
 static struct platform_device orion_xor1_shared = {
         .name           = MV_XOR_SHARED_NAME,
         .id             = 1,
-        .dev            = {
-                .platform_data = &orion_xor_shared_data,
-        },
         .num_resources  = ARRAY_SIZE(orion_xor1_shared_resources),
         .resource       = orion_xor1_shared_resources,
 };
@@ -828,11 +811,9 @@ static struct platform_device orion_ehci = {
         },
 };
 
-void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
-                            unsigned long mapbase,
+void __init orion_ehci_init(unsigned long mapbase,
                             unsigned long irq)
 {
-        orion_ehci_data.dram = mbus_dram_info;
         fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
                        irq);
 
@@ -854,11 +835,9 @@ static struct platform_device orion_ehci_1 = {
         },
 };
 
-void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
-                              unsigned long mapbase,
+void __init orion_ehci_1_init(unsigned long mapbase,
                               unsigned long irq)
 {
-        orion_ehci_data.dram = mbus_dram_info;
         fill_resources(&orion_ehci_1, orion_ehci_1_resources,
                        mapbase, SZ_4K - 1, irq);
 
@@ -880,11 +859,9 @@ static struct platform_device orion_ehci_2 = {
         },
 };
 
-void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
-                              unsigned long mapbase,
+void __init orion_ehci_2_init(unsigned long mapbase,
                               unsigned long irq)
 {
-        orion_ehci_data.dram = mbus_dram_info;
         fill_resources(&orion_ehci_2, orion_ehci_2_resources,
                        mapbase, SZ_4K - 1, irq);
 
@@ -911,11 +888,9 @@ static struct platform_device orion_sata = {
 };
 
 void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq)
 {
-        sata_data->dram = mbus_dram_info;
         orion_sata.dev.platform_data = sata_data;
         fill_resources(&orion_sata, orion_sata_resources,
                        mapbase, 0x5000 - 1, irq);
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
new file mode 100644
index 00000000000..fd556f77562
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/plat-orion/include/plat/addr-map.h
+ *
+ * Marvell Orion SoC address map handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_ADDR_MAP_H
+#define __PLAT_ADDR_MAP_H
+
+extern struct mbus_dram_target_info orion_mbus_dram_info;
+
+struct orion_addr_map_cfg {
+        const int num_wins;     /* Total number of windows */
+        const int remappable_wins;
+        const u32 bridge_virt_base;
+
+        /* If NULL, the default cpu_win_can_remap will be used, using
+           the value in remappable_wins */
+        int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
+                                  const int win);
+        /* If NULL, the default win_cfg_base will be used, using the
+           value in bridge_virt_base */
+        void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
+                                 const int win);
+};
+
+/*
+ * Information needed to setup one address mapping.
+ */
+struct orion_addr_map_info {
+        const int win;
+        const u32 base;
+        const u32 size;
+        const u8 target;
+        const u8 attr;
+        const int remap;
+};
+
+void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
+                              const struct orion_addr_map_info *info);
+
+void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
+                                const int win, const u32 base,
+                                const u32 size, const u8 target,
+                                const u8 attr, const int remap);
+
+void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
+                                        const u32 ddr_window_cpu_base);
+#endif
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 9cf1f781329..885f8abd927 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -1,11 +1,8 @@
 #ifndef __PLAT_AUDIO_H
 #define __PLAT_AUDIO_H
 
-#include <linux/mbus.h>
-
 struct kirkwood_asoc_platform_data {
         u32 tclk;
-        struct mbus_dram_target_info *dram;
         int burst;
 };
 #endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index a63c357e2ab..0fe08d77e83 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -37,28 +37,24 @@ void __init orion_rtc_init(unsigned long mapbase,
                            unsigned long irq);
 
 void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
                             int tclk);
 
 void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
                             int tclk);
 
 void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
                             int tclk);
 
 void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq,
                             unsigned long irq_err,
@@ -82,8 +78,7 @@ void __init orion_spi_1_init(unsigned long mapbase,
 
 void __init orion_wdt_init(unsigned long tclk);
 
-void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
-                            unsigned long mapbase_low,
+void __init orion_xor0_init(unsigned long mapbase_low,
                             unsigned long mapbase_high,
                             unsigned long irq_0,
                             unsigned long irq_1);
@@ -93,20 +88,16 @@ void __init orion_xor1_init(unsigned long mapbase_low,
                             unsigned long irq_0,
                             unsigned long irq_1);
 
-void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
-                            unsigned long mapbase,
+void __init orion_ehci_init(unsigned long mapbase,
                             unsigned long irq);
 
-void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
-                              unsigned long mapbase,
+void __init orion_ehci_1_init(unsigned long mapbase,
                               unsigned long irq);
 
-void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
-                              unsigned long mapbase,
+void __init orion_ehci_2_init(unsigned long mapbase,
                               unsigned long irq);
 
 void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
-                            struct mbus_dram_target_info *mbus_dram_info,
                             unsigned long mapbase,
                             unsigned long irq);
 
diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h
index 4ec668e7746..6fc78e43042 100644
--- a/arch/arm/plat-orion/include/plat/ehci-orion.h
+++ b/arch/arm/plat-orion/include/plat/ehci-orion.h
@@ -19,7 +19,6 @@ enum orion_ehci_phy_ver {
 };
 
 struct orion_ehci_data {
-        struct mbus_dram_target_info    *dram;
         enum orion_ehci_phy_ver phy_version;
 };
 
diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h
index bd5f3bdb4ae..2ba1f7d76ee 100644
--- a/arch/arm/plat-orion/include/plat/mv_xor.h
+++ b/arch/arm/plat-orion/include/plat/mv_xor.h
@@ -13,12 +13,6 @@
 #define MV_XOR_SHARED_NAME      "mv_xor_shared"
 #define MV_XOR_NAME             "mv_xor"
 
-struct mbus_dram_target_info;
-
-struct mv_xor_platform_shared_data {
-        struct mbus_dram_target_info    *dram;
-};
-
 struct mv_xor_platform_data {
         struct platform_device          *shared;
         int                             hw_id;
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h
index 14ca8867600..1190efedcb9 100644
--- a/arch/arm/plat-orion/include/plat/mvsdio.h
+++ b/arch/arm/plat-orion/include/plat/mvsdio.h
@@ -12,7 +12,6 @@
 #include <linux/mbus.h>
 
 struct mvsdio_platform_data {
-        struct mbus_dram_target_info *dram;
         unsigned int clock;
         int gpio_card_detect;
         int gpio_write_protect;
diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h
index cc99163e73f..fe5b9e86274 100644
--- a/arch/arm/plat-orion/include/plat/pcie.h
+++ b/arch/arm/plat-orion/include/plat/pcie.h
@@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base);
 int orion_pcie_get_local_bus_nr(void __iomem *base);
 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
 void orion_pcie_reset(void __iomem *base);
-void orion_pcie_setup(void __iomem *base,
-                      struct mbus_dram_target_info *dram);
+void orion_pcie_setup(void __iomem *base);
 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
                        u32 devfn, int where, int size, u32 *val);
 int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index af2d733c50b..86dbb5bdb17 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <plat/addr-map.h>
 #include <linux/delay.h>
 
 /*
@@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
         writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
 }
 
-void __init orion_pcie_setup(void __iomem *base,
-                             struct mbus_dram_target_info *dram)
+void __init orion_pcie_setup(void __iomem *base)
 {
         u16 cmd;
         u32 mask;
@@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base,
         /*
          * Point PCIe unit MBUS decode windows to DRAM space.
          */
-        orion_pcie_setup_wins(base, dram);
+        orion_pcie_setup_wins(base, &orion_mbus_dram_info);
 
         /*
          * Master + slave enable.
diff --git a/arch/arm/plat-pxa/include/plat/gpio-pxa.h b/arch/arm/plat-pxa/include/plat/gpio-pxa.h
deleted file mode 100644
index b6390beff32..00000000000
--- a/arch/arm/plat-pxa/include/plat/gpio-pxa.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __PLAT_PXA_GPIO_H
-#define __PLAT_PXA_GPIO_H
-
-struct irq_data;
-
-/*
- * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
- * one set of registers. The register offsets are organized below:
- *
- *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
- * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
- * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
- * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
- *
- * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
- * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
- * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
- *
- * NOTE:
- *   BANK 3 is only available on PXA27x and later processors.
- *   BANK 4 and 5 are only available on PXA935
- */
-
-#define GPIO_BANK(n)    (GPIO_REGS_VIRT + BANK_OFF(n))
-
-#define GPLR_OFFSET     0x00
-#define GPDR_OFFSET     0x0C
-#define GPSR_OFFSET     0x18
-#define GPCR_OFFSET     0x24
-#define GRER_OFFSET     0x30
-#define GFER_OFFSET     0x3C
-#define GEDR_OFFSET     0x48
-
-/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
- * Those cases currently cause holes in the GPIO number space, the
- * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
- */
-extern int pxa_last_gpio;
-
-typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
-
-extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
-
-#endif /* __PLAT_PXA_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
deleted file mode 100644
index 258f77210b0..00000000000
--- a/arch/arm/plat-pxa/include/plat/gpio.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __PLAT_GPIO_H
-#define __PLAT_GPIO_H
-
-#define __ARM_GPIOLIB_COMPLEX
-
-/* The individual machine provides register offsets and NR_BUILTIN_GPIO */
-#include <mach/gpio-pxa.h>
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
-                return GPLR(gpio) & GPIO_bit(gpio);
-        else
-                return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
-                if (value)
-                        GPSR(gpio) = GPIO_bit(gpio);
-                else
-                        GPCR(gpio) = GPIO_bit(gpio);
-        } else
-                __gpio_set_value(gpio, value);
-}
-
-#define gpio_cansleep           __gpio_cansleep
-
-#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 53754bcf15a..9fe35348e03 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1437,11 +1437,10 @@ int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
         size_t map_sz = sizeof(*nmap) * sel->map_size;
         int ptr;
 
-        nmap = kmalloc(map_sz, GFP_KERNEL);
+        nmap = kmemdup(sel->map, map_sz, GFP_KERNEL);
         if (nmap == NULL)
                 return -ENOMEM;
 
-        memcpy(nmap, sel->map, map_sz);
         memcpy(&dma_sel, sel, sizeof(*sel));
 
         dma_sel.map = nmap;
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 5a21b15b2a9..95e68190d59 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -297,13 +297,6 @@ static struct clksrc_clk clk_usb_bus_host = {
 
 static struct clksrc_clk clksrc_clks[] = {
         {
-                /* ART baud-rate clock sourced from esysclk via a divisor */
-                .clk    = {
-                        .name           = "uartclk",
-                        .parent         = &clk_esysclk.clk,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
-        }, {
                 /* camera interface bus-clock, divided down from esysclk */
                 .clk    = {
                         .name           = "camif-upll", /* same as 2440 name */
@@ -323,6 +316,15 @@ static struct clksrc_clk clksrc_clks[] = {
         },
 };
 
+static struct clksrc_clk clk_esys_uart = {
+        /* ART baud-rate clock sourced from esysclk via a divisor */
+        .clk    = {
+                .name           = "uartclk",
+                .parent         = &clk_esysclk.clk,
+        },
+        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
+};
+
 static struct clk clk_i2s_ext = {
         .name           = "i2s-ext",
 };
@@ -425,12 +427,6 @@ static struct clk init_clocks[] = {
                 .enable         = s3c2443_clkcon_enable_h,
                 .ctrlbit        = S3C2443_HCLKCON_DMA5,
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_HSMMC,
-        }, {
                 .name           = "gpio",
                 .parent         = &clk_p,
                 .enable         = s3c2443_clkcon_enable_p,
@@ -512,6 +508,14 @@ static struct clk init_clocks[] = {
         }
 };
 
+static struct clk hsmmc1_clk = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_h,
+        .enable         = s3c2443_clkcon_enable_h,
+        .ctrlbit        = S3C2443_HCLKCON_HSMMC,
+};
+
 static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
 {
         clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -577,6 +581,7 @@ static struct clk *clks[] __initdata = {
         &clk_epll,
         &clk_usb_bus,
         &clk_armdiv,
+        &hsmmc1_clk,
 };
 
 static struct clksrc_clk *clksrcs[] __initdata = {
@@ -589,6 +594,13 @@ static struct clksrc_clk *clksrcs[] __initdata = {
         &clk_arm,
 };
 
+static struct clk_lookup s3c2443_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
+};
+
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
                                        unsigned int *divs, int nr_divs,
                                        int divmask)
@@ -618,6 +630,7 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
         /* See s3c2443/etc notes on disabling clocks at init time */
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
 
         s3c2443_common_setup_clocks(get_mpll);
 }
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 313eb26cfa6..6a2abe67c8b 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -88,12 +88,20 @@ config S5P_GPIO_DRVSTR
 
 config SAMSUNG_GPIO_EXTRA
         int "Number of additional GPIO pins"
+        default 128 if SAMSUNG_GPIO_EXTRA128
+        default 64 if SAMSUNG_GPIO_EXTRA64
         default 0
         help
           Use additional GPIO space in addition to the GPIO's the SOC
           provides. This allows expanding the GPIO space for use with
           GPIO expanders.
 
+config SAMSUNG_GPIO_EXTRA64
+        bool
+
+config SAMSUNG_GPIO_EXTRA128
+        bool
+
 config S3C_GPIO_SPACE
         int "Space between gpio banks"
         default 0
@@ -226,11 +234,23 @@ config SAMSUNG_DEV_IDE
         help
           Compile in platform device definitions for IDE
 
-config S3C64XX_DEV_SPI
+config S3C64XX_DEV_SPI0
+        bool
+        help
+          Compile in platform device definitions for S3C64XX's type
+          SPI controller 0
+
+config S3C64XX_DEV_SPI1
+        bool
+        help
+          Compile in platform device definitions for S3C64XX's type
+          SPI controller 1
+
+config S3C64XX_DEV_SPI2
         bool
         help
           Compile in platform device definitions for S3C64XX's type
-          SPI controllers.
+          SPI controller 2
 
 config SAMSUNG_DEV_TS
         bool
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 4ca8b571f97..32a6e394db2 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
 #include <linux/ioport.h>
+#include <linux/platform_data/s3c-hsudc.h>
 
 #include <asm/irq.h>
 #include <asm/pmu.h>
@@ -61,6 +62,7 @@
 #include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
+#include <plat/s3c64xx-spi.h>
 
 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
 
@@ -1461,3 +1463,129 @@ struct platform_device s3c_device_wdt = {
         .resource       = s3c_wdt_resource,
 };
 #endif /* CONFIG_S3C_DEV_WDT */
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+static struct resource s3c64xx_spi0_resource[] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
+        [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
+        [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
+        [3] = DEFINE_RES_IRQ(IRQ_SPI0),
+};
+
+struct platform_device s3c64xx_device_spi0 = {
+        .name           = "s3c64xx-spi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s3c64xx_spi0_resource),
+        .resource       = s3c64xx_spi0_resource,
+        .dev = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
+                                      int src_clk_nr, int num_cs)
+{
+        if (!pd) {
+                pr_err("%s:Need to pass platform data\n", __func__);
+                return;
+        }
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0) {
+                pr_err("%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        if (!pd->cfg_gpio)
+                pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
+
+        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
+}
+#endif /* CONFIG_S3C64XX_DEV_SPI0 */
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+static struct resource s3c64xx_spi1_resource[] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
+        [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
+        [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
+        [3] = DEFINE_RES_IRQ(IRQ_SPI1),
+};
+
+struct platform_device s3c64xx_device_spi1 = {
+        .name           = "s3c64xx-spi",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s3c64xx_spi1_resource),
+        .resource       = s3c64xx_spi1_resource,
+        .dev = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
+                                      int src_clk_nr, int num_cs)
+{
+        if (!pd) {
+                pr_err("%s:Need to pass platform data\n", __func__);
+                return;
+        }
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0) {
+                pr_err("%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        if (!pd->cfg_gpio)
+                pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
+
+        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
+}
+#endif /* CONFIG_S3C64XX_DEV_SPI1 */
+
+#ifdef CONFIG_S3C64XX_DEV_SPI2
+static struct resource s3c64xx_spi2_resource[] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
+        [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
+        [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
+        [3] = DEFINE_RES_IRQ(IRQ_SPI2),
+};
+
+struct platform_device s3c64xx_device_spi2 = {
+        .name           = "s3c64xx-spi",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s3c64xx_spi2_resource),
+        .resource       = s3c64xx_spi2_resource,
+        .dev = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
+                                      int src_clk_nr, int num_cs)
+{
+        if (!pd) {
+                pr_err("%s:Need to pass platform data\n", __func__);
+                return;
+        }
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0) {
+                pr_err("%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        if (!pd->cfg_gpio)
+                pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
+
+        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
+}
+#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 93a994a5dd8..2cded872f22 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -18,23 +18,24 @@
 
 #include <mach/dma.h>
 
-static inline bool pl330_filter(struct dma_chan *chan, void *param)
-{
-        struct dma_pl330_peri *peri = chan->private;
-        return peri->peri_id == (unsigned)param;
-}
-
 static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
                                 struct samsung_dma_info *info)
 {
         struct dma_chan *chan;
         dma_cap_mask_t mask;
         struct dma_slave_config slave_config;
+        void *filter_param;
 
         dma_cap_zero(mask);
         dma_cap_set(info->cap, mask);
 
-        chan = dma_request_channel(mask, pl330_filter, (void *)dma_ch);
+        /*
+         * If a dma channel property of a device node from device tree is
+         * specified, use that as the fliter parameter.
+         */
+        filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)info->dt_dmach_prop :
+                                (void *)dma_ch;
+        chan = dma_request_channel(mask, pl330_filter, filter_param);
 
         if (info->direction == DMA_FROM_DEVICE) {
                 memset(&slave_config, 0, sizeof(struct dma_slave_config));
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ab633c9c2ae..4214ea0ff8f 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -39,6 +39,7 @@ extern struct platform_device s3c64xx_device_pcm0;
 extern struct platform_device s3c64xx_device_pcm1;
 extern struct platform_device s3c64xx_device_spi0;
 extern struct platform_device s3c64xx_device_spi1;
+extern struct platform_device s3c64xx_device_spi2;
 
 extern struct platform_device s3c_device_adc;
 extern struct platform_device s3c_device_cfcon;
@@ -98,8 +99,6 @@ extern struct platform_device s5p6450_device_iis1;
 extern struct platform_device s5p6450_device_iis2;
 extern struct platform_device s5p6450_device_pcm0;
 
-extern struct platform_device s5p64x0_device_spi0;
-extern struct platform_device s5p64x0_device_spi1;
 
 extern struct platform_device s5pc100_device_ac97;
 extern struct platform_device s5pc100_device_iis0;
@@ -108,9 +107,6 @@ extern struct platform_device s5pc100_device_iis2;
 extern struct platform_device s5pc100_device_pcm0;
 extern struct platform_device s5pc100_device_pcm1;
 extern struct platform_device s5pc100_device_spdif;
-extern struct platform_device s5pc100_device_spi0;
-extern struct platform_device s5pc100_device_spi1;
-extern struct platform_device s5pc100_device_spi2;
 
 extern struct platform_device s5pv210_device_ac97;
 extern struct platform_device s5pv210_device_iis0;
@@ -120,8 +116,6 @@ extern struct platform_device s5pv210_device_pcm0;
 extern struct platform_device s5pv210_device_pcm1;
 extern struct platform_device s5pv210_device_pcm2;
 extern struct platform_device s5pv210_device_spdif;
-extern struct platform_device s5pv210_device_spi0;
-extern struct platform_device s5pv210_device_spi1;
 
 extern struct platform_device exynos4_device_ac97;
 extern struct platform_device exynos4_device_ahci;
@@ -129,6 +123,7 @@ extern struct platform_device exynos4_device_dwmci;
 extern struct platform_device exynos4_device_i2s0;
 extern struct platform_device exynos4_device_i2s1;
 extern struct platform_device exynos4_device_i2s2;
+extern struct platform_device exynos4_device_ohci;
 extern struct platform_device exynos4_device_pcm0;
 extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 4c1a363526c..22eafc310bd 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -31,6 +31,7 @@ struct samsung_dma_info {
         enum dma_slave_buswidth width;
         dma_addr_t fifo;
         struct s3c2410_dma_client *client;
+        struct property *dt_dmach_prop;
 };
 
 struct samsung_dma_ops {
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 2e55e595867..c5eaad529de 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -21,7 +21,8 @@
  * use these just as IDs.
  */
 enum dma_ch {
-        DMACH_UART0_RX,
+        DMACH_DT_PROP = -1,
+        DMACH_UART0_RX = 0,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
         DMACH_UART1_TX,
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
index 08d1a7ef97b..df46b776976 100644
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -44,13 +44,14 @@
 #define S5P_IRQ_VIC2(x)         (S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)         (S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)        (11 + (x))
+#define S5P_TIMER_IRQ(x)        (IRQ_TIMER_BASE + (x))
 
 #define IRQ_TIMER0              S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1              S5P_TIMER_IRQ(1)
 #define IRQ_TIMER2              S5P_TIMER_IRQ(2)
 #define IRQ_TIMER3              S5P_TIMER_IRQ(3)
 #define IRQ_TIMER4              S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT         (5)
 
 #define IRQ_EINT(x)             ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
                                         : ((x) - 16 + S5P_EINT_BASE2))
diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
index b59a6483cd8..c81ace332a1 100644
--- a/arch/arm/plat-samsung/include/plat/keypad.h
+++ b/arch/arm/plat-samsung/include/plat/keypad.h
@@ -13,32 +13,7 @@
 #ifndef __PLAT_SAMSUNG_KEYPAD_H
 #define __PLAT_SAMSUNG_KEYPAD_H
 
-#include <linux/input/matrix_keypad.h>
-
-#define SAMSUNG_MAX_ROWS        8
-#define SAMSUNG_MAX_COLS        8
-
-/**
- * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
- * @keymap_data: pointer to &matrix_keymap_data.
- * @rows: number of keypad row supported.
- * @cols: number of keypad col supported.
- * @no_autorepeat: disable key autorepeat.
- * @wakeup: controls whether the device should be set up as wakeup source.
- * @cfg_gpio: configure the GPIO.
- *
- * Initialisation data specific to either the machine or the platform
- * for the device driver to use or call-back when configuring gpio.
- */
-struct samsung_keypad_platdata {
-        const struct matrix_keymap_data *keymap_data;
-        unsigned int rows;
-        unsigned int cols;
-        bool no_autorepeat;
-        bool wakeup;
-
-        void (*cfg_gpio)(unsigned int rows, unsigned int cols);
-};
+#include <linux/input/samsung-keypad.h>
 
 /**
  * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 72073484702..29c26a81884 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -71,6 +71,7 @@
 #define S3C2410_LCON_IRM          (1<<6)
 
 #define S3C2440_UCON_CLKMASK      (3<<10)
+#define S3C2440_UCON_CLKSHIFT     (10)
 #define S3C2440_UCON_PCLK         (0<<10)
 #define S3C2440_UCON_UCLK         (1<<10)
 #define S3C2440_UCON_PCLK2        (2<<10)
@@ -78,6 +79,7 @@
 #define S3C2443_UCON_EPLL         (3<<10)
 
 #define S3C6400_UCON_CLKMASK    (3<<10)
+#define S3C6400_UCON_CLKSHIFT   (10)
 #define S3C6400_UCON_PCLK       (0<<10)
 #define S3C6400_UCON_PCLK2      (2<<10)
 #define S3C6400_UCON_UCLK0      (1<<10)
@@ -90,11 +92,14 @@
 #define S3C2440_UCON_DIVSHIFT     (12)
 
 #define S3C2412_UCON_CLKMASK    (3<<10)
+#define S3C2412_UCON_CLKSHIFT   (10)
 #define S3C2412_UCON_UCLK       (1<<10)
 #define S3C2412_UCON_USYSCLK    (3<<10)
 #define S3C2412_UCON_PCLK       (0<<10)
 #define S3C2412_UCON_PCLK2      (2<<10)
 
+#define S3C2410_UCON_CLKMASK    (1 << 10)
+#define S3C2410_UCON_CLKSHIFT   (10)
 #define S3C2410_UCON_UCLK         (1<<10)
 #define S3C2410_UCON_SBREAK       (1<<4)
 
@@ -193,6 +198,7 @@
 
 /* Following are specific to S5PV210 */
 #define S5PV210_UCON_CLKMASK    (1<<10)
+#define S5PV210_UCON_CLKSHIFT   (10)
 #define S5PV210_UCON_PCLK       (0<<10)
 #define S5PV210_UCON_UCLK       (1<<10)
 
@@ -221,29 +227,24 @@
 #define S5PV210_UFSTAT_RXMASK   (255<<0)
 #define S5PV210_UFSTAT_RXSHIFT  (0)
 
-#define NO_NEED_CHECK_CLKSRC    1
+#define S3C2410_UCON_CLKSEL0    (1 << 0)
+#define S3C2410_UCON_CLKSEL1    (1 << 1)
+#define S3C2410_UCON_CLKSEL2    (1 << 2)
+#define S3C2410_UCON_CLKSEL3    (1 << 3)
 
-#ifndef __ASSEMBLY__
+/* Default values for s5pv210 UCON and UFCON uart registers */
+#define S5PV210_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
 
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
+#define S5PV210_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
 
-struct s3c24xx_uart_clksrc {
-        const char      *name;
-        unsigned int     divisor;
-        unsigned int     min_baud;
-        unsigned int     max_baud;
-};
+#ifndef __ASSEMBLY__
 
 /* configuration structure for per-machine configurations for the
  * serial port
@@ -257,15 +258,13 @@ struct s3c2410_uartcfg {
         unsigned char      unused;
         unsigned short     flags;
         upf_t              uart_flags;   /* default uart flags */
+        unsigned int       clk_sel;
 
         unsigned int       has_fracval;
 
         unsigned long      ucon;         /* value of ucon for port */
         unsigned long      ulcon;        /* value of ulcon for port */
         unsigned long      ufcon;        /* value of ufcon for port */
-
-        struct s3c24xx_uart_clksrc *clocks;
-        unsigned int                clocks_size;
 };
 
 /* s3c24xx_uart_devs
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3621b..aea68b60ef9 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
 /**
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @src_clk_name: Platform name of the corresponding clock.
  * @clk_from_cmu: If the SPI clock/prescalar control block is present
  *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
  */
 struct s3c64xx_spi_info {
         int src_clk_nr;
-        char *src_clk_name;
         bool clk_from_cmu;
 
         int num_cs;
@@ -58,18 +56,28 @@ struct s3c64xx_spi_info {
 };
 
 /**
- * s3c64xx_spi_set_info - SPI Controller configure callback by the board
+ * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
  *                              initialization code.
- * @cntrlr: SPI controller number the configuration is for.
+ * @pd: SPI platform data to set.
  * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
  * @num_cs: Number of elements in the 'cs' array.
  *
  * Call this from machine init code for each SPI Controller that
  * has some chips attached to it.
  */
-extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
-extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
-extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
-extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
+                                      int src_clk_nr, int num_cs);
+extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
+                                      int src_clk_nr, int num_cs);
+extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
+                                      int src_clk_nr, int num_cs);
 
+/* defined by architecture to configure gpio */
+extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
+
+extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
+extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
+extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
 #endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index e7b3c752e91..656dc00d30e 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -66,8 +66,6 @@ struct s3c_sdhci_platdata {
         enum cd_types   cd_type;
         enum clk_types  clk_type;
 
-        char            **clocks;       /* set of clock sources */
-
         int             ext_cd_gpio;
         bool            ext_cd_gpio_invert;
         int     (*ext_cd_init)(void (*notify_func)(struct platform_device *,
@@ -125,16 +123,17 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
+extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 
 /* S3C2416 SDHCI setup */
 
 #ifdef CONFIG_S3C2416_SETUP_SDHCI
-extern char *s3c2416_hsmmc_clksrcs[4];
-
 static inline void s3c2416_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
 #endif /* CONFIG_S3C_DEV_HSMMC */
 }
@@ -142,7 +141,6 @@ static inline void s3c2416_default_sdhci0(void)
 static inline void s3c2416_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
 }
@@ -152,15 +150,13 @@ static inline void s3c2416_default_sdhci0(void) { }
 static inline void s3c2416_default_sdhci1(void) { }
 
 #endif /* CONFIG_S3C2416_SETUP_SDHCI */
+
 /* S3C64XX SDHCI setup */
 
 #ifdef CONFIG_S3C64XX_SETUP_SDHCI
-extern char *s3c64xx_hsmmc_clksrcs[4];
-
 static inline void s3c6400_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
 #endif
 }
@@ -168,7 +164,6 @@ static inline void s3c6400_default_sdhci0(void)
 static inline void s3c6400_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
 #endif
 }
@@ -176,7 +171,6 @@ static inline void s3c6400_default_sdhci1(void)
 static inline void s3c6400_default_sdhci2(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
 #endif
 }
@@ -184,7 +178,6 @@ static inline void s3c6400_default_sdhci2(void)
 static inline void s3c6410_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
 #endif
 }
@@ -192,7 +185,6 @@ static inline void s3c6410_default_sdhci0(void)
 static inline void s3c6410_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
 #endif
 }
@@ -200,7 +192,6 @@ static inline void s3c6410_default_sdhci1(void)
 static inline void s3c6410_default_sdhci2(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
 #endif
 }
@@ -215,15 +206,51 @@ static inline void s3c6400_default_sdhci2(void) { }
 
 #endif /* CONFIG_S3C64XX_SETUP_SDHCI */
 
+/* S5P64X0 SDHCI setup */
+
+#ifdef CONFIG_S5P64X0_SETUP_SDHCI
+static inline void s5p64x0_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+        s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio;
+#endif
+}
+
+static inline void s5p64x0_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+        s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio;
+#endif
+}
+
+static inline void s5p6440_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
+#endif
+}
+
+static inline void s5p6450_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
+#endif
+}
+
+#else
+static inline void s5p64x0_default_sdhci0(void) { }
+static inline void s5p64x0_default_sdhci1(void) { }
+static inline void s5p6440_default_sdhci2(void) { }
+static inline void s5p6450_default_sdhci2(void) { }
+
+#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
+
 /* S5PC100 SDHCI setup */
 
 #ifdef CONFIG_S5PC100_SETUP_SDHCI
-extern char *s5pc100_hsmmc_clksrcs[4];
-
 static inline void s5pc100_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
 #endif
 }
@@ -231,7 +258,6 @@ static inline void s5pc100_default_sdhci0(void)
 static inline void s5pc100_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
 #endif
 }
@@ -239,7 +265,6 @@ static inline void s5pc100_default_sdhci1(void)
 static inline void s5pc100_default_sdhci2(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
 #endif
 }
@@ -254,12 +279,9 @@ static inline void s5pc100_default_sdhci2(void) { }
 /* S5PV210 SDHCI setup */
 
 #ifdef CONFIG_S5PV210_SETUP_SDHCI
-extern char *s5pv210_hsmmc_clksrcs[4];
-
 static inline void s5pv210_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
 #endif
 }
@@ -267,7 +289,6 @@ static inline void s5pv210_default_sdhci0(void)
 static inline void s5pv210_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
 #endif
 }
@@ -275,7 +296,6 @@ static inline void s5pv210_default_sdhci1(void)
 static inline void s5pv210_default_sdhci2(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
 #endif
 }
@@ -283,7 +303,6 @@ static inline void s5pv210_default_sdhci2(void)
 static inline void s5pv210_default_sdhci3(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC3
-        s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
 #endif
 }
@@ -298,12 +317,9 @@ static inline void s5pv210_default_sdhci3(void) { }
 
 /* EXYNOS4 SDHCI setup */
 #ifdef CONFIG_EXYNOS4_SETUP_SDHCI
-extern char *exynos4_hsmmc_clksrcs[4];
-
 static inline void exynos4_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
 #endif
 }
@@ -311,7 +327,6 @@ static inline void exynos4_default_sdhci0(void)
 static inline void exynos4_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
 #endif
 }
@@ -319,7 +334,6 @@ static inline void exynos4_default_sdhci1(void)
 static inline void exynos4_default_sdhci2(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
 #endif
 }
@@ -327,7 +341,6 @@ static inline void exynos4_default_sdhci2(void)
 static inline void exynos4_default_sdhci3(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC3
-        s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
 #endif
 }
diff --git a/arch/arm/plat-samsung/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h
index 8c22d586bef..de8e2288a50 100644
--- a/arch/arm/plat-samsung/include/plat/udc.h
+++ b/arch/arm/plat-samsung/include/plat/udc.h
@@ -37,20 +37,7 @@ struct s3c2410_udc_mach_info {
 
 extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
 
-/**
- * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
- * @epnum: Number of endpoints to be instantiated by the controller driver.
- * @gpio_init: Platform specific USB related GPIO initialization.
- * @gpio_uninit: Platform specific USB releted GPIO uninitialzation.
- *
- * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
- * controllers.
- */
-struct s3c24xx_hsudc_platdata {
-        unsigned int    epnum;
-        void            (*gpio_init)(void);
-        void            (*gpio_uninit)(void);
-};
+struct s3c24xx_hsudc_platdata;
 
 extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
 
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index 1f17bde52cd..7c756fb189f 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -109,7 +109,7 @@ struct eth_addr {
         u8 addr[6];
 };
 static struct eth_addr __initdata hw_addr[2];
-static struct eth_platform_data __initdata eth_data[2];
+static struct macb_platform_data __initdata eth_data[2];
 
 static struct spi_board_info spi0_board_info[] __initdata = {
         {
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index 4643ff5107c..c56ddac85d6 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -105,7 +105,7 @@ struct eth_addr {
 };
 
 static struct eth_addr __initdata hw_addr[2];
-static struct eth_platform_data __initdata eth_data[2] = {
+static struct macb_platform_data __initdata eth_data[2] = {
         {
                 /*
                  * The MDIO pullups on STK1000 are a bit too weak for
diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c
index 86fab77a5a0..27bd6fbe21c 100644
--- a/arch/avr32/boards/favr-32/setup.c
+++ b/arch/avr32/boards/favr-32/setup.c
@@ -50,7 +50,7 @@ struct eth_addr {
         u8 addr[6];
 };
 static struct eth_addr __initdata hw_addr[1];
-static struct eth_platform_data __initdata eth_data[1] = {
+static struct macb_platform_data __initdata eth_data[1] = {
         {
                 .phy_mask       = ~(1U << 1),
         },
diff --git a/arch/avr32/boards/hammerhead/setup.c b/arch/avr32/boards/hammerhead/setup.c
index da14fbdd4e8..9d1efd1cd42 100644
--- a/arch/avr32/boards/hammerhead/setup.c
+++ b/arch/avr32/boards/hammerhead/setup.c
@@ -102,7 +102,7 @@ struct eth_addr {
 };
 
 static struct eth_addr __initdata hw_addr[1];
-static struct eth_platform_data __initdata eth_data[1];
+static struct macb_platform_data __initdata eth_data[1];
 
 /*
  * The next two functions should go away as the boot loader is
diff --git a/arch/avr32/boards/merisc/setup.c b/arch/avr32/boards/merisc/setup.c
index e61bc948f95..ed137e33579 100644
--- a/arch/avr32/boards/merisc/setup.c
+++ b/arch/avr32/boards/merisc/setup.c
@@ -52,7 +52,7 @@ struct eth_addr {
 };
 
 static struct eth_addr __initdata hw_addr[2];
-static struct eth_platform_data __initdata eth_data[2];
+static struct macb_platform_data __initdata eth_data[2];
 
 static int ads7846_get_pendown_state_PB26(void)
 {
diff --git a/arch/avr32/boards/mimc200/setup.c b/arch/avr32/boards/mimc200/setup.c
index c4da5cba2db..05358aa5ef7 100644
--- a/arch/avr32/boards/mimc200/setup.c
+++ b/arch/avr32/boards/mimc200/setup.c
@@ -86,7 +86,7 @@ struct eth_addr {
         u8 addr[6];
 };
 static struct eth_addr __initdata hw_addr[2];
-static struct eth_platform_data __initdata eth_data[2];
+static struct macb_platform_data __initdata eth_data[2];
 
 static struct spi_eeprom eeprom_25lc010 = {
                 .name = "25lc010",
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 7fbf0dcb9af..402a7bb7266 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1067,7 +1067,7 @@ void __init at32_setup_serial_console(unsigned int usart_id)
  * -------------------------------------------------------------------- */
 
 #ifdef CONFIG_CPU_AT32AP7000
-static struct eth_platform_data macb0_data;
+static struct macb_platform_data macb0_data;
 static struct resource macb0_resource[] = {
         PBMEM(0xfff01800),
         IRQ(25),
@@ -1076,7 +1076,7 @@ DEFINE_DEV_DATA(macb, 0);
 DEV_CLK(hclk, macb0, hsb, 8);
 DEV_CLK(pclk, macb0, pbb, 6);
 
-static struct eth_platform_data macb1_data;
+static struct macb_platform_data macb1_data;
 static struct resource macb1_resource[] = {
         PBMEM(0xfff01c00),
         IRQ(26),
@@ -1086,7 +1086,7 @@ DEV_CLK(hclk, macb1, hsb, 9);
 DEV_CLK(pclk, macb1, pbb, 7);
 
 struct platform_device *__init
-at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
+at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
 {
         struct platform_device *pdev;
         u32 pin_mask;
@@ -1163,7 +1163,7 @@ at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
                 return NULL;
         }
 
-        memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
+        memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
         platform_device_register(pdev);
 
         return pdev;
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index 5d7ffca7d69..67b111ce332 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -6,6 +6,7 @@
 
 #include <linux/types.h>
 #include <linux/serial.h>
+#include <linux/platform_data/macb.h>
 
 #define GPIO_PIN_NONE   (-1)
 
@@ -42,12 +43,8 @@ struct atmel_uart_data {
 void at32_map_usart(unsigned int hw_id, unsigned int line, int flags);
 struct platform_device *at32_add_device_usart(unsigned int id);
 
-struct eth_platform_data {
-        u32     phy_mask;
-        u8      is_rmii;
-};
 struct platform_device *
-at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
+at32_add_device_eth(unsigned int id, struct macb_platform_data *data);
 
 struct spi_board_info;
 struct platform_device *
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 5edcb58d6f7..0b7039cf07f 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -80,7 +80,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 2e549572d4f..5553205d7cb 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -97,7 +97,7 @@ CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_WATCHDOG=y
diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
index ad0881ba30a..d95658fc312 100644
--- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
+++ b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
@@ -68,7 +68,7 @@ CONFIG_I2C_ALGOBIT=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index 8465b3e6b86..498f64a8705 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -105,7 +105,7 @@ CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 5e7321b2604..72e0317565e 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -99,7 +99,7 @@ CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index a7eb54bf308..2f075e0b262 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -81,7 +81,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index b90d3792ed5..ab38a82597b 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -84,7 +84,7 @@ CONFIG_I2C=m
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_GPIO=m
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 005362537a7..5c802d6bbbc 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -94,7 +94,7 @@ CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_BLACKFIN_TWI=m
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index 580bf4296a1..972aa6263ad 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -101,7 +101,7 @@ CONFIG_I2C=m
 CONFIG_I2C_BLACKFIN_TWI=m
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 0e6d841b5d0..7a1e3bf2b04 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -113,7 +113,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
index 77a27e31d6d..0fdc4ecaa53 100644
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
@@ -85,7 +85,7 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_PCA_PLATFORM=y
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
index f5ed34e12e0..78adbbf3982 100644
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -84,7 +84,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index d7ff2aee3fb..d3cd0f561c8 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -86,7 +86,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 85014319672..7b982d0502a 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -80,7 +80,7 @@ CONFIG_I2C=m
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_GPIO=m
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_SPI_SPIDEV=m
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index dbf750cd2db..c280a50e794 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -88,7 +88,7 @@ CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_BLACKFIN_TWI=m
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_WATCHDOG=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index 07ffbdae34e..c940a1e3ab3 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -57,7 +57,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 # CONFIG_HWMON is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index 707cbf8a259..2e47df77490 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -78,7 +78,7 @@ CONFIG_SERIAL_BFIN_UART1=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_USB_GADGET=m
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index 4596935eada..6da629ffc2f 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -72,7 +72,7 @@ CONFIG_SERIAL_BFIN_UART1=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_USB_GADGET=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index 9f1d08401fc..349922be01f 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -89,7 +89,7 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index 6c7b21585a4..0456deaa2d6 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -78,7 +78,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_USB_GADGET=m
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
index b192acfae38..89162d0fff9 100644
--- a/arch/blackfin/configs/DNP5370_defconfig
+++ b/arch/blackfin/configs/DNP5370_defconfig
@@ -78,7 +78,7 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index 06e9f497fae..a26436bf50f 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -68,7 +68,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_WATCHDOG=y
 CONFIG_SOUND=m
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index 5e797cf7204..647991514ac 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -70,7 +70,7 @@ CONFIG_SERIAL_BFIN_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_HW_RANDOM=y
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_USB=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index a566a2fe6b9..8fd9b446d65 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -84,7 +84,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index 12e66cd7cda..0520c160230 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -71,7 +71,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_HWMON=m
 CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig
index d496ae9a39b..e4ed865b885 100644
--- a/arch/blackfin/configs/TCM-BF518_defconfig
+++ b/arch/blackfin/configs/TCM-BF518_defconfig
@@ -92,7 +92,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index 65f642167a5..c1f45f15295 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -70,7 +70,7 @@ CONFIG_SERIAL_BFIN_UART1=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
-CONFIG_SPI_BFIN=y
+CONFIG_SPI_BFIN5XX=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index ecacdf34768..68bcc3d119b 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -51,9 +51,6 @@ struct bfin_serial_port {
 #elif ANOMALY_05000363
         unsigned int anomaly_threshold;
 #endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        int scts;
-#endif
 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
         defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
         int cts_pin;
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index 05043786da2..e349631c829 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -14,6 +14,9 @@ struct blackfin_cpudata {
         struct cpu cpu;
         unsigned int imemctl;
         unsigned int dmemctl;
+#ifdef CONFIG_SMP
+        struct task_struct *idle;
+#endif
 };
 
 DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
index af6c0aa79ba..dc3d144b4bb 100644
--- a/arch/blackfin/include/asm/smp.h
+++ b/arch/blackfin/include/asm/smp.h
@@ -37,7 +37,7 @@ extern unsigned long dcache_invld_count[NR_CPUS];
 #endif
 
 void smp_icache_flush_range_others(unsigned long start,
-                                   unsigned long end);
+                                        unsigned long end);
 #ifdef CONFIG_HOTPLUG_CPU
 void coreb_die(void);
 void cpu_die(void);
@@ -46,4 +46,7 @@ int __cpu_disable(void);
 int __cpu_die(unsigned int cpu);
 #endif
 
+void smp_timer_broadcast(const struct cpumask *mask);
+
+
 #endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index dfa2525a442..d6102c86d03 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -828,10 +828,18 @@ static inline int __init get_mem_size(void)
         u32 ddrctl = bfin_read_EBIU_DDRCTL1();
         int ret = 0;
         switch (ddrctl & 0xc0000) {
-                case DEVSZ_64:  ret = 64 / 8;
-                case DEVSZ_128: ret = 128 / 8;
-                case DEVSZ_256: ret = 256 / 8;
-                case DEVSZ_512: ret = 512 / 8;
+        case DEVSZ_64:
+                ret = 64 / 8;
+                break;
+        case DEVSZ_128:
+                ret = 128 / 8;
+                break;
+        case DEVSZ_256:
+                ret = 256 / 8;
+                break;
+        case DEVSZ_512:
+                ret = 512 / 8;
+                break;
         }
         switch (ddrctl & 0x30000) {
                 case DEVWD_4:  ret *= 2;
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index 1bcf3a3c57d..d98f2d69b0c 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -219,7 +219,7 @@ static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
 
 #if defined(CONFIG_TICKSOURCE_CORETMR)
 /* per-cpu local core timer */
-static DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
+DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
 
 static int bfin_coretmr_set_next_event(unsigned long cycles,
                                 struct clock_event_device *evt)
@@ -281,6 +281,7 @@ void bfin_coretmr_init(void)
 #ifdef CONFIG_CORE_TIMER_IRQ_L1
 __attribute__((l1_text))
 #endif
+
 irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
 {
         int cpu = smp_processor_id();
@@ -306,6 +307,11 @@ void bfin_coretmr_clockevent_init(void)
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
 
+#ifdef CONFIG_SMP
+        evt->broadcast = smp_timer_broadcast;
+#endif
+
+
         evt->name = "bfin_core_timer";
         evt->rating = 350;
         evt->irq = -1;
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index d1c0c0cff3e..a2d96d31bbf 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -61,7 +61,7 @@ static struct physmap_flash_data ezbrd_flash_data = {
 
 static struct resource ezbrd_flash_resource = {
         .start = 0x20000000,
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         .end   = 0x202fffff,
 #else
         .end   = 0x203fffff,
@@ -122,6 +122,8 @@ static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
 #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
         .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
 #endif
+        .vlan1_mask = 1,
+        .vlan2_mask = 2,
 };
 
 static struct platform_device bfin_mii_bus = {
@@ -292,7 +294,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 };
 
 /* SPI controller data */
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = 6,
@@ -715,7 +717,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
         &bfin_spi1_device,
 #endif
@@ -777,7 +779,7 @@ static int __init ezbrd_init(void)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
         /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
         peripheral_request(P_AMS2, "ParaFlash");
-#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
+#if !defined(CONFIG_SPI_BFIN5XX) && !defined(CONFIG_SPI_BFIN5XX_MODULE)
         peripheral_request(P_AMS3, "ParaFlash");
 #endif
         return 0;
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 5470bf89e52..f271310f739 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -228,7 +228,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 };
 
 /* SPI controller data */
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = 6,
@@ -635,7 +635,7 @@ static struct platform_device *tcm_devices[] __initdata = {
         &bfin_mac_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
         &bfin_spi1_device,
 #endif
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index 5bc6938157a..c8d5d2b7c73 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -334,7 +334,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
@@ -744,7 +744,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_mac_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index cd289698b4d..7330607856e 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -444,7 +444,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = 8,
@@ -893,7 +893,7 @@ static struct platform_device *cmbf527_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 9f792eafd1c..db3ecfce830 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -371,7 +371,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = 8,
@@ -776,7 +776,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_mac_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 3ecafff5d2e..dfdd8e6bac7 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -664,7 +664,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = 8,
@@ -1189,7 +1189,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 3a92c4318d2..360e97fc529 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -448,7 +448,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
@@ -831,7 +831,7 @@ static struct platform_device *tll6527m_devices[] __initdata = {
         &bfin_mac_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 47cadd316e7..6cb7b3ed9b3 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -125,7 +125,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
@@ -398,7 +398,7 @@ static struct platform_device *h8606_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -428,7 +428,7 @@ static int __init H8606_init(void)
         printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
         return 0;
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 18817d57c7a..de44a3765e5 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -146,7 +146,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
         [0] = {
@@ -422,7 +422,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 2c8f30ef6a7..fe47e048c4e 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -29,7 +29,7 @@
  */
 const char bfin_board_name[] = "Bluetechnix CM BF533";
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
@@ -536,7 +536,7 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -549,7 +549,7 @@ static int __init cm_bf533_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
         return 0;
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 144556e1449..07811c209b9 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -245,7 +245,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
         [0] = {
@@ -484,7 +484,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &smc91x_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index b597d4e50d5..e303dae4e2d 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -104,7 +104,7 @@ static struct platform_device dm9000_device2 = {
 #endif
 
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -270,7 +270,7 @@ static struct platform_device *ip0x_devices[] __initdata = {
 #endif
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &spi_bfin_master_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 2afd02e14bd..ce88a7165b6 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -219,9 +219,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
         {
-                .modalias = "ad183x",
+                .modalias = "ad1836",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
@@ -251,7 +252,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
         [0] = {
@@ -471,7 +472,7 @@ static struct i2c_gpio_platform_data i2c_gpio_data = {
         .scl_pin                = GPIO_PF3,
         .sda_is_open_drain      = 0,
         .scl_is_open_drain      = 0,
-        .udelay                 = 40,
+        .udelay                 = 10,
 };
 
 static struct platform_device i2c_gpio_device = {
@@ -540,27 +541,150 @@ static struct platform_device bfin_dpmc = {
         },
 };
 
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) \
+        || defined(CONFIG_SND_BF5XX_AC97) || \
+        defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#include <asm/bfin_sport.h>
+
+#define SPORT_REQ(x) \
+        [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+                P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+        SPORT_REQ(0),
+        SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+        {
+                .pin_req = &bfin_snd_pin[0][0],
+        },
+        {
+                .pin_req = &bfin_snd_pin[1][0],
+        },
+};
+
+#define BFIN_SND_RES(x) \
+        [x] = { \
+                { \
+                        .start = SPORT##x##_TCR1, \
+                        .end = SPORT##x##_TCR1, \
+                        .flags = IORESOURCE_MEM \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_RX, \
+                        .end = CH_SPORT##x##_RX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_TX, \
+                        .end = CH_SPORT##x##_TX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = IRQ_SPORT##x##_ERROR, \
+                        .end = IRQ_SPORT##x##_ERROR, \
+                        .flags = IORESOURCE_IRQ, \
+                } \
+        }
+
+static struct resource bfin_snd_resources[][4] = {
+        BFIN_SND_RES(0),
+        BFIN_SND_RES(1),
+};
+#endif
+
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+static struct platform_device bfin_tdm_pcm = {
+        .name = "bfin-tdm-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+static struct platform_device bfin_ac97_pcm = {
+        .name = "bfin-ac97-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+        defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static const unsigned ad73311_gpio[] = {
+        GPIO_PF4,
+};
+
+static struct platform_device bfin_ad73311_machine = {
+        .name = "bfin-snd-ad73311",
+        .id = 1,
+        .dev = {
+                .platform_data = (void *)ad73311_gpio,
+        },
+};
+#endif
+
+#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+        .name = "ad73311",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_SOC_AD74111) || defined(CONFIG_SND_SOC_AD74111_MODULE)
+static struct platform_device bfin_ad74111_codec_device = {
+        .name = "ad74111",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || \
+        defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
 static struct platform_device bfin_i2s = {
         .name = "bfin-i2s",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources =
+                ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || \
+        defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
 static struct platform_device bfin_tdm = {
         .name = "bfin-tdm",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources =
+                ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || \
+        defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources =
+                ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
@@ -580,7 +704,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -596,7 +720,8 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
 
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || \
+        defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
         &bfin_sport0_uart_device,
 #endif
@@ -618,14 +743,42 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
-        &bfin_i2s,
+        &bfin_i2s_pcm,
 #endif
 
 #if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm,
+        &bfin_tdm_pcm,
 #endif
 
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_ac97_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+        defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+        &bfin_ad73311_machine,
+#endif
+
+#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
+        &bfin_ad73311_codec_device,
+#endif
+
+#if defined(CONFIG_SND_SOC_AD74111) || defined(CONFIG_SND_SOC_AD74111_MODULE)
+        &bfin_ad74111_codec_device,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || \
+        defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
+        &bfin_i2s,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || \
+        defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
+        &bfin_tdm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || \
+        defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
         &bfin_ac97,
 #endif
 };
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 604a430038e..0d4a2f61a97 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -31,7 +31,7 @@
  */
 const char bfin_board_name[] = "Bluetechnix CM BF537E";
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
@@ -735,7 +735,7 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -770,7 +770,7 @@ static int __init cm_bf537e_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
 
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index d916b46a44f..f5536982706 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -32,7 +32,7 @@
  */
 const char bfin_board_name[] = "Bluetechnix CM BF537U";
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
@@ -700,7 +700,7 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -747,7 +747,7 @@ static int __init cm_bf537u_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
 
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 5f307228be6..11dadeb33d7 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -125,7 +125,7 @@ static struct platform_device asmb_flash_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 
@@ -370,7 +370,7 @@ static struct platform_device *dnp5370_devices[] __initdata = {
         &bfin_mac_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &spi_bfin_master_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 3901dd093b9..d2d71282618 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -121,7 +121,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) \
@@ -496,7 +496,7 @@ static struct platform_device *minotaur_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -537,7 +537,7 @@ static int __init minotaur_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info,
                                 ARRAY_SIZE(bfin_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index aebd31c845f..6fd84709fc6 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -154,7 +154,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) \
@@ -477,7 +477,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -508,7 +508,7 @@ static int __init pnav_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info,
                                 ARRAY_SIZE(bfin_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 7fbb0bbf867..2221173e489 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -1420,7 +1420,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
@@ -1462,7 +1462,7 @@ static struct platform_device bfin_spi0_device = {
 
 /* SPORT SPI controller data */
 static struct bfin5xx_spi_master bfin_sport_spi0_info = {
-        .num_chipselect = 1, /* master only supports one device */
+        .num_chipselect = MAX_BLACKFIN_GPIOS,
         .enable_dma = 0,  /* master don't support DMA */
         .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
                 P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
@@ -1492,7 +1492,7 @@ static struct platform_device bfin_sport_spi0_device = {
 };
 
 static struct bfin5xx_spi_master bfin_sport_spi1_info = {
-        .num_chipselect = 1, /* master only supports one device */
+        .num_chipselect = MAX_BLACKFIN_GPIOS,
         .enable_dma = 0,  /* master don't support DMA */
         .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
                 P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
@@ -1558,6 +1558,71 @@ static struct platform_device bfin_lq035q1_device = {
 };
 #endif
 
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_capture.h>
+#include <media/blackfin/ppi.h>
+
+static const unsigned short ppi_req[] = {
+        P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+        P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+        0,
+};
+
+static const struct ppi_info ppi_info = {
+        .type = PPI_TYPE_PPI,
+        .dma_ch = CH_PPI,
+        .irq_err = IRQ_PPI_ERROR,
+        .base = (void __iomem *)PPI_CONTROL,
+        .pin_req = ppi_req,
+};
+
+#if defined(CONFIG_VIDEO_VS6624) \
+        || defined(CONFIG_VIDEO_VS6624_MODULE)
+static struct v4l2_input vs6624_inputs[] = {
+        {
+                .index = 0,
+                .name = "Camera",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_UNKNOWN,
+        },
+};
+
+static struct bcap_route vs6624_routes[] = {
+        {
+                .input = 0,
+                .output = 0,
+        },
+};
+
+static const unsigned vs6624_ce_pin = GPIO_PF10;
+
+static struct bfin_capture_config bfin_capture_data = {
+        .card_name = "BF537",
+        .inputs = vs6624_inputs,
+        .num_inputs = ARRAY_SIZE(vs6624_inputs),
+        .routes = vs6624_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "vs6624",
+                .addr = 0x10,
+                .platform_data = (void *)&vs6624_ce_pin,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020),
+};
+#endif
+
+static struct platform_device bfin_capture_device = {
+        .name = "bfin_capture",
+        .dev = {
+                .platform_data = &bfin_capture_data,
+        },
+};
+#endif
+
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
@@ -2716,7 +2781,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -2733,6 +2798,11 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_lq035q1_device,
 #endif
 
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+        &bfin_capture_device,
+#endif
+
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_UART0
         &bfin_uart0_device,
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 6917ce2fa55..988517671a5 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -32,7 +32,7 @@
  */
 const char bfin_board_name[] = "Bluetechnix TCM BF537";
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
@@ -702,7 +702,7 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -737,7 +737,7 @@ static int __init tcm_bf537_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
 
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 8356eb599f1..1633a6f306c 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -490,7 +490,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -874,7 +874,7 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
 #endif
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bf538_spi_master0,
         &bf538_spi_master1,
         &bf538_spi_master2,
@@ -938,7 +938,7 @@ static int __init ezkit_init(void)
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bf538_spi_board_info,
                         ARRAY_SIZE(bf538_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 0350eacec21..68af594db48 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -854,7 +854,7 @@ static struct platform_device para_flash_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -1175,7 +1175,7 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
         &bf54x_sdh_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bf54x_spi_master0,
         &bf54x_spi_master1,
 #endif
@@ -1210,7 +1210,7 @@ static int __init cm_bf548_init(void)
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bf54x_spi_board_info,
                         ARRAY_SIZE(bf54x_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index bb868ac0fe2..3ea45f8bd61 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -1110,7 +1110,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 };
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
         [0] = {
@@ -1183,6 +1183,71 @@ static struct platform_device bf54x_spi_master1 = {
 };
 #endif  /* spi master and devices */
 
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_capture.h>
+#include <media/blackfin/ppi.h>
+
+static const unsigned short ppi_req[] = {
+        P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
+        P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
+        P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
+        0,
+};
+
+static const struct ppi_info ppi_info = {
+        .type = PPI_TYPE_EPPI,
+        .dma_ch = CH_EPPI1,
+        .irq_err = IRQ_EPPI1_ERROR,
+        .base = (void __iomem *)EPPI1_STATUS,
+        .pin_req = ppi_req,
+};
+
+#if defined(CONFIG_VIDEO_VS6624) \
+        || defined(CONFIG_VIDEO_VS6624_MODULE)
+static struct v4l2_input vs6624_inputs[] = {
+        {
+                .index = 0,
+                .name = "Camera",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_UNKNOWN,
+        },
+};
+
+static struct bcap_route vs6624_routes[] = {
+        {
+                .input = 0,
+                .output = 0,
+        },
+};
+
+static const unsigned vs6624_ce_pin = GPIO_PG6;
+
+static struct bfin_capture_config bfin_capture_data = {
+        .card_name = "BF548",
+        .inputs = vs6624_inputs,
+        .num_inputs = ARRAY_SIZE(vs6624_inputs),
+        .routes = vs6624_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "vs6624",
+                .addr = 0x10,
+                .platform_data = (void *)&vs6624_ce_pin,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
+};
+#endif
+
+static struct platform_device bfin_capture_device = {
+        .name = "bfin_capture",
+        .dev = {
+                .platform_data = &bfin_capture_data,
+        },
+};
+#endif
+
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
         [0] = {
@@ -1502,10 +1567,14 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bf54x_sdh_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bf54x_spi_master0,
         &bf54x_spi_master1,
 #endif
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+        &bfin_capture_device,
+#endif
 
 #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
         &bf54x_kpad_device,
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index b1b7339b6ba..f6ffd6f054c 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -372,7 +372,7 @@ static struct bfin5xx_spi_chip data_flash_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
         [0] = {
@@ -475,7 +475,7 @@ static struct platform_device bfin_dpmc = {
 static struct platform_device *acvilon_devices[] __initdata = {
         &bfin_dpmc,
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index c017cf07ed4..d81450f635d 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -29,7 +29,7 @@
  */
 const char bfin_board_name[] = "Bluetechnix CM BF561";
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
 
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
@@ -488,7 +488,7 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -523,7 +523,7 @@ static int __init cm_bf561_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
 
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 27f22ed381d..838978808a1 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -291,7 +291,7 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
         [0] = {
@@ -383,7 +383,7 @@ static struct i2c_gpio_platform_data i2c_gpio_data = {
         .scl_pin                = GPIO_PF0,
         .sda_is_open_drain      = 0,
         .scl_is_open_drain      = 0,
-        .udelay                 = 40,
+        .udelay                 = 10,
 };
 
 static struct platform_device i2c_gpio_device = {
@@ -422,6 +422,96 @@ static struct platform_device bfin_dpmc = {
         },
 };
 
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_capture.h>
+#include <media/blackfin/ppi.h>
+
+static const unsigned short ppi_req[] = {
+        P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+        P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+        0,
+};
+
+static const struct ppi_info ppi_info = {
+        .type = PPI_TYPE_PPI,
+        .dma_ch = CH_PPI0,
+        .irq_err = IRQ_PPI1_ERROR,
+        .base = (void __iomem *)PPI0_CONTROL,
+        .pin_req = ppi_req,
+};
+
+#if defined(CONFIG_VIDEO_ADV7183) \
+        || defined(CONFIG_VIDEO_ADV7183_MODULE)
+#include <media/adv7183.h>
+static struct v4l2_input adv7183_inputs[] = {
+        {
+                .index = 0,
+                .name = "Composite",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+        },
+        {
+                .index = 1,
+                .name = "S-Video",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+        },
+        {
+                .index = 2,
+                .name = "Component",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+        },
+};
+
+static struct bcap_route adv7183_routes[] = {
+        {
+                .input = ADV7183_COMPOSITE4,
+                .output = ADV7183_8BIT_OUT,
+        },
+        {
+                .input = ADV7183_SVIDEO0,
+                .output = ADV7183_8BIT_OUT,
+        },
+        {
+                .input = ADV7183_COMPONENT0,
+                .output = ADV7183_8BIT_OUT,
+        },
+};
+
+
+static const unsigned adv7183_gpio[] = {
+        GPIO_PF13, /* reset pin */
+        GPIO_PF2,  /* output enable pin */
+};
+
+static struct bfin_capture_config bfin_capture_data = {
+        .card_name = "BF561",
+        .inputs = adv7183_inputs,
+        .num_inputs = ARRAY_SIZE(adv7183_inputs),
+        .routes = adv7183_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "adv7183",
+                .addr = 0x20,
+                .platform_data = (void *)adv7183_gpio,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL),
+};
+#endif
+
+static struct platform_device bfin_capture_device = {
+        .name = "bfin_capture",
+        .dev = {
+                .platform_data = &bfin_capture_data,
+        },
+};
+#endif
+
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 static struct platform_device bfin_i2s = {
         .name = "bfin-i2s",
@@ -462,7 +552,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_isp1760_device,
 #endif
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
         &bfin_spi0_device,
 #endif
 
@@ -494,6 +584,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &ezkit_flash_device,
 #endif
 
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+        &bfin_capture_device,
+#endif
+
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s,
 #endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
index 7977db2f1c1..00bdacee9cc 100644
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -16,6 +16,7 @@
 #include <mach/irq.h>
 
 #define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
+#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
 
 static inline void
 bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
@@ -42,7 +43,8 @@ bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
 static inline void
 bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
 {
-        bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2);
+        bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
+                        IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
 }
 
 #endif
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index db22401e760..ab1c617b9cf 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -84,7 +84,7 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
 
         if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
                 /* CoreB already running, sending ipi to wakeup it */
-                platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
+                smp_send_reschedule(cpu);
         } else {
                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
                 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
@@ -114,7 +114,8 @@ void __init platform_request_ipi(int irq, void *handler)
         int ret;
         const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
 
-        ret = request_irq(irq, handler, IRQF_PERCPU, name, handler);
+        ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
+                        IRQF_FORCE_RESUME, name, handler);
         if (ret)
                 panic("Cannot request %s for IPI service", name);
 }
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 0784a52389c..ac8f8a43158 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -14,6 +14,7 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/cache.h>
+#include <linux/clockchips.h>
 #include <linux/profile.h>
 #include <linux/errno.h>
 #include <linux/mm.h>
@@ -47,9 +48,10 @@ unsigned long blackfin_iflush_l1_entry[NR_CPUS];
 
 struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
 
-#define BFIN_IPI_RESCHEDULE   0
-#define BFIN_IPI_CALL_FUNC    1
-#define BFIN_IPI_CPU_STOP     2
+#define BFIN_IPI_TIMER        0
+#define BFIN_IPI_RESCHEDULE   1
+#define BFIN_IPI_CALL_FUNC    2
+#define BFIN_IPI_CPU_STOP     3
 
 struct blackfin_flush_data {
         unsigned long start;
@@ -160,6 +162,14 @@ static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
         return IRQ_HANDLED;
 }
 
+DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
+void ipi_timer(void)
+{
+        int cpu = smp_processor_id();
+        struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
+        evt->event_handler(evt);
+}
+
 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 {
         struct ipi_message *msg;
@@ -176,18 +186,17 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
         while (msg_queue->count) {
                 msg = &msg_queue->ipi_message[msg_queue->head];
                 switch (msg->type) {
+                case BFIN_IPI_TIMER:
+                        ipi_timer();
+                        break;
                 case BFIN_IPI_RESCHEDULE:
                         scheduler_ipi();
                         break;
                 case BFIN_IPI_CALL_FUNC:
-                        spin_unlock_irqrestore(&msg_queue->lock, flags);
                         ipi_call_function(cpu, msg);
-                        spin_lock_irqsave(&msg_queue->lock, flags);
                         break;
                 case BFIN_IPI_CPU_STOP:
-                        spin_unlock_irqrestore(&msg_queue->lock, flags);
                         ipi_cpu_stop(cpu);
-                        spin_lock_irqsave(&msg_queue->lock, flags);
                         break;
                 default:
                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
@@ -297,8 +306,6 @@ void smp_send_reschedule(int cpu)
 {
         cpumask_t callmap;
         /* simply trigger an ipi */
-        if (cpu_is_offline(cpu))
-                return;
 
         cpumask_clear(&callmap);
         cpumask_set_cpu(cpu, &callmap);
@@ -308,6 +315,16 @@ void smp_send_reschedule(int cpu)
         return;
 }
 
+void smp_send_msg(const struct cpumask *mask, unsigned long type)
+{
+        smp_send_message(*mask, type, NULL, NULL, 0);
+}
+
+void smp_timer_broadcast(const struct cpumask *mask)
+{
+        smp_send_msg(mask, BFIN_IPI_TIMER);
+}
+
 void smp_send_stop(void)
 {
         cpumask_t callmap;
@@ -326,17 +343,24 @@ void smp_send_stop(void)
 int __cpuinit __cpu_up(unsigned int cpu)
 {
         int ret;
-        static struct task_struct *idle;
+        struct blackfin_cpudata *ci = &per_cpu(cpu_data, cpu);
+        struct task_struct *idle = ci->idle;
 
-        if (idle)
+        if (idle) {
                 free_task(idle);
-
-        idle = fork_idle(cpu);
-        if (IS_ERR(idle)) {
-                printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
-                return PTR_ERR(idle);
+                idle = NULL;
         }
 
+        if (!idle) {
+                idle = fork_idle(cpu);
+                if (IS_ERR(idle)) {
+                        printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
+                        return PTR_ERR(idle);
+                }
+                ci->idle = idle;
+        } else {
+                init_idle(idle, cpu);
+        }
         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
 
         ret = platform_boot_secondary(cpu, idle);
@@ -411,6 +435,7 @@ void __cpuinit secondary_start_kernel(void)
 
         bfin_setup_caches(cpu);
 
+        notify_cpu_starting(cpu);
         /*
          * Calibrate loops per jiffy value.
          * IRQs need to be enabled here - D-cache can be invalidated
@@ -453,8 +478,10 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
         smp_flush_data.start = start;
         smp_flush_data.end = end;
 
-        if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
+        preempt_disable();
+        if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
+        preempt_enable();
 }
 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
 
diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig
new file mode 100644
index 00000000000..26e67f0f005
--- /dev/null
+++ b/arch/c6x/Kconfig
@@ -0,0 +1,174 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config TMS320C6X
+        def_bool y
+        select CLKDEV_LOOKUP
+        select GENERIC_IRQ_SHOW
+        select HAVE_ARCH_TRACEHOOK
+        select HAVE_DMA_API_DEBUG
+        select HAVE_GENERIC_HARDIRQS
+        select HAVE_MEMBLOCK
+        select HAVE_SPARSE_IRQ
+        select OF
+        select OF_EARLY_FLATTREE
+
+config MMU
+        def_bool n
+
+config ZONE_DMA
+        def_bool y
+
+config FPU
+        def_bool n
+
+config HIGHMEM
+        def_bool n
+
+config NUMA
+        def_bool n
+
+config RWSEM_GENERIC_SPINLOCK
+        def_bool y
+
+config RWSEM_XCHGADD_ALGORITHM
+        def_bool n
+
+config GENERIC_CALIBRATE_DELAY
+        def_bool y
+
+config GENERIC_HWEIGHT
+        def_bool y
+
+config GENERIC_CLOCKEVENTS
+        def_bool y
+
+config GENERIC_CLOCKEVENTS_BROADCAST
+        bool
+
+config GENERIC_BUG
+        def_bool y
+
+config COMMON_CLKDEV
+        def_bool y
+
+config C6X_BIG_KERNEL
+        bool "Build a big kernel"
+        help
+          The C6X function call instruction has a limited range of +/- 2MiB.
+          This is sufficient for most kernels, but some kernel configurations
+          with lots of compiled-in functionality may require a larger range
+          for function calls. Use this option to have the compiler generate
+          function calls with 32-bit range. This will make the kernel both
+          larger and slower.
+
+          If unsure, say N.
+
+source "init/Kconfig"
+
+# Use the generic interrupt handling code in kernel/irq/
+
+source "kernel/Kconfig.freezer"
+
+config CMDLINE_BOOL
+        bool "Default bootloader kernel arguments"
+
+config CMDLINE
+        string "Kernel command line"
+        depends on CMDLINE_BOOL
+        default "console=ttyS0,57600"
+        help
+          On some architectures there is currently no way for the boot loader
+          to pass arguments to the kernel. For these architectures, you should
+          supply some command-line options at build time by entering them
+          here.
+
+config CMDLINE_FORCE
+        bool "Force default kernel command string"
+        depends on CMDLINE_BOOL
+        default n
+        help
+          Set this to have arguments from the default kernel command string
+          override those passed by the boot loader.
+
+config CPU_BIG_ENDIAN
+        bool "Build big-endian kernel"
+        default n
+        help
+          Say Y if you plan on running a kernel in big-endian mode.
+          Note that your board must be properly built and your board
+          port must properly enable any big-endian related features
+          of your chipset/board/processor.
+
+config FORCE_MAX_ZONEORDER
+        int "Maximum zone order"
+        default "13"
+        help
+          The kernel memory allocator divides physically contiguous memory
+          blocks into "zones", where each zone is a power of two number of
+          pages.  This option selects the largest power of two that the kernel
+          keeps in the memory allocator.  If you need to allocate very large
+          blocks of physically contiguous memory, then you may need to
+          increase this value.
+
+          This config option is actually maximum order plus one. For example,
+          a value of 11 means that the largest free memory block is 2^10 pages.
+
+menu "Processor type and features"
+
+source "arch/c6x/platforms/Kconfig"
+
+config TMS320C6X_CACHES_ON
+        bool "L2 cache support"
+        default y
+
+config KERNEL_RAM_BASE_ADDRESS
+        hex "Virtual address of memory base"
+        default 0xe0000000 if SOC_TMS320C6455
+        default 0xe0000000 if SOC_TMS320C6457
+        default 0xe0000000 if SOC_TMS320C6472
+        default 0x80000000
+
+source "mm/Kconfig"
+
+source "kernel/Kconfig.preempt"
+
+source "kernel/Kconfig.hz"
+source "kernel/time/Kconfig"
+
+endmenu
+
+menu "Executable file formats"
+
+source "fs/Kconfig.binfmt"
+
+endmenu
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "security/Kconfig"
+
+source "crypto/Kconfig"
+
+source "lib/Kconfig"
+
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config ACCESS_CHECK
+        bool "Check the user pointer address"
+        default y
+        help
+          Usually the pointer transfer from user space is checked to see if its
+          address is in the kernel space.
+
+          Say N here to disable that check to improve the performance.
+
+endmenu
diff --git a/arch/c6x/Makefile b/arch/c6x/Makefile
new file mode 100644
index 00000000000..1d08dd07027
--- /dev/null
+++ b/arch/c6x/Makefile
@@ -0,0 +1,60 @@
+#
+# linux/arch/c6x/Makefile
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+
+cflags-y += -mno-dsbt -msdata=none
+
+cflags-$(CONFIG_C6X_BIG_KERNEL) += -mlong-calls
+
+CFLAGS_MODULE   += -mlong-calls -mno-dsbt -msdata=none
+
+CHECKFLAGS      +=
+
+KBUILD_CFLAGS   += $(cflags-y)
+KBUILD_AFLAGS   += $(cflags-y)
+
+ifdef CONFIG_CPU_BIG_ENDIAN
+KBUILD_CFLAGS   += -mbig-endian
+KBUILD_AFLAGS   += -mbig-endian
+LINKFLAGS       += -mbig-endian
+KBUILD_LDFLAGS  += -mbig-endian
+LDFLAGS += -EB
+endif
+
+head-y          := arch/c6x/kernel/head.o
+core-y          += arch/c6x/kernel/ arch/c6x/mm/ arch/c6x/platforms/
+libs-y          += arch/c6x/lib/
+
+# Default to vmlinux.bin, override when needed
+all: vmlinux.bin
+
+boot := arch/$(ARCH)/boot
+
+# Are we making a dtbImage.<boardname> target? If so, crack out the boardname
+DTB:=$(subst dtbImage.,,$(filter dtbImage.%, $(MAKECMDGOALS)))
+export DTB
+
+ifneq ($(DTB),)
+core-y  += $(boot)/
+endif
+
+# With make 3.82 we cannot mix normal and wildcard targets
+
+vmlinux.bin: vmlinux
+        $(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
+
+dtbImage.%: vmlinux
+        $(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
+
+archclean:
+        $(Q)$(MAKE) $(clean)=$(boot)
+
+define archhelp
+  @echo '  vmlinux.bin     - Binary kernel image (arch/$(ARCH)/boot/vmlinux.bin)'
+  @echo '  dtbImage.<dt>   - ELF image with $(arch)/boot/dts/<dt>.dts linked in'
+  @echo '                  - stripped elf with fdt blob'
+endef
diff --git a/arch/c6x/boot/Makefile b/arch/c6x/boot/Makefile
new file mode 100644
index 00000000000..ecca820e604
--- /dev/null
+++ b/arch/c6x/boot/Makefile
@@ -0,0 +1,30 @@
+#
+# Makefile for bootable kernel images
+#
+
+OBJCOPYFLAGS_vmlinux.bin := -O binary
+$(obj)/vmlinux.bin: vmlinux FORCE
+        $(call if_changed,objcopy)
+
+DTC_FLAGS ?= -p 1024
+
+ifneq ($(DTB),)
+obj-y += linked_dtb.o
+endif
+
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+        $(call cmd,dtc)
+
+quiet_cmd_cp = CP      $< $@$2
+        cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
+
+# Generate builtin.dtb from $(DTB).dtb
+$(obj)/builtin.dtb: $(obj)/$(DTB).dtb
+        $(call if_changed,cp)
+
+$(obj)/linked_dtb.o: $(obj)/builtin.dtb
+
+$(obj)/dtbImage.%: vmlinux
+        $(call if_changed,objcopy)
+
+clean-files := $(obj)/*.dtb
diff --git a/arch/c6x/boot/dts/dsk6455.dts b/arch/c6x/boot/dts/dsk6455.dts
new file mode 100644
index 00000000000..2b71f800618
--- /dev/null
+++ b/arch/c6x/boot/dts/dsk6455.dts
@@ -0,0 +1,62 @@
+/*
+ * arch/c6x/boot/dts/dsk6455.dts
+ *
+ * DSK6455 Evaluation Platform For TMS320C6455
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/include/ "tms320c6455.dtsi"
+
+/ {
+        model = "Spectrum Digital DSK6455";
+        compatible = "spectrum-digital,dsk6455";
+
+        chosen {
+                bootargs = "root=/dev/nfs ip=dhcp rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0xE0000000 0x08000000>;
+        };
+
+        soc {
+                megamod_pic: interrupt-controller@1800000 {
+                        interrupts = < 12 13 14 15 >;
+                };
+
+                emifa@70000000 {
+                        flash@3,0 {
+                                  #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "cfi-flash";
+                                reg = <0x3 0x0 0x400000>;
+                                bank-width = <1>;
+                                device-width = <1>;
+                                partition@0 {
+                                        reg = <0x0 0x400000>;
+                                        label = "NOR";
+                                };
+                        };
+                };
+
+                timer1: timer@2980000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 69 >;
+                };
+
+                clock-controller@029a0000 {
+                        clock-frequency = <50000000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/evmc6457.dts b/arch/c6x/boot/dts/evmc6457.dts
new file mode 100644
index 00000000000..0301eb9a8ff
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6457.dts
@@ -0,0 +1,48 @@
+/*
+ * arch/c6x/boot/dts/evmc6457.dts
+ *
+ * EVMC6457 Evaluation Platform For TMS320C6457
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/include/ "tms320c6457.dtsi"
+
+/ {
+        model = "eInfochips EVMC6457";
+        compatible = "einfochips,evmc6457";
+
+        chosen {
+                bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0xE0000000 0x10000000>;
+        };
+
+        soc {
+                megamod_pic: interrupt-controller@1800000 {
+                       interrupts = < 12 13 14 15 >;
+                };
+
+                timer0: timer@2940000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 67 >;
+                };
+
+                clock-controller@29a0000 {
+                        clock-frequency = <60000000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/evmc6472.dts b/arch/c6x/boot/dts/evmc6472.dts
new file mode 100644
index 00000000000..3e207b449a9
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6472.dts
@@ -0,0 +1,73 @@
+/*
+ * arch/c6x/boot/dts/evmc6472.dts
+ *
+ * EVMC6472 Evaluation Platform For TMS320C6472
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/include/ "tms320c6472.dtsi"
+
+/ {
+        model = "eInfochips EVMC6472";
+        compatible = "einfochips,evmc6472";
+
+        chosen {
+                bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0xE0000000 0x10000000>;
+        };
+
+        soc {
+                megamod_pic: interrupt-controller@1800000 {
+                       interrupts = < 12 13 14 15 >;
+                };
+
+                timer0: timer@25e0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 16 >;
+                };
+
+                timer1: timer@25f0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 16 >;
+                };
+
+                timer2: timer@2600000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 16 >;
+                };
+
+                timer3: timer@2610000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 16 >;
+                };
+
+                timer4: timer@2620000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 16 >;
+                };
+
+                timer5: timer@2630000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 16 >;
+                };
+
+                clock-controller@29a0000 {
+                        clock-frequency = <25000000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/evmc6474.dts b/arch/c6x/boot/dts/evmc6474.dts
new file mode 100644
index 00000000000..4dc291292bc
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6474.dts
@@ -0,0 +1,58 @@
+/*
+ * arch/c6x/boot/dts/evmc6474.dts
+ *
+ * EVMC6474 Evaluation Platform For TMS320C6474
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/include/ "tms320c6474.dtsi"
+
+/ {
+        model = "Spectrum Digital EVMC6474";
+        compatible = "spectrum-digital,evmc6474";
+
+        chosen {
+                bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x08000000>;
+        };
+
+        soc {
+                megamod_pic: interrupt-controller@1800000 {
+                       interrupts = < 12 13 14 15 >;
+                };
+
+                timer3: timer@2940000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 39 >;
+                };
+
+                timer4: timer@2950000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 41 >;
+                };
+
+                timer5: timer@2960000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 43 >;
+                };
+
+                clock-controller@29a0000 {
+                        clock-frequency = <50000000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/tms320c6455.dtsi b/arch/c6x/boot/dts/tms320c6455.dtsi
new file mode 100644
index 00000000000..a804ec1e018
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6455.dtsi
@@ -0,0 +1,96 @@
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "ti,c64x+";
+                        reg = <0>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6455";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                core_pic: interrupt-controller {
+                          interrupt-controller;
+                          #interrupt-cells = <1>;
+                          compatible = "ti,c64x+core-pic";
+                };
+
+                /*
+                 * Megamodule interrupt controller
+                 */
+                megamod_pic: interrupt-controller@1800000 {
+                       compatible = "ti,c64x+megamod-pic";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x1800000 0x1000>;
+                       interrupt-parent = <&core_pic>;
+                };
+
+                cache-controller@1840000 {
+                        compatible = "ti,c64x+cache";
+                        reg = <0x01840000 0x8400>;
+                };
+
+                emifa@70000000 {
+                        compatible = "ti,c64x+emifa", "simple-bus";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        reg = <0x70000000 0x100>;
+                        ranges = <0x2 0x0 0xa0000000 0x00000008
+                                  0x3 0x0 0xb0000000 0x00400000
+                                  0x4 0x0 0xc0000000 0x10000000
+                                  0x5 0x0 0xD0000000 0x10000000>;
+
+                        ti,dscr-dev-enable = <13>;
+                        ti,emifa-burst-priority = <255>;
+                        ti,emifa-ce-config = <0x00240120
+                                              0x00240120
+                                              0x00240122
+                                              0x00240122>;
+                };
+
+                timer1: timer@2980000 {
+                        compatible = "ti,c64x+timer64";
+                        reg = <0x2980000 0x40>;
+                        ti,dscr-dev-enable = <4>;
+                };
+
+                clock-controller@029a0000 {
+                        compatible = "ti,c6455-pll", "ti,c64x+pll";
+                        reg = <0x029a0000 0x200>;
+                        ti,c64x+pll-bypass-delay = <1440>;
+                        ti,c64x+pll-reset-delay = <15360>;
+                        ti,c64x+pll-lock-delay = <24000>;
+                };
+
+                device-state-config-regs@2a80000 {
+                        compatible = "ti,c64x+dscr";
+                        reg = <0x02a80000 0x41000>;
+
+                        ti,dscr-devstat = <0>;
+                        ti,dscr-silicon-rev = <8 28 0xf>;
+                        ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
+
+                        ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
+                        ti,dscr-devstate-ctl-regs =
+                                 <0 12 0x40008 1 0  0  2
+                                  12 1 0x40008 3 0 30  2
+                                  13 2 0x4002c 1 0xffffffff 0 1>;
+                        ti,dscr-devstate-stat-regs =
+                                <0 10 0x40014 1 0  0  3
+                                 10 2 0x40018 1 0  0  3>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/tms320c6457.dtsi b/arch/c6x/boot/dts/tms320c6457.dtsi
new file mode 100644
index 00000000000..35f40709a71
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6457.dtsi
@@ -0,0 +1,68 @@
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "ti,c64x+";
+                        reg = <0>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6457";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                core_pic: interrupt-controller {
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        compatible = "ti,c64x+core-pic";
+                };
+
+                megamod_pic: interrupt-controller@1800000 {
+                        compatible = "ti,c64x+megamod-pic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&core_pic>;
+                        reg = <0x1800000 0x1000>;
+                };
+
+                cache-controller@1840000 {
+                        compatible = "ti,c64x+cache";
+                        reg = <0x01840000 0x8400>;
+                };
+
+                device-state-controller@2880800 {
+                        compatible = "ti,c64x+dscr";
+                        reg = <0x02880800 0x400>;
+
+                        ti,dscr-devstat = <0x20>;
+                        ti,dscr-silicon-rev = <0x18 28 0xf>;
+                        ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
+                                                 0x118 0 0 1 2>;
+                        ti,dscr-kick-regs = <0x38 0x83E70B13
+                                             0x3c 0x95A4F1E0>;
+                };
+
+                timer0: timer@2940000 {
+                        compatible = "ti,c64x+timer64";
+                        reg = <0x2940000 0x40>;
+                };
+
+                clock-controller@29a0000 {
+                        compatible = "ti,c6457-pll", "ti,c64x+pll";
+                        reg = <0x029a0000 0x200>;
+                        ti,c64x+pll-bypass-delay = <300>;
+                        ti,c64x+pll-reset-delay = <24000>;
+                        ti,c64x+pll-lock-delay = <50000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/tms320c6472.dtsi b/arch/c6x/boot/dts/tms320c6472.dtsi
new file mode 100644
index 00000000000..b488aaec65c
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6472.dtsi
@@ -0,0 +1,134 @@
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        model = "ti,c64x+";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        model = "ti,c64x+";
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        model = "ti,c64x+";
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        model = "ti,c64x+";
+                };
+                cpu@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        model = "ti,c64x+";
+                };
+                cpu@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        model = "ti,c64x+";
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6472";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                core_pic: interrupt-controller {
+                        compatible = "ti,c64x+core-pic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                megamod_pic: interrupt-controller@1800000 {
+                       compatible = "ti,c64x+megamod-pic";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x1800000 0x1000>;
+                       interrupt-parent = <&core_pic>;
+                };
+
+                cache-controller@1840000 {
+                        compatible = "ti,c64x+cache";
+                        reg = <0x01840000 0x8400>;
+                };
+
+                timer0: timer@25e0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x01 >;
+                        reg = <0x25e0000 0x40>;
+                };
+
+                timer1: timer@25f0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x02 >;
+                        reg = <0x25f0000 0x40>;
+                };
+
+                timer2: timer@2600000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x04 >;
+                        reg = <0x2600000 0x40>;
+                };
+
+                timer3: timer@2610000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x08 >;
+                        reg = <0x2610000 0x40>;
+                };
+
+                timer4: timer@2620000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x10 >;
+                        reg = <0x2620000 0x40>;
+                };
+
+                timer5: timer@2630000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x20 >;
+                        reg = <0x2630000 0x40>;
+                };
+
+                clock-controller@29a0000 {
+                        compatible = "ti,c6472-pll", "ti,c64x+pll";
+                        reg = <0x029a0000 0x200>;
+                        ti,c64x+pll-bypass-delay = <200>;
+                        ti,c64x+pll-reset-delay = <12000>;
+                        ti,c64x+pll-lock-delay = <80000>;
+                };
+
+                device-state-controller@2a80000 {
+                        compatible = "ti,c64x+dscr";
+                        reg = <0x02a80000 0x1000>;
+
+                        ti,dscr-devstat = <0>;
+                        ti,dscr-silicon-rev = <0x70c 16 0xff>;
+
+                        ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
+                                                 0x704 5 6 0 0>;
+
+                        ti,dscr-rmii-resets = <0x208 1
+                                               0x20c 1>;
+
+                        ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
+                                               0x40c 0x420 0xbea7
+                                               0x41c 0x420 0xbea7>;
+
+                        ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
+
+                        ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/tms320c6474.dtsi b/arch/c6x/boot/dts/tms320c6474.dtsi
new file mode 100644
index 00000000000..cc601bf348a
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6474.dtsi
@@ -0,0 +1,89 @@
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        model = "ti,c64x+";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        model = "ti,c64x+";
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        model = "ti,c64x+";
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6474";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                core_pic: interrupt-controller {
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        compatible = "ti,c64x+core-pic";
+                };
+
+                megamod_pic: interrupt-controller@1800000 {
+                       compatible = "ti,c64x+megamod-pic";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x1800000 0x1000>;
+                       interrupt-parent = <&core_pic>;
+                };
+
+                cache-controller@1840000 {
+                        compatible = "ti,c64x+cache";
+                        reg = <0x01840000 0x8400>;
+                };
+
+                timer3: timer@2940000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x04 >;
+                        reg = <0x2940000 0x40>;
+                };
+
+                timer4: timer@2950000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x02 >;
+                        reg = <0x2950000 0x40>;
+                };
+
+                timer5: timer@2960000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x01 >;
+                        reg = <0x2960000 0x40>;
+                };
+
+                device-state-controller@2880800 {
+                        compatible = "ti,c64x+dscr";
+                        reg = <0x02880800 0x400>;
+
+                        ti,dscr-devstat = <0x004>;
+                        ti,dscr-silicon-rev = <0x014 28 0xf>;
+                        ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
+                                                 0x38 0 0 1 2>;
+                };
+
+                clock-controller@29a0000 {
+                        compatible = "ti,c6474-pll", "ti,c64x+pll";
+                        reg = <0x029a0000 0x200>;
+                        ti,c64x+pll-bypass-delay = <120>;
+                        ti,c64x+pll-reset-delay = <30000>;
+                        ti,c64x+pll-lock-delay = <60000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/linked_dtb.S b/arch/c6x/boot/linked_dtb.S
new file mode 100644
index 00000000000..57a4454eaec
--- /dev/null
+++ b/arch/c6x/boot/linked_dtb.S
@@ -0,0 +1,2 @@
+.section __fdt_blob,"a"
+.incbin "arch/c6x/boot/builtin.dtb"
diff --git a/arch/c6x/configs/dsk6455_defconfig b/arch/c6x/configs/dsk6455_defconfig
new file mode 100644
index 00000000000..4663487c67a
--- /dev/null
+++ b/arch/c6x/configs/dsk6455_defconfig
@@ -0,0 +1,44 @@
+CONFIG_SOC_TMS320C6455=y
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+# CONFIG_FUTEX is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=17000
+CONFIG_MISC_DEVICES=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_CRC16=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_MTD=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
diff --git a/arch/c6x/configs/evmc6457_defconfig b/arch/c6x/configs/evmc6457_defconfig
new file mode 100644
index 00000000000..bba40e195ec
--- /dev/null
+++ b/arch/c6x/configs/evmc6457_defconfig
@@ -0,0 +1,41 @@
+CONFIG_SOC_TMS320C6457=y
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+# CONFIG_FUTEX is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+CONFIG_BOARD_EVM6457=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=17000
+CONFIG_MISC_DEVICES=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_CRC16=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/configs/evmc6472_defconfig b/arch/c6x/configs/evmc6472_defconfig
new file mode 100644
index 00000000000..8c46155f6d3
--- /dev/null
+++ b/arch/c6x/configs/evmc6472_defconfig
@@ -0,0 +1,42 @@
+CONFIG_SOC_TMS320C6472=y
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+# CONFIG_FUTEX is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_FORCE is not set
+CONFIG_BOARD_EVM6472=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=17000
+CONFIG_MISC_DEVICES=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_CRC16=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/configs/evmc6474_defconfig b/arch/c6x/configs/evmc6474_defconfig
new file mode 100644
index 00000000000..15533f63231
--- /dev/null
+++ b/arch/c6x/configs/evmc6474_defconfig
@@ -0,0 +1,42 @@
+CONFIG_SOC_TMS320C6474=y
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+# CONFIG_FUTEX is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_FORCE is not set
+CONFIG_BOARD_EVM6474=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=17000
+CONFIG_MISC_DEVICES=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_CRC16=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild
new file mode 100644
index 00000000000..13dcf78adf9
--- /dev/null
+++ b/arch/c6x/include/asm/Kbuild
@@ -0,0 +1,54 @@
+include include/asm-generic/Kbuild.asm
+
+generic-y += atomic.h
+generic-y += auxvec.h
+generic-y += bitsperlong.h
+generic-y += bug.h
+generic-y += bugs.h
+generic-y += cputime.h
+generic-y += current.h
+generic-y += device.h
+generic-y += div64.h
+generic-y += dma.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += fb.h
+generic-y += fcntl.h
+generic-y += futex.h
+generic-y += hw_irq.h
+generic-y += io.h
+generic-y += ioctl.h
+generic-y += ioctls.h
+generic-y += ipcbuf.h
+generic-y += irq_regs.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += local.h
+generic-y += mman.h
+generic-y += mmu_context.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += pci.h
+generic-y += percpu.h
+generic-y += pgalloc.h
+generic-y += poll.h
+generic-y += posix_types.h
+generic-y += resource.h
+generic-y += scatterlist.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += shmbuf.h
+generic-y += shmparam.h
+generic-y += siginfo.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += stat.h
+generic-y += statfs.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += tlbflush.h
+generic-y += topology.h
+generic-y += types.h
+generic-y += ucontext.h
+generic-y += user.h
+generic-y += vga.h
diff --git a/arch/c6x/include/asm/asm-offsets.h b/arch/c6x/include/asm/asm-offsets.h
new file mode 100644
index 00000000000..d370ee36a18
--- /dev/null
+++ b/arch/c6x/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/c6x/include/asm/bitops.h b/arch/c6x/include/asm/bitops.h
new file mode 100644
index 00000000000..39ab7e874d9
--- /dev/null
+++ b/arch/c6x/include/asm/bitops.h
@@ -0,0 +1,105 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_BITOPS_H
+#define _ASM_C6X_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <linux/bitops.h>
+
+#include <asm/system.h>
+#include <asm/byteorder.h>
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit()  barrier()
+
+/*
+ * We are lucky, DSP is perfect for bitops: do it in 3 cycles
+ */
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ * Note __ffs(0) = undef, __ffs(1) = 0, __ffs(0x80000000) = 31.
+ *
+ */
+static inline unsigned long __ffs(unsigned long x)
+{
+        asm (" bitr  .M1  %0,%0\n"
+             " nop\n"
+             " lmbd  .L1  1,%0,%0\n"
+             : "+a"(x));
+
+        return x;
+}
+
+/*
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+#define ffz(x) __ffs(~(x))
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static inline int fls(int x)
+{
+        if (!x)
+                return 0;
+
+        asm (" lmbd  .L1  1,%0,%0\n" : "+a"(x));
+
+        return 32 - x;
+}
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ * Note ffs(0) = 0, ffs(1) = 1, ffs(0x80000000) = 32.
+ */
+static inline int ffs(int x)
+{
+        if (!x)
+                return 0;
+
+        return __ffs(x) + 1;
+}
+
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/find.h>
+
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+
+#include <asm-generic/bitops/atomic.h>
+#include <asm-generic/bitops/non-atomic.h>
+#include <asm-generic/bitops/le.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_C6X_BITOPS_H */
diff --git a/arch/c6x/include/asm/byteorder.h b/arch/c6x/include/asm/byteorder.h
new file mode 100644
index 00000000000..166038db342
--- /dev/null
+++ b/arch/c6x/include/asm/byteorder.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_C6X_BYTEORDER_H
+#define _ASM_C6X_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef _BIG_ENDIAN
+#include <linux/byteorder/big_endian.h>
+#else /* _BIG_ENDIAN */
+#include <linux/byteorder/little_endian.h>
+#endif /* _BIG_ENDIAN */
+
+#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
new file mode 100644
index 00000000000..6d521d96d94
--- /dev/null
+++ b/arch/c6x/include/asm/cache.h
@@ -0,0 +1,90 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_CACHE_H
+#define _ASM_C6X_CACHE_H
+
+#include <linux/irqflags.h>
+
+/*
+ * Cache line size
+ */
+#define L1D_CACHE_BYTES   64
+#define L1P_CACHE_BYTES   32
+#define L2_CACHE_BYTES    128
+
+/*
+ * L2 used as cache
+ */
+#define L2MODE_SIZE       L2MODE_256K_CACHE
+
+/*
+ * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
+ * the L2 line size
+ */
+#define L1_CACHE_BYTES        L2_CACHE_BYTES
+
+#define L2_CACHE_ALIGN_LOW(x) \
+        (((x) & ~(L2_CACHE_BYTES - 1)))
+#define L2_CACHE_ALIGN_UP(x) \
+        (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
+#define L2_CACHE_ALIGN_CNT(x) \
+        (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
+
+#define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
+#define ARCH_SLAB_MINALIGN      L1_CACHE_BYTES
+
+/*
+ * This is the granularity of hardware cacheability control.
+ */
+#define CACHEABILITY_ALIGN      0x01000000
+
+/*
+ * Align a physical address to MAR regions
+ */
+#define CACHE_REGION_START(v) \
+        (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
+#define CACHE_REGION_END(v) \
+        (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
+
+extern void __init c6x_cache_init(void);
+
+extern void enable_caching(unsigned long start, unsigned long end);
+extern void disable_caching(unsigned long start, unsigned long end);
+
+extern void L1_cache_off(void);
+extern void L1_cache_on(void);
+
+extern void L1P_cache_global_invalidate(void);
+extern void L1D_cache_global_invalidate(void);
+extern void L1D_cache_global_writeback(void);
+extern void L1D_cache_global_writeback_invalidate(void);
+extern void L2_cache_set_mode(unsigned int mode);
+extern void L2_cache_global_writeback_invalidate(void);
+extern void L2_cache_global_writeback(void);
+
+extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
+extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
+extern void L1D_cache_block_writeback_invalidate(unsigned int start,
+                                                 unsigned int end);
+extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
+extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
+extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
+extern void L2_cache_block_writeback_invalidate(unsigned int start,
+                                                unsigned int end);
+extern void L2_cache_block_invalidate_nowait(unsigned int start,
+                                             unsigned int end);
+extern void L2_cache_block_writeback_nowait(unsigned int start,
+                                            unsigned int end);
+
+extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
+                                                       unsigned int end);
+
+#endif /* _ASM_C6X_CACHE_H */
diff --git a/arch/c6x/include/asm/cacheflush.h b/arch/c6x/include/asm/cacheflush.h
new file mode 100644
index 00000000000..df5db90dbe5
--- /dev/null
+++ b/arch/c6x/include/asm/cacheflush.h
@@ -0,0 +1,65 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_CACHEFLUSH_H
+#define _ASM_C6X_CACHEFLUSH_H
+
+#include <linux/spinlock.h>
+
+#include <asm/setup.h>
+#include <asm/cache.h>
+#include <asm/mman.h>
+#include <asm/page.h>
+#include <asm/string.h>
+
+/*
+ * virtually-indexed cache management (our cache is physically indexed)
+ */
+#define flush_cache_all()                       do {} while (0)
+#define flush_cache_mm(mm)                      do {} while (0)
+#define flush_cache_dup_mm(mm)                  do {} while (0)
+#define flush_cache_range(mm, start, end)       do {} while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do {} while (0)
+#define flush_cache_vmap(start, end)            do {} while (0)
+#define flush_cache_vunmap(start, end)          do {} while (0)
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
+#define flush_dcache_page(page)                 do {} while (0)
+#define flush_dcache_mmap_lock(mapping)         do {} while (0)
+#define flush_dcache_mmap_unlock(mapping)       do {} while (0)
+
+/*
+ * physically-indexed cache management
+ */
+#define flush_icache_range(s, e)                                  \
+do {                                                              \
+                L1D_cache_block_writeback((s), (e));              \
+                L1P_cache_block_invalidate((s), (e));             \
+} while (0)
+
+#define flush_icache_page(vma, page)                                      \
+do {                                                              \
+        if ((vma)->vm_flags & PROT_EXEC)                                  \
+                L1D_cache_block_writeback_invalidate(page_address(page),  \
+                        (unsigned long) page_address(page) + PAGE_SIZE)); \
+                L1P_cache_block_invalidate(page_address(page),            \
+                        (unsigned long) page_address(page) + PAGE_SIZE)); \
+} while (0)
+
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do {                                                 \
+        memcpy(dst, src, len);                       \
+        flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
+} while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+#endif /* _ASM_C6X_CACHEFLUSH_H */
diff --git a/arch/c6x/include/asm/checksum.h b/arch/c6x/include/asm/checksum.h
new file mode 100644
index 00000000000..7246816d6e4
--- /dev/null
+++ b/arch/c6x/include/asm/checksum.h
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_CHECKSUM_H
+#define _ASM_C6X_CHECKSUM_H
+
+static inline __wsum
+csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
+                   unsigned short proto, __wsum sum)
+{
+        unsigned long long tmp;
+
+        asm ("add     .d1   %1,%5,%1\n"
+             "|| addu .l1   %3,%4,%0\n"
+             "addu    .l1   %2,%0,%0\n"
+#ifndef CONFIG_CPU_BIG_ENDIAN
+             "|| shl  .s1   %1,8,%1\n"
+#endif
+             "addu    .l1   %1,%0,%0\n"
+             "add     .l1   %P0,%p0,%2\n"
+             : "=&a"(tmp), "+a"(len), "+a"(sum)
+             : "a" (saddr), "a" (daddr), "a" (proto));
+        return sum;
+}
+#define csum_tcpudp_nofold csum_tcpudp_nofold
+
+#include <asm-generic/checksum.h>
+
+#endif /* _ASM_C6X_CHECKSUM_H */
diff --git a/arch/c6x/include/asm/clkdev.h b/arch/c6x/include/asm/clkdev.h
new file mode 100644
index 00000000000..76a070b1c2e
--- /dev/null
+++ b/arch/c6x/include/asm/clkdev.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_CLKDEV_H
+#define _ASM_CLKDEV_H
+
+#include <linux/slab.h>
+
+struct clk;
+
+static inline int __clk_get(struct clk *clk)
+{
+        return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+        return kzalloc(size, GFP_KERNEL);
+}
+
+#endif /* _ASM_CLKDEV_H */
diff --git a/arch/c6x/include/asm/clock.h b/arch/c6x/include/asm/clock.h
new file mode 100644
index 00000000000..bcf42b2b4b1
--- /dev/null
+++ b/arch/c6x/include/asm/clock.h
@@ -0,0 +1,148 @@
+/*
+ * TI C64X clock definitions
+ *
+ * Copyright (C) 2010, 2011 Texas Instruments.
+ * Contributed by: Mark Salter <msalter@redhat.com>
+ *
+ * Copied heavily from arm/mach-davinci/clock.h, so:
+ *
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ASM_C6X_CLOCK_H
+#define _ASM_C6X_CLOCK_H
+
+#ifndef __ASSEMBLER__
+
+#include <linux/list.h>
+
+/* PLL/Reset register offsets */
+#define PLLCTL          0x100
+#define PLLM            0x110
+#define PLLPRE          0x114
+#define PLLDIV1         0x118
+#define PLLDIV2         0x11c
+#define PLLDIV3         0x120
+#define PLLPOST         0x128
+#define PLLCMD          0x138
+#define PLLSTAT         0x13c
+#define PLLALNCTL       0x140
+#define PLLDCHANGE      0x144
+#define PLLCKEN         0x148
+#define PLLCKSTAT       0x14c
+#define PLLSYSTAT       0x150
+#define PLLDIV4         0x160
+#define PLLDIV5         0x164
+#define PLLDIV6         0x168
+#define PLLDIV7         0x16c
+#define PLLDIV8         0x170
+#define PLLDIV9         0x174
+#define PLLDIV10        0x178
+#define PLLDIV11        0x17c
+#define PLLDIV12        0x180
+#define PLLDIV13        0x184
+#define PLLDIV14        0x188
+#define PLLDIV15        0x18c
+#define PLLDIV16        0x190
+
+/* PLLM register bits */
+#define PLLM_PLLM_MASK  0xff
+#define PLLM_VAL(x)     ((x) - 1)
+
+/* PREDIV register bits */
+#define PLLPREDIV_EN    BIT(15)
+#define PLLPREDIV_VAL(x) ((x) - 1)
+
+/* PLLCTL register bits */
+#define PLLCTL_PLLEN    BIT(0)
+#define PLLCTL_PLLPWRDN BIT(1)
+#define PLLCTL_PLLRST   BIT(3)
+#define PLLCTL_PLLDIS   BIT(4)
+#define PLLCTL_PLLENSRC BIT(5)
+#define PLLCTL_CLKMODE  BIT(8)
+
+/* PLLCMD register bits */
+#define PLLCMD_GOSTAT   BIT(0)
+
+/* PLLSTAT register bits */
+#define PLLSTAT_GOSTAT  BIT(0)
+
+/* PLLDIV register bits */
+#define PLLDIV_EN       BIT(15)
+#define PLLDIV_RATIO_MASK 0x1f
+#define PLLDIV_RATIO(x) ((x) - 1)
+
+struct pll_data;
+
+struct clk {
+        struct list_head        node;
+        struct module           *owner;
+        const char              *name;
+        unsigned long           rate;
+        int                     usecount;
+        u32                     flags;
+        struct clk              *parent;
+        struct list_head        children;       /* list of children */
+        struct list_head        childnode;      /* parent's child list node */
+        struct pll_data         *pll_data;
+        u32                     div;
+        unsigned long (*recalc) (struct clk *);
+        int (*set_rate) (struct clk *clk, unsigned long rate);
+        int (*round_rate) (struct clk *clk, unsigned long rate);
+};
+
+/* Clock flags: SoC-specific flags start at BIT(16) */
+#define ALWAYS_ENABLED          BIT(1)
+#define CLK_PLL                 BIT(2) /* PLL-derived clock */
+#define PRE_PLL                 BIT(3) /* source is before PLL mult/div */
+#define FIXED_DIV_PLL           BIT(4) /* fixed divisor from PLL */
+#define FIXED_RATE_PLL          BIT(5) /* fixed ouput rate PLL */
+
+#define MAX_PLL_SYSCLKS 16
+
+struct pll_data {
+        void __iomem *base;
+        u32 num;
+        u32 flags;
+        u32 input_rate;
+        u32 bypass_delay; /* in loops */
+        u32 reset_delay;  /* in loops */
+        u32 lock_delay;   /* in loops */
+        struct clk sysclks[MAX_PLL_SYSCLKS + 1];
+};
+
+/* pll_data flag bit */
+#define PLL_HAS_PRE     BIT(0)
+#define PLL_HAS_MUL     BIT(1)
+#define PLL_HAS_POST    BIT(2)
+
+#define CLK(dev, con, ck)       \
+        {                       \
+                .dev_id = dev,  \
+                .con_id = con,  \
+                .clk = ck,      \
+        }                       \
+
+extern void c6x_clks_init(struct clk_lookup *clocks);
+extern int clk_register(struct clk *clk);
+extern void clk_unregister(struct clk *clk);
+extern void c64x_setup_clocks(void);
+
+extern struct pll_data c6x_soc_pll1;
+
+extern struct clk clkin1;
+extern struct clk c6x_core_clk;
+extern struct clk c6x_i2c_clk;
+extern struct clk c6x_watchdog_clk;
+extern struct clk c6x_mcbsp1_clk;
+extern struct clk c6x_mcbsp2_clk;
+extern struct clk c6x_mdio_clk;
+
+#endif
+
+#endif /* _ASM_C6X_CLOCK_H */
diff --git a/arch/c6x/include/asm/delay.h b/arch/c6x/include/asm/delay.h
new file mode 100644
index 00000000000..f314c2e9eb5
--- /dev/null
+++ b/arch/c6x/include/asm/delay.h
@@ -0,0 +1,67 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_DELAY_H
+#define _ASM_C6X_DELAY_H
+
+#include <linux/kernel.h>
+
+extern unsigned int ticks_per_ns_scaled;
+
+static inline void __delay(unsigned long loops)
+{
+        uint32_t tmp;
+
+        /* 6 cycles per loop */
+        asm volatile ("        mv    .s1  %0,%1\n"
+                      "0: [%1] b     .s1  0b\n"
+                      "        add   .l1  -6,%0,%0\n"
+                      "        cmplt .l1  1,%0,%1\n"
+                      "        nop   3\n"
+                      : "+a"(loops), "=A"(tmp));
+}
+
+static inline void _c6x_tickdelay(unsigned int x)
+{
+        uint32_t cnt, endcnt;
+
+        asm volatile ("        mvc   .s2   TSCL,%0\n"
+                      "        add   .s2x  %0,%1,%2\n"
+                      " ||     mvk   .l2   1,B0\n"
+                      "0: [B0] b     .s2   0b\n"
+                      "        mvc   .s2   TSCL,%0\n"
+                      "        sub   .s2   %0,%2,%0\n"
+                      "        cmpgt .l2   0,%0,B0\n"
+                      "        nop   2\n"
+                      : "=b"(cnt), "+a"(x), "=b"(endcnt) : : "B0");
+}
+
+/* use scaled math to avoid slow division */
+#define C6X_NDELAY_SCALE 10
+
+static inline void _ndelay(unsigned int n)
+{
+        _c6x_tickdelay((ticks_per_ns_scaled * n) >> C6X_NDELAY_SCALE);
+}
+
+static inline void _udelay(unsigned int n)
+{
+        while (n >= 10) {
+                _ndelay(10000);
+                n -= 10;
+        }
+        while (n-- > 0)
+                _ndelay(1000);
+}
+
+#define udelay(x) _udelay((unsigned int)(x))
+#define ndelay(x) _ndelay((unsigned int)(x))
+
+#endif /* _ASM_C6X_DELAY_H */
diff --git a/arch/c6x/include/asm/dma-mapping.h b/arch/c6x/include/asm/dma-mapping.h
new file mode 100644
index 00000000000..03579fd99db
--- /dev/null
+++ b/arch/c6x/include/asm/dma-mapping.h
@@ -0,0 +1,91 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot <aurelien.jacquiot@ti.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#ifndef _ASM_C6X_DMA_MAPPING_H
+#define _ASM_C6X_DMA_MAPPING_H
+
+#include <linux/dma-debug.h>
+#include <asm-generic/dma-coherent.h>
+
+#define dma_supported(d, m)     1
+
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
+                return -EIO;
+
+        *dev->dma_mask = dma_mask;
+
+        return 0;
+}
+
+/*
+ * DMA errors are defined by all-bits-set in the DMA address.
+ */
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return dma_addr == ~0;
+}
+
+extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                                 size_t size, enum dma_data_direction dir);
+
+extern void dma_unmap_single(struct device *dev, dma_addr_t handle,
+                             size_t size, enum dma_data_direction dir);
+
+extern int dma_map_sg(struct device *dev, struct scatterlist *sglist,
+                      int nents, enum dma_data_direction direction);
+
+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
+                         int nents, enum dma_data_direction direction);
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction dir)
+{
+        dma_addr_t handle;
+
+        handle = dma_map_single(dev, page_address(page) + offset, size, dir);
+
+        debug_dma_map_page(dev, page, offset, size, dir, handle, false);
+
+        return handle;
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
+{
+        dma_unmap_single(dev, handle, size, dir);
+
+        debug_dma_unmap_page(dev, handle, size, dir, false);
+}
+
+extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
+                                    size_t size, enum dma_data_direction dir);
+
+extern void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
+                                       size_t size,
+                                       enum dma_data_direction dir);
+
+extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction dir);
+
+extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                                   int nents, enum dma_data_direction dir);
+
+extern void coherent_mem_init(u32 start, u32 size);
+extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
+extern void dma_free_coherent(struct device *, size_t, void *, dma_addr_t);
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent((d), (s), (h), (f))
+#define dma_free_noncoherent(d, s, v, h)  dma_free_coherent((d), (s), (v), (h))
+
+#endif  /* _ASM_C6X_DMA_MAPPING_H */
diff --git a/arch/c6x/include/asm/dscr.h b/arch/c6x/include/asm/dscr.h
new file mode 100644
index 00000000000..561ba833204
--- /dev/null
+++ b/arch/c6x/include/asm/dscr.h
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#ifndef _ASM_C6X_DSCR_H
+#define _ASM_C6X_DSCR_H
+
+enum dscr_devstate_t {
+        DSCR_DEVSTATE_ENABLED,
+        DSCR_DEVSTATE_DISABLED,
+};
+
+/*
+ * Set the device state of the device with the given ID.
+ *
+ * Individual drivers should use this to enable or disable the
+ * hardware device. The devid used to identify the device being
+ * controlled should be a property in the device's tree node.
+ */
+extern void dscr_set_devstate(int devid, enum dscr_devstate_t state);
+
+/*
+ * Assert or de-assert an RMII reset.
+ */
+extern void dscr_rmii_reset(int id, int assert);
+
+extern void dscr_probe(void);
+
+#endif /* _ASM_C6X_DSCR_H */
diff --git a/arch/c6x/include/asm/elf.h b/arch/c6x/include/asm/elf.h
new file mode 100644
index 00000000000..d57865ba2c4
--- /dev/null
+++ b/arch/c6x/include/asm/elf.h
@@ -0,0 +1,113 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_ELF_H
+#define _ASM_C6X_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+#include <asm/ptrace.h>
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_fpreg_t;
+
+#define ELF_NGREG  58
+#define ELF_NFPREG 1
+
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_TI_C6000)
+
+#define elf_check_const_displacement(x) (1)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#ifdef __LITTLE_ENDIAN__
+#define ELF_DATA        ELFDATA2LSB
+#else
+#define ELF_DATA        ELFDATA2MSB
+#endif
+
+#define ELF_CLASS       ELFCLASS32
+#define ELF_ARCH        EM_TI_C6000
+
+/* Nothing for now. Need to setup DP... */
+#define ELF_PLAT_INIT(_r)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
+
+#define ELF_CORE_COPY_REGS(_dest, _regs)                \
+        memcpy((char *) &_dest, (char *) _regs,         \
+        sizeof(struct pt_regs));
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  */
+
+#define ELF_HWCAP       (0)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.  */
+
+#define ELF_PLATFORM  (NULL)
+
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+
+/* C6X specific section types */
+#define SHT_C6000_UNWIND        0x70000001
+#define SHT_C6000_PREEMPTMAP    0x70000002
+#define SHT_C6000_ATTRIBUTES    0x70000003
+
+/* C6X specific DT_ tags */
+#define DT_C6000_DSBT_BASE      0x70000000
+#define DT_C6000_DSBT_SIZE      0x70000001
+#define DT_C6000_PREEMPTMAP     0x70000002
+#define DT_C6000_DSBT_INDEX     0x70000003
+
+/* C6X specific relocs */
+#define R_C6000_NONE            0
+#define R_C6000_ABS32           1
+#define R_C6000_ABS16           2
+#define R_C6000_ABS8            3
+#define R_C6000_PCR_S21         4
+#define R_C6000_PCR_S12         5
+#define R_C6000_PCR_S10         6
+#define R_C6000_PCR_S7          7
+#define R_C6000_ABS_S16         8
+#define R_C6000_ABS_L16         9
+#define R_C6000_ABS_H16         10
+#define R_C6000_SBR_U15_B       11
+#define R_C6000_SBR_U15_H       12
+#define R_C6000_SBR_U15_W       13
+#define R_C6000_SBR_S16         14
+#define R_C6000_SBR_L16_B       15
+#define R_C6000_SBR_L16_H       16
+#define R_C6000_SBR_L16_W       17
+#define R_C6000_SBR_H16_B       18
+#define R_C6000_SBR_H16_H       19
+#define R_C6000_SBR_H16_W       20
+#define R_C6000_SBR_GOT_U15_W   21
+#define R_C6000_SBR_GOT_L16_W   22
+#define R_C6000_SBR_GOT_H16_W   23
+#define R_C6000_DSBT_INDEX      24
+#define R_C6000_PREL31          25
+#define R_C6000_COPY            26
+#define R_C6000_ALIGN           253
+#define R_C6000_FPHEAD          254
+#define R_C6000_NOCMP           255
+
+#endif /*_ASM_C6X_ELF_H */
diff --git a/arch/c6x/include/asm/ftrace.h b/arch/c6x/include/asm/ftrace.h
new file mode 100644
index 00000000000..3701958d3d1
--- /dev/null
+++ b/arch/c6x/include/asm/ftrace.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_C6X_FTRACE_H
+#define _ASM_C6X_FTRACE_H
+
+/* empty */
+
+#endif /* _ASM_C6X_FTRACE_H */
diff --git a/arch/c6x/include/asm/hardirq.h b/arch/c6x/include/asm/hardirq.h
new file mode 100644
index 00000000000..9621954f98f
--- /dev/null
+++ b/arch/c6x/include/asm/hardirq.h
@@ -0,0 +1,20 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef _ASM_C6X_HARDIRQ_H
+#define _ASM_C6X_HARDIRQ_H
+
+extern void ack_bad_irq(int irq);
+#define ack_bad_irq ack_bad_irq
+
+#include <asm-generic/hardirq.h>
+
+#endif /* _ASM_C6X_HARDIRQ_H */
diff --git a/arch/c6x/include/asm/irq.h b/arch/c6x/include/asm/irq.h
new file mode 100644
index 00000000000..a6ae3c9d9c4
--- /dev/null
+++ b/arch/c6x/include/asm/irq.h
@@ -0,0 +1,302 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Large parts taken directly from powerpc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_IRQ_H
+#define _ASM_C6X_IRQ_H
+
+#include <linux/threads.h>
+#include <linux/list.h>
+#include <linux/radix-tree.h>
+#include <asm/percpu.h>
+
+#define irq_canonicalize(irq)  (irq)
+
+/*
+ * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
+ * are reserved. The remaining 12 vectors are used to route SoC interrupts.
+ * These interrupt vectors are prioritized with IRQ 4 having the highest
+ * priority and IRQ 15 having the lowest.
+ *
+ * The C64x+ megamodule provides a PIC which combines SoC IRQ sources into a
+ * single core IRQ vector. There are four combined sources, each of which
+ * feed into one of the 12 general interrupt vectors. The remaining 8 vectors
+ * can each route a single SoC interrupt directly.
+ */
+#define NR_PRIORITY_IRQS 16
+
+#define NR_IRQS_LEGACY  NR_PRIORITY_IRQS
+
+/* Total number of virq in the platform */
+#define NR_IRQS         256
+
+/* This number is used when no interrupt has been assigned */
+#define NO_IRQ          0
+
+/* This type is the placeholder for a hardware interrupt number. It has to
+ * be big enough to enclose whatever representation is used by a given
+ * platform.
+ */
+typedef unsigned long irq_hw_number_t;
+
+/* Interrupt controller "host" data structure. This could be defined as a
+ * irq domain controller. That is, it handles the mapping between hardware
+ * and virtual interrupt numbers for a given interrupt domain. The host
+ * structure is generally created by the PIC code for a given PIC instance
+ * (though a host can cover more than one PIC if they have a flat number
+ * model). It's the host callbacks that are responsible for setting the
+ * irq_chip on a given irq_desc after it's been mapped.
+ *
+ * The host code and data structures are fairly agnostic to the fact that
+ * we use an open firmware device-tree. We do have references to struct
+ * device_node in two places: in irq_find_host() to find the host matching
+ * a given interrupt controller node, and of course as an argument to its
+ * counterpart host->ops->match() callback. However, those are treated as
+ * generic pointers by the core and the fact that it's actually a device-node
+ * pointer is purely a convention between callers and implementation. This
+ * code could thus be used on other architectures by replacing those two
+ * by some sort of arch-specific void * "token" used to identify interrupt
+ * controllers.
+ */
+struct irq_host;
+struct radix_tree_root;
+struct device_node;
+
+/* Functions below are provided by the host and called whenever a new mapping
+ * is created or an old mapping is disposed. The host can then proceed to
+ * whatever internal data structures management is required. It also needs
+ * to setup the irq_desc when returning from map().
+ */
+struct irq_host_ops {
+        /* Match an interrupt controller device node to a host, returns
+         * 1 on a match
+         */
+        int (*match)(struct irq_host *h, struct device_node *node);
+
+        /* Create or update a mapping between a virtual irq number and a hw
+         * irq number. This is called only once for a given mapping.
+         */
+        int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
+
+        /* Dispose of such a mapping */
+        void (*unmap)(struct irq_host *h, unsigned int virq);
+
+        /* Translate device-tree interrupt specifier from raw format coming
+         * from the firmware to a irq_hw_number_t (interrupt line number) and
+         * type (sense) that can be passed to set_irq_type(). In the absence
+         * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
+         * will return the hw number in the first cell and IRQ_TYPE_NONE for
+         * the type (which amount to keeping whatever default value the
+         * interrupt controller has for that line)
+         */
+        int (*xlate)(struct irq_host *h, struct device_node *ctrler,
+                     const u32 *intspec, unsigned int intsize,
+                     irq_hw_number_t *out_hwirq, unsigned int *out_type);
+};
+
+struct irq_host {
+        struct list_head        link;
+
+        /* type of reverse mapping technique */
+        unsigned int            revmap_type;
+#define IRQ_HOST_MAP_PRIORITY   0 /* core priority irqs, get irqs 1..15 */
+#define IRQ_HOST_MAP_NOMAP      1 /* no fast reverse mapping */
+#define IRQ_HOST_MAP_LINEAR     2 /* linear map of interrupts */
+#define IRQ_HOST_MAP_TREE       3 /* radix tree */
+        union {
+                struct {
+                        unsigned int size;
+                        unsigned int *revmap;
+                } linear;
+                struct radix_tree_root tree;
+        } revmap_data;
+        struct irq_host_ops     *ops;
+        void                    *host_data;
+        irq_hw_number_t         inval_irq;
+
+        /* Optional device node pointer */
+        struct device_node      *of_node;
+};
+
+struct irq_data;
+extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
+extern irq_hw_number_t virq_to_hw(unsigned int virq);
+extern bool virq_is_host(unsigned int virq, struct irq_host *host);
+
+/**
+ * irq_alloc_host - Allocate a new irq_host data structure
+ * @of_node: optional device-tree node of the interrupt controller
+ * @revmap_type: type of reverse mapping to use
+ * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
+ * @ops: map/unmap host callbacks
+ * @inval_irq: provide a hw number in that host space that is always invalid
+ *
+ * Allocates and initialize and irq_host structure. Note that in the case of
+ * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
+ * for all legacy interrupts except 0 (which is always the invalid irq for
+ * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
+ * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
+ * later during boot automatically (the reverse mapping will use the slow path
+ * until that happens).
+ */
+extern struct irq_host *irq_alloc_host(struct device_node *of_node,
+                                       unsigned int revmap_type,
+                                       unsigned int revmap_arg,
+                                       struct irq_host_ops *ops,
+                                       irq_hw_number_t inval_irq);
+
+
+/**
+ * irq_find_host - Locates a host for a given device node
+ * @node: device-tree node of the interrupt controller
+ */
+extern struct irq_host *irq_find_host(struct device_node *node);
+
+
+/**
+ * irq_set_default_host - Set a "default" host
+ * @host: default host pointer
+ *
+ * For convenience, it's possible to set a "default" host that will be used
+ * whenever NULL is passed to irq_create_mapping(). It makes life easier for
+ * platforms that want to manipulate a few hard coded interrupt numbers that
+ * aren't properly represented in the device-tree.
+ */
+extern void irq_set_default_host(struct irq_host *host);
+
+
+/**
+ * irq_set_virq_count - Set the maximum number of virt irqs
+ * @count: number of linux virtual irqs, capped with NR_IRQS
+ *
+ * This is mainly for use by platforms like iSeries who want to program
+ * the virtual irq number in the controller to avoid the reverse mapping
+ */
+extern void irq_set_virq_count(unsigned int count);
+
+
+/**
+ * irq_create_mapping - Map a hardware interrupt into linux virq space
+ * @host: host owning this hardware interrupt or NULL for default host
+ * @hwirq: hardware irq number in that host space
+ *
+ * Only one mapping per hardware interrupt is permitted. Returns a linux
+ * virq number.
+ * If the sense/trigger is to be specified, set_irq_type() should be called
+ * on the number returned from that call.
+ */
+extern unsigned int irq_create_mapping(struct irq_host *host,
+                                       irq_hw_number_t hwirq);
+
+
+/**
+ * irq_dispose_mapping - Unmap an interrupt
+ * @virq: linux virq number of the interrupt to unmap
+ */
+extern void irq_dispose_mapping(unsigned int virq);
+
+/**
+ * irq_find_mapping - Find a linux virq from an hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a slow path, for use by generic code. It's expected that an
+ * irq controller implementation directly calls the appropriate low level
+ * mapping function.
+ */
+extern unsigned int irq_find_mapping(struct irq_host *host,
+                                     irq_hw_number_t hwirq);
+
+/**
+ * irq_create_direct_mapping - Allocate a virq for direct mapping
+ * @host: host to allocate the virq for or NULL for default host
+ *
+ * This routine is used for irq controllers which can choose the hardware
+ * interrupt numbers they generate. In such a case it's simplest to use
+ * the linux virq as the hardware interrupt number.
+ */
+extern unsigned int irq_create_direct_mapping(struct irq_host *host);
+
+/**
+ * irq_radix_revmap_insert - Insert a hw irq to linux virq number mapping.
+ * @host: host owning this hardware interrupt
+ * @virq: linux irq number
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is for use by irq controllers that use a radix tree reverse
+ * mapping for fast lookup.
+ */
+extern void irq_radix_revmap_insert(struct irq_host *host, unsigned int virq,
+                                    irq_hw_number_t hwirq);
+
+/**
+ * irq_radix_revmap_lookup - Find a linux virq from a hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a fast path, for use by irq controller code that uses radix tree
+ * revmaps
+ */
+extern unsigned int irq_radix_revmap_lookup(struct irq_host *host,
+                                            irq_hw_number_t hwirq);
+
+/**
+ * irq_linear_revmap - Find a linux virq from a hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a fast path, for use by irq controller code that uses linear
+ * revmaps. It does fallback to the slow path if the revmap doesn't exist
+ * yet and will create the revmap entry with appropriate locking
+ */
+
+extern unsigned int irq_linear_revmap(struct irq_host *host,
+                                      irq_hw_number_t hwirq);
+
+
+
+/**
+ * irq_alloc_virt - Allocate virtual irq numbers
+ * @host: host owning these new virtual irqs
+ * @count: number of consecutive numbers to allocate
+ * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
+ *
+ * This is a low level function that is used internally by irq_create_mapping()
+ * and that can be used by some irq controllers implementations for things
+ * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
+ */
+extern unsigned int irq_alloc_virt(struct irq_host *host,
+                                   unsigned int count,
+                                   unsigned int hint);
+
+/**
+ * irq_free_virt - Free virtual irq numbers
+ * @virq: virtual irq number of the first interrupt to free
+ * @count: number of interrupts to free
+ *
+ * This function is the opposite of irq_alloc_virt. It will not clear reverse
+ * maps, this should be done previously by unmap'ing the interrupt. In fact,
+ * all interrupts covered by the range being freed should have been unmapped
+ * prior to calling this.
+ */
+extern void irq_free_virt(unsigned int virq, unsigned int count);
+
+extern void __init init_pic_c64xplus(void);
+
+extern void init_IRQ(void);
+
+struct pt_regs;
+
+extern asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs);
+
+extern unsigned long irq_err_count;
+
+#endif /* _ASM_C6X_IRQ_H */
diff --git a/arch/c6x/include/asm/irqflags.h b/arch/c6x/include/asm/irqflags.h
new file mode 100644
index 00000000000..cf78e09e18c
--- /dev/null
+++ b/arch/c6x/include/asm/irqflags.h
@@ -0,0 +1,72 @@
+/*
+ *  C6X IRQ flag handling
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Written by Mark Salter (msalter@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+/* read interrupt enabled status */
+static inline unsigned long arch_local_save_flags(void)
+{
+        unsigned long flags;
+
+        asm volatile (" mvc .s2 CSR,%0\n" : "=b"(flags));
+        return flags;
+}
+
+/* set interrupt enabled status */
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+        asm volatile (" mvc .s2 %0,CSR\n" : : "b"(flags));
+}
+
+/* unconditionally enable interrupts */
+static inline void arch_local_irq_enable(void)
+{
+        unsigned long flags = arch_local_save_flags();
+        flags |= 1;
+        arch_local_irq_restore(flags);
+}
+
+/* unconditionally disable interrupts */
+static inline void arch_local_irq_disable(void)
+{
+        unsigned long flags = arch_local_save_flags();
+        flags &= ~1;
+        arch_local_irq_restore(flags);
+}
+
+/* get status and disable interrupts */
+static inline unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags;
+
+        flags = arch_local_save_flags();
+        arch_local_irq_restore(flags & ~1);
+        return flags;
+}
+
+/* test flags */
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags & 1) == 0;
+}
+
+/* test hardware interrupt enable bit */
+static inline int arch_irqs_disabled(void)
+{
+        return arch_irqs_disabled_flags(arch_local_save_flags());
+}
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_IRQFLAGS_H */
diff --git a/arch/c6x/include/asm/linkage.h b/arch/c6x/include/asm/linkage.h
new file mode 100644
index 00000000000..376925c47d5
--- /dev/null
+++ b/arch/c6x/include/asm/linkage.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_C6X_LINKAGE_H
+#define _ASM_C6X_LINKAGE_H
+
+#ifdef __ASSEMBLER__
+
+#define __ALIGN         .align 2
+#define __ALIGN_STR     ".align 2"
+
+#ifndef __DSBT__
+#define ENTRY(name)             \
+        .global name @          \
+        __ALIGN @               \
+name:
+#else
+#define ENTRY(name)             \
+        .global name @          \
+        .hidden name @          \
+        __ALIGN @               \
+name:
+#endif
+
+#define ENDPROC(name)           \
+        .type name, @function @ \
+        .size name, . - name
+
+#endif
+
+#include <asm-generic/linkage.h>
+
+#endif /* _ASM_C6X_LINKAGE_H */
diff --git a/arch/c6x/include/asm/megamod-pic.h b/arch/c6x/include/asm/megamod-pic.h
new file mode 100644
index 00000000000..eca0a867803
--- /dev/null
+++ b/arch/c6x/include/asm/megamod-pic.h
@@ -0,0 +1,9 @@
+#ifndef _C6X_MEGAMOD_PIC_H
+#define _C6X_MEGAMOD_PIC_H
+
+#ifdef __KERNEL__
+
+extern void __init megamod_pic_init(void);
+
+#endif /* __KERNEL__ */
+#endif /* _C6X_MEGAMOD_PIC_H */
diff --git a/arch/c6x/include/asm/mmu.h b/arch/c6x/include/asm/mmu.h
new file mode 100644
index 00000000000..41592bf1606
--- /dev/null
+++ b/arch/c6x/include/asm/mmu.h
@@ -0,0 +1,18 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_MMU_H
+#define _ASM_C6X_MMU_H
+
+typedef struct {
+        unsigned long           end_brk;
+} mm_context_t;
+
+#endif /* _ASM_C6X_MMU_H */
diff --git a/arch/c6x/include/asm/module.h b/arch/c6x/include/asm/module.h
new file mode 100644
index 00000000000..a453f9744f4
--- /dev/null
+++ b/arch/c6x/include/asm/module.h
@@ -0,0 +1,33 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Updated for 2.6.34 by: Mark Salter (msalter@redhat.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_MODULE_H
+#define _ASM_C6X_MODULE_H
+
+#define Elf_Shdr        Elf32_Shdr
+#define Elf_Sym         Elf32_Sym
+#define Elf_Ehdr        Elf32_Ehdr
+#define Elf_Addr        Elf32_Addr
+#define Elf_Word        Elf32_Word
+
+/*
+ * This file contains the C6x architecture specific module code.
+ */
+struct mod_arch_specific {
+};
+
+struct loaded_sections {
+        unsigned int new_vaddr;
+        unsigned int loaded;
+};
+
+#endif /* _ASM_C6X_MODULE_H */
diff --git a/arch/c6x/include/asm/mutex.h b/arch/c6x/include/asm/mutex.h
new file mode 100644
index 00000000000..7a7248e0462
--- /dev/null
+++ b/arch/c6x/include/asm/mutex.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_C6X_MUTEX_H
+#define _ASM_C6X_MUTEX_H
+
+#include <asm-generic/mutex-null.h>
+
+#endif /* _ASM_C6X_MUTEX_H */
diff --git a/arch/c6x/include/asm/page.h b/arch/c6x/include/asm/page.h
new file mode 100644
index 00000000000..d18e2b0c7ae
--- /dev/null
+++ b/arch/c6x/include/asm/page.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_C6X_PAGE_H
+#define _ASM_C6X_PAGE_H
+
+#define VM_DATA_DEFAULT_FLAGS \
+        (VM_READ | VM_WRITE | \
+        ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
+                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/page.h>
+
+#endif /* _ASM_C6X_PAGE_H */
diff --git a/arch/c6x/include/asm/pgtable.h b/arch/c6x/include/asm/pgtable.h
new file mode 100644
index 00000000000..68c8af4f1f9
--- /dev/null
+++ b/arch/c6x/include/asm/pgtable.h
@@ -0,0 +1,81 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_PGTABLE_H
+#define _ASM_C6X_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * All 32bit addresses are effectively valid for vmalloc...
+ * Sort of meaningless for non-VM targets.
+ */
+#define VMALLOC_START   0
+#define VMALLOC_END     0xffffffff
+
+#define pgd_present(pgd)        (1)
+#define pgd_none(pgd)           (0)
+#define pgd_bad(pgd)            (0)
+#define pgd_clear(pgdp)
+#define kern_addr_valid(addr) (1)
+
+#define pmd_offset(a, b)        ((void *)0)
+#define pmd_none(x)             (!pmd_val(x))
+#define pmd_present(x)          (pmd_val(x))
+#define pmd_clear(xp)           do { set_pmd(xp, __pmd(0)); } while (0)
+#define pmd_bad(x)              (pmd_val(x) & ~PAGE_MASK)
+
+#define PAGE_NONE               __pgprot(0)    /* these mean nothing to NO_MM */
+#define PAGE_SHARED             __pgprot(0)    /* these mean nothing to NO_MM */
+#define PAGE_COPY               __pgprot(0)    /* these mean nothing to NO_MM */
+#define PAGE_READONLY           __pgprot(0)    /* these mean nothing to NO_MM */
+#define PAGE_KERNEL             __pgprot(0)    /* these mean nothing to NO_MM */
+#define pgprot_noncached(prot)  (prot)
+
+extern void paging_init(void);
+
+#define __swp_type(x)           (0)
+#define __swp_offset(x)         (0)
+#define __swp_entry(typ, off)   ((swp_entry_t) { ((typ) | ((off) << 7)) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+static inline int pte_file(pte_t pte)
+{
+        return 0;
+}
+
+#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+#define ZERO_PAGE(vaddr)        virt_to_page(empty_zero_page)
+extern unsigned long empty_zero_page;
+
+#define swapper_pg_dir ((pgd_t *) 0)
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()   do { } while (0)
+#define io_remap_pfn_range      remap_pfn_range
+
+#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
+                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
+
+#include <asm-generic/pgtable.h>
+
+#endif /* _ASM_C6X_PGTABLE_H */
diff --git a/arch/c6x/include/asm/processor.h b/arch/c6x/include/asm/processor.h
new file mode 100644
index 00000000000..8154c4ee8c9
--- /dev/null
+++ b/arch/c6x/include/asm/processor.h
@@ -0,0 +1,132 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Updated for 2.6.34: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_PROCESSOR_H
+#define _ASM_C6X_PROCESSOR_H
+
+#include <asm/ptrace.h>
+#include <asm/page.h>
+#include <asm/current.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr()                     \
+({                                              \
+        void *__pc;                             \
+        asm("mvc .S2 pce1,%0\n" : "=b"(__pc));  \
+        __pc;                                   \
+})
+
+/*
+ * User space process size. This is mostly meaningless for NOMMU
+ * but some C6X processors may have RAM addresses up to 0xFFFFFFFF.
+ * Since calls like mmap() can return an address or an error, we
+ * have to allow room for error returns when code does something
+ * like:
+ *
+ *       addr = do_mmap(...)
+ *       if ((unsigned long)addr >= TASK_SIZE)
+ *            ... its an error code, not an address ...
+ *
+ * Here, we allow for 4096 error codes which means we really can't
+ * use the last 4K page on systems with RAM extending all the way
+ * to the end of the 32-bit address space.
+ */
+#define TASK_SIZE       0xFFFFF000
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's. We won't be using it
+ */
+#define TASK_UNMAPPED_BASE      0
+
+struct thread_struct {
+        unsigned long long b15_14;
+        unsigned long long a15_14;
+        unsigned long long b13_12;
+        unsigned long long a13_12;
+        unsigned long long b11_10;
+        unsigned long long a11_10;
+        unsigned long long ricl_icl;
+        unsigned long  usp;             /* user stack pointer */
+        unsigned long  pc;              /* kernel pc */
+        unsigned long  wchan;
+};
+
+#define INIT_THREAD                                     \
+{                                                       \
+        .usp = 0,                                       \
+        .wchan = 0,                                     \
+}
+
+#define INIT_MMAP { \
+        &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \
+        NULL, NULL }
+
+#define task_pt_regs(task) \
+        ((struct pt_regs *)(THREAD_START_SP + task_stack_page(task)) - 1)
+
+#define alloc_kernel_stack()    __get_free_page(GFP_KERNEL)
+#define free_kernel_stack(page) free_page((page))
+
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+extern void start_thread(struct pt_regs *regs, unsigned int pc,
+                         unsigned long usp);
+
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+#define copy_segments(tsk, mm)          do { } while (0)
+#define release_segments(mm)            do { } while (0)
+
+/*
+ * saved PC of a blocked thread.
+ */
+#define thread_saved_pc(tsk) (task_pt_regs(tsk)->pc)
+
+/*
+ * saved kernel SP and DP of a blocked thread.
+ */
+#ifdef _BIG_ENDIAN
+#define thread_saved_ksp(tsk) \
+        (*(unsigned long *)&(tsk)->thread.b15_14)
+#define thread_saved_dp(tsk) \
+        (*(((unsigned long *)&(tsk)->thread.b15_14) + 1))
+#else
+#define thread_saved_ksp(tsk) \
+        (*(((unsigned long *)&(tsk)->thread.b15_14) + 1))
+#define thread_saved_dp(tsk) \
+        (*(unsigned long *)&(tsk)->thread.b15_14)
+#endif
+
+extern unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)   (task_pt_regs(task)->pc)
+#define KSTK_ESP(tsk)   (task_pt_regs(task)->sp)
+
+#define cpu_relax()             do { } while (0)
+
+extern const struct seq_operations cpuinfo_op;
+
+#endif /* ASM_C6X_PROCESSOR_H */
diff --git a/arch/c6x/include/asm/procinfo.h b/arch/c6x/include/asm/procinfo.h
new file mode 100644
index 00000000000..c139d1e71f8
--- /dev/null
+++ b/arch/c6x/include/asm/procinfo.h
@@ -0,0 +1,28 @@
+/*
+ *  Copyright (C) 2010 Texas Instruments Incorporated
+ *  Author: Mark Salter (msalter@redhat.com)
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_PROCINFO_H
+#define _ASM_C6X_PROCINFO_H
+
+#ifdef __KERNEL__
+
+struct proc_info_list {
+        unsigned int            cpu_val;
+        unsigned int            cpu_mask;
+        const char              *arch_name;
+        const char              *elf_name;
+        unsigned int            elf_hwcap;
+};
+
+#else   /* __KERNEL__ */
+#include <asm/elf.h>
+#warning "Please include asm/elf.h instead"
+#endif  /* __KERNEL__ */
+
+#endif  /* _ASM_C6X_PROCINFO_H */
diff --git a/arch/c6x/include/asm/prom.h b/arch/c6x/include/asm/prom.h
new file mode 100644
index 00000000000..b4ec95f0751
--- /dev/null
+++ b/arch/c6x/include/asm/prom.h
@@ -0,0 +1 @@
+/* dummy prom.h; here to make linux/of.h's #includes happy */
diff --git a/arch/c6x/include/asm/ptrace.h b/arch/c6x/include/asm/ptrace.h
new file mode 100644
index 00000000000..21e8d7931fe
--- /dev/null
+++ b/arch/c6x/include/asm/ptrace.h
@@ -0,0 +1,174 @@
+/*
+ *  Copyright (C) 2004, 2006, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Updated for 2.6.34: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_PTRACE_H
+#define _ASM_C6X_PTRACE_H
+
+#define BKPT_OPCODE     0x56454314      /* illegal opcode */
+
+#ifdef _BIG_ENDIAN
+#define PT_LO(odd, even)  odd
+#define PT_HI(odd, even)  even
+#else
+#define PT_LO(odd, even)  even
+#define PT_HI(odd, even)  odd
+#endif
+
+#define PT_A4_ORG  PT_LO(1, 0)
+#define PT_TSR     PT_HI(1, 0)
+#define PT_ILC     PT_LO(3, 2)
+#define PT_RILC    PT_HI(3, 2)
+#define PT_CSR     PT_LO(5, 4)
+#define PT_PC      PT_HI(5, 4)
+#define PT_B16     PT_LO(7, 6)
+#define PT_B17     PT_HI(7, 6)
+#define PT_B18     PT_LO(9, 8)
+#define PT_B19     PT_HI(9, 8)
+#define PT_B20     PT_LO(11, 10)
+#define PT_B21     PT_HI(11, 10)
+#define PT_B22     PT_LO(13, 12)
+#define PT_B23     PT_HI(13, 12)
+#define PT_B24     PT_LO(15, 14)
+#define PT_B25     PT_HI(15, 14)
+#define PT_B26     PT_LO(17, 16)
+#define PT_B27     PT_HI(17, 16)
+#define PT_B28     PT_LO(19, 18)
+#define PT_B29     PT_HI(19, 18)
+#define PT_B30     PT_LO(21, 20)
+#define PT_B31     PT_HI(21, 20)
+#define PT_B0      PT_LO(23, 22)
+#define PT_B1      PT_HI(23, 22)
+#define PT_B2      PT_LO(25, 24)
+#define PT_B3      PT_HI(25, 24)
+#define PT_B4      PT_LO(27, 26)
+#define PT_B5      PT_HI(27, 26)
+#define PT_B6      PT_LO(29, 28)
+#define PT_B7      PT_HI(29, 28)
+#define PT_B8      PT_LO(31, 30)
+#define PT_B9      PT_HI(31, 30)
+#define PT_B10     PT_LO(33, 32)
+#define PT_B11     PT_HI(33, 32)
+#define PT_B12     PT_LO(35, 34)
+#define PT_B13     PT_HI(35, 34)
+#define PT_A16     PT_LO(37, 36)
+#define PT_A17     PT_HI(37, 36)
+#define PT_A18     PT_LO(39, 38)
+#define PT_A19     PT_HI(39, 38)
+#define PT_A20     PT_LO(41, 40)
+#define PT_A21     PT_HI(41, 40)
+#define PT_A22     PT_LO(43, 42)
+#define PT_A23     PT_HI(43, 42)
+#define PT_A24     PT_LO(45, 44)
+#define PT_A25     PT_HI(45, 44)
+#define PT_A26     PT_LO(47, 46)
+#define PT_A27     PT_HI(47, 46)
+#define PT_A28     PT_LO(49, 48)
+#define PT_A29     PT_HI(49, 48)
+#define PT_A30     PT_LO(51, 50)
+#define PT_A31     PT_HI(51, 50)
+#define PT_A0      PT_LO(53, 52)
+#define PT_A1      PT_HI(53, 52)
+#define PT_A2      PT_LO(55, 54)
+#define PT_A3      PT_HI(55, 54)
+#define PT_A4      PT_LO(57, 56)
+#define PT_A5      PT_HI(57, 56)
+#define PT_A6      PT_LO(59, 58)
+#define PT_A7      PT_HI(59, 58)
+#define PT_A8      PT_LO(61, 60)
+#define PT_A9      PT_HI(61, 60)
+#define PT_A10     PT_LO(63, 62)
+#define PT_A11     PT_HI(63, 62)
+#define PT_A12     PT_LO(65, 64)
+#define PT_A13     PT_HI(65, 64)
+#define PT_A14     PT_LO(67, 66)
+#define PT_A15     PT_HI(67, 66)
+#define PT_B14     PT_LO(69, 68)
+#define PT_B15     PT_HI(69, 68)
+
+#define NR_PTREGS  70
+
+#define PT_DP      PT_B14  /* Data Segment Pointer (B14) */
+#define PT_SP      PT_B15  /* Stack Pointer (B15)  */
+
+#ifndef __ASSEMBLY__
+
+#ifdef _BIG_ENDIAN
+#define REG_PAIR(odd, even) unsigned long odd; unsigned long even
+#else
+#define REG_PAIR(odd, even) unsigned long even; unsigned long odd
+#endif
+
+/*
+ * this struct defines the way the registers are stored on the
+ * stack during a system call. fields defined with REG_PAIR
+ * are saved and restored using double-word memory operations
+ * which means the word ordering of the pair depends on endianess.
+ */
+struct pt_regs {
+        REG_PAIR(tsr, orig_a4);
+        REG_PAIR(rilc, ilc);
+        REG_PAIR(pc, csr);
+
+        REG_PAIR(b17, b16);
+        REG_PAIR(b19, b18);
+        REG_PAIR(b21, b20);
+        REG_PAIR(b23, b22);
+        REG_PAIR(b25, b24);
+        REG_PAIR(b27, b26);
+        REG_PAIR(b29, b28);
+        REG_PAIR(b31, b30);
+
+        REG_PAIR(b1, b0);
+        REG_PAIR(b3, b2);
+        REG_PAIR(b5, b4);
+        REG_PAIR(b7, b6);
+        REG_PAIR(b9, b8);
+        REG_PAIR(b11, b10);
+        REG_PAIR(b13, b12);
+
+        REG_PAIR(a17, a16);
+        REG_PAIR(a19, a18);
+        REG_PAIR(a21, a20);
+        REG_PAIR(a23, a22);
+        REG_PAIR(a25, a24);
+        REG_PAIR(a27, a26);
+        REG_PAIR(a29, a28);
+        REG_PAIR(a31, a30);
+
+        REG_PAIR(a1, a0);
+        REG_PAIR(a3, a2);
+        REG_PAIR(a5, a4);
+        REG_PAIR(a7, a6);
+        REG_PAIR(a9, a8);
+        REG_PAIR(a11, a10);
+        REG_PAIR(a13, a12);
+
+        REG_PAIR(a15, a14);
+        REG_PAIR(sp, dp);
+};
+
+#ifdef __KERNEL__
+
+#include <linux/linkage.h>
+
+#define user_mode(regs) ((((regs)->tsr) & 0x40) != 0)
+
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+#define user_stack_pointer(regs) ((regs)->sp)
+
+extern void show_regs(struct pt_regs *);
+
+extern asmlinkage unsigned long syscall_trace_entry(struct pt_regs *regs);
+extern asmlinkage void syscall_trace_exit(struct pt_regs *regs);
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_C6X_PTRACE_H */
diff --git a/arch/c6x/include/asm/sections.h b/arch/c6x/include/asm/sections.h
new file mode 100644
index 00000000000..f703989d837
--- /dev/null
+++ b/arch/c6x/include/asm/sections.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_C6X_SECTIONS_H
+#define _ASM_C6X_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern char _vectors_start[];
+extern char _vectors_end[];
+
+extern char _data_lma[];
+extern char _fdt_start[], _fdt_end[];
+
+#endif /* _ASM_C6X_SECTIONS_H */
diff --git a/arch/c6x/include/asm/setup.h b/arch/c6x/include/asm/setup.h
new file mode 100644
index 00000000000..1808f279f82
--- /dev/null
+++ b/arch/c6x/include/asm/setup.h
@@ -0,0 +1,32 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_SETUP_H
+#define _ASM_C6X_SETUP_H
+
+#define COMMAND_LINE_SIZE   1024
+
+#ifndef __ASSEMBLY__
+extern char c6x_command_line[COMMAND_LINE_SIZE];
+
+extern int c6x_add_memory(phys_addr_t start, unsigned long size);
+
+extern unsigned long ram_start;
+extern unsigned long ram_end;
+
+extern int c6x_num_cores;
+extern unsigned int c6x_silicon_rev;
+extern unsigned int c6x_devstat;
+extern unsigned char c6x_fuse_mac[6];
+
+extern void machine_init(unsigned long dt_ptr);
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_C6X_SETUP_H */
diff --git a/arch/c6x/include/asm/sigcontext.h b/arch/c6x/include/asm/sigcontext.h
new file mode 100644
index 00000000000..eb702f39cde
--- /dev/null
+++ b/arch/c6x/include/asm/sigcontext.h
@@ -0,0 +1,80 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_SIGCONTEXT_H
+#define _ASM_C6X_SIGCONTEXT_H
+
+
+struct sigcontext {
+        unsigned long  sc_mask;         /* old sigmask */
+        unsigned long  sc_sp;           /* old user stack pointer */
+
+        unsigned long  sc_a4;
+        unsigned long  sc_b4;
+        unsigned long  sc_a6;
+        unsigned long  sc_b6;
+        unsigned long  sc_a8;
+        unsigned long  sc_b8;
+
+        unsigned long  sc_a0;
+        unsigned long  sc_a1;
+        unsigned long  sc_a2;
+        unsigned long  sc_a3;
+        unsigned long  sc_a5;
+        unsigned long  sc_a7;
+        unsigned long  sc_a9;
+
+        unsigned long  sc_b0;
+        unsigned long  sc_b1;
+        unsigned long  sc_b2;
+        unsigned long  sc_b3;
+        unsigned long  sc_b5;
+        unsigned long  sc_b7;
+        unsigned long  sc_b9;
+
+        unsigned long  sc_a16;
+        unsigned long  sc_a17;
+        unsigned long  sc_a18;
+        unsigned long  sc_a19;
+        unsigned long  sc_a20;
+        unsigned long  sc_a21;
+        unsigned long  sc_a22;
+        unsigned long  sc_a23;
+        unsigned long  sc_a24;
+        unsigned long  sc_a25;
+        unsigned long  sc_a26;
+        unsigned long  sc_a27;
+        unsigned long  sc_a28;
+        unsigned long  sc_a29;
+        unsigned long  sc_a30;
+        unsigned long  sc_a31;
+
+        unsigned long  sc_b16;
+        unsigned long  sc_b17;
+        unsigned long  sc_b18;
+        unsigned long  sc_b19;
+        unsigned long  sc_b20;
+        unsigned long  sc_b21;
+        unsigned long  sc_b22;
+        unsigned long  sc_b23;
+        unsigned long  sc_b24;
+        unsigned long  sc_b25;
+        unsigned long  sc_b26;
+        unsigned long  sc_b27;
+        unsigned long  sc_b28;
+        unsigned long  sc_b29;
+        unsigned long  sc_b30;
+        unsigned long  sc_b31;
+
+        unsigned long  sc_csr;
+        unsigned long  sc_pc;
+};
+
+#endif /* _ASM_C6X_SIGCONTEXT_H */
diff --git a/arch/c6x/include/asm/signal.h b/arch/c6x/include/asm/signal.h
new file mode 100644
index 00000000000..f1cd870596a
--- /dev/null
+++ b/arch/c6x/include/asm/signal.h
@@ -0,0 +1,17 @@
+#ifndef _ASM_C6X_SIGNAL_H
+#define _ASM_C6X_SIGNAL_H
+
+#include <asm-generic/signal.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/linkage.h>
+
+struct pt_regs;
+
+extern asmlinkage int do_rt_sigreturn(struct pt_regs *regs);
+extern asmlinkage void do_notify_resume(struct pt_regs *regs,
+                                        u32 thread_info_flags,
+                                        int syscall);
+#endif
+
+#endif /* _ASM_C6X_SIGNAL_H */
diff --git a/arch/c6x/include/asm/soc.h b/arch/c6x/include/asm/soc.h
new file mode 100644
index 00000000000..43f50159e59
--- /dev/null
+++ b/arch/c6x/include/asm/soc.h
@@ -0,0 +1,35 @@
+/*
+ * Miscellaneous SoC-specific hooks.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _ASM_C6X_SOC_H
+#define _ASM_C6X_SOC_H
+
+struct soc_ops {
+        /* Return active exception event or -1 if none */
+        int             (*get_exception)(void);
+
+        /* Assert an event */
+        void            (*assert_event)(unsigned int evt);
+};
+
+extern struct soc_ops soc_ops;
+
+extern int soc_get_exception(void);
+extern void soc_assert_event(unsigned int event);
+extern int soc_mac_addr(unsigned int index, u8 *addr);
+
+/*
+ * for mmio on SoC devices. regs are always same byte order as cpu.
+ */
+#define soc_readl(addr)    __raw_readl(addr)
+#define soc_writel(b, addr) __raw_writel((b), (addr))
+
+#endif /* _ASM_C6X_SOC_H */
diff --git a/arch/c6x/include/asm/string.h b/arch/c6x/include/asm/string.h
new file mode 100644
index 00000000000..b21517c80a1
--- /dev/null
+++ b/arch/c6x/include/asm/string.h
@@ -0,0 +1,21 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_STRING_H
+#define _ASM_C6X_STRING_H
+
+#include <asm/page.h>
+#include <linux/linkage.h>
+
+asmlinkage extern void *memcpy(void *to, const void *from, size_t n);
+
+#define __HAVE_ARCH_MEMCPY
+
+#endif /* _ASM_C6X_STRING_H */
diff --git a/arch/c6x/include/asm/swab.h b/arch/c6x/include/asm/swab.h
new file mode 100644
index 00000000000..fd4bb0520e5
--- /dev/null
+++ b/arch/c6x/include/asm/swab.h
@@ -0,0 +1,54 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_SWAB_H
+#define _ASM_C6X_SWAB_H
+
+static inline __attribute_const__ __u16 __c6x_swab16(__u16 val)
+{
+        asm("swap4 .l1 %0,%0\n" : "+a"(val));
+        return val;
+}
+
+static inline __attribute_const__ __u32 __c6x_swab32(__u32 val)
+{
+        asm("swap4 .l1 %0,%0\n"
+            "swap2 .l1 %0,%0\n"
+            : "+a"(val));
+        return val;
+}
+
+static inline __attribute_const__ __u64 __c6x_swab64(__u64 val)
+{
+        asm("   swap2 .s1 %p0,%P0\n"
+            "|| swap2 .l1 %P0,%p0\n"
+            "   swap4 .l1 %p0,%p0\n"
+            "   swap4 .l1 %P0,%P0\n"
+            : "+a"(val));
+        return val;
+}
+
+static inline __attribute_const__ __u32 __c6x_swahw32(__u32 val)
+{
+        asm("swap2 .l1 %0,%0\n" : "+a"(val));
+        return val;
+}
+
+static inline __attribute_const__ __u32 __c6x_swahb32(__u32 val)
+{
+        asm("swap4 .l1 %0,%0\n" : "+a"(val));
+        return val;
+}
+
+#define __arch_swab16 __c6x_swab16
+#define __arch_swab32 __c6x_swab32
+#define __arch_swab64 __c6x_swab64
+#define __arch_swahw32 __c6x_swahw32
+#define __arch_swahb32 __c6x_swahb32
+
+#endif /* _ASM_C6X_SWAB_H */
diff --git a/arch/c6x/include/asm/syscall.h b/arch/c6x/include/asm/syscall.h
new file mode 100644
index 00000000000..ae2be315ee9
--- /dev/null
+++ b/arch/c6x/include/asm/syscall.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_C6X_SYSCALL_H
+#define __ASM_C6X_SYSCALL_H
+
+#include <linux/err.h>
+#include <linux/sched.h>
+
+static inline int syscall_get_nr(struct task_struct *task,
+                                 struct pt_regs *regs)
+{
+        return regs->b0;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        /* do nothing */
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        return IS_ERR_VALUE(regs->a4) ? regs->a4 : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->a4;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        regs->a4 = error ?: val;
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs, unsigned int i,
+                                         unsigned int n, unsigned long *args)
+{
+        switch (i) {
+        case 0:
+                if (!n--)
+                        break;
+                *args++ = regs->a4;
+        case 1:
+                if (!n--)
+                        break;
+                *args++ = regs->b4;
+        case 2:
+                if (!n--)
+                        break;
+                *args++ = regs->a6;
+        case 3:
+                if (!n--)
+                        break;
+                *args++ = regs->b6;
+        case 4:
+                if (!n--)
+                        break;
+                *args++ = regs->a8;
+        case 5:
+                if (!n--)
+                        break;
+                *args++ = regs->b8;
+        case 6:
+                if (!n--)
+                        break;
+        default:
+                BUG();
+        }
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        switch (i) {
+        case 0:
+                if (!n--)
+                        break;
+                regs->a4 = *args++;
+        case 1:
+                if (!n--)
+                        break;
+                regs->b4 = *args++;
+        case 2:
+                if (!n--)
+                        break;
+                regs->a6 = *args++;
+        case 3:
+                if (!n--)
+                        break;
+                regs->b6 = *args++;
+        case 4:
+                if (!n--)
+                        break;
+                regs->a8 = *args++;
+        case 5:
+                if (!n--)
+                        break;
+                regs->a9 = *args++;
+        case 6:
+                if (!n)
+                        break;
+        default:
+                BUG();
+        }
+}
+
+#endif /* __ASM_C6X_SYSCALLS_H */
diff --git a/arch/c6x/include/asm/syscalls.h b/arch/c6x/include/asm/syscalls.h
new file mode 100644
index 00000000000..aed53da703c
--- /dev/null
+++ b/arch/c6x/include/asm/syscalls.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ * Author: Mark Salter <msalter@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __ASM_C6X_SYSCALLS_H
+#define __ASM_C6X_SYSCALLS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+
+/* The array of function pointers for syscalls. */
+extern void *sys_call_table[];
+
+/* The following are trampolines in entry.S to handle 64-bit arguments */
+extern long sys_pread_c6x(unsigned int fd, char __user *buf,
+                          size_t count, off_t pos_low, off_t pos_high);
+extern long sys_pwrite_c6x(unsigned int fd, const char __user *buf,
+                           size_t count, off_t pos_low, off_t pos_high);
+extern long sys_truncate64_c6x(const char __user *path,
+                               off_t length_low, off_t length_high);
+extern long sys_ftruncate64_c6x(unsigned int fd,
+                               off_t length_low, off_t length_high);
+extern long sys_fadvise64_c6x(int fd, u32 offset_lo, u32 offset_hi,
+                              u32 len, int advice);
+extern long sys_fadvise64_64_c6x(int fd, u32 offset_lo, u32 offset_hi,
+                                u32 len_lo, u32 len_hi, int advice);
+extern long sys_fallocate_c6x(int fd, int mode,
+                              u32 offset_lo, u32 offset_hi,
+                              u32 len_lo, u32 len_hi);
+extern int sys_cache_sync(unsigned long s, unsigned long e);
+
+struct pt_regs;
+
+extern asmlinkage long sys_c6x_clone(struct pt_regs *regs);
+extern asmlinkage long sys_c6x_execve(const char __user *name,
+                                      const char __user *const __user *argv,
+                                      const char __user *const __user *envp,
+                                      struct pt_regs *regs);
+
+
+#include <asm-generic/syscalls.h>
+
+#endif /* __ASM_C6X_SYSCALLS_H */
diff --git a/arch/c6x/include/asm/system.h b/arch/c6x/include/asm/system.h
new file mode 100644
index 00000000000..e076dc0eacc
--- /dev/null
+++ b/arch/c6x/include/asm/system.h
@@ -0,0 +1,168 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_SYSTEM_H
+#define _ASM_C6X_SYSTEM_H
+
+#include <linux/linkage.h>
+#include <linux/irqflags.h>
+
+#define prepare_to_switch()    do { } while (0)
+
+struct task_struct;
+struct thread_struct;
+asmlinkage void *__switch_to(struct thread_struct *prev,
+                             struct thread_struct *next,
+                             struct task_struct *tsk);
+
+#define switch_to(prev, next, last)                             \
+        do {                                                    \
+                current->thread.wchan = (u_long) __builtin_return_address(0); \
+                (last) = __switch_to(&(prev)->thread,           \
+                                     &(next)->thread, (prev));  \
+                mb();                                           \
+                current->thread.wchan = 0;                      \
+        } while (0)
+
+/* Reset the board */
+#define HARD_RESET_NOW()
+
+#define get_creg(reg) \
+        ({ unsigned int __x; \
+           asm volatile ("mvc .s2 " #reg ",%0\n" : "=b"(__x)); __x; })
+
+#define set_creg(reg, v) \
+        do { unsigned int __x = (unsigned int)(v); \
+                asm volatile ("mvc .s2 %0," #reg "\n" : : "b"(__x)); \
+        } while (0)
+
+#define or_creg(reg, n) \
+        do { unsigned __x, __n = (unsigned)(n);           \
+                asm volatile ("mvc .s2 " #reg ",%0\n"     \
+                              "or  .l2 %1,%0,%0\n"        \
+                              "mvc .s2 %0," #reg "\n"     \
+                              "nop\n"                     \
+                              : "=&b"(__x) : "b"(__n));   \
+        } while (0)
+
+#define and_creg(reg, n) \
+        do { unsigned __x, __n = (unsigned)(n);           \
+                asm volatile ("mvc .s2 " #reg ",%0\n"     \
+                              "and .l2 %1,%0,%0\n"        \
+                              "mvc .s2 %0," #reg "\n"     \
+                              "nop\n"    \
+                              : "=&b"(__x) : "b"(__n));   \
+        } while (0)
+
+#define get_coreid() (get_creg(DNUM) & 0xff)
+
+/* Set/get IST */
+#define set_ist(x)      set_creg(ISTP, x)
+#define get_ist()       get_creg(ISTP)
+
+/*
+ * Exception management
+ */
+asmlinkage void enable_exception(void);
+#define disable_exception()
+#define get_except_type()        get_creg(EFR)
+#define ack_exception(type)      set_creg(ECR, 1 << (type))
+#define get_iexcept()            get_creg(IERR)
+#define set_iexcept(mask)        set_creg(IERR, (mask))
+
+/*
+ * Misc. functions
+ */
+#define nop()                    asm("NOP\n");
+#define mb()                     barrier()
+#define rmb()                    barrier()
+#define wmb()                    barrier()
+#define set_mb(var, value)       do { var = value;  mb(); } while (0)
+#define set_wmb(var, value)      do { var = value; wmb(); } while (0)
+
+#define smp_mb()                 barrier()
+#define smp_rmb()                barrier()
+#define smp_wmb()                barrier()
+#define smp_read_barrier_depends()      do { } while (0)
+
+#define xchg(ptr, x) \
+        ((__typeof__(*(ptr)))__xchg((unsigned int)(x), (void *) (ptr), \
+                                    sizeof(*(ptr))))
+#define tas(ptr)    xchg((ptr), 1)
+
+unsigned int _lmbd(unsigned int, unsigned int);
+unsigned int _bitr(unsigned int);
+
+struct __xchg_dummy { unsigned int a[100]; };
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned int __xchg(unsigned int x, volatile void *ptr, int size)
+{
+        unsigned int tmp;
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        switch (size) {
+        case 1:
+                tmp = 0;
+                tmp = *((unsigned char *) ptr);
+                *((unsigned char *) ptr) = (unsigned char) x;
+                break;
+        case 2:
+                tmp = 0;
+                tmp = *((unsigned short *) ptr);
+                *((unsigned short *) ptr) = x;
+                break;
+        case 4:
+                tmp = 0;
+                tmp = *((unsigned int *) ptr);
+                *((unsigned int *) ptr) = x;
+                break;
+        }
+        local_irq_restore(flags);
+        return tmp;
+}
+
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)                                        \
+        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr),             \
+                                                     (unsigned long)(o), \
+                                                     (unsigned long)(n), \
+                                                     sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+#include <asm-generic/cmpxchg.h>
+
+#define _extu(x, s, e)                                                  \
+        ({      unsigned int __x;                                       \
+                asm volatile ("extu .S2 %3,%1,%2,%0\n" :                \
+                              "=b"(__x) : "n"(s), "n"(e), "b"(x));      \
+               __x; })
+
+
+extern unsigned int c6x_core_freq;
+
+struct pt_regs;
+
+extern void die(char *str, struct pt_regs *fp, int nr);
+extern asmlinkage int process_exception(struct pt_regs *regs);
+extern void time_init(void);
+extern void free_initmem(void);
+
+extern void (*c6x_restart)(void);
+extern void (*c6x_halt)(void);
+
+#endif /* _ASM_C6X_SYSTEM_H */
diff --git a/arch/c6x/include/asm/thread_info.h b/arch/c6x/include/asm/thread_info.h
new file mode 100644
index 00000000000..fd99148cda9
--- /dev/null
+++ b/arch/c6x/include/asm/thread_info.h
@@ -0,0 +1,121 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Updated for 2.6.3x: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_THREAD_INFO_H
+#define _ASM_C6X_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#include <asm/page.h>
+
+#ifdef CONFIG_4KSTACKS
+#define THREAD_SIZE             4096
+#define THREAD_SHIFT            12
+#define THREAD_ORDER            0
+#else
+#define THREAD_SIZE             8192
+#define THREAD_SHIFT            13
+#define THREAD_ORDER            1
+#endif
+
+#define THREAD_START_SP         (THREAD_SIZE - 8)
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+/*
+ * low level task data.
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        int                     cpu;            /* cpu we're on */
+        int                     preempt_count;  /* 0 = preemptable, <0 = BUG */
+        mm_segment_t            addr_limit;     /* thread address space */
+        struct restart_block    restart_block;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = INIT_PREEMPT_COUNT,   \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* get the thread information struct of current task */
+static inline __attribute__((const))
+struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+        asm volatile (" clr   .s2 B15,0,%1,%0\n"
+                      : "=b" (ti)
+                      : "Iu5" (THREAD_SHIFT - 1));
+        return ti;
+}
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+/* thread information allocation */
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO)
+#else
+#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK)
+#endif
+
+#define alloc_thread_info_node(tsk, node)       \
+        ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
+
+#define free_thread_info(ti)    free_pages((unsigned long) (ti), THREAD_ORDER)
+#define get_thread_info(ti)     get_task_struct((ti)->task)
+#define put_thread_info(ti)     put_task_struct((ti)->task)
+#endif /* __ASSEMBLY__ */
+
+#define PREEMPT_ACTIVE  0x10000000
+
+/*
+ * thread information flag bit numbers
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_RESTORE_SIGMASK     4       /* restore signal mask in do_signal() */
+
+#define TIF_POLLING_NRFLAG      16      /* true if polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              17      /* OOM killer killed process */
+
+#define TIF_WORK_MASK           0x00007FFE /* work on irq/exception return */
+#define TIF_ALLWORK_MASK        0x00007FFF /* work on any return to u-space */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_C6X_THREAD_INFO_H */
diff --git a/arch/c6x/include/asm/timer64.h b/arch/c6x/include/asm/timer64.h
new file mode 100644
index 00000000000..bbe27bb9887
--- /dev/null
+++ b/arch/c6x/include/asm/timer64.h
@@ -0,0 +1,6 @@
+#ifndef _C6X_TIMER64_H
+#define _C6X_TIMER64_H
+
+extern void __init timer64_init(void);
+
+#endif /* _C6X_TIMER64_H */
diff --git a/arch/c6x/include/asm/timex.h b/arch/c6x/include/asm/timex.h
new file mode 100644
index 00000000000..508c3ec971f
--- /dev/null
+++ b/arch/c6x/include/asm/timex.h
@@ -0,0 +1,33 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Modified for 2.6.34: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_TIMEX_H
+#define _ASM_C6X_TIMEX_H
+
+#define CLOCK_TICK_RATE ((1000 * 1000000UL) / 6)
+
+/* 64-bit timestamp */
+typedef unsigned long long cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+        unsigned l, h;
+
+        asm volatile (" dint\n"
+                      " mvc .s2 TSCL,%0\n"
+                      " mvc .s2 TSCH,%1\n"
+                      " rint\n"
+                      : "=b"(l), "=b"(h));
+        return ((cycles_t)h << 32) | l;
+}
+
+#endif /* _ASM_C6X_TIMEX_H */
diff --git a/arch/c6x/include/asm/tlb.h b/arch/c6x/include/asm/tlb.h
new file mode 100644
index 00000000000..8709e5e29d2
--- /dev/null
+++ b/arch/c6x/include/asm/tlb.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_C6X_TLB_H
+#define _ASM_C6X_TLB_H
+
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* _ASM_C6X_TLB_H */
diff --git a/arch/c6x/include/asm/traps.h b/arch/c6x/include/asm/traps.h
new file mode 100644
index 00000000000..62124d7b1b5
--- /dev/null
+++ b/arch/c6x/include/asm/traps.h
@@ -0,0 +1,36 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_TRAPS_H
+#define _ASM_C6X_TRAPS_H
+
+#define EXCEPT_TYPE_NXF   31       /* NMI */
+#define EXCEPT_TYPE_EXC   30       /* external exception */
+#define EXCEPT_TYPE_IXF   1        /* internal exception */
+#define EXCEPT_TYPE_SXF   0        /* software exception */
+
+#define EXCEPT_CAUSE_LBX  (1 << 7) /* loop buffer exception */
+#define EXCEPT_CAUSE_PRX  (1 << 6) /* privilege exception */
+#define EXCEPT_CAUSE_RAX  (1 << 5) /* resource access exception */
+#define EXCEPT_CAUSE_RCX  (1 << 4) /* resource conflict exception */
+#define EXCEPT_CAUSE_OPX  (1 << 3) /* opcode exception */
+#define EXCEPT_CAUSE_EPX  (1 << 2) /* execute packet exception */
+#define EXCEPT_CAUSE_FPX  (1 << 1) /* fetch packet exception */
+#define EXCEPT_CAUSE_IFX  (1 << 0) /* instruction fetch exception */
+
+struct exception_info {
+        char *kernel_str;
+        int  signo;
+        int  code;
+};
+
+extern int (*c6x_nmi_handler)(struct pt_regs *regs);
+
+#endif /* _ASM_C6X_TRAPS_H */
diff --git a/arch/c6x/include/asm/uaccess.h b/arch/c6x/include/asm/uaccess.h
new file mode 100644
index 00000000000..453dd263bee
--- /dev/null
+++ b/arch/c6x/include/asm/uaccess.h
@@ -0,0 +1,107 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_UACCESS_H
+#define _ASM_C6X_UACCESS_H
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/string.h>
+
+#ifdef CONFIG_ACCESS_CHECK
+#define __access_ok _access_ok
+#endif
+
+/*
+ * __copy_from_user/copy_to_user are based on ones in asm-generic/uaccess.h
+ *
+ * C6X supports unaligned 32 and 64 bit loads and stores.
+ */
+static inline __must_check long __copy_from_user(void *to,
+                const void __user *from, unsigned long n)
+{
+        u32 tmp32;
+        u64 tmp64;
+
+        if (__builtin_constant_p(n)) {
+                switch (n) {
+                case 1:
+                        *(u8 *)to = *(u8 __force *)from;
+                        return 0;
+                case 4:
+                        asm volatile ("ldnw .d1t1 *%2,%0\n"
+                                      "nop  4\n"
+                                      "stnw .d1t1 %0,*%1\n"
+                                      : "=&a"(tmp32)
+                                      : "A"(to), "a"(from)
+                                      : "memory");
+                        return 0;
+                case 8:
+                        asm volatile ("ldndw .d1t1 *%2,%0\n"
+                                      "nop   4\n"
+                                      "stndw .d1t1 %0,*%1\n"
+                                      : "=&a"(tmp64)
+                                      : "a"(to), "a"(from)
+                                      : "memory");
+                        return 0;
+                default:
+                        break;
+                }
+        }
+
+        memcpy(to, (const void __force *)from, n);
+        return 0;
+}
+
+static inline __must_check long __copy_to_user(void __user *to,
+                const void *from, unsigned long n)
+{
+        u32 tmp32;
+        u64 tmp64;
+
+        if (__builtin_constant_p(n)) {
+                switch (n) {
+                case 1:
+                        *(u8 __force *)to = *(u8 *)from;
+                        return 0;
+                case 4:
+                        asm volatile ("ldnw .d1t1 *%2,%0\n"
+                                      "nop  4\n"
+                                      "stnw .d1t1 %0,*%1\n"
+                                      : "=&a"(tmp32)
+                                      : "a"(to), "a"(from)
+                                      : "memory");
+                        return 0;
+                case 8:
+                        asm volatile ("ldndw .d1t1 *%2,%0\n"
+                                      "nop   4\n"
+                                      "stndw .d1t1 %0,*%1\n"
+                                      : "=&a"(tmp64)
+                                      : "a"(to), "a"(from)
+                                      : "memory");
+                        return 0;
+                default:
+                        break;
+                }
+        }
+
+        memcpy((void __force *)to, from, n);
+        return 0;
+}
+
+#define __copy_to_user   __copy_to_user
+#define __copy_from_user __copy_from_user
+
+extern int _access_ok(unsigned long addr, unsigned long size);
+#ifdef CONFIG_ACCESS_CHECK
+#define __access_ok _access_ok
+#endif
+
+#include <asm-generic/uaccess.h>
+
+#endif /* _ASM_C6X_UACCESS_H */
diff --git a/arch/c6x/include/asm/unaligned.h b/arch/c6x/include/asm/unaligned.h
new file mode 100644
index 00000000000..b976cb740ea
--- /dev/null
+++ b/arch/c6x/include/asm/unaligned.h
@@ -0,0 +1,170 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *  Rewritten for 2.6.3x: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef _ASM_C6X_UNALIGNED_H
+#define _ASM_C6X_UNALIGNED_H
+
+#include <linux/swab.h>
+
+/*
+ * The C64x+ can do unaligned word and dword accesses in hardware
+ * using special load/store instructions.
+ */
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+        const u8 *_p = p;
+        return _p[0] | _p[1] << 8;
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+        const u8 *_p = p;
+        return _p[0] << 8 | _p[1];
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+        u8 *_p = p;
+        _p[0] = val;
+        _p[1] = val >> 8;
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+        u8 *_p = p;
+        _p[0] = val >> 8;
+        _p[1] = val;
+}
+
+static inline u32 get_unaligned32(const void *p)
+{
+        u32 val = (u32) p;
+        asm (" ldnw     .d1t1   *%0,%0\n"
+             " nop     4\n"
+             : "+a"(val));
+        return val;
+}
+
+static inline void put_unaligned32(u32 val, void *p)
+{
+        asm volatile (" stnw    .d2t1   %0,*%1\n"
+                      : : "a"(val), "b"(p) : "memory");
+}
+
+static inline u64 get_unaligned64(const void *p)
+{
+        u64 val;
+        asm volatile (" ldndw   .d1t1   *%1,%0\n"
+                      " nop     4\n"
+                      : "=a"(val) : "a"(p));
+        return val;
+}
+
+static inline void put_unaligned64(u64 val, const void *p)
+{
+        asm volatile (" stndw   .d2t1   %0,*%1\n"
+                      : : "a"(val), "b"(p) : "memory");
+}
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+
+#define get_unaligned_le32(p)    __swab32(get_unaligned32(p))
+#define get_unaligned_le64(p)    __swab64(get_unaligned64(p))
+#define get_unaligned_be32(p)    get_unaligned32(p)
+#define get_unaligned_be64(p)    get_unaligned64(p)
+#define put_unaligned_le32(v, p) put_unaligned32(__swab32(v), (p))
+#define put_unaligned_le64(v, p) put_unaligned64(__swab64(v), (p))
+#define put_unaligned_be32(v, p) put_unaligned32((v), (p))
+#define put_unaligned_be64(v, p) put_unaligned64((v), (p))
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+
+#else
+
+#define get_unaligned_le32(p)    get_unaligned32(p)
+#define get_unaligned_le64(p)    get_unaligned64(p)
+#define get_unaligned_be32(p)    __swab32(get_unaligned32(p))
+#define get_unaligned_be64(p)    __swab64(get_unaligned64(p))
+#define put_unaligned_le32(v, p) put_unaligned32((v), (p))
+#define put_unaligned_le64(v, p) put_unaligned64((v), (p))
+#define put_unaligned_be32(v, p) put_unaligned32(__swab32(v), (p))
+#define put_unaligned_be64(v, p) put_unaligned64(__swab64(v), (p))
+#define get_unaligned   __get_unaligned_le
+#define put_unaligned   __put_unaligned_le
+
+#endif
+
+/*
+ * Cause a link-time error if we try an unaligned access other than
+ * 1,2,4 or 8 bytes long
+ */
+extern int __bad_unaligned_access_size(void);
+
+#define __get_unaligned_le(ptr) (typeof(*(ptr)))({                      \
+        sizeof(*(ptr)) == 1 ? *(ptr) :                                  \
+          (sizeof(*(ptr)) == 2 ? get_unaligned_le16((ptr)) :            \
+             (sizeof(*(ptr)) == 4 ? get_unaligned_le32((ptr)) :         \
+                (sizeof(*(ptr)) == 8 ? get_unaligned_le64((ptr)) :      \
+                   __bad_unaligned_access_size())));                    \
+        })
+
+#define __get_unaligned_be(ptr) (__force typeof(*(ptr)))({      \
+        sizeof(*(ptr)) == 1 ? *(ptr) :                                  \
+          (sizeof(*(ptr)) == 2 ? get_unaligned_be16((ptr)) :            \
+             (sizeof(*(ptr)) == 4 ? get_unaligned_be32((ptr)) :         \
+                (sizeof(*(ptr)) == 8 ? get_unaligned_be64((ptr)) :      \
+                   __bad_unaligned_access_size())));                    \
+        })
+
+#define __put_unaligned_le(val, ptr) ({                                 \
+        void *__gu_p = (ptr);                                           \
+        switch (sizeof(*(ptr))) {                                       \
+        case 1:                                                         \
+                *(u8 *)__gu_p = (__force u8)(val);                      \
+                break;                                                  \
+        case 2:                                                         \
+                put_unaligned_le16((__force u16)(val), __gu_p);         \
+                break;                                                  \
+        case 4:                                                         \
+                put_unaligned_le32((__force u32)(val), __gu_p);         \
+                break;                                                  \
+        case 8:                                                         \
+                put_unaligned_le64((__force u64)(val), __gu_p);         \
+                break;                                                  \
+        default:                                                        \
+                __bad_unaligned_access_size();                          \
+                break;                                                  \
+        }                                                               \
+        (void)0; })
+
+#define __put_unaligned_be(val, ptr) ({                                 \
+        void *__gu_p = (ptr);                                           \
+        switch (sizeof(*(ptr))) {                                       \
+        case 1:                                                         \
+                *(u8 *)__gu_p = (__force u8)(val);                      \
+                break;                                                  \
+        case 2:                                                         \
+                put_unaligned_be16((__force u16)(val), __gu_p);         \
+                break;                                                  \
+        case 4:                                                         \
+                put_unaligned_be32((__force u32)(val), __gu_p);         \
+                break;                                                  \
+        case 8:                                                         \
+                put_unaligned_be64((__force u64)(val), __gu_p);         \
+                break;                                                  \
+        default:                                                        \
+                __bad_unaligned_access_size();                          \
+                break;                                                  \
+        }                                                               \
+        (void)0; })
+
+#endif /* _ASM_C6X_UNALIGNED_H */
diff --git a/arch/c6x/include/asm/unistd.h b/arch/c6x/include/asm/unistd.h
new file mode 100644
index 00000000000..6d54ea4262e
--- /dev/null
+++ b/arch/c6x/include/asm/unistd.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * Based on arch/tile version.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+#if !defined(_ASM_C6X_UNISTD_H) || defined(__SYSCALL)
+#define _ASM_C6X_UNISTD_H
+
+/* Use the standard ABI for syscalls. */
+#include <asm-generic/unistd.h>
+
+/* C6X-specific syscalls. */
+#define __NR_cache_sync (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_cache_sync, sys_cache_sync)
+
+#endif /* _ASM_C6X_UNISTD_H */
diff --git a/arch/c6x/kernel/Makefile b/arch/c6x/kernel/Makefile
new file mode 100644
index 00000000000..580a515a944
--- /dev/null
+++ b/arch/c6x/kernel/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for arch/c6x/kernel/
+#
+
+extra-y := head.o vmlinux.lds
+
+obj-y := process.o traps.o irq.o signal.o ptrace.o
+obj-y += setup.o sys_c6x.o time.o devicetree.o
+obj-y += switch_to.o entry.o vectors.o c6x_ksyms.o
+obj-y += soc.o dma.o
+
+obj-$(CONFIG_MODULES)           += module.o
diff --git a/arch/c6x/kernel/asm-offsets.c b/arch/c6x/kernel/asm-offsets.c
new file mode 100644
index 00000000000..759ad6d207b
--- /dev/null
+++ b/arch/c6x/kernel/asm-offsets.c
@@ -0,0 +1,123 @@
+/*
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed
+ * to extract and format the required data.
+ */
+
+#include <linux/sched.h>
+#include <linux/thread_info.h>
+#include <asm/procinfo.h>
+#include <linux/kbuild.h>
+#include <linux/unistd.h>
+
+void foo(void)
+{
+        OFFSET(REGS_A16,        pt_regs, a16);
+        OFFSET(REGS_A17,        pt_regs, a17);
+        OFFSET(REGS_A18,        pt_regs, a18);
+        OFFSET(REGS_A19,        pt_regs, a19);
+        OFFSET(REGS_A20,        pt_regs, a20);
+        OFFSET(REGS_A21,        pt_regs, a21);
+        OFFSET(REGS_A22,        pt_regs, a22);
+        OFFSET(REGS_A23,        pt_regs, a23);
+        OFFSET(REGS_A24,        pt_regs, a24);
+        OFFSET(REGS_A25,        pt_regs, a25);
+        OFFSET(REGS_A26,        pt_regs, a26);
+        OFFSET(REGS_A27,        pt_regs, a27);
+        OFFSET(REGS_A28,        pt_regs, a28);
+        OFFSET(REGS_A29,        pt_regs, a29);
+        OFFSET(REGS_A30,        pt_regs, a30);
+        OFFSET(REGS_A31,        pt_regs, a31);
+
+        OFFSET(REGS_B16,        pt_regs, b16);
+        OFFSET(REGS_B17,        pt_regs, b17);
+        OFFSET(REGS_B18,        pt_regs, b18);
+        OFFSET(REGS_B19,        pt_regs, b19);
+        OFFSET(REGS_B20,        pt_regs, b20);
+        OFFSET(REGS_B21,        pt_regs, b21);
+        OFFSET(REGS_B22,        pt_regs, b22);
+        OFFSET(REGS_B23,        pt_regs, b23);
+        OFFSET(REGS_B24,        pt_regs, b24);
+        OFFSET(REGS_B25,        pt_regs, b25);
+        OFFSET(REGS_B26,        pt_regs, b26);
+        OFFSET(REGS_B27,        pt_regs, b27);
+        OFFSET(REGS_B28,        pt_regs, b28);
+        OFFSET(REGS_B29,        pt_regs, b29);
+        OFFSET(REGS_B30,        pt_regs, b30);
+        OFFSET(REGS_B31,        pt_regs, b31);
+
+        OFFSET(REGS_A0,         pt_regs, a0);
+        OFFSET(REGS_A1,         pt_regs, a1);
+        OFFSET(REGS_A2,         pt_regs, a2);
+        OFFSET(REGS_A3,         pt_regs, a3);
+        OFFSET(REGS_A4,         pt_regs, a4);
+        OFFSET(REGS_A5,         pt_regs, a5);
+        OFFSET(REGS_A6,         pt_regs, a6);
+        OFFSET(REGS_A7,         pt_regs, a7);
+        OFFSET(REGS_A8,         pt_regs, a8);
+        OFFSET(REGS_A9,         pt_regs, a9);
+        OFFSET(REGS_A10,        pt_regs, a10);
+        OFFSET(REGS_A11,        pt_regs, a11);
+        OFFSET(REGS_A12,        pt_regs, a12);
+        OFFSET(REGS_A13,        pt_regs, a13);
+        OFFSET(REGS_A14,        pt_regs, a14);
+        OFFSET(REGS_A15,        pt_regs, a15);
+
+        OFFSET(REGS_B0,         pt_regs, b0);
+        OFFSET(REGS_B1,         pt_regs, b1);
+        OFFSET(REGS_B2,         pt_regs, b2);
+        OFFSET(REGS_B3,         pt_regs, b3);
+        OFFSET(REGS_B4,         pt_regs, b4);
+        OFFSET(REGS_B5,         pt_regs, b5);
+        OFFSET(REGS_B6,         pt_regs, b6);
+        OFFSET(REGS_B7,         pt_regs, b7);
+        OFFSET(REGS_B8,         pt_regs, b8);
+        OFFSET(REGS_B9,         pt_regs, b9);
+        OFFSET(REGS_B10,        pt_regs, b10);
+        OFFSET(REGS_B11,        pt_regs, b11);
+        OFFSET(REGS_B12,        pt_regs, b12);
+        OFFSET(REGS_B13,        pt_regs, b13);
+        OFFSET(REGS_DP,         pt_regs, dp);
+        OFFSET(REGS_SP,         pt_regs, sp);
+
+        OFFSET(REGS_TSR,        pt_regs, tsr);
+        OFFSET(REGS_ORIG_A4,    pt_regs, orig_a4);
+
+        DEFINE(REGS__END,       sizeof(struct pt_regs));
+        BLANK();
+
+        OFFSET(THREAD_PC,       thread_struct, pc);
+        OFFSET(THREAD_B15_14,   thread_struct, b15_14);
+        OFFSET(THREAD_A15_14,   thread_struct, a15_14);
+        OFFSET(THREAD_B13_12,   thread_struct, b13_12);
+        OFFSET(THREAD_A13_12,   thread_struct, a13_12);
+        OFFSET(THREAD_B11_10,   thread_struct, b11_10);
+        OFFSET(THREAD_A11_10,   thread_struct, a11_10);
+        OFFSET(THREAD_RICL_ICL, thread_struct, ricl_icl);
+        BLANK();
+
+        OFFSET(TASK_STATE,      task_struct, state);
+        BLANK();
+
+        OFFSET(THREAD_INFO_FLAGS,       thread_info, flags);
+        OFFSET(THREAD_INFO_PREEMPT_COUNT, thread_info, preempt_count);
+        BLANK();
+
+        /* These would be unneccessary if we ran asm files
+         * through the preprocessor.
+         */
+        DEFINE(KTHREAD_SIZE, THREAD_SIZE);
+        DEFINE(KTHREAD_SHIFT, THREAD_SHIFT);
+        DEFINE(KTHREAD_START_SP, THREAD_START_SP);
+        DEFINE(ENOSYS_, ENOSYS);
+        DEFINE(NR_SYSCALLS_, __NR_syscalls);
+
+        DEFINE(_TIF_SYSCALL_TRACE, (1<<TIF_SYSCALL_TRACE));
+        DEFINE(_TIF_NOTIFY_RESUME, (1<<TIF_NOTIFY_RESUME));
+        DEFINE(_TIF_SIGPENDING, (1<<TIF_SIGPENDING));
+        DEFINE(_TIF_NEED_RESCHED, (1<<TIF_NEED_RESCHED));
+        DEFINE(_TIF_POLLING_NRFLAG, (1<<TIF_POLLING_NRFLAG));
+
+        DEFINE(_TIF_ALLWORK_MASK, TIF_ALLWORK_MASK);
+        DEFINE(_TIF_WORK_MASK, TIF_WORK_MASK);
+}
diff --git a/arch/c6x/kernel/c6x_ksyms.c b/arch/c6x/kernel/c6x_ksyms.c
new file mode 100644
index 00000000000..0ba3e0bba3e
--- /dev/null
+++ b/arch/c6x/kernel/c6x_ksyms.c
@@ -0,0 +1,66 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <asm/checksum.h>
+#include <linux/io.h>
+
+/*
+ * libgcc functions - used internally by the compiler...
+ */
+extern int __c6xabi_divi(int dividend, int divisor);
+EXPORT_SYMBOL(__c6xabi_divi);
+
+extern unsigned __c6xabi_divu(unsigned  dividend, unsigned divisor);
+EXPORT_SYMBOL(__c6xabi_divu);
+
+extern int __c6xabi_remi(int dividend, int divisor);
+EXPORT_SYMBOL(__c6xabi_remi);
+
+extern unsigned __c6xabi_remu(unsigned  dividend, unsigned divisor);
+EXPORT_SYMBOL(__c6xabi_remu);
+
+extern int __c6xabi_divremi(int dividend, int divisor);
+EXPORT_SYMBOL(__c6xabi_divremi);
+
+extern unsigned __c6xabi_divremu(unsigned  dividend, unsigned divisor);
+EXPORT_SYMBOL(__c6xabi_divremu);
+
+extern unsigned long long __c6xabi_mpyll(unsigned long long src1,
+                                         unsigned long long src2);
+EXPORT_SYMBOL(__c6xabi_mpyll);
+
+extern long long __c6xabi_negll(long long src);
+EXPORT_SYMBOL(__c6xabi_negll);
+
+extern unsigned long long __c6xabi_llshl(unsigned long long src1, uint src2);
+EXPORT_SYMBOL(__c6xabi_llshl);
+
+extern long long __c6xabi_llshr(long long src1, uint src2);
+EXPORT_SYMBOL(__c6xabi_llshr);
+
+extern unsigned long long __c6xabi_llshru(unsigned long long src1, uint src2);
+EXPORT_SYMBOL(__c6xabi_llshru);
+
+extern void __c6xabi_strasgi(int *dst, const int *src, unsigned cnt);
+EXPORT_SYMBOL(__c6xabi_strasgi);
+
+extern void __c6xabi_push_rts(void);
+EXPORT_SYMBOL(__c6xabi_push_rts);
+
+extern void __c6xabi_pop_rts(void);
+EXPORT_SYMBOL(__c6xabi_pop_rts);
+
+extern void __c6xabi_strasgi_64plus(int *dst, const int *src, unsigned cnt);
+EXPORT_SYMBOL(__c6xabi_strasgi_64plus);
+
+/* lib functions */
+EXPORT_SYMBOL(memcpy);
diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c
new file mode 100644
index 00000000000..bdb56f09d0a
--- /dev/null
+++ b/arch/c6x/kernel/devicetree.c
@@ -0,0 +1,53 @@
+/*
+ *  Architecture specific OF callbacks.
+ *
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/initrd.h>
+#include <linux/memblock.h>
+
+void __init early_init_devtree(void *params)
+{
+        /* Setup flat device-tree pointer */
+        initial_boot_params = params;
+
+        /* Retrieve various informations from the /chosen node of the
+         * device-tree, including the platform type, initrd location and
+         * size and more ...
+         */
+        of_scan_flat_dt(early_init_dt_scan_chosen, c6x_command_line);
+
+        /* Scan memory nodes and rebuild MEMBLOCKs */
+        of_scan_flat_dt(early_init_dt_scan_root, NULL);
+        of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+}
+
+
+#ifdef CONFIG_BLK_DEV_INITRD
+void __init early_init_dt_setup_initrd_arch(unsigned long start,
+                unsigned long end)
+{
+        initrd_start = (unsigned long)__va(start);
+        initrd_end = (unsigned long)__va(end);
+        initrd_below_start_ok = 1;
+}
+#endif
+
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+        c6x_add_memory(base, size);
+}
+
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+        return __va(memblock_alloc(size, align));
+}
diff --git a/arch/c6x/kernel/dma.c b/arch/c6x/kernel/dma.c
new file mode 100644
index 00000000000..ab7b12de144
--- /dev/null
+++ b/arch/c6x/kernel/dma.c
@@ -0,0 +1,153 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/mm_types.h>
+#include <linux/scatterlist.h>
+
+#include <asm/cacheflush.h>
+
+static void c6x_dma_sync(dma_addr_t handle, size_t size,
+                         enum dma_data_direction dir)
+{
+        unsigned long paddr = handle;
+
+        BUG_ON(!valid_dma_direction(dir));
+
+        switch (dir) {
+        case DMA_FROM_DEVICE:
+                L2_cache_block_invalidate(paddr, paddr + size);
+                break;
+        case DMA_TO_DEVICE:
+                L2_cache_block_writeback(paddr, paddr + size);
+                break;
+        case DMA_BIDIRECTIONAL:
+                L2_cache_block_writeback_invalidate(paddr, paddr + size);
+                break;
+        default:
+                break;
+        }
+}
+
+dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+                          enum dma_data_direction dir)
+{
+        dma_addr_t addr = virt_to_phys(ptr);
+
+        c6x_dma_sync(addr, size, dir);
+
+        debug_dma_map_page(dev, virt_to_page(ptr),
+                           (unsigned long)ptr & ~PAGE_MASK, size,
+                           dir, addr, true);
+        return addr;
+}
+EXPORT_SYMBOL(dma_map_single);
+
+
+void dma_unmap_single(struct device *dev, dma_addr_t handle,
+                      size_t size, enum dma_data_direction dir)
+{
+        c6x_dma_sync(handle, size, dir);
+
+        debug_dma_unmap_page(dev, handle, size, dir, true);
+}
+EXPORT_SYMBOL(dma_unmap_single);
+
+
+int dma_map_sg(struct device *dev, struct scatterlist *sglist,
+               int nents, enum dma_data_direction dir)
+{
+        struct scatterlist *sg;
+        int i;
+
+        for_each_sg(sglist, sg, nents, i)
+                sg->dma_address = dma_map_single(dev, sg_virt(sg), sg->length,
+                                                 dir);
+
+        debug_dma_map_sg(dev, sglist, nents, nents, dir);
+
+        return nents;
+}
+EXPORT_SYMBOL(dma_map_sg);
+
+
+void dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
+                  int nents, enum dma_data_direction dir)
+{
+        struct scatterlist *sg;
+        int i;
+
+        for_each_sg(sglist, sg, nents, i)
+                dma_unmap_single(dev, sg_dma_address(sg), sg->length, dir);
+
+        debug_dma_unmap_sg(dev, sglist, nents, dir);
+}
+EXPORT_SYMBOL(dma_unmap_sg);
+
+void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
+                             size_t size, enum dma_data_direction dir)
+{
+        c6x_dma_sync(handle, size, dir);
+
+        debug_dma_sync_single_for_cpu(dev, handle, size, dir);
+}
+EXPORT_SYMBOL(dma_sync_single_for_cpu);
+
+
+void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
+                                size_t size, enum dma_data_direction dir)
+{
+        c6x_dma_sync(handle, size, dir);
+
+        debug_dma_sync_single_for_device(dev, handle, size, dir);
+}
+EXPORT_SYMBOL(dma_sync_single_for_device);
+
+
+void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sglist,
+                         int nents, enum dma_data_direction dir)
+{
+        struct scatterlist *sg;
+        int i;
+
+        for_each_sg(sglist, sg, nents, i)
+                dma_sync_single_for_cpu(dev, sg_dma_address(sg),
+                                        sg->length, dir);
+
+        debug_dma_sync_sg_for_cpu(dev, sglist, nents, dir);
+}
+EXPORT_SYMBOL(dma_sync_sg_for_cpu);
+
+
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sglist,
+                            int nents, enum dma_data_direction dir)
+{
+        struct scatterlist *sg;
+        int i;
+
+        for_each_sg(sglist, sg, nents, i)
+                dma_sync_single_for_device(dev, sg_dma_address(sg),
+                                           sg->length, dir);
+
+        debug_dma_sync_sg_for_device(dev, sglist, nents, dir);
+}
+EXPORT_SYMBOL(dma_sync_sg_for_device);
+
+
+/* Number of entries preallocated for DMA-API debugging */
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init dma_init(void)
+{
+        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+
+        return 0;
+}
+fs_initcall(dma_init);
diff --git a/arch/c6x/kernel/entry.S b/arch/c6x/kernel/entry.S
new file mode 100644
index 00000000000..3e977ccda82
--- /dev/null
+++ b/arch/c6x/kernel/entry.S
@@ -0,0 +1,803 @@
+;
+;  Port on Texas Instruments TMS320C6x architecture
+;
+;  Copyright (C) 2004-2011 Texas Instruments Incorporated
+;  Author: Aurelien Jacquiot (aurelien.jacquiot@virtuallogix.com)
+;  Updated for 2.6.34: Mark Salter <msalter@redhat.com>
+;
+;  This program is free software; you can redistribute it and/or modify
+;  it under the terms of the GNU General Public License version 2 as
+;  published by the Free Software Foundation.
+;
+
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/thread_info.h>
+#include <asm/asm-offsets.h>
+#include <asm/unistd.h>
+#include <asm/errno.h>
+
+; Registers naming
+#define DP      B14
+#define SP      B15
+
+#ifndef CONFIG_PREEMPT
+#define resume_kernel restore_all
+#endif
+
+        .altmacro
+
+        .macro MASK_INT reg
+        MVC     .S2     CSR,reg
+        CLR     .S2     reg,0,0,reg
+        MVC     .S2     reg,CSR
+        .endm
+
+        .macro UNMASK_INT reg
+        MVC     .S2     CSR,reg
+        SET     .S2     reg,0,0,reg
+        MVC     .S2     reg,CSR
+        .endm
+
+        .macro GET_THREAD_INFO reg
+        SHR     .S1X    SP,THREAD_SHIFT,reg
+        SHL     .S1     reg,THREAD_SHIFT,reg
+        .endm
+
+        ;;
+        ;;  This defines the normal kernel pt_regs layout.
+        ;;
+        .macro SAVE_ALL __rp __tsr
+        STW     .D2T2   B0,*SP--[2]             ; save original B0
+        MVKL    .S2     current_ksp,B0
+        MVKH    .S2     current_ksp,B0
+        LDW     .D2T2   *B0,B1                  ; KSP
+
+        NOP     3
+        STW     .D2T2   B1,*+SP[1]              ; save original B1
+        XOR     .D2     SP,B1,B0                ; (SP ^ KSP)
+        LDW     .D2T2   *+SP[1],B1              ; restore B0/B1
+        LDW     .D2T2   *++SP[2],B0
+        SHR     .S2     B0,THREAD_SHIFT,B0      ; 0 if already using kstack
+  [B0]  STDW    .D2T2   SP:DP,*--B1[1]          ; user: save user sp/dp kstack
+  [B0]  MV      .S2     B1,SP                   ;    and switch to kstack
+||[!B0] STDW    .D2T2   SP:DP,*--SP[1]          ; kernel: save on current stack
+
+        SUBAW   .D2     SP,2,SP
+
+        ADD     .D1X    SP,-8,A15
+ ||     STDW    .D2T1   A15:A14,*SP--[16]       ; save A15:A14
+
+        STDW    .D2T2   B13:B12,*SP--[1]
+ ||     STDW    .D1T1   A13:A12,*A15--[1]
+ ||     MVC     .S2     __rp,B13
+
+        STDW    .D2T2   B11:B10,*SP--[1]
+ ||     STDW    .D1T1   A11:A10,*A15--[1]
+ ||     MVC     .S2     CSR,B12
+
+        STDW    .D2T2   B9:B8,*SP--[1]
+ ||     STDW    .D1T1   A9:A8,*A15--[1]
+ ||     MVC     .S2     RILC,B11
+        STDW    .D2T2   B7:B6,*SP--[1]
+ ||     STDW    .D1T1   A7:A6,*A15--[1]
+ ||     MVC     .S2     ILC,B10
+
+        STDW    .D2T2   B5:B4,*SP--[1]
+ ||     STDW    .D1T1   A5:A4,*A15--[1]
+
+        STDW    .D2T2   B3:B2,*SP--[1]
+ ||     STDW    .D1T1   A3:A2,*A15--[1]
+ ||     MVC     .S2     __tsr,B5
+
+        STDW    .D2T2   B1:B0,*SP--[1]
+ ||     STDW    .D1T1   A1:A0,*A15--[1]
+ ||     MV      .S1X    B5,A5
+
+        STDW    .D2T2   B31:B30,*SP--[1]
+ ||     STDW    .D1T1   A31:A30,*A15--[1]
+        STDW    .D2T2   B29:B28,*SP--[1]
+ ||     STDW    .D1T1   A29:A28,*A15--[1]
+        STDW    .D2T2   B27:B26,*SP--[1]
+ ||     STDW    .D1T1   A27:A26,*A15--[1]
+        STDW    .D2T2   B25:B24,*SP--[1]
+ ||     STDW    .D1T1   A25:A24,*A15--[1]
+        STDW    .D2T2   B23:B22,*SP--[1]
+ ||     STDW    .D1T1   A23:A22,*A15--[1]
+        STDW    .D2T2   B21:B20,*SP--[1]
+ ||     STDW    .D1T1   A21:A20,*A15--[1]
+        STDW    .D2T2   B19:B18,*SP--[1]
+ ||     STDW    .D1T1   A19:A18,*A15--[1]
+        STDW    .D2T2   B17:B16,*SP--[1]
+ ||     STDW    .D1T1   A17:A16,*A15--[1]
+
+        STDW    .D2T2   B13:B12,*SP--[1]        ; save PC and CSR
+
+        STDW    .D2T2   B11:B10,*SP--[1]        ; save RILC and ILC
+        STDW    .D2T1   A5:A4,*SP--[1]          ; save TSR and orig A4
+
+        ;; We left an unused word on the stack just above pt_regs.
+        ;; It is used to save whether or not this frame is due to
+        ;; a syscall. It is cleared here, but the syscall handler
+        ;; sets it to a non-zero value.
+        MVK     .L2     0,B1
+        STW     .D2T2   B1,*+SP(REGS__END+8)    ; clear syscall flag
+        .endm
+
+        .macro RESTORE_ALL __rp __tsr
+        LDDW    .D2T2   *++SP[1],B9:B8          ; get TSR (B9)
+        LDDW    .D2T2   *++SP[1],B11:B10        ; get RILC (B11) and ILC (B10)
+        LDDW    .D2T2   *++SP[1],B13:B12        ; get PC (B13) and CSR (B12)
+
+        ADDAW   .D1X    SP,30,A15
+
+        LDDW    .D1T1   *++A15[1],A17:A16
+ ||     LDDW    .D2T2   *++SP[1],B17:B16
+        LDDW    .D1T1   *++A15[1],A19:A18
+ ||     LDDW    .D2T2   *++SP[1],B19:B18
+        LDDW    .D1T1   *++A15[1],A21:A20
+ ||     LDDW    .D2T2   *++SP[1],B21:B20
+        LDDW    .D1T1   *++A15[1],A23:A22
+ ||     LDDW    .D2T2   *++SP[1],B23:B22
+        LDDW    .D1T1   *++A15[1],A25:A24
+ ||     LDDW    .D2T2   *++SP[1],B25:B24
+        LDDW    .D1T1   *++A15[1],A27:A26
+ ||     LDDW    .D2T2   *++SP[1],B27:B26
+        LDDW    .D1T1   *++A15[1],A29:A28
+ ||     LDDW    .D2T2   *++SP[1],B29:B28
+        LDDW    .D1T1   *++A15[1],A31:A30
+ ||     LDDW    .D2T2   *++SP[1],B31:B30
+
+        LDDW    .D1T1   *++A15[1],A1:A0
+ ||     LDDW    .D2T2   *++SP[1],B1:B0
+
+        LDDW    .D1T1   *++A15[1],A3:A2
+ ||     LDDW    .D2T2   *++SP[1],B3:B2
+ ||     MVC     .S2     B9,__tsr
+        LDDW    .D1T1   *++A15[1],A5:A4
+ ||     LDDW    .D2T2   *++SP[1],B5:B4
+ ||     MVC     .S2     B11,RILC
+        LDDW    .D1T1   *++A15[1],A7:A6
+ ||     LDDW    .D2T2   *++SP[1],B7:B6
+ ||     MVC     .S2     B10,ILC
+
+        LDDW    .D1T1   *++A15[1],A9:A8
+ ||     LDDW    .D2T2   *++SP[1],B9:B8
+ ||     MVC     .S2     B13,__rp
+
+        LDDW    .D1T1   *++A15[1],A11:A10
+ ||     LDDW    .D2T2   *++SP[1],B11:B10
+ ||     MVC     .S2     B12,CSR
+
+        LDDW    .D1T1   *++A15[1],A13:A12
+ ||     LDDW    .D2T2   *++SP[1],B13:B12
+
+        MV      .D2X    A15,SP
+ ||     MVKL    .S1     current_ksp,A15
+        MVKH    .S1     current_ksp,A15
+ ||     ADDAW   .D1X    SP,6,A14
+        STW     .D1T1   A14,*A15        ; save kernel stack pointer
+
+        LDDW    .D2T1   *++SP[1],A15:A14
+
+        B       .S2     __rp            ; return from interruption
+        LDDW    .D2T2   *+SP[1],SP:DP
+        NOP     4
+        .endm
+
+        .section .text
+
+        ;;
+        ;; Jump to schedule() then return to ret_from_exception
+        ;;
+_reschedule:
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     schedule,A0
+        MVKH    .S1     schedule,A0
+        B       .S2X    A0
+#else
+        B       .S1     schedule
+#endif
+        ADDKPC  .S2     ret_from_exception,B3,4
+
+        ;;
+        ;; Called before syscall handler when process is being debugged
+        ;;
+tracesys_on:
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     syscall_trace_entry,A0
+        MVKH    .S1     syscall_trace_entry,A0
+        B       .S2X    A0
+#else
+        B       .S1     syscall_trace_entry
+#endif
+        ADDKPC  .S2     ret_from_syscall_trace,B3,3
+        ADD     .S1X    8,SP,A4
+
+ret_from_syscall_trace:
+        ;; tracing returns (possibly new) syscall number
+        MV      .D2X    A4,B0
+ ||     MVK     .S2     __NR_syscalls,B1
+        CMPLTU  .L2     B0,B1,B1
+
+ [!B1]  BNOP    .S2     ret_from_syscall_function,5
+ ||     MVK     .S1     -ENOSYS,A4
+
+        ;; reload syscall args from (possibly modified) stack frame
+        ;; and get syscall handler addr from sys_call_table:
+        LDW     .D2T2   *+SP(REGS_B4+8),B4
+ ||     MVKL    .S2     sys_call_table,B1
+        LDW     .D2T1   *+SP(REGS_A6+8),A6
+ ||     MVKH    .S2     sys_call_table,B1
+        LDW     .D2T2   *+B1[B0],B0
+ ||     MVKL    .S2     ret_from_syscall_function,B3
+        LDW     .D2T2   *+SP(REGS_B6+8),B6
+ ||     MVKH    .S2     ret_from_syscall_function,B3
+        LDW     .D2T1   *+SP(REGS_A8+8),A8
+        LDW     .D2T2   *+SP(REGS_B8+8),B8
+        NOP
+        ; B0 = sys_call_table[__NR_*]
+        BNOP    .S2     B0,5                    ; branch to syscall handler
+ ||     LDW     .D2T1   *+SP(REGS_ORIG_A4+8),A4
+
+syscall_exit_work:
+        AND     .D1     _TIF_SYSCALL_TRACE,A2,A0
+ [!A0]  BNOP    .S1     work_pending,5
+ [A0]   B       .S2     syscall_trace_exit
+        ADDKPC  .S2     resume_userspace,B3,1
+        MVC     .S2     CSR,B1
+        SET     .S2     B1,0,0,B1
+        MVC     .S2     B1,CSR          ; enable ints
+
+work_pending:
+        AND     .D1     _TIF_NEED_RESCHED,A2,A0
+ [!A0]  BNOP    .S1     work_notifysig,5
+
+work_resched:
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     schedule,A1
+        MVKH    .S1     schedule,A1
+        B       .S2X    A1
+#else
+        B       .S2     schedule
+#endif
+        ADDKPC  .S2     work_rescheduled,B3,4
+work_rescheduled:
+        ;; make sure we don't miss an interrupt setting need_resched or
+        ;; sigpending between sampling and the rti
+        MASK_INT B2
+        GET_THREAD_INFO A12
+        LDW     .D1T1   *+A12(THREAD_INFO_FLAGS),A2
+        MVK     .S1     _TIF_WORK_MASK,A1
+        MVK     .S1     _TIF_NEED_RESCHED,A3
+        NOP     2
+        AND     .D1     A1,A2,A0
+ ||     AND     .S1     A3,A2,A1
+ [!A0]  BNOP    .S1     restore_all,5
+ [A1]   BNOP    .S1     work_resched,5
+
+work_notifysig:
+        B       .S2     do_notify_resume
+        LDW     .D2T1   *+SP(REGS__END+8),A6 ; syscall flag
+        ADDKPC  .S2     resume_userspace,B3,1
+        ADD     .S1X    8,SP,A4         ; pt_regs pointer is first arg
+        MV      .D2X    A2,B4           ; thread_info flags is second arg
+
+        ;;
+        ;; On C64x+, the return way from exception and interrupt
+        ;; is a little bit different
+        ;;
+ENTRY(ret_from_exception)
+#ifdef CONFIG_PREEMPT
+        MASK_INT B2
+#endif
+
+ENTRY(ret_from_interrupt)
+        ;;
+        ;; Check if we are comming from user mode.
+        ;;
+        LDW     .D2T2   *+SP(REGS_TSR+8),B0
+        MVK     .S2     0x40,B1
+        NOP     3
+        AND     .D2     B0,B1,B0
+ [!B0]  BNOP    .S2     resume_kernel,5
+
+resume_userspace:
+        ;; make sure we don't miss an interrupt setting need_resched or
+        ;; sigpending between sampling and the rti
+        MASK_INT B2
+        GET_THREAD_INFO A12
+        LDW     .D1T1   *+A12(THREAD_INFO_FLAGS),A2
+        MVK     .S1     _TIF_WORK_MASK,A1
+        MVK     .S1     _TIF_NEED_RESCHED,A3
+        NOP     2
+        AND     .D1     A1,A2,A0
+ [A0]   BNOP    .S1     work_pending,5
+        BNOP    .S1     restore_all,5
+
+        ;;
+        ;; System call handling
+        ;; B0 = syscall number (in sys_call_table)
+        ;; A4,B4,A6,B6,A8,B8 = arguments of the syscall function
+        ;; A4 is the return value register
+        ;;
+system_call_saved:
+        MVK     .L2     1,B2
+        STW     .D2T2   B2,*+SP(REGS__END+8)    ; set syscall flag
+        MVC     .S2     B2,ECR                  ; ack the software exception
+
+        UNMASK_INT B2                   ; re-enable global IT
+
+system_call_saved_noack:
+        ;; Check system call number
+        MVK     .S2     __NR_syscalls,B1
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_ni_syscall,A0
+#endif
+        CMPLTU  .L2     B0,B1,B1
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKH    .S1     sys_ni_syscall,A0
+#endif
+
+        ;; Check for ptrace
+        GET_THREAD_INFO A12
+
+#ifdef CONFIG_C6X_BIG_KERNEL
+ [!B1]  B       .S2X    A0
+#else
+ [!B1]  B       .S2     sys_ni_syscall
+#endif
+ [!B1]  ADDKPC  .S2     ret_from_syscall_function,B3,4
+
+        ;; Get syscall handler addr from sys_call_table
+        ;; call tracesys_on or call syscall handler
+        LDW     .D1T1   *+A12(THREAD_INFO_FLAGS),A2
+ ||     MVKL    .S2     sys_call_table,B1
+        MVKH    .S2     sys_call_table,B1
+        LDW     .D2T2   *+B1[B0],B0
+        NOP     2
+        ; A2 = thread_info flags
+        AND     .D1     _TIF_SYSCALL_TRACE,A2,A2
+ [A2]   BNOP    .S1     tracesys_on,5
+        ;; B0 = _sys_call_table[__NR_*]
+        B       .S2     B0
+        ADDKPC  .S2     ret_from_syscall_function,B3,4
+
+ret_from_syscall_function:
+        STW     .D2T1   A4,*+SP(REGS_A4+8)      ; save return value in A4
+                                                ; original A4 is in orig_A4
+syscall_exit:
+        ;; make sure we don't miss an interrupt setting need_resched or
+        ;; sigpending between sampling and the rti
+        MASK_INT B2
+        LDW     .D1T1   *+A12(THREAD_INFO_FLAGS),A2
+        MVK     .S1     _TIF_ALLWORK_MASK,A1
+        NOP     3
+        AND     .D1     A1,A2,A2 ; check for work to do
+ [A2]   BNOP    .S1     syscall_exit_work,5
+
+restore_all:
+        RESTORE_ALL NRP,NTSR
+
+        ;;
+        ;; After a fork we jump here directly from resume,
+        ;; so that A4 contains the previous task structure.
+        ;;
+ENTRY(ret_from_fork)
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     schedule_tail,A0
+        MVKH    .S1     schedule_tail,A0
+        B       .S2X    A0
+#else
+        B       .S2     schedule_tail
+#endif
+        ADDKPC  .S2     ret_from_fork_2,B3,4
+ret_from_fork_2:
+        ;; return 0 in A4 for child process
+        GET_THREAD_INFO A12
+        BNOP    .S2     syscall_exit,3
+        MVK     .L2     0,B0
+        STW     .D2T2   B0,*+SP(REGS_A4+8)
+ENDPROC(ret_from_fork)
+
+        ;;
+        ;; These are the interrupt handlers, responsible for calling __do_IRQ()
+        ;; int6 is used for syscalls (see _system_call entry)
+        ;;
+        .macro SAVE_ALL_INT
+        SAVE_ALL IRP,ITSR
+        .endm
+
+        .macro CALL_INT int
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     c6x_do_IRQ,A0
+        MVKH    .S1     c6x_do_IRQ,A0
+        BNOP    .S2X    A0,1
+        MVK     .S1     int,A4
+        ADDAW   .D2     SP,2,B4
+        MVKL    .S2     ret_from_interrupt,B3
+        MVKH    .S2     ret_from_interrupt,B3
+#else
+        CALLP   .S2     c6x_do_IRQ,B3
+ ||     MVK     .S1     int,A4
+ ||     ADDAW   .D2     SP,2,B4
+        B       .S1     ret_from_interrupt
+        NOP     5
+#endif
+        .endm
+
+ENTRY(_int4_handler)
+        SAVE_ALL_INT
+        CALL_INT 4
+ENDPROC(_int4_handler)
+
+ENTRY(_int5_handler)
+        SAVE_ALL_INT
+        CALL_INT 5
+ENDPROC(_int5_handler)
+
+ENTRY(_int6_handler)
+        SAVE_ALL_INT
+        CALL_INT 6
+ENDPROC(_int6_handler)
+
+ENTRY(_int7_handler)
+        SAVE_ALL_INT
+        CALL_INT 7
+ENDPROC(_int7_handler)
+
+ENTRY(_int8_handler)
+        SAVE_ALL_INT
+        CALL_INT 8
+ENDPROC(_int8_handler)
+
+ENTRY(_int9_handler)
+        SAVE_ALL_INT
+        CALL_INT 9
+ENDPROC(_int9_handler)
+
+ENTRY(_int10_handler)
+        SAVE_ALL_INT
+        CALL_INT 10
+ENDPROC(_int10_handler)
+
+ENTRY(_int11_handler)
+        SAVE_ALL_INT
+        CALL_INT 11
+ENDPROC(_int11_handler)
+
+ENTRY(_int12_handler)
+        SAVE_ALL_INT
+        CALL_INT 12
+ENDPROC(_int12_handler)
+
+ENTRY(_int13_handler)
+        SAVE_ALL_INT
+        CALL_INT 13
+ENDPROC(_int13_handler)
+
+ENTRY(_int14_handler)
+        SAVE_ALL_INT
+        CALL_INT 14
+ENDPROC(_int14_handler)
+
+ENTRY(_int15_handler)
+        SAVE_ALL_INT
+        CALL_INT 15
+ENDPROC(_int15_handler)
+
+        ;;
+        ;; Handler for uninitialized and spurious interrupts
+        ;;
+ENTRY(_bad_interrupt)
+        B       .S2     IRP
+        NOP     5
+ENDPROC(_bad_interrupt)
+
+        ;;
+        ;; Entry for NMI/exceptions/syscall
+        ;;
+ENTRY(_nmi_handler)
+        SAVE_ALL NRP,NTSR
+
+        MVC     .S2     EFR,B2
+        CMPEQ   .L2     1,B2,B2
+ ||     MVC     .S2     TSR,B1
+        CLR     .S2     B1,10,10,B1
+        MVC     .S2     B1,TSR
+#ifdef CONFIG_C6X_BIG_KERNEL
+ [!B2]  MVKL    .S1     process_exception,A0
+ [!B2]  MVKH    .S1     process_exception,A0
+ [!B2]  B       .S2X    A0
+#else
+ [!B2]  B       .S2     process_exception
+#endif
+ [B2]   B       .S2     system_call_saved
+ [!B2]  ADDAW   .D2     SP,2,B1
+ [!B2]  MV      .D1X    B1,A4
+        ADDKPC  .S2     ret_from_trap,B3,2
+
+ret_from_trap:
+        MV      .D2X    A4,B0
+ [!B0]  BNOP    .S2     ret_from_exception,5
+
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S2     system_call_saved_noack,B3
+        MVKH    .S2     system_call_saved_noack,B3
+#endif
+        LDW     .D2T2   *+SP(REGS_B0+8),B0
+        LDW     .D2T1   *+SP(REGS_A4+8),A4
+        LDW     .D2T2   *+SP(REGS_B4+8),B4
+        LDW     .D2T1   *+SP(REGS_A6+8),A6
+        LDW     .D2T2   *+SP(REGS_B6+8),B6
+        LDW     .D2T1   *+SP(REGS_A8+8),A8
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     B       .S2     B3
+#else
+ ||     B       .S2     system_call_saved_noack
+#endif
+        LDW     .D2T2   *+SP(REGS_B8+8),B8
+        NOP     4
+ENDPROC(_nmi_handler)
+
+        ;;
+        ;; Jump to schedule() then return to ret_from_isr
+        ;;
+#ifdef  CONFIG_PREEMPT
+resume_kernel:
+        GET_THREAD_INFO A12
+        LDW     .D1T1   *+A12(THREAD_INFO_PREEMPT_COUNT),A1
+        NOP     4
+ [A1]   BNOP    .S2     restore_all,5
+
+preempt_schedule:
+        GET_THREAD_INFO A2
+        LDW     .D1T1   *+A2(THREAD_INFO_FLAGS),A1
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S2     preempt_schedule_irq,B0
+        MVKH    .S2     preempt_schedule_irq,B0
+        NOP     2
+#else
+        NOP     4
+#endif
+        AND     .D1     _TIF_NEED_RESCHED,A1,A1
+ [!A1]  BNOP    .S2     restore_all,5
+#ifdef CONFIG_C6X_BIG_KERNEL
+        B       .S2     B0
+#else
+        B       .S2     preempt_schedule_irq
+#endif
+        ADDKPC  .S2     preempt_schedule,B3,4
+#endif /* CONFIG_PREEMPT */
+
+ENTRY(enable_exception)
+        DINT
+        MVC     .S2     TSR,B0
+        MVC     .S2     B3,NRP
+        MVK     .L2     0xc,B1
+        OR      .D2     B0,B1,B0
+        MVC     .S2     B0,TSR                  ;  Set GEE and XEN in TSR
+        B       .S2     NRP
+        NOP     5
+ENDPROC(enable_exception)
+
+ENTRY(sys_sigaltstack)
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     do_sigaltstack,A0       ; branch to do_sigaltstack
+        MVKH    .S1     do_sigaltstack,A0
+        B       .S2X    A0
+#else
+        B       .S2     do_sigaltstack
+#endif
+        LDW     .D2T1   *+SP(REGS_SP+8),A6
+        NOP     4
+ENDPROC(sys_sigaltstack)
+
+        ;; kernel_execve
+ENTRY(kernel_execve)
+        MVK     .S2     __NR_execve,B0
+        SWE
+        BNOP    .S2     B3,5
+ENDPROC(kernel_execve)
+
+        ;;
+        ;; Special system calls
+        ;; return address is in B3
+        ;;
+ENTRY(sys_clone)
+        ADD     .D1X    SP,8,A4
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_c6x_clone,A0
+        MVKH    .S1     sys_c6x_clone,A0
+        BNOP    .S2X    A0,5
+#else
+ ||     B       .S2     sys_c6x_clone
+        NOP     5
+#endif
+ENDPROC(sys_clone)
+
+ENTRY(sys_rt_sigreturn)
+        ADD     .D1X    SP,8,A4
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     do_rt_sigreturn,A0
+        MVKH    .S1     do_rt_sigreturn,A0
+        BNOP    .S2X    A0,5
+#else
+ ||     B       .S2     do_rt_sigreturn
+        NOP     5
+#endif
+ENDPROC(sys_rt_sigreturn)
+
+ENTRY(sys_execve)
+        ADDAW   .D2     SP,2,B6         ; put regs addr in 4th parameter
+                                        ; & adjust regs stack addr
+        LDW     .D2T2   *+SP(REGS_B4+8),B4
+
+        ;; c6x_execve(char *name, char **argv,
+        ;;            char **envp, struct pt_regs *regs)
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_c6x_execve,A0
+        MVKH    .S1     sys_c6x_execve,A0
+        B       .S2X    A0
+#else
+ ||     B       .S2     sys_c6x_execve
+#endif
+        STW     .D2T2   B3,*SP--[2]
+        ADDKPC  .S2     ret_from_c6x_execve,B3,3
+
+ret_from_c6x_execve:
+        LDW     .D2T2   *++SP[2],B3
+        NOP     4
+        BNOP    .S2     B3,5
+ENDPROC(sys_execve)
+
+ENTRY(sys_pread_c6x)
+        MV      .D2X    A8,B7
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_pread64,A0
+        MVKH    .S1     sys_pread64,A0
+        BNOP    .S2X    A0,5
+#else
+ ||     B       .S2     sys_pread64
+        NOP     5
+#endif
+ENDPROC(sys_pread_c6x)
+
+ENTRY(sys_pwrite_c6x)
+        MV      .D2X    A8,B7
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_pwrite64,A0
+        MVKH    .S1     sys_pwrite64,A0
+        BNOP    .S2X    A0,5
+#else
+ ||     B       .S2     sys_pwrite64
+        NOP     5
+#endif
+ENDPROC(sys_pwrite_c6x)
+
+;; On Entry
+;;   A4 - path
+;;   B4 - offset_lo (LE), offset_hi (BE)
+;;   A6 - offset_lo (BE), offset_hi (LE)
+ENTRY(sys_truncate64_c6x)
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        MV      .S2     B4,B5
+        MV      .D2X    A6,B4
+#else
+        MV      .D2X    A6,B5
+#endif
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_truncate64,A0
+        MVKH    .S1     sys_truncate64,A0
+        BNOP    .S2X    A0,5
+#else
+ ||     B       .S2     sys_truncate64
+        NOP     5
+#endif
+ENDPROC(sys_truncate64_c6x)
+
+;; On Entry
+;;   A4 - fd
+;;   B4 - offset_lo (LE), offset_hi (BE)
+;;   A6 - offset_lo (BE), offset_hi (LE)
+ENTRY(sys_ftruncate64_c6x)
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        MV      .S2     B4,B5
+        MV      .D2X    A6,B4
+#else
+        MV      .D2X    A6,B5
+#endif
+#ifdef CONFIG_C6X_BIG_KERNEL
+ ||     MVKL    .S1     sys_ftruncate64,A0
+        MVKH    .S1     sys_ftruncate64,A0
+        BNOP    .S2X    A0,5
+#else
+ ||     B       .S2     sys_ftruncate64
+        NOP     5
+#endif
+ENDPROC(sys_ftruncate64_c6x)
+
+#ifdef __ARCH_WANT_SYSCALL_OFF_T
+;; On Entry
+;;   A4 - fd
+;;   B4 - offset_lo (LE), offset_hi (BE)
+;;   A6 - offset_lo (BE), offset_hi (LE)
+;;   B6 - len
+;;   A8 - advice
+ENTRY(sys_fadvise64_c6x)
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     sys_fadvise64,A0
+        MVKH    .S1     sys_fadvise64,A0
+        BNOP    .S2X    A0,2
+#else
+        B       .S2     sys_fadvise64
+        NOP     2
+#endif
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        MV      .L2     B4,B5
+ ||     MV      .D2X    A6,B4
+#else
+        MV      .D2X    A6,B5
+#endif
+        MV      .D1X    B6,A6
+        MV      .D2X    A8,B6
+#endif
+ENDPROC(sys_fadvise64_c6x)
+
+;; On Entry
+;;   A4 - fd
+;;   B4 - offset_lo (LE), offset_hi (BE)
+;;   A6 - offset_lo (BE), offset_hi (LE)
+;;   B6 - len_lo (LE), len_hi (BE)
+;;   A8 - len_lo (BE), len_hi (LE)
+;;   B8 - advice
+ENTRY(sys_fadvise64_64_c6x)
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     sys_fadvise64_64,A0
+        MVKH    .S1     sys_fadvise64_64,A0
+        BNOP    .S2X    A0,2
+#else
+        B       .S2     sys_fadvise64_64
+        NOP     2
+#endif
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        MV      .L2     B4,B5
+ ||     MV      .D2X    A6,B4
+        MV      .L1     A8,A6
+ ||     MV      .D1X    B6,A7
+#else
+        MV      .D2X    A6,B5
+        MV      .L1     A8,A7
+ ||     MV      .D1X    B6,A6
+#endif
+        MV      .L2     B8,B6
+ENDPROC(sys_fadvise64_64_c6x)
+
+;; On Entry
+;;   A4 - fd
+;;   B4 - mode
+;;   A6 - offset_hi
+;;   B6 - offset_lo
+;;   A8 - len_hi
+;;   B8 - len_lo
+ENTRY(sys_fallocate_c6x)
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     sys_fallocate,A0
+        MVKH    .S1     sys_fallocate,A0
+        BNOP    .S2X    A0,1
+#else
+        B       .S2     sys_fallocate
+        NOP
+#endif
+        MV      .D1     A6,A7
+        MV      .D1X    B6,A6
+        MV      .D2X    A8,B7
+        MV      .D2     B8,B6
+ENDPROC(sys_fallocate_c6x)
+
+        ;; put this in .neardata for faster access when using DSBT mode
+        .section .neardata,"aw",@progbits
+        .global current_ksp
+        .hidden current_ksp
+current_ksp:
+        .word   init_thread_union + THREAD_START_SP
diff --git a/arch/c6x/kernel/head.S b/arch/c6x/kernel/head.S
new file mode 100644
index 00000000000..133eab6edf6
--- /dev/null
+++ b/arch/c6x/kernel/head.S
@@ -0,0 +1,84 @@
+;
+;  Port on Texas Instruments TMS320C6x architecture
+;
+;  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+;  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+;
+;  This program is free software; you can redistribute it and/or modify
+;  it under the terms of the GNU General Public License version 2 as
+;  published by the Free Software Foundation.
+;
+#include <linux/linkage.h>
+#include <linux/of_fdt.h>
+#include <asm/asm-offsets.h>
+
+        __HEAD
+ENTRY(_c_int00)
+        ;; Save magic and pointer
+        MV      .S1     A4,A10
+        MV      .S2     B4,B10
+        MVKL    .S2     __bss_start,B5
+        MVKH    .S2     __bss_start,B5
+        MVKL    .S2     __bss_stop,B6
+        MVKH    .S2     __bss_stop,B6
+        SUB     .L2     B6,B5,B6 ; bss size
+
+        ;; Set the stack pointer
+        MVKL    .S2     current_ksp,B0
+        MVKH    .S2     current_ksp,B0
+        LDW     .D2T2   *B0,B15
+
+        ;; clear bss
+        SHR     .S2     B6,3,B0   ; number of dwords to clear
+        ZERO    .L2     B13
+        ZERO    .L2     B12
+bss_loop:
+        BDEC    .S2     bss_loop,B0
+        NOP     3
+        CMPLT   .L2     B0,0,B1
+ [!B1]  STDW    .D2T2   B13:B12,*B5++[1]
+
+        NOP     4
+        AND     .D2     ~7,B15,B15
+
+        ;; Clear GIE and PGIE
+        MVC     .S2     CSR,B2
+        CLR     .S2     B2,0,1,B2
+        MVC     .S2     B2,CSR
+        MVC     .S2     TSR,B2
+        CLR     .S2     B2,0,1,B2
+        MVC     .S2     B2,TSR
+        MVC     .S2     ITSR,B2
+        CLR     .S2     B2,0,1,B2
+        MVC     .S2     B2,ITSR
+        MVC     .S2     NTSR,B2
+        CLR     .S2     B2,0,1,B2
+        MVC     .S2     B2,NTSR
+
+        ;; pass DTB pointer to machine_init (or zero if none)
+        MVKL    .S1     OF_DT_HEADER,A0
+        MVKH    .S1     OF_DT_HEADER,A0
+        CMPEQ   .L1     A10,A0,A0
+  [A0]  MV      .S1X    B10,A4
+  [!A0] MVK     .S1     0,A4
+
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     machine_init,A0
+        MVKH    .S1     machine_init,A0
+        B       .S2X    A0
+        ADDKPC  .S2     0f,B3,4
+0:
+#else
+        CALLP   .S2     machine_init,B3
+#endif
+
+        ;; Jump to Linux init
+#ifdef CONFIG_C6X_BIG_KERNEL
+        MVKL    .S1     start_kernel,A0
+        MVKH    .S1     start_kernel,A0
+        B       .S2X    A0
+#else
+        B       .S2     start_kernel
+#endif
+        NOP     5
+L1:     BNOP    .S2     L1,5
diff --git a/arch/c6x/kernel/irq.c b/arch/c6x/kernel/irq.c
new file mode 100644
index 00000000000..0929e4b2b24
--- /dev/null
+++ b/arch/c6x/kernel/irq.c
@@ -0,0 +1,728 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ *  This borrows heavily from powerpc version, which is:
+ *
+ *  Derived from arch/i386/kernel/irq.c
+ *    Copyright (C) 1992 Linus Torvalds
+ *  Adapted from arch/i386 by Gary Thomas
+ *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *  Updated and modified by Cort Dougan <cort@fsmlabs.com>
+ *    Copyright (C) 1996-2001 Cort Dougan
+ *  Adapted for Power Macintosh by Paul Mackerras
+ *    Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/radix-tree.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+
+#include <asm/megamod-pic.h>
+
+unsigned long irq_err_count;
+
+static DEFINE_RAW_SPINLOCK(core_irq_lock);
+
+static void mask_core_irq(struct irq_data *data)
+{
+        unsigned int prio = data->irq;
+
+        BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);
+
+        raw_spin_lock(&core_irq_lock);
+        and_creg(IER, ~(1 << prio));
+        raw_spin_unlock(&core_irq_lock);
+}
+
+static void unmask_core_irq(struct irq_data *data)
+{
+        unsigned int prio = data->irq;
+
+        raw_spin_lock(&core_irq_lock);
+        or_creg(IER, 1 << prio);
+        raw_spin_unlock(&core_irq_lock);
+}
+
+static struct irq_chip core_chip = {
+        .name           = "core",
+        .irq_mask       = mask_core_irq,
+        .irq_unmask     = unmask_core_irq,
+};
+
+asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        irq_enter();
+
+        BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);
+
+        generic_handle_irq(prio);
+
+        irq_exit();
+
+        set_irq_regs(old_regs);
+}
+
+static struct irq_host *core_host;
+
+static int core_host_map(struct irq_host *h, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+        if (hw < 4 || hw >= NR_PRIORITY_IRQS)
+                return -EINVAL;
+
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &core_chip, handle_level_irq);
+        return 0;
+}
+
+static struct irq_host_ops core_host_ops = {
+        .map = core_host_map,
+};
+
+void __init init_IRQ(void)
+{
+        struct device_node *np;
+
+        /* Mask all priority IRQs */
+        and_creg(IER, ~0xfff0);
+
+        np = of_find_compatible_node(NULL, NULL, "ti,c64x+core-pic");
+        if (np != NULL) {
+                /* create the core host */
+                core_host = irq_alloc_host(np, IRQ_HOST_MAP_PRIORITY, 0,
+                                           &core_host_ops, 0);
+                if (core_host)
+                        irq_set_default_host(core_host);
+                of_node_put(np);
+        }
+
+        printk(KERN_INFO "Core interrupt controller initialized\n");
+
+        /* now we're ready for other SoC controllers */
+        megamod_pic_init();
+
+        /* Clear all general IRQ flags */
+        set_creg(ICR, 0xfff0);
+}
+
+void ack_bad_irq(int irq)
+{
+        printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
+        irq_err_count++;
+}
+
+int arch_show_interrupts(struct seq_file *p, int prec)
+{
+        seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
+        return 0;
+}
+
+/*
+ * IRQ controller and virtual interrupts
+ */
+
+/* The main irq map itself is an array of NR_IRQ entries containing the
+ * associate host and irq number. An entry with a host of NULL is free.
+ * An entry can be allocated if it's free, the allocator always then sets
+ * hwirq first to the host's invalid irq number and then fills ops.
+ */
+struct irq_map_entry {
+        irq_hw_number_t hwirq;
+        struct irq_host *host;
+};
+
+static LIST_HEAD(irq_hosts);
+static DEFINE_RAW_SPINLOCK(irq_big_lock);
+static DEFINE_MUTEX(revmap_trees_mutex);
+static struct irq_map_entry irq_map[NR_IRQS];
+static unsigned int irq_virq_count = NR_IRQS;
+static struct irq_host *irq_default_host;
+
+irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
+{
+        return irq_map[d->irq].hwirq;
+}
+EXPORT_SYMBOL_GPL(irqd_to_hwirq);
+
+irq_hw_number_t virq_to_hw(unsigned int virq)
+{
+        return irq_map[virq].hwirq;
+}
+EXPORT_SYMBOL_GPL(virq_to_hw);
+
+bool virq_is_host(unsigned int virq, struct irq_host *host)
+{
+        return irq_map[virq].host == host;
+}
+EXPORT_SYMBOL_GPL(virq_is_host);
+
+static int default_irq_host_match(struct irq_host *h, struct device_node *np)
+{
+        return h->of_node != NULL && h->of_node == np;
+}
+
+struct irq_host *irq_alloc_host(struct device_node *of_node,
+                                unsigned int revmap_type,
+                                unsigned int revmap_arg,
+                                struct irq_host_ops *ops,
+                                irq_hw_number_t inval_irq)
+{
+        struct irq_host *host;
+        unsigned int size = sizeof(struct irq_host);
+        unsigned int i;
+        unsigned int *rmap;
+        unsigned long flags;
+
+        /* Allocate structure and revmap table if using linear mapping */
+        if (revmap_type == IRQ_HOST_MAP_LINEAR)
+                size += revmap_arg * sizeof(unsigned int);
+        host = kzalloc(size, GFP_KERNEL);
+        if (host == NULL)
+                return NULL;
+
+        /* Fill structure */
+        host->revmap_type = revmap_type;
+        host->inval_irq = inval_irq;
+        host->ops = ops;
+        host->of_node = of_node_get(of_node);
+
+        if (host->ops->match == NULL)
+                host->ops->match = default_irq_host_match;
+
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
+
+        /* Check for the priority controller. */
+        if (revmap_type == IRQ_HOST_MAP_PRIORITY) {
+                if (irq_map[0].host != NULL) {
+                        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
+                        of_node_put(host->of_node);
+                        kfree(host);
+                        return NULL;
+                }
+                irq_map[0].host = host;
+        }
+
+        list_add(&host->link, &irq_hosts);
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
+
+        /* Additional setups per revmap type */
+        switch (revmap_type) {
+        case IRQ_HOST_MAP_PRIORITY:
+                /* 0 is always the invalid number for priority */
+                host->inval_irq = 0;
+                /* setup us as the host for all priority interrupts */
+                for (i = 1; i < NR_PRIORITY_IRQS; i++) {
+                        irq_map[i].hwirq = i;
+                        smp_wmb();
+                        irq_map[i].host = host;
+                        smp_wmb();
+
+                        ops->map(host, i, i);
+                }
+                break;
+        case IRQ_HOST_MAP_LINEAR:
+                rmap = (unsigned int *)(host + 1);
+                for (i = 0; i < revmap_arg; i++)
+                        rmap[i] = NO_IRQ;
+                host->revmap_data.linear.size = revmap_arg;
+                smp_wmb();
+                host->revmap_data.linear.revmap = rmap;
+                break;
+        case IRQ_HOST_MAP_TREE:
+                INIT_RADIX_TREE(&host->revmap_data.tree, GFP_KERNEL);
+                break;
+        default:
+                break;
+        }
+
+        pr_debug("irq: Allocated host of type %d @0x%p\n", revmap_type, host);
+
+        return host;
+}
+
+struct irq_host *irq_find_host(struct device_node *node)
+{
+        struct irq_host *h, *found = NULL;
+        unsigned long flags;
+
+        /* We might want to match the legacy controller last since
+         * it might potentially be set to match all interrupts in
+         * the absence of a device node. This isn't a problem so far
+         * yet though...
+         */
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
+        list_for_each_entry(h, &irq_hosts, link)
+                if (h->ops->match(h, node)) {
+                        found = h;
+                        break;
+                }
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
+        return found;
+}
+EXPORT_SYMBOL_GPL(irq_find_host);
+
+void irq_set_default_host(struct irq_host *host)
+{
+        pr_debug("irq: Default host set to @0x%p\n", host);
+
+        irq_default_host = host;
+}
+
+void irq_set_virq_count(unsigned int count)
+{
+        pr_debug("irq: Trying to set virq count to %d\n", count);
+
+        BUG_ON(count < NR_PRIORITY_IRQS);
+        if (count < NR_IRQS)
+                irq_virq_count = count;
+}
+
+static int irq_setup_virq(struct irq_host *host, unsigned int virq,
+                            irq_hw_number_t hwirq)
+{
+        int res;
+
+        res = irq_alloc_desc_at(virq, 0);
+        if (res != virq) {
+                pr_debug("irq: -> allocating desc failed\n");
+                goto error;
+        }
+
+        /* map it */
+        smp_wmb();
+        irq_map[virq].hwirq = hwirq;
+        smp_mb();
+
+        if (host->ops->map(host, virq, hwirq)) {
+                pr_debug("irq: -> mapping failed, freeing\n");
+                goto errdesc;
+        }
+
+        irq_clear_status_flags(virq, IRQ_NOREQUEST);
+
+        return 0;
+
+errdesc:
+        irq_free_descs(virq, 1);
+error:
+        irq_free_virt(virq, 1);
+        return -1;
+}
+
+unsigned int irq_create_direct_mapping(struct irq_host *host)
+{
+        unsigned int virq;
+
+        if (host == NULL)
+                host = irq_default_host;
+
+        BUG_ON(host == NULL);
+        WARN_ON(host->revmap_type != IRQ_HOST_MAP_NOMAP);
+
+        virq = irq_alloc_virt(host, 1, 0);
+        if (virq == NO_IRQ) {
+                pr_debug("irq: create_direct virq allocation failed\n");
+                return NO_IRQ;
+        }
+
+        pr_debug("irq: create_direct obtained virq %d\n", virq);
+
+        if (irq_setup_virq(host, virq, virq))
+                return NO_IRQ;
+
+        return virq;
+}
+
+unsigned int irq_create_mapping(struct irq_host *host,
+                                irq_hw_number_t hwirq)
+{
+        unsigned int virq, hint;
+
+        pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", host, hwirq);
+
+        /* Look for default host if nececssary */
+        if (host == NULL)
+                host = irq_default_host;
+        if (host == NULL) {
+                printk(KERN_WARNING "irq_create_mapping called for"
+                       " NULL host, hwirq=%lx\n", hwirq);
+                WARN_ON(1);
+                return NO_IRQ;
+        }
+        pr_debug("irq: -> using host @%p\n", host);
+
+        /* Check if mapping already exists */
+        virq = irq_find_mapping(host, hwirq);
+        if (virq != NO_IRQ) {
+                pr_debug("irq: -> existing mapping on virq %d\n", virq);
+                return virq;
+        }
+
+        /* Allocate a virtual interrupt number */
+        hint = hwirq % irq_virq_count;
+        virq = irq_alloc_virt(host, 1, hint);
+        if (virq == NO_IRQ) {
+                pr_debug("irq: -> virq allocation failed\n");
+                return NO_IRQ;
+        }
+
+        if (irq_setup_virq(host, virq, hwirq))
+                return NO_IRQ;
+
+        pr_debug("irq: irq %lu on host %s mapped to virtual irq %u\n",
+                hwirq, host->of_node ? host->of_node->full_name : "null", virq);
+
+        return virq;
+}
+EXPORT_SYMBOL_GPL(irq_create_mapping);
+
+unsigned int irq_create_of_mapping(struct device_node *controller,
+                                   const u32 *intspec, unsigned int intsize)
+{
+        struct irq_host *host;
+        irq_hw_number_t hwirq;
+        unsigned int type = IRQ_TYPE_NONE;
+        unsigned int virq;
+
+        if (controller == NULL)
+                host = irq_default_host;
+        else
+                host = irq_find_host(controller);
+        if (host == NULL) {
+                printk(KERN_WARNING "irq: no irq host found for %s !\n",
+                       controller->full_name);
+                return NO_IRQ;
+        }
+
+        /* If host has no translation, then we assume interrupt line */
+        if (host->ops->xlate == NULL)
+                hwirq = intspec[0];
+        else {
+                if (host->ops->xlate(host, controller, intspec, intsize,
+                                     &hwirq, &type))
+                        return NO_IRQ;
+        }
+
+        /* Create mapping */
+        virq = irq_create_mapping(host, hwirq);
+        if (virq == NO_IRQ)
+                return virq;
+
+        /* Set type if specified and different than the current one */
+        if (type != IRQ_TYPE_NONE &&
+            type != (irqd_get_trigger_type(irq_get_irq_data(virq))))
+                irq_set_irq_type(virq, type);
+        return virq;
+}
+EXPORT_SYMBOL_GPL(irq_create_of_mapping);
+
+void irq_dispose_mapping(unsigned int virq)
+{
+        struct irq_host *host;
+        irq_hw_number_t hwirq;
+
+        if (virq == NO_IRQ)
+                return;
+
+        /* Never unmap priority interrupts */
+        if (virq < NR_PRIORITY_IRQS)
+                return;
+
+        host = irq_map[virq].host;
+        if (WARN_ON(host == NULL))
+                return;
+
+        irq_set_status_flags(virq, IRQ_NOREQUEST);
+
+        /* remove chip and handler */
+        irq_set_chip_and_handler(virq, NULL, NULL);
+
+        /* Make sure it's completed */
+        synchronize_irq(virq);
+
+        /* Tell the PIC about it */
+        if (host->ops->unmap)
+                host->ops->unmap(host, virq);
+        smp_mb();
+
+        /* Clear reverse map */
+        hwirq = irq_map[virq].hwirq;
+        switch (host->revmap_type) {
+        case IRQ_HOST_MAP_LINEAR:
+                if (hwirq < host->revmap_data.linear.size)
+                        host->revmap_data.linear.revmap[hwirq] = NO_IRQ;
+                break;
+        case IRQ_HOST_MAP_TREE:
+                mutex_lock(&revmap_trees_mutex);
+                radix_tree_delete(&host->revmap_data.tree, hwirq);
+                mutex_unlock(&revmap_trees_mutex);
+                break;
+        }
+
+        /* Destroy map */
+        smp_mb();
+        irq_map[virq].hwirq = host->inval_irq;
+
+        irq_free_descs(virq, 1);
+        /* Free it */
+        irq_free_virt(virq, 1);
+}
+EXPORT_SYMBOL_GPL(irq_dispose_mapping);
+
+unsigned int irq_find_mapping(struct irq_host *host,
+                              irq_hw_number_t hwirq)
+{
+        unsigned int i;
+        unsigned int hint = hwirq % irq_virq_count;
+
+        /* Look for default host if nececssary */
+        if (host == NULL)
+                host = irq_default_host;
+        if (host == NULL)
+                return NO_IRQ;
+
+        /* Slow path does a linear search of the map */
+        i = hint;
+        do  {
+                if (irq_map[i].host == host &&
+                    irq_map[i].hwirq == hwirq)
+                        return i;
+                i++;
+                if (i >= irq_virq_count)
+                        i = 4;
+        } while (i != hint);
+        return NO_IRQ;
+}
+EXPORT_SYMBOL_GPL(irq_find_mapping);
+
+unsigned int irq_radix_revmap_lookup(struct irq_host *host,
+                                     irq_hw_number_t hwirq)
+{
+        struct irq_map_entry *ptr;
+        unsigned int virq;
+
+        if (WARN_ON_ONCE(host->revmap_type != IRQ_HOST_MAP_TREE))
+                return irq_find_mapping(host, hwirq);
+
+        /*
+         * The ptr returned references the static global irq_map.
+         * but freeing an irq can delete nodes along the path to
+         * do the lookup via call_rcu.
+         */
+        rcu_read_lock();
+        ptr = radix_tree_lookup(&host->revmap_data.tree, hwirq);
+        rcu_read_unlock();
+
+        /*
+         * If found in radix tree, then fine.
+         * Else fallback to linear lookup - this should not happen in practice
+         * as it means that we failed to insert the node in the radix tree.
+         */
+        if (ptr)
+                virq = ptr - irq_map;
+        else
+                virq = irq_find_mapping(host, hwirq);
+
+        return virq;
+}
+
+void irq_radix_revmap_insert(struct irq_host *host, unsigned int virq,
+                             irq_hw_number_t hwirq)
+{
+        if (WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE))
+                return;
+
+        if (virq != NO_IRQ) {
+                mutex_lock(&revmap_trees_mutex);
+                radix_tree_insert(&host->revmap_data.tree, hwirq,
+                                  &irq_map[virq]);
+                mutex_unlock(&revmap_trees_mutex);
+        }
+}
+
+unsigned int irq_linear_revmap(struct irq_host *host,
+                               irq_hw_number_t hwirq)
+{
+        unsigned int *revmap;
+
+        if (WARN_ON_ONCE(host->revmap_type != IRQ_HOST_MAP_LINEAR))
+                return irq_find_mapping(host, hwirq);
+
+        /* Check revmap bounds */
+        if (unlikely(hwirq >= host->revmap_data.linear.size))
+                return irq_find_mapping(host, hwirq);
+
+        /* Check if revmap was allocated */
+        revmap = host->revmap_data.linear.revmap;
+        if (unlikely(revmap == NULL))
+                return irq_find_mapping(host, hwirq);
+
+        /* Fill up revmap with slow path if no mapping found */
+        if (unlikely(revmap[hwirq] == NO_IRQ))
+                revmap[hwirq] = irq_find_mapping(host, hwirq);
+
+        return revmap[hwirq];
+}
+
+unsigned int irq_alloc_virt(struct irq_host *host,
+                            unsigned int count,
+                            unsigned int hint)
+{
+        unsigned long flags;
+        unsigned int i, j, found = NO_IRQ;
+
+        if (count == 0 || count > (irq_virq_count - NR_PRIORITY_IRQS))
+                return NO_IRQ;
+
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
+
+        /* Use hint for 1 interrupt if any */
+        if (count == 1 && hint >= NR_PRIORITY_IRQS &&
+            hint < irq_virq_count && irq_map[hint].host == NULL) {
+                found = hint;
+                goto hint_found;
+        }
+
+        /* Look for count consecutive numbers in the allocatable
+         * (non-legacy) space
+         */
+        for (i = NR_PRIORITY_IRQS, j = 0; i < irq_virq_count; i++) {
+                if (irq_map[i].host != NULL)
+                        j = 0;
+                else
+                        j++;
+
+                if (j == count) {
+                        found = i - count + 1;
+                        break;
+                }
+        }
+        if (found == NO_IRQ) {
+                raw_spin_unlock_irqrestore(&irq_big_lock, flags);
+                return NO_IRQ;
+        }
+ hint_found:
+        for (i = found; i < (found + count); i++) {
+                irq_map[i].hwirq = host->inval_irq;
+                smp_wmb();
+                irq_map[i].host = host;
+        }
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
+        return found;
+}
+
+void irq_free_virt(unsigned int virq, unsigned int count)
+{
+        unsigned long flags;
+        unsigned int i;
+
+        WARN_ON(virq < NR_PRIORITY_IRQS);
+        WARN_ON(count == 0 || (virq + count) > irq_virq_count);
+
+        if (virq < NR_PRIORITY_IRQS) {
+                if (virq + count < NR_PRIORITY_IRQS)
+                        return;
+                count  -= NR_PRIORITY_IRQS - virq;
+                virq = NR_PRIORITY_IRQS;
+        }
+
+        if (count > irq_virq_count || virq > irq_virq_count - count) {
+                if (virq > irq_virq_count)
+                        return;
+                count = irq_virq_count - virq;
+        }
+
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
+        for (i = virq; i < (virq + count); i++) {
+                struct irq_host *host;
+
+                host = irq_map[i].host;
+                irq_map[i].hwirq = host->inval_irq;
+                smp_wmb();
+                irq_map[i].host = NULL;
+        }
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
+}
+
+#ifdef CONFIG_VIRQ_DEBUG
+static int virq_debug_show(struct seq_file *m, void *private)
+{
+        unsigned long flags;
+        struct irq_desc *desc;
+        const char *p;
+        static const char none[] = "none";
+        void *data;
+        int i;
+
+        seq_printf(m, "%-5s  %-7s  %-15s  %-18s  %s\n", "virq", "hwirq",
+                      "chip name", "chip data", "host name");
+
+        for (i = 1; i < nr_irqs; i++) {
+                desc = irq_to_desc(i);
+                if (!desc)
+                        continue;
+
+                raw_spin_lock_irqsave(&desc->lock, flags);
+
+                if (desc->action && desc->action->handler) {
+                        struct irq_chip *chip;
+
+                        seq_printf(m, "%5d  ", i);
+                        seq_printf(m, "0x%05lx  ", irq_map[i].hwirq);
+
+                        chip = irq_desc_get_chip(desc);
+                        if (chip && chip->name)
+                                p = chip->name;
+                        else
+                                p = none;
+                        seq_printf(m, "%-15s  ", p);
+
+                        data = irq_desc_get_chip_data(desc);
+                        seq_printf(m, "0x%16p  ", data);
+
+                        if (irq_map[i].host && irq_map[i].host->of_node)
+                                p = irq_map[i].host->of_node->full_name;
+                        else
+                                p = none;
+                        seq_printf(m, "%s\n", p);
+                }
+
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
+        }
+
+        return 0;
+}
+
+static int virq_debug_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, virq_debug_show, inode->i_private);
+}
+
+static const struct file_operations virq_debug_fops = {
+        .open = virq_debug_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int __init irq_debugfs_init(void)
+{
+        if (debugfs_create_file("virq_mapping", S_IRUGO, powerpc_debugfs_root,
+                                 NULL, &virq_debug_fops) == NULL)
+                return -ENOMEM;
+
+        return 0;
+}
+device_initcall(irq_debugfs_init);
+#endif /* CONFIG_VIRQ_DEBUG */
diff --git a/arch/c6x/kernel/module.c b/arch/c6x/kernel/module.c
new file mode 100644
index 00000000000..5fc03f18f56
--- /dev/null
+++ b/arch/c6x/kernel/module.c
@@ -0,0 +1,123 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2005, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Thomas Charleux (thomas.charleux@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <linux/moduleloader.h>
+#include <linux/elf.h>
+#include <linux/vmalloc.h>
+#include <linux/kernel.h>
+
+static inline int fixup_pcr(u32 *ip, Elf32_Addr dest, u32 maskbits, int shift)
+{
+        u32 opcode;
+        long ep = (long)ip & ~31;
+        long delta = ((long)dest - ep) >> 2;
+        long mask = (1 << maskbits) - 1;
+
+        if ((delta >> (maskbits - 1)) == 0 ||
+            (delta >> (maskbits - 1)) == -1) {
+                opcode = *ip;
+                opcode &= ~(mask << shift);
+                opcode |= ((delta & mask) << shift);
+                *ip = opcode;
+
+                pr_debug("REL PCR_S%d[%p] dest[%p] opcode[%08x]\n",
+                         maskbits, ip, (void *)dest, opcode);
+
+                return 0;
+        }
+        pr_err("PCR_S%d reloc %p -> %p out of range!\n",
+               maskbits, ip, (void *)dest);
+
+        return -1;
+}
+
+/*
+ * apply a RELA relocation
+ */
+int apply_relocate_add(Elf32_Shdr *sechdrs,
+                       const char *strtab,
+                       unsigned int symindex,
+                       unsigned int relsec,
+                       struct module *me)
+{
+        Elf32_Rela *rel = (void *) sechdrs[relsec].sh_addr;
+        Elf_Sym *sym;
+        u32 *location, opcode;
+        unsigned int i;
+        Elf32_Addr v;
+        Elf_Addr offset = 0;
+
+        pr_debug("Applying relocate section %u to %u with offset 0x%x\n",
+                 relsec, sechdrs[relsec].sh_info, offset);
+
+        for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
+                /* This is where to make the change */
+                location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+                        + rel[i].r_offset - offset;
+
+                /* This is the symbol it is referring to.  Note that all
+                   undefined symbols have been resolved.  */
+                sym = (Elf_Sym *)sechdrs[symindex].sh_addr
+                        + ELF32_R_SYM(rel[i].r_info);
+
+                /* this is the adjustment to be made */
+                v = sym->st_value + rel[i].r_addend;
+
+                switch (ELF32_R_TYPE(rel[i].r_info)) {
+                case R_C6000_ABS32:
+                        pr_debug("RELA ABS32: [%p] = 0x%x\n", location, v);
+                        *location = v;
+                        break;
+                case R_C6000_ABS16:
+                        pr_debug("RELA ABS16: [%p] = 0x%x\n", location, v);
+                        *(u16 *)location = v;
+                        break;
+                case R_C6000_ABS8:
+                        pr_debug("RELA ABS8: [%p] = 0x%x\n", location, v);
+                        *(u8 *)location = v;
+                        break;
+                case R_C6000_ABS_L16:
+                        opcode = *location;
+                        opcode &= ~0x7fff80;
+                        opcode |= ((v & 0xffff) << 7);
+                        pr_debug("RELA ABS_L16[%p] v[0x%x] opcode[0x%x]\n",
+                                 location, v, opcode);
+                        *location = opcode;
+                        break;
+                case R_C6000_ABS_H16:
+                        opcode = *location;
+                        opcode &= ~0x7fff80;
+                        opcode |= ((v >> 9) & 0x7fff80);
+                        pr_debug("RELA ABS_H16[%p] v[0x%x] opcode[0x%x]\n",
+                                 location, v, opcode);
+                        *location = opcode;
+                        break;
+                case R_C6000_PCR_S21:
+                        if (fixup_pcr(location, v, 21, 7))
+                                return -ENOEXEC;
+                        break;
+                case R_C6000_PCR_S12:
+                        if (fixup_pcr(location, v, 12, 16))
+                                return -ENOEXEC;
+                        break;
+                case R_C6000_PCR_S10:
+                        if (fixup_pcr(location, v, 10, 13))
+                                return -ENOEXEC;
+                        break;
+                default:
+                        pr_err("module %s: Unknown RELA relocation: %u\n",
+                               me->name, ELF32_R_TYPE(rel[i].r_info));
+                        return -ENOEXEC;
+                }
+        }
+
+        return 0;
+}
diff --git a/arch/c6x/kernel/process.c b/arch/c6x/kernel/process.c
new file mode 100644
index 00000000000..7ca8c41b03c
--- /dev/null
+++ b/arch/c6x/kernel/process.c
@@ -0,0 +1,265 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/init_task.h>
+#include <linux/tick.h>
+#include <linux/mqueue.h>
+#include <linux/syscalls.h>
+#include <linux/reboot.h>
+
+#include <asm/syscalls.h>
+
+/* hooks for board specific support */
+void    (*c6x_restart)(void);
+void    (*c6x_halt)(void);
+
+extern asmlinkage void ret_from_fork(void);
+
+static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
+static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
+
+/*
+ * Initial thread structure.
+ */
+union thread_union init_thread_union __init_task_data = {
+        INIT_THREAD_INFO(init_task)
+};
+
+/*
+ * Initial task structure.
+ */
+struct task_struct init_task = INIT_TASK(init_task);
+EXPORT_SYMBOL(init_task);
+
+/*
+ * power off function, if any
+ */
+void (*pm_power_off)(void);
+EXPORT_SYMBOL(pm_power_off);
+
+static void c6x_idle(void)
+{
+        unsigned long tmp;
+
+        /*
+         * Put local_irq_enable and idle in same execute packet
+         * to make them atomic and avoid race to idle with
+         * interrupts enabled.
+         */
+        asm volatile ("   mvc .s2 CSR,%0\n"
+                      "   or  .d2 1,%0,%0\n"
+                      "   mvc .s2 %0,CSR\n"
+                      "|| idle\n"
+                      : "=b"(tmp));
+}
+
+/*
+ * The idle loop for C64x
+ */
+void cpu_idle(void)
+{
+        /* endless idle loop with no priority at all */
+        while (1) {
+                tick_nohz_idle_enter();
+                rcu_idle_enter();
+                while (1) {
+                        local_irq_disable();
+                        if (need_resched()) {
+                                local_irq_enable();
+                                break;
+                        }
+                        c6x_idle(); /* enables local irqs */
+                }
+                rcu_idle_exit();
+                tick_nohz_idle_exit();
+
+                preempt_enable_no_resched();
+                schedule();
+                preempt_disable();
+        }
+}
+
+static void halt_loop(void)
+{
+        printk(KERN_EMERG "System Halted, OK to turn off power\n");
+        local_irq_disable();
+        while (1)
+                asm volatile("idle\n");
+}
+
+void machine_restart(char *__unused)
+{
+        if (c6x_restart)
+                c6x_restart();
+        halt_loop();
+}
+
+void machine_halt(void)
+{
+        if (c6x_halt)
+                c6x_halt();
+        halt_loop();
+}
+
+void machine_power_off(void)
+{
+        if (pm_power_off)
+                pm_power_off();
+        halt_loop();
+}
+
+static void kernel_thread_helper(int dummy, void *arg, int (*fn)(void *))
+{
+        do_exit(fn(arg));
+}
+
+/*
+ * Create a kernel thread
+ */
+int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
+{
+        struct pt_regs regs;
+
+        /*
+         * copy_thread sets a4 to zero (child return from fork)
+         * so we can't just set things up to directly return to
+         * fn.
+         */
+        memset(&regs, 0, sizeof(regs));
+        regs.b4 = (unsigned long) arg;
+        regs.a6 = (unsigned long) fn;
+        regs.pc = (unsigned long) kernel_thread_helper;
+        local_save_flags(regs.csr);
+        regs.csr |= 1;
+        regs.tsr = 5; /* Set GEE and GIE in TSR */
+
+        /* Ok, create the new process.. */
+        return do_fork(flags | CLONE_VM | CLONE_UNTRACED, -1, &regs,
+                       0, NULL, NULL);
+}
+EXPORT_SYMBOL(kernel_thread);
+
+void flush_thread(void)
+{
+}
+
+void exit_thread(void)
+{
+}
+
+SYSCALL_DEFINE1(c6x_clone, struct pt_regs *, regs)
+{
+        unsigned long clone_flags;
+        unsigned long newsp;
+
+        /* syscall puts clone_flags in A4 and usp in B4 */
+        clone_flags = regs->orig_a4;
+        if (regs->b4)
+                newsp = regs->b4;
+        else
+                newsp = regs->sp;
+
+        return do_fork(clone_flags, newsp, regs, 0, (int __user *)regs->a6,
+                       (int __user *)regs->b6);
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+void start_thread(struct pt_regs *regs, unsigned int pc, unsigned long usp)
+{
+        /*
+         * The binfmt loader will setup a "full" stack, but the C6X
+         * operates an "empty" stack. So we adjust the usp so that
+         * argc doesn't get destroyed if an interrupt is taken before
+         * it is read from the stack.
+         *
+         * NB: Library startup code needs to match this.
+         */
+        usp -= 8;
+
+        set_fs(USER_DS);
+        regs->pc  = pc;
+        regs->sp  = usp;
+        regs->tsr |= 0x40; /* set user mode */
+        current->thread.usp = usp;
+}
+
+/*
+ * Copy a new thread context in its stack.
+ */
+int copy_thread(unsigned long clone_flags, unsigned long usp,
+                unsigned long ustk_size,
+                struct task_struct *p, struct pt_regs *regs)
+{
+        struct pt_regs *childregs;
+
+        childregs = task_pt_regs(p);
+
+        *childregs = *regs;
+        childregs->a4 = 0;
+
+        if (usp == -1)
+                /* case of  __kernel_thread: we return to supervisor space */
+                childregs->sp = (unsigned long)(childregs + 1);
+        else
+                /* Otherwise use the given stack */
+                childregs->sp = usp;
+
+        /* Set usp/ksp */
+        p->thread.usp = childregs->sp;
+        /* switch_to uses stack to save/restore 14 callee-saved regs */
+        thread_saved_ksp(p) = (unsigned long)childregs - 8;
+        p->thread.pc = (unsigned int) ret_from_fork;
+        p->thread.wchan = (unsigned long) ret_from_fork;
+#ifdef __DSBT__
+        {
+                unsigned long dp;
+
+                asm volatile ("mv .S2 b14,%0\n" : "=b"(dp));
+
+                thread_saved_dp(p) = dp;
+                if (usp == -1)
+                        childregs->dp = dp;
+        }
+#endif
+        return 0;
+}
+
+/*
+ * c6x_execve() executes a new program.
+ */
+SYSCALL_DEFINE4(c6x_execve, const char __user *, name,
+                const char __user *const __user *, argv,
+                const char __user *const __user *, envp,
+                struct pt_regs *, regs)
+{
+        int error;
+        char *filename;
+
+        filename = getname(name);
+        error = PTR_ERR(filename);
+        if (IS_ERR(filename))
+                goto out;
+
+        error = do_execve(filename, argv, envp, regs);
+        putname(filename);
+out:
+        return error;
+}
+
+unsigned long get_wchan(struct task_struct *p)
+{
+        return p->thread.wchan;
+}
diff --git a/arch/c6x/kernel/ptrace.c b/arch/c6x/kernel/ptrace.c
new file mode 100644
index 00000000000..3c494e84444
--- /dev/null
+++ b/arch/c6x/kernel/ptrace.c
@@ -0,0 +1,187 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Updated for 2.6.34: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/ptrace.h>
+#include <linux/tracehook.h>
+#include <linux/regset.h>
+#include <linux/elf.h>
+
+#include <asm/cacheflush.h>
+
+#define PT_REG_SIZE       (sizeof(struct pt_regs))
+
+/*
+ * Called by kernel/ptrace.c when detaching.
+ */
+void ptrace_disable(struct task_struct *child)
+{
+        /* nothing to do */
+}
+
+/*
+ * Get a register number from live pt_regs for the specified task.
+ */
+static inline long get_reg(struct task_struct *task, int regno)
+{
+        long *addr = (long *)task_pt_regs(task);
+
+        if (regno == PT_TSR || regno == PT_CSR)
+                return 0;
+
+        return addr[regno];
+}
+
+/*
+ * Write contents of register REGNO in task TASK.
+ */
+static inline int put_reg(struct task_struct *task,
+                          int regno,
+                          unsigned long data)
+{
+        unsigned long *addr = (unsigned long *)task_pt_regs(task);
+
+        if (regno != PT_TSR && regno != PT_CSR)
+                addr[regno] = data;
+
+        return 0;
+}
+
+/* regset get/set implementations */
+
+static int gpr_get(struct task_struct *target,
+                   const struct user_regset *regset,
+                   unsigned int pos, unsigned int count,
+                   void *kbuf, void __user *ubuf)
+{
+        struct pt_regs *regs = task_pt_regs(target);
+
+        return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                   regs,
+                                   0, sizeof(*regs));
+}
+
+static int gpr_set(struct task_struct *target,
+                   const struct user_regset *regset,
+                   unsigned int pos, unsigned int count,
+                   const void *kbuf, const void __user *ubuf)
+{
+        int ret;
+        struct pt_regs *regs = task_pt_regs(target);
+
+        /* Don't copyin TSR or CSR */
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                 &regs,
+                                 0, PT_TSR * sizeof(long));
+        if (ret)
+                return ret;
+
+        ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+                                        PT_TSR * sizeof(long),
+                                        (PT_TSR + 1) * sizeof(long));
+        if (ret)
+                return ret;
+
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                 &regs,
+                                 (PT_TSR + 1) * sizeof(long),
+                                 PT_CSR * sizeof(long));
+        if (ret)
+                return ret;
+
+        ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+                                        PT_CSR * sizeof(long),
+                                        (PT_CSR + 1) * sizeof(long));
+        if (ret)
+                return ret;
+
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                 &regs,
+                                 (PT_CSR + 1) * sizeof(long), -1);
+        return ret;
+}
+
+enum c6x_regset {
+        REGSET_GPR,
+};
+
+static const struct user_regset c6x_regsets[] = {
+        [REGSET_GPR] = {
+                .core_note_type = NT_PRSTATUS,
+                .n = ELF_NGREG,
+                .size = sizeof(u32),
+                .align = sizeof(u32),
+                .get = gpr_get,
+                .set = gpr_set
+        },
+};
+
+static const struct user_regset_view user_c6x_native_view = {
+        .name           = "tic6x",
+        .e_machine      = EM_TI_C6000,
+        .regsets        = c6x_regsets,
+        .n              = ARRAY_SIZE(c6x_regsets),
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+        return &user_c6x_native_view;
+}
+
+/*
+ * Perform ptrace request
+ */
+long arch_ptrace(struct task_struct *child, long request,
+                 unsigned long addr, unsigned long data)
+{
+        int ret = 0;
+
+        switch (request) {
+                /*
+                 * write the word at location addr.
+                 */
+        case PTRACE_POKETEXT:
+                ret = generic_ptrace_pokedata(child, addr, data);
+                if (ret == 0 && request == PTRACE_POKETEXT)
+                        flush_icache_range(addr, addr + 4);
+                break;
+        default:
+                ret = ptrace_request(child, request, addr, data);
+                break;
+        }
+
+        return ret;
+}
+
+/*
+ * handle tracing of system call entry
+ * - return the revised system call number or ULONG_MAX to cause ENOSYS
+ */
+asmlinkage unsigned long syscall_trace_entry(struct pt_regs *regs)
+{
+        if (tracehook_report_syscall_entry(regs))
+                /* tracing decided this syscall should not happen, so
+                 * We'll return a bogus call number to get an ENOSYS
+                 * error, but leave the original number in
+                 * regs->orig_a4
+                 */
+                return ULONG_MAX;
+
+        return regs->b0;
+}
+
+/*
+ * handle tracing of system call exit
+ */
+asmlinkage void syscall_trace_exit(struct pt_regs *regs)
+{
+        tracehook_report_syscall_exit(regs, 0);
+}
diff --git a/arch/c6x/kernel/setup.c b/arch/c6x/kernel/setup.c
new file mode 100644
index 00000000000..0c07921747f
--- /dev/null
+++ b/arch/c6x/kernel/setup.c
@@ -0,0 +1,510 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/dma-mapping.h>
+#include <linux/memblock.h>
+#include <linux/seq_file.h>
+#include <linux/bootmem.h>
+#include <linux/clkdev.h>
+#include <linux/initrd.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_fdt.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/cache.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/fs.h>
+#include <linux/of.h>
+
+
+#include <asm/sections.h>
+#include <asm/div64.h>
+#include <asm/setup.h>
+#include <asm/dscr.h>
+#include <asm/clock.h>
+#include <asm/soc.h>
+
+static const char *c6x_soc_name;
+
+int c6x_num_cores;
+EXPORT_SYMBOL_GPL(c6x_num_cores);
+
+unsigned int c6x_silicon_rev;
+EXPORT_SYMBOL_GPL(c6x_silicon_rev);
+
+/*
+ * Device status register. This holds information
+ * about device configuration needed by some drivers.
+ */
+unsigned int c6x_devstat;
+EXPORT_SYMBOL_GPL(c6x_devstat);
+
+/*
+ * Some SoCs have fuse registers holding a unique MAC
+ * address. This is parsed out of the device tree with
+ * the resulting MAC being held here.
+ */
+unsigned char c6x_fuse_mac[6];
+
+unsigned long memory_start;
+unsigned long memory_end;
+
+unsigned long ram_start;
+unsigned long ram_end;
+
+/* Uncached memory for DMA consistent use (memdma=) */
+static unsigned long dma_start __initdata;
+static unsigned long dma_size __initdata;
+
+char c6x_command_line[COMMAND_LINE_SIZE];
+
+#if defined(CONFIG_CMDLINE_BOOL)
+static const char default_command_line[COMMAND_LINE_SIZE] __section(.cmdline) =
+        CONFIG_CMDLINE;
+#endif
+
+struct cpuinfo_c6x {
+        const char *cpu_name;
+        const char *cpu_voltage;
+        const char *mmu;
+        const char *fpu;
+        char *cpu_rev;
+        unsigned int core_id;
+        char __cpu_rev[5];
+};
+
+static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
+
+unsigned int ticks_per_ns_scaled;
+EXPORT_SYMBOL(ticks_per_ns_scaled);
+
+unsigned int c6x_core_freq;
+
+static void __init get_cpuinfo(void)
+{
+        unsigned cpu_id, rev_id, csr;
+        struct clk *coreclk = clk_get_sys(NULL, "core");
+        unsigned long core_khz;
+        u64 tmp;
+        struct cpuinfo_c6x *p;
+        struct device_node *node, *np;
+
+        p = &per_cpu(cpu_data, smp_processor_id());
+
+        if (!IS_ERR(coreclk))
+                c6x_core_freq = clk_get_rate(coreclk);
+        else {
+                printk(KERN_WARNING
+                       "Cannot find core clock frequency. Using 700MHz\n");
+                c6x_core_freq = 700000000;
+        }
+
+        core_khz = c6x_core_freq / 1000;
+
+        tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
+        do_div(tmp, 1000000);
+        ticks_per_ns_scaled = tmp;
+
+        csr = get_creg(CSR);
+        cpu_id = csr >> 24;
+        rev_id = (csr >> 16) & 0xff;
+
+        p->mmu = "none";
+        p->fpu = "none";
+        p->cpu_voltage = "unknown";
+
+        switch (cpu_id) {
+        case 0:
+                p->cpu_name = "C67x";
+                p->fpu = "yes";
+                break;
+        case 2:
+                p->cpu_name = "C62x";
+                break;
+        case 8:
+                p->cpu_name = "C64x";
+                break;
+        case 12:
+                p->cpu_name = "C64x";
+                break;
+        case 16:
+                p->cpu_name = "C64x+";
+                p->cpu_voltage = "1.2";
+                break;
+        default:
+                p->cpu_name = "unknown";
+                break;
+        }
+
+        if (cpu_id < 16) {
+                switch (rev_id) {
+                case 0x1:
+                        if (cpu_id > 8) {
+                                p->cpu_rev = "DM640/DM641/DM642/DM643";
+                                p->cpu_voltage = "1.2 - 1.4";
+                        } else {
+                                p->cpu_rev = "C6201";
+                                p->cpu_voltage = "2.5";
+                        }
+                        break;
+                case 0x2:
+                        p->cpu_rev = "C6201B/C6202/C6211";
+                        p->cpu_voltage = "1.8";
+                        break;
+                case 0x3:
+                        p->cpu_rev = "C6202B/C6203/C6204/C6205";
+                        p->cpu_voltage = "1.5";
+                        break;
+                case 0x201:
+                        p->cpu_rev = "C6701 revision 0 (early CPU)";
+                        p->cpu_voltage = "1.8";
+                        break;
+                case 0x202:
+                        p->cpu_rev = "C6701/C6711/C6712";
+                        p->cpu_voltage = "1.8";
+                        break;
+                case 0x801:
+                        p->cpu_rev = "C64x";
+                        p->cpu_voltage = "1.5";
+                        break;
+                default:
+                        p->cpu_rev = "unknown";
+                }
+        } else {
+                p->cpu_rev = p->__cpu_rev;
+                snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
+        }
+
+        p->core_id = get_coreid();
+
+        node = of_find_node_by_name(NULL, "cpus");
+        if (node) {
+                for_each_child_of_node(node, np)
+                        if (!strcmp("cpu", np->name))
+                                ++c6x_num_cores;
+                of_node_put(node);
+        }
+
+        node = of_find_node_by_name(NULL, "soc");
+        if (node) {
+                if (of_property_read_string(node, "model", &c6x_soc_name))
+                        c6x_soc_name = "unknown";
+                of_node_put(node);
+        } else
+                c6x_soc_name = "unknown";
+
+        printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
+               p->core_id, p->cpu_name, p->cpu_rev,
+               p->cpu_voltage, c6x_core_freq / 1000000);
+}
+
+/*
+ * Early parsing of the command line
+ */
+static u32 mem_size __initdata;
+
+/* "mem=" parsing. */
+static int __init early_mem(char *p)
+{
+        if (!p)
+                return -EINVAL;
+
+        mem_size = memparse(p, &p);
+        /* don't remove all of memory when handling "mem={invalid}" */
+        if (mem_size == 0)
+                return -EINVAL;
+
+        return 0;
+}
+early_param("mem", early_mem);
+
+/* "memdma=<size>[@<address>]" parsing. */
+static int __init early_memdma(char *p)
+{
+        if (!p)
+                return -EINVAL;
+
+        dma_size = memparse(p, &p);
+        if (*p == '@')
+                dma_start = memparse(p, &p);
+
+        return 0;
+}
+early_param("memdma", early_memdma);
+
+int __init c6x_add_memory(phys_addr_t start, unsigned long size)
+{
+        static int ram_found __initdata;
+
+        /* We only handle one bank (the one with PAGE_OFFSET) for now */
+        if (ram_found)
+                return -EINVAL;
+
+        if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
+                return 0;
+
+        ram_start = start;
+        ram_end = start + size;
+
+        ram_found = 1;
+        return 0;
+}
+
+/*
+ * Do early machine setup and device tree parsing. This is called very
+ * early on the boot process.
+ */
+notrace void __init machine_init(unsigned long dt_ptr)
+{
+        struct boot_param_header *dtb = __va(dt_ptr);
+        struct boot_param_header *fdt = (struct boot_param_header *)_fdt_start;
+
+        /* interrupts must be masked */
+        set_creg(IER, 2);
+
+        /*
+         * Set the Interrupt Service Table (IST) to the beginning of the
+         * vector table.
+         */
+        set_ist(_vectors_start);
+
+        lockdep_init();
+
+        /*
+         * dtb is passed in from bootloader.
+         * fdt is linked in blob.
+         */
+        if (dtb && dtb != fdt)
+                fdt = dtb;
+
+        /* Do some early initialization based on the flat device tree */
+        early_init_devtree(fdt);
+
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, c6x_command_line, COMMAND_LINE_SIZE);
+        parse_early_param();
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+        int bootmap_size;
+        struct memblock_region *reg;
+
+        printk(KERN_INFO "Initializing kernel\n");
+
+        /* Initialize command line */
+        *cmdline_p = c6x_command_line;
+
+        memory_end = ram_end;
+        memory_end &= ~(PAGE_SIZE - 1);
+
+        if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
+                memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
+
+        /* add block that this kernel can use */
+        memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
+
+        /* reserve kernel text/data/bss */
+        memblock_reserve(PAGE_OFFSET,
+                         PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
+
+        if (dma_size) {
+                /* align to cacheability granularity */
+                dma_size = CACHE_REGION_END(dma_size);
+
+                if (!dma_start)
+                        dma_start = memory_end - dma_size;
+
+                /* align to cacheability granularity */
+                dma_start = CACHE_REGION_START(dma_start);
+
+                /* reserve DMA memory taken from kernel memory */
+                if (memblock_is_region_memory(dma_start, dma_size))
+                        memblock_reserve(dma_start, dma_size);
+        }
+
+        memory_start = PAGE_ALIGN((unsigned int) &_end);
+
+        printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
+               memory_start, memory_end);
+
+#ifdef CONFIG_BLK_DEV_INITRD
+        /*
+         * Reserve initrd memory if in kernel memory.
+         */
+        if (initrd_start < initrd_end)
+                if (memblock_is_region_memory(initrd_start,
+                                              initrd_end - initrd_start))
+                        memblock_reserve(initrd_start,
+                                         initrd_end - initrd_start);
+#endif
+
+        init_mm.start_code = (unsigned long) &_stext;
+        init_mm.end_code   = (unsigned long) &_etext;
+        init_mm.end_data   = memory_start;
+        init_mm.brk        = memory_start;
+
+        /*
+         * Give all the memory to the bootmap allocator,  tell it to put the
+         * boot mem_map at the start of memory
+         */
+        bootmap_size = init_bootmem_node(NODE_DATA(0),
+                                         memory_start >> PAGE_SHIFT,
+                                         PAGE_OFFSET >> PAGE_SHIFT,
+                                         memory_end >> PAGE_SHIFT);
+        memblock_reserve(memory_start, bootmap_size);
+
+        unflatten_device_tree();
+
+        c6x_cache_init();
+
+        /* Set the whole external memory as non-cacheable */
+        disable_caching(ram_start, ram_end - 1);
+
+        /* Set caching of external RAM used by Linux */
+        for_each_memblock(memory, reg)
+                enable_caching(CACHE_REGION_START(reg->base),
+                               CACHE_REGION_START(reg->base + reg->size - 1));
+
+#ifdef CONFIG_BLK_DEV_INITRD
+        /*
+         * Enable caching for initrd which falls outside kernel memory.
+         */
+        if (initrd_start < initrd_end) {
+                if (!memblock_is_region_memory(initrd_start,
+                                               initrd_end - initrd_start))
+                        enable_caching(CACHE_REGION_START(initrd_start),
+                                       CACHE_REGION_START(initrd_end - 1));
+        }
+#endif
+
+        /*
+         * Disable caching for dma coherent memory taken from kernel memory.
+         */
+        if (dma_size && memblock_is_region_memory(dma_start, dma_size))
+                disable_caching(dma_start,
+                                CACHE_REGION_START(dma_start + dma_size - 1));
+
+        /* Initialize the coherent memory allocator */
+        coherent_mem_init(dma_start, dma_size);
+
+        /*
+         * Free all memory as a starting point.
+         */
+        free_bootmem(PAGE_OFFSET, memory_end - PAGE_OFFSET);
+
+        /*
+         * Then reserve memory which is already being used.
+         */
+        for_each_memblock(reserved, reg) {
+                pr_debug("reserved - 0x%08x-0x%08x\n",
+                         (u32) reg->base, (u32) reg->size);
+                reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+        }
+
+        max_low_pfn = PFN_DOWN(memory_end);
+        min_low_pfn = PFN_UP(memory_start);
+        max_mapnr = max_low_pfn - min_low_pfn;
+
+        /* Get kmalloc into gear */
+        paging_init();
+
+        /*
+         * Probe for Device State Configuration Registers.
+         * We have to do this early in case timer needs to be enabled
+         * through DSCR.
+         */
+        dscr_probe();
+
+        /* We do this early for timer and core clock frequency */
+        c64x_setup_clocks();
+
+        /* Get CPU info */
+        get_cpuinfo();
+
+#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
+        conswitchp = &dummy_con;
+#endif
+}
+
+#define cpu_to_ptr(n) ((void *)((long)(n)+1))
+#define ptr_to_cpu(p) ((long)(p) - 1)
+
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+        int n = ptr_to_cpu(v);
+        struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
+
+        if (n == 0) {
+                seq_printf(m,
+                           "soc\t\t: %s\n"
+                           "soc revision\t: 0x%x\n"
+                           "soc cores\t: %d\n",
+                           c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
+        }
+
+        seq_printf(m,
+                   "\n"
+                   "processor\t: %d\n"
+                   "cpu\t\t: %s\n"
+                   "core revision\t: %s\n"
+                   "core voltage\t: %s\n"
+                   "core id\t\t: %d\n"
+                   "mmu\t\t: %s\n"
+                   "fpu\t\t: %s\n"
+                   "cpu MHz\t\t: %u\n"
+                   "bogomips\t: %lu.%02lu\n\n",
+                   n,
+                   p->cpu_name, p->cpu_rev, p->cpu_voltage,
+                   p->core_id, p->mmu, p->fpu,
+                   (c6x_core_freq + 500000) / 1000000,
+                   (loops_per_jiffy/(500000/HZ)),
+                   (loops_per_jiffy/(5000/HZ))%100);
+
+        return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+        return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
+}
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+        ++*pos;
+        return NULL;
+}
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+const struct seq_operations cpuinfo_op = {
+        c_start,
+        c_stop,
+        c_next,
+        show_cpuinfo
+};
+
+static struct cpu cpu_devices[NR_CPUS];
+
+static int __init topology_init(void)
+{
+        int i;
+
+        for_each_present_cpu(i)
+                register_cpu(&cpu_devices[i], i);
+
+        return 0;
+}
+
+subsys_initcall(topology_init);
diff --git a/arch/c6x/kernel/signal.c b/arch/c6x/kernel/signal.c
new file mode 100644
index 00000000000..304f675826e
--- /dev/null
+++ b/arch/c6x/kernel/signal.c
@@ -0,0 +1,377 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  Updated for 2.6.34: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/uaccess.h>
+#include <linux/syscalls.h>
+#include <linux/tracehook.h>
+
+#include <asm/ucontext.h>
+#include <asm/cacheflush.h>
+
+
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+/*
+ * Do a signal return, undo the signal stack.
+ */
+
+#define RETCODE_SIZE (9 << 2)   /* 9 instructions = 36 bytes */
+
+struct rt_sigframe {
+        struct siginfo __user *pinfo;
+        void __user *puc;
+        struct siginfo info;
+        struct ucontext uc;
+        unsigned long retcode[RETCODE_SIZE >> 2];
+};
+
+static int restore_sigcontext(struct pt_regs *regs,
+                              struct sigcontext __user *sc)
+{
+        int err = 0;
+
+        /* The access_ok check was done by caller, so use __get_user here */
+#define COPY(x)  (err |= __get_user(regs->x, &sc->sc_##x))
+
+        COPY(sp); COPY(a4); COPY(b4); COPY(a6); COPY(b6); COPY(a8); COPY(b8);
+        COPY(a0); COPY(a1); COPY(a2); COPY(a3); COPY(a5); COPY(a7); COPY(a9);
+        COPY(b0); COPY(b1); COPY(b2); COPY(b3); COPY(b5); COPY(b7); COPY(b9);
+
+        COPY(a16); COPY(a17); COPY(a18); COPY(a19);
+        COPY(a20); COPY(a21); COPY(a22); COPY(a23);
+        COPY(a24); COPY(a25); COPY(a26); COPY(a27);
+        COPY(a28); COPY(a29); COPY(a30); COPY(a31);
+        COPY(b16); COPY(b17); COPY(b18); COPY(b19);
+        COPY(b20); COPY(b21); COPY(b22); COPY(b23);
+        COPY(b24); COPY(b25); COPY(b26); COPY(b27);
+        COPY(b28); COPY(b29); COPY(b30); COPY(b31);
+
+        COPY(csr); COPY(pc);
+
+#undef COPY
+
+        return err;
+}
+
+asmlinkage int do_rt_sigreturn(struct pt_regs *regs)
+{
+        struct rt_sigframe __user *frame;
+        sigset_t set;
+
+        /*
+         * Since we stacked the signal on a dword boundary,
+         * 'sp' should be dword aligned here.  If it's
+         * not, then the user is trying to mess with us.
+         */
+        if (regs->sp & 7)
+                goto badframe;
+
+        frame = (struct rt_sigframe __user *) ((unsigned long) regs->sp + 8);
+
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+                goto badframe;
+
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        spin_lock_irq(&current->sighand->siglock);
+        current->blocked = set;
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+
+        if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
+                goto badframe;
+
+        return regs->a4;
+
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+
+static int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
+                            unsigned long mask)
+{
+        int err = 0;
+
+        err |= __put_user(mask, &sc->sc_mask);
+
+        /* The access_ok check was done by caller, so use __put_user here */
+#define COPY(x) (err |= __put_user(regs->x, &sc->sc_##x))
+
+        COPY(sp); COPY(a4); COPY(b4); COPY(a6); COPY(b6); COPY(a8); COPY(b8);
+        COPY(a0); COPY(a1); COPY(a2); COPY(a3); COPY(a5); COPY(a7); COPY(a9);
+        COPY(b0); COPY(b1); COPY(b2); COPY(b3); COPY(b5); COPY(b7); COPY(b9);
+
+        COPY(a16); COPY(a17); COPY(a18); COPY(a19);
+        COPY(a20); COPY(a21); COPY(a22); COPY(a23);
+        COPY(a24); COPY(a25); COPY(a26); COPY(a27);
+        COPY(a28); COPY(a29); COPY(a30); COPY(a31);
+        COPY(b16); COPY(b17); COPY(b18); COPY(b19);
+        COPY(b20); COPY(b21); COPY(b22); COPY(b23);
+        COPY(b24); COPY(b25); COPY(b26); COPY(b27);
+        COPY(b28); COPY(b29); COPY(b30); COPY(b31);
+
+        COPY(csr); COPY(pc);
+
+#undef COPY
+
+        return err;
+}
+
+static inline void __user *get_sigframe(struct k_sigaction *ka,
+                                        struct pt_regs *regs,
+                                        unsigned long framesize)
+{
+        unsigned long sp = regs->sp;
+
+        /*
+         * This is the X/Open sanctioned signal stack switching.
+         */
+        if ((ka->sa.sa_flags & SA_ONSTACK) && sas_ss_flags(sp) == 0)
+                sp = current->sas_ss_sp + current->sas_ss_size;
+
+        /*
+         * No matter what happens, 'sp' must be dword
+         * aligned. Otherwise, nasty things will happen
+         */
+        return (void __user *)((sp - framesize) & ~7);
+}
+
+static int setup_rt_frame(int signr, struct k_sigaction *ka, siginfo_t *info,
+                           sigset_t *set, struct pt_regs *regs)
+{
+        struct rt_sigframe __user *frame;
+        unsigned long __user *retcode;
+        int err = 0;
+
+        frame = get_sigframe(ka, regs, sizeof(*frame));
+
+        if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+                goto segv_and_exit;
+
+        err |= __put_user(&frame->info, &frame->pinfo);
+        err |= __put_user(&frame->uc, &frame->puc);
+        err |= copy_siginfo_to_user(&frame->info, info);
+
+        /* Clear all the bits of the ucontext we don't use.  */
+        err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
+
+        err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
+        err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
+
+        /* Set up to return from userspace */
+        retcode = (unsigned long __user *) &frame->retcode;
+
+        /* The access_ok check was done above, so use __put_user here */
+#define COPY(x) (err |= __put_user(x, retcode++))
+
+        COPY(0x0000002AUL | (__NR_rt_sigreturn << 7));
+                                /* MVK __NR_rt_sigreturn,B0 */
+        COPY(0x10000000UL);     /* SWE */
+        COPY(0x00006000UL);     /* NOP 4 */
+        COPY(0x00006000UL);     /* NOP 4 */
+        COPY(0x00006000UL);     /* NOP 4 */
+        COPY(0x00006000UL);     /* NOP 4 */
+        COPY(0x00006000UL);     /* NOP 4 */
+        COPY(0x00006000UL);     /* NOP 4 */
+        COPY(0x00006000UL);     /* NOP 4 */
+
+#undef COPY
+
+        if (err)
+                goto segv_and_exit;
+
+        flush_icache_range((unsigned long) &frame->retcode,
+                           (unsigned long) &frame->retcode + RETCODE_SIZE);
+
+        retcode = (unsigned long __user *) &frame->retcode;
+
+        /* Change user context to branch to signal handler */
+        regs->sp = (unsigned long) frame - 8;
+        regs->b3 = (unsigned long) retcode;
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+
+        /* Give the signal number to the handler */
+        regs->a4 = signr;
+
+        /*
+         * For realtime signals we must also set the second and third
+         * arguments for the signal handler.
+         *   -- Peter Maydell <pmaydell@chiark.greenend.org.uk> 2000-12-06
+         */
+        regs->b4 = (unsigned long)&frame->info;
+        regs->a6 = (unsigned long)&frame->uc;
+
+        return 0;
+
+segv_and_exit:
+        force_sigsegv(signr, current);
+        return -EFAULT;
+}
+
+static inline void
+handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
+{
+        switch (regs->a4) {
+        case -ERESTARTNOHAND:
+                if (!has_handler)
+                        goto do_restart;
+                regs->a4 = -EINTR;
+                break;
+
+        case -ERESTARTSYS:
+                if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
+                        regs->a4 = -EINTR;
+                        break;
+                }
+        /* fallthrough */
+        case -ERESTARTNOINTR:
+do_restart:
+                regs->a4 = regs->orig_a4;
+                regs->pc -= 4;
+                break;
+        }
+}
+
+/*
+ * handle the actual delivery of a signal to userspace
+ */
+static int handle_signal(int sig,
+                         siginfo_t *info, struct k_sigaction *ka,
+                         sigset_t *oldset, struct pt_regs *regs,
+                         int syscall)
+{
+        int ret;
+
+        /* Are we from a system call? */
+        if (syscall) {
+                /* If so, check system call restarting.. */
+                switch (regs->a4) {
+                case -ERESTART_RESTARTBLOCK:
+                case -ERESTARTNOHAND:
+                        regs->a4 = -EINTR;
+                        break;
+
+                case -ERESTARTSYS:
+                        if (!(ka->sa.sa_flags & SA_RESTART)) {
+                                regs->a4 = -EINTR;
+                                break;
+                        }
+
+                        /* fallthrough */
+                case -ERESTARTNOINTR:
+                        regs->a4 = regs->orig_a4;
+                        regs->pc -= 4;
+                }
+        }
+
+        /* Set up the stack frame */
+        ret = setup_rt_frame(sig, ka, info, oldset, regs);
+        if (ret == 0) {
+                spin_lock_irq(&current->sighand->siglock);
+                sigorsets(&current->blocked, &current->blocked,
+                          &ka->sa.sa_mask);
+                if (!(ka->sa.sa_flags & SA_NODEFER))
+                        sigaddset(&current->blocked, sig);
+                recalc_sigpending();
+                spin_unlock_irq(&current->sighand->siglock);
+        }
+
+        return ret;
+}
+
+/*
+ * handle a potential signal
+ */
+static void do_signal(struct pt_regs *regs, int syscall)
+{
+        struct k_sigaction ka;
+        siginfo_t info;
+        sigset_t *oldset;
+        int signr;
+
+        /* we want the common case to go fast, which is why we may in certain
+         * cases get here from kernel mode */
+        if (!user_mode(regs))
+                return;
+
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
+                oldset = &current->blocked;
+
+        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+        if (signr > 0) {
+                if (handle_signal(signr, &info, &ka, oldset,
+                                  regs, syscall) == 0) {
+                        /* a signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag */
+                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                                clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+                        tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                }
+
+                return;
+        }
+
+        /* did we come from a system call? */
+        if (syscall) {
+                /* restart the system call - no handlers present */
+                switch (regs->a4) {
+                case -ERESTARTNOHAND:
+                case -ERESTARTSYS:
+                case -ERESTARTNOINTR:
+                        regs->a4 = regs->orig_a4;
+                        regs->pc -= 4;
+                        break;
+
+                case -ERESTART_RESTARTBLOCK:
+                        regs->a4 = regs->orig_a4;
+                        regs->b0 = __NR_restart_syscall;
+                        regs->pc -= 4;
+                        break;
+                }
+        }
+
+        /* if there's no signal to deliver, we just put the saved sigmask
+         * back */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
+}
+
+/*
+ * notification of userspace execution resumption
+ * - triggered by current->work.notify_resume
+ */
+asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags,
+                                 int syscall)
+{
+        /* deal with pending signal delivery */
+        if (thread_info_flags & ((1 << TIF_SIGPENDING) |
+                                 (1 << TIF_RESTORE_SIGMASK)))
+                do_signal(regs, syscall);
+
+        if (thread_info_flags & (1 << TIF_NOTIFY_RESUME)) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
+}
diff --git a/arch/c6x/kernel/soc.c b/arch/c6x/kernel/soc.c
new file mode 100644
index 00000000000..dd45bc39af0
--- /dev/null
+++ b/arch/c6x/kernel/soc.c
@@ -0,0 +1,91 @@
+/*
+ *  Miscellaneous SoC-specific hooks.
+ *
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/ctype.h>
+#include <linux/etherdevice.h>
+#include <asm/system.h>
+#include <asm/setup.h>
+#include <asm/soc.h>
+
+struct soc_ops soc_ops;
+
+int soc_get_exception(void)
+{
+        if (!soc_ops.get_exception)
+                return -1;
+        return soc_ops.get_exception();
+}
+
+void soc_assert_event(unsigned int evt)
+{
+        if (soc_ops.assert_event)
+                soc_ops.assert_event(evt);
+}
+
+static u8 cmdline_mac[6];
+
+static int __init get_mac_addr_from_cmdline(char *str)
+{
+        int count, i, val;
+
+        for (count = 0; count < 6 && *str; count++, str += 3) {
+                if (!isxdigit(str[0]) || !isxdigit(str[1]))
+                        return 0;
+                if (str[2] != ((count < 5) ? ':' : '\0'))
+                        return 0;
+
+                for (i = 0, val = 0; i < 2; i++) {
+                        val = val << 4;
+                        val |= isdigit(str[i]) ?
+                                str[i] - '0' : toupper(str[i]) - 'A' + 10;
+                }
+                cmdline_mac[count] = val;
+        }
+        return 1;
+}
+__setup("emac_addr=", get_mac_addr_from_cmdline);
+
+/*
+ * Setup the MAC address for SoC ethernet devices.
+ *
+ * Before calling this function, the ethernet driver will have
+ * initialized the addr with local-mac-address from the device
+ * tree (if found). Allow command line to override, but not
+ * the fused address.
+ */
+int soc_mac_addr(unsigned int index, u8 *addr)
+{
+        int i, have_dt_mac = 0, have_cmdline_mac = 0, have_fuse_mac = 0;
+
+        for (i = 0; i < 6; i++) {
+                if (cmdline_mac[i])
+                        have_cmdline_mac = 1;
+                if (c6x_fuse_mac[i])
+                        have_fuse_mac = 1;
+                if (addr[i])
+                        have_dt_mac = 1;
+        }
+
+        /* cmdline overrides all */
+        if (have_cmdline_mac)
+                memcpy(addr, cmdline_mac, 6);
+        else if (!have_dt_mac) {
+                if (have_fuse_mac)
+                        memcpy(addr, c6x_fuse_mac, 6);
+                else
+                        random_ether_addr(addr);
+        }
+
+        /* adjust for specific EMAC device */
+        addr[5] += index * c6x_num_cores;
+        return 1;
+}
+EXPORT_SYMBOL_GPL(soc_mac_addr);
diff --git a/arch/c6x/kernel/switch_to.S b/arch/c6x/kernel/switch_to.S
new file mode 100644
index 00000000000..09177ed0fa5
--- /dev/null
+++ b/arch/c6x/kernel/switch_to.S
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter (msalter@redhat.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+
+#define SP      B15
+
+        /*
+         * void __switch_to(struct thread_info *prev,
+         *                  struct thread_info *next,
+         *                  struct task_struct *tsk) ;
+         */
+ENTRY(__switch_to)
+        LDDW    .D2T2   *+B4(THREAD_B15_14),B7:B6
+ ||     MV      .L2X    A4,B5   ; prev
+ ||     MV      .L1X    B4,A5   ; next
+ ||     MVC     .S2     RILC,B1
+
+        STW     .D2T2   B3,*+B5(THREAD_PC)
+ ||     STDW    .D1T1   A13:A12,*+A4(THREAD_A13_12)
+ ||     MVC     .S2     ILC,B0
+
+        LDW     .D2T2   *+B4(THREAD_PC),B3
+ ||     LDDW    .D1T1   *+A5(THREAD_A13_12),A13:A12
+
+        STDW    .D1T1   A11:A10,*+A4(THREAD_A11_10)
+ ||     STDW    .D2T2   B1:B0,*+B5(THREAD_RICL_ICL)
+#ifndef __DSBT__
+ ||     MVKL    .S2     current_ksp,B1
+#endif
+
+        STDW    .D2T2   B15:B14,*+B5(THREAD_B15_14)
+ ||     STDW    .D1T1   A15:A14,*+A4(THREAD_A15_14)
+#ifndef __DSBT__
+ ||     MVKH    .S2     current_ksp,B1
+#endif
+
+        ;; Switch to next SP
+        MV      .S2     B7,SP
+#ifdef __DSBT__
+ ||     STW     .D2T2   B7,*+B14(current_ksp)
+#else
+ ||     STW     .D2T2   B7,*B1
+ ||     MV      .L2     B6,B14
+#endif
+ ||     LDDW    .D1T1   *+A5(THREAD_RICL_ICL),A1:A0
+
+        STDW    .D2T2   B11:B10,*+B5(THREAD_B11_10)
+ ||     LDDW    .D1T1   *+A5(THREAD_A15_14),A15:A14
+
+        STDW    .D2T2   B13:B12,*+B5(THREAD_B13_12)
+ ||     LDDW    .D1T1   *+A5(THREAD_A11_10),A11:A10
+
+        B       .S2     B3              ; return in next E1
+ ||     LDDW    .D2T2   *+B4(THREAD_B13_12),B13:B12
+
+        LDDW    .D2T2   *+B4(THREAD_B11_10),B11:B10
+        NOP
+
+        MV      .L2X    A0,B0
+ ||     MV      .S1     A6,A4
+
+        MVC     .S2     B0,ILC
+ ||     MV      .L2X    A1,B1
+
+        MVC     .S2     B1,RILC
+ENDPROC(__switch_to)
diff --git a/arch/c6x/kernel/sys_c6x.c b/arch/c6x/kernel/sys_c6x.c
new file mode 100644
index 00000000000..3e9bdfbee8a
--- /dev/null
+++ b/arch/c6x/kernel/sys_c6x.c
@@ -0,0 +1,74 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+
+#include <asm/syscalls.h>
+
+#ifdef CONFIG_ACCESS_CHECK
+int _access_ok(unsigned long addr, unsigned long size)
+{
+        if (!size)
+                return 1;
+
+        if (!addr || addr > (0xffffffffUL - (size - 1)))
+                goto _bad_access;
+
+        if (segment_eq(get_fs(), KERNEL_DS))
+                return 1;
+
+        if (memory_start <= addr && (addr + size - 1) < memory_end)
+                return 1;
+
+_bad_access:
+        pr_debug("Bad access attempt: pid[%d] addr[%08lx] size[0x%lx]\n",
+                 current->pid, addr, size);
+        return 0;
+}
+EXPORT_SYMBOL(_access_ok);
+#endif
+
+/* sys_cache_sync -- sync caches over given range */
+asmlinkage int sys_cache_sync(unsigned long s, unsigned long e)
+{
+        L1D_cache_block_writeback_invalidate(s, e);
+        L1P_cache_block_invalidate(s, e);
+
+        return 0;
+}
+
+/* Provide the actual syscall number to call mapping. */
+#undef __SYSCALL
+#define __SYSCALL(nr, call) [nr] = (call),
+
+/*
+ * Use trampolines
+ */
+#define sys_pread64             sys_pread_c6x
+#define sys_pwrite64            sys_pwrite_c6x
+#define sys_truncate64          sys_truncate64_c6x
+#define sys_ftruncate64         sys_ftruncate64_c6x
+#define sys_fadvise64           sys_fadvise64_c6x
+#define sys_fadvise64_64        sys_fadvise64_64_c6x
+#define sys_fallocate           sys_fallocate_c6x
+
+/* Use sys_mmap_pgoff directly */
+#define sys_mmap2 sys_mmap_pgoff
+
+/*
+ * Note that we can't include <linux/unistd.h> here since the header
+ * guard will defeat us; <asm/unistd.h> checks for __SYSCALL as well.
+ */
+void *sys_call_table[__NR_syscalls] = {
+        [0 ... __NR_syscalls-1] = sys_ni_syscall,
+#include <asm/unistd.h>
+};
diff --git a/arch/c6x/kernel/time.c b/arch/c6x/kernel/time.c
new file mode 100644
index 00000000000..4c9f136165f
--- /dev/null
+++ b/arch/c6x/kernel/time.c
@@ -0,0 +1,65 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clocksource.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/timex.h>
+#include <linux/profile.h>
+
+#include <asm/timer64.h>
+
+static u32 sched_clock_multiplier;
+#define SCHED_CLOCK_SHIFT 16
+
+static cycle_t tsc_read(struct clocksource *cs)
+{
+        return get_cycles();
+}
+
+static struct clocksource clocksource_tsc = {
+        .name           = "timestamp",
+        .rating         = 300,
+        .read           = tsc_read,
+        .mask           = CLOCKSOURCE_MASK(64),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/*
+ * scheduler clock - returns current time in nanoseconds.
+ */
+u64 sched_clock(void)
+{
+        u64 tsc = get_cycles();
+
+        return (tsc * sched_clock_multiplier) >> SCHED_CLOCK_SHIFT;
+}
+
+void time_init(void)
+{
+        u64 tmp = (u64)NSEC_PER_SEC << SCHED_CLOCK_SHIFT;
+
+        do_div(tmp, c6x_core_freq);
+        sched_clock_multiplier = tmp;
+
+        clocksource_register_hz(&clocksource_tsc, c6x_core_freq);
+
+        /* write anything into TSCL to enable counting */
+        set_creg(TSCL, 0);
+
+        /* probe for timer64 event timer */
+        timer64_init();
+}
diff --git a/arch/c6x/kernel/traps.c b/arch/c6x/kernel/traps.c
new file mode 100644
index 00000000000..f50e3edd6da
--- /dev/null
+++ b/arch/c6x/kernel/traps.c
@@ -0,0 +1,423 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/ptrace.h>
+#include <linux/kallsyms.h>
+#include <linux/bug.h>
+
+#include <asm/soc.h>
+#include <asm/traps.h>
+
+int (*c6x_nmi_handler)(struct pt_regs *regs);
+
+void __init trap_init(void)
+{
+        ack_exception(EXCEPT_TYPE_NXF);
+        ack_exception(EXCEPT_TYPE_EXC);
+        ack_exception(EXCEPT_TYPE_IXF);
+        ack_exception(EXCEPT_TYPE_SXF);
+        enable_exception();
+}
+
+void show_regs(struct pt_regs *regs)
+{
+        pr_err("\n");
+        pr_err("PC: %08lx SP: %08lx\n", regs->pc, regs->sp);
+        pr_err("Status: %08lx ORIG_A4: %08lx\n", regs->csr, regs->orig_a4);
+        pr_err("A0: %08lx  B0: %08lx\n", regs->a0, regs->b0);
+        pr_err("A1: %08lx  B1: %08lx\n", regs->a1, regs->b1);
+        pr_err("A2: %08lx  B2: %08lx\n", regs->a2, regs->b2);
+        pr_err("A3: %08lx  B3: %08lx\n", regs->a3, regs->b3);
+        pr_err("A4: %08lx  B4: %08lx\n", regs->a4, regs->b4);
+        pr_err("A5: %08lx  B5: %08lx\n", regs->a5, regs->b5);
+        pr_err("A6: %08lx  B6: %08lx\n", regs->a6, regs->b6);
+        pr_err("A7: %08lx  B7: %08lx\n", regs->a7, regs->b7);
+        pr_err("A8: %08lx  B8: %08lx\n", regs->a8, regs->b8);
+        pr_err("A9: %08lx  B9: %08lx\n", regs->a9, regs->b9);
+        pr_err("A10: %08lx  B10: %08lx\n", regs->a10, regs->b10);
+        pr_err("A11: %08lx  B11: %08lx\n", regs->a11, regs->b11);
+        pr_err("A12: %08lx  B12: %08lx\n", regs->a12, regs->b12);
+        pr_err("A13: %08lx  B13: %08lx\n", regs->a13, regs->b13);
+        pr_err("A14: %08lx  B14: %08lx\n", regs->a14, regs->dp);
+        pr_err("A15: %08lx  B15: %08lx\n", regs->a15, regs->sp);
+        pr_err("A16: %08lx  B16: %08lx\n", regs->a16, regs->b16);
+        pr_err("A17: %08lx  B17: %08lx\n", regs->a17, regs->b17);
+        pr_err("A18: %08lx  B18: %08lx\n", regs->a18, regs->b18);
+        pr_err("A19: %08lx  B19: %08lx\n", regs->a19, regs->b19);
+        pr_err("A20: %08lx  B20: %08lx\n", regs->a20, regs->b20);
+        pr_err("A21: %08lx  B21: %08lx\n", regs->a21, regs->b21);
+        pr_err("A22: %08lx  B22: %08lx\n", regs->a22, regs->b22);
+        pr_err("A23: %08lx  B23: %08lx\n", regs->a23, regs->b23);
+        pr_err("A24: %08lx  B24: %08lx\n", regs->a24, regs->b24);
+        pr_err("A25: %08lx  B25: %08lx\n", regs->a25, regs->b25);
+        pr_err("A26: %08lx  B26: %08lx\n", regs->a26, regs->b26);
+        pr_err("A27: %08lx  B27: %08lx\n", regs->a27, regs->b27);
+        pr_err("A28: %08lx  B28: %08lx\n", regs->a28, regs->b28);
+        pr_err("A29: %08lx  B29: %08lx\n", regs->a29, regs->b29);
+        pr_err("A30: %08lx  B30: %08lx\n", regs->a30, regs->b30);
+        pr_err("A31: %08lx  B31: %08lx\n", regs->a31, regs->b31);
+}
+
+void dump_stack(void)
+{
+        unsigned long stack;
+
+        show_stack(current, &stack);
+}
+EXPORT_SYMBOL(dump_stack);
+
+
+void die(char *str, struct pt_regs *fp, int nr)
+{
+        console_verbose();
+        pr_err("%s: %08x\n", str, nr);
+        show_regs(fp);
+
+        pr_err("Process %s (pid: %d, stackpage=%08lx)\n",
+               current->comm, current->pid, (PAGE_SIZE +
+                                             (unsigned long) current));
+
+        dump_stack();
+        while (1)
+                ;
+}
+
+static void die_if_kernel(char *str, struct pt_regs *fp, int nr)
+{
+        if (user_mode(fp))
+                return;
+
+        die(str, fp, nr);
+}
+
+
+/* Internal exceptions */
+static struct exception_info iexcept_table[10] = {
+        { "Oops - instruction fetch", SIGBUS, BUS_ADRERR },
+        { "Oops - fetch packet", SIGBUS, BUS_ADRERR },
+        { "Oops - execute packet", SIGILL, ILL_ILLOPC },
+        { "Oops - undefined instruction", SIGILL, ILL_ILLOPC },
+        { "Oops - resource conflict", SIGILL, ILL_ILLOPC },
+        { "Oops - resource access", SIGILL, ILL_PRVREG },
+        { "Oops - privilege", SIGILL, ILL_PRVOPC },
+        { "Oops - loops buffer", SIGILL, ILL_ILLOPC },
+        { "Oops - software exception", SIGILL, ILL_ILLTRP },
+        { "Oops - unknown exception", SIGILL, ILL_ILLOPC }
+};
+
+/* External exceptions */
+static struct exception_info eexcept_table[128] = {
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - external exception", SIGBUS, BUS_ADRERR },
+        { "Oops - CPU memory protection fault", SIGSEGV, SEGV_ACCERR },
+        { "Oops - CPU memory protection fault in L1P", SIGSEGV, SEGV_ACCERR },
+        { "Oops - DMA memory protection fault in L1P", SIGSEGV, SEGV_ACCERR },
+        { "Oops - CPU memory protection fault in L1D", SIGSEGV, SEGV_ACCERR },
+        { "Oops - DMA memory protection fault in L1D", SIGSEGV, SEGV_ACCERR },
+        { "Oops - CPU memory protection fault in L2", SIGSEGV, SEGV_ACCERR },
+        { "Oops - DMA memory protection fault in L2", SIGSEGV, SEGV_ACCERR },
+        { "Oops - EMC CPU memory protection fault", SIGSEGV, SEGV_ACCERR },
+        { "Oops - EMC bus error", SIGBUS, BUS_ADRERR }
+};
+
+static void do_trap(struct exception_info *except_info, struct pt_regs *regs)
+{
+        unsigned long addr = instruction_pointer(regs);
+        siginfo_t info;
+
+        if (except_info->code != TRAP_BRKPT)
+                pr_err("TRAP: %s PC[0x%lx] signo[%d] code[%d]\n",
+                       except_info->kernel_str, regs->pc,
+                       except_info->signo, except_info->code);
+
+        die_if_kernel(except_info->kernel_str, regs, addr);
+
+        info.si_signo = except_info->signo;
+        info.si_errno = 0;
+        info.si_code  = except_info->code;
+        info.si_addr  = (void __user *)addr;
+
+        force_sig_info(except_info->signo, &info, current);
+}
+
+/*
+ * Process an internal exception (non maskable)
+ */
+static int process_iexcept(struct pt_regs *regs)
+{
+        unsigned int iexcept_report = get_iexcept();
+        unsigned int iexcept_num;
+
+        ack_exception(EXCEPT_TYPE_IXF);
+
+        pr_err("IEXCEPT: PC[0x%lx]\n", regs->pc);
+
+        while (iexcept_report) {
+                iexcept_num = __ffs(iexcept_report);
+                iexcept_report &= ~(1 << iexcept_num);
+                set_iexcept(iexcept_report);
+                if (*(unsigned int *)regs->pc == BKPT_OPCODE) {
+                        /* This is a breakpoint */
+                        struct exception_info bkpt_exception = {
+                                "Oops - undefined instruction",
+                                  SIGTRAP, TRAP_BRKPT
+                        };
+                        do_trap(&bkpt_exception, regs);
+                        iexcept_report &= ~(0xFF);
+                        set_iexcept(iexcept_report);
+                        continue;
+                }
+
+                do_trap(&iexcept_table[iexcept_num], regs);
+        }
+        return 0;
+}
+
+/*
+ * Process an external exception (maskable)
+ */
+static void process_eexcept(struct pt_regs *regs)
+{
+        int evt;
+
+        pr_err("EEXCEPT: PC[0x%lx]\n", regs->pc);
+
+        while ((evt = soc_get_exception()) >= 0)
+                do_trap(&eexcept_table[evt], regs);
+
+        ack_exception(EXCEPT_TYPE_EXC);
+}
+
+/*
+ * Main exception processing
+ */
+asmlinkage int process_exception(struct pt_regs *regs)
+{
+        unsigned int type;
+        unsigned int type_num;
+        unsigned int ie_num = 9; /* default is unknown exception */
+
+        while ((type = get_except_type()) != 0) {
+                type_num = fls(type) - 1;
+
+                switch (type_num) {
+                case EXCEPT_TYPE_NXF:
+                        ack_exception(EXCEPT_TYPE_NXF);
+                        if (c6x_nmi_handler)
+                                (c6x_nmi_handler)(regs);
+                        else
+                                pr_alert("NMI interrupt!\n");
+                        break;
+
+                case EXCEPT_TYPE_IXF:
+                        if (process_iexcept(regs))
+                                return 1;
+                        break;
+
+                case EXCEPT_TYPE_EXC:
+                        process_eexcept(regs);
+                        break;
+
+                case EXCEPT_TYPE_SXF:
+                        ie_num = 8;
+                default:
+                        ack_exception(type_num);
+                        do_trap(&iexcept_table[ie_num], regs);
+                        break;
+                }
+        }
+        return 0;
+}
+
+static int kstack_depth_to_print = 48;
+
+static void show_trace(unsigned long *stack, unsigned long *endstack)
+{
+        unsigned long addr;
+        int i;
+
+        pr_debug("Call trace:");
+        i = 0;
+        while (stack + 1 <= endstack) {
+                addr = *stack++;
+                /*
+                 * If the address is either in the text segment of the
+                 * kernel, or in the region which contains vmalloc'ed
+                 * memory, it *may* be the address of a calling
+                 * routine; if so, print it so that someone tracing
+                 * down the cause of the crash will be able to figure
+                 * out the call path that was taken.
+                 */
+                if (__kernel_text_address(addr)) {
+#ifndef CONFIG_KALLSYMS
+                        if (i % 5 == 0)
+                                pr_debug("\n        ");
+#endif
+                        pr_debug(" [<%08lx>]", addr);
+                        print_symbol(" %s\n", addr);
+                        i++;
+                }
+        }
+        pr_debug("\n");
+}
+
+void show_stack(struct task_struct *task, unsigned long *stack)
+{
+        unsigned long *p, *endstack;
+        int i;
+
+        if (!stack) {
+                if (task && task != current)
+                        /* We know this is a kernel stack,
+                           so this is the start/end */
+                        stack = (unsigned long *)thread_saved_ksp(task);
+                else
+                        stack = (unsigned long *)&stack;
+        }
+        endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1)
+                                     & -THREAD_SIZE);
+
+        pr_debug("Stack from %08lx:", (unsigned long)stack);
+        for (i = 0, p = stack; i < kstack_depth_to_print; i++) {
+                if (p + 1 > endstack)
+                        break;
+                if (i % 8 == 0)
+                        pr_cont("\n         ");
+                pr_cont(" %08lx", *p++);
+        }
+        pr_cont("\n");
+        show_trace(stack, endstack);
+}
+
+int is_valid_bugaddr(unsigned long addr)
+{
+        return __kernel_text_address(addr);
+}
diff --git a/arch/c6x/kernel/vectors.S b/arch/c6x/kernel/vectors.S
new file mode 100644
index 00000000000..c95c66fc71e
--- /dev/null
+++ b/arch/c6x/kernel/vectors.S
@@ -0,0 +1,81 @@
+;
+;  Port on Texas Instruments TMS320C6x architecture
+;
+;  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+;  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+;
+;  This program is free software; you can redistribute it and/or modify
+;  it under the terms of the GNU General Public License version 2 as
+;  published by the Free Software Foundation.
+;
+;  This section handles all the interrupt vector routines.
+;  At RESET the processor sets up the DRAM timing parameters and
+;  branches to the label _c_int00 which handles initialization for the C code.
+;
+
+#define ALIGNMENT 5
+
+        .macro IRQVEC name, handler
+        .align ALIGNMENT
+        .hidden \name
+        .global \name
+\name:
+#ifdef CONFIG_C6X_BIG_KERNEL
+        STW     .D2T1   A0,*B15--[2]
+ ||     MVKL    .S1     \handler,A0
+        MVKH    .S1     \handler,A0
+        B       .S2X    A0
+        LDW     .D2T1   *++B15[2],A0
+        NOP     4
+        NOP
+        NOP
+        .endm
+#else /* CONFIG_C6X_BIG_KERNEL */
+        B       .S2     \handler
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        .endm
+#endif /* CONFIG_C6X_BIG_KERNEL */
+
+           .sect ".vectors","ax"
+           .align ALIGNMENT
+           .global RESET
+           .hidden RESET
+RESET:
+#ifdef CONFIG_C6X_BIG_KERNEL
+           MVKL .S1     _c_int00,A0             ; branch to _c_int00
+           MVKH .S1     _c_int00,A0
+           B    .S2X    A0
+#else
+           B    .S2     _c_int00
+           NOP
+           NOP
+#endif
+           NOP
+           NOP
+           NOP
+           NOP
+           NOP
+
+
+           IRQVEC NMI,_nmi_handler              ; NMI interrupt
+           IRQVEC AINT,_bad_interrupt           ; reserved
+           IRQVEC MSGINT,_bad_interrupt         ; reserved
+
+           IRQVEC INT4,_int4_handler
+           IRQVEC INT5,_int5_handler
+           IRQVEC INT6,_int6_handler
+           IRQVEC INT7,_int7_handler
+           IRQVEC INT8,_int8_handler
+           IRQVEC INT9,_int9_handler
+           IRQVEC INT10,_int10_handler
+           IRQVEC INT11,_int11_handler
+           IRQVEC INT12,_int12_handler
+           IRQVEC INT13,_int13_handler
+           IRQVEC INT14,_int14_handler
+           IRQVEC INT15,_int15_handler
diff --git a/arch/c6x/kernel/vmlinux.lds.S b/arch/c6x/kernel/vmlinux.lds.S
new file mode 100644
index 00000000000..1d81c4c129e
--- /dev/null
+++ b/arch/c6x/kernel/vmlinux.lds.S
@@ -0,0 +1,162 @@
+/*
+ * ld script for the c6x kernel
+ *
+ *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
+ *  Mark Salter <msalter@redhat.com>
+ */
+#include <asm-generic/vmlinux.lds.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
+
+ENTRY(_c_int00)
+
+#if defined(CONFIG_CPU_BIG_ENDIAN)
+jiffies = jiffies_64 + 4;
+#else
+jiffies = jiffies_64;
+#endif
+
+#define READONLY_SEGMENT_START  \
+        . = PAGE_OFFSET;
+#define READWRITE_SEGMENT_START \
+        . = ALIGN(128);         \
+        _data_lma = .;
+
+SECTIONS
+{
+        /*
+         * Start kernel read only segment
+         */
+        READONLY_SEGMENT_START
+
+        .vectors :
+        {
+                _vectors_start = .;
+                *(.vectors)
+                . = ALIGN(0x400);
+                _vectors_end = .;
+        }
+
+        . = ALIGN(0x1000);
+        .cmdline :
+        {
+                *(.cmdline)
+        }
+
+        /*
+         * This section contains data which may be shared with other
+         * cores. It needs to be a fixed offset from PAGE_OFFSET
+         * regardless of kernel configuration.
+         */
+        .virtio_ipc_dev :
+        {
+                *(.virtio_ipc_dev)
+        }
+
+        . = ALIGN(PAGE_SIZE);
+        .init :
+        {
+                _stext = .;
+                _sinittext = .;
+                HEAD_TEXT
+                INIT_TEXT
+                _einittext = .;
+        }
+
+        __init_begin = _stext;
+        INIT_DATA_SECTION(16)
+
+        PERCPU_SECTION(128)
+
+        . = ALIGN(PAGE_SIZE);
+        __init_end = .;
+
+        .text :
+        {
+                _text = .;
+                TEXT_TEXT
+                SCHED_TEXT
+                LOCK_TEXT
+                IRQENTRY_TEXT
+                KPROBES_TEXT
+                *(.fixup)
+                *(.gnu.warning)
+        }
+
+        EXCEPTION_TABLE(16)
+        NOTES
+
+        RO_DATA_SECTION(PAGE_SIZE)
+        .const :
+        {
+                *(.const .const.* .gnu.linkonce.r.*)
+                *(.switch)
+        }
+
+        . = ALIGN (8) ;
+        __fdt_blob : AT(ADDR(__fdt_blob) - LOAD_OFFSET)
+        {
+                _fdt_start = . ;        /* place for fdt blob */
+                *(__fdt_blob) ;         /* Any link-placed DTB */
+                BYTE(0);                /* section always has contents */
+                . = _fdt_start + 0x4000;        /* Pad up to 16kbyte */
+                _fdt_end = . ;
+        }
+
+        _etext = .;
+
+        /*
+         * Start kernel read-write segment.
+         */
+        READWRITE_SEGMENT_START
+        _sdata = .;
+
+        .fardata : AT(ADDR(.fardata) - LOAD_OFFSET)
+        {
+                INIT_TASK_DATA(THREAD_SIZE)
+                NOSAVE_DATA
+                PAGE_ALIGNED_DATA(PAGE_SIZE)
+                CACHELINE_ALIGNED_DATA(128)
+                READ_MOSTLY_DATA(128)
+                DATA_DATA
+                CONSTRUCTORS
+                *(.data1)
+                *(.fardata .fardata.*)
+                *(.data.debug_bpt)
+        }
+
+        .neardata ALIGN(8) : AT(ADDR(.neardata) - LOAD_OFFSET)
+        {
+                *(.neardata2 .neardata2.* .gnu.linkonce.s2.*)
+                *(.neardata .neardata.* .gnu.linkonce.s.*)
+                . = ALIGN(8);
+        }
+
+        _edata = .;
+
+        __bss_start = .;
+        SBSS(8)
+        BSS(8)
+        .far :
+        {
+                . = ALIGN(8);
+                *(.dynfar)
+                *(.far .far.* .gnu.linkonce.b.*)
+                . = ALIGN(8);
+        }
+        __bss_stop = .;
+
+        _end = .;
+
+        DWARF_DEBUG
+
+        /DISCARD/ :
+        {
+                  EXIT_TEXT
+                  EXIT_DATA
+                  EXIT_CALL
+                  *(.discard)
+                  *(.discard.*)
+                  *(.interp)
+        }
+}
diff --git a/arch/c6x/lib/Makefile b/arch/c6x/lib/Makefile
new file mode 100644
index 00000000000..ffd3c659091
--- /dev/null
+++ b/arch/c6x/lib/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for arch/c6x/lib/
+#
+
+lib-y := divu.o divi.o pop_rts.o push_rts.o remi.o remu.o strasgi.o llshru.o
+lib-y += llshr.o llshl.o negll.o mpyll.o divremi.o divremu.o
+lib-y += checksum.o csum_64plus.o memcpy_64plus.o strasgi_64plus.o
diff --git a/arch/c6x/lib/checksum.c b/arch/c6x/lib/checksum.c
new file mode 100644
index 00000000000..67cc93b0b93
--- /dev/null
+++ b/arch/c6x/lib/checksum.c
@@ -0,0 +1,36 @@
+/*
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <net/checksum.h>
+
+#include <asm/byteorder.h>
+
+/*
+ * copy from fs while checksumming, otherwise like csum_partial
+ */
+__wsum
+csum_partial_copy_from_user(const void __user *src, void *dst, int len,
+                            __wsum sum, int *csum_err)
+{
+        int missing;
+
+        missing = __copy_from_user(dst, src, len);
+        if (missing) {
+                memset(dst + len - missing, 0, missing);
+                *csum_err = -EFAULT;
+        } else
+                *csum_err = 0;
+
+        return csum_partial(dst, len, sum);
+}
+EXPORT_SYMBOL(csum_partial_copy_from_user);
+
+/* These are from csum_64plus.S */
+EXPORT_SYMBOL(csum_partial);
+EXPORT_SYMBOL(csum_partial_copy);
+EXPORT_SYMBOL(ip_compute_csum);
+EXPORT_SYMBOL(ip_fast_csum);
diff --git a/arch/c6x/lib/csum_64plus.S b/arch/c6x/lib/csum_64plus.S
new file mode 100644
index 00000000000..6d258964722
--- /dev/null
+++ b/arch/c6x/lib/csum_64plus.S
@@ -0,0 +1,419 @@
+;
+;  linux/arch/c6x/lib/csum_64plus.s
+;
+;  Port on Texas Instruments TMS320C6x architecture
+;
+;  Copyright (C) 2006, 2009, 2010, 2011 Texas Instruments Incorporated
+;  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+;
+;  This program is free software; you can redistribute it and/or modify
+;  it under the terms of the GNU General Public License version 2 as
+;  published by the Free Software Foundation.
+;
+#include <linux/linkage.h>
+
+;
+;unsigned int csum_partial_copy(const char *src, char * dst,
+;                               int len, int sum)
+;
+; A4:   src
+; B4:   dst
+; A6:   len
+; B6:   sum
+; return csum in A4
+;
+
+        .text
+ENTRY(csum_partial_copy)
+        MVC     .S2     ILC,B30
+
+        MV      .D1X    B6,A31          ; given csum
+        ZERO    .D1     A9              ; csum (a side)
+||      ZERO    .D2     B9              ; csum (b side)
+||      SHRU    .S2X    A6,2,B5         ; len / 4
+
+        ;; Check alignment and size
+        AND     .S1     3,A4,A1
+||      AND     .S2     3,B4,B0
+        OR      .L2X    B0,A1,B0        ; non aligned condition
+||      MVC     .S2     B5,ILC
+||      MVK     .D2     1,B2
+||      MV      .D1X    B5,A1           ; words condition
+  [!A1] B       .S1     L8
+   [B0] BNOP    .S1     L6,5
+
+        SPLOOP          1
+
+        ;; Main loop for aligned words
+        LDW     .D1T1   *A4++,A7
+        NOP     4
+        MV      .S2X    A7,B7
+||      EXTU    .S1     A7,0,16,A16
+        STW     .D2T2   B7,*B4++
+||      MPYU    .M2     B7,B2,B8
+||      ADD     .L1     A16,A9,A9
+        NOP
+        SPKERNEL        8,0
+||      ADD     .L2     B8,B9,B9
+
+        ZERO    .D1     A1
+||      ADD     .L1X    A9,B9,A9        ;  add csum from a and b sides
+
+L6:
+  [!A1] BNOP    .S1     L8,5
+
+        ;; Main loop for non-aligned words
+        SPLOOP          2
+ ||     MVK     .L1     1,A2
+
+        LDNW    .D1T1   *A4++,A7
+        NOP             3
+
+        NOP
+        MV      .S2X    A7,B7
+ ||     EXTU    .S1     A7,0,16,A16
+ ||     MPYU    .M1     A7,A2,A8
+
+        ADD     .L1     A16,A9,A9
+        SPKERNEL        6,0
+ ||     STNW    .D2T2   B7,*B4++
+ ||     ADD     .L1     A8,A9,A9
+
+L8:     AND     .S2X    2,A6,B5
+        CMPGT   .L2     B5,0,B0
+  [!B0] BNOP    .S1     L82,4
+
+        ;; Manage half-word
+        ZERO    .L1     A7
+||      ZERO    .D1     A8
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+
+        LDBU    .D1T1   *A4++,A7
+        LDBU    .D1T1   *A4++,A8
+        NOP             3
+        SHL     .S1     A7,8,A0
+        ADD     .S1     A8,A9,A9
+        STB     .D2T1   A7,*B4++
+||      ADD     .S1     A0,A9,A9
+        STB     .D2T1   A8,*B4++
+
+#else
+
+        LDBU    .D1T1   *A4++,A7
+        LDBU    .D1T1   *A4++,A8
+        NOP             3
+        ADD     .S1     A7,A9,A9
+        SHL     .S1     A8,8,A0
+
+        STB     .D2T1   A7,*B4++
+||      ADD     .S1     A0,A9,A9
+        STB     .D2T1   A8,*B4++
+
+#endif
+
+        ;; Manage eventually the last byte
+L82:    AND     .S2X    1,A6,B0
+  [!B0] BNOP    .S1     L9,5
+
+||      ZERO    .L1     A7
+
+L83:    LDBU    .D1T1   *A4++,A7
+        NOP             4
+
+        MV      .L2X    A7,B7
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+
+        STB     .D2T2   B7,*B4++
+||      SHL     .S1     A7,8,A7
+        ADD     .S1     A7,A9,A9
+
+#else
+
+        STB     .D2T2   B7,*B4++
+||      ADD     .S1     A7,A9,A9
+
+#endif
+
+        ;; Fold the csum
+L9:     SHRU    .S2X    A9,16,B0
+  [!B0] BNOP    .S1     L10,5
+
+L91:    SHRU    .S2X    A9,16,B4
+||      EXTU    .S1     A9,16,16,A3
+        ADD     .D1X    A3,B4,A9
+
+        SHRU    .S1     A9,16,A0
+   [A0] BNOP    .S1     L91,5
+
+L10:    ADD     .D1     A31,A9,A9
+        MV      .D1     A9,A4
+
+        BNOP    .S2     B3,4
+        MVC     .S2     B30,ILC
+ENDPROC(csum_partial_copy)
+
+;
+;unsigned short
+;ip_fast_csum(unsigned char *iph, unsigned int ihl)
+;{
+;       unsigned int checksum = 0;
+;       unsigned short *tosum = (unsigned short *) iph;
+;       int len;
+;
+;       len = ihl*4;
+;
+;       if (len <= 0)
+;               return 0;
+;
+;       while(len) {
+;               len -= 2;
+;               checksum += *tosum++;
+;       }
+;       if (len & 1)
+;               checksum += *(unsigned char*) tosum;
+;
+;       while(checksum >> 16)
+;               checksum = (checksum & 0xffff) + (checksum >> 16);
+;
+;       return ~checksum;
+;}
+;
+; A4:   iph
+; B4:   ihl
+; return checksum in A4
+;
+        .text
+
+ENTRY(ip_fast_csum)
+        ZERO    .D1     A5
+ ||     MVC     .S2     ILC,B30
+        SHL     .S2     B4,2,B0
+        CMPGT   .L2     B0,0,B1
+  [!B1] BNOP    .S1     L15,4
+  [!B1] ZERO    .D1     A3
+
+  [!B0] B       .S1     L12
+        SHRU    .S2     B0,1,B0
+        MVC     .S2     B0,ILC
+        NOP     3
+
+        SPLOOP  1
+        LDHU    .D1T1   *A4++,A3
+        NOP     3
+        NOP
+        SPKERNEL        5,0
+ ||     ADD     .L1     A3,A5,A5
+
+L12:    SHRU    .S1     A5,16,A0
+  [!A0] BNOP    .S1     L14,5
+
+L13:    SHRU    .S2X    A5,16,B4
+        EXTU    .S1     A5,16,16,A3
+        ADD     .D1X    A3,B4,A5
+        SHRU    .S1     A5,16,A0
+  [A0]  BNOP    .S1     L13,5
+
+L14:    NOT     .D1     A5,A3
+        EXTU    .S1     A3,16,16,A3
+
+L15:    BNOP    .S2     B3,3
+        MVC     .S2     B30,ILC
+        MV      .D1     A3,A4
+ENDPROC(ip_fast_csum)
+
+;
+;unsigned short
+;do_csum(unsigned char *buff, unsigned int len)
+;{
+;       int odd, count;
+;       unsigned int result = 0;
+;
+;       if (len <= 0)
+;               goto out;
+;       odd = 1 & (unsigned long) buff;
+;       if (odd) {
+;#ifdef __LITTLE_ENDIAN
+;               result += (*buff << 8);
+;#else
+;               result = *buff;
+;#endif
+;               len--;
+;               buff++;
+;       }
+;       count = len >> 1;               /* nr of 16-bit words.. */
+;       if (count) {
+;               if (2 & (unsigned long) buff) {
+;                       result += *(unsigned short *) buff;
+;                       count--;
+;                       len -= 2;
+;                       buff += 2;
+;               }
+;               count >>= 1;            /* nr of 32-bit words.. */
+;               if (count) {
+;                       unsigned int carry = 0;
+;                       do {
+;                               unsigned int w = *(unsigned int *) buff;
+;                               count--;
+;                               buff += 4;
+;                               result += carry;
+;                               result += w;
+;                               carry = (w > result);
+;                       } while (count);
+;                       result += carry;
+;                       result = (result & 0xffff) + (result >> 16);
+;               }
+;               if (len & 2) {
+;                       result += *(unsigned short *) buff;
+;                       buff += 2;
+;               }
+;       }
+;       if (len & 1)
+;#ifdef __LITTLE_ENDIAN
+;               result += *buff;
+;#else
+;               result += (*buff << 8);
+;#endif
+;       result = (result & 0xffff) + (result >> 16);
+;       /* add up carry.. */
+;       result = (result & 0xffff) + (result >> 16);
+;       if (odd)
+;               result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
+;out:
+;       return result;
+;}
+;
+; A4:   buff
+; B4:   len
+; return checksum in A4
+;
+
+ENTRY(do_csum)
+           CMPGT   .L2     B4,0,B0
+   [!B0]   BNOP    .S1     L26,3
+           EXTU    .S1     A4,31,31,A0
+
+           MV      .L1     A0,A3
+||         MV      .S1X    B3,A5
+||         MV      .L2     B4,B3
+||         ZERO    .D1     A1
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+   [A0]    SUB     .L2     B3,1,B3
+|| [A0]    LDBU    .D1T1   *A4++,A1
+#else
+   [!A0]   BNOP    .S1     L21,5
+|| [A0]    LDBU    .D1T1   *A4++,A0
+           SUB     .L2     B3,1,B3
+||         SHL     .S1     A0,8,A1
+L21:
+#endif
+           SHR     .S2     B3,1,B0
+   [!B0]   BNOP    .S1     L24,3
+           MVK     .L1     2,A0
+           AND     .L1     A4,A0,A0
+
+   [!A0]   BNOP    .S1     L22,5
+|| [A0]    LDHU    .D1T1   *A4++,A0
+           SUB     .L2     B0,1,B0
+||         SUB     .S2     B3,2,B3
+||         ADD     .L1     A0,A1,A1
+L22:
+           SHR     .S2     B0,1,B0
+||         ZERO    .L1     A0
+
+   [!B0]   BNOP    .S1     L23,5
+|| [B0]    MVC     .S2     B0,ILC
+
+           SPLOOP  3
+           SPMASK  L1
+||         MV      .L1     A1,A2
+||         LDW     .D1T1   *A4++,A1
+
+           NOP     4
+           ADD     .L1     A0,A1,A0
+           ADD     .L1     A2,A0,A2
+
+           SPKERNEL 1,2
+||         CMPGTU  .L1     A1,A2,A0
+
+           ADD     .L1     A0,A2,A6
+           EXTU    .S1     A6,16,16,A7
+           SHRU    .S2X    A6,16,B0
+           NOP             1
+           ADD     .L1X    A7,B0,A1
+L23:
+           MVK     .L2     2,B0
+           AND     .L2     B3,B0,B0
+   [B0]    LDHU    .D1T1   *A4++,A0
+           NOP     4
+   [B0]    ADD     .L1     A0,A1,A1
+L24:
+           EXTU    .S2     B3,31,31,B0
+#ifdef CONFIG_CPU_BIG_ENDIAN
+   [!B0]   BNOP    .S1     L25,4
+|| [B0]    LDBU    .D1T1   *A4,A0
+           SHL     .S1     A0,8,A0
+           ADD     .L1     A0,A1,A1
+L25:
+#else
+   [B0]    LDBU    .D1T1   *A4,A0
+           NOP     4
+   [B0]    ADD     .L1     A0,A1,A1
+#endif
+           EXTU    .S1     A1,16,16,A0
+           SHRU    .S2X    A1,16,B0
+           NOP     1
+           ADD     .L1X    A0,B0,A0
+           SHRU    .S1     A0,16,A1
+           ADD     .L1     A0,A1,A0
+           EXTU    .S1     A0,16,16,A1
+           EXTU    .S1     A1,16,24,A2
+
+           EXTU    .S1     A1,24,16,A0
+||         MV      .L2X    A3,B0
+
+   [B0]    OR      .L1     A0,A2,A1
+L26:
+           NOP     1
+           BNOP    .S2X    A5,4
+           MV      .L1     A1,A4
+ENDPROC(do_csum)
+
+;__wsum csum_partial(const void *buff, int len, __wsum wsum)
+;{
+;       unsigned int sum = (__force unsigned int)wsum;
+;       unsigned int result = do_csum(buff, len);
+;
+;       /* add in old sum, and carry.. */
+;       result += sum;
+;       if (sum > result)
+;               result += 1;
+;       return (__force __wsum)result;
+;}
+;
+ENTRY(csum_partial)
+           MV      .L1X    B3,A9
+||         CALLP   .S2     do_csum,B3
+||         MV      .S1     A6,A8
+           BNOP    .S2X    A9,2
+           ADD     .L1     A8,A4,A1
+           CMPGTU  .L1     A8,A1,A0
+           ADD     .L1     A1,A0,A4
+ENDPROC(csum_partial)
+
+;unsigned short
+;ip_compute_csum(unsigned char *buff, unsigned int len)
+;
+; A4:   buff
+; B4:   len
+; return checksum in A4
+
+ENTRY(ip_compute_csum)
+           MV      .L1X    B3,A9
+||         CALLP   .S2     do_csum,B3
+           BNOP    .S2X    A9,3
+           NOT     .S1     A4,A4
+           CLR     .S1     A4,16,31,A4
+ENDPROC(ip_compute_csum)
diff --git a/arch/c6x/lib/divi.S b/arch/c6x/lib/divi.S
new file mode 100644
index 00000000000..4bde924f2a9
--- /dev/null
+++ b/arch/c6x/lib/divi.S
@@ -0,0 +1,53 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        ;; ABI considerations for the divide functions
+        ;; The following registers are call-used:
+        ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
+        ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
+        ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
+        ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
+        ;;
+        ;; In our implementation, divu and remu are leaf functions,
+        ;; while both divi and remi call into divu.
+        ;; A0 is not clobbered by any of the functions.
+        ;; divu does not clobber B2 either, which is taken advantage of
+        ;; in remi.
+        ;; divi uses B5 to hold the original return address during
+        ;; the call to divu.
+        ;; remi uses B2 and A5 to hold the input values during the
+        ;; call to divu.  It stores B3 in on the stack.
+
+        .text
+ENTRY(__c6xabi_divi)
+        call    .s2     __c6xabi_divu
+||      mv      .d2     B3, B5
+||      cmpgt   .l1     0, A4, A1
+||      cmpgt   .l2     0, B4, B1
+
+   [A1] neg     .l1     A4, A4
+|| [B1] neg     .l2     B4, B4
+||      xor     .s1x    A1, B1, A1
+   [A1] addkpc  .s2     _divu_ret, B3, 4
+_divu_ret:
+        neg     .l1     A4, A4
+||      mv      .l2     B3,B5
+||      ret     .s2     B5
+        nop             5
+ENDPROC(__c6xabi_divi)
diff --git a/arch/c6x/lib/divremi.S b/arch/c6x/lib/divremi.S
new file mode 100644
index 00000000000..64bc5aa95ad
--- /dev/null
+++ b/arch/c6x/lib/divremi.S
@@ -0,0 +1,46 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        .text
+ENTRY(__c6xabi_divremi)
+        stw     .d2t2   B3, *B15--[2]
+||      cmpgt   .l1     0, A4, A1
+||      cmpgt   .l2     0, B4, B2
+||      mv      .s1     A4, A5
+||      call    .s2     __c6xabi_divu
+
+   [A1] neg     .l1     A4, A4
+|| [B2] neg     .l2     B4, B4
+||      xor     .s2x    B2, A1, B0
+||      mv      .d2     B4, B2
+
+   [B0] addkpc  .s2     _divu_ret_1, B3, 1
+  [!B0] addkpc  .s2     _divu_ret_2, B3, 1
+        nop     2
+_divu_ret_1:
+        neg     .l1     A4, A4
+_divu_ret_2:
+        ldw     .d2t2   *++B15[2], B3
+
+        mpy32   .m1x    A4, B2, A6
+        nop             3
+        ret     .s2     B3
+        sub     .l1     A5, A6, A5
+        nop     4
+ENDPROC(__c6xabi_divremi)
diff --git a/arch/c6x/lib/divremu.S b/arch/c6x/lib/divremu.S
new file mode 100644
index 00000000000..caa9f23ee16
--- /dev/null
+++ b/arch/c6x/lib/divremu.S
@@ -0,0 +1,87 @@
+;;  Copyright 2011  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        .text
+ENTRY(__c6xabi_divremu)
+        ;; We use a series of up to 31 subc instructions.  First, we find
+        ;; out how many leading zero bits there are in the divisor.  This
+        ;; gives us both a shift count for aligning (shifting) the divisor
+        ;; to the, and the number of times we have to execute subc.
+
+        ;; At the end, we have both the remainder and most of the quotient
+        ;; in A4.  The top bit of the quotient is computed first and is
+        ;; placed in A2.
+
+        ;; Return immediately if the dividend is zero.  Setting B4 to 1
+        ;; is a trick to allow us to leave the following insns in the jump
+        ;; delay slot without affecting the result.
+        mv      .s2x    A4, B1
+
+  [b1]  lmbd    .l2     1, B4, B1
+||[!b1] b       .s2     B3      ; RETURN A
+||[!b1] mvk     .d2     1, B4
+
+||[!b1] zero    .s1     A5
+        mv      .l1x    B1, A6
+||      shl     .s2     B4, B1, B4
+
+        ;; The loop performs a maximum of 28 steps, so we do the
+        ;; first 3 here.
+        cmpltu  .l1x    A4, B4, A2
+  [!A2] sub     .l1x    A4, B4, A4
+||      shru    .s2     B4, 1, B4
+||      xor     .s1     1, A2, A2
+
+        shl     .s1     A2, 31, A2
+|| [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+
+        ;; RETURN A may happen here (note: must happen before the next branch)
+__divremu0:
+        cmpgt   .l2     B1, 7, B0
+|| [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+|| [b0] b       .s1     __divremu0
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+   [b1] subc    .l1x    A4,B4,A4
+|| [b1] add     .s2     -1, B1, B1
+        ;; loop backwards branch happens here
+
+        ret     .s2     B3
+||      mvk     .s1     32, A1
+        sub     .l1     A1, A6, A6
+||      extu    .s1     A4, A6, A5
+        shl     .s1     A4, A6, A4
+        shru    .s1     A4, 1, A4
+||      sub     .l1     A6, 1, A6
+        or      .l1     A2, A4, A4
+        shru    .s1     A4, A6, A4
+        nop
+ENDPROC(__c6xabi_divremu)
diff --git a/arch/c6x/lib/divu.S b/arch/c6x/lib/divu.S
new file mode 100644
index 00000000000..64af3c006dd
--- /dev/null
+++ b/arch/c6x/lib/divu.S
@@ -0,0 +1,98 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        ;; ABI considerations for the divide functions
+        ;; The following registers are call-used:
+        ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
+        ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
+        ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
+        ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
+        ;;
+        ;; In our implementation, divu and remu are leaf functions,
+        ;; while both divi and remi call into divu.
+        ;; A0 is not clobbered by any of the functions.
+        ;; divu does not clobber B2 either, which is taken advantage of
+        ;; in remi.
+        ;; divi uses B5 to hold the original return address during
+        ;; the call to divu.
+        ;; remi uses B2 and A5 to hold the input values during the
+        ;; call to divu.  It stores B3 in on the stack.
+
+        .text
+ENTRY(__c6xabi_divu)
+        ;; We use a series of up to 31 subc instructions.  First, we find
+        ;; out how many leading zero bits there are in the divisor.  This
+        ;; gives us both a shift count for aligning (shifting) the divisor
+        ;; to the, and the number of times we have to execute subc.
+
+        ;; At the end, we have both the remainder and most of the quotient
+        ;; in A4.  The top bit of the quotient is computed first and is
+        ;; placed in A2.
+
+        ;; Return immediately if the dividend is zero.
+         mv     .s2x    A4, B1
+   [B1]  lmbd   .l2     1, B4, B1
+|| [!B1] b      .s2     B3      ; RETURN A
+|| [!B1] mvk    .d2     1, B4
+         mv     .l1x    B1, A6
+||       shl    .s2     B4, B1, B4
+
+        ;; The loop performs a maximum of 28 steps, so we do the
+        ;; first 3 here.
+         cmpltu .l1x    A4, B4, A2
+   [!A2] sub    .l1x    A4, B4, A4
+||       shru   .s2     B4, 1, B4
+||       xor    .s1     1, A2, A2
+
+         shl    .s1     A2, 31, A2
+|| [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+
+        ;; RETURN A may happen here (note: must happen before the next branch)
+_divu_loop:
+         cmpgt  .l2     B1, 7, B0
+|| [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+|| [B0]  b      .s1     _divu_loop
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+        ;; loop backwards branch happens here
+
+         ret    .s2     B3
+||       mvk    .s1     32, A1
+         sub    .l1     A1, A6, A6
+         shl    .s1     A4, A6, A4
+         shru   .s1     A4, 1, A4
+||       sub    .l1     A6, 1, A6
+         or     .l1     A2, A4, A4
+         shru   .s1     A4, A6, A4
+         nop
+ENDPROC(__c6xabi_divu)
diff --git a/arch/c6x/lib/llshl.S b/arch/c6x/lib/llshl.S
new file mode 100644
index 00000000000..7b105e2d1b7
--- /dev/null
+++ b/arch/c6x/lib/llshl.S
@@ -0,0 +1,37 @@
+;;  Copyright (C) 2010 Texas Instruments Incorporated
+;;  Contributed by Mark Salter <msalter@redhat.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+;;  uint64_t __c6xabi_llshl(uint64_t val, uint shift)
+
+#include <linux/linkage.h>
+
+        .text
+ENTRY(__c6xabi_llshl)
+         mv     .l1x    B4,A1
+   [!A1] b      .s2     B3              ; just return if zero shift
+         mvk    .s1     32,A0
+         sub    .d1     A0,A1,A0
+         cmplt  .l1     0,A0,A2
+   [A2]  shru   .s1     A4,A0,A0
+   [!A2] neg    .l1     A0,A5
+|| [A2]  shl    .s1     A5,A1,A5
+   [!A2] shl    .s1     A4,A5,A5
+|| [A2]  or     .d1     A5,A0,A5
+|| [!A2] mvk    .l1     0,A4
+   [A2]  shl    .s1     A4,A1,A4
+         bnop   .s2     B3,5
+ENDPROC(__c6xabi_llshl)
diff --git a/arch/c6x/lib/llshr.S b/arch/c6x/lib/llshr.S
new file mode 100644
index 00000000000..fde1bec7cf5
--- /dev/null
+++ b/arch/c6x/lib/llshr.S
@@ -0,0 +1,38 @@
+;;  Copyright (C) 2010 Texas Instruments Incorporated
+;;  Contributed by Mark Salter <msalter@redhat.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+;;  uint64_t __c6xabi_llshr(uint64_t val, uint shift)
+
+#include <linux/linkage.h>
+
+        .text
+ENTRY(__c6xabi_llshr)
+         mv     .l1x    B4,A1
+   [!A1] b      .s2     B3              ; return if zero shift count
+         mvk    .s1     32,A0
+         sub    .d1     A0,A1,A0
+         cmplt  .l1     0,A0,A2
+   [A2]  shl    .s1     A5,A0,A0
+         nop
+   [!A2] neg    .l1     A0,A4
+|| [A2]  shru   .s1     A4,A1,A4
+   [!A2] shr    .s1     A5,A4,A4
+|| [A2]  or     .d1     A4,A0,A4
+   [!A2] shr    .s1     A5,0x1f,A5
+   [A2]  shr    .s1     A5,A1,A5
+         bnop   .s2     B3,5
+ENDPROC(__c6xabi_llshr)
diff --git a/arch/c6x/lib/llshru.S b/arch/c6x/lib/llshru.S
new file mode 100644
index 00000000000..596ae3ff5c0
--- /dev/null
+++ b/arch/c6x/lib/llshru.S
@@ -0,0 +1,38 @@
+;;  Copyright (C) 2010 Texas Instruments Incorporated
+;;  Contributed by Mark Salter <msalter@redhat.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+;;  uint64_t __c6xabi_llshru(uint64_t val, uint shift)
+
+#include <linux/linkage.h>
+
+        .text
+ENTRY(__c6xabi_llshru)
+         mv     .l1x    B4,A1
+   [!A1] b      .s2     B3              ; return if zero shift count
+         mvk    .s1     32,A0
+         sub    .d1     A0,A1,A0
+         cmplt  .l1     0,A0,A2
+   [A2]  shl    .s1     A5,A0,A0
+         nop
+   [!A2] neg    .l1     A0,A4
+|| [A2]  shru   .s1     A4,A1,A4
+   [!A2] shru   .s1     A5,A4,A4
+|| [A2]  or     .d1     A4,A0,A4
+|| [!A2] mvk    .l1     0,A5
+   [A2]  shru   .s1     A5,A1,A5
+         bnop   .s2     B3,5
+ENDPROC(__c6xabi_llshru)
diff --git a/arch/c6x/lib/memcpy_64plus.S b/arch/c6x/lib/memcpy_64plus.S
new file mode 100644
index 00000000000..0bbc2cbf931
--- /dev/null
+++ b/arch/c6x/lib/memcpy_64plus.S
@@ -0,0 +1,46 @@
+;  Port on Texas Instruments TMS320C6x architecture
+;
+;  Copyright (C) 2006, 2009, 2010 Texas Instruments Incorporated
+;  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+;
+;  This program is free software; you can redistribute it and/or modify
+;  it under the terms of the GNU General Public License version 2 as
+;  published by the Free Software Foundation.
+;
+
+#include <linux/linkage.h>
+
+        .text
+
+ENTRY(memcpy)
+        AND     .L1     0x1,A6,A0
+ ||     AND     .S1     0x2,A6,A1
+ ||     AND     .L2X    0x4,A6,B0
+ ||     MV      .D1     A4,A3
+ ||     MVC     .S2     ILC,B2
+
+   [A0] LDB     .D2T1   *B4++,A5
+   [A1] LDB     .D2T1   *B4++,A7
+   [A1] LDB     .D2T1   *B4++,A8
+   [B0] LDNW    .D2T1   *B4++,A9
+ ||     SHRU    .S2X    A6,0x3,B1
+  [!B1] BNOP    .S2     B3,1
+
+   [A0] STB     .D1T1   A5,*A3++
+ ||[B1] MVC     .S2     B1,ILC
+   [A1] STB     .D1T1   A7,*A3++
+   [A1] STB     .D1T1   A8,*A3++
+   [B0] STNW    .D1T1   A9,*A3++        ; return when len < 8
+
+        SPLOOP  2
+
+        LDNDW   .D2T1   *B4++,A9:A8
+        NOP     3
+
+        NOP
+        SPKERNEL        0,0
+ ||     STNDW   .D1T1   A9:A8,*A3++
+
+        BNOP    .S2     B3,4
+        MVC     .S2     B2,ILC
+ENDPROC(memcpy)
diff --git a/arch/c6x/lib/mpyll.S b/arch/c6x/lib/mpyll.S
new file mode 100644
index 00000000000..f1034418b4d
--- /dev/null
+++ b/arch/c6x/lib/mpyll.S
@@ -0,0 +1,49 @@
+;;  Copyright (C) 2010 Texas Instruments Incorporated
+;;  Contributed by Mark Salter <msalter@redhat.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        ;; uint64_t __c6xabi_mpyll(uint64_t x, uint64_t y)
+        ;;
+        ;; 64x64 multiply
+        ;; First compute partial results using 32-bit parts of x and y:
+        ;;
+        ;;   b63         b32 b31          b0
+        ;;    -----------------------------
+        ;;    |      1      |      0      |
+        ;;    -----------------------------
+        ;;
+        ;;   P0 = X0*Y0
+        ;;   P1 = X0*Y1 + X1*Y0
+        ;;   P2 = X1*Y1
+        ;;
+        ;;   result = (P2 << 64) + (P1 << 32) + P0
+        ;;
+        ;; Since the result is also 64-bit, we can skip the P2 term.
+
+        .text
+ENTRY(__c6xabi_mpyll)
+        mpy32u  .m1x    A4,B4,A1:A0     ; X0*Y0
+        b       .s2     B3
+ ||     mpy32u  .m2x    B5,A4,B1:B0     ; X0*Y1 (don't need upper 32-bits)
+ ||     mpy32u  .m1x    A5,B4,A3:A2     ; X1*Y0 (don't need upper 32-bits)
+        nop
+        nop
+        mv      .s1     A0,A4
+        add     .l1x    A2,B0,A5
+        add     .s1     A1,A5,A5
+ENDPROC(__c6xabi_mpyll)
diff --git a/arch/c6x/lib/negll.S b/arch/c6x/lib/negll.S
new file mode 100644
index 00000000000..82f4bcec9af
--- /dev/null
+++ b/arch/c6x/lib/negll.S
@@ -0,0 +1,31 @@
+;;  Copyright (C) 2010 Texas Instruments Incorporated
+;;  Contributed by Mark Salter <msalter@redhat.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+;;  int64_t __c6xabi_negll(int64_t val)
+
+#include <linux/linkage.h>
+
+        .text
+ENTRY(__c6xabi_negll)
+        b       .s2     B3
+        mvk     .l1     0,A0
+        subu    .l1     A0,A4,A3:A2
+        sub     .l1     A0,A5,A0
+||      ext     .s1     A3,24,24,A5
+        add     .l1     A5,A0,A5
+        mv      .s1     A2,A4
+ENDPROC(__c6xabi_negll)
diff --git a/arch/c6x/lib/pop_rts.S b/arch/c6x/lib/pop_rts.S
new file mode 100644
index 00000000000..d7d96c70e9e
--- /dev/null
+++ b/arch/c6x/lib/pop_rts.S
@@ -0,0 +1,32 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        .text
+
+ENTRY(__c6xabi_pop_rts)
+        lddw    .d2t2   *++B15, B3:B2
+        lddw    .d2t1   *++B15, A11:A10
+        lddw    .d2t2   *++B15, B11:B10
+        lddw    .d2t1   *++B15, A13:A12
+        lddw    .d2t2   *++B15, B13:B12
+        lddw    .d2t1   *++B15, A15:A14
+||      b       .s2     B3
+        ldw     .d2t2   *++B15[2], B14
+        nop     4
+ENDPROC(__c6xabi_pop_rts)
diff --git a/arch/c6x/lib/push_rts.S b/arch/c6x/lib/push_rts.S
new file mode 100644
index 00000000000..f6e3db3b606
--- /dev/null
+++ b/arch/c6x/lib/push_rts.S
@@ -0,0 +1,31 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        .text
+
+ENTRY(__c6xabi_push_rts)
+        stw     .d2t2   B14, *B15--[2]
+        stdw    .d2t1   A15:A14, *B15--
+||      b       .s2x    A3
+        stdw    .d2t2   B13:B12, *B15--
+        stdw    .d2t1   A13:A12, *B15--
+        stdw    .d2t2   B11:B10, *B15--
+        stdw    .d2t1   A11:A10, *B15--
+        stdw    .d2t2   B3:B2, *B15--
+ENDPROC(__c6xabi_push_rts)
diff --git a/arch/c6x/lib/remi.S b/arch/c6x/lib/remi.S
new file mode 100644
index 00000000000..6f2ca18c3f9
--- /dev/null
+++ b/arch/c6x/lib/remi.S
@@ -0,0 +1,64 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        ;; ABI considerations for the divide functions
+        ;; The following registers are call-used:
+        ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
+        ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
+        ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
+        ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
+        ;;
+        ;; In our implementation, divu and remu are leaf functions,
+        ;; while both divi and remi call into divu.
+        ;; A0 is not clobbered by any of the functions.
+        ;; divu does not clobber B2 either, which is taken advantage of
+        ;; in remi.
+        ;; divi uses B5 to hold the original return address during
+        ;; the call to divu.
+        ;; remi uses B2 and A5 to hold the input values during the
+        ;; call to divu.  It stores B3 in on the stack.
+
+        .text
+
+ENTRY(__c6xabi_remi)
+        stw     .d2t2   B3, *B15--[2]
+||      cmpgt   .l1     0, A4, A1
+||      cmpgt   .l2     0, B4, B2
+||      mv      .s1     A4, A5
+||      call    .s2     __c6xabi_divu
+
+   [A1] neg     .l1     A4, A4
+|| [B2] neg     .l2     B4, B4
+||      xor     .s2x    B2, A1, B0
+||      mv      .d2     B4, B2
+
+   [B0] addkpc  .s2     _divu_ret_1, B3, 1
+  [!B0] addkpc  .s2     _divu_ret_2, B3, 1
+        nop     2
+_divu_ret_1:
+        neg     .l1     A4, A4
+_divu_ret_2:
+        ldw     .d2t2   *++B15[2], B3
+
+        mpy32   .m1x    A4, B2, A6
+        nop             3
+        ret     .s2     B3
+        sub     .l1     A5, A6, A4
+        nop     4
+ENDPROC(__c6xabi_remi)
diff --git a/arch/c6x/lib/remu.S b/arch/c6x/lib/remu.S
new file mode 100644
index 00000000000..3fae719185a
--- /dev/null
+++ b/arch/c6x/lib/remu.S
@@ -0,0 +1,82 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        ;; ABI considerations for the divide functions
+        ;; The following registers are call-used:
+        ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
+        ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
+        ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
+        ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
+        ;;
+        ;; In our implementation, divu and remu are leaf functions,
+        ;; while both divi and remi call into divu.
+        ;; A0 is not clobbered by any of the functions.
+        ;; divu does not clobber B2 either, which is taken advantage of
+        ;; in remi.
+        ;; divi uses B5 to hold the original return address during
+        ;; the call to divu.
+        ;; remi uses B2 and A5 to hold the input values during the
+        ;; call to divu.  It stores B3 in on the stack.
+
+
+        .text
+
+ENTRY(__c6xabi_remu)
+        ;; The ABI seems designed to prevent these functions calling each other,
+        ;; so we duplicate most of the divsi3 code here.
+         mv     .s2x    A4, B1
+         lmbd   .l2     1, B4, B1
+|| [!B1] b      .s2     B3      ; RETURN A
+|| [!B1] mvk    .d2     1, B4
+
+         mv     .l1x    B1, A7
+||       shl    .s2     B4, B1, B4
+
+         cmpltu .l1x    A4, B4, A1
+   [!A1] sub    .l1x    A4, B4, A4
+         shru   .s2     B4, 1, B4
+
+_remu_loop:
+         cmpgt  .l2     B1, 7, B0
+|| [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+        ;; RETURN A may happen here (note: must happen before the next branch)
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+|| [B0]  b      .s1     _remu_loop
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+        ;; loop backwards branch happens here
+
+         ret    .s2     B3
+   [B1]  subc   .l1x    A4,B4,A4
+|| [B1]  add    .s2     -1, B1, B1
+   [B1]  subc   .l1x    A4,B4,A4
+
+         extu   .s1     A4, A7, A4
+         nop    2
+ENDPROC(__c6xabi_remu)
diff --git a/arch/c6x/lib/strasgi.S b/arch/c6x/lib/strasgi.S
new file mode 100644
index 00000000000..de274076553
--- /dev/null
+++ b/arch/c6x/lib/strasgi.S
@@ -0,0 +1,89 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        .text
+
+ENTRY(__c6xabi_strasgi)
+        ;; This is essentially memcpy, with alignment known to be at least
+        ;; 4, and the size a multiple of 4 greater than or equal to 28.
+         ldw    .d2t1   *B4++, A0
+||       mvk    .s2     16, B1
+         ldw    .d2t1   *B4++, A1
+||       mvk    .s2     20, B2
+||       sub    .d1     A6, 24, A6
+         ldw    .d2t1   *B4++, A5
+         ldw    .d2t1   *B4++, A7
+||       mv     .l2x    A6, B7
+         ldw    .d2t1   *B4++, A8
+         ldw    .d2t1   *B4++, A9
+||       mv     .s2x    A0, B5
+||       cmpltu .l2     B2, B7, B0
+
+_strasgi_loop:
+         stw    .d1t2   B5, *A4++
+|| [B0]  ldw    .d2t1   *B4++, A0
+||       mv     .s2x    A1, B5
+||       mv     .l2     B7, B6
+
+   [B0]  sub    .d2     B6, 24, B7
+|| [B0]  b      .s2     _strasgi_loop
+||       cmpltu .l2     B1, B6, B0
+
+   [B0]  ldw    .d2t1   *B4++, A1
+||       stw    .d1t2   B5, *A4++
+||       mv     .s2x    A5, B5
+||       cmpltu .l2     12, B6, B0
+
+   [B0]  ldw    .d2t1   *B4++, A5
+||       stw    .d1t2   B5, *A4++
+||       mv     .s2x    A7, B5
+||       cmpltu .l2     8, B6, B0
+
+   [B0]  ldw    .d2t1   *B4++, A7
+||       stw    .d1t2   B5, *A4++
+||       mv     .s2x    A8, B5
+||       cmpltu .l2     4, B6, B0
+
+   [B0]  ldw    .d2t1   *B4++, A8
+||       stw    .d1t2   B5, *A4++
+||       mv     .s2x    A9, B5
+||       cmpltu .l2     0, B6, B0
+
+   [B0]  ldw    .d2t1   *B4++, A9
+||       stw    .d1t2   B5, *A4++
+||       mv     .s2x    A0, B5
+||       cmpltu .l2     B2, B7, B0
+
+        ;; loop back branch happens here
+
+         cmpltu .l2     B1, B6, B0
+||       ret    .s2     b3
+
+   [B0]  stw    .d1t1   A1, *A4++
+||       cmpltu .l2     12, B6, B0
+   [B0]  stw    .d1t1   A5, *A4++
+||       cmpltu .l2     8, B6, B0
+   [B0]  stw    .d1t1   A7, *A4++
+||       cmpltu .l2     4, B6, B0
+   [B0]  stw    .d1t1   A8, *A4++
+||       cmpltu .l2     0, B6, B0
+   [B0]  stw    .d1t1   A9, *A4++
+
+        ;; return happens here
+ENDPROC(__c6xabi_strasgi)
diff --git a/arch/c6x/lib/strasgi_64plus.S b/arch/c6x/lib/strasgi_64plus.S
new file mode 100644
index 00000000000..c9fd159b5fa
--- /dev/null
+++ b/arch/c6x/lib/strasgi_64plus.S
@@ -0,0 +1,39 @@
+;;  Copyright 2010  Free Software Foundation, Inc.
+;;  Contributed by Bernd Schmidt <bernds@codesourcery.com>.
+;;
+;; This program is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2 of the License, or
+;; (at your option) any later version.
+;;
+;; This program is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with this program; if not, write to the Free Software
+;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+#include <linux/linkage.h>
+
+        .text
+
+ENTRY(__c6xabi_strasgi_64plus)
+        shru    .s2x    a6, 2, b31
+||      mv      .s1     a4, a30
+||      mv      .d2     b4, b30
+
+        add     .s2     -4, b31, b31
+
+        sploopd         1
+||      mvc     .s2     b31, ilc
+        ldw     .d2t2   *b30++, b31
+        nop     4
+        mv      .s1x    b31,a31
+        spkernel        6, 0
+||      stw     .d1t1   a31, *a30++
+
+        ret     .s2     b3
+        nop 5
+ENDPROC(__c6xabi_strasgi_64plus)
diff --git a/arch/c6x/mm/Makefile b/arch/c6x/mm/Makefile
new file mode 100644
index 00000000000..136a97576c6
--- /dev/null
+++ b/arch/c6x/mm/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the linux c6x-specific parts of the memory manager.
+#
+
+obj-y := init.o dma-coherent.o
diff --git a/arch/c6x/mm/dma-coherent.c b/arch/c6x/mm/dma-coherent.c
new file mode 100644
index 00000000000..4187e518037
--- /dev/null
+++ b/arch/c6x/mm/dma-coherent.c
@@ -0,0 +1,143 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot <aurelien.jacquiot@ti.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  DMA uncached mapping support.
+ *
+ *  Using code pulled from ARM
+ *  Copyright (C) 2000-2004 Russell King
+ *
+ */
+#include <linux/slab.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/memblock.h>
+
+#include <asm/page.h>
+
+/*
+ * DMA coherent memory management, can be redefined using the memdma=
+ * kernel command line
+ */
+
+/* none by default */
+static phys_addr_t dma_base;
+static u32 dma_size;
+static u32 dma_pages;
+
+static unsigned long *dma_bitmap;
+
+/* bitmap lock */
+static DEFINE_SPINLOCK(dma_lock);
+
+/*
+ * Return a DMA coherent and contiguous memory chunk from the DMA memory
+ */
+static inline u32 __alloc_dma_pages(int order)
+{
+        unsigned long flags;
+        u32 pos;
+
+        spin_lock_irqsave(&dma_lock, flags);
+        pos = bitmap_find_free_region(dma_bitmap, dma_pages, order);
+        spin_unlock_irqrestore(&dma_lock, flags);
+
+        return dma_base + (pos << PAGE_SHIFT);
+}
+
+static void __free_dma_pages(u32 addr, int order)
+{
+        unsigned long flags;
+        u32 pos = (addr - dma_base) >> PAGE_SHIFT;
+
+        if (addr < dma_base || (pos + (1 << order)) >= dma_pages) {
+                printk(KERN_ERR "%s: freeing outside range.\n", __func__);
+                BUG();
+        }
+
+        spin_lock_irqsave(&dma_lock, flags);
+        bitmap_release_region(dma_bitmap, pos, order);
+        spin_unlock_irqrestore(&dma_lock, flags);
+}
+
+/*
+ * Allocate DMA coherent memory space and return both the kernel
+ * virtual and DMA address for that space.
+ */
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                         dma_addr_t *handle, gfp_t gfp)
+{
+        u32 paddr;
+        int order;
+
+        if (!dma_size || !size)
+                return NULL;
+
+        order = get_count_order(((size - 1) >> PAGE_SHIFT) + 1);
+
+        paddr = __alloc_dma_pages(order);
+
+        if (handle)
+                *handle = paddr;
+
+        if (!paddr)
+                return NULL;
+
+        return phys_to_virt(paddr);
+}
+EXPORT_SYMBOL(dma_alloc_coherent);
+
+/*
+ * Free DMA coherent memory as defined by the above mapping.
+ */
+void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+                       dma_addr_t dma_handle)
+{
+        int order;
+
+        if (!dma_size || !size)
+                return;
+
+        order = get_count_order(((size - 1) >> PAGE_SHIFT) + 1);
+
+        __free_dma_pages(virt_to_phys(vaddr), order);
+}
+EXPORT_SYMBOL(dma_free_coherent);
+
+/*
+ * Initialise the coherent DMA memory allocator using the given uncached region.
+ */
+void __init coherent_mem_init(phys_addr_t start, u32 size)
+{
+        phys_addr_t bitmap_phys;
+
+        if (!size)
+                return;
+
+        printk(KERN_INFO
+               "Coherent memory (DMA) region start=0x%x size=0x%x\n",
+               start, size);
+
+        dma_base = start;
+        dma_size = size;
+
+        /* allocate bitmap */
+        dma_pages = dma_size >> PAGE_SHIFT;
+        if (dma_size & (PAGE_SIZE - 1))
+                ++dma_pages;
+
+        bitmap_phys = memblock_alloc(BITS_TO_LONGS(dma_pages) * sizeof(long),
+                                     sizeof(long));
+
+        dma_bitmap = phys_to_virt(bitmap_phys);
+        memset(dma_bitmap, 0, dma_pages * PAGE_SIZE);
+}
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
new file mode 100644
index 00000000000..89395f09648
--- /dev/null
+++ b/arch/c6x/mm/init.c
@@ -0,0 +1,113 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
+ *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/module.h>
+#include <linux/bootmem.h>
+#ifdef CONFIG_BLK_DEV_RAM
+#include <linux/blkdev.h>
+#endif
+#include <linux/initrd.h>
+
+#include <asm/sections.h>
+
+/*
+ * ZERO_PAGE is a special page that is used for zero-initialized
+ * data and COW.
+ */
+unsigned long empty_zero_page;
+EXPORT_SYMBOL(empty_zero_page);
+
+/*
+ * paging_init() continues the virtual memory environment setup which
+ * was begun by the code in arch/head.S.
+ * The parameters are pointers to where to stick the starting and ending
+ * addresses  of available kernel virtual memory.
+ */
+void __init paging_init(void)
+{
+        struct pglist_data *pgdat = NODE_DATA(0);
+        unsigned long zones_size[MAX_NR_ZONES] = {0, };
+
+        empty_zero_page      = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
+        memset((void *)empty_zero_page, 0, PAGE_SIZE);
+
+        /*
+         * Set up user data space
+         */
+        set_fs(KERNEL_DS);
+
+        /*
+         * Define zones
+         */
+        zones_size[ZONE_NORMAL] = (memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
+        pgdat->node_zones[ZONE_NORMAL].zone_start_pfn =
+                __pa(PAGE_OFFSET) >> PAGE_SHIFT;
+
+        free_area_init(zones_size);
+}
+
+void __init mem_init(void)
+{
+        int codek, datak;
+        unsigned long tmp;
+        unsigned long len = memory_end - memory_start;
+
+        high_memory = (void *)(memory_end & PAGE_MASK);
+
+        /* this will put all memory onto the freelists */
+        totalram_pages = free_all_bootmem();
+
+        codek = (_etext - _stext) >> 10;
+        datak = (_end - _sdata) >> 10;
+
+        tmp = nr_free_pages() << PAGE_SHIFT;
+        printk(KERN_INFO "Memory: %luk/%luk RAM (%dk kernel code, %dk data)\n",
+               tmp >> 10, len >> 10, codek, datak);
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+void __init free_initrd_mem(unsigned long start, unsigned long end)
+{
+        int pages = 0;
+        for (; start < end; start += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(start));
+                init_page_count(virt_to_page(start));
+                free_page(start);
+                totalram_pages++;
+                pages++;
+        }
+        printk(KERN_INFO "Freeing initrd memory: %luk freed\n",
+               (pages * PAGE_SIZE) >> 10);
+}
+#endif
+
+void __init free_initmem(void)
+{
+        unsigned long addr;
+
+        /*
+         * The following code should be cool even if these sections
+         * are not page aligned.
+         */
+        addr = PAGE_ALIGN((unsigned long)(__init_begin));
+
+        /* next to check that the page we free is not a partial page */
+        for (; addr + PAGE_SIZE < (unsigned long)(__init_end);
+             addr += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(addr));
+                init_page_count(virt_to_page(addr));
+                free_page(addr);
+                totalram_pages++;
+        }
+        printk(KERN_INFO "Freeing unused kernel memory: %dK freed\n",
+               (int) ((addr - PAGE_ALIGN((long) &__init_begin)) >> 10));
+}
diff --git a/arch/c6x/platforms/Kconfig b/arch/c6x/platforms/Kconfig
new file mode 100644
index 00000000000..401ee678fd0
--- /dev/null
+++ b/arch/c6x/platforms/Kconfig
@@ -0,0 +1,16 @@
+
+config SOC_TMS320C6455
+        bool "TMS320C6455"
+        default n
+
+config SOC_TMS320C6457
+        bool "TMS320C6457"
+        default n
+
+config SOC_TMS320C6472
+        bool "TMS320C6472"
+        default n
+
+config SOC_TMS320C6474
+        bool "TMS320C6474"
+        default n
diff --git a/arch/c6x/platforms/Makefile b/arch/c6x/platforms/Makefile
new file mode 100644
index 00000000000..9a95b9bca8d
--- /dev/null
+++ b/arch/c6x/platforms/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for arch/c6x/platforms
+#
+# Copyright 2010, 2011 Texas Instruments Incorporated
+#
+
+obj-y = platform.o cache.o megamod-pic.o pll.o plldata.o timer64.o
+obj-y += dscr.o
+
+# SoC objects
+obj-$(CONFIG_SOC_TMS320C6455)   += emif.o
+obj-$(CONFIG_SOC_TMS320C6457)   += emif.o
diff --git a/arch/c6x/platforms/cache.c b/arch/c6x/platforms/cache.c
new file mode 100644
index 00000000000..86318a16a25
--- /dev/null
+++ b/arch/c6x/platforms/cache.c
@@ -0,0 +1,445 @@
+/*
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#include <asm/cache.h>
+#include <asm/soc.h>
+
+/*
+ * Internal Memory Control Registers for caches
+ */
+#define IMCR_CCFG         0x0000
+#define IMCR_L1PCFG       0x0020
+#define IMCR_L1PCC        0x0024
+#define IMCR_L1DCFG       0x0040
+#define IMCR_L1DCC        0x0044
+#define IMCR_L2ALLOC0     0x2000
+#define IMCR_L2ALLOC1     0x2004
+#define IMCR_L2ALLOC2     0x2008
+#define IMCR_L2ALLOC3     0x200c
+#define IMCR_L2WBAR       0x4000
+#define IMCR_L2WWC        0x4004
+#define IMCR_L2WIBAR      0x4010
+#define IMCR_L2WIWC       0x4014
+#define IMCR_L2IBAR       0x4018
+#define IMCR_L2IWC        0x401c
+#define IMCR_L1PIBAR      0x4020
+#define IMCR_L1PIWC       0x4024
+#define IMCR_L1DWIBAR     0x4030
+#define IMCR_L1DWIWC      0x4034
+#define IMCR_L1DWBAR      0x4040
+#define IMCR_L1DWWC       0x4044
+#define IMCR_L1DIBAR      0x4048
+#define IMCR_L1DIWC       0x404c
+#define IMCR_L2WB         0x5000
+#define IMCR_L2WBINV      0x5004
+#define IMCR_L2INV        0x5008
+#define IMCR_L1PINV       0x5028
+#define IMCR_L1DWB        0x5040
+#define IMCR_L1DWBINV     0x5044
+#define IMCR_L1DINV       0x5048
+#define IMCR_MAR_BASE     0x8000
+#define IMCR_MAR96_111    0x8180
+#define IMCR_MAR128_191   0x8200
+#define IMCR_MAR224_239   0x8380
+#define IMCR_L2MPFAR      0xa000
+#define IMCR_L2MPFSR      0xa004
+#define IMCR_L2MPFCR      0xa008
+#define IMCR_L2MPLK0      0xa100
+#define IMCR_L2MPLK1      0xa104
+#define IMCR_L2MPLK2      0xa108
+#define IMCR_L2MPLK3      0xa10c
+#define IMCR_L2MPLKCMD    0xa110
+#define IMCR_L2MPLKSTAT   0xa114
+#define IMCR_L2MPPA_BASE  0xa200
+#define IMCR_L1PMPFAR     0xa400
+#define IMCR_L1PMPFSR     0xa404
+#define IMCR_L1PMPFCR     0xa408
+#define IMCR_L1PMPLK0     0xa500
+#define IMCR_L1PMPLK1     0xa504
+#define IMCR_L1PMPLK2     0xa508
+#define IMCR_L1PMPLK3     0xa50c
+#define IMCR_L1PMPLKCMD   0xa510
+#define IMCR_L1PMPLKSTAT  0xa514
+#define IMCR_L1PMPPA_BASE 0xa600
+#define IMCR_L1DMPFAR     0xac00
+#define IMCR_L1DMPFSR     0xac04
+#define IMCR_L1DMPFCR     0xac08
+#define IMCR_L1DMPLK0     0xad00
+#define IMCR_L1DMPLK1     0xad04
+#define IMCR_L1DMPLK2     0xad08
+#define IMCR_L1DMPLK3     0xad0c
+#define IMCR_L1DMPLKCMD   0xad10
+#define IMCR_L1DMPLKSTAT  0xad14
+#define IMCR_L1DMPPA_BASE 0xae00
+#define IMCR_L2PDWAKE0    0xc040
+#define IMCR_L2PDWAKE1    0xc044
+#define IMCR_L2PDSLEEP0   0xc050
+#define IMCR_L2PDSLEEP1   0xc054
+#define IMCR_L2PDSTAT0    0xc060
+#define IMCR_L2PDSTAT1    0xc064
+
+/*
+ * CCFG register values and bits
+ */
+#define L2MODE_0K_CACHE   0x0
+#define L2MODE_32K_CACHE  0x1
+#define L2MODE_64K_CACHE  0x2
+#define L2MODE_128K_CACHE 0x3
+#define L2MODE_256K_CACHE 0x7
+
+#define L2PRIO_URGENT     0x0
+#define L2PRIO_HIGH       0x1
+#define L2PRIO_MEDIUM     0x2
+#define L2PRIO_LOW        0x3
+
+#define CCFG_ID           0x100   /* Invalidate L1P bit */
+#define CCFG_IP           0x200   /* Invalidate L1D bit */
+
+static void __iomem *cache_base;
+
+/*
+ * L1 & L2 caches generic functions
+ */
+#define imcr_get(reg) soc_readl(cache_base + (reg))
+#define imcr_set(reg, value) \
+do {                                                            \
+        soc_writel((value), cache_base + (reg));                \
+        soc_readl(cache_base + (reg));                          \
+} while (0)
+
+static void cache_block_operation_wait(unsigned int wc_reg)
+{
+        /* Wait for completion */
+        while (imcr_get(wc_reg))
+                cpu_relax();
+}
+
+static DEFINE_SPINLOCK(cache_lock);
+
+/*
+ * Generic function to perform a block cache operation as
+ * invalidate or writeback/invalidate
+ */
+static void cache_block_operation(unsigned int *start,
+                                  unsigned int *end,
+                                  unsigned int bar_reg,
+                                  unsigned int wc_reg)
+{
+        unsigned long flags;
+        unsigned int wcnt =
+                (L2_CACHE_ALIGN_CNT((unsigned int) end)
+                 - L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
+        unsigned int wc = 0;
+
+        for (; wcnt; wcnt -= wc, start += wc) {
+loop:
+                spin_lock_irqsave(&cache_lock, flags);
+
+                /*
+                 * If another cache operation is occuring
+                 */
+                if (unlikely(imcr_get(wc_reg))) {
+                        spin_unlock_irqrestore(&cache_lock, flags);
+
+                        /* Wait for previous operation completion */
+                        cache_block_operation_wait(wc_reg);
+
+                        /* Try again */
+                        goto loop;
+                }
+
+                imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
+
+                if (wcnt > 0xffff)
+                        wc = 0xffff;
+                else
+                        wc = wcnt;
+
+                /* Set word count value in the WC register */
+                imcr_set(wc_reg, wc & 0xffff);
+
+                spin_unlock_irqrestore(&cache_lock, flags);
+
+                /* Wait for completion */
+                cache_block_operation_wait(wc_reg);
+        }
+}
+
+static void cache_block_operation_nowait(unsigned int *start,
+                                         unsigned int *end,
+                                         unsigned int bar_reg,
+                                         unsigned int wc_reg)
+{
+        unsigned long flags;
+        unsigned int wcnt =
+                (L2_CACHE_ALIGN_CNT((unsigned int) end)
+                 - L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
+        unsigned int wc = 0;
+
+        for (; wcnt; wcnt -= wc, start += wc) {
+
+                spin_lock_irqsave(&cache_lock, flags);
+
+                imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
+
+                if (wcnt > 0xffff)
+                        wc = 0xffff;
+                else
+                        wc = wcnt;
+
+                /* Set word count value in the WC register */
+                imcr_set(wc_reg, wc & 0xffff);
+
+                spin_unlock_irqrestore(&cache_lock, flags);
+
+                /* Don't wait for completion on last cache operation */
+                if (wcnt > 0xffff)
+                        cache_block_operation_wait(wc_reg);
+        }
+}
+
+/*
+ * L1 caches management
+ */
+
+/*
+ * Disable L1 caches
+ */
+void L1_cache_off(void)
+{
+        unsigned int dummy;
+
+        imcr_set(IMCR_L1PCFG, 0);
+        dummy = imcr_get(IMCR_L1PCFG);
+
+        imcr_set(IMCR_L1DCFG, 0);
+        dummy = imcr_get(IMCR_L1DCFG);
+}
+
+/*
+ * Enable L1 caches
+ */
+void L1_cache_on(void)
+{
+        unsigned int dummy;
+
+        imcr_set(IMCR_L1PCFG, 7);
+        dummy = imcr_get(IMCR_L1PCFG);
+
+        imcr_set(IMCR_L1DCFG, 7);
+        dummy = imcr_get(IMCR_L1DCFG);
+}
+
+/*
+ *  L1P global-invalidate all
+ */
+void L1P_cache_global_invalidate(void)
+{
+        unsigned int set = 1;
+        imcr_set(IMCR_L1PINV, set);
+        while (imcr_get(IMCR_L1PINV) & 1)
+                cpu_relax();
+}
+
+/*
+ *  L1D global-invalidate all
+ *
+ * Warning: this operation causes all updated data in L1D to
+ * be discarded rather than written back to the lower levels of
+ * memory
+ */
+void L1D_cache_global_invalidate(void)
+{
+        unsigned int set = 1;
+        imcr_set(IMCR_L1DINV, set);
+        while (imcr_get(IMCR_L1DINV) & 1)
+                cpu_relax();
+}
+
+void L1D_cache_global_writeback(void)
+{
+        unsigned int set = 1;
+        imcr_set(IMCR_L1DWB, set);
+        while (imcr_get(IMCR_L1DWB) & 1)
+                cpu_relax();
+}
+
+void L1D_cache_global_writeback_invalidate(void)
+{
+        unsigned int set = 1;
+        imcr_set(IMCR_L1DWBINV, set);
+        while (imcr_get(IMCR_L1DWBINV) & 1)
+                cpu_relax();
+}
+
+/*
+ * L2 caches management
+ */
+
+/*
+ * Set L2 operation mode
+ */
+void L2_cache_set_mode(unsigned int mode)
+{
+        unsigned int ccfg = imcr_get(IMCR_CCFG);
+
+        /* Clear and set the L2MODE bits in CCFG */
+        ccfg &= ~7;
+        ccfg |= (mode & 7);
+        imcr_set(IMCR_CCFG, ccfg);
+        ccfg = imcr_get(IMCR_CCFG);
+}
+
+/*
+ *  L2 global-writeback and global-invalidate all
+ */
+void L2_cache_global_writeback_invalidate(void)
+{
+        imcr_set(IMCR_L2WBINV, 1);
+        while (imcr_get(IMCR_L2WBINV))
+                cpu_relax();
+}
+
+/*
+ *  L2 global-writeback all
+ */
+void L2_cache_global_writeback(void)
+{
+        imcr_set(IMCR_L2WB, 1);
+        while (imcr_get(IMCR_L2WB))
+                cpu_relax();
+}
+
+/*
+ * Cacheability controls
+ */
+void enable_caching(unsigned long start, unsigned long end)
+{
+        unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
+        unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
+
+        for (; mar <= mar_e; mar += 4)
+                imcr_set(mar, imcr_get(mar) | 1);
+}
+
+void disable_caching(unsigned long start, unsigned long end)
+{
+        unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
+        unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
+
+        for (; mar <= mar_e; mar += 4)
+                imcr_set(mar, imcr_get(mar) & ~1);
+}
+
+
+/*
+ *  L1 block operations
+ */
+void L1P_cache_block_invalidate(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L1PIBAR, IMCR_L1PIWC);
+}
+
+void L1D_cache_block_invalidate(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L1DIBAR, IMCR_L1DIWC);
+}
+
+void L1D_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L1DWIBAR, IMCR_L1DWIWC);
+}
+
+void L1D_cache_block_writeback(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L1DWBAR, IMCR_L1DWWC);
+}
+
+/*
+ *  L2 block operations
+ */
+void L2_cache_block_invalidate(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L2IBAR, IMCR_L2IWC);
+}
+
+void L2_cache_block_writeback(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L2WBAR, IMCR_L2WWC);
+}
+
+void L2_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
+{
+        cache_block_operation((unsigned int *) start,
+                              (unsigned int *) end,
+                              IMCR_L2WIBAR, IMCR_L2WIWC);
+}
+
+void L2_cache_block_invalidate_nowait(unsigned int start, unsigned int end)
+{
+        cache_block_operation_nowait((unsigned int *) start,
+                                     (unsigned int *) end,
+                                     IMCR_L2IBAR, IMCR_L2IWC);
+}
+
+void L2_cache_block_writeback_nowait(unsigned int start, unsigned int end)
+{
+        cache_block_operation_nowait((unsigned int *) start,
+                                     (unsigned int *) end,
+                                     IMCR_L2WBAR, IMCR_L2WWC);
+}
+
+void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
+                                                unsigned int end)
+{
+        cache_block_operation_nowait((unsigned int *) start,
+                                     (unsigned int *) end,
+                                     IMCR_L2WIBAR, IMCR_L2WIWC);
+}
+
+
+/*
+ * L1 and L2 caches configuration
+ */
+void __init c6x_cache_init(void)
+{
+        struct device_node *node;
+
+        node = of_find_compatible_node(NULL, NULL, "ti,c64x+cache");
+        if (!node)
+                return;
+
+        cache_base = of_iomap(node, 0);
+
+        of_node_put(node);
+
+        if (!cache_base)
+                return;
+
+        /* Set L2 caches on the the whole L2 SRAM memory */
+        L2_cache_set_mode(L2MODE_SIZE);
+
+        /* Enable L1 */
+        L1_cache_on();
+}
diff --git a/arch/c6x/platforms/dscr.c b/arch/c6x/platforms/dscr.c
new file mode 100644
index 00000000000..f848a65ee64
--- /dev/null
+++ b/arch/c6x/platforms/dscr.c
@@ -0,0 +1,598 @@
+/*
+ *  Device State Control Registers driver
+ *
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+/*
+ * The Device State Control Registers (DSCR) provide SoC level control over
+ * a number of peripherals. Details vary considerably among the various SoC
+ * parts. In general, the DSCR block will provide one or more configuration
+ * registers often protected by a lock register. One or more key values must
+ * be written to a lock register in order to unlock the configuration register.
+ * The configuration register may be used to enable (and disable in some
+ * cases) SoC pin drivers, peripheral clock sources (internal or pin), etc.
+ * In some cases, a configuration register is write once or the individual
+ * bits are write once. That is, you may be able to enable a device, but
+ * will not be able to disable it.
+ *
+ * In addition to device configuration, the DSCR block may provide registers
+ * which are used to reset SoC peripherals, provide device ID information,
+ * provide MAC addresses, and other miscellaneous functions.
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <asm/soc.h>
+#include <asm/dscr.h>
+
+#define MAX_DEVSTATE_IDS   32
+#define MAX_DEVCTL_REGS     8
+#define MAX_DEVSTAT_REGS    8
+#define MAX_LOCKED_REGS     4
+#define MAX_SOC_EMACS       2
+
+struct rmii_reset_reg {
+        u32 reg;
+        u32 mask;
+};
+
+/*
+ * Some registerd may be locked. In order to write to these
+ * registers, the key value must first be written to the lockreg.
+ */
+struct locked_reg {
+        u32 reg;        /* offset from base */
+        u32 lockreg;    /* offset from base */
+        u32 key;        /* unlock key */
+};
+
+/*
+ * This describes a contiguous area of like control bits used to enable/disable
+ * SoC devices. Each controllable device is given an ID which is used by the
+ * individual device drivers to control the device state. These IDs start at
+ * zero and are assigned sequentially to the control bitfield ranges described
+ * by this structure.
+ */
+struct devstate_ctl_reg {
+        u32 reg;                /* register holding the control bits */
+        u8  start_id;           /* start id of this range */
+        u8  num_ids;            /* number of devices in this range */
+        u8  enable_only;        /* bits are write-once to enable only */
+        u8  enable;             /* value used to enable device */
+        u8  disable;            /* value used to disable device */
+        u8  shift;              /* starting (rightmost) bit in range */
+        u8  nbits;              /* number of bits per device */
+};
+
+
+/*
+ * This describes a region of status bits indicating the state of
+ * various devices. This is used internally to wait for status
+ * change completion when enabling/disabling a device. Status is
+ * optional and not all device controls will have a corresponding
+ * status.
+ */
+struct devstate_stat_reg {
+        u32 reg;                /* register holding the status bits */
+        u8  start_id;           /* start id of this range */
+        u8  num_ids;            /* number of devices in this range */
+        u8  enable;             /* value indicating enabled state */
+        u8  disable;            /* value indicating disabled state */
+        u8  shift;              /* starting (rightmost) bit in range */
+        u8  nbits;              /* number of bits per device */
+};
+
+struct devstate_info {
+        struct devstate_ctl_reg *ctl;
+        struct devstate_stat_reg *stat;
+};
+
+/* These are callbacks to SOC-specific code. */
+struct dscr_ops {
+        void (*init)(struct device_node *node);
+};
+
+struct dscr_regs {
+        spinlock_t              lock;
+        void __iomem            *base;
+        u32                     kick_reg[2];
+        u32                     kick_key[2];
+        struct locked_reg       locked[MAX_LOCKED_REGS];
+        struct devstate_info    devstate_info[MAX_DEVSTATE_IDS];
+        struct rmii_reset_reg   rmii_resets[MAX_SOC_EMACS];
+        struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS];
+        struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS];
+};
+
+static struct dscr_regs dscr;
+
+static struct locked_reg *find_locked_reg(u32 reg)
+{
+        int i;
+
+        for (i = 0; i < MAX_LOCKED_REGS; i++)
+                if (dscr.locked[i].key && reg == dscr.locked[i].reg)
+                        return &dscr.locked[i];
+        return NULL;
+}
+
+/*
+ * Write to a register with one lock
+ */
+static void dscr_write_locked1(u32 reg, u32 val,
+                               u32 lock, u32 key)
+{
+        void __iomem *reg_addr = dscr.base + reg;
+        void __iomem *lock_addr = dscr.base + lock;
+
+        /*
+         * For some registers, the lock is relocked after a short number
+         * of cycles. We have to put the lock write and register write in
+         * the same fetch packet to meet this timing. The .align ensures
+         * the two stw instructions are in the same fetch packet.
+         */
+        asm volatile ("b        .s2     0f\n"
+                      "nop      5\n"
+                      "    .align 5\n"
+                      "0:\n"
+                      "stw      .D1T2   %3,*%2\n"
+                      "stw      .D1T2   %1,*%0\n"
+                      :
+                      : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
+                );
+
+        /* in case the hw doesn't reset the lock */
+        soc_writel(0, lock_addr);
+}
+
+/*
+ * Write to a register protected by two lock registers
+ */
+static void dscr_write_locked2(u32 reg, u32 val,
+                               u32 lock0, u32 key0,
+                               u32 lock1, u32 key1)
+{
+        soc_writel(key0, dscr.base + lock0);
+        soc_writel(key1, dscr.base + lock1);
+        soc_writel(val, dscr.base + reg);
+        soc_writel(0, dscr.base + lock0);
+        soc_writel(0, dscr.base + lock1);
+}
+
+static void dscr_write(u32 reg, u32 val)
+{
+        struct locked_reg *lock;
+
+        lock = find_locked_reg(reg);
+        if (lock)
+                dscr_write_locked1(reg, val, lock->lockreg, lock->key);
+        else if (dscr.kick_key[0])
+                dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0],
+                                   dscr.kick_reg[1], dscr.kick_key[1]);
+        else
+                soc_writel(val, dscr.base + reg);
+}
+
+
+/*
+ * Drivers can use this interface to enable/disable SoC IP blocks.
+ */
+void dscr_set_devstate(int id, enum dscr_devstate_t state)
+{
+        struct devstate_ctl_reg *ctl;
+        struct devstate_stat_reg *stat;
+        struct devstate_info *info;
+        u32 ctl_val, val;
+        int ctl_shift, ctl_mask;
+        unsigned long flags;
+
+        if (!dscr.base)
+                return;
+
+        if (id < 0 || id >= MAX_DEVSTATE_IDS)
+                return;
+
+        info = &dscr.devstate_info[id];
+        ctl = info->ctl;
+        stat = info->stat;
+
+        if (ctl == NULL)
+                return;
+
+        ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);
+        ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;
+
+        switch (state) {
+        case DSCR_DEVSTATE_ENABLED:
+                ctl_val = ctl->enable << ctl_shift;
+                break;
+        case DSCR_DEVSTATE_DISABLED:
+                if (ctl->enable_only)
+                        return;
+                ctl_val = ctl->disable << ctl_shift;
+                break;
+        default:
+                return;
+        }
+
+        spin_lock_irqsave(&dscr.lock, flags);
+
+        val = soc_readl(dscr.base + ctl->reg);
+        val &= ~ctl_mask;
+        val |= ctl_val;
+
+        dscr_write(ctl->reg, val);
+
+        spin_unlock_irqrestore(&dscr.lock, flags);
+
+        if (!stat)
+                return;
+
+        ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);
+
+        if (state == DSCR_DEVSTATE_ENABLED)
+                ctl_val = stat->enable;
+        else
+                ctl_val = stat->disable;
+
+        do {
+                val = soc_readl(dscr.base + stat->reg);
+                val >>= ctl_shift;
+                val &= ((1 << stat->nbits) - 1);
+        } while (val != ctl_val);
+}
+EXPORT_SYMBOL(dscr_set_devstate);
+
+/*
+ * Drivers can use this to reset RMII module.
+ */
+void dscr_rmii_reset(int id, int assert)
+{
+        struct rmii_reset_reg *r;
+        unsigned long flags;
+        u32 val;
+
+        if (id < 0 || id >= MAX_SOC_EMACS)
+                return;
+
+        r = &dscr.rmii_resets[id];
+        if (r->mask == 0)
+                return;
+
+        spin_lock_irqsave(&dscr.lock, flags);
+
+        val = soc_readl(dscr.base + r->reg);
+        if (assert)
+                dscr_write(r->reg, val | r->mask);
+        else
+                dscr_write(r->reg, val & ~(r->mask));
+
+        spin_unlock_irqrestore(&dscr.lock, flags);
+}
+EXPORT_SYMBOL(dscr_rmii_reset);
+
+static void __init dscr_parse_devstat(struct device_node *node,
+                                      void __iomem *base)
+{
+        u32 val;
+        int err;
+
+        err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1);
+        if (!err)
+                c6x_devstat = soc_readl(base + val);
+        printk(KERN_INFO "DEVSTAT: %08x\n", c6x_devstat);
+}
+
+static void __init dscr_parse_silicon_rev(struct device_node *node,
+                                         void __iomem *base)
+{
+        u32 vals[3];
+        int err;
+
+        err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3);
+        if (!err) {
+                c6x_silicon_rev = soc_readl(base + vals[0]);
+                c6x_silicon_rev >>= vals[1];
+                c6x_silicon_rev &= vals[2];
+        }
+}
+
+/*
+ * Some SoCs will have a pair of fuse registers which hold
+ * an ethernet MAC address. The "ti,dscr-mac-fuse-regs"
+ * property is a mapping from fuse register bytes to MAC
+ * address bytes. The expected format is:
+ *
+ *      ti,dscr-mac-fuse-regs = <reg0 b3 b2 b1 b0
+ *                               reg1 b3 b2 b1 b0>
+ *
+ * reg0 and reg1 are the offsets of the two fuse registers.
+ * b3-b0 positionally represent bytes within the fuse register.
+ * b3 is the most significant byte and b0 is the least.
+ * Allowable values for b3-b0 are:
+ *
+ *        0 = fuse register byte not used in MAC address
+ *      1-6 = index+1 into c6x_fuse_mac[]
+ */
+static void __init dscr_parse_mac_fuse(struct device_node *node,
+                                       void __iomem *base)
+{
+        u32 vals[10], fuse;
+        int f, i, j, err;
+
+        err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs",
+                                         vals, 10);
+        if (err)
+                return;
+
+        for (f = 0; f < 2; f++) {
+                fuse = soc_readl(base + vals[f * 5]);
+                for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++)
+                        if (vals[j] && vals[j] <= 6)
+                                c6x_fuse_mac[vals[j] - 1] = fuse >> i;
+        }
+}
+
+static void __init dscr_parse_rmii_resets(struct device_node *node,
+                                          void __iomem *base)
+{
+        const __be32 *p;
+        int i, size;
+
+        /* look for RMII reset registers */
+        p = of_get_property(node, "ti,dscr-rmii-resets", &size);
+        if (p) {
+                /* parse all the reg/mask pairs we can handle */
+                size /= (sizeof(*p) * 2);
+                if (size > MAX_SOC_EMACS)
+                        size = MAX_SOC_EMACS;
+
+                for (i = 0; i < size; i++) {
+                        dscr.rmii_resets[i].reg = be32_to_cpup(p++);
+                        dscr.rmii_resets[i].mask = be32_to_cpup(p++);
+                }
+        }
+}
+
+
+static void __init dscr_parse_privperm(struct device_node *node,
+                                       void __iomem *base)
+{
+        u32 vals[2];
+        int err;
+
+        err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2);
+        if (err)
+                return;
+        dscr_write(vals[0], vals[1]);
+}
+
+/*
+ * SoCs may have "locked" DSCR registers which can only be written
+ * to only after writing a key value to a lock registers. These
+ * regisers can be described with the "ti,dscr-locked-regs" property.
+ * This property provides a list of register descriptions with each
+ * description consisting of three values.
+ *
+ *      ti,dscr-locked-regs = <reg0 lockreg0 key0
+ *                               ...
+ *                             regN lockregN keyN>;
+ *
+ * reg is the offset of the locked register
+ * lockreg is the offset of the lock register
+ * key is the unlock key written to lockreg
+ *
+ */
+static void __init dscr_parse_locked_regs(struct device_node *node,
+                                          void __iomem *base)
+{
+        struct locked_reg *r;
+        const __be32 *p;
+        int i, size;
+
+        p = of_get_property(node, "ti,dscr-locked-regs", &size);
+        if (p) {
+                /* parse all the register descriptions we can handle */
+                size /= (sizeof(*p) * 3);
+                if (size > MAX_LOCKED_REGS)
+                        size = MAX_LOCKED_REGS;
+
+                for (i = 0; i < size; i++) {
+                        r = &dscr.locked[i];
+
+                        r->reg = be32_to_cpup(p++);
+                        r->lockreg = be32_to_cpup(p++);
+                        r->key = be32_to_cpup(p++);
+                }
+        }
+}
+
+/*
+ * SoCs may have DSCR registers which are only write enabled after
+ * writing specific key values to two registers. The two key registers
+ * and the key values can be parsed from a "ti,dscr-kick-regs"
+ * propety with the following layout:
+ *
+ *      ti,dscr-kick-regs = <kickreg0 key0 kickreg1 key1>
+ *
+ * kickreg is the offset of the "kick" register
+ * key is the value which unlocks writing for protected regs
+ */
+static void __init dscr_parse_kick_regs(struct device_node *node,
+                                        void __iomem *base)
+{
+        u32 vals[4];
+        int err;
+
+        err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4);
+        if (!err) {
+                dscr.kick_reg[0] = vals[0];
+                dscr.kick_key[0] = vals[1];
+                dscr.kick_reg[1] = vals[2];
+                dscr.kick_key[1] = vals[3];
+        }
+}
+
+
+/*
+ * SoCs may provide controls to enable/disable individual IP blocks. These
+ * controls in the DSCR usually control pin drivers but also may control
+ * clocking and or resets. The device tree is used to describe the bitfields
+ * in registers used to control device state. The number of bits and their
+ * values may vary even within the same register.
+ *
+ * The layout of these bitfields is described by the ti,dscr-devstate-ctl-regs
+ * property. This property is a list where each element describes a contiguous
+ * range of control fields with like properties. Each element of the list
+ * consists of 7 cells with the following values:
+ *
+ *   start_id num_ids reg enable disable start_bit nbits
+ *
+ * start_id is device id for the first device control in the range
+ * num_ids is the number of device controls in the range
+ * reg is the offset of the register holding the control bits
+ * enable is the value to enable a device
+ * disable is the value to disable a device (0xffffffff if cannot disable)
+ * start_bit is the bit number of the first bit in the range
+ * nbits is the number of bits per device control
+ */
+static void __init dscr_parse_devstate_ctl_regs(struct device_node *node,
+                                                void __iomem *base)
+{
+        struct devstate_ctl_reg *r;
+        const __be32 *p;
+        int i, j, size;
+
+        p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size);
+        if (p) {
+                /* parse all the ranges we can handle */
+                size /= (sizeof(*p) * 7);
+                if (size > MAX_DEVCTL_REGS)
+                        size = MAX_DEVCTL_REGS;
+
+                for (i = 0; i < size; i++) {
+                        r = &dscr.devctl[i];
+
+                        r->start_id = be32_to_cpup(p++);
+                        r->num_ids = be32_to_cpup(p++);
+                        r->reg = be32_to_cpup(p++);
+                        r->enable = be32_to_cpup(p++);
+                        r->disable = be32_to_cpup(p++);
+                        if (r->disable == 0xffffffff)
+                                r->enable_only = 1;
+                        r->shift = be32_to_cpup(p++);
+                        r->nbits = be32_to_cpup(p++);
+
+                        for (j = r->start_id;
+                             j < (r->start_id + r->num_ids);
+                             j++)
+                                dscr.devstate_info[j].ctl = r;
+                }
+        }
+}
+
+/*
+ * SoCs may provide status registers indicating the state (enabled/disabled) of
+ * devices on the SoC. The device tree is used to describe the bitfields in
+ * registers used to provide device status. The number of bits and their
+ * values used to provide status may vary even within the same register.
+ *
+ * The layout of these bitfields is described by the ti,dscr-devstate-stat-regs
+ * property. This property is a list where each element describes a contiguous
+ * range of status fields with like properties. Each element of the list
+ * consists of 7 cells with the following values:
+ *
+ *   start_id num_ids reg enable disable start_bit nbits
+ *
+ * start_id is device id for the first device status in the range
+ * num_ids is the number of devices covered by the range
+ * reg is the offset of the register holding the status bits
+ * enable is the value indicating device is enabled
+ * disable is the value indicating device is disabled
+ * start_bit is the bit number of the first bit in the range
+ * nbits is the number of bits per device status
+ */
+static void __init dscr_parse_devstate_stat_regs(struct device_node *node,
+                                                 void __iomem *base)
+{
+        struct devstate_stat_reg *r;
+        const __be32 *p;
+        int i, j, size;
+
+        p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size);
+        if (p) {
+                /* parse all the ranges we can handle */
+                size /= (sizeof(*p) * 7);
+                if (size > MAX_DEVSTAT_REGS)
+                        size = MAX_DEVSTAT_REGS;
+
+                for (i = 0; i < size; i++) {
+                        r = &dscr.devstat[i];
+
+                        r->start_id = be32_to_cpup(p++);
+                        r->num_ids = be32_to_cpup(p++);
+                        r->reg = be32_to_cpup(p++);
+                        r->enable = be32_to_cpup(p++);
+                        r->disable = be32_to_cpup(p++);
+                        r->shift = be32_to_cpup(p++);
+                        r->nbits = be32_to_cpup(p++);
+
+                        for (j = r->start_id;
+                             j < (r->start_id + r->num_ids);
+                             j++)
+                                dscr.devstate_info[j].stat = r;
+                }
+        }
+}
+
+static struct of_device_id dscr_ids[] __initdata = {
+        { .compatible = "ti,c64x+dscr" },
+        {}
+};
+
+/*
+ * Probe for DSCR area.
+ *
+ * This has to be done early on in case timer or interrupt controller
+ * needs something. e.g. On C6455 SoC, timer must be enabled through
+ * DSCR before it is functional.
+ */
+void __init dscr_probe(void)
+{
+        struct device_node *node;
+        void __iomem *base;
+
+        spin_lock_init(&dscr.lock);
+
+        node = of_find_matching_node(NULL, dscr_ids);
+        if (!node)
+                return;
+
+        base = of_iomap(node, 0);
+        if (!base) {
+                of_node_put(node);
+                return;
+        }
+
+        dscr.base = base;
+
+        dscr_parse_devstat(node, base);
+        dscr_parse_silicon_rev(node, base);
+        dscr_parse_mac_fuse(node, base);
+        dscr_parse_rmii_resets(node, base);
+        dscr_parse_locked_regs(node, base);
+        dscr_parse_kick_regs(node, base);
+        dscr_parse_devstate_ctl_regs(node, base);
+        dscr_parse_devstate_stat_regs(node, base);
+        dscr_parse_privperm(node, base);
+}
diff --git a/arch/c6x/platforms/emif.c b/arch/c6x/platforms/emif.c
new file mode 100644
index 00000000000..8b564dec241
--- /dev/null
+++ b/arch/c6x/platforms/emif.c
@@ -0,0 +1,87 @@
+/*
+ *  External Memory Interface
+ *
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <asm/soc.h>
+#include <asm/dscr.h>
+
+#define NUM_EMIFA_CHIP_ENABLES 4
+
+struct emifa_regs {
+        u32     midr;
+        u32     stat;
+        u32     reserved1[6];
+        u32     bprio;
+        u32     reserved2[23];
+        u32     cecfg[NUM_EMIFA_CHIP_ENABLES];
+        u32     reserved3[4];
+        u32     awcc;
+        u32     reserved4[7];
+        u32     intraw;
+        u32     intmsk;
+        u32     intmskset;
+        u32     intmskclr;
+};
+
+static struct of_device_id emifa_match[] __initdata = {
+        { .compatible = "ti,c64x+emifa" },
+        {}
+};
+
+/*
+ * Parse device tree for existence of an EMIF (External Memory Interface)
+ * and initialize it if found.
+ */
+static int __init c6x_emifa_init(void)
+{
+        struct emifa_regs __iomem *regs;
+        struct device_node *node;
+        const __be32 *p;
+        u32 val;
+        int i, len, err;
+
+        node = of_find_matching_node(NULL, emifa_match);
+        if (!node)
+                return 0;
+
+        regs = of_iomap(node, 0);
+        if (!regs)
+                return 0;
+
+        /* look for a dscr-based enable for emifa pin buffers */
+        err = of_property_read_u32_array(node, "ti,dscr-dev-enable", &val, 1);
+        if (!err)
+                dscr_set_devstate(val, DSCR_DEVSTATE_ENABLED);
+
+        /* set up the chip enables */
+        p = of_get_property(node, "ti,emifa-ce-config", &len);
+        if (p) {
+                len /= sizeof(u32);
+                if (len > NUM_EMIFA_CHIP_ENABLES)
+                        len = NUM_EMIFA_CHIP_ENABLES;
+                for (i = 0; i <= len; i++)
+                        soc_writel(be32_to_cpup(&p[i]), &regs->cecfg[i]);
+        }
+
+        err = of_property_read_u32_array(node, "ti,emifa-burst-priority", &val, 1);
+        if (!err)
+                soc_writel(val, &regs->bprio);
+
+        err = of_property_read_u32_array(node, "ti,emifa-async-wait-control", &val, 1);
+        if (!err)
+                soc_writel(val, &regs->awcc);
+
+        iounmap(regs);
+        of_node_put(node);
+        return 0;
+}
+pure_initcall(c6x_emifa_init);
diff --git a/arch/c6x/platforms/megamod-pic.c b/arch/c6x/platforms/megamod-pic.c
new file mode 100644
index 00000000000..7c37a947fb1
--- /dev/null
+++ b/arch/c6x/platforms/megamod-pic.c
@@ -0,0 +1,349 @@
+/*
+ *  Support for C64x+ Megamodule Interrupt Controller
+ *
+ *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
+ *  Contributed by: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <asm/soc.h>
+#include <asm/megamod-pic.h>
+
+#define NR_COMBINERS    4
+#define NR_MUX_OUTPUTS  12
+
+#define IRQ_UNMAPPED 0xffff
+
+/*
+ * Megamodule Interrupt Controller register layout
+ */
+struct megamod_regs {
+        u32     evtflag[8];
+        u32     evtset[8];
+        u32     evtclr[8];
+        u32     reserved0[8];
+        u32     evtmask[8];
+        u32     mevtflag[8];
+        u32     expmask[8];
+        u32     mexpflag[8];
+        u32     intmux_unused;
+        u32     intmux[7];
+        u32     reserved1[8];
+        u32     aegmux[2];
+        u32     reserved2[14];
+        u32     intxstat;
+        u32     intxclr;
+        u32     intdmask;
+        u32     reserved3[13];
+        u32     evtasrt;
+};
+
+struct megamod_pic {
+        struct irq_host *irqhost;
+        struct megamod_regs __iomem *regs;
+        raw_spinlock_t lock;
+
+        /* hw mux mapping */
+        unsigned int output_to_irq[NR_MUX_OUTPUTS];
+};
+
+static struct megamod_pic *mm_pic;
+
+struct megamod_cascade_data {
+        struct megamod_pic *pic;
+        int index;
+};
+
+static struct megamod_cascade_data cascade_data[NR_COMBINERS];
+
+static void mask_megamod(struct irq_data *data)
+{
+        struct megamod_pic *pic = irq_data_get_irq_chip_data(data);
+        irq_hw_number_t src = irqd_to_hwirq(data);
+        u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];
+
+        raw_spin_lock(&pic->lock);
+        soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask);
+        raw_spin_unlock(&pic->lock);
+}
+
+static void unmask_megamod(struct irq_data *data)
+{
+        struct megamod_pic *pic = irq_data_get_irq_chip_data(data);
+        irq_hw_number_t src = irqd_to_hwirq(data);
+        u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];
+
+        raw_spin_lock(&pic->lock);
+        soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask);
+        raw_spin_unlock(&pic->lock);
+}
+
+static struct irq_chip megamod_chip = {
+        .name           = "megamod",
+        .irq_mask       = mask_megamod,
+        .irq_unmask     = unmask_megamod,
+};
+
+static void megamod_irq_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        struct megamod_cascade_data *cascade;
+        struct megamod_pic *pic;
+        u32 events;
+        int n, idx;
+
+        cascade = irq_desc_get_handler_data(desc);
+
+        pic = cascade->pic;
+        idx = cascade->index;
+
+        while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) {
+                n = __ffs(events);
+
+                irq = irq_linear_revmap(pic->irqhost, idx * 32 + n);
+
+                soc_writel(1 << n, &pic->regs->evtclr[idx]);
+
+                generic_handle_irq(irq);
+        }
+}
+
+static int megamod_map(struct irq_host *h, unsigned int virq,
+                       irq_hw_number_t hw)
+{
+        struct megamod_pic *pic = h->host_data;
+        int i;
+
+        /* We shouldn't see a hwirq which is muxed to core controller */
+        for (i = 0; i < NR_MUX_OUTPUTS; i++)
+                if (pic->output_to_irq[i] == hw)
+                        return -1;
+
+        irq_set_chip_data(virq, pic);
+        irq_set_chip_and_handler(virq, &megamod_chip, handle_level_irq);
+
+        /* Set default irq type */
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
+
+        return 0;
+}
+
+static int megamod_xlate(struct irq_host *h, struct device_node *ct,
+                         const u32 *intspec, unsigned int intsize,
+                         irq_hw_number_t *out_hwirq, unsigned int *out_type)
+
+{
+        /* megamod intspecs must have 1 cell */
+        BUG_ON(intsize != 1);
+        *out_hwirq = intspec[0];
+        *out_type = IRQ_TYPE_NONE;
+        return 0;
+}
+
+static struct irq_host_ops megamod_host_ops = {
+        .map    = megamod_map,
+        .xlate  = megamod_xlate,
+};
+
+static void __init set_megamod_mux(struct megamod_pic *pic, int src, int output)
+{
+        int index, offset;
+        u32 val;
+
+        if (src < 0 || src >= (NR_COMBINERS * 32)) {
+                pic->output_to_irq[output] = IRQ_UNMAPPED;
+                return;
+        }
+
+        /* four mappings per mux register */
+        index = output / 4;
+        offset = (output & 3) * 8;
+
+        val = soc_readl(&pic->regs->intmux[index]);
+        val &= ~(0xff << offset);
+        val |= src << offset;
+        soc_writel(val, &pic->regs->intmux[index]);
+}
+
+/*
+ * Parse the MUX mapping, if one exists.
+ *
+ * The MUX map is an array of up to 12 cells; one for each usable core priority
+ * interrupt. The value of a given cell is the megamodule interrupt source
+ * which is to me MUXed to the output corresponding to the cell position
+ * withing the array. The first cell in the array corresponds to priority
+ * 4 and the last (12th) cell corresponds to priority 15. The allowed
+ * values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt
+ * sources (0 - 3) are not allowed to be mapped through this property. They
+ * are handled through the "interrupts" property. This allows us to use a
+ * value of zero as a "do not map" placeholder.
+ */
+static void __init parse_priority_map(struct megamod_pic *pic,
+                                      int *mapping, int size)
+{
+        struct device_node *np = pic->irqhost->of_node;
+        const __be32 *map;
+        int i, maplen;
+        u32 val;
+
+        map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen);
+        if (map) {
+                maplen /= 4;
+                if (maplen > size)
+                        maplen = size;
+
+                for (i = 0; i < maplen; i++) {
+                        val = be32_to_cpup(map);
+                        if (val && val >= 4)
+                                mapping[i] = val;
+                        ++map;
+                }
+        }
+}
+
+static struct megamod_pic * __init init_megamod_pic(struct device_node *np)
+{
+        struct megamod_pic *pic;
+        int i, irq;
+        int mapping[NR_MUX_OUTPUTS];
+
+        pr_info("Initializing C64x+ Megamodule PIC\n");
+
+        pic = kzalloc(sizeof(struct megamod_pic), GFP_KERNEL);
+        if (!pic) {
+                pr_err("%s: Could not alloc PIC structure.\n", np->full_name);
+                return NULL;
+        }
+
+        pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
+                                      NR_COMBINERS * 32, &megamod_host_ops,
+                                      IRQ_UNMAPPED);
+        if (!pic->irqhost) {
+                pr_err("%s: Could not alloc host.\n", np->full_name);
+                goto error_free;
+        }
+
+        pic->irqhost->host_data = pic;
+
+        raw_spin_lock_init(&pic->lock);
+
+        pic->regs = of_iomap(np, 0);
+        if (!pic->regs) {
+                pr_err("%s: Could not map registers.\n", np->full_name);
+                goto error_free;
+        }
+
+        /* Initialize MUX map */
+        for (i = 0; i < ARRAY_SIZE(mapping); i++)
+                mapping[i] = IRQ_UNMAPPED;
+
+        parse_priority_map(pic, mapping, ARRAY_SIZE(mapping));
+
+        /*
+         * We can have up to 12 interrupts cascading to the core controller.
+         * These cascades can be from the combined interrupt sources or for
+         * individual interrupt sources. The "interrupts" property only
+         * deals with the cascaded combined interrupts. The individual
+         * interrupts muxed to the core controller use the core controller
+         * as their interrupt parent.
+         */
+        for (i = 0; i < NR_COMBINERS; i++) {
+
+                irq = irq_of_parse_and_map(np, i);
+                if (irq == NO_IRQ)
+                        continue;
+
+                /*
+                 * We count on the core priority interrupts (4 - 15) being
+                 * direct mapped. Check that device tree provided something
+                 * in that range.
+                 */
+                if (irq < 4 || irq >= NR_PRIORITY_IRQS) {
+                        pr_err("%s: combiner-%d virq %d out of range!\n",
+                                 np->full_name, i, irq);
+                        continue;
+                }
+
+                /* record the mapping */
+                mapping[irq - 4] = i;
+
+                pr_debug("%s: combiner-%d cascading to virq %d\n",
+                         np->full_name, i, irq);
+
+                cascade_data[i].pic = pic;
+                cascade_data[i].index = i;
+
+                /* mask and clear all events in combiner */
+                soc_writel(~0, &pic->regs->evtmask[i]);
+                soc_writel(~0, &pic->regs->evtclr[i]);
+
+                irq_set_handler_data(irq, &cascade_data[i]);
+                irq_set_chained_handler(irq, megamod_irq_cascade);
+        }
+
+        /* Finally, set up the MUX registers */
+        for (i = 0; i < NR_MUX_OUTPUTS; i++) {
+                if (mapping[i] != IRQ_UNMAPPED) {
+                        pr_debug("%s: setting mux %d to priority %d\n",
+                                 np->full_name, mapping[i], i + 4);
+                        set_megamod_mux(pic, mapping[i], i);
+                }
+        }
+
+        return pic;
+
+error_free:
+        kfree(pic);
+
+        return NULL;
+}
+
+/*
+ * Return next active event after ACK'ing it.
+ * Return -1 if no events active.
+ */
+static int get_exception(void)
+{
+        int i, bit;
+        u32 mask;
+
+        for (i = 0; i < NR_COMBINERS; i++) {
+                mask = soc_readl(&mm_pic->regs->mexpflag[i]);
+                if (mask) {
+                        bit = __ffs(mask);
+                        soc_writel(1 << bit, &mm_pic->regs->evtclr[i]);
+                        return (i * 32) + bit;
+                }
+        }
+        return -1;
+}
+
+static void assert_event(unsigned int val)
+{
+        soc_writel(val, &mm_pic->regs->evtasrt);
+}
+
+void __init megamod_pic_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic");
+        if (!np)
+                return;
+
+        mm_pic = init_megamod_pic(np);
+        of_node_put(np);
+
+        soc_ops.get_exception = get_exception;
+        soc_ops.assert_event = assert_event;
+
+        return;
+}
diff --git a/arch/c6x/platforms/platform.c b/arch/c6x/platforms/platform.c
new file mode 100644
index 00000000000..26c1a355d60
--- /dev/null
+++ b/arch/c6x/platforms/platform.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2011 Texas Instruments Incorporated
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+static int __init c6x_device_probe(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        return 0;
+}
+core_initcall(c6x_device_probe);
diff --git a/arch/c6x/platforms/pll.c b/arch/c6x/platforms/pll.c
new file mode 100644
index 00000000000..3aa898f7ce4
--- /dev/null
+++ b/arch/c6x/platforms/pll.c
@@ -0,0 +1,444 @@
+/*
+ * Clock and PLL control for C64x+ devices
+ *
+ * Copyright (C) 2010, 2011 Texas Instruments.
+ * Contributed by: Mark Salter <msalter@redhat.com>
+ *
+ * Copied heavily from arm/mach-davinci/clock.c, so:
+ *
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <asm/clock.h>
+#include <asm/soc.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+static DEFINE_SPINLOCK(clockfw_lock);
+
+static void __clk_enable(struct clk *clk)
+{
+        if (clk->parent)
+                __clk_enable(clk->parent);
+        clk->usecount++;
+}
+
+static void __clk_disable(struct clk *clk)
+{
+        if (WARN_ON(clk->usecount == 0))
+                return;
+        --clk->usecount;
+
+        if (clk->parent)
+                __clk_disable(clk->parent);
+}
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        __clk_enable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        __clk_disable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        if (clk->round_rate)
+                return clk->round_rate(clk, rate);
+
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/* Propagate rate to children */
+static void propagate_rate(struct clk *root)
+{
+        struct clk *clk;
+
+        list_for_each_entry(clk, &root->children, childnode) {
+                if (clk->recalc)
+                        clk->rate = clk->recalc(clk);
+                propagate_rate(clk);
+        }
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+
+        if (clk->set_rate)
+                ret = clk->set_rate(clk, rate);
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (ret == 0) {
+                if (clk->recalc)
+                        clk->rate = clk->recalc(clk);
+                propagate_rate(clk);
+        }
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned long flags;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        /* Cannot change parent on enabled clock */
+        if (WARN_ON(clk->usecount))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        clk->parent = parent;
+        list_del_init(&clk->childnode);
+        list_add(&clk->childnode, &clk->parent->children);
+        mutex_unlock(&clocks_mutex);
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (clk->recalc)
+                clk->rate = clk->recalc(clk);
+        propagate_rate(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+int clk_register(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        if (WARN(clk->parent && !clk->parent->rate,
+                 "CLK: %s parent %s has no rate!\n",
+                 clk->name, clk->parent->name))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        list_add_tail(&clk->node, &clocks);
+        if (clk->parent)
+                list_add_tail(&clk->childnode, &clk->parent->children);
+        mutex_unlock(&clocks_mutex);
+
+        /* If rate is already set, use it */
+        if (clk->rate)
+                return 0;
+
+        /* Else, see if there is a way to calculate it */
+        if (clk->recalc)
+                clk->rate = clk->recalc(clk);
+
+        /* Otherwise, default to parent rate */
+        else if (clk->parent)
+                clk->rate = clk->parent->rate;
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+void clk_unregister(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        list_del(&clk->node);
+        list_del(&clk->childnode);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_unregister);
+
+
+static u32 pll_read(struct pll_data *pll, int reg)
+{
+        return soc_readl(pll->base + reg);
+}
+
+static unsigned long clk_sysclk_recalc(struct clk *clk)
+{
+        u32 v, plldiv = 0;
+        struct pll_data *pll;
+        unsigned long rate = clk->rate;
+
+        if (WARN_ON(!clk->parent))
+                return rate;
+
+        rate = clk->parent->rate;
+
+        /* the parent must be a PLL */
+        if (WARN_ON(!clk->parent->pll_data))
+                return rate;
+
+        pll = clk->parent->pll_data;
+
+        /* If pre-PLL, source clock is before the multiplier and divider(s) */
+        if (clk->flags & PRE_PLL)
+                rate = pll->input_rate;
+
+        if (!clk->div) {
+                pr_debug("%s: (no divider) rate = %lu KHz\n",
+                         clk->name, rate / 1000);
+                return rate;
+        }
+
+        if (clk->flags & FIXED_DIV_PLL) {
+                rate /= clk->div;
+                pr_debug("%s: (fixed divide by %d) rate = %lu KHz\n",
+                         clk->name, clk->div, rate / 1000);
+                return rate;
+        }
+
+        v = pll_read(pll, clk->div);
+        if (v & PLLDIV_EN)
+                plldiv = (v & PLLDIV_RATIO_MASK) + 1;
+
+        if (plldiv == 0)
+                plldiv = 1;
+
+        rate /= plldiv;
+
+        pr_debug("%s: (divide by %d) rate = %lu KHz\n",
+                 clk->name, plldiv, rate / 1000);
+
+        return rate;
+}
+
+static unsigned long clk_leafclk_recalc(struct clk *clk)
+{
+        if (WARN_ON(!clk->parent))
+                return clk->rate;
+
+        pr_debug("%s: (parent %s) rate = %lu KHz\n",
+                 clk->name, clk->parent->name,  clk->parent->rate / 1000);
+
+        return clk->parent->rate;
+}
+
+static unsigned long clk_pllclk_recalc(struct clk *clk)
+{
+        u32 ctrl, mult = 0, prediv = 0, postdiv = 0;
+        u8 bypass;
+        struct pll_data *pll = clk->pll_data;
+        unsigned long rate = clk->rate;
+
+        if (clk->flags & FIXED_RATE_PLL)
+                return rate;
+
+        ctrl = pll_read(pll, PLLCTL);
+        rate = pll->input_rate = clk->parent->rate;
+
+        if (ctrl & PLLCTL_PLLEN)
+                bypass = 0;
+        else
+                bypass = 1;
+
+        if (pll->flags & PLL_HAS_MUL) {
+                mult = pll_read(pll, PLLM);
+                mult = (mult & PLLM_PLLM_MASK) + 1;
+        }
+        if (pll->flags & PLL_HAS_PRE) {
+                prediv = pll_read(pll, PLLPRE);
+                if (prediv & PLLDIV_EN)
+                        prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+                else
+                        prediv = 0;
+        }
+        if (pll->flags & PLL_HAS_POST) {
+                postdiv = pll_read(pll, PLLPOST);
+                if (postdiv & PLLDIV_EN)
+                        postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+                else
+                        postdiv = 1;
+        }
+
+        if (!bypass) {
+                if (prediv)
+                        rate /= prediv;
+                if (mult)
+                        rate *= mult;
+                if (postdiv)
+                        rate /= postdiv;
+
+                pr_debug("PLL%d: input = %luMHz, pre[%d] mul[%d] post[%d] "
+                         "--> %luMHz output.\n",
+                         pll->num, clk->parent->rate / 1000000,
+                         prediv, mult, postdiv, rate / 1000000);
+        } else
+                pr_debug("PLL%d: input = %luMHz, bypass mode.\n",
+                         pll->num, clk->parent->rate / 1000000);
+
+        return rate;
+}
+
+
+static void __init __init_clk(struct clk *clk)
+{
+        INIT_LIST_HEAD(&clk->node);
+        INIT_LIST_HEAD(&clk->children);
+        INIT_LIST_HEAD(&clk->childnode);
+
+        if (!clk->recalc) {
+
+                /* Check if clock is a PLL */
+                if (clk->pll_data)
+                        clk->recalc = clk_pllclk_recalc;
+
+                /* Else, if it is a PLL-derived clock */
+                else if (clk->flags & CLK_PLL)
+                        clk->recalc = clk_sysclk_recalc;
+
+                /* Otherwise, it is a leaf clock (PSC clock) */
+                else if (clk->parent)
+                        clk->recalc = clk_leafclk_recalc;
+        }
+}
+
+void __init c6x_clks_init(struct clk_lookup *clocks)
+{
+        struct clk_lookup *c;
+        struct clk *clk;
+        size_t num_clocks = 0;
+
+        for (c = clocks; c->clk; c++) {
+                clk = c->clk;
+
+                __init_clk(clk);
+                clk_register(clk);
+                num_clocks++;
+
+                /* Turn on clocks that Linux doesn't otherwise manage */
+                if (clk->flags & ALWAYS_ENABLED)
+                        clk_enable(clk);
+        }
+
+        clkdev_add_table(clocks, num_clocks);
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#define CLKNAME_MAX     10              /* longest clock name */
+#define NEST_DELTA      2
+#define NEST_MAX        4
+
+static void
+dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
+{
+        char            *state;
+        char            buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
+        struct clk      *clk;
+        unsigned        i;
+
+        if (parent->flags & CLK_PLL)
+                state = "pll";
+        else
+                state = "";
+
+        /* <nest spaces> name <pad to end> */
+        memset(buf, ' ', sizeof(buf) - 1);
+        buf[sizeof(buf) - 1] = 0;
+        i = strlen(parent->name);
+        memcpy(buf + nest, parent->name,
+               min(i, (unsigned)(sizeof(buf) - 1 - nest)));
+
+        seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
+                   buf, parent->usecount, state, clk_get_rate(parent));
+        /* REVISIT show device associations too */
+
+        /* cost is now small, but not linear... */
+        list_for_each_entry(clk, &parent->children, childnode) {
+                dump_clock(s, nest + NEST_DELTA, clk);
+        }
+}
+
+static int c6x_ck_show(struct seq_file *m, void *v)
+{
+        struct clk *clk;
+
+        /*
+         * Show clock tree; We trust nonzero usecounts equate to PSC enables...
+         */
+        mutex_lock(&clocks_mutex);
+        list_for_each_entry(clk, &clocks, node)
+                if (!clk->parent)
+                        dump_clock(m, 0, clk);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+
+static int c6x_ck_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, c6x_ck_show, NULL);
+}
+
+static const struct file_operations c6x_ck_operations = {
+        .open           = c6x_ck_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init c6x_clk_debugfs_init(void)
+{
+        debugfs_create_file("c6x_clocks", S_IFREG | S_IRUGO, NULL, NULL,
+                            &c6x_ck_operations);
+
+        return 0;
+}
+device_initcall(c6x_clk_debugfs_init);
+#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/c6x/platforms/plldata.c b/arch/c6x/platforms/plldata.c
new file mode 100644
index 00000000000..2cfd6f42968
--- /dev/null
+++ b/arch/c6x/platforms/plldata.c
@@ -0,0 +1,404 @@
+/*
+ *  Port on Texas Instruments TMS320C6x architecture
+ *
+ *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Author: Mark Salter <msalter@redhat.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/clock.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+
+/*
+ * Common SoC clock support.
+ */
+
+/* Default input for PLL1 */
+struct clk clkin1 = {
+        .name = "clkin1",
+        .node = LIST_HEAD_INIT(clkin1.node),
+        .children = LIST_HEAD_INIT(clkin1.children),
+        .childnode = LIST_HEAD_INIT(clkin1.childnode),
+};
+
+struct pll_data c6x_soc_pll1 = {
+        .num       = 1,
+        .sysclks   = {
+                {
+                        .name = "pll1",
+                        .parent = &clkin1,
+                        .pll_data = &c6x_soc_pll1,
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk1",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk2",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk3",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk4",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk5",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk6",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk7",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk8",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk9",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk10",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk11",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk12",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk13",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk14",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk15",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+                {
+                        .name = "pll1_sysclk16",
+                        .parent = &c6x_soc_pll1.sysclks[0],
+                        .flags = CLK_PLL,
+                },
+        },
+};
+
+/* CPU core clock */
+struct clk c6x_core_clk = {
+        .name = "core",
+};
+
+/* miscellaneous IO clocks */
+struct clk c6x_i2c_clk = {
+        .name = "i2c",
+};
+
+struct clk c6x_watchdog_clk = {
+        .name = "watchdog",
+};
+
+struct clk c6x_mcbsp1_clk = {
+        .name = "mcbsp1",
+};
+
+struct clk c6x_mcbsp2_clk = {
+        .name = "mcbsp2",
+};
+
+struct clk c6x_mdio_clk = {
+        .name = "mdio",
+};
+
+
+#ifdef CONFIG_SOC_TMS320C6455
+static struct clk_lookup c6455_clks[] = {
+        CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
+        CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
+        CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
+        CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
+        CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
+        CLK(NULL, "core", &c6x_core_clk),
+        CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
+        CLK("watchdog", NULL, &c6x_watchdog_clk),
+        CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
+        CLK("", NULL, NULL)
+};
+
+
+static void __init c6455_setup_clocks(struct device_node *node)
+{
+        struct pll_data *pll = &c6x_soc_pll1;
+        struct clk *sysclks = pll->sysclks;
+
+        pll->flags = PLL_HAS_PRE | PLL_HAS_MUL;
+
+        sysclks[2].flags |= FIXED_DIV_PLL;
+        sysclks[2].div = 3;
+        sysclks[3].flags |= FIXED_DIV_PLL;
+        sysclks[3].div = 6;
+        sysclks[4].div = PLLDIV4;
+        sysclks[5].div = PLLDIV5;
+
+        c6x_core_clk.parent = &sysclks[0];
+        c6x_i2c_clk.parent = &sysclks[3];
+        c6x_watchdog_clk.parent = &sysclks[3];
+        c6x_mdio_clk.parent = &sysclks[3];
+
+        c6x_clks_init(c6455_clks);
+}
+#endif /* CONFIG_SOC_TMS320C6455 */
+
+#ifdef CONFIG_SOC_TMS320C6457
+static struct clk_lookup c6457_clks[] = {
+        CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
+        CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
+        CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
+        CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
+        CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
+        CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
+        CLK(NULL, "core", &c6x_core_clk),
+        CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
+        CLK("watchdog", NULL, &c6x_watchdog_clk),
+        CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
+        CLK("", NULL, NULL)
+};
+
+static void __init c6457_setup_clocks(struct device_node *node)
+{
+        struct pll_data *pll = &c6x_soc_pll1;
+        struct clk *sysclks = pll->sysclks;
+
+        pll->flags = PLL_HAS_MUL | PLL_HAS_POST;
+
+        sysclks[1].flags |= FIXED_DIV_PLL;
+        sysclks[1].div = 1;
+        sysclks[2].flags |= FIXED_DIV_PLL;
+        sysclks[2].div = 3;
+        sysclks[3].flags |= FIXED_DIV_PLL;
+        sysclks[3].div = 6;
+        sysclks[4].div = PLLDIV4;
+        sysclks[5].div = PLLDIV5;
+
+        c6x_core_clk.parent = &sysclks[1];
+        c6x_i2c_clk.parent = &sysclks[3];
+        c6x_watchdog_clk.parent = &sysclks[5];
+        c6x_mdio_clk.parent = &sysclks[5];
+
+        c6x_clks_init(c6457_clks);
+}
+#endif /* CONFIG_SOC_TMS320C6455 */
+
+#ifdef CONFIG_SOC_TMS320C6472
+static struct clk_lookup c6472_clks[] = {
+        CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
+        CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
+        CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
+        CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
+        CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
+        CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
+        CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
+        CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
+        CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
+        CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
+        CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
+        CLK(NULL, "core", &c6x_core_clk),
+        CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
+        CLK("watchdog", NULL, &c6x_watchdog_clk),
+        CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
+        CLK("", NULL, NULL)
+};
+
+/* assumptions used for delay loop calculations */
+#define MIN_CLKIN1_KHz 15625
+#define MAX_CORE_KHz   700000
+#define MIN_PLLOUT_KHz MIN_CLKIN1_KHz
+
+static void __init c6472_setup_clocks(struct device_node *node)
+{
+        struct pll_data *pll = &c6x_soc_pll1;
+        struct clk *sysclks = pll->sysclks;
+        int i;
+
+        pll->flags = PLL_HAS_MUL;
+
+        for (i = 1; i <= 6; i++) {
+                sysclks[i].flags |= FIXED_DIV_PLL;
+                sysclks[i].div = 1;
+        }
+
+        sysclks[7].flags |= FIXED_DIV_PLL;
+        sysclks[7].div = 3;
+        sysclks[8].flags |= FIXED_DIV_PLL;
+        sysclks[8].div = 6;
+        sysclks[9].flags |= FIXED_DIV_PLL;
+        sysclks[9].div = 2;
+        sysclks[10].div = PLLDIV10;
+
+        c6x_core_clk.parent = &sysclks[get_coreid() + 1];
+        c6x_i2c_clk.parent = &sysclks[8];
+        c6x_watchdog_clk.parent = &sysclks[8];
+        c6x_mdio_clk.parent = &sysclks[5];
+
+        c6x_clks_init(c6472_clks);
+}
+#endif /* CONFIG_SOC_TMS320C6472 */
+
+
+#ifdef CONFIG_SOC_TMS320C6474
+static struct clk_lookup c6474_clks[] = {
+        CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
+        CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
+        CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
+        CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
+        CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
+        CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]),
+        CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]),
+        CLK(NULL, "core", &c6x_core_clk),
+        CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
+        CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk),
+        CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk),
+        CLK("watchdog", NULL, &c6x_watchdog_clk),
+        CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
+        CLK("", NULL, NULL)
+};
+
+static void __init c6474_setup_clocks(struct device_node *node)
+{
+        struct pll_data *pll = &c6x_soc_pll1;
+        struct clk *sysclks = pll->sysclks;
+
+        pll->flags = PLL_HAS_MUL;
+
+        sysclks[7].flags |= FIXED_DIV_PLL;
+        sysclks[7].div = 1;
+        sysclks[9].flags |= FIXED_DIV_PLL;
+        sysclks[9].div = 3;
+        sysclks[10].flags |= FIXED_DIV_PLL;
+        sysclks[10].div = 6;
+
+        sysclks[11].div = PLLDIV11;
+
+        sysclks[12].flags |= FIXED_DIV_PLL;
+        sysclks[12].div = 2;
+
+        sysclks[13].div = PLLDIV13;
+
+        c6x_core_clk.parent = &sysclks[7];
+        c6x_i2c_clk.parent = &sysclks[10];
+        c6x_watchdog_clk.parent = &sysclks[10];
+        c6x_mcbsp1_clk.parent = &sysclks[10];
+        c6x_mcbsp2_clk.parent = &sysclks[10];
+
+        c6x_clks_init(c6474_clks);
+}
+#endif /* CONFIG_SOC_TMS320C6474 */
+
+static struct of_device_id c6x_clkc_match[] __initdata = {
+#ifdef CONFIG_SOC_TMS320C6455
+        { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
+#endif
+#ifdef CONFIG_SOC_TMS320C6457
+        { .compatible = "ti,c6457-pll", .data = c6457_setup_clocks },
+#endif
+#ifdef CONFIG_SOC_TMS320C6472
+        { .compatible = "ti,c6472-pll", .data = c6472_setup_clocks },
+#endif
+#ifdef CONFIG_SOC_TMS320C6474
+        { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
+#endif
+        { .compatible = "ti,c64x+pll" },
+        {}
+};
+
+void __init c64x_setup_clocks(void)
+{
+        void (*__setup_clocks)(struct device_node *np);
+        struct pll_data *pll = &c6x_soc_pll1;
+        struct device_node *node;
+        const struct of_device_id *id;
+        int err;
+        u32 val;
+
+        node = of_find_matching_node(NULL, c6x_clkc_match);
+        if (!node)
+                return;
+
+        pll->base = of_iomap(node, 0);
+        if (!pll->base)
+                goto out;
+
+        err = of_property_read_u32(node, "clock-frequency", &val);
+        if (err || val == 0) {
+                pr_err("%s: no clock-frequency found! Using %dMHz\n",
+                       node->full_name, (int)val / 1000000);
+                val = 25000000;
+        }
+        clkin1.rate = val;
+
+        err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val);
+        if (err)
+                val = 5000;
+        pll->bypass_delay = val;
+
+        err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val);
+        if (err)
+                val = 30000;
+        pll->reset_delay = val;
+
+        err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val);
+        if (err)
+                val = 30000;
+        pll->lock_delay = val;
+
+        /* id->data is a pointer to SoC-specific setup */
+        id = of_match_node(c6x_clkc_match, node);
+        if (id && id->data) {
+                __setup_clocks = id->data;
+                __setup_clocks(node);
+        }
+
+out:
+        of_node_put(node);
+}
diff --git a/arch/c6x/platforms/timer64.c b/arch/c6x/platforms/timer64.c
new file mode 100644
index 00000000000..03c03c24919
--- /dev/null
+++ b/arch/c6x/platforms/timer64.c
@@ -0,0 +1,244 @@
+/*
+ *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
+ *  Contributed by: Mark Salter (msalter@redhat.com)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <asm/soc.h>
+#include <asm/dscr.h>
+#include <asm/timer64.h>
+
+struct timer_regs {
+        u32     reserved0;
+        u32     emumgt;
+        u32     reserved1;
+        u32     reserved2;
+        u32     cntlo;
+        u32     cnthi;
+        u32     prdlo;
+        u32     prdhi;
+        u32     tcr;
+        u32     tgcr;
+        u32     wdtcr;
+};
+
+static struct timer_regs __iomem *timer;
+
+#define TCR_TSTATLO          0x001
+#define TCR_INVOUTPLO        0x002
+#define TCR_INVINPLO         0x004
+#define TCR_CPLO             0x008
+#define TCR_ENAMODELO_ONCE   0x040
+#define TCR_ENAMODELO_CONT   0x080
+#define TCR_ENAMODELO_MASK   0x0c0
+#define TCR_PWIDLO_MASK      0x030
+#define TCR_CLKSRCLO         0x100
+#define TCR_TIENLO           0x200
+#define TCR_TSTATHI          (0x001 << 16)
+#define TCR_INVOUTPHI        (0x002 << 16)
+#define TCR_CPHI             (0x008 << 16)
+#define TCR_PWIDHI_MASK      (0x030 << 16)
+#define TCR_ENAMODEHI_ONCE   (0x040 << 16)
+#define TCR_ENAMODEHI_CONT   (0x080 << 16)
+#define TCR_ENAMODEHI_MASK   (0x0c0 << 16)
+
+#define TGCR_TIMLORS         0x001
+#define TGCR_TIMHIRS         0x002
+#define TGCR_TIMMODE_UD32    0x004
+#define TGCR_TIMMODE_WDT64   0x008
+#define TGCR_TIMMODE_CD32    0x00c
+#define TGCR_TIMMODE_MASK    0x00c
+#define TGCR_PSCHI_MASK      (0x00f << 8)
+#define TGCR_TDDRHI_MASK     (0x00f << 12)
+
+/*
+ * Timer clocks are divided down from the CPU clock
+ * The divisor is in the EMUMGTCLKSPD register
+ */
+#define TIMER_DIVISOR \
+        ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
+
+#define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
+
+#define TIMER64_MODE_DISABLED 0
+#define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
+#define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
+
+static int timer64_mode;
+static int timer64_devstate_id = -1;
+
+static void timer64_config(unsigned long period)
+{
+        u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
+
+        soc_writel(tcr, &timer->tcr);
+        soc_writel(period - 1, &timer->prdlo);
+        soc_writel(0, &timer->cntlo);
+        tcr |= timer64_mode;
+        soc_writel(tcr, &timer->tcr);
+}
+
+static void timer64_enable(void)
+{
+        u32 val;
+
+        if (timer64_devstate_id >= 0)
+                dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
+
+        /* disable timer, reset count */
+        soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
+        soc_writel(0, &timer->prdlo);
+
+        /* use internal clock and 1 cycle pulse width */
+        val = soc_readl(&timer->tcr);
+        soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
+
+        /* dual 32-bit unchained mode */
+        val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
+        soc_writel(val, &timer->tgcr);
+        soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
+}
+
+static void timer64_disable(void)
+{
+        /* disable timer, reset count */
+        soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
+        soc_writel(0, &timer->prdlo);
+
+        if (timer64_devstate_id >= 0)
+                dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
+}
+
+static int next_event(unsigned long delta,
+                      struct clock_event_device *evt)
+{
+        timer64_config(delta);
+        return 0;
+}
+
+static void set_clock_mode(enum clock_event_mode mode,
+                           struct clock_event_device *evt)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                timer64_enable();
+                timer64_mode = TIMER64_MODE_PERIODIC;
+                timer64_config(TIMER64_RATE / HZ);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                timer64_enable();
+                timer64_mode = TIMER64_MODE_ONE_SHOT;
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                timer64_mode = TIMER64_MODE_DISABLED;
+                timer64_disable();
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device t64_clockevent_device = {
+        .name           = "TIMER64_EVT32_TIMER",
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .rating         = 200,
+        .set_mode       = set_clock_mode,
+        .set_next_event = next_event,
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *cd = &t64_clockevent_device;
+
+        cd->event_handler(cd);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction timer_iact = {
+        .name           = "timer",
+        .flags          = IRQF_TIMER,
+        .handler        = timer_interrupt,
+        .dev_id         = &t64_clockevent_device,
+};
+
+void __init timer64_init(void)
+{
+        struct clock_event_device *cd = &t64_clockevent_device;
+        struct device_node *np, *first = NULL;
+        u32 val;
+        int err, found = 0;
+
+        for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
+                err = of_property_read_u32(np, "ti,core-mask", &val);
+                if (!err) {
+                        if (val & (1 << get_coreid())) {
+                                found = 1;
+                                break;
+                        }
+                } else if (!first)
+                        first = np;
+        }
+        if (!found) {
+                /* try first one with no core-mask */
+                if (first)
+                        np = of_node_get(first);
+                else {
+                        pr_debug("Cannot find ti,c64x+timer64 timer.\n");
+                        return;
+                }
+        }
+
+        timer = of_iomap(np, 0);
+        if (!timer) {
+                pr_debug("%s: Cannot map timer registers.\n", np->full_name);
+                goto out;
+        }
+        pr_debug("%s: Timer registers=%p.\n", np->full_name, timer);
+
+        cd->irq = irq_of_parse_and_map(np, 0);
+        if (cd->irq == NO_IRQ) {
+                pr_debug("%s: Cannot find interrupt.\n", np->full_name);
+                iounmap(timer);
+                goto out;
+        }
+
+        /* If there is a device state control, save the ID. */
+        err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
+        if (!err) {
+                timer64_devstate_id = val;
+
+                /*
+                 * It is necessary to enable the timer block here because
+                 * the TIMER_DIVISOR macro needs to read a timer register
+                 * to get the divisor.
+                 */
+                dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
+        }
+
+        pr_debug("%s: Timer irq=%d.\n", np->full_name, cd->irq);
+
+        clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
+
+        cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
+        cd->min_delta_ns        = clockevent_delta2ns(250, cd);
+
+        cd->cpumask             = cpumask_of(smp_processor_id());
+
+        clockevents_register_device(cd);
+        setup_irq(cd->irq, &timer_iact);
+
+out:
+        of_node_put(np);
+        return;
+}
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 408b055c585..b3abfb08aa5 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -19,10 +19,6 @@ config GENERIC_CMOS_UPDATE
 config ARCH_USES_GETTIMEOFFSET
         def_bool n
 
-config GENERIC_IOMAP
-       bool
-       default y
-
 config ARCH_HAS_ILOG2_U32
         bool
         default n
@@ -52,6 +48,7 @@ config CRIS
         select HAVE_IDE
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
+        select GENERIC_IOMAP
 
 config HZ
         int
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
index a2bde374462..b34438e026b 100644
--- a/arch/cris/arch-v32/drivers/axisflashmap.c
+++ b/arch/cris/arch-v32/drivers/axisflashmap.c
@@ -404,8 +404,7 @@ static int __init init_axis_flash(void)
                  */
                 int blockstat;
                 do {
-                        blockstat = main_mtd->block_isbad(main_mtd,
-                                ptable_sector);
+                        blockstat = mtd_block_isbad(main_mtd, ptable_sector);
                         if (blockstat < 0)
                                 ptable_sector = 0; /* read error */
                         else if (blockstat)
@@ -413,8 +412,8 @@ static int __init init_axis_flash(void)
                 } while (blockstat && ptable_sector);
 #endif
                 if (ptable_sector) {
-                        main_mtd->read(main_mtd, ptable_sector, PAGESIZE,
-                                &len, page);
+                        mtd_read(main_mtd, ptable_sector, PAGESIZE, &len,
+                                 page);
                         ptable_head = &((struct partitiontable *) page)->head;
                 }
 
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index c5e69abb488..bbbf7927f23 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -317,6 +317,7 @@ config PCI
         bool "Use PCI"
         depends on MB93090_MB00
         default y
+        select GENERIC_PCI_IOMAP
         help
           Some FR-V systems (such as the MB93090-MB00 VDK) have PCI
           onboard. If you have one of these boards and you wish to use the PCI
diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h
index ca7475e73b5..8cb50a2fbcb 100644
--- a/arch/frv/include/asm/io.h
+++ b/arch/frv/include/asm/io.h
@@ -21,6 +21,7 @@
 #include <asm/virtconvert.h>
 #include <asm/string.h>
 #include <asm/mb-regs.h>
+#include <asm-generic/pci_iomap.h>
 #include <linux/delay.h>
 
 /*
@@ -370,7 +371,6 @@ static inline void iowrite32_rep(void __iomem *p, const void *src, unsigned long
 
 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
 {
 }
diff --git a/arch/frv/mb93090-mb00/Makefile b/arch/frv/mb93090-mb00/Makefile
index b73b542f8f4..21f1df1b378 100644
--- a/arch/frv/mb93090-mb00/Makefile
+++ b/arch/frv/mb93090-mb00/Makefile
@@ -3,7 +3,7 @@
 #
 
 ifeq "$(CONFIG_PCI)" "y"
-obj-y := pci-frv.o pci-irq.o pci-vdk.o pci-iomap.o
+obj-y := pci-frv.o pci-irq.o pci-vdk.o
 
 ifeq "$(CONFIG_MMU)" "y"
 obj-y += pci-dma.o
diff --git a/arch/frv/mb93090-mb00/pci-iomap.c b/arch/frv/mb93090-mb00/pci-iomap.c
deleted file mode 100644
index 35f6df28351..00000000000
--- a/arch/frv/mb93090-mb00/pci-iomap.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* pci-iomap.c: description
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/pci.h>
-#include <linux/module.h>
-
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-
-        if ((flags & IORESOURCE_IO) || (flags & IORESOURCE_MEM))
-                return (void __iomem *) start;
-
-        return NULL;
-}
-
-EXPORT_SYMBOL(pci_iomap);
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 02513c2dd5e..9059e390588 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -26,6 +26,7 @@ config HEXAGON
         select HAVE_ARCH_KGDB
         select HAVE_ARCH_TRACEHOOK
         select NO_IOPORT
+        select GENERIC_IOMAP
         # mostly generic routines, with some accelerated ones
         ---help---
           Qualcomm Hexagon is a processor architecture designed for high
@@ -73,9 +74,6 @@ config GENERIC_CSUM
 config GENERIC_IRQ_PROBE
         def_bool y
 
-config GENERIC_IOMAP
-        def_bool y
-
 #config ZONE_DMA
 #       bool
 #       default y
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 3b7a7c48378..bd7266903bf 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -32,6 +32,7 @@ config IA64
         select GENERIC_IRQ_SHOW
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
+        select GENERIC_IOMAP
         default y
         help
           The Itanium Processor Family is Intel's 64-bit successor to
@@ -105,10 +106,6 @@ config EFI
         bool
         default y
 
-config GENERIC_IOMAP
-        bool
-        default y
-
 config ARCH_CLOCKSOURCE_DATA
         def_bool y
 
diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h
index 105c93b00b1..b6a809fa299 100644
--- a/arch/ia64/include/asm/iommu.h
+++ b/arch/ia64/include/asm/iommu.h
@@ -11,10 +11,12 @@ extern void no_iommu_init(void);
 extern int force_iommu, no_iommu;
 extern int iommu_pass_through;
 extern int iommu_detected;
+extern int iommu_group_mf;
 #else
 #define iommu_pass_through      (0)
 #define no_iommu                (1)
 #define iommu_detected          (0)
+#define iommu_group_mf          (0)
 #endif
 extern void iommu_dma_init(void);
 extern void machvec_init(const char *name);
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 1d2427d116e..fbb519828aa 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -71,7 +71,7 @@
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint, unsigned int);
 __DEFINE_GUEST_HANDLE(ulong, unsigned long);
-__DEFINE_GUEST_HANDLE(u64, unsigned long);
+
 DEFINE_GUEST_HANDLE(char);
 DEFINE_GUEST_HANDLE(int);
 DEFINE_GUEST_HANDLE(long);
diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c
index c16162c7086..eb117572005 100644
--- a/arch/ia64/kernel/pci-dma.c
+++ b/arch/ia64/kernel/pci-dma.c
@@ -33,6 +33,7 @@ int force_iommu __read_mostly;
 #endif
 
 int iommu_pass_through;
+int iommu_group_mf;
 
 /* Dummy device used for NULL arguments (normally ISA). Better would
    be probably a smaller DMA mask, but this is bug-to-bug compatible
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 43f4c92816e..40505200249 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -774,13 +774,13 @@ struct kvm *kvm_arch_alloc_vm(void)
         return kvm;
 }
 
-struct kvm_io_range {
+struct kvm_ia64_io_range {
         unsigned long start;
         unsigned long size;
         unsigned long type;
 };
 
-static const struct kvm_io_range io_ranges[] = {
+static const struct kvm_ia64_io_range io_ranges[] = {
         {VGA_IO_START, VGA_IO_SIZE, GPFN_FRAME_BUFFER},
         {MMIO_START, MMIO_SIZE, GPFN_LOW_MMIO},
         {LEGACY_IO_START, LEGACY_IO_SIZE, GPFN_LEGACY_IO},
@@ -1366,14 +1366,12 @@ static void kvm_release_vm_pages(struct kvm *kvm)
 {
         struct kvm_memslots *slots;
         struct kvm_memory_slot *memslot;
-        int i, j;
+        int j;
         unsigned long base_gfn;
 
         slots = kvm_memslots(kvm);
-        for (i = 0; i < slots->nmemslots; i++) {
-                memslot = &slots->memslots[i];
+        kvm_for_each_memslot(memslot, slots) {
                 base_gfn = memslot->base_gfn;
-
                 for (j = 0; j < memslot->npages; j++) {
                         if (memslot->rmap[j])
                                 put_page((struct page *)memslot->rmap[j]);
@@ -1820,7 +1818,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
         if (log->slot >= KVM_MEMORY_SLOTS)
                 goto out;
 
-        memslot = &kvm->memslots->memslots[log->slot];
+        memslot = id_to_memslot(kvm->memslots, log->slot);
         r = -ENOENT;
         if (!memslot->dirty_bitmap)
                 goto out;
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 81fdaa72c54..99c363617f2 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -37,9 +37,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config GENERIC_IOMAP
-        def_bool MMU
-
 config GENERIC_CSUM
         bool
 
@@ -81,6 +78,7 @@ source "kernel/Kconfig.freezer"
 config MMU
         bool "MMU-based Paged Memory Management Support"
         default y
+        select GENERIC_IOMAP
         help
           Select if you want MMU-based virtualised addressing space
           support by paged memory management. If unsure, say 'Y'.
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index e446bab2427..f0eead74fff 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -17,6 +17,7 @@ config MICROBLAZE
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
+        select GENERIC_PCI_IOMAP
 
 config SWAP
         def_bool n
diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h
index cc54187f3d3..a175132e449 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -9,7 +9,14 @@
 #ifndef _ASM_MICROBLAZE_IRQ_H
 #define _ASM_MICROBLAZE_IRQ_H
 
-#define NR_IRQS 32
+
+/*
+ * Linux IRQ# is currently offset by one to map to the hardware
+ * irq number. So hardware IRQ0 maps to Linux irq 1.
+ */
+#define NO_IRQ_OFFSET   1
+#define IRQ_OFFSET      NO_IRQ_OFFSET
+#define NR_IRQS         (32 + IRQ_OFFSET)
 #include <asm-generic/irq.h>
 
 /* This type is the placeholder for a hardware interrupt number. It has to
@@ -20,8 +27,6 @@ typedef unsigned long irq_hw_number_t;
 
 extern unsigned int nr_irq;
 
-#define NO_IRQ (-1)
-
 struct pt_regs;
 extern void do_IRQ(struct pt_regs *regs);
 
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index ed9d0f6e2cd..a25e6b5e2ad 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -174,15 +174,8 @@ extern int page_is_ram(unsigned long pfn);
 
 #define virt_addr_valid(vaddr)  (pfn_valid(virt_to_pfn(vaddr)))
 
-
-#  ifndef CONFIG_MMU
-#  define __pa(vaddr)   ((unsigned long) (vaddr))
-#  define __va(paddr)   ((void *) (paddr))
-#  else /* CONFIG_MMU */
-#  define __pa(x)       __virt_to_phys((unsigned long)(x))
-#  define __va(x)       ((void *)__phys_to_virt((unsigned long)(x)))
-#  endif /* CONFIG_MMU */
-
+# define __pa(x)        __virt_to_phys((unsigned long)(x))
+# define __va(x)        ((void *)__phys_to_virt((unsigned long)(x)))
 
 /* Convert between virtual and physical address for MMU. */
 /* Handle MicroBlaze processor with virtual memory. */
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index 904e5ef6a11..6c72ed7eba9 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -26,12 +26,6 @@ int setup_early_printk(char *opt);
 void remap_early_printk(void);
 void disable_early_printk(void);
 
-#if defined(CONFIG_EARLY_PRINTK)
-#define eprintk early_printk
-#else
-#define eprintk printk
-#endif
-
 void heartbeat(void);
 void setup_heartbeat(void);
 
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index 7d7092b917a..d20ffbc86be 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -391,8 +391,11 @@
 #define __NR_clock_adjtime      373
 #define __NR_syncfs             374
 #define __NR_setns              375
+#define __NR_sendmmsg           376
+#define __NR_process_vm_readv   377
+#define __NR_process_vm_writev  378
 
-#define __NR_syscalls           376
+#define __NR_syscalls           379
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
diff --git a/arch/microblaze/kernel/early_printk.c b/arch/microblaze/kernel/early_printk.c
index d26d92d4775..8356e47631c 100644
--- a/arch/microblaze/kernel/early_printk.c
+++ b/arch/microblaze/kernel/early_printk.c
@@ -50,9 +50,9 @@ static void early_printk_uartlite_write(struct console *unused,
                                         const char *s, unsigned n)
 {
         while (*s && n-- > 0) {
-                early_printk_uartlite_putc(*s);
                 if (*s == '\n')
                         early_printk_uartlite_putc('\r');
+                early_printk_uartlite_putc(*s);
                 s++;
         }
 }
@@ -94,9 +94,9 @@ static void early_printk_uart16550_write(struct console *unused,
                                         const char *s, unsigned n)
 {
         while (*s && n-- > 0) {
-                early_printk_uart16550_putc(*s);
                 if (*s == '\n')
                         early_printk_uart16550_putc('\r');
+                early_printk_uart16550_putc(*s);
                 s++;
         }
 }
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index ca15bc5c744..66e34a3bfe1 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -468,7 +468,7 @@ C_ENTRY(sys_fork_wrapper):
         addi    r5, r0, SIGCHLD                 /* Arg 0: flags */
         lwi     r6, r1, PT_R1   /* Arg 1: child SP (use parent's) */
         addik   r7, r1, 0                       /* Arg 2: parent context */
-        add     r8. r0, r0                      /* Arg 3: (unused) */
+        add     r8, r0, r0                      /* Arg 3: (unused) */
         add     r9, r0, r0;                     /* Arg 4: (unused) */
         brid    do_fork         /* Do real work (tail-call) */
         add     r10, r0, r0;                    /* Arg 5: (unused) */
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index eb41441c7fd..44b177e2ab1 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -42,8 +42,9 @@ unsigned int nr_irq;
 
 static void intc_enable_or_unmask(struct irq_data *d)
 {
-        unsigned long mask = 1 << d->irq;
-        pr_debug("enable_or_unmask: %d\n", d->irq);
+        unsigned long mask = 1 << d->hwirq;
+
+        pr_debug("enable_or_unmask: %ld\n", d->hwirq);
         out_be32(INTC_BASE + SIE, mask);
 
         /* ack level irqs because they can't be acked during
@@ -56,20 +57,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
-        pr_debug("disable: %d\n", d->irq);
-        out_be32(INTC_BASE + CIE, 1 << d->irq);
+        pr_debug("disable: %ld\n", d->hwirq);
+        out_be32(INTC_BASE + CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
-        pr_debug("ack: %d\n", d->irq);
-        out_be32(INTC_BASE + IAR, 1 << d->irq);
+        pr_debug("ack: %ld\n", d->hwirq);
+        out_be32(INTC_BASE + IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
 {
-        unsigned long mask = 1 << d->irq;
-        pr_debug("disable_and_ack: %d\n", d->irq);
+        unsigned long mask = 1 << d->hwirq;
+
+        pr_debug("disable_and_ack: %ld\n", d->hwirq);
         out_be32(INTC_BASE + CIE, mask);
         out_be32(INTC_BASE + IAR, mask);
 }
@@ -91,7 +93,7 @@ unsigned int get_irq(struct pt_regs *regs)
          * order to handle multiple interrupt controllers. It currently
          * is hardcoded to check for interrupts only on the first INTC.
          */
-        irq = in_be32(INTC_BASE + IVR);
+        irq = in_be32(INTC_BASE + IVR) + NO_IRQ_OFFSET;
         pr_debug("get_irq: %d\n", irq);
 
         return irq;
@@ -99,7 +101,7 @@ unsigned int get_irq(struct pt_regs *regs)
 
 void __init init_IRQ(void)
 {
-        u32 i, j, intr_type;
+        u32 i, intr_mask;
         struct device_node *intc = NULL;
 #ifdef CONFIG_SELFMOD_INTC
         unsigned int intc_baseaddr = 0;
@@ -113,35 +115,24 @@ void __init init_IRQ(void)
                                 0
                         };
 #endif
-        const char * const intc_list[] = {
-                                "xlnx,xps-intc-1.00.a",
-                                NULL
-                        };
-
-        for (j = 0; intc_list[j] != NULL; j++) {
-                intc = of_find_compatible_node(NULL, NULL, intc_list[j]);
-                if (intc)
-                        break;
-        }
+        intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
         BUG_ON(!intc);
 
-        intc_baseaddr = be32_to_cpup(of_get_property(intc,
-                                                                "reg", NULL));
+        intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL));
         intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
         nr_irq = be32_to_cpup(of_get_property(intc,
                                                 "xlnx,num-intr-inputs", NULL));
 
-        intr_type =
-                be32_to_cpup(of_get_property(intc,
-                                                "xlnx,kind-of-intr", NULL));
-        if (intr_type > (u32)((1ULL << nr_irq) - 1))
+        intr_mask =
+                be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL));
+        if (intr_mask > (u32)((1ULL << nr_irq) - 1))
                 printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
 
 #ifdef CONFIG_SELFMOD_INTC
         selfmod_function((int *) arr_func, intc_baseaddr);
 #endif
-        printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
-                intc_list[j], intc_baseaddr, nr_irq, intr_type);
+        printk(KERN_INFO "XPS intc #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
+                intc_baseaddr, nr_irq, intr_mask);
 
         /*
          * Disable all external interrupts until they are
@@ -155,8 +146,8 @@ void __init init_IRQ(void)
         /* Turn on the Master Enable. */
         out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
 
-        for (i = 0; i < nr_irq; ++i) {
-                if (intr_type & (0x00000001 << i)) {
+        for (i = IRQ_OFFSET; i < (nr_irq + IRQ_OFFSET); ++i) {
+                if (intr_mask & (0x00000001 << (i - IRQ_OFFSET))) {
                         irq_set_chip_and_handler_name(i, &intc_dev,
                                 handle_edge_irq, "edge");
                         irq_clear_status_flags(i, IRQ_LEVEL);
@@ -165,5 +156,6 @@ void __init init_IRQ(void)
                                 handle_level_irq, "level");
                         irq_set_status_flags(i, IRQ_LEVEL);
                 }
+                irq_get_irq_data(i)->hwirq = i - IRQ_OFFSET;
         }
 }
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index e5d63a89b9b..bbebcae72c0 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -33,11 +33,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
         irq_enter();
         irq = get_irq(regs);
 next_irq:
-        BUG_ON(irq == -1U);
-        generic_handle_irq(irq);
+        BUG_ON(!irq);
+        /* Substract 1 because of get_irq */
+        generic_handle_irq(irq + IRQ_OFFSET - NO_IRQ_OFFSET);
 
         irq = get_irq(regs);
-        if (irq != -1U) {
+        if (irq) {
                 pr_debug("next irq: %d\n", irq);
                 ++concurrent_irq;
                 goto next_irq;
@@ -52,13 +53,13 @@ next_irq:
   intc without any cascades or any connection that's why mapping is 1:1 */
 unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq)
 {
-        return hwirq;
+        return hwirq + IRQ_OFFSET;
 }
 EXPORT_SYMBOL_GPL(irq_create_mapping);
 
 unsigned int irq_create_of_mapping(struct device_node *controller,
                                    const u32 *intspec, unsigned int intsize)
 {
-        return intspec[0];
+        return intspec[0] + IRQ_OFFSET;
 }
 EXPORT_SYMBOL_GPL(irq_create_of_mapping);
diff --git a/arch/microblaze/kernel/module.c b/arch/microblaze/kernel/module.c
index 142426f631b..f39257a5abc 100644
--- a/arch/microblaze/kernel/module.c
+++ b/arch/microblaze/kernel/module.c
@@ -100,7 +100,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
                         break;
 
                 case R_MICROBLAZE_64_NONE:
-                        pr_debug("R_MICROBLAZE_NONE\n");
+                        pr_debug("R_MICROBLAZE_64_NONE\n");
                         break;
 
                 case R_MICROBLAZE_NONE:
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 0e654a12d37..604cd9dd133 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -145,32 +145,32 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         setup_early_printk(NULL);
 #endif
 
-        eprintk("Ramdisk addr 0x%08x, ", ram);
+        printk("Ramdisk addr 0x%08x, ", ram);
         if (fdt)
-                eprintk("FDT at 0x%08x\n", fdt);
+                printk("FDT at 0x%08x\n", fdt);
         else
-                eprintk("Compiled-in FDT at 0x%08x\n",
+                printk("Compiled-in FDT at 0x%08x\n",
                                         (unsigned int)_fdt_start);
 
 #ifdef CONFIG_MTD_UCLINUX
-        eprintk("Found romfs @ 0x%08x (0x%08x)\n",
+        printk("Found romfs @ 0x%08x (0x%08x)\n",
                         romfs_base, romfs_size);
-        eprintk("#### klimit %p ####\n", old_klimit);
+        printk("#### klimit %p ####\n", old_klimit);
         BUG_ON(romfs_size < 0); /* What else can we do? */
 
-        eprintk("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",
+        printk("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",
                         romfs_size, romfs_base, (unsigned)&_ebss);
 
-        eprintk("New klimit: 0x%08x\n", (unsigned)klimit);
+        printk("New klimit: 0x%08x\n", (unsigned)klimit);
 #endif
 
 #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
         if (msr)
-                eprintk("!!!Your kernel has setup MSR instruction but "
+                printk("!!!Your kernel has setup MSR instruction but "
                                 "CPU don't have it %x\n", msr);
 #else
         if (!msr)
-                eprintk("!!!Your kernel not setup MSR instruction but "
+                printk("!!!Your kernel not setup MSR instruction but "
                                 "CPU have it %x\n", msr);
 #endif
 
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index 8789daa2a34..6a2b294ef6d 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -380,3 +380,6 @@ ENTRY(sys_call_table)
         .long sys_clock_adjtime
         .long sys_syncfs
         .long sys_setns                 /* 375 */
+        .long sys_sendmmsg
+        .long sys_process_vm_readv
+        .long sys_process_vm_writev
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index af74b1113aa..3cb0bf64013 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -243,7 +243,7 @@ static int timer_initialized;
 
 void __init time_init(void)
 {
-        u32 irq, i = 0;
+        u32 irq;
         u32 timer_num = 1;
         struct device_node *timer = NULL;
         const void *prop;
@@ -258,33 +258,24 @@ void __init time_init(void)
                                 0
                         };
 #endif
-        const char * const timer_list[] = {
-                "xlnx,xps-timer-1.00.a",
-                NULL
-        };
-
-        for (i = 0; timer_list[i] != NULL; i++) {
-                timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
-                if (timer)
-                        break;
-        }
+        timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a");
         BUG_ON(!timer);
 
         timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
         timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
-        irq = be32_to_cpup(of_get_property(timer, "interrupts", NULL));
+        irq = irq_of_parse_and_map(timer, 0);
         timer_num = be32_to_cpup(of_get_property(timer,
                                                 "xlnx,one-timer-only", NULL));
         if (timer_num) {
-                eprintk(KERN_EMERG "Please enable two timers in HW\n");
+                printk(KERN_EMERG "Please enable two timers in HW\n");
                 BUG();
         }
 
 #ifdef CONFIG_SELFMOD_TIMER
         selfmod_function((int *) arr_func, timer_baseaddr);
 #endif
-        printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
-                timer_list[i], timer_baseaddr, irq);
+        printk(KERN_INFO "XPS timer #0 at 0x%08x, irq=%d\n",
+                timer_baseaddr, irq);
 
         /* If there is clock-frequency property than use it */
         prop = of_get_property(timer, "clock-frequency", NULL);
diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile
index c13067b243c..844960e8ae1 100644
--- a/arch/microblaze/lib/Makefile
+++ b/arch/microblaze/lib/Makefile
@@ -20,6 +20,7 @@ lib-y += uaccess_old.o
 
 lib-y += ashldi3.o
 lib-y += ashrdi3.o
+lib-y += cmpdi2.o
 lib-y += divsi3.o
 lib-y += lshrdi3.o
 lib-y += modsi3.o
diff --git a/arch/microblaze/lib/cmpdi2.c b/arch/microblaze/lib/cmpdi2.c
new file mode 100644
index 00000000000..a708400ea7b
--- /dev/null
+++ b/arch/microblaze/lib/cmpdi2.c
@@ -0,0 +1,26 @@
+#include <linux/module.h>
+
+#include "libgcc.h"
+
+word_type __cmpdi2(long long a, long long b)
+{
+        const DWunion au = {
+                .ll = a
+        };
+        const DWunion bu = {
+                .ll = b
+        };
+
+        if (au.s.high < bu.s.high)
+                return 0;
+        else if (au.s.high > bu.s.high)
+                return 2;
+
+        if ((unsigned int) au.s.low < (unsigned int) bu.s.low)
+                return 0;
+        else if ((unsigned int) au.s.low > (unsigned int) bu.s.low)
+                return 2;
+
+        return 1;
+}
+EXPORT_SYMBOL(__cmpdi2);
diff --git a/arch/microblaze/pci/iomap.c b/arch/microblaze/pci/iomap.c
index 57acda852f5..b07abbac031 100644
--- a/arch/microblaze/pci/iomap.c
+++ b/arch/microblaze/pci/iomap.c
@@ -10,25 +10,6 @@
 #include <asm/io.h>
 #include <asm/pci-bridge.h>
 
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len)
-                return NULL;
-        if (max && len > max)
-                len = max;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM)
-                return ioremap(start, len);
-        /* What? */
-        return NULL;
-}
-EXPORT_SYMBOL(pci_iomap);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
         if (isa_vaddr_is_ioport(addr))
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index db841c7b9d5..0d71b2ed810 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -242,7 +242,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
                          line, pin);
 
                 virq = irq_create_mapping(NULL, line);
-                if (virq != NO_IRQ)
+                if (virq)
                         irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
         } else {
                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
@@ -253,7 +253,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
                                              oirq.size);
         }
-        if (virq == NO_IRQ) {
+        if (!virq) {
                 pr_debug(" Failed to map !\n");
                 return -1;
         }
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a7636d3ddc6..29d92187ff3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -16,6 +16,7 @@ config MIPS
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_KPROBES
         select HAVE_KRETPROBES
+        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
         select HAVE_DMA_ATTRS
@@ -2316,6 +2317,7 @@ config PCI
         bool "Support for PCI controller"
         depends on HW_HAS_PCI
         select PCI_DOMAINS
+        select GENERIC_PCI_IOMAP
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b603b..c22385400fc 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -834,10 +834,13 @@ static struct mtd_partition mtd_partitions[] = {
         }
 };
 
+static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
+
 static struct physmap_flash_data flash_data = {
         .width                  = 2,
         .nr_parts               = ARRAY_SIZE(mtd_partitions),
         .parts                  = mtd_partitions,
+        .part_probe_types       = bcm63xx_part_types,
 };
 
 static struct resource mtd_resources[] = {
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index ed72e6a26b7..1e6b587f62c 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -16,7 +16,6 @@
 #define TAGINFO1_LEN            30      /* Length of vendor information field1 in tag */
 #define FLASHLAYOUTVER_LEN      4       /* Length of Flash Layout Version String tag */
 #define TAGINFO2_LEN            16      /* Length of vendor information field2 in tag */
-#define CRC_LEN                 4       /* Length of CRC in bytes */
 #define ALTTAGINFO_LEN          54      /* Alternate length for vendor information; Pirelli */
 
 #define NUM_PIRELLI             2
@@ -77,19 +76,19 @@ struct bcm_tag {
         /* 192-195: Version flash layout */
         char flash_layout_ver[FLASHLAYOUTVER_LEN];
         /* 196-199: kernel+rootfs CRC32 */
-        char fskernel_crc[CRC_LEN];
+        __u32 fskernel_crc;
         /* 200-215: Unused except on Alice Gate where is is information */
         char information2[TAGINFO2_LEN];
         /* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */
-        char image_crc[CRC_LEN];
+        __u32 image_crc;
         /* 220-223: CRC32 of rootfs partition */
-        char rootfs_crc[CRC_LEN];
+        __u32 rootfs_crc;
         /* 224-227: CRC32 of kernel partition */
-        char kernel_crc[CRC_LEN];
+        __u32 kernel_crc;
         /* 228-235: Unused at present */
         char reserved1[8];
         /* 236-239: CRC32 of header excluding last 20 bytes */
-        char header_crc[CRC_LEN];
+        __u32 header_crc;
         /* 240-255: Unused at present */
         char reserved2[16];
 };
diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c
index 2ab899c4b4c..2635b1a9633 100644
--- a/arch/mips/lib/iomap-pci.c
+++ b/arch/mips/lib/iomap-pci.c
@@ -40,32 +40,6 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
         return (void __iomem *) (ctrl->io_map_base + port);
 }
 
-/*
- * Create a virtual mapping cookie for a PCI BAR (memory or IO)
- */
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-        if (flags & IORESOURCE_IO)
-                return ioport_map_pci(dev, start, len);
-        if (flags & IORESOURCE_MEM) {
-                if (flags & IORESOURCE_CACHEABLE)
-                        return ioremap(start, len);
-                return ioremap_nocache(start, len);
-        }
-        /* What? */
-        return NULL;
-}
-
-EXPORT_SYMBOL(pci_iomap);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
 {
         iounmap(addr);
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 438db84a1f7..8f1c40d5817 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -252,6 +252,7 @@ config PCI
         bool "Use PCI"
         depends on MN10300_UNIT_ASB2305
         default y
+        select GENERIC_PCI_IOMAP
         help
           Some systems (such as the ASB2305) have PCI onboard. If you have one
           of these boards and you wish to use the PCI facilities, say Y here.
diff --git a/arch/mn10300/include/asm/io.h b/arch/mn10300/include/asm/io.h
index 787255da744..139df8c53de 100644
--- a/arch/mn10300/include/asm/io.h
+++ b/arch/mn10300/include/asm/io.h
@@ -229,7 +229,6 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
 
 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
 {
 }
@@ -251,15 +250,15 @@ static inline void *phys_to_virt(unsigned long address)
 /*
  * Change "struct page" to physical address.
  */
-static inline void *__ioremap(unsigned long offset, unsigned long size,
-                              unsigned long flags)
+static inline void __iomem *__ioremap(unsigned long offset, unsigned long size,
+                                      unsigned long flags)
 {
-        return (void *) offset;
+        return (void __iomem *) offset;
 }
 
-static inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
 {
-        return (void *) offset;
+        return (void __iomem *) offset;
 }
 
 /*
@@ -267,14 +266,14 @@ static inline void *ioremap(unsigned long offset, unsigned long size)
  * area.  it's useful if some control registers are in such an area and write
  * combining or read caching is not desirable:
  */
-static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void __iomem *ioremap_nocache(unsigned long offset, unsigned long size)
 {
-        return (void *) (offset | 0x20000000);
+        return (void __iomem *) (offset | 0x20000000);
 }
 
 #define ioremap_wc ioremap_nocache
 
-static inline void iounmap(void *addr)
+static inline void iounmap(void __iomem *addr)
 {
 }
 
diff --git a/arch/mn10300/unit-asb2305/Makefile b/arch/mn10300/unit-asb2305/Makefile
index 0551022225b..cbc5abaa939 100644
--- a/arch/mn10300/unit-asb2305/Makefile
+++ b/arch/mn10300/unit-asb2305/Makefile
@@ -5,4 +5,4 @@
 ###############################################################################
 obj-y   := unit-init.o leds.o
 
-obj-$(CONFIG_PCI) += pci.o pci-asb2305.o pci-irq.o pci-iomap.o
+obj-$(CONFIG_PCI) += pci.o pci-asb2305.o pci-irq.o
diff --git a/arch/mn10300/unit-asb2305/pci-iomap.c b/arch/mn10300/unit-asb2305/pci-iomap.c
deleted file mode 100644
index c1a8d8f941f..00000000000
--- a/arch/mn10300/unit-asb2305/pci-iomap.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* ASB2305 PCI I/O mapping handler
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/pci.h>
-#include <linux/module.h>
-
-/*
- * Create a virtual mapping cookie for a PCI BAR (memory or IO)
- */
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-
-        if ((flags & IORESOURCE_IO) || (flags & IORESOURCE_MEM))
-                return (void __iomem *) start;
-
-        return NULL;
-}
-EXPORT_SYMBOL(pci_iomap);
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index e518a5a4cf4..081a54f1a93 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -38,9 +38,6 @@ config RWSEM_XCHGADD_ALGORITHM
 config GENERIC_HWEIGHT
         def_bool y
 
-config GENERIC_IOMAP
-        def_bool y
-
 config NO_IOPORT
         def_bool y
 
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index fdfd8be29e9..242a1b7ac75 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -14,6 +14,7 @@ config PARISC
         select GENERIC_ATOMIC64 if !64BIT
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
+        select GENERIC_PCI_IOMAP
         select IRQ_PER_CPU
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
 
diff --git a/arch/parisc/lib/iomap.c b/arch/parisc/lib/iomap.c
index 8f470c93b16..fb8e10a4fb3 100644
--- a/arch/parisc/lib/iomap.c
+++ b/arch/parisc/lib/iomap.c
@@ -436,28 +436,6 @@ void ioport_unmap(void __iomem *addr)
         }
 }
 
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM) {
-                if (flags & IORESOURCE_CACHEABLE)
-                        return ioremap(start, len);
-                return ioremap_nocache(start, len);
-        }
-        /* What? */
-        return NULL;
-}
-
 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
 {
         if (!INDIRECT_ADDR(addr)) {
@@ -483,5 +461,4 @@ EXPORT_SYMBOL(iowrite16_rep);
 EXPORT_SYMBOL(iowrite32_rep);
 EXPORT_SYMBOL(ioport_map);
 EXPORT_SYMBOL(ioport_unmap);
-EXPORT_SYMBOL(pci_iomap);
 EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 692ac7588e2..1919634a9b3 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -718,6 +718,7 @@ config PCI
         default PCI_PERMEDIA if !4xx && !CPM2 && !8xx
         default PCI_QSPAN if !4xx && !CPM2 && 8xx
         select ARCH_SUPPORTS_MSI
+        select GENERIC_PCI_IOMAP
         help
           Find out whether your system includes a PCI bus. PCI is the name of
           a bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
index 0ad432bc81d..f7727d91ac6 100644
--- a/arch/powerpc/include/asm/kvm.h
+++ b/arch/powerpc/include/asm/kvm.h
@@ -170,8 +170,8 @@ struct kvm_sregs {
                         } ppc64;
                         struct {
                                 __u32 sr[16];
-                                __u64 ibat[8]; 
-                                __u64 dbat[8]; 
+                                __u64 ibat[8];
+                                __u64 dbat[8];
                         } ppc32;
                 } s;
                 struct {
diff --git a/arch/powerpc/kernel/iomap.c b/arch/powerpc/kernel/iomap.c
index 26279180739..97a3715ac8b 100644
--- a/arch/powerpc/kernel/iomap.c
+++ b/arch/powerpc/kernel/iomap.c
@@ -119,24 +119,6 @@ EXPORT_SYMBOL(ioport_map);
 EXPORT_SYMBOL(ioport_unmap);
 
 #ifdef CONFIG_PCI
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len)
-                return NULL;
-        if (max && len > max)
-                len = max;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM)
-                return ioremap(start, len);
-        /* What? */
-        return NULL;
-}
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
         if (isa_vaddr_is_ioport(addr))
@@ -146,6 +128,5 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
         iounmap(addr);
 }
 
-EXPORT_SYMBOL(pci_iomap);
 EXPORT_SYMBOL(pci_iounmap);
 #endif /* CONFIG_PCI */
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index c7b5afeecaf..3fea3689527 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -441,6 +441,9 @@ static void __init fixup_port_irq(int index,
                 return;
 
         port->irq = virq;
+
+        if (of_device_is_compatible(np, "fsl,ns16550"))
+                port->handle_irq = fsl8250_handle_irq;
 }
 
 static void __init fixup_port_pio(int index,
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index a459479995c..e41ac6f7dcf 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -498,7 +498,7 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
 
         /* If nothing is dirty, don't bother messing with page tables. */
         if (is_dirty) {
-                memslot = &kvm->memslots->memslots[log->slot];
+                memslot = id_to_memslot(kvm->memslots, log->slot);
 
                 ga = memslot->base_gfn << PAGE_SHIFT;
                 ga_end = ga + (memslot->npages << PAGE_SHIFT);
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 286f13d601c..a795a13f4a7 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -86,7 +86,7 @@ static inline int lpcr_rmls(unsigned long rma_size)
  * to allocate contiguous physical memory for the real memory
  * areas for guests.
  */
-void kvm_rma_init(void)
+void __init kvm_rma_init(void)
 {
         unsigned long i;
         unsigned long j, npages;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 31e1adeaa92..0cfb46d54b8 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -175,9 +175,6 @@ config PPC_INDIRECT_MMIO
 config PPC_IO_WORKAROUNDS
         bool
 
-config GENERIC_IOMAP
-        bool
-
 source "drivers/cpufreq/Kconfig"
 
 menu "CPU Frequency drivers"
diff --git a/arch/s390/Kbuild b/arch/s390/Kbuild
index ae4b01060ed..9858476fa0f 100644
--- a/arch/s390/Kbuild
+++ b/arch/s390/Kbuild
@@ -1,6 +1,7 @@
-obj-y += kernel/
-obj-y += mm/
-obj-y += crypto/
-obj-y += appldata/
-obj-y += hypfs/
-obj-y += kvm/
+obj-y                           += kernel/
+obj-y                           += mm/
+obj-$(CONFIG_KVM)               += kvm/
+obj-$(CONFIG_CRYPTO_HW)         += crypto/
+obj-$(CONFIG_S390_HYPFS_FS)     += hypfs/
+obj-$(CONFIG_APPLDATA_BASE)     += appldata/
+obj-$(CONFIG_MATHEMU)           += math-emu/
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 28d183c4275..d1727584230 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -193,18 +193,13 @@ config HOTPLUG_CPU
           Say N if you want to disable CPU hotplug.
 
 config SCHED_MC
-        def_bool y
-        prompt "Multi-core scheduler support"
-        depends on SMP
-        help
-          Multi-core scheduler support improves the CPU scheduler's decision
-          making when dealing with multi-core CPU chips at a cost of slightly
-          increased overhead in some places.
+        def_bool n
 
 config SCHED_BOOK
         def_bool y
         prompt "Book scheduler support"
-        depends on SMP && SCHED_MC
+        depends on SMP
+        select SCHED_MC
         help
           Book scheduler support improves the CPU scheduler's decision making
           when dealing with machines that have several books.
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index 27a0b5df5ea..e9f35334169 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -99,7 +99,6 @@ core-y		+= arch/s390/
 
 libs-y          += arch/s390/lib/
 drivers-y       += drivers/s390/
-drivers-$(CONFIG_MATHEMU) += arch/s390/math-emu/
 
 # must be linked after kernel
 drivers-$(CONFIG_OPROFILE)      += arch/s390/oprofile/
diff --git a/arch/s390/boot/Makefile b/arch/s390/boot/Makefile
index 635d677d328..f2737a005af 100644
--- a/arch/s390/boot/Makefile
+++ b/arch/s390/boot/Makefile
@@ -23,4 +23,4 @@ $(obj)/compressed/vmlinux: FORCE
 
 install: $(CONFIGURE) $(obj)/image
         sh -x  $(srctree)/$(obj)/install.sh $(KERNELRELEASE) $(obj)/image \
-              System.map Kerntypes "$(INSTALL_PATH)"
+              System.map "$(INSTALL_PATH)"
diff --git a/arch/s390/include/asm/kdebug.h b/arch/s390/include/asm/kdebug.h
index 40db27cd6e6..5c1abd47612 100644
--- a/arch/s390/include/asm/kdebug.h
+++ b/arch/s390/include/asm/kdebug.h
@@ -22,6 +22,6 @@ enum die_val {
         DIE_NMI_IPI,
 };
 
-extern void die(const char *, struct pt_regs *, long);
+extern void die(struct pt_regs *, const char *);
 
 #endif
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index 9e13c7d56cc..707f2306725 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -97,47 +97,52 @@ struct _lowcore {
         __u32   gpregs_save_area[16];           /* 0x0180 */
         __u32   cregs_save_area[16];            /* 0x01c0 */
 
+        /* Save areas. */
+        __u32   save_area_sync[8];              /* 0x0200 */
+        __u32   save_area_async[8];             /* 0x0220 */
+        __u32   save_area_restart[1];           /* 0x0240 */
+        __u8    pad_0x0244[0x0248-0x0244];      /* 0x0244 */
+
         /* Return psws. */
-        __u32   save_area[16];                  /* 0x0200 */
-        psw_t   return_psw;                     /* 0x0240 */
-        psw_t   return_mcck_psw;                /* 0x0248 */
+        psw_t   return_psw;                     /* 0x0248 */
+        psw_t   return_mcck_psw;                /* 0x0250 */
 
         /* CPU time accounting values */
-        __u64   sync_enter_timer;               /* 0x0250 */
-        __u64   async_enter_timer;              /* 0x0258 */
-        __u64   mcck_enter_timer;               /* 0x0260 */
-        __u64   exit_timer;                     /* 0x0268 */
-        __u64   user_timer;                     /* 0x0270 */
-        __u64   system_timer;                   /* 0x0278 */
-        __u64   steal_timer;                    /* 0x0280 */
-        __u64   last_update_timer;              /* 0x0288 */
-        __u64   last_update_clock;              /* 0x0290 */
+        __u64   sync_enter_timer;               /* 0x0258 */
+        __u64   async_enter_timer;              /* 0x0260 */
+        __u64   mcck_enter_timer;               /* 0x0268 */
+        __u64   exit_timer;                     /* 0x0270 */
+        __u64   user_timer;                     /* 0x0278 */
+        __u64   system_timer;                   /* 0x0280 */
+        __u64   steal_timer;                    /* 0x0288 */
+        __u64   last_update_timer;              /* 0x0290 */
+        __u64   last_update_clock;              /* 0x0298 */
 
         /* Current process. */
-        __u32   current_task;                   /* 0x0298 */
-        __u32   thread_info;                    /* 0x029c */
-        __u32   kernel_stack;                   /* 0x02a0 */
+        __u32   current_task;                   /* 0x02a0 */
+        __u32   thread_info;                    /* 0x02a4 */
+        __u32   kernel_stack;                   /* 0x02a8 */
 
         /* Interrupt and panic stack. */
-        __u32   async_stack;                    /* 0x02a4 */
-        __u32   panic_stack;                    /* 0x02a8 */
+        __u32   async_stack;                    /* 0x02ac */
+        __u32   panic_stack;                    /* 0x02b0 */
 
         /* Address space pointer. */
-        __u32   kernel_asce;                    /* 0x02ac */
-        __u32   user_asce;                      /* 0x02b0 */
-        __u32   current_pid;                    /* 0x02b4 */
+        __u32   kernel_asce;                    /* 0x02b4 */
+        __u32   user_asce;                      /* 0x02b8 */
+        __u32   current_pid;                    /* 0x02bc */
 
         /* SMP info area */
-        __u32   cpu_nr;                         /* 0x02b8 */
-        __u32   softirq_pending;                /* 0x02bc */
-        __u32   percpu_offset;                  /* 0x02c0 */
-        __u32   ext_call_fast;                  /* 0x02c4 */
-        __u64   int_clock;                      /* 0x02c8 */
-        __u64   mcck_clock;                     /* 0x02d0 */
-        __u64   clock_comparator;               /* 0x02d8 */
-        __u32   machine_flags;                  /* 0x02e0 */
-        __u32   ftrace_func;                    /* 0x02e4 */
-        __u8    pad_0x02e8[0x0300-0x02e8];      /* 0x02e8 */
+        __u32   cpu_nr;                         /* 0x02c0 */
+        __u32   softirq_pending;                /* 0x02c4 */
+        __u32   percpu_offset;                  /* 0x02c8 */
+        __u32   ext_call_fast;                  /* 0x02cc */
+        __u64   int_clock;                      /* 0x02d0 */
+        __u64   mcck_clock;                     /* 0x02d8 */
+        __u64   clock_comparator;               /* 0x02e0 */
+        __u32   machine_flags;                  /* 0x02e8 */
+        __u32   ftrace_func;                    /* 0x02ec */
+        __u8    pad_0x02f8[0x0300-0x02f0];      /* 0x02f0 */
 
         /* Interrupt response block */
         __u8    irb[64];                        /* 0x0300 */
@@ -229,57 +234,62 @@ struct _lowcore {
         psw_t   mcck_new_psw;                   /* 0x01e0 */
         psw_t   io_new_psw;                     /* 0x01f0 */
 
-        /* Entry/exit save area & return psws. */
-        __u64   save_area[16];                  /* 0x0200 */
-        psw_t   return_psw;                     /* 0x0280 */
-        psw_t   return_mcck_psw;                /* 0x0290 */
+        /* Save areas. */
+        __u64   save_area_sync[8];              /* 0x0200 */
+        __u64   save_area_async[8];             /* 0x0240 */
+        __u64   save_area_restart[1];           /* 0x0280 */
+        __u8    pad_0x0288[0x0290-0x0288];      /* 0x0288 */
+
+        /* Return psws. */
+        psw_t   return_psw;                     /* 0x0290 */
+        psw_t   return_mcck_psw;                /* 0x02a0 */
 
         /* CPU accounting and timing values. */
-        __u64   sync_enter_timer;               /* 0x02a0 */
-        __u64   async_enter_timer;              /* 0x02a8 */
-        __u64   mcck_enter_timer;               /* 0x02b0 */
-        __u64   exit_timer;                     /* 0x02b8 */
-        __u64   user_timer;                     /* 0x02c0 */
-        __u64   system_timer;                   /* 0x02c8 */
-        __u64   steal_timer;                    /* 0x02d0 */
-        __u64   last_update_timer;              /* 0x02d8 */
-        __u64   last_update_clock;              /* 0x02e0 */
+        __u64   sync_enter_timer;               /* 0x02b0 */
+        __u64   async_enter_timer;              /* 0x02b8 */
+        __u64   mcck_enter_timer;               /* 0x02c0 */
+        __u64   exit_timer;                     /* 0x02c8 */
+        __u64   user_timer;                     /* 0x02d0 */
+        __u64   system_timer;                   /* 0x02d8 */
+        __u64   steal_timer;                    /* 0x02e0 */
+        __u64   last_update_timer;              /* 0x02e8 */
+        __u64   last_update_clock;              /* 0x02f0 */
 
         /* Current process. */
-        __u64   current_task;                   /* 0x02e8 */
-        __u64   thread_info;                    /* 0x02f0 */
-        __u64   kernel_stack;                   /* 0x02f8 */
+        __u64   current_task;                   /* 0x02f8 */
+        __u64   thread_info;                    /* 0x0300 */
+        __u64   kernel_stack;                   /* 0x0308 */
 
         /* Interrupt and panic stack. */
-        __u64   async_stack;                    /* 0x0300 */
-        __u64   panic_stack;                    /* 0x0308 */
+        __u64   async_stack;                    /* 0x0310 */
+        __u64   panic_stack;                    /* 0x0318 */
 
         /* Address space pointer. */
-        __u64   kernel_asce;                    /* 0x0310 */
-        __u64   user_asce;                      /* 0x0318 */
-        __u64   current_pid;                    /* 0x0320 */
+        __u64   kernel_asce;                    /* 0x0320 */
+        __u64   user_asce;                      /* 0x0328 */
+        __u64   current_pid;                    /* 0x0330 */
 
         /* SMP info area */
-        __u32   cpu_nr;                         /* 0x0328 */
-        __u32   softirq_pending;                /* 0x032c */
-        __u64   percpu_offset;                  /* 0x0330 */
-        __u64   ext_call_fast;                  /* 0x0338 */
-        __u64   int_clock;                      /* 0x0340 */
-        __u64   mcck_clock;                     /* 0x0348 */
-        __u64   clock_comparator;               /* 0x0350 */
-        __u64   vdso_per_cpu_data;              /* 0x0358 */
-        __u64   machine_flags;                  /* 0x0360 */
-        __u64   ftrace_func;                    /* 0x0368 */
-        __u64   gmap;                           /* 0x0370 */
-        __u64   cmf_hpp;                        /* 0x0378 */
+        __u32   cpu_nr;                         /* 0x0338 */
+        __u32   softirq_pending;                /* 0x033c */
+        __u64   percpu_offset;                  /* 0x0340 */
+        __u64   ext_call_fast;                  /* 0x0348 */
+        __u64   int_clock;                      /* 0x0350 */
+        __u64   mcck_clock;                     /* 0x0358 */
+        __u64   clock_comparator;               /* 0x0360 */
+        __u64   vdso_per_cpu_data;              /* 0x0368 */
+        __u64   machine_flags;                  /* 0x0370 */
+        __u64   ftrace_func;                    /* 0x0378 */
+        __u64   gmap;                           /* 0x0380 */
+        __u8    pad_0x0388[0x0400-0x0388];      /* 0x0388 */
 
         /* Interrupt response block. */
-        __u8    irb[64];                        /* 0x0380 */
+        __u8    irb[64];                        /* 0x0400 */
 
         /* Per cpu primary space access list */
-        __u32   paste[16];                      /* 0x03c0 */
+        __u32   paste[16];                      /* 0x0440 */
 
-        __u8    pad_0x0400[0x0e00-0x0400];      /* 0x0400 */
+        __u8    pad_0x0480[0x0e00-0x0480];      /* 0x0480 */
 
         /*
          * 0xe00 contains the address of the IPL Parameter Information
diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h
index 5325c89a584..0fbd1899c7b 100644
--- a/arch/s390/include/asm/percpu.h
+++ b/arch/s390/include/asm/percpu.h
@@ -19,7 +19,7 @@
 #define ARCH_NEEDS_WEAK_PER_CPU
 #endif
 
-#define arch_irqsafe_cpu_to_op(pcp, val, op)                            \
+#define arch_this_cpu_to_op(pcp, val, op)                               \
 do {                                                                    \
         typedef typeof(pcp) pcp_op_T__;                                 \
         pcp_op_T__ old__, new__, prev__;                                \
@@ -41,27 +41,27 @@ do {									\
         preempt_enable();                                               \
 } while (0)
 
-#define irqsafe_cpu_add_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
-#define irqsafe_cpu_add_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
-#define irqsafe_cpu_add_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
-#define irqsafe_cpu_add_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define this_cpu_add_1(pcp, val) arch_this_cpu_to_op(pcp, val, +)
+#define this_cpu_add_2(pcp, val) arch_this_cpu_to_op(pcp, val, +)
+#define this_cpu_add_4(pcp, val) arch_this_cpu_to_op(pcp, val, +)
+#define this_cpu_add_8(pcp, val) arch_this_cpu_to_op(pcp, val, +)
 
-#define irqsafe_cpu_and_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
-#define irqsafe_cpu_and_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
-#define irqsafe_cpu_and_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
-#define irqsafe_cpu_and_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define this_cpu_and_1(pcp, val) arch_this_cpu_to_op(pcp, val, &)
+#define this_cpu_and_2(pcp, val) arch_this_cpu_to_op(pcp, val, &)
+#define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, &)
+#define this_cpu_and_8(pcp, val) arch_this_cpu_to_op(pcp, val, &)
 
-#define irqsafe_cpu_or_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
-#define irqsafe_cpu_or_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
-#define irqsafe_cpu_or_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
-#define irqsafe_cpu_or_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define this_cpu_or_1(pcp, val) arch_this_cpu_to_op(pcp, val, |)
+#define this_cpu_or_2(pcp, val) arch_this_cpu_to_op(pcp, val, |)
+#define this_cpu_or_4(pcp, val) arch_this_cpu_to_op(pcp, val, |)
+#define this_cpu_or_8(pcp, val) arch_this_cpu_to_op(pcp, val, |)
 
-#define irqsafe_cpu_xor_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
-#define irqsafe_cpu_xor_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
-#define irqsafe_cpu_xor_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
-#define irqsafe_cpu_xor_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define this_cpu_xor_1(pcp, val) arch_this_cpu_to_op(pcp, val, ^)
+#define this_cpu_xor_2(pcp, val) arch_this_cpu_to_op(pcp, val, ^)
+#define this_cpu_xor_4(pcp, val) arch_this_cpu_to_op(pcp, val, ^)
+#define this_cpu_xor_8(pcp, val) arch_this_cpu_to_op(pcp, val, ^)
 
-#define arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)                       \
+#define arch_this_cpu_cmpxchg(pcp, oval, nval)                  \
 ({                                                                      \
         typedef typeof(pcp) pcp_op_T__;                                 \
         pcp_op_T__ ret__;                                               \
@@ -79,10 +79,10 @@ do {									\
         ret__;                                                          \
 })
 
-#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
-#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
-#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
-#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define this_cpu_cmpxchg_1(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)
+#define this_cpu_cmpxchg_2(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)
+#define this_cpu_cmpxchg_4(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)
+#define this_cpu_cmpxchg_8(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)
 
 #include <asm-generic/percpu.h>
 
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 4f289ff0b7f..011358c1b18 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -128,28 +128,11 @@ static inline int is_zero_pfn(unsigned long pfn)
  * effect, this also makes sure that 64 bit module code cannot be used
  * as system call address.
  */
-
 extern unsigned long VMALLOC_START;
+extern unsigned long VMALLOC_END;
+extern struct page *vmemmap;
 
-#ifndef __s390x__
-#define VMALLOC_SIZE    (96UL << 20)
-#define VMALLOC_END     0x7e000000UL
-#define VMEM_MAP_END    0x80000000UL
-#else /* __s390x__ */
-#define VMALLOC_SIZE    (128UL << 30)
-#define VMALLOC_END     0x3e000000000UL
-#define VMEM_MAP_END    0x40000000000UL
-#endif /* __s390x__ */
-
-/*
- * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
- * mapping. This needs to be calculated at compile time since the size of the
- * VMEM_MAP is static but the size of struct page can change.
- */
-#define VMEM_MAX_PAGES  ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
-#define VMEM_MAX_PFN    min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
-#define VMEM_MAX_PHYS   ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
-#define vmemmap         ((struct page *) VMALLOC_END)
+#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
 
 /*
  * A 31 bit pagetable entry of S390 has following format:
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 5f33d37d032..27272f6a14c 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -80,8 +80,6 @@ struct thread_struct {
         unsigned int  acrs[NUM_ACRS];
         unsigned long ksp;              /* kernel stack pointer             */
         mm_segment_t mm_segment;
-        unsigned long prot_addr;        /* address of protection-excep.     */
-        unsigned int trap_no;
         unsigned long gmap_addr;        /* address of last gmap fault. */
         struct per_regs per_user;       /* User specified PER registers */
         struct per_event per_event;     /* Cause of the last PER trap */
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index a65846340d5..56da355678f 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -324,7 +324,8 @@ struct pt_regs
         psw_t psw;
         unsigned long gprs[NUM_GPRS];
         unsigned long orig_gpr2;
-        unsigned int svc_code;
+        unsigned int int_code;
+        unsigned long int_parm_long;
 };
 
 /*
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index e63d13dd3bf..d75c8e78f7e 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -352,7 +352,7 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
  * @no_output_qs: number of output queues
  * @input_handler: handler to be called for input queues
  * @output_handler: handler to be called for output queues
- * @queue_start_poll: polling handlers (one per input queue or NULL)
+ * @queue_start_poll_array: polling handlers (one per input queue or NULL)
  * @int_parm: interruption parameter
  * @input_sbal_addr_array:  address of no_input_qs * 128 pointers
  * @output_sbal_addr_array: address of no_output_qs * 128 pointers
@@ -372,7 +372,8 @@ struct qdio_initialize {
         unsigned int no_output_qs;
         qdio_handler_t *input_handler;
         qdio_handler_t *output_handler;
-        void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
+        void (**queue_start_poll_array) (struct ccw_device *, int,
+                                          unsigned long);
         int scan_threshold;
         unsigned long int_parm;
         void **input_sbal_addr_array;
diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
index e3bffd4e2d6..7040b8567cd 100644
--- a/arch/s390/include/asm/sigp.h
+++ b/arch/s390/include/asm/sigp.h
@@ -56,6 +56,7 @@ enum {
         ec_schedule = 0,
         ec_call_function,
         ec_call_function_single,
+        ec_stop_cpu,
 };
 
 /*
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index ab47a69fdf0..c32e9123b40 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -23,7 +23,6 @@ extern void __cpu_die (unsigned int cpu);
 extern int __cpu_up (unsigned int cpu);
 
 extern struct mutex smp_cpu_state_mutex;
-extern int smp_cpu_polarization[];
 
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
diff --git a/arch/s390/include/asm/sparsemem.h b/arch/s390/include/asm/sparsemem.h
index 545d219e6a2..0fb34027d3f 100644
--- a/arch/s390/include/asm/sparsemem.h
+++ b/arch/s390/include/asm/sparsemem.h
@@ -4,8 +4,8 @@
 #ifdef CONFIG_64BIT
 
 #define SECTION_SIZE_BITS       28
-#define MAX_PHYSADDR_BITS       42
-#define MAX_PHYSMEM_BITS        42
+#define MAX_PHYSADDR_BITS       46
+#define MAX_PHYSMEM_BITS        46
 
 #else
 
diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h
index b239ff53b18..fb214dd9b7e 100644
--- a/arch/s390/include/asm/syscall.h
+++ b/arch/s390/include/asm/syscall.h
@@ -27,7 +27,7 @@ static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
 {
         return test_tsk_thread_flag(task, TIF_SYSCALL) ?
-                (regs->svc_code & 0xffff) : -1;
+                (regs->int_code & 0xffff) : -1;
 }
 
 static inline void syscall_rollback(struct task_struct *task,
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
index ef573c1d71a..d73cc6b6000 100644
--- a/arch/s390/include/asm/system.h
+++ b/arch/s390/include/asm/system.h
@@ -20,8 +20,6 @@
 
 struct task_struct;
 
-extern int sysctl_userprocess_debug;
-
 extern struct task_struct *__switch_to(void *, void *);
 extern void update_per_regs(struct task_struct *task);
 
diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h
index 005d77d8ae2..0837de80c35 100644
--- a/arch/s390/include/asm/topology.h
+++ b/arch/s390/include/asm/topology.h
@@ -4,6 +4,10 @@
 #include <linux/cpumask.h>
 #include <asm/sysinfo.h>
 
+struct cpu;
+
+#ifdef CONFIG_SCHED_BOOK
+
 extern unsigned char cpu_core_id[NR_CPUS];
 extern cpumask_t cpu_core_map[NR_CPUS];
 
@@ -16,8 +20,6 @@ static inline const struct cpumask *cpu_coregroup_mask(int cpu)
 #define topology_core_cpumask(cpu)      (&cpu_core_map[cpu])
 #define mc_capable()                    (1)
 
-#ifdef CONFIG_SCHED_BOOK
-
 extern unsigned char cpu_book_id[NR_CPUS];
 extern cpumask_t cpu_book_map[NR_CPUS];
 
@@ -29,19 +31,45 @@ static inline const struct cpumask *cpu_book_mask(int cpu)
 #define topology_book_id(cpu)           (cpu_book_id[cpu])
 #define topology_book_cpumask(cpu)      (&cpu_book_map[cpu])
 
-#endif /* CONFIG_SCHED_BOOK */
-
+int topology_cpu_init(struct cpu *);
 int topology_set_cpu_management(int fc);
 void topology_schedule_update(void);
 void store_topology(struct sysinfo_15_1_x *info);
+void topology_expect_change(void);
+
+#else /* CONFIG_SCHED_BOOK */
+
+static inline void topology_schedule_update(void) { }
+static inline int topology_cpu_init(struct cpu *cpu) { return 0; }
+static inline void topology_expect_change(void) { }
 
-#define POLARIZATION_UNKNWN     (-1)
+#endif /* CONFIG_SCHED_BOOK */
+
+#define POLARIZATION_UNKNOWN    (-1)
 #define POLARIZATION_HRZ        (0)
 #define POLARIZATION_VL         (1)
 #define POLARIZATION_VM         (2)
 #define POLARIZATION_VH         (3)
 
-#ifdef CONFIG_SMP
+extern int cpu_polarization[];
+
+static inline void cpu_set_polarization(int cpu, int val)
+{
+#ifdef CONFIG_SCHED_BOOK
+        cpu_polarization[cpu] = val;
+#endif
+}
+
+static inline int cpu_read_polarization(int cpu)
+{
+#ifdef CONFIG_SCHED_BOOK
+        return cpu_polarization[cpu];
+#else
+        return POLARIZATION_HRZ;
+#endif
+}
+
+#ifdef CONFIG_SCHED_BOOK
 void s390_init_cpu_topology(void);
 #else
 static inline void s390_init_cpu_topology(void)
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index 58de4c91c33..8a8008fe7b8 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -398,6 +398,7 @@
 #define __ARCH_WANT_SYS_SIGNAL
 #define __ARCH_WANT_SYS_UTIME
 #define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_IPC
 #define __ARCH_WANT_SYS_FADVISE64
 #define __ARCH_WANT_SYS_GETPGRP
 #define __ARCH_WANT_SYS_LLSEEK
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index dd4f0764091..7d9ec924e7e 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -32,7 +32,8 @@ extra-y				+= head.o init_task.o vmlinux.lds
 extra-y                         += $(if $(CONFIG_64BIT),head64.o,head31.o)
 
 obj-$(CONFIG_MODULES)           += s390_ksyms.o module.o
-obj-$(CONFIG_SMP)               += smp.o topology.o
+obj-$(CONFIG_SMP)               += smp.o
+obj-$(CONFIG_SCHED_BOOK)        += topology.o
 obj-$(CONFIG_SMP)               += $(if $(CONFIG_64BIT),switch_cpu64.o, \
                                                         switch_cpu.o)
 obj-$(CONFIG_HIBERNATION)       += suspend.o swsusp_asm64.o
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 751318765e2..6e6a72e66d6 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -45,7 +45,8 @@ int main(void)
         DEFINE(__PT_PSW, offsetof(struct pt_regs, psw));
         DEFINE(__PT_GPRS, offsetof(struct pt_regs, gprs));
         DEFINE(__PT_ORIG_GPR2, offsetof(struct pt_regs, orig_gpr2));
-        DEFINE(__PT_SVC_CODE, offsetof(struct pt_regs, svc_code));
+        DEFINE(__PT_INT_CODE, offsetof(struct pt_regs, int_code));
+        DEFINE(__PT_INT_PARM_LONG, offsetof(struct pt_regs, int_parm_long));
         DEFINE(__PT_SIZE, sizeof(struct pt_regs));
         BLANK();
         DEFINE(__SF_BACKCHAIN, offsetof(struct stack_frame, back_chain));
@@ -108,7 +109,9 @@ int main(void)
         DEFINE(__LC_PGM_NEW_PSW, offsetof(struct _lowcore, program_new_psw));
         DEFINE(__LC_MCK_NEW_PSW, offsetof(struct _lowcore, mcck_new_psw));
         DEFINE(__LC_IO_NEW_PSW, offsetof(struct _lowcore, io_new_psw));
-        DEFINE(__LC_SAVE_AREA, offsetof(struct _lowcore, save_area));
+        DEFINE(__LC_SAVE_AREA_SYNC, offsetof(struct _lowcore, save_area_sync));
+        DEFINE(__LC_SAVE_AREA_ASYNC, offsetof(struct _lowcore, save_area_async));
+        DEFINE(__LC_SAVE_AREA_RESTART, offsetof(struct _lowcore, save_area_restart));
         DEFINE(__LC_RETURN_PSW, offsetof(struct _lowcore, return_psw));
         DEFINE(__LC_RETURN_MCCK_PSW, offsetof(struct _lowcore, return_mcck_psw));
         DEFINE(__LC_SYNC_ENTER_TIMER, offsetof(struct _lowcore, sync_enter_timer));
@@ -150,7 +153,6 @@ int main(void)
         DEFINE(__LC_LAST_BREAK, offsetof(struct _lowcore, breaking_event_addr));
         DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
         DEFINE(__LC_GMAP, offsetof(struct _lowcore, gmap));
-        DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp));
         DEFINE(__GMAP_ASCE, offsetof(struct gmap, asce));
 #endif /* CONFIG_32BIT */
         return 0;
diff --git a/arch/s390/kernel/base.S b/arch/s390/kernel/base.S
index f8828d38fa6..3aa4d00aaf5 100644
--- a/arch/s390/kernel/base.S
+++ b/arch/s390/kernel/base.S
@@ -33,7 +33,7 @@ s390_base_mcck_handler_fn:
         .previous
 
 ENTRY(s390_base_ext_handler)
-        stmg    %r0,%r15,__LC_SAVE_AREA
+        stmg    %r0,%r15,__LC_SAVE_AREA_ASYNC
         basr    %r13,0
 0:      aghi    %r15,-STACK_FRAME_OVERHEAD
         larl    %r1,s390_base_ext_handler_fn
@@ -41,7 +41,7 @@ ENTRY(s390_base_ext_handler)
         ltgr    %r1,%r1
         jz      1f
         basr    %r14,%r1
-1:      lmg     %r0,%r15,__LC_SAVE_AREA
+1:      lmg     %r0,%r15,__LC_SAVE_AREA_ASYNC
         ni      __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
         lpswe   __LC_EXT_OLD_PSW
 
@@ -53,7 +53,7 @@ s390_base_ext_handler_fn:
         .previous
 
 ENTRY(s390_base_pgm_handler)
-        stmg    %r0,%r15,__LC_SAVE_AREA
+        stmg    %r0,%r15,__LC_SAVE_AREA_SYNC
         basr    %r13,0
 0:      aghi    %r15,-STACK_FRAME_OVERHEAD
         larl    %r1,s390_base_pgm_handler_fn
@@ -61,7 +61,7 @@ ENTRY(s390_base_pgm_handler)
         ltgr    %r1,%r1
         jz      1f
         basr    %r14,%r1
-        lmg     %r0,%r15,__LC_SAVE_AREA
+        lmg     %r0,%r15,__LC_SAVE_AREA_SYNC
         lpswe   __LC_PGM_OLD_PSW
 1:      lpswe   disabled_wait_psw-0b(%r13)
 
@@ -142,7 +142,7 @@ s390_base_mcck_handler_fn:
         .previous
 
 ENTRY(s390_base_ext_handler)
-        stm     %r0,%r15,__LC_SAVE_AREA
+        stm     %r0,%r15,__LC_SAVE_AREA_ASYNC
         basr    %r13,0
 0:      ahi     %r15,-STACK_FRAME_OVERHEAD
         l       %r1,2f-0b(%r13)
@@ -150,7 +150,7 @@ ENTRY(s390_base_ext_handler)
         ltr     %r1,%r1
         jz      1f
         basr    %r14,%r1
-1:      lm      %r0,%r15,__LC_SAVE_AREA
+1:      lm      %r0,%r15,__LC_SAVE_AREA_ASYNC
         ni      __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
         lpsw    __LC_EXT_OLD_PSW
 
@@ -164,7 +164,7 @@ s390_base_ext_handler_fn:
         .previous
 
 ENTRY(s390_base_pgm_handler)
-        stm     %r0,%r15,__LC_SAVE_AREA
+        stm     %r0,%r15,__LC_SAVE_AREA_SYNC
         basr    %r13,0
 0:      ahi     %r15,-STACK_FRAME_OVERHEAD
         l       %r1,2f-0b(%r13)
@@ -172,7 +172,7 @@ ENTRY(s390_base_pgm_handler)
         ltr     %r1,%r1
         jz      1f
         basr    %r14,%r1
-        lm      %r0,%r15,__LC_SAVE_AREA
+        lm      %r0,%r15,__LC_SAVE_AREA_SYNC
         lpsw    __LC_PGM_OLD_PSW
 
 1:      lpsw    disabled_wait_psw-0b(%r13)
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index 84a98289844..ab64bdbab2a 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -278,9 +278,6 @@ asmlinkage long sys32_ipc(u32 call, int first, int second, int third, u32 ptr)
 {
         if (call >> 16)         /* hack for backward compatibility */
                 return -EINVAL;
-
-        call &= 0xffff;
-
         switch (call) {
         case SEMTIMEDOP:
                 return compat_sys_semtimedop(first, compat_ptr(ptr),
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index 4f68c81d3ff..6fe78c2f95d 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -501,8 +501,12 @@ static int setup_frame32(int sig, struct k_sigaction *ka,
 
         /* We forgot to include these in the sigcontext.
            To avoid breaking binary compatibility, they are passed as args. */
-        regs->gprs[4] = current->thread.trap_no;
-        regs->gprs[5] = current->thread.prot_addr;
+        if (sig == SIGSEGV || sig == SIGBUS || sig == SIGILL ||
+            sig == SIGTRAP || sig == SIGFPE) {
+                /* set extra registers only for synchronous signals */
+                regs->gprs[4] = regs->int_code & 127;
+                regs->gprs[5] = regs->int_parm_long;
+        }
 
         /* Place signal number on stack to allow backtrace from handler.  */
         if (__put_user(regs->gprs[2], (int __force __user *) &frame->signo))
@@ -544,9 +548,9 @@ static int setup_rt_frame32(int sig, struct k_sigaction *ka, siginfo_t *info,
         /* Set up to return from userspace.  If provided, use a stub
            already in userspace.  */
         if (ka->sa.sa_flags & SA_RESTORER) {
-                regs->gprs[14] = (__u64) ka->sa.sa_restorer;
+                regs->gprs[14] = (__u64) ka->sa.sa_restorer | PSW32_ADDR_AMODE;
         } else {
-                regs->gprs[14] = (__u64) frame->retcode;
+                regs->gprs[14] = (__u64) frame->retcode | PSW32_ADDR_AMODE;
                 err |= __put_user(S390_SYSCALL_OPCODE | __NR_rt_sigreturn,
                                   (u16 __force __user *)(frame->retcode));
         }
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 45df6d456aa..e2f847599c8 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -1578,10 +1578,15 @@ void show_code(struct pt_regs *regs)
         ptr += sprintf(ptr, "%s Code:", mode);
         hops = 0;
         while (start < end && hops < 8) {
-                *ptr++ = (start == 32) ? '>' : ' ';
+                opsize = insn_length(code[start]);
+                if  (start + opsize == 32)
+                        *ptr++ = '#';
+                else if (start == 32)
+                        *ptr++ = '>';
+                else
+                        *ptr++ = ' ';
                 addr = regs->psw.addr + start - 32;
                 ptr += sprintf(ptr, ONELONG, addr);
-                opsize = insn_length(code[start]);
                 if (start + opsize >= end)
                         break;
                 for (i = 0; i < opsize; i++)
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index c9ffe002519..52098d6dfaa 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -434,18 +434,22 @@ static void __init append_to_cmdline(size_t (*ipl_data)(char *, size_t))
         }
 }
 
-static void __init setup_boot_command_line(void)
+static inline int has_ebcdic_char(const char *str)
 {
         int i;
 
-        /* convert arch command line to ascii */
-        for (i = 0; i < ARCH_COMMAND_LINE_SIZE; i++)
-                if (COMMAND_LINE[i] & 0x80)
-                        break;
-        if (i < ARCH_COMMAND_LINE_SIZE)
-                EBCASC(COMMAND_LINE, ARCH_COMMAND_LINE_SIZE);
-        COMMAND_LINE[ARCH_COMMAND_LINE_SIZE-1] = 0;
+        for (i = 0; str[i]; i++)
+                if (str[i] & 0x80)
+                        return 1;
+        return 0;
+}
 
+static void __init setup_boot_command_line(void)
+{
+        COMMAND_LINE[ARCH_COMMAND_LINE_SIZE - 1] = 0;
+        /* convert arch command line to ascii if necessary */
+        if (has_ebcdic_char(COMMAND_LINE))
+                EBCASC(COMMAND_LINE, ARCH_COMMAND_LINE_SIZE);
         /* copy arch command line */
         strlcpy(boot_command_line, strstrip(COMMAND_LINE),
                 ARCH_COMMAND_LINE_SIZE);
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index b13157057e0..3705700ed37 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -19,32 +19,22 @@
 #include <asm/unistd.h>
 #include <asm/page.h>
 
-/*
- * Stack layout for the system_call stack entry.
- * The first few entries are identical to the user_regs_struct.
- */
-SP_PTREGS    =  STACK_FRAME_OVERHEAD
-SP_ARGS      =  STACK_FRAME_OVERHEAD + __PT_ARGS
-SP_PSW       =  STACK_FRAME_OVERHEAD + __PT_PSW
-SP_R0        =  STACK_FRAME_OVERHEAD + __PT_GPRS
-SP_R1        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 4
-SP_R2        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 8
-SP_R3        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 12
-SP_R4        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 16
-SP_R5        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 20
-SP_R6        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 24
-SP_R7        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 28
-SP_R8        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 32
-SP_R9        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 36
-SP_R10       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 40
-SP_R11       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 44
-SP_R12       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 48
-SP_R13       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 52
-SP_R14       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 56
-SP_R15       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 60
-SP_ORIG_R2   =  STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
-SP_SVC_CODE  =  STACK_FRAME_OVERHEAD + __PT_SVC_CODE
-SP_SIZE      =  STACK_FRAME_OVERHEAD + __PT_SIZE
+__PT_R0      =  __PT_GPRS
+__PT_R1      =  __PT_GPRS + 4
+__PT_R2      =  __PT_GPRS + 8
+__PT_R3      =  __PT_GPRS + 12
+__PT_R4      =  __PT_GPRS + 16
+__PT_R5      =  __PT_GPRS + 20
+__PT_R6      =  __PT_GPRS + 24
+__PT_R7      =  __PT_GPRS + 28
+__PT_R8      =  __PT_GPRS + 32
+__PT_R9      =  __PT_GPRS + 36
+__PT_R10     =  __PT_GPRS + 40
+__PT_R11     =  __PT_GPRS + 44
+__PT_R12     =  __PT_GPRS + 48
+__PT_R13     =  __PT_GPRS + 524
+__PT_R14     =  __PT_GPRS + 56
+__PT_R15     =  __PT_GPRS + 60
 
 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING | _TIF_PER_TRAP )
@@ -58,133 +48,91 @@ STACK_SIZE  = 1 << STACK_SHIFT
 
 #define BASED(name) name-system_call(%r13)
 
-#ifdef CONFIG_TRACE_IRQFLAGS
         .macro  TRACE_IRQS_ON
+#ifdef CONFIG_TRACE_IRQFLAGS
         basr    %r2,%r0
-        l       %r1,BASED(.Ltrace_irq_on_caller)
-        basr    %r14,%r1
+        l       %r1,BASED(.Lhardirqs_on)
+        basr    %r14,%r1                # call trace_hardirqs_on_caller
+#endif
         .endm
 
         .macro  TRACE_IRQS_OFF
+#ifdef CONFIG_TRACE_IRQFLAGS
         basr    %r2,%r0
-        l       %r1,BASED(.Ltrace_irq_off_caller)
-        basr    %r14,%r1
-        .endm
-#else
-#define TRACE_IRQS_ON
-#define TRACE_IRQS_OFF
+        l       %r1,BASED(.Lhardirqs_off)
+        basr    %r14,%r1                # call trace_hardirqs_off_caller
 #endif
+        .endm
 
-#ifdef CONFIG_LOCKDEP
         .macro  LOCKDEP_SYS_EXIT
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
-        jz      0f
+#ifdef CONFIG_LOCKDEP
+        tm      __PT_PSW+1(%r11),0x01   # returning to user ?
+        jz      .+10
         l       %r1,BASED(.Llockdep_sys_exit)
-        basr    %r14,%r1
-0:
-        .endm
-#else
-#define LOCKDEP_SYS_EXIT
+        basr    %r14,%r1                # call lockdep_sys_exit
 #endif
-
-/*
- * Register usage in interrupt handlers:
- *    R9  - pointer to current task structure
- *    R13 - pointer to literal pool
- *    R14 - return register for function calls
- *    R15 - kernel stack pointer
- */
-
-        .macro  UPDATE_VTIME lc_from,lc_to,lc_sum
-        lm      %r10,%r11,\lc_from
-        sl      %r10,\lc_to
-        sl      %r11,\lc_to+4
-        bc      3,BASED(0f)
-        sl      %r10,BASED(.Lc_1)
-0:      al      %r10,\lc_sum
-        al      %r11,\lc_sum+4
-        bc      12,BASED(1f)
-        al      %r10,BASED(.Lc_1)
-1:      stm     %r10,%r11,\lc_sum
-        .endm
-
-        .macro  SAVE_ALL_SVC psworg,savearea
-        stm     %r12,%r15,\savearea
-        l       %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
-        l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
-        s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
-        .endm
-
-        .macro  SAVE_ALL_BASE savearea
-        stm     %r12,%r15,\savearea
-        l       %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
         .endm
 
-        .macro  SAVE_ALL_PGM psworg,savearea
-        tm      \psworg+1,0x01          # test problem state bit
+        .macro  CHECK_STACK stacksize,savearea
 #ifdef CONFIG_CHECK_STACK
-        bnz     BASED(1f)
-        tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
-        bnz     BASED(2f)
-        la      %r12,\psworg
-        b       BASED(stack_overflow)
-#else
-        bz      BASED(2f)
+        tml     %r15,\stacksize - CONFIG_STACK_GUARD
+        la      %r14,\savearea
+        jz      stack_overflow
 #endif
-1:      l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
-2:      s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
         .endm
 
-        .macro  SAVE_ALL_ASYNC psworg,savearea
-        stm     %r12,%r15,\savearea
-        l       %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
-        la      %r12,\psworg
-        tm      \psworg+1,0x01          # test problem state bit
-        bnz     BASED(1f)               # from user -> load async stack
-        clc     \psworg+4(4),BASED(.Lcritical_end)
-        bhe     BASED(0f)
-        clc     \psworg+4(4),BASED(.Lcritical_start)
-        bl      BASED(0f)
-        l       %r14,BASED(.Lcleanup_critical)
-        basr    %r14,%r14
-        tm      1(%r12),0x01            # retest problem state after cleanup
-        bnz     BASED(1f)
-0:      l       %r14,__LC_ASYNC_STACK   # are we already on the async stack ?
+        .macro  SWITCH_ASYNC savearea,stack,shift
+        tmh     %r8,0x0001              # interrupting from user ?
+        jnz     1f
+        lr      %r14,%r9
+        sl      %r14,BASED(.Lcritical_start)
+        cl      %r14,BASED(.Lcritical_length)
+        jhe     0f
+        la      %r11,\savearea          # inside critical section, do cleanup
+        bras    %r14,cleanup_critical
+        tmh     %r8,0x0001              # retest problem state after cleanup
+        jnz     1f
+0:      l       %r14,\stack             # are we already on the target stack?
         slr     %r14,%r15
-        sra     %r14,STACK_SHIFT
-#ifdef CONFIG_CHECK_STACK
-        bnz     BASED(1f)
-        tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
-        bnz     BASED(2f)
-        b       BASED(stack_overflow)
-#else
-        bz      BASED(2f)
-#endif
-1:      l       %r15,__LC_ASYNC_STACK
-2:      s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
+        sra     %r14,\shift
+        jnz     1f
+        CHECK_STACK 1<<\shift,\savearea
+        j       2f
+1:      l       %r15,\stack             # load target stack
+2:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
         .endm
 
-        .macro  CREATE_STACK_FRAME savearea
-        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
-        st      %r2,SP_ORIG_R2(%r15)    # store original content of gpr 2
-        mvc     SP_R12(16,%r15),\savearea # move %r12-%r15 to stack
-        stm     %r0,%r11,SP_R0(%r15)    # store gprs %r0-%r11 to kernel stack
+        .macro  ADD64 high,low,timer
+        al      \high,\timer
+        al      \low,\timer+4
+        brc     12,.+8
+        ahi     \high,1
         .endm
 
-        .macro  RESTORE_ALL psworg,sync
-        mvc     \psworg(8),SP_PSW(%r15) # move user PSW to lowcore
-        .if !\sync
-        ni      \psworg+1,0xfd          # clear wait state bit
-        .endif
-        lm      %r0,%r15,SP_R0(%r15)    # load gprs 0-15 of user
-        stpt    __LC_EXIT_TIMER
-        lpsw    \psworg                 # back to caller
+        .macro  SUB64 high,low,timer
+        sl      \high,\timer
+        sl      \low,\timer+4
+        brc     3,.+8
+        ahi     \high,-1
+        .endm
+
+        .macro  UPDATE_VTIME high,low,enter_timer
+        lm      \high,\low,__LC_EXIT_TIMER
+        SUB64   \high,\low,\enter_timer
+        ADD64   \high,\low,__LC_USER_TIMER
+        stm     \high,\low,__LC_USER_TIMER
+        lm      \high,\low,__LC_LAST_UPDATE_TIMER
+        SUB64   \high,\low,__LC_EXIT_TIMER
+        ADD64   \high,\low,__LC_SYSTEM_TIMER
+        stm     \high,\low,__LC_SYSTEM_TIMER
+        mvc     __LC_LAST_UPDATE_TIMER(8),\enter_timer
         .endm
 
         .macro REENABLE_IRQS
-        mvc     __SF_EMPTY(1,%r15),SP_PSW(%r15)
-        ni      __SF_EMPTY(%r15),0xbf
-        ssm     __SF_EMPTY(%r15)
+        st      %r8,__LC_RETURN_PSW
+        ni      __LC_RETURN_PSW,0xbf
+        ssm     __LC_RETURN_PSW
         .endm
 
         .section .kprobes.text, "ax"
@@ -197,14 +145,13 @@ STACK_SIZE  = 1 << STACK_SHIFT
  *  gpr2 = prev
  */
 ENTRY(__switch_to)
-        basr    %r1,0
-0:      l       %r4,__THREAD_info(%r2)          # get thread_info of prev
+        l       %r4,__THREAD_info(%r2)          # get thread_info of prev
         l       %r5,__THREAD_info(%r3)          # get thread_info of next
         tm      __TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending?
-        bz      1f-0b(%r1)
+        jz      0f
         ni      __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
         oi      __TI_flags+3(%r5),_TIF_MCCK_PENDING     # set it in next
-1:      stm     %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+0:      stm     %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
         st      %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
         l       %r15,__THREAD_ksp(%r3)          # load kernel stack of next
         lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
@@ -224,48 +171,55 @@ __critical_start:
 
 ENTRY(system_call)
         stpt    __LC_SYNC_ENTER_TIMER
-sysc_saveall:
-        SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        mvc     SP_PSW(8,%r15),__LC_SVC_OLD_PSW
-        mvc     SP_SVC_CODE(4,%r15),__LC_SVC_ILC
-        oi      __TI_flags+3(%r12),_TIF_SYSCALL
+sysc_stm:
+        stm     %r8,%r15,__LC_SAVE_AREA_SYNC
+        l       %r12,__LC_THREAD_INFO
+        l       %r13,__LC_SVC_NEW_PSW+4
+sysc_per:
+        l       %r15,__LC_KERNEL_STACK
+        ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
 sysc_vtime:
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-sysc_stime:
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-sysc_update:
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
+        UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
+        stm     %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_SYNC
+        mvc     __PT_PSW(8,%r11),__LC_SVC_OLD_PSW
+        mvc     __PT_INT_CODE(4,%r11),__LC_SVC_ILC
 sysc_do_svc:
-        xr      %r7,%r7
-        icm     %r7,3,SP_SVC_CODE+2(%r15)# load svc number and test for svc 0
-        bnz     BASED(sysc_nr_ok)       # svc number > 0
+        oi      __TI_flags+3(%r12),_TIF_SYSCALL
+        lh      %r8,__PT_INT_CODE+2(%r11)
+        sla     %r8,2                           # shift and test for svc0
+        jnz     sysc_nr_ok
         # svc 0: system call number in %r1
         cl      %r1,BASED(.Lnr_syscalls)
-        bnl     BASED(sysc_nr_ok)
-        sth     %r1,SP_SVC_CODE+2(%r15)
-        lr      %r7,%r1           # copy svc number to %r7
+        jnl     sysc_nr_ok
+        sth     %r1,__PT_INT_CODE+2(%r11)
+        lr      %r8,%r1
+        sla     %r8,2
 sysc_nr_ok:
-        sll     %r7,2             # svc number *4
-        l       %r10,BASED(.Lsysc_table)
+        l       %r10,BASED(.Lsys_call_table)    # 31 bit system call table
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
+        st      %r2,__PT_ORIG_GPR2(%r11)
+        st      %r7,STACK_FRAME_OVERHEAD(%r15)
+        l       %r9,0(%r8,%r10)                 # get system call addr.
         tm      __TI_flags+2(%r12),_TIF_TRACE >> 8
-        mvc     SP_ARGS(4,%r15),SP_R7(%r15)
-        l       %r8,0(%r7,%r10)   # get system call addr.
-        bnz     BASED(sysc_tracesys)
-        basr    %r14,%r8          # call sys_xxxx
-        st      %r2,SP_R2(%r15)   # store return value (change R2 on stack)
+        jnz     sysc_tracesys
+        basr    %r14,%r9                        # call sys_xxxx
+        st      %r2,__PT_R2(%r11)               # store return value
 
 sysc_return:
         LOCKDEP_SYS_EXIT
 sysc_tif:
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
-        bno     BASED(sysc_restore)
+        tm      __PT_PSW+1(%r11),0x01           # returning to user ?
+        jno     sysc_restore
         tm      __TI_flags+3(%r12),_TIF_WORK_SVC
-        bnz     BASED(sysc_work)  # there is work to do (signals etc.)
+        jnz     sysc_work                       # check for work
         ni      __TI_flags+3(%r12),255-_TIF_SYSCALL
 sysc_restore:
-        RESTORE_ALL __LC_RETURN_PSW,1
+        mvc     __LC_RETURN_PSW(8),__PT_PSW(%r11)
+        stpt    __LC_EXIT_TIMER
+        lm      %r0,%r15,__PT_R0(%r11)
+        lpsw    __LC_RETURN_PSW
 sysc_done:
 
 #
@@ -273,16 +227,16 @@ sysc_done:
 #
 sysc_work:
         tm      __TI_flags+3(%r12),_TIF_MCCK_PENDING
-        bo      BASED(sysc_mcck_pending)
+        jo      sysc_mcck_pending
         tm      __TI_flags+3(%r12),_TIF_NEED_RESCHED
-        bo      BASED(sysc_reschedule)
+        jo      sysc_reschedule
         tm      __TI_flags+3(%r12),_TIF_SIGPENDING
-        bo      BASED(sysc_sigpending)
+        jo      sysc_sigpending
         tm      __TI_flags+3(%r12),_TIF_NOTIFY_RESUME
-        bo      BASED(sysc_notify_resume)
+        jo      sysc_notify_resume
         tm      __TI_flags+3(%r12),_TIF_PER_TRAP
-        bo      BASED(sysc_singlestep)
-        b       BASED(sysc_return)      # beware of critical section cleanup
+        jo      sysc_singlestep
+        j       sysc_return             # beware of critical section cleanup
 
 #
 # _TIF_NEED_RESCHED is set, call schedule
@@ -290,13 +244,13 @@ sysc_work:
 sysc_reschedule:
         l       %r1,BASED(.Lschedule)
         la      %r14,BASED(sysc_return)
-        br      %r1                     # call scheduler
+        br      %r1                     # call schedule
 
 #
 # _TIF_MCCK_PENDING is set, call handler
 #
 sysc_mcck_pending:
-        l       %r1,BASED(.Ls390_handle_mcck)
+        l       %r1,BASED(.Lhandle_mcck)
         la      %r14,BASED(sysc_return)
         br      %r1                     # TIF bit will be cleared by handler
 
@@ -305,23 +259,24 @@ sysc_mcck_pending:
 #
 sysc_sigpending:
         ni      __TI_flags+3(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        lr      %r2,%r11                # pass pointer to pt_regs
         l       %r1,BASED(.Ldo_signal)
         basr    %r14,%r1                # call do_signal
         tm      __TI_flags+3(%r12),_TIF_SYSCALL
-        bno     BASED(sysc_return)
-        lm      %r2,%r6,SP_R2(%r15)     # load svc arguments
-        xr      %r7,%r7                 # svc 0 returns -ENOSYS
-        clc     SP_SVC_CODE+2(2,%r15),BASED(.Lnr_syscalls+2)
-        bnl     BASED(sysc_nr_ok)       # invalid svc number -> do svc 0
-        icm     %r7,3,SP_SVC_CODE+2(%r15)# load new svc number
-        b       BASED(sysc_nr_ok)       # restart svc
+        jno     sysc_return
+        lm      %r2,%r7,__PT_R2(%r11)   # load svc arguments
+        xr      %r8,%r8                 # svc 0 returns -ENOSYS
+        clc     __PT_INT_CODE+2(2,%r11),BASED(.Lnr_syscalls+2)
+        jnl     sysc_nr_ok              # invalid svc number -> do svc 0
+        lh      %r8,__PT_INT_CODE+2(%r11)       # load new svc number
+        sla     %r8,2
+        j       sysc_nr_ok              # restart svc
 
 #
 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
 #
 sysc_notify_resume:
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        lr      %r2,%r11                # pass pointer to pt_regs
         l       %r1,BASED(.Ldo_notify_resume)
         la      %r14,BASED(sysc_return)
         br      %r1                     # call do_notify_resume
@@ -331,56 +286,57 @@ sysc_notify_resume:
 #
 sysc_singlestep:
         ni      __TI_flags+3(%r12),255-(_TIF_SYSCALL | _TIF_PER_TRAP)
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        l       %r1,BASED(.Lhandle_per) # load adr. of per handler
-        la      %r14,BASED(sysc_return) # load adr. of system return
-        br      %r1                     # branch to do_per_trap
+        lr      %r2,%r11                # pass pointer to pt_regs
+        l       %r1,BASED(.Ldo_per_trap)
+        la      %r14,BASED(sysc_return)
+        br      %r1                     # call do_per_trap
 
 #
 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
 # and after the system call
 #
 sysc_tracesys:
-        l       %r1,BASED(.Ltrace_entry)
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        l       %r1,BASED(.Ltrace_enter)
+        lr      %r2,%r11                # pass pointer to pt_regs
         la      %r3,0
         xr      %r0,%r0
-        icm     %r0,3,SP_SVC_CODE(%r15)
-        st      %r0,SP_R2(%r15)
-        basr    %r14,%r1
+        icm     %r0,3,__PT_INT_CODE+2(%r11)
+        st      %r0,__PT_R2(%r11)
+        basr    %r14,%r1                # call do_syscall_trace_enter
         cl      %r2,BASED(.Lnr_syscalls)
-        bnl     BASED(sysc_tracenogo)
-        lr      %r7,%r2
-        sll     %r7,2                   # svc number *4
-        l       %r8,0(%r7,%r10)
+        jnl     sysc_tracenogo
+        lr      %r8,%r2
+        sll     %r8,2
+        l       %r9,0(%r8,%r10)
 sysc_tracego:
-        lm      %r3,%r6,SP_R3(%r15)
-        mvc     SP_ARGS(4,%r15),SP_R7(%r15)
-        l       %r2,SP_ORIG_R2(%r15)
-        basr    %r14,%r8                # call sys_xxx
-        st      %r2,SP_R2(%r15)         # store return value
+        lm      %r3,%r7,__PT_R3(%r11)
+        st      %r7,STACK_FRAME_OVERHEAD(%r15)
+        l       %r2,__PT_ORIG_GPR2(%r11)
+        basr    %r14,%r9                # call sys_xxx
+        st      %r2,__PT_R2(%r11)       # store return value
 sysc_tracenogo:
         tm      __TI_flags+2(%r12),_TIF_TRACE >> 8
-        bz      BASED(sysc_return)
+        jz      sysc_return
         l       %r1,BASED(.Ltrace_exit)
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        lr      %r2,%r11                # pass pointer to pt_regs
         la      %r14,BASED(sysc_return)
-        br      %r1
+        br      %r1                     # call do_syscall_trace_exit
 
 #
 # a new process exits the kernel with ret_from_fork
 #
 ENTRY(ret_from_fork)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        l       %r12,__LC_THREAD_INFO
         l       %r13,__LC_SVC_NEW_PSW+4
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      SP_PSW+1(%r15),0x01     # forking a kernel thread ?
-        bo      BASED(0f)
-        st      %r15,SP_R15(%r15)       # store stack pointer for new kthread
-0:      l       %r1,BASED(.Lschedtail)
-        basr    %r14,%r1
+        tm      __PT_PSW+1(%r11),0x01   # forking a kernel thread ?
+        jo      0f
+        st      %r15,__PT_R15(%r11)     # store stack pointer for new kthread
+0:      l       %r1,BASED(.Lschedule_tail)
+        basr    %r14,%r1                # call schedule_tail
         TRACE_IRQS_ON
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        b       BASED(sysc_tracenogo)
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
+        j       sysc_tracenogo
 
 #
 # kernel_execve function needs to deal with pt_regs that is not
@@ -390,153 +346,98 @@ ENTRY(kernel_execve)
         stm     %r12,%r15,48(%r15)
         lr      %r14,%r15
         l       %r13,__LC_SVC_NEW_PSW+4
-        s       %r15,BASED(.Lc_spsize)
+        ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         st      %r14,__SF_BACKCHAIN(%r15)
-        la      %r12,SP_PTREGS(%r15)
+        la      %r12,STACK_FRAME_OVERHEAD(%r15)
         xc      0(__PT_SIZE,%r12),0(%r12)
         l       %r1,BASED(.Ldo_execve)
         lr      %r5,%r12
-        basr    %r14,%r1
+        basr    %r14,%r1                # call do_execve
         ltr     %r2,%r2
-        be      BASED(0f)
-        a       %r15,BASED(.Lc_spsize)
+        je      0f
+        ahi     %r15,(STACK_FRAME_OVERHEAD + __PT_SIZE)
         lm      %r12,%r15,48(%r15)
         br      %r14
         # execve succeeded.
-0:      stnsm   __SF_EMPTY(%r15),0xfc   # disable interrupts
+0:      ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         l       %r15,__LC_KERNEL_STACK  # load ksp
-        s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
-        mvc     SP_PTREGS(__PT_SIZE,%r15),0(%r12)       # copy pt_regs
+        ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        mvc     0(__PT_SIZE,%r11),0(%r12)       # copy pt_regs
         l       %r12,__LC_THREAD_INFO
         xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
         l       %r1,BASED(.Lexecve_tail)
-        basr    %r14,%r1
-        b       BASED(sysc_return)
+        basr    %r14,%r1                # call execve_tail
+        j       sysc_return
 
 /*
  * Program check handler routine
  */
 
 ENTRY(pgm_check_handler)
-/*
- * First we need to check for a special case:
- * Single stepping an instruction that disables the PER event mask will
- * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
- * For a single stepped SVC the program check handler gets control after
- * the SVC new PSW has been loaded. But we want to execute the SVC first and
- * then handle the PER event. Therefore we update the SVC old PSW to point
- * to the pgm_check_handler and branch to the SVC handler after we checked
- * if we have to load the kernel stack register.
- * For every other possible cause for PER event without the PER mask set
- * we just ignore the PER event (FIXME: is there anything we have to do
- * for LPSW?).
- */
         stpt    __LC_SYNC_ENTER_TIMER
-        SAVE_ALL_BASE __LC_SAVE_AREA
-        tm      __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
-        bnz     BASED(pgm_per)          # got per exception -> special case
-        SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        mvc     SP_PSW(8,%r15),__LC_PGM_OLD_PSW
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        bz      BASED(pgm_no_vtime)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-pgm_no_vtime:
-        l       %r3,__LC_PGM_ILC        # load program interruption code
-        l       %r4,__LC_TRANS_EXC_CODE
-        REENABLE_IRQS
-        la      %r8,0x7f
-        nr      %r8,%r3
-        sll     %r8,2
-        l       %r1,BASED(.Ljump_table)
-        l       %r1,0(%r8,%r1)          # load address of handler routine
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        basr    %r14,%r1                # branch to interrupt-handler
-pgm_exit:
-        b       BASED(sysc_return)
-
-#
-# handle per exception
-#
-pgm_per:
-        tm      __LC_PGM_OLD_PSW,0x40   # test if per event recording is on
-        bnz     BASED(pgm_per_std)      # ok, normal per event from user space
-# ok its one of the special cases, now we need to find out which one
-        clc     __LC_PGM_OLD_PSW(8),__LC_SVC_NEW_PSW
-        be      BASED(pgm_svcper)
-# no interesting special case, ignore PER event
-        lm      %r12,%r15,__LC_SAVE_AREA
-        lpsw    0x28
-
-#
-# Normal per exception
-#
-pgm_per_std:
-        SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        mvc     SP_PSW(8,%r15),__LC_PGM_OLD_PSW
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        bz      BASED(pgm_no_vtime2)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-pgm_no_vtime2:
+        stm     %r8,%r15,__LC_SAVE_AREA_SYNC
+        l       %r12,__LC_THREAD_INFO
+        l       %r13,__LC_SVC_NEW_PSW+4
+        lm      %r8,%r9,__LC_PGM_OLD_PSW
+        tmh     %r8,0x0001              # test problem state bit
+        jnz     1f                      # -> fault in user space
+        tmh     %r8,0x4000              # PER bit set in old PSW ?
+        jnz     0f                      # -> enabled, can't be a double fault
+        tm      __LC_PGM_ILC+3,0x80     # check for per exception
+        jnz     pgm_svcper              # -> single stepped svc
+0:      CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
+        j       2f
+1:      UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
+        l       %r15,__LC_KERNEL_STACK
+2:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        stm     %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_SYNC
+        stm     %r8,%r9,__PT_PSW(%r11)
+        mvc     __PT_INT_CODE(4,%r11),__LC_PGM_ILC
+        mvc     __PT_INT_PARM_LONG(4,%r11),__LC_TRANS_EXC_CODE
+        tm      __LC_PGM_ILC+3,0x80     # check for per exception
+        jz      0f
         l       %r1,__TI_task(%r12)
-        tm      SP_PSW+1(%r15),0x01     # kernel per event ?
-        bz      BASED(kernel_per)
-        mvc     __THREAD_per_cause(2,%r1),__LC_PER_CAUSE
+        tmh     %r8,0x0001              # kernel per event ?
+        jz      pgm_kprobe
+        oi      __TI_flags+3(%r12),_TIF_PER_TRAP
         mvc     __THREAD_per_address(4,%r1),__LC_PER_ADDRESS
+        mvc     __THREAD_per_cause(2,%r1),__LC_PER_CAUSE
         mvc     __THREAD_per_paid(1,%r1),__LC_PER_PAID
-        oi      __TI_flags+3(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP
-        l       %r3,__LC_PGM_ILC        # load program interruption code
-        l       %r4,__LC_TRANS_EXC_CODE
-        REENABLE_IRQS
-        la      %r8,0x7f
-        nr      %r8,%r3                 # clear per-event-bit and ilc
-        be      BASED(pgm_exit2)        # only per or per+check ?
-        sll     %r8,2
+0:      REENABLE_IRQS
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
         l       %r1,BASED(.Ljump_table)
-        l       %r1,0(%r8,%r1)          # load address of handler routine
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
+        la      %r10,0x7f
+        n       %r10,__PT_INT_CODE(%r11)
+        je      sysc_return
+        sll     %r10,2
+        l       %r1,0(%r10,%r1)         # load address of handler routine
+        lr      %r2,%r11                # pass pointer to pt_regs
         basr    %r14,%r1                # branch to interrupt-handler
-pgm_exit2:
-        b       BASED(sysc_return)
+        j       sysc_return
 
 #
-# it was a single stepped SVC that is causing all the trouble
+# PER event in supervisor state, must be kprobes
 #
-pgm_svcper:
-        SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        mvc     SP_PSW(8,%r15),__LC_SVC_OLD_PSW
-        mvc     SP_SVC_CODE(4,%r15),__LC_SVC_ILC
-        oi      __TI_flags+3(%r12),(_TIF_SYSCALL | _TIF_PER_TRAP)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        l       %r8,__TI_task(%r12)
-        mvc     __THREAD_per_cause(2,%r8),__LC_PER_CAUSE
-        mvc     __THREAD_per_address(4,%r8),__LC_PER_ADDRESS
-        mvc     __THREAD_per_paid(1,%r8),__LC_PER_PAID
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        lm      %r2,%r6,SP_R2(%r15)     # load svc arguments
-        b       BASED(sysc_do_svc)
+pgm_kprobe:
+        REENABLE_IRQS
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
+        l       %r1,BASED(.Ldo_per_trap)
+        lr      %r2,%r11                # pass pointer to pt_regs
+        basr    %r14,%r1                # call do_per_trap
+        j       sysc_return
 
 #
-# per was called from kernel, must be kprobes
+# single stepped system call
 #
-kernel_per:
-        REENABLE_IRQS
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        l       %r1,BASED(.Lhandle_per) # load adr. of per handler
-        basr    %r14,%r1                # branch to do_single_step
-        b       BASED(pgm_exit)
+pgm_svcper:
+        oi      __TI_flags+3(%r12),_TIF_PER_TRAP
+        mvc     __LC_RETURN_PSW(4),__LC_SVC_NEW_PSW
+        mvc     __LC_RETURN_PSW+4(4),BASED(.Lsysc_per)
+        lpsw    __LC_RETURN_PSW         # branch to sysc_per and enable irqs
 
 /*
  * IO interrupt handler routine
@@ -545,28 +446,35 @@ kernel_per:
 ENTRY(io_int_handler)
         stck    __LC_INT_CLOCK
         stpt    __LC_ASYNC_ENTER_TIMER
-        SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+16
-        CREATE_STACK_FRAME __LC_SAVE_AREA+16
-        mvc     SP_PSW(8,%r15),0(%r12)  # move user PSW to stack
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        bz      BASED(io_no_vtime)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
-io_no_vtime:
+        stm     %r8,%r15,__LC_SAVE_AREA_ASYNC
+        l       %r12,__LC_THREAD_INFO
+        l       %r13,__LC_SVC_NEW_PSW+4
+        lm      %r8,%r9,__LC_IO_OLD_PSW
+        tmh     %r8,0x0001              # interrupting from user ?
+        jz      io_skip
+        UPDATE_VTIME %r14,%r15,__LC_ASYNC_ENTER_TIMER
+io_skip:
+        SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_STACK,STACK_SHIFT
+        stm     %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_ASYNC
+        stm     %r8,%r9,__PT_PSW(%r11)
         TRACE_IRQS_OFF
-        l       %r1,BASED(.Ldo_IRQ)     # load address of do_IRQ
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        basr    %r14,%r1                # branch to standard irq handler
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
+        l       %r1,BASED(.Ldo_IRQ)
+        lr      %r2,%r11                # pass pointer to pt_regs
+        basr    %r14,%r1                # call do_IRQ
 io_return:
         LOCKDEP_SYS_EXIT
         TRACE_IRQS_ON
 io_tif:
         tm      __TI_flags+3(%r12),_TIF_WORK_INT
-        bnz     BASED(io_work)          # there is work to do (signals etc.)
+        jnz     io_work                 # there is work to do (signals etc.)
 io_restore:
-        RESTORE_ALL __LC_RETURN_PSW,0
+        mvc     __LC_RETURN_PSW(8),__PT_PSW(%r11)
+        ni      __LC_RETURN_PSW+1,0xfd  # clean wait state bit
+        stpt    __LC_EXIT_TIMER
+        lm      %r0,%r15,__PT_R0(%r11)
+        lpsw    __LC_RETURN_PSW
 io_done:
 
 #
@@ -577,28 +485,29 @@ io_done:
 # Before any work can be done, a switch to the kernel stack is required.
 #
 io_work:
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
-        bo      BASED(io_work_user)     # yes -> do resched & signal
+        tm      __PT_PSW+1(%r11),0x01   # returning to user ?
+        jo      io_work_user            # yes -> do resched & signal
 #ifdef CONFIG_PREEMPT
         # check for preemptive scheduling
         icm     %r0,15,__TI_precount(%r12)
-        bnz     BASED(io_restore)       # preemption disabled
+        jnz     io_restore              # preemption disabled
         tm      __TI_flags+3(%r12),_TIF_NEED_RESCHED
-        bno     BASED(io_restore)
+        jno     io_restore
         # switch to kernel stack
-        l       %r1,SP_R15(%r15)
-        s       %r1,BASED(.Lc_spsize)
-        mvc     SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
-        xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain
+        l       %r1,__PT_R15(%r11)
+        ahi     %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
+        xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1)
+        la      %r11,STACK_FRAME_OVERHEAD(%r1)
         lr      %r15,%r1
         # TRACE_IRQS_ON already done at io_return, call
         # TRACE_IRQS_OFF to keep things symmetrical
         TRACE_IRQS_OFF
-        l       %r1,BASED(.Lpreempt_schedule_irq)
+        l       %r1,BASED(.Lpreempt_irq)
         basr    %r14,%r1                # call preempt_schedule_irq
-        b       BASED(io_return)
+        j       io_return
 #else
-        b       BASED(io_restore)
+        j       io_restore
 #endif
 
 #
@@ -606,9 +515,10 @@ io_work:
 #
 io_work_user:
         l       %r1,__LC_KERNEL_STACK
-        s       %r1,BASED(.Lc_spsize)
-        mvc     SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
-        xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain
+        ahi     %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
+        xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1)
+        la      %r11,STACK_FRAME_OVERHEAD(%r1)
         lr      %r15,%r1
 
 #
@@ -618,24 +528,24 @@ io_work_user:
 #
 io_work_tif:
         tm      __TI_flags+3(%r12),_TIF_MCCK_PENDING
-        bo      BASED(io_mcck_pending)
+        jo      io_mcck_pending
         tm      __TI_flags+3(%r12),_TIF_NEED_RESCHED
-        bo      BASED(io_reschedule)
+        jo      io_reschedule
         tm      __TI_flags+3(%r12),_TIF_SIGPENDING
-        bo      BASED(io_sigpending)
+        jo      io_sigpending
         tm      __TI_flags+3(%r12),_TIF_NOTIFY_RESUME
-        bo      BASED(io_notify_resume)
-        b       BASED(io_return)        # beware of critical section cleanup
+        jo      io_notify_resume
+        j       io_return               # beware of critical section cleanup
 
 #
 # _TIF_MCCK_PENDING is set, call handler
 #
 io_mcck_pending:
         # TRACE_IRQS_ON already done at io_return
-        l       %r1,BASED(.Ls390_handle_mcck)
+        l       %r1,BASED(.Lhandle_mcck)
         basr    %r14,%r1                # TIF bit will be cleared by handler
         TRACE_IRQS_OFF
-        b       BASED(io_return)
+        j       io_return
 
 #
 # _TIF_NEED_RESCHED is set, call schedule
@@ -643,37 +553,37 @@ io_mcck_pending:
 io_reschedule:
         # TRACE_IRQS_ON already done at io_return
         l       %r1,BASED(.Lschedule)
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
         basr    %r14,%r1                # call scheduler
-        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         TRACE_IRQS_OFF
-        b       BASED(io_return)
+        j       io_return
 
 #
 # _TIF_SIGPENDING is set, call do_signal
 #
 io_sigpending:
         # TRACE_IRQS_ON already done at io_return
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
         l       %r1,BASED(.Ldo_signal)
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
+        lr      %r2,%r11                # pass pointer to pt_regs
         basr    %r14,%r1                # call do_signal
-        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         TRACE_IRQS_OFF
-        b       BASED(io_return)
+        j       io_return
 
 #
 # _TIF_SIGPENDING is set, call do_signal
 #
 io_notify_resume:
         # TRACE_IRQS_ON already done at io_return
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
         l       %r1,BASED(.Ldo_notify_resume)
-        basr    %r14,%r1                # call do_signal
-        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
+        lr      %r2,%r11                # pass pointer to pt_regs
+        basr    %r14,%r1                # call do_notify_resume
+        ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         TRACE_IRQS_OFF
-        b       BASED(io_return)
+        j       io_return
 
 /*
  * External interrupt handler routine
@@ -682,23 +592,25 @@ io_notify_resume:
 ENTRY(ext_int_handler)
         stck    __LC_INT_CLOCK
         stpt    __LC_ASYNC_ENTER_TIMER
-        SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16
-        CREATE_STACK_FRAME __LC_SAVE_AREA+16
-        mvc     SP_PSW(8,%r15),0(%r12)  # move user PSW to stack
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        bz      BASED(ext_no_vtime)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
-ext_no_vtime:
+        stm     %r8,%r15,__LC_SAVE_AREA_ASYNC
+        l       %r12,__LC_THREAD_INFO
+        l       %r13,__LC_SVC_NEW_PSW+4
+        lm      %r8,%r9,__LC_EXT_OLD_PSW
+        tmh     %r8,0x0001              # interrupting from user ?
+        jz      ext_skip
+        UPDATE_VTIME %r14,%r15,__LC_ASYNC_ENTER_TIMER
+ext_skip:
+        SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_STACK,STACK_SHIFT
+        stm     %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_ASYNC
+        stm     %r8,%r9,__PT_PSW(%r11)
         TRACE_IRQS_OFF
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
+        lr      %r2,%r11                # pass pointer to pt_regs
         l       %r3,__LC_CPU_ADDRESS    # get cpu address + interruption code
         l       %r4,__LC_EXT_PARAMS     # get external parameters
         l       %r1,BASED(.Ldo_extint)
-        basr    %r14,%r1
-        b       BASED(io_return)
+        basr    %r14,%r1                # call do_extint
+        j       io_return
 
 __critical_end:
 
@@ -710,82 +622,74 @@ ENTRY(mcck_int_handler)
         stck    __LC_MCCK_CLOCK
         spt     __LC_CPU_TIMER_SAVE_AREA        # revalidate cpu timer
         lm      %r0,%r15,__LC_GPREGS_SAVE_AREA  # revalidate gprs
-        SAVE_ALL_BASE __LC_SAVE_AREA+32
-        la      %r12,__LC_MCK_OLD_PSW
+        l       %r12,__LC_THREAD_INFO
+        l       %r13,__LC_SVC_NEW_PSW+4
+        lm      %r8,%r9,__LC_MCK_OLD_PSW
         tm      __LC_MCCK_CODE,0x80     # system damage?
-        bo      BASED(mcck_int_main)    # yes -> rest of mcck code invalid
-        mvc     __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA
+        jo      mcck_panic              # yes -> rest of mcck code invalid
+        la      %r14,__LC_CPU_TIMER_SAVE_AREA
+        mvc     __LC_MCCK_ENTER_TIMER(8),0(%r14)
         tm      __LC_MCCK_CODE+5,0x02   # stored cpu timer value valid?
-        bo      BASED(1f)
+        jo      3f
         la      %r14,__LC_SYNC_ENTER_TIMER
         clc     0(8,%r14),__LC_ASYNC_ENTER_TIMER
-        bl      BASED(0f)
+        jl      0f
         la      %r14,__LC_ASYNC_ENTER_TIMER
 0:      clc     0(8,%r14),__LC_EXIT_TIMER
-        bl      BASED(0f)
+        jl      1f
         la      %r14,__LC_EXIT_TIMER
-0:      clc     0(8,%r14),__LC_LAST_UPDATE_TIMER
-        bl      BASED(0f)
+1:      clc     0(8,%r14),__LC_LAST_UPDATE_TIMER
+        jl      2f
         la      %r14,__LC_LAST_UPDATE_TIMER
-0:      spt     0(%r14)
+2:      spt     0(%r14)
         mvc     __LC_MCCK_ENTER_TIMER(8),0(%r14)
-1:      tm      __LC_MCCK_CODE+2,0x09   # mwp + ia of old psw valid?
-        bno     BASED(mcck_int_main)    # no -> skip cleanup critical
-        tm      __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
-        bnz     BASED(mcck_int_main)    # from user -> load async stack
-        clc     __LC_MCK_OLD_PSW+4(4),BASED(.Lcritical_end)
-        bhe     BASED(mcck_int_main)
-        clc     __LC_MCK_OLD_PSW+4(4),BASED(.Lcritical_start)
-        bl      BASED(mcck_int_main)
-        l       %r14,BASED(.Lcleanup_critical)
-        basr    %r14,%r14
-mcck_int_main:
-        l       %r14,__LC_PANIC_STACK   # are we already on the panic stack?
-        slr     %r14,%r15
-        sra     %r14,PAGE_SHIFT
-        be      BASED(0f)
-        l       %r15,__LC_PANIC_STACK   # load panic stack
-0:      s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
-        CREATE_STACK_FRAME __LC_SAVE_AREA+32
-        mvc     SP_PSW(8,%r15),0(%r12)
-        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      __LC_MCCK_CODE+2,0x08   # mwp of old psw valid?
-        bno     BASED(mcck_no_vtime)    # no -> skip cleanup critical
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        bz      BASED(mcck_no_vtime)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
-mcck_no_vtime:
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        l       %r1,BASED(.Ls390_mcck)
-        basr    %r14,%r1                # call machine check handler
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
-        bno     BASED(mcck_return)
+3:      tm      __LC_MCCK_CODE+2,0x09   # mwp + ia of old psw valid?
+        jno     mcck_panic              # no -> skip cleanup critical
+        tm      %r8,0x0001              # interrupting from user ?
+        jz      mcck_skip
+        UPDATE_VTIME %r14,%r15,__LC_MCCK_ENTER_TIMER
+mcck_skip:
+        SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+32,__LC_PANIC_STACK,PAGE_SHIFT
+        mvc     __PT_R0(64,%r11),__LC_GPREGS_SAVE_AREA
+        stm     %r8,%r9,__PT_PSW(%r11)
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
+        l       %r1,BASED(.Ldo_machine_check)
+        lr      %r2,%r11                # pass pointer to pt_regs
+        basr    %r14,%r1                # call s390_do_machine_check
+        tm      __PT_PSW+1(%r11),0x01   # returning to user ?
+        jno     mcck_return
         l       %r1,__LC_KERNEL_STACK   # switch to kernel stack
-        s       %r1,BASED(.Lc_spsize)
-        mvc     SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
-        xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain
+        ahi     %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
+        xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
         lr      %r15,%r1
-        stosm   __SF_EMPTY(%r15),0x04   # turn dat on
+        ssm     __LC_PGM_NEW_PSW        # turn dat on, keep irqs off
         tm      __TI_flags+3(%r12),_TIF_MCCK_PENDING
-        bno     BASED(mcck_return)
+        jno     mcck_return
         TRACE_IRQS_OFF
-        l       %r1,BASED(.Ls390_handle_mcck)
-        basr    %r14,%r1                # call machine check handler
+        l       %r1,BASED(.Lhandle_mcck)
+        basr    %r14,%r1                # call s390_handle_mcck
         TRACE_IRQS_ON
 mcck_return:
-        mvc     __LC_RETURN_MCCK_PSW(8),SP_PSW(%r15) # move return PSW
+        mvc     __LC_RETURN_MCCK_PSW(8),__PT_PSW(%r11) # move return PSW
         ni      __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
         tm      __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
-        bno     BASED(0f)
-        lm      %r0,%r15,SP_R0(%r15)    # load gprs 0-15
+        jno     0f
+        lm      %r0,%r15,__PT_R0(%r11)
         stpt    __LC_EXIT_TIMER
-        lpsw    __LC_RETURN_MCCK_PSW    # back to caller
-0:      lm      %r0,%r15,SP_R0(%r15)    # load gprs 0-15
-        lpsw    __LC_RETURN_MCCK_PSW    # back to caller
+        lpsw    __LC_RETURN_MCCK_PSW
+0:      lm      %r0,%r15,__PT_R0(%r11)
+        lpsw    __LC_RETURN_MCCK_PSW
 
-        RESTORE_ALL __LC_RETURN_MCCK_PSW,0
+mcck_panic:
+        l       %r14,__LC_PANIC_STACK
+        slr     %r14,%r15
+        sra     %r14,PAGE_SHIFT
+        jz      0f
+        l       %r15,__LC_PANIC_STACK
+0:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        j       mcck_skip
 
 /*
  * Restart interruption handler, kick starter for additional CPUs
@@ -799,18 +703,18 @@ restart_base:
         stck    __LC_LAST_UPDATE_CLOCK
         mvc     __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
         mvc     __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
-        l       %r15,__LC_SAVE_AREA+60  # load ksp
+        l       %r15,__LC_GPREGS_SAVE_AREA+60 # load ksp
         lctl    %c0,%c15,__LC_CREGS_SAVE_AREA # get new ctl regs
         lam     %a0,%a15,__LC_AREGS_SAVE_AREA
-        lm      %r6,%r15,__SF_GPRS(%r15) # load registers from clone
+        lm      %r6,%r15,__SF_GPRS(%r15)# load registers from clone
         l       %r1,__LC_THREAD_INFO
         mvc     __LC_USER_TIMER(8),__TI_user_timer(%r1)
         mvc     __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
         xc      __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
-        stosm   __SF_EMPTY(%r15),0x04   # now we can turn dat on
+        ssm     __LC_PGM_NEW_PSW        # turn dat on, keep irqs off
         basr    %r14,0
         l       %r14,restart_addr-.(%r14)
-        basr    %r14,%r14               # branch to start_secondary
+        basr    %r14,%r14               # call start_secondary
 restart_addr:
         .long   start_secondary
         .align  8
@@ -835,19 +739,19 @@ restart_go:
 # PSW restart interrupt handler
 #
 ENTRY(psw_restart_int_handler)
-        st      %r15,__LC_SAVE_AREA+48(%r0)     # save r15
+        st      %r15,__LC_SAVE_AREA_RESTART
         basr    %r15,0
 0:      l       %r15,.Lrestart_stack-0b(%r15)   # load restart stack
         l       %r15,0(%r15)
-        ahi     %r15,-SP_SIZE                   # make room for pt_regs
-        stm     %r0,%r14,SP_R0(%r15)            # store gprs %r0-%r14 to stack
-        mvc     SP_R15(4,%r15),__LC_SAVE_AREA+48(%r0)# store saved %r15 to stack
-        mvc     SP_PSW(8,%r15),__LC_RST_OLD_PSW(%r0) # store restart old psw
-        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # set backchain to 0
+        ahi     %r15,-__PT_SIZE                 # create pt_regs on stack
+        stm     %r0,%r14,__PT_R0(%r15)
+        mvc     __PT_R15(4,%r15),__LC_SAVE_AREA_RESTART
+        mvc     __PT_PSW(8,%r15),__LC_RST_OLD_PSW # store restart old psw
+        ahi     %r15,-STACK_FRAME_OVERHEAD
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
         basr    %r14,0
 1:      l       %r14,.Ldo_restart-1b(%r14)
         basr    %r14,%r14
-
         basr    %r14,0                          # load disabled wait PSW if
 2:      lpsw    restart_psw_crash-2b(%r14)      # do_restart returns
         .align 4
@@ -869,215 +773,174 @@ restart_psw_crash:
  */
 stack_overflow:
         l       %r15,__LC_PANIC_STACK   # change to panic stack
-        sl      %r15,BASED(.Lc_spsize)
-        mvc     SP_PSW(8,%r15),0(%r12)  # move user PSW to stack
-        stm     %r0,%r11,SP_R0(%r15)    # store gprs %r0-%r11 to kernel stack
-        la      %r1,__LC_SAVE_AREA
-        ch      %r12,BASED(.L0x020)     # old psw addr == __LC_SVC_OLD_PSW ?
-        be      BASED(0f)
-        ch      %r12,BASED(.L0x028)     # old psw addr == __LC_PGM_OLD_PSW ?
-        be      BASED(0f)
-        la      %r1,__LC_SAVE_AREA+16
-0:      mvc     SP_R12(16,%r15),0(%r1)  # move %r12-%r15 to stack
-        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear back chain
-        l       %r1,BASED(1f)           # branch to kernel_stack_overflow
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        br      %r1
+        ahi     %r15,-__PT_SIZE         # create pt_regs
+        stm     %r0,%r7,__PT_R0(%r15)
+        stm     %r8,%r9,__PT_PSW(%r15)
+        mvc     __PT_R8(32,%r11),0(%r14)
+        lr      %r15,%r11
+        ahi     %r15,-STACK_FRAME_OVERHEAD
+        l       %r1,BASED(1f)
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
+        lr      %r2,%r11                # pass pointer to pt_regs
+        br      %r1                     # branch to kernel_stack_overflow
 1:      .long   kernel_stack_overflow
 #endif
 
-cleanup_table_system_call:
-        .long   system_call + 0x80000000, sysc_do_svc + 0x80000000
-cleanup_table_sysc_tif:
-        .long   sysc_tif + 0x80000000, sysc_restore + 0x80000000
-cleanup_table_sysc_restore:
-        .long   sysc_restore + 0x80000000, sysc_done + 0x80000000
-cleanup_table_io_tif:
-        .long   io_tif + 0x80000000, io_restore + 0x80000000
-cleanup_table_io_restore:
-        .long   io_restore + 0x80000000, io_done + 0x80000000
+cleanup_table:
+        .long   system_call + 0x80000000
+        .long   sysc_do_svc + 0x80000000
+        .long   sysc_tif + 0x80000000
+        .long   sysc_restore + 0x80000000
+        .long   sysc_done + 0x80000000
+        .long   io_tif + 0x80000000
+        .long   io_restore + 0x80000000
+        .long   io_done + 0x80000000
 
 cleanup_critical:
-        clc     4(4,%r12),BASED(cleanup_table_system_call)
-        bl      BASED(0f)
-        clc     4(4,%r12),BASED(cleanup_table_system_call+4)
-        bl      BASED(cleanup_system_call)
-0:
-        clc     4(4,%r12),BASED(cleanup_table_sysc_tif)
-        bl      BASED(0f)
-        clc     4(4,%r12),BASED(cleanup_table_sysc_tif+4)
-        bl      BASED(cleanup_sysc_tif)
-0:
-        clc     4(4,%r12),BASED(cleanup_table_sysc_restore)
-        bl      BASED(0f)
-        clc     4(4,%r12),BASED(cleanup_table_sysc_restore+4)
-        bl      BASED(cleanup_sysc_restore)
-0:
-        clc     4(4,%r12),BASED(cleanup_table_io_tif)
-        bl      BASED(0f)
-        clc     4(4,%r12),BASED(cleanup_table_io_tif+4)
-        bl      BASED(cleanup_io_tif)
-0:
-        clc     4(4,%r12),BASED(cleanup_table_io_restore)
-        bl      BASED(0f)
-        clc     4(4,%r12),BASED(cleanup_table_io_restore+4)
-        bl      BASED(cleanup_io_restore)
-0:
-        br      %r14
+        cl      %r9,BASED(cleanup_table)        # system_call
+        jl      0f
+        cl      %r9,BASED(cleanup_table+4)      # sysc_do_svc
+        jl      cleanup_system_call
+        cl      %r9,BASED(cleanup_table+8)      # sysc_tif
+        jl      0f
+        cl      %r9,BASED(cleanup_table+12)     # sysc_restore
+        jl      cleanup_sysc_tif
+        cl      %r9,BASED(cleanup_table+16)     # sysc_done
+        jl      cleanup_sysc_restore
+        cl      %r9,BASED(cleanup_table+20)     # io_tif
+        jl      0f
+        cl      %r9,BASED(cleanup_table+24)     # io_restore
+        jl      cleanup_io_tif
+        cl      %r9,BASED(cleanup_table+28)     # io_done
+        jl      cleanup_io_restore
+0:      br      %r14
 
 cleanup_system_call:
-        mvc     __LC_RETURN_PSW(8),0(%r12)
-        clc     __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+4)
-        bh      BASED(0f)
-        mvc     __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
-        c       %r12,BASED(.Lmck_old_psw)
-        be      BASED(0f)
+        # check if stpt has been executed
+        cl      %r9,BASED(cleanup_system_call_insn)
+        jh      0f
         mvc     __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
-0:      c       %r12,BASED(.Lmck_old_psw)
-        la      %r12,__LC_SAVE_AREA+32
-        be      BASED(0f)
-        la      %r12,__LC_SAVE_AREA+16
-0:      clc     __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+8)
-        bhe     BASED(cleanup_vtime)
-        clc     __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn)
-        bh      BASED(0f)
-        mvc     __LC_SAVE_AREA(16),0(%r12)
-0:      st      %r13,4(%r12)
-        l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
-        s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
-        st      %r15,12(%r12)
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        mvc     0(4,%r12),__LC_THREAD_INFO
-        l       %r12,__LC_THREAD_INFO
-        mvc     SP_PSW(8,%r15),__LC_SVC_OLD_PSW
-        mvc     SP_SVC_CODE(4,%r15),__LC_SVC_ILC
-        oi      __TI_flags+3(%r12),_TIF_SYSCALL
-cleanup_vtime:
-        clc     __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+12)
-        bhe     BASED(cleanup_stime)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-cleanup_stime:
-        clc     __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+16)
-        bh      BASED(cleanup_update)
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-cleanup_update:
+        chi     %r11,__LC_SAVE_AREA_ASYNC
+        je      0f
+        mvc     __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
+0:      # check if stm has been executed
+        cl      %r9,BASED(cleanup_system_call_insn+4)
+        jh      0f
+        mvc     __LC_SAVE_AREA_SYNC(32),0(%r11)
+0:      # set up saved registers r12, and r13
+        st      %r12,16(%r11)           # r12 thread-info pointer
+        st      %r13,20(%r11)           # r13 literal-pool pointer
+        # check if the user time calculation has been done
+        cl      %r9,BASED(cleanup_system_call_insn+8)
+        jh      0f
+        l       %r10,__LC_EXIT_TIMER
+        l       %r15,__LC_EXIT_TIMER+4
+        SUB64   %r10,%r15,__LC_SYNC_ENTER_TIMER
+        ADD64   %r10,%r15,__LC_USER_TIMER
+        st      %r10,__LC_USER_TIMER
+        st      %r15,__LC_USER_TIMER+4
+0:      # check if the system time calculation has been done
+        cl      %r9,BASED(cleanup_system_call_insn+12)
+        jh      0f
+        l       %r10,__LC_LAST_UPDATE_TIMER
+        l       %r15,__LC_LAST_UPDATE_TIMER+4
+        SUB64   %r10,%r15,__LC_EXIT_TIMER
+        ADD64   %r10,%r15,__LC_SYSTEM_TIMER
+        st      %r10,__LC_SYSTEM_TIMER
+        st      %r15,__LC_SYSTEM_TIMER+4
+0:      # update accounting time stamp
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        mvc     __LC_RETURN_PSW+4(4),BASED(cleanup_table_system_call+4)
-        la      %r12,__LC_RETURN_PSW
+        # set up saved register 11
+        l       %r15,__LC_KERNEL_STACK
+        ahi     %r15,-__PT_SIZE
+        st      %r15,12(%r11)           # r11 pt_regs pointer
+        # fill pt_regs
+        mvc     __PT_R8(32,%r15),__LC_SAVE_AREA_SYNC
+        stm     %r0,%r7,__PT_R0(%r15)
+        mvc     __PT_PSW(8,%r15),__LC_SVC_OLD_PSW
+        mvc     __PT_INT_CODE(4,%r15),__LC_SVC_ILC
+        # setup saved register 15
+        ahi     %r15,-STACK_FRAME_OVERHEAD
+        st      %r15,28(%r11)           # r15 stack pointer
+        # set new psw address and exit
+        l       %r9,BASED(cleanup_table+4)      # sysc_do_svc + 0x80000000
         br      %r14
 cleanup_system_call_insn:
-        .long   sysc_saveall + 0x80000000
         .long   system_call + 0x80000000
-        .long   sysc_vtime + 0x80000000
-        .long   sysc_stime + 0x80000000
-        .long   sysc_update + 0x80000000
+        .long   sysc_stm + 0x80000000
+        .long   sysc_vtime + 0x80000000 + 36
+        .long   sysc_vtime + 0x80000000 + 76
 
 cleanup_sysc_tif:
-        mvc     __LC_RETURN_PSW(4),0(%r12)
-        mvc     __LC_RETURN_PSW+4(4),BASED(cleanup_table_sysc_tif)
-        la      %r12,__LC_RETURN_PSW
+        l       %r9,BASED(cleanup_table+8)      # sysc_tif + 0x80000000
         br      %r14
 
 cleanup_sysc_restore:
-        clc     4(4,%r12),BASED(cleanup_sysc_restore_insn)
-        be      BASED(2f)
-        mvc     __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
-        c       %r12,BASED(.Lmck_old_psw)
-        be      BASED(0f)
-        mvc     __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
-0:      clc     4(4,%r12),BASED(cleanup_sysc_restore_insn+4)
-        be      BASED(2f)
-        mvc     __LC_RETURN_PSW(8),SP_PSW(%r15)
-        c       %r12,BASED(.Lmck_old_psw)
-        la      %r12,__LC_SAVE_AREA+32
-        be      BASED(1f)
-        la      %r12,__LC_SAVE_AREA+16
-1:      mvc     0(16,%r12),SP_R12(%r15)
-        lm      %r0,%r11,SP_R0(%r15)
-        l       %r15,SP_R15(%r15)
-2:      la      %r12,__LC_RETURN_PSW
+        cl      %r9,BASED(cleanup_sysc_restore_insn)
+        jhe     0f
+        l       %r9,12(%r11)            # get saved pointer to pt_regs
+        mvc     __LC_RETURN_PSW(8),__PT_PSW(%r9)
+        mvc     0(32,%r11),__PT_R8(%r9)
+        lm      %r0,%r7,__PT_R0(%r9)
+0:      lm      %r8,%r9,__LC_RETURN_PSW
         br      %r14
 cleanup_sysc_restore_insn:
         .long   sysc_done - 4 + 0x80000000
-        .long   sysc_done - 8 + 0x80000000
 
 cleanup_io_tif:
-        mvc     __LC_RETURN_PSW(4),0(%r12)
-        mvc     __LC_RETURN_PSW+4(4),BASED(cleanup_table_io_tif)
-        la      %r12,__LC_RETURN_PSW
+        l       %r9,BASED(cleanup_table+20)     # io_tif + 0x80000000
         br      %r14
 
 cleanup_io_restore:
-        clc     4(4,%r12),BASED(cleanup_io_restore_insn)
-        be      BASED(1f)
-        mvc     __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
-        clc     4(4,%r12),BASED(cleanup_io_restore_insn+4)
-        be      BASED(1f)
-        mvc     __LC_RETURN_PSW(8),SP_PSW(%r15)
-        mvc     __LC_SAVE_AREA+32(16),SP_R12(%r15)
-        lm      %r0,%r11,SP_R0(%r15)
-        l       %r15,SP_R15(%r15)
-1:      la      %r12,__LC_RETURN_PSW
+        cl      %r9,BASED(cleanup_io_restore_insn)
+        jhe     0f
+        l       %r9,12(%r11)            # get saved r11 pointer to pt_regs
+        mvc     __LC_RETURN_PSW(8),__PT_PSW(%r9)
+        ni      __LC_RETURN_PSW+1,0xfd  # clear wait state bit
+        mvc     0(32,%r11),__PT_R8(%r9)
+        lm      %r0,%r7,__PT_R0(%r9)
+0:      lm      %r8,%r9,__LC_RETURN_PSW
         br      %r14
 cleanup_io_restore_insn:
         .long   io_done - 4 + 0x80000000
-        .long   io_done - 8 + 0x80000000
 
 /*
  * Integer constants
  */
-                .align  4
-.Lc_spsize:     .long   SP_SIZE
-.Lc_overhead:   .long   STACK_FRAME_OVERHEAD
-.Lnr_syscalls:  .long   NR_syscalls
-.L0x018:        .short  0x018
-.L0x020:        .short  0x020
-.L0x028:        .short  0x028
-.L0x030:        .short  0x030
-.L0x038:        .short  0x038
-.Lc_1:          .long   1
+        .align  4
+.Lnr_syscalls:          .long   NR_syscalls
 
 /*
  * Symbol constants
  */
-.Ls390_mcck:    .long   s390_do_machine_check
-.Ls390_handle_mcck:
-                .long   s390_handle_mcck
-.Lmck_old_psw:  .long   __LC_MCK_OLD_PSW
-.Ldo_IRQ:       .long   do_IRQ
-.Ldo_extint:    .long   do_extint
-.Ldo_signal:    .long   do_signal
-.Ldo_notify_resume:
-                .long   do_notify_resume
-.Lhandle_per:   .long   do_per_trap
-.Ldo_execve:    .long   do_execve
-.Lexecve_tail:  .long   execve_tail
-.Ljump_table:   .long   pgm_check_table
-.Lschedule:     .long   schedule
+.Ldo_machine_check:     .long   s390_do_machine_check
+.Lhandle_mcck:          .long   s390_handle_mcck
+.Ldo_IRQ:               .long   do_IRQ
+.Ldo_extint:            .long   do_extint
+.Ldo_signal:            .long   do_signal
+.Ldo_notify_resume:     .long   do_notify_resume
+.Ldo_per_trap:          .long   do_per_trap
+.Ldo_execve:            .long   do_execve
+.Lexecve_tail:          .long   execve_tail
+.Ljump_table:           .long   pgm_check_table
+.Lschedule:             .long   schedule
 #ifdef CONFIG_PREEMPT
-.Lpreempt_schedule_irq:
-                .long   preempt_schedule_irq
+.Lpreempt_irq:          .long   preempt_schedule_irq
 #endif
-.Ltrace_entry:  .long   do_syscall_trace_enter
-.Ltrace_exit:   .long   do_syscall_trace_exit
-.Lschedtail:    .long   schedule_tail
-.Lsysc_table:   .long   sys_call_table
+.Ltrace_enter:          .long   do_syscall_trace_enter
+.Ltrace_exit:           .long   do_syscall_trace_exit
+.Lschedule_tail:        .long   schedule_tail
+.Lsys_call_table:       .long   sys_call_table
+.Lsysc_per:             .long   sysc_per + 0x80000000
 #ifdef CONFIG_TRACE_IRQFLAGS
-.Ltrace_irq_on_caller:
-                .long   trace_hardirqs_on_caller
-.Ltrace_irq_off_caller:
-                .long   trace_hardirqs_off_caller
+.Lhardirqs_on:          .long   trace_hardirqs_on_caller
+.Lhardirqs_off:         .long   trace_hardirqs_off_caller
 #endif
 #ifdef CONFIG_LOCKDEP
-.Llockdep_sys_exit:
-                .long   lockdep_sys_exit
+.Llockdep_sys_exit:     .long   lockdep_sys_exit
 #endif
-.Lcritical_start:
-                .long   __critical_start + 0x80000000
-.Lcritical_end:
-                .long   __critical_end + 0x80000000
-.Lcleanup_critical:
-                .long   cleanup_critical
+.Lcritical_start:       .long   __critical_start + 0x80000000
+.Lcritical_length:      .long   __critical_end - __critical_start
 
                 .section .rodata, "a"
 #define SYSCALL(esa,esame,emu)  .long esa
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index ef8fb1d6e8d..bf538aaf407 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -6,15 +6,15 @@
 #include <asm/ptrace.h>
 
 
-extern void (*pgm_check_table[128])(struct pt_regs *, long, unsigned long);
+extern void (*pgm_check_table[128])(struct pt_regs *);
 extern void *restart_stack;
 
 asmlinkage long do_syscall_trace_enter(struct pt_regs *regs);
 asmlinkage void do_syscall_trace_exit(struct pt_regs *regs);
 
-void do_protection_exception(struct pt_regs *, long, unsigned long);
-void do_dat_exception(struct pt_regs *, long, unsigned long);
-void do_asce_exception(struct pt_regs *, long, unsigned long);
+void do_protection_exception(struct pt_regs *regs);
+void do_dat_exception(struct pt_regs *regs);
+void do_asce_exception(struct pt_regs *regs);
 
 void do_per_trap(struct pt_regs *regs);
 void syscall_trace(struct pt_regs *regs, int entryexit);
@@ -28,7 +28,7 @@ void do_extint(struct pt_regs *regs, unsigned int, unsigned int, unsigned long);
 void do_restart(void);
 int __cpuinit start_secondary(void *cpuvoid);
 void __init startup_init(void);
-void die(const char * str, struct pt_regs * regs, long err);
+void die(struct pt_regs *regs, const char *str);
 
 void __init time_init(void);
 
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 83a93747e2f..412a7b8783d 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -19,32 +19,22 @@
 #include <asm/unistd.h>
 #include <asm/page.h>
 
-/*
- * Stack layout for the system_call stack entry.
- * The first few entries are identical to the user_regs_struct.
- */
-SP_PTREGS    =  STACK_FRAME_OVERHEAD
-SP_ARGS      =  STACK_FRAME_OVERHEAD + __PT_ARGS
-SP_PSW       =  STACK_FRAME_OVERHEAD + __PT_PSW
-SP_R0        =  STACK_FRAME_OVERHEAD + __PT_GPRS
-SP_R1        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 8
-SP_R2        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 16
-SP_R3        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 24
-SP_R4        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 32
-SP_R5        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 40
-SP_R6        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 48
-SP_R7        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 56
-SP_R8        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 64
-SP_R9        =  STACK_FRAME_OVERHEAD + __PT_GPRS + 72
-SP_R10       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 80
-SP_R11       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 88
-SP_R12       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 96
-SP_R13       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 104
-SP_R14       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 112
-SP_R15       =  STACK_FRAME_OVERHEAD + __PT_GPRS + 120
-SP_ORIG_R2   =  STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
-SP_SVC_CODE  =  STACK_FRAME_OVERHEAD + __PT_SVC_CODE
-SP_SIZE      =  STACK_FRAME_OVERHEAD + __PT_SIZE
+__PT_R0      =  __PT_GPRS
+__PT_R1      =  __PT_GPRS + 8
+__PT_R2      =  __PT_GPRS + 16
+__PT_R3      =  __PT_GPRS + 24
+__PT_R4      =  __PT_GPRS + 32
+__PT_R5      =  __PT_GPRS + 40
+__PT_R6      =  __PT_GPRS + 48
+__PT_R7      =  __PT_GPRS + 56
+__PT_R8      =  __PT_GPRS + 64
+__PT_R9      =  __PT_GPRS + 72
+__PT_R10     =  __PT_GPRS + 80
+__PT_R11     =  __PT_GPRS + 88
+__PT_R12     =  __PT_GPRS + 96
+__PT_R13     =  __PT_GPRS + 104
+__PT_R14     =  __PT_GPRS + 112
+__PT_R15     =  __PT_GPRS + 120
 
 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
 STACK_SIZE  = 1 << STACK_SHIFT
@@ -59,154 +49,103 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
 
 #define BASED(name) name-system_call(%r13)
 
-        .macro SPP newpp
-#if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
-        tm      __LC_MACHINE_FLAGS+6,0x20       # MACHINE_FLAG_SPP
-        jz      .+8
-        .insn   s,0xb2800000,\newpp
-#endif
-        .endm
-
-        .macro  HANDLE_SIE_INTERCEPT
-#if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
-        tm      __TI_flags+6(%r12),_TIF_SIE>>8
-        jz      0f
-        SPP     __LC_CMF_HPP                    # set host id
-        clc     SP_PSW+8(8,%r15),BASED(.Lsie_loop)
-        jl      0f
-        clc     SP_PSW+8(8,%r15),BASED(.Lsie_done)
-        jhe     0f
-        mvc     SP_PSW+8(8,%r15),BASED(.Lsie_loop)
-0:
-#endif
-        .endm
-
-#ifdef CONFIG_TRACE_IRQFLAGS
         .macro  TRACE_IRQS_ON
+#ifdef CONFIG_TRACE_IRQFLAGS
         basr    %r2,%r0
         brasl   %r14,trace_hardirqs_on_caller
+#endif
         .endm
 
         .macro  TRACE_IRQS_OFF
+#ifdef CONFIG_TRACE_IRQFLAGS
         basr    %r2,%r0
         brasl   %r14,trace_hardirqs_off_caller
-        .endm
-#else
-#define TRACE_IRQS_ON
-#define TRACE_IRQS_OFF
 #endif
+        .endm
 
-#ifdef CONFIG_LOCKDEP
         .macro  LOCKDEP_SYS_EXIT
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
-        jz      0f
+#ifdef CONFIG_LOCKDEP
+        tm      __PT_PSW+1(%r11),0x01   # returning to user ?
+        jz      .+10
         brasl   %r14,lockdep_sys_exit
-0:
-        .endm
-#else
-#define LOCKDEP_SYS_EXIT
 #endif
-
-        .macro  UPDATE_VTIME lc_from,lc_to,lc_sum
-        lg      %r10,\lc_from
-        slg     %r10,\lc_to
-        alg     %r10,\lc_sum
-        stg     %r10,\lc_sum
         .endm
 
-/*
- * Register usage in interrupt handlers:
- *    R9  - pointer to current task structure
- *    R13 - pointer to literal pool
- *    R14 - return register for function calls
- *    R15 - kernel stack pointer
- */
+        .macro SPP newpp
+#if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
+        tm      __LC_MACHINE_FLAGS+6,0x20       # MACHINE_FLAG_SPP
+        jz      .+8
+        .insn   s,0xb2800000,\newpp
+#endif
+        .endm
 
-        .macro  SAVE_ALL_SVC psworg,savearea
-        stmg    %r11,%r15,\savearea
-        lg      %r15,__LC_KERNEL_STACK  # problem state -> load ksp
-        aghi    %r15,-SP_SIZE           # make room for registers & psw
-        lg      %r11,__LC_LAST_BREAK
+        .macro  HANDLE_SIE_INTERCEPT scratch
+#if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
+        tm      __TI_flags+6(%r12),_TIF_SIE>>8
+        jz      .+42
+        tm      __LC_MACHINE_FLAGS+6,0x20       # MACHINE_FLAG_SPP
+        jz      .+8
+        .insn   s,0xb2800000,BASED(.Lhost_id)   # set host id
+        lgr     \scratch,%r9
+        slg     \scratch,BASED(.Lsie_loop)
+        clg     \scratch,BASED(.Lsie_length)
+        jhe     .+10
+        lg      %r9,BASED(.Lsie_loop)
+#endif
         .endm
 
-        .macro  SAVE_ALL_PGM psworg,savearea
-        stmg    %r11,%r15,\savearea
-        tm      \psworg+1,0x01          # test problem state bit
+        .macro  CHECK_STACK stacksize,savearea
 #ifdef CONFIG_CHECK_STACK
-        jnz     1f
-        tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
-        jnz     2f
-        la      %r12,\psworg
-        j       stack_overflow
-#else
-        jz      2f
+        tml     %r15,\stacksize - CONFIG_STACK_GUARD
+        lghi    %r14,\savearea
+        jz      stack_overflow
 #endif
-1:      lg      %r15,__LC_KERNEL_STACK  # problem state -> load ksp
-2:      aghi    %r15,-SP_SIZE           # make room for registers & psw
-        larl    %r13,system_call
-        lg      %r11,__LC_LAST_BREAK
         .endm
 
-        .macro  SAVE_ALL_ASYNC psworg,savearea
-        stmg    %r11,%r15,\savearea
-        larl    %r13,system_call
-        lg      %r11,__LC_LAST_BREAK
-        la      %r12,\psworg
-        tm      \psworg+1,0x01          # test problem state bit
-        jnz     1f                      # from user -> load kernel stack
-        clc     \psworg+8(8),BASED(.Lcritical_end)
+        .macro  SWITCH_ASYNC savearea,stack,shift
+        tmhh    %r8,0x0001              # interrupting from user ?
+        jnz     1f
+        lgr     %r14,%r9
+        slg     %r14,BASED(.Lcritical_start)
+        clg     %r14,BASED(.Lcritical_length)
         jhe     0f
-        clc     \psworg+8(8),BASED(.Lcritical_start)
-        jl      0f
+        lghi    %r11,\savearea          # inside critical section, do cleanup
         brasl   %r14,cleanup_critical
-        tm      1(%r12),0x01            # retest problem state after cleanup
+        tmhh    %r8,0x0001              # retest problem state after cleanup
         jnz     1f
-0:      lg      %r14,__LC_ASYNC_STACK   # are we already on the async. stack ?
+0:      lg      %r14,\stack             # are we already on the target stack?
         slgr    %r14,%r15
-        srag    %r14,%r14,STACK_SHIFT
-#ifdef CONFIG_CHECK_STACK
+        srag    %r14,%r14,\shift
         jnz     1f
-        tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
-        jnz     2f
-        j       stack_overflow
-#else
-        jz      2f
-#endif
-1:      lg      %r15,__LC_ASYNC_STACK   # load async stack
-2:      aghi    %r15,-SP_SIZE           # make room for registers & psw
-        .endm
-
-        .macro  CREATE_STACK_FRAME savearea
-        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
-        stg     %r2,SP_ORIG_R2(%r15)    # store original content of gpr 2
-        mvc     SP_R11(40,%r15),\savearea # move %r11-%r15 to stack
-        stmg    %r0,%r10,SP_R0(%r15)    # store gprs %r0-%r10 to kernel stack
+        CHECK_STACK 1<<\shift,\savearea
+        j       2f
+1:      lg      %r15,\stack             # load target stack
+2:      aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
         .endm
 
-        .macro  RESTORE_ALL psworg,sync
-        mvc     \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
-        .if !\sync
-        ni      \psworg+1,0xfd          # clear wait state bit
-        .endif
-        lg      %r14,__LC_VDSO_PER_CPU
-        lmg     %r0,%r13,SP_R0(%r15)    # load gprs 0-13 of user
-        stpt    __LC_EXIT_TIMER
-        mvc     __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
-        lmg     %r14,%r15,SP_R14(%r15)  # load grps 14-15 of user
-        lpswe   \psworg                 # back to caller
+        .macro UPDATE_VTIME scratch,enter_timer
+        lg      \scratch,__LC_EXIT_TIMER
+        slg     \scratch,\enter_timer
+        alg     \scratch,__LC_USER_TIMER
+        stg     \scratch,__LC_USER_TIMER
+        lg      \scratch,__LC_LAST_UPDATE_TIMER
+        slg     \scratch,__LC_EXIT_TIMER
+        alg     \scratch,__LC_SYSTEM_TIMER
+        stg     \scratch,__LC_SYSTEM_TIMER
+        mvc     __LC_LAST_UPDATE_TIMER(8),\enter_timer
         .endm
 
-        .macro  LAST_BREAK
-        srag    %r10,%r11,23
-        jz      0f
-        stg     %r11,__TI_last_break(%r12)
-0:
+        .macro  LAST_BREAK scratch
+        srag    \scratch,%r10,23
+        jz      .+10
+        stg     %r10,__TI_last_break(%r12)
         .endm
 
         .macro REENABLE_IRQS
-        mvc     __SF_EMPTY(1,%r15),SP_PSW(%r15)
-        ni      __SF_EMPTY(%r15),0xbf
-        ssm     __SF_EMPTY(%r15)
+        stg     %r8,__LC_RETURN_PSW
+        ni      __LC_RETURN_PSW,0xbf
+        ssm     __LC_RETURN_PSW
         .endm
 
         .section .kprobes.text, "ax"
@@ -245,55 +184,66 @@ __critical_start:
 
 ENTRY(system_call)
         stpt    __LC_SYNC_ENTER_TIMER
-sysc_saveall:
-        SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        mvc     SP_PSW(16,%r15),__LC_SVC_OLD_PSW
-        mvc     SP_SVC_CODE(4,%r15),__LC_SVC_ILC
-        oi      __TI_flags+7(%r12),_TIF_SYSCALL
+sysc_stmg:
+        stmg    %r8,%r15,__LC_SAVE_AREA_SYNC
+        lg      %r10,__LC_LAST_BREAK
+        lg      %r12,__LC_THREAD_INFO
+        larl    %r13,system_call
+sysc_per:
+        lg      %r15,__LC_KERNEL_STACK
+        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
 sysc_vtime:
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-sysc_stime:
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-sysc_update:
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        LAST_BREAK
+        UPDATE_VTIME %r13,__LC_SYNC_ENTER_TIMER
+        LAST_BREAK %r13
+        stmg    %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
+        mvc     __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
+        mvc     __PT_INT_CODE(4,%r11),__LC_SVC_ILC
 sysc_do_svc:
-        llgh    %r7,SP_SVC_CODE+2(%r15)
-        slag    %r7,%r7,2       # shift and test for svc 0
+        oi      __TI_flags+7(%r12),_TIF_SYSCALL
+        llgh    %r8,__PT_INT_CODE+2(%r11)
+        slag    %r8,%r8,2                       # shift and test for svc 0
         jnz     sysc_nr_ok
         # svc 0: system call number in %r1
-        llgfr   %r1,%r1         # clear high word in r1
+        llgfr   %r1,%r1                         # clear high word in r1
         cghi    %r1,NR_syscalls
         jnl     sysc_nr_ok
-        sth     %r1,SP_SVC_CODE+2(%r15)
-        slag    %r7,%r1,2       # shift and test for svc 0
+        sth     %r1,__PT_INT_CODE+2(%r11)
+        slag    %r8,%r1,2
 sysc_nr_ok:
-        larl    %r10,sys_call_table
+        larl    %r10,sys_call_table             # 64 bit system call table
 #ifdef CONFIG_COMPAT
-        tm      __TI_flags+5(%r12),(_TIF_31BIT>>16)  # running in 31 bit mode ?
+        tm      __TI_flags+5(%r12),(_TIF_31BIT>>16)
         jno     sysc_noemu
-        larl    %r10,sys_call_table_emu  # use 31 bit emulation system calls
+        larl    %r10,sys_call_table_emu         # 31 bit system call table
 sysc_noemu:
 #endif
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+        stg     %r2,__PT_ORIG_GPR2(%r11)
+        stg     %r7,STACK_FRAME_OVERHEAD(%r15)
+        lgf     %r9,0(%r8,%r10)                 # get system call add.
         tm      __TI_flags+6(%r12),_TIF_TRACE >> 8
-        mvc     SP_ARGS(8,%r15),SP_R7(%r15)
-        lgf     %r8,0(%r7,%r10) # load address of system call routine
         jnz     sysc_tracesys
-        basr    %r14,%r8        # call sys_xxxx
-        stg     %r2,SP_R2(%r15) # store return value (change R2 on stack)
+        basr    %r14,%r9                        # call sys_xxxx
+        stg     %r2,__PT_R2(%r11)               # store return value
 
 sysc_return:
         LOCKDEP_SYS_EXIT
 sysc_tif:
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
+        tm      __PT_PSW+1(%r11),0x01           # returning to user ?
         jno     sysc_restore
         tm      __TI_flags+7(%r12),_TIF_WORK_SVC
-        jnz     sysc_work       # there is work to do (signals etc.)
+        jnz     sysc_work                       # check for work
         ni      __TI_flags+7(%r12),255-_TIF_SYSCALL
 sysc_restore:
-        RESTORE_ALL __LC_RETURN_PSW,1
+        lg      %r14,__LC_VDSO_PER_CPU
+        lmg     %r0,%r10,__PT_R0(%r11)
+        mvc     __LC_RETURN_PSW(16),__PT_PSW(%r11)
+        stpt    __LC_EXIT_TIMER
+        mvc     __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
+        lmg     %r11,%r15,__PT_R11(%r11)
+        lpswe   __LC_RETURN_PSW
 sysc_done:
 
 #
@@ -317,7 +267,7 @@ sysc_work:
 #
 sysc_reschedule:
         larl    %r14,sysc_return
-        jg      schedule                # return point is sysc_return
+        jg      schedule
 
 #
 # _TIF_MCCK_PENDING is set, call handler
@@ -331,33 +281,33 @@ sysc_mcck_pending:
 #
 sysc_sigpending:
         ni      __TI_flags+7(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        brasl   %r14,do_signal          # call do_signal
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        brasl   %r14,do_signal
         tm      __TI_flags+7(%r12),_TIF_SYSCALL
         jno     sysc_return
-        lmg     %r2,%r6,SP_R2(%r15)     # load svc arguments
-        lghi    %r7,0                   # svc 0 returns -ENOSYS
-        lh      %r1,SP_SVC_CODE+2(%r15) # load new svc number
+        lmg     %r2,%r7,__PT_R2(%r11)   # load svc arguments
+        lghi    %r8,0                   # svc 0 returns -ENOSYS
+        lh      %r1,__PT_INT_CODE+2(%r11)       # load new svc number
         cghi    %r1,NR_syscalls
         jnl     sysc_nr_ok              # invalid svc number -> do svc 0
-        slag    %r7,%r1,2
+        slag    %r8,%r1,2
         j       sysc_nr_ok              # restart svc
 
 #
 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
 #
 sysc_notify_resume:
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        lgr     %r2,%r11                # pass pointer to pt_regs
         larl    %r14,sysc_return
-        jg      do_notify_resume        # call do_notify_resume
+        jg      do_notify_resume
 
 #
 # _TIF_PER_TRAP is set, call do_per_trap
 #
 sysc_singlestep:
         ni      __TI_flags+7(%r12),255-(_TIF_SYSCALL | _TIF_PER_TRAP)
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        larl    %r14,sysc_return        # load adr. of system return
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        larl    %r14,sysc_return
         jg      do_per_trap
 
 #
@@ -365,41 +315,41 @@ sysc_singlestep:
 # and after the system call
 #
 sysc_tracesys:
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        lgr     %r2,%r11                # pass pointer to pt_regs
         la      %r3,0
-        llgh    %r0,SP_SVC_CODE+2(%r15)
-        stg     %r0,SP_R2(%r15)
+        llgh    %r0,__PT_INT_CODE+2(%r11)
+        stg     %r0,__PT_R2(%r11)
         brasl   %r14,do_syscall_trace_enter
         lghi    %r0,NR_syscalls
         clgr    %r0,%r2
         jnh     sysc_tracenogo
-        sllg    %r7,%r2,2               # svc number *4
-        lgf     %r8,0(%r7,%r10)
+        sllg    %r8,%r2,2
+        lgf     %r9,0(%r8,%r10)
 sysc_tracego:
-        lmg     %r3,%r6,SP_R3(%r15)
-        mvc     SP_ARGS(8,%r15),SP_R7(%r15)
-        lg      %r2,SP_ORIG_R2(%r15)
-        basr    %r14,%r8                # call sys_xxx
-        stg     %r2,SP_R2(%r15)         # store return value
+        lmg     %r3,%r7,__PT_R3(%r11)
+        stg     %r7,STACK_FRAME_OVERHEAD(%r15)
+        lg      %r2,__PT_ORIG_GPR2(%r11)
+        basr    %r14,%r9                # call sys_xxx
+        stg     %r2,__PT_R2(%r11)       # store return value
 sysc_tracenogo:
         tm      __TI_flags+6(%r12),_TIF_TRACE >> 8
         jz      sysc_return
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        larl    %r14,sysc_return        # return point is sysc_return
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        larl    %r14,sysc_return
         jg      do_syscall_trace_exit
 
 #
 # a new process exits the kernel with ret_from_fork
 #
 ENTRY(ret_from_fork)
-        lg      %r13,__LC_SVC_NEW_PSW+8
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      SP_PSW+1(%r15),0x01     # forking a kernel thread ?
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        lg      %r12,__LC_THREAD_INFO
+        tm      __PT_PSW+1(%r11),0x01   # forking a kernel thread ?
         jo      0f
-        stg     %r15,SP_R15(%r15)       # store stack pointer for new kthread
+        stg     %r15,__PT_R15(%r11)     # store stack pointer for new kthread
 0:      brasl   %r14,schedule_tail
         TRACE_IRQS_ON
-        stosm   24(%r15),0x03           # reenable interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
         j       sysc_tracenogo
 
 #
@@ -409,26 +359,26 @@ ENTRY(ret_from_fork)
 ENTRY(kernel_execve)
         stmg    %r12,%r15,96(%r15)
         lgr     %r14,%r15
-        aghi    %r15,-SP_SIZE
+        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         stg     %r14,__SF_BACKCHAIN(%r15)
-        la      %r12,SP_PTREGS(%r15)
+        la      %r12,STACK_FRAME_OVERHEAD(%r15)
         xc      0(__PT_SIZE,%r12),0(%r12)
         lgr     %r5,%r12
         brasl   %r14,do_execve
         ltgfr   %r2,%r2
         je      0f
-        aghi    %r15,SP_SIZE
+        aghi    %r15,(STACK_FRAME_OVERHEAD + __PT_SIZE)
         lmg     %r12,%r15,96(%r15)
         br      %r14
         # execve succeeded.
-0:      stnsm   __SF_EMPTY(%r15),0xfc   # disable interrupts
+0:      ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         lg      %r15,__LC_KERNEL_STACK  # load ksp
-        aghi    %r15,-SP_SIZE           # make room for registers & psw
-        lg      %r13,__LC_SVC_NEW_PSW+8
-        mvc     SP_PTREGS(__PT_SIZE,%r15),0(%r12)       # copy pt_regs
+        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        mvc     0(__PT_SIZE,%r11),0(%r12)       # copy pt_regs
         lg      %r12,__LC_THREAD_INFO
         xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
         brasl   %r14,execve_tail
         j       sysc_return
 
@@ -437,127 +387,72 @@ ENTRY(kernel_execve)
  */
 
 ENTRY(pgm_check_handler)
-/*
- * First we need to check for a special case:
- * Single stepping an instruction that disables the PER event mask will
- * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
- * For a single stepped SVC the program check handler gets control after
- * the SVC new PSW has been loaded. But we want to execute the SVC first and
- * then handle the PER event. Therefore we update the SVC old PSW to point
- * to the pgm_check_handler and branch to the SVC handler after we checked
- * if we have to load the kernel stack register.
- * For every other possible cause for PER event without the PER mask set
- * we just ignore the PER event (FIXME: is there anything we have to do
- * for LPSW?).
- */
         stpt    __LC_SYNC_ENTER_TIMER
-        tm      __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
-        jnz     pgm_per                  # got per exception -> special case
-        SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        mvc     SP_PSW(16,%r15),__LC_PGM_OLD_PSW
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        HANDLE_SIE_INTERCEPT
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        jz      pgm_no_vtime
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        LAST_BREAK
-pgm_no_vtime:
-        stg     %r11,SP_ARGS(%r15)
-        lgf     %r3,__LC_PGM_ILC        # load program interruption code
-        lg      %r4,__LC_TRANS_EXC_CODE
-        REENABLE_IRQS
-        lghi    %r8,0x7f
-        ngr     %r8,%r3
-        sll     %r8,3
-        larl    %r1,pgm_check_table
-        lg      %r1,0(%r8,%r1)          # load address of handler routine
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        basr    %r14,%r1                # branch to interrupt-handler
-pgm_exit:
-        j       sysc_return
-
-#
-# handle per exception
-#
-pgm_per:
-        tm      __LC_PGM_OLD_PSW,0x40   # test if per event recording is on
-        jnz     pgm_per_std             # ok, normal per event from user space
-# ok its one of the special cases, now we need to find out which one
-        clc     __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
-        je      pgm_svcper
-# no interesting special case, ignore PER event
-        lpswe   __LC_PGM_OLD_PSW
-
-#
-# Normal per exception
-#
-pgm_per_std:
-        SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        mvc     SP_PSW(16,%r15),__LC_PGM_OLD_PSW
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        HANDLE_SIE_INTERCEPT
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        jz      pgm_no_vtime2
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        LAST_BREAK
-pgm_no_vtime2:
+        stmg    %r8,%r15,__LC_SAVE_AREA_SYNC
+        lg      %r10,__LC_LAST_BREAK
+        lg      %r12,__LC_THREAD_INFO
+        larl    %r13,system_call
+        lmg     %r8,%r9,__LC_PGM_OLD_PSW
+        HANDLE_SIE_INTERCEPT %r14
+        tmhh    %r8,0x0001              # test problem state bit
+        jnz     1f                      # -> fault in user space
+        tmhh    %r8,0x4000              # PER bit set in old PSW ?
+        jnz     0f                      # -> enabled, can't be a double fault
+        tm      __LC_PGM_ILC+3,0x80     # check for per exception
+        jnz     pgm_svcper              # -> single stepped svc
+0:      CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
+        j       2f
+1:      UPDATE_VTIME %r14,__LC_SYNC_ENTER_TIMER
+        LAST_BREAK %r14
+        lg      %r15,__LC_KERNEL_STACK
+2:      aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        stmg    %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
+        stmg    %r8,%r9,__PT_PSW(%r11)
+        mvc     __PT_INT_CODE(4,%r11),__LC_PGM_ILC
+        mvc     __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
+        stg     %r10,__PT_ARGS(%r11)
+        tm      __LC_PGM_ILC+3,0x80     # check for per exception
+        jz      0f
         lg      %r1,__TI_task(%r12)
-        tm      SP_PSW+1(%r15),0x01     # kernel per event ?
-        jz      kernel_per
-        mvc     __THREAD_per_cause(2,%r1),__LC_PER_CAUSE
+        tmhh    %r8,0x0001              # kernel per event ?
+        jz      pgm_kprobe
+        oi      __TI_flags+7(%r12),_TIF_PER_TRAP
         mvc     __THREAD_per_address(8,%r1),__LC_PER_ADDRESS
+        mvc     __THREAD_per_cause(2,%r1),__LC_PER_CAUSE
         mvc     __THREAD_per_paid(1,%r1),__LC_PER_PAID
-        oi      __TI_flags+7(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP
-        lgf     %r3,__LC_PGM_ILC        # load program interruption code
-        lg      %r4,__LC_TRANS_EXC_CODE
-        REENABLE_IRQS
-        lghi    %r8,0x7f
-        ngr     %r8,%r3                 # clear per-event-bit and ilc
-        je      pgm_exit2
-        sll     %r8,3
+0:      REENABLE_IRQS
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
         larl    %r1,pgm_check_table
-        lg      %r1,0(%r8,%r1)          # load address of handler routine
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
+        llgh    %r10,__PT_INT_CODE+2(%r11)
+        nill    %r10,0x007f
+        sll     %r10,3
+        je      sysc_return
+        lg      %r1,0(%r10,%r1)         # load address of handler routine
+        lgr     %r2,%r11                # pass pointer to pt_regs
         basr    %r14,%r1                # branch to interrupt-handler
-pgm_exit2:
         j       sysc_return
 
 #
-# it was a single stepped SVC that is causing all the trouble
+# PER event in supervisor state, must be kprobes
 #
-pgm_svcper:
-        SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        mvc     SP_PSW(16,%r15),__LC_SVC_OLD_PSW
-        mvc     SP_SVC_CODE(4,%r15),__LC_SVC_ILC
-        oi      __TI_flags+7(%r12),(_TIF_SYSCALL | _TIF_PER_TRAP)
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        LAST_BREAK
-        lg      %r8,__TI_task(%r12)
-        mvc     __THREAD_per_cause(2,%r8),__LC_PER_CAUSE
-        mvc     __THREAD_per_address(8,%r8),__LC_PER_ADDRESS
-        mvc     __THREAD_per_paid(1,%r8),__LC_PER_PAID
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        lmg     %r2,%r6,SP_R2(%r15)     # load svc arguments
-        j       sysc_do_svc
+pgm_kprobe:
+        REENABLE_IRQS
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        brasl   %r14,do_per_trap
+        j       sysc_return
 
 #
-# per was called from kernel, must be kprobes
+# single stepped system call
 #
-kernel_per:
-        REENABLE_IRQS
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        brasl   %r14,do_per_trap
-        j       pgm_exit
+pgm_svcper:
+        oi      __TI_flags+7(%r12),_TIF_PER_TRAP
+        mvc     __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
+        larl    %r14,sysc_per
+        stg     %r14,__LC_RETURN_PSW+8
+        lpswe   __LC_RETURN_PSW         # branch to sysc_per and enable irqs
 
 /*
  * IO interrupt handler routine
@@ -565,21 +460,25 @@ kernel_per:
 ENTRY(io_int_handler)
         stck    __LC_INT_CLOCK
         stpt    __LC_ASYNC_ENTER_TIMER
-        SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+40
-        CREATE_STACK_FRAME __LC_SAVE_AREA+40
-        mvc     SP_PSW(16,%r15),0(%r12) # move user PSW to stack
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        HANDLE_SIE_INTERCEPT
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        jz      io_no_vtime
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
-        LAST_BREAK
-io_no_vtime:
+        stmg    %r8,%r15,__LC_SAVE_AREA_ASYNC
+        lg      %r10,__LC_LAST_BREAK
+        lg      %r12,__LC_THREAD_INFO
+        larl    %r13,system_call
+        lmg     %r8,%r9,__LC_IO_OLD_PSW
+        HANDLE_SIE_INTERCEPT %r14
+        SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_STACK,STACK_SHIFT
+        tmhh    %r8,0x0001              # interrupting from user?
+        jz      io_skip
+        UPDATE_VTIME %r14,__LC_ASYNC_ENTER_TIMER
+        LAST_BREAK %r14
+io_skip:
+        stmg    %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
+        stmg    %r8,%r9,__PT_PSW(%r11)
         TRACE_IRQS_OFF
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        brasl   %r14,do_IRQ             # call standard irq handler
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        brasl   %r14,do_IRQ
 io_return:
         LOCKDEP_SYS_EXIT
         TRACE_IRQS_ON
@@ -587,7 +486,14 @@ io_tif:
         tm      __TI_flags+7(%r12),_TIF_WORK_INT
         jnz     io_work                 # there is work to do (signals etc.)
 io_restore:
-        RESTORE_ALL __LC_RETURN_PSW,0
+        lg      %r14,__LC_VDSO_PER_CPU
+        lmg     %r0,%r10,__PT_R0(%r11)
+        mvc     __LC_RETURN_PSW(16),__PT_PSW(%r11)
+        ni      __LC_RETURN_PSW+1,0xfd  # clear wait state bit
+        stpt    __LC_EXIT_TIMER
+        mvc     __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
+        lmg     %r11,%r15,__PT_R11(%r11)
+        lpswe   __LC_RETURN_PSW
 io_done:
 
 #
@@ -600,7 +506,7 @@ io_done:
 # Before any work can be done, a switch to the kernel stack is required.
 #
 io_work:
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
+        tm      __PT_PSW+1(%r11),0x01   # returning to user ?
         jo      io_work_user            # yes -> do resched & signal
 #ifdef CONFIG_PREEMPT
         # check for preemptive scheduling
@@ -609,10 +515,11 @@ io_work:
         tm      __TI_flags+7(%r12),_TIF_NEED_RESCHED
         jno     io_restore
         # switch to kernel stack
-        lg      %r1,SP_R15(%r15)
-        aghi    %r1,-SP_SIZE
-        mvc     SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
-        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
+        lg      %r1,__PT_R15(%r11)
+        aghi    %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
+        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
+        la      %r11,STACK_FRAME_OVERHEAD(%r1)
         lgr     %r15,%r1
         # TRACE_IRQS_ON already done at io_return, call
         # TRACE_IRQS_OFF to keep things symmetrical
@@ -628,9 +535,10 @@ io_work:
 #
 io_work_user:
         lg      %r1,__LC_KERNEL_STACK
-        aghi    %r1,-SP_SIZE
-        mvc     SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
-        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
+        aghi    %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
+        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
+        la      %r11,STACK_FRAME_OVERHEAD(%r1)
         lgr     %r15,%r1
 
 #
@@ -663,9 +571,9 @@ io_mcck_pending:
 #
 io_reschedule:
         # TRACE_IRQS_ON already done at io_return
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
         brasl   %r14,schedule           # call scheduler
-        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         TRACE_IRQS_OFF
         j       io_return
 
@@ -674,10 +582,10 @@ io_reschedule:
 #
 io_sigpending:
         # TRACE_IRQS_ON already done at io_return
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        brasl   %r14,do_signal          # call do_signal
-        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        brasl   %r14,do_signal
+        ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         TRACE_IRQS_OFF
         j       io_return
 
@@ -686,10 +594,10 @@ io_sigpending:
 #
 io_notify_resume:
         # TRACE_IRQS_ON already done at io_return
-        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        brasl   %r14,do_notify_resume   # call do_notify_resume
-        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        ssm     __LC_SVC_NEW_PSW        # reenable interrupts
+        lgr     %r2,%r11                # pass pointer to pt_regs
+        brasl   %r14,do_notify_resume
+        ssm     __LC_PGM_NEW_PSW        # disable I/O and ext. interrupts
         TRACE_IRQS_OFF
         j       io_return
 
@@ -699,21 +607,24 @@ io_notify_resume:
 ENTRY(ext_int_handler)
         stck    __LC_INT_CLOCK
         stpt    __LC_ASYNC_ENTER_TIMER
-        SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+40
-        CREATE_STACK_FRAME __LC_SAVE_AREA+40
-        mvc     SP_PSW(16,%r15),0(%r12) # move user PSW to stack
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        HANDLE_SIE_INTERCEPT
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        jz      ext_no_vtime
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
-        LAST_BREAK
-ext_no_vtime:
+        stmg    %r8,%r15,__LC_SAVE_AREA_ASYNC
+        lg      %r10,__LC_LAST_BREAK
+        lg      %r12,__LC_THREAD_INFO
+        larl    %r13,system_call
+        lmg     %r8,%r9,__LC_EXT_OLD_PSW
+        HANDLE_SIE_INTERCEPT %r14
+        SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_STACK,STACK_SHIFT
+        tmhh    %r8,0x0001              # interrupting from user ?
+        jz      ext_skip
+        UPDATE_VTIME %r14,__LC_ASYNC_ENTER_TIMER
+        LAST_BREAK %r14
+ext_skip:
+        stmg    %r0,%r7,__PT_R0(%r11)
+        mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
+        stmg    %r8,%r9,__PT_PSW(%r11)
         TRACE_IRQS_OFF
         lghi    %r1,4096
-        la      %r2,SP_PTREGS(%r15)     # address of register-save area
+        lgr     %r2,%r11                # pass pointer to pt_regs
         llgf    %r3,__LC_CPU_ADDRESS    # get cpu address + interruption code
         llgf    %r4,__LC_EXT_PARAMS     # get external parameter
         lg      %r5,__LC_EXT_PARAMS2-4096(%r1)  # get 64 bit external parameter
@@ -730,81 +641,77 @@ ENTRY(mcck_int_handler)
         la      %r1,4095                # revalidate r1
         spt     __LC_CPU_TIMER_SAVE_AREA-4095(%r1)      # revalidate cpu timer
         lmg     %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
-        stmg    %r11,%r15,__LC_SAVE_AREA+80
+        lg      %r10,__LC_LAST_BREAK
+        lg      %r12,__LC_THREAD_INFO
         larl    %r13,system_call
-        lg      %r11,__LC_LAST_BREAK
-        la      %r12,__LC_MCK_OLD_PSW
+        lmg     %r8,%r9,__LC_MCK_OLD_PSW
+        HANDLE_SIE_INTERCEPT %r14
         tm      __LC_MCCK_CODE,0x80     # system damage?
-        jo      mcck_int_main           # yes -> rest of mcck code invalid
-        la      %r14,4095
-        mvc     __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
+        jo      mcck_panic              # yes -> rest of mcck code invalid
+        lghi    %r14,__LC_CPU_TIMER_SAVE_AREA
+        mvc     __LC_MCCK_ENTER_TIMER(8),0(%r14)
         tm      __LC_MCCK_CODE+5,0x02   # stored cpu timer value valid?
-        jo      1f
+        jo      3f
         la      %r14,__LC_SYNC_ENTER_TIMER
         clc     0(8,%r14),__LC_ASYNC_ENTER_TIMER
         jl      0f
         la      %r14,__LC_ASYNC_ENTER_TIMER
 0:      clc     0(8,%r14),__LC_EXIT_TIMER
-        jl      0f
+        jl      1f
         la      %r14,__LC_EXIT_TIMER
-0:      clc     0(8,%r14),__LC_LAST_UPDATE_TIMER
-        jl      0f
+1:      clc     0(8,%r14),__LC_LAST_UPDATE_TIMER
+        jl      2f
         la      %r14,__LC_LAST_UPDATE_TIMER
-0:      spt     0(%r14)
+2:      spt     0(%r14)
         mvc     __LC_MCCK_ENTER_TIMER(8),0(%r14)
-1:      tm      __LC_MCCK_CODE+2,0x09   # mwp + ia of old psw valid?
-        jno     mcck_int_main           # no -> skip cleanup critical
-        tm      __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
-        jnz     mcck_int_main           # from user -> load kernel stack
-        clc     __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
-        jhe     mcck_int_main
-        clc     __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
-        jl      mcck_int_main
-        brasl   %r14,cleanup_critical
-mcck_int_main:
-        lg      %r14,__LC_PANIC_STACK   # are we already on the panic stack?
-        slgr    %r14,%r15
-        srag    %r14,%r14,PAGE_SHIFT
-        jz      0f
-        lg      %r15,__LC_PANIC_STACK   # load panic stack
-0:      aghi    %r15,-SP_SIZE           # make room for registers & psw
-        CREATE_STACK_FRAME __LC_SAVE_AREA+80
-        mvc     SP_PSW(16,%r15),0(%r12)
-        lg      %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
-        tm      __LC_MCCK_CODE+2,0x08   # mwp of old psw valid?
-        jno     mcck_no_vtime           # no -> no timer update
-        HANDLE_SIE_INTERCEPT
-        tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
-        jz      mcck_no_vtime
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
-        LAST_BREAK
-mcck_no_vtime:
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+3:      tm      __LC_MCCK_CODE+2,0x09   # mwp + ia of old psw valid?
+        jno     mcck_panic              # no -> skip cleanup critical
+        SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_PANIC_STACK,PAGE_SHIFT
+        tm      %r8,0x0001              # interrupting from user ?
+        jz      mcck_skip
+        UPDATE_VTIME %r14,__LC_MCCK_ENTER_TIMER
+        LAST_BREAK %r14
+mcck_skip:
+        lghi    %r14,__LC_GPREGS_SAVE_AREA
+        mvc     __PT_R0(128,%r11),0(%r14)
+        stmg    %r8,%r9,__PT_PSW(%r11)
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+        lgr     %r2,%r11                # pass pointer to pt_regs
         brasl   %r14,s390_do_machine_check
-        tm      SP_PSW+1(%r15),0x01     # returning to user ?
+        tm      __PT_PSW+1(%r11),0x01   # returning to user ?
         jno     mcck_return
         lg      %r1,__LC_KERNEL_STACK   # switch to kernel stack
-        aghi    %r1,-SP_SIZE
-        mvc     SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
-        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
+        aghi    %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
+        xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
+        la      %r11,STACK_FRAME_OVERHEAD(%r1)
         lgr     %r15,%r1
-        stosm   __SF_EMPTY(%r15),0x04   # turn dat on
+        ssm     __LC_PGM_NEW_PSW        # turn dat on, keep irqs off
         tm      __TI_flags+7(%r12),_TIF_MCCK_PENDING
         jno     mcck_return
         TRACE_IRQS_OFF
         brasl   %r14,s390_handle_mcck
         TRACE_IRQS_ON
 mcck_return:
-        mvc     __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
+        lg      %r14,__LC_VDSO_PER_CPU
+        lmg     %r0,%r10,__PT_R0(%r11)
+        mvc     __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
         ni      __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
-        lmg     %r0,%r15,SP_R0(%r15)    # load gprs 0-15
         tm      __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
         jno     0f
         stpt    __LC_EXIT_TIMER
-0:      lpswe   __LC_RETURN_MCCK_PSW    # back to caller
-mcck_done:
+        mvc     __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
+0:      lmg     %r11,%r15,__PT_R11(%r11)
+        lpswe   __LC_RETURN_MCCK_PSW
+
+mcck_panic:
+        lg      %r14,__LC_PANIC_STACK
+        slgr    %r14,%r15
+        srag    %r14,%r14,PAGE_SHIFT
+        jz      0f
+        lg      %r15,__LC_PANIC_STACK
+0:      aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
+        j       mcck_skip
 
 /*
  * Restart interruption handler, kick starter for additional CPUs
@@ -818,17 +725,18 @@ restart_base:
         stck    __LC_LAST_UPDATE_CLOCK
         mvc     __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
         mvc     __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
-        lg      %r15,__LC_SAVE_AREA+120 # load ksp
+        lghi    %r10,__LC_GPREGS_SAVE_AREA
+        lg      %r15,120(%r10)          # load ksp
         lghi    %r10,__LC_CREGS_SAVE_AREA
-        lctlg   %c0,%c15,0(%r10) # get new ctl regs
+        lctlg   %c0,%c15,0(%r10)        # get new ctl regs
         lghi    %r10,__LC_AREGS_SAVE_AREA
         lam     %a0,%a15,0(%r10)
-        lmg     %r6,%r15,__SF_GPRS(%r15) # load registers from clone
+        lmg     %r6,%r15,__SF_GPRS(%r15)# load registers from clone
         lg      %r1,__LC_THREAD_INFO
         mvc     __LC_USER_TIMER(8),__TI_user_timer(%r1)
         mvc     __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
         xc      __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
-        stosm   __SF_EMPTY(%r15),0x04   # now we can turn dat on
+        ssm     __LC_PGM_NEW_PSW        # turn dat on, keep irqs off
         brasl   %r14,start_secondary
         .align  8
 restart_vtime:
@@ -852,16 +760,16 @@ restart_go:
 # PSW restart interrupt handler
 #
 ENTRY(psw_restart_int_handler)
-        stg     %r15,__LC_SAVE_AREA+120(%r0)    # save r15
+        stg     %r15,__LC_SAVE_AREA_RESTART
         larl    %r15,restart_stack              # load restart stack
         lg      %r15,0(%r15)
-        aghi    %r15,-SP_SIZE                   # make room for pt_regs
-        stmg    %r0,%r14,SP_R0(%r15)            # store gprs %r0-%r14 to stack
-        mvc     SP_R15(8,%r15),__LC_SAVE_AREA+120(%r0)# store saved %r15 to stack
-        mvc     SP_PSW(16,%r15),__LC_RST_OLD_PSW(%r0)# store restart old psw
-        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # set backchain to 0
+        aghi    %r15,-__PT_SIZE                 # create pt_regs on stack
+        stmg    %r0,%r14,__PT_R0(%r15)
+        mvc     __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
+        mvc     __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
+        aghi    %r15,-STACK_FRAME_OVERHEAD
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
         brasl   %r14,do_restart
-
         larl    %r14,restart_psw_crash          # load disabled wait PSW if
         lpswe   0(%r14)                         # do_restart returns
         .align 8
@@ -877,172 +785,153 @@ restart_psw_crash:
  * Setup a pt_regs so that show_trace can provide a good call trace.
  */
 stack_overflow:
-        lg      %r15,__LC_PANIC_STACK   # change to panic stack
-        aghi    %r15,-SP_SIZE
-        mvc     SP_PSW(16,%r15),0(%r12) # move user PSW to stack
-        stmg    %r0,%r10,SP_R0(%r15)    # store gprs %r0-%r10 to kernel stack
-        la      %r1,__LC_SAVE_AREA
-        chi     %r12,__LC_SVC_OLD_PSW
-        je      0f
-        chi     %r12,__LC_PGM_OLD_PSW
-        je      0f
-        la      %r1,__LC_SAVE_AREA+40
-0:      mvc     SP_R11(40,%r15),0(%r1)  # move %r11-%r15 to stack
-        mvc     SP_ARGS(8,%r15),__LC_LAST_BREAK
-        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
-        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        lg      %r11,__LC_PANIC_STACK   # change to panic stack
+        aghi    %r11,-__PT_SIZE         # create pt_regs
+        stmg    %r0,%r7,__PT_R0(%r11)
+        stmg    %r8,%r9,__PT_PSW(%r11)
+        mvc     __PT_R8(64,%r11),0(%r14)
+        stg     %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
+        lgr     %r15,%r11
+        aghi    %r15,-STACK_FRAME_OVERHEAD
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+        lgr     %r2,%r11                # pass pointer to pt_regs
         jg      kernel_stack_overflow
 #endif
 
-cleanup_table_system_call:
-        .quad   system_call, sysc_do_svc
-cleanup_table_sysc_tif:
-        .quad   sysc_tif, sysc_restore
-cleanup_table_sysc_restore:
-        .quad   sysc_restore, sysc_done
-cleanup_table_io_tif:
-        .quad   io_tif, io_restore
-cleanup_table_io_restore:
-        .quad   io_restore, io_done
+        .align  8
+cleanup_table:
+        .quad   system_call
+        .quad   sysc_do_svc
+        .quad   sysc_tif
+        .quad   sysc_restore
+        .quad   sysc_done
+        .quad   io_tif
+        .quad   io_restore
+        .quad   io_done
 
 cleanup_critical:
-        clc     8(8,%r12),BASED(cleanup_table_system_call)
+        clg     %r9,BASED(cleanup_table)        # system_call
         jl      0f
-        clc     8(8,%r12),BASED(cleanup_table_system_call+8)
+        clg     %r9,BASED(cleanup_table+8)      # sysc_do_svc
         jl      cleanup_system_call
-0:
-        clc     8(8,%r12),BASED(cleanup_table_sysc_tif)
+        clg     %r9,BASED(cleanup_table+16)     # sysc_tif
         jl      0f
-        clc     8(8,%r12),BASED(cleanup_table_sysc_tif+8)
+        clg     %r9,BASED(cleanup_table+24)     # sysc_restore
         jl      cleanup_sysc_tif
-0:
-        clc     8(8,%r12),BASED(cleanup_table_sysc_restore)
-        jl      0f
-        clc     8(8,%r12),BASED(cleanup_table_sysc_restore+8)
+        clg     %r9,BASED(cleanup_table+32)     # sysc_done
         jl      cleanup_sysc_restore
-0:
-        clc     8(8,%r12),BASED(cleanup_table_io_tif)
+        clg     %r9,BASED(cleanup_table+40)     # io_tif
         jl      0f
-        clc     8(8,%r12),BASED(cleanup_table_io_tif+8)
+        clg     %r9,BASED(cleanup_table+48)     # io_restore
         jl      cleanup_io_tif
-0:
-        clc     8(8,%r12),BASED(cleanup_table_io_restore)
-        jl      0f
-        clc     8(8,%r12),BASED(cleanup_table_io_restore+8)
+        clg     %r9,BASED(cleanup_table+56)     # io_done
         jl      cleanup_io_restore
-0:
-        br      %r14
+0:      br      %r14
+
 
 cleanup_system_call:
-        mvc     __LC_RETURN_PSW(16),0(%r12)
-        clc     __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
+        # check if stpt has been executed
+        clg     %r9,BASED(cleanup_system_call_insn)
         jh      0f
-        mvc     __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
-        cghi    %r12,__LC_MCK_OLD_PSW
-        je      0f
         mvc     __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
-0:      cghi    %r12,__LC_MCK_OLD_PSW
-        la      %r12,__LC_SAVE_AREA+80
+        cghi    %r11,__LC_SAVE_AREA_ASYNC
         je      0f
-        la      %r12,__LC_SAVE_AREA+40
-0:      clc     __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
-        jhe     cleanup_vtime
-        clc     __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
+        mvc     __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
+0:      # check if stmg has been executed
+        clg     %r9,BASED(cleanup_system_call_insn+8)
         jh      0f
-        mvc     __LC_SAVE_AREA(40),0(%r12)
-0:      lg      %r15,__LC_KERNEL_STACK  # problem state -> load ksp
-        aghi    %r15,-SP_SIZE           # make room for registers & psw
-        stg     %r15,32(%r12)
-        stg     %r11,0(%r12)
-        CREATE_STACK_FRAME __LC_SAVE_AREA
-        mvc     8(8,%r12),__LC_THREAD_INFO
-        lg      %r12,__LC_THREAD_INFO
-        mvc     SP_PSW(16,%r15),__LC_SVC_OLD_PSW
-        mvc     SP_SVC_CODE(4,%r15),__LC_SVC_ILC
-        oi      __TI_flags+7(%r12),_TIF_SYSCALL
-cleanup_vtime:
-        clc     __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
-        jhe     cleanup_stime
-        UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
-cleanup_stime:
-        clc     __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
-        jh      cleanup_update
-        UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
-cleanup_update:
+        mvc     __LC_SAVE_AREA_SYNC(64),0(%r11)
+0:      # check if base register setup + TIF bit load has been done
+        clg     %r9,BASED(cleanup_system_call_insn+16)
+        jhe     0f
+        # set up saved registers r10 and r12
+        stg     %r10,16(%r11)           # r10 last break
+        stg     %r12,32(%r11)           # r12 thread-info pointer
+0:      # check if the user time update has been done
+        clg     %r9,BASED(cleanup_system_call_insn+24)
+        jh      0f
+        lg      %r15,__LC_EXIT_TIMER
+        slg     %r15,__LC_SYNC_ENTER_TIMER
+        alg     %r15,__LC_USER_TIMER
+        stg     %r15,__LC_USER_TIMER
+0:      # check if the system time update has been done
+        clg     %r9,BASED(cleanup_system_call_insn+32)
+        jh      0f
+        lg      %r15,__LC_LAST_UPDATE_TIMER
+        slg     %r15,__LC_EXIT_TIMER
+        alg     %r15,__LC_SYSTEM_TIMER
+        stg     %r15,__LC_SYSTEM_TIMER
+0:      # update accounting time stamp
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        srag    %r12,%r11,23
-        lg      %r12,__LC_THREAD_INFO
+        # do LAST_BREAK
+        lg      %r9,16(%r11)
+        srag    %r9,%r9,23
         jz      0f
-        stg     %r11,__TI_last_break(%r12)
-0:      mvc     __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
-        la      %r12,__LC_RETURN_PSW
+        mvc     __TI_last_break(8,%r12),16(%r11)
+0:      # set up saved register r11
+        lg      %r15,__LC_KERNEL_STACK
+        aghi    %r15,-__PT_SIZE
+        stg     %r15,24(%r11)           # r11 pt_regs pointer
+        # fill pt_regs
+        mvc     __PT_R8(64,%r15),__LC_SAVE_AREA_SYNC
+        stmg    %r0,%r7,__PT_R0(%r15)
+        mvc     __PT_PSW(16,%r15),__LC_SVC_OLD_PSW
+        mvc     __PT_INT_CODE(4,%r15),__LC_SVC_ILC
+        # setup saved register r15
+        aghi    %r15,-STACK_FRAME_OVERHEAD
+        stg     %r15,56(%r11)           # r15 stack pointer
+        # set new psw address and exit
+        larl    %r9,sysc_do_svc
         br      %r14
 cleanup_system_call_insn:
-        .quad   sysc_saveall
         .quad   system_call
-        .quad   sysc_vtime
-        .quad   sysc_stime
-        .quad   sysc_update
+        .quad   sysc_stmg
+        .quad   sysc_per
+        .quad   sysc_vtime+18
+        .quad   sysc_vtime+42
 
 cleanup_sysc_tif:
-        mvc     __LC_RETURN_PSW(8),0(%r12)
-        mvc     __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_tif)
-        la      %r12,__LC_RETURN_PSW
+        larl    %r9,sysc_tif
         br      %r14
 
 cleanup_sysc_restore:
-        clc     8(8,%r12),BASED(cleanup_sysc_restore_insn)
-        je      2f
-        clc     8(8,%r12),BASED(cleanup_sysc_restore_insn+8)
-        jhe     0f
-        mvc     __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
-        cghi    %r12,__LC_MCK_OLD_PSW
+        clg     %r9,BASED(cleanup_sysc_restore_insn)
         je      0f
-        mvc     __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
-0:      mvc     __LC_RETURN_PSW(16),SP_PSW(%r15)
-        cghi    %r12,__LC_MCK_OLD_PSW
-        la      %r12,__LC_SAVE_AREA+80
-        je      1f
-        la      %r12,__LC_SAVE_AREA+40
-1:      mvc     0(40,%r12),SP_R11(%r15)
-        lmg     %r0,%r10,SP_R0(%r15)
-        lg      %r15,SP_R15(%r15)
-2:      la      %r12,__LC_RETURN_PSW
+        lg      %r9,24(%r11)            # get saved pointer to pt_regs
+        mvc     __LC_RETURN_PSW(16),__PT_PSW(%r9)
+        mvc     0(64,%r11),__PT_R8(%r9)
+        lmg     %r0,%r7,__PT_R0(%r9)
+0:      lmg     %r8,%r9,__LC_RETURN_PSW
         br      %r14
 cleanup_sysc_restore_insn:
         .quad   sysc_done - 4
-        .quad   sysc_done - 16
 
 cleanup_io_tif:
-        mvc     __LC_RETURN_PSW(8),0(%r12)
-        mvc     __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_tif)
-        la      %r12,__LC_RETURN_PSW
+        larl    %r9,io_tif
         br      %r14
 
 cleanup_io_restore:
-        clc     8(8,%r12),BASED(cleanup_io_restore_insn)
-        je      1f
-        clc     8(8,%r12),BASED(cleanup_io_restore_insn+8)
-        jhe     0f
-        mvc     __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
-0:      mvc     __LC_RETURN_PSW(16),SP_PSW(%r15)
-        mvc     __LC_SAVE_AREA+80(40),SP_R11(%r15)
-        lmg     %r0,%r10,SP_R0(%r15)
-        lg      %r15,SP_R15(%r15)
-1:      la      %r12,__LC_RETURN_PSW
+        clg     %r9,BASED(cleanup_io_restore_insn)
+        je      0f
+        lg      %r9,24(%r11)            # get saved r11 pointer to pt_regs
+        mvc     __LC_RETURN_PSW(16),__PT_PSW(%r9)
+        ni      __LC_RETURN_PSW+1,0xfd  # clear wait state bit
+        mvc     0(64,%r11),__PT_R8(%r9)
+        lmg     %r0,%r7,__PT_R0(%r9)
+0:      lmg     %r8,%r9,__LC_RETURN_PSW
         br      %r14
 cleanup_io_restore_insn:
         .quad   io_done - 4
-        .quad   io_done - 16
 
 /*
  * Integer constants
  */
-                .align  4
+        .align  8
 .Lcritical_start:
-                .quad   __critical_start
-.Lcritical_end:
-                .quad   __critical_end
+        .quad   __critical_start
+.Lcritical_length:
+        .quad   __critical_end - __critical_start
+
 
 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
 /*
@@ -1054,6 +943,7 @@ ENTRY(sie64a)
         stmg    %r6,%r14,__SF_GPRS(%r15)        # save kernel registers
         stg     %r2,__SF_EMPTY(%r15)            # save control block pointer
         stg     %r3,__SF_EMPTY+8(%r15)          # save guest register save area
+        xc      __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # host id == 0
         lmg     %r0,%r13,0(%r3)                 # load guest gprs 0-13
         lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
         oi      __TI_flags+6(%r14),_TIF_SIE>>8
@@ -1070,7 +960,7 @@ sie_gmap:
         SPP     __SF_EMPTY(%r15)                # set guest id
         sie     0(%r14)
 sie_done:
-        SPP     __LC_CMF_HPP                    # set host id
+        SPP     __SF_EMPTY+16(%r15)             # set host id
         lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
 sie_exit:
         lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
@@ -1093,8 +983,10 @@ sie_fault:
         .align  8
 .Lsie_loop:
         .quad   sie_loop
-.Lsie_done:
-        .quad   sie_done
+.Lsie_length:
+        .quad   sie_done - sie_loop
+.Lhost_id:
+        .quad   0
 
         .section __ex_table,"a"
         .quad   sie_loop,sie_fault
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index 900068d2bf9..c27a0727f93 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -329,8 +329,8 @@ iplstart:
 #
 # reset files in VM reader
 #
-        stidp   __LC_SAVE_AREA          # store cpuid
-        tm      __LC_SAVE_AREA,0xff     # running VM ?
+        stidp   __LC_SAVE_AREA_SYNC     # store cpuid
+        tm      __LC_SAVE_AREA_SYNC,0xff# running VM ?
         bno     .Lnoreset
         la      %r2,.Lreset
         lhi     %r3,26
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index 3cd0f25ab01..47b168fb29c 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -208,6 +208,7 @@ void machine_kexec_cleanup(struct kimage *image)
 void arch_crash_save_vmcoreinfo(void)
 {
         VMCOREINFO_SYMBOL(lowcore_ptr);
+        VMCOREINFO_SYMBOL(high_memory);
         VMCOREINFO_LENGTH(lowcore_ptr, NR_CPUS);
 }
 
diff --git a/arch/s390/kernel/mem_detect.c b/arch/s390/kernel/mem_detect.c
index 19b4568f4ce..22d502e885e 100644
--- a/arch/s390/kernel/mem_detect.c
+++ b/arch/s390/kernel/mem_detect.c
@@ -64,70 +64,82 @@ void detect_memory_layout(struct mem_chunk chunk[])
 EXPORT_SYMBOL(detect_memory_layout);
 
 /*
+ * Move memory chunks array from index "from" to index "to"
+ */
+static void mem_chunk_move(struct mem_chunk chunk[], int to, int from)
+{
+        int cnt = MEMORY_CHUNKS - to;
+
+        memmove(&chunk[to], &chunk[from], cnt * sizeof(struct mem_chunk));
+}
+
+/*
+ * Initialize memory chunk
+ */
+static void mem_chunk_init(struct mem_chunk *chunk, unsigned long addr,
+                           unsigned long size, int type)
+{
+        chunk->type = type;
+        chunk->addr = addr;
+        chunk->size = size;
+}
+
+/*
  * Create memory hole with given address, size, and type
  */
-void create_mem_hole(struct mem_chunk chunks[], unsigned long addr,
+void create_mem_hole(struct mem_chunk chunk[], unsigned long addr,
                      unsigned long size, int type)
 {
-        unsigned long start, end, new_size;
-        int i;
+        unsigned long lh_start, lh_end, lh_size, ch_start, ch_end, ch_size;
+        int i, ch_type;
 
         for (i = 0; i < MEMORY_CHUNKS; i++) {
-                if (chunks[i].size == 0)
-                        continue;
-                if (addr + size < chunks[i].addr)
-                        continue;
-                if (addr >= chunks[i].addr + chunks[i].size)
+                if (chunk[i].size == 0)
                         continue;
-                start = max(addr, chunks[i].addr);
-                end = min(addr + size, chunks[i].addr + chunks[i].size);
-                new_size = end - start;
-                if (new_size == 0)
-                        continue;
-                if (start == chunks[i].addr &&
-                    end == chunks[i].addr + chunks[i].size) {
-                        /* Remove chunk */
-                        chunks[i].type = type;
-                } else if (start == chunks[i].addr) {
-                        /* Make chunk smaller at start */
-                        if (i >= MEMORY_CHUNKS - 1)
-                                panic("Unable to create memory hole");
-                        memmove(&chunks[i + 1], &chunks[i],
-                                sizeof(struct mem_chunk) *
-                                (MEMORY_CHUNKS - (i + 1)));
-                        chunks[i + 1].addr = chunks[i].addr + new_size;
-                        chunks[i + 1].size = chunks[i].size - new_size;
-                        chunks[i].size = new_size;
-                        chunks[i].type = type;
-                        i += 1;
-                } else if (end == chunks[i].addr + chunks[i].size) {
-                        /* Make chunk smaller at end */
-                        if (i >= MEMORY_CHUNKS - 1)
-                                panic("Unable to create memory hole");
-                        memmove(&chunks[i + 1], &chunks[i],
-                                sizeof(struct mem_chunk) *
-                                (MEMORY_CHUNKS - (i + 1)));
-                        chunks[i + 1].addr = start;
-                        chunks[i + 1].size = new_size;
-                        chunks[i + 1].type = type;
-                        chunks[i].size -= new_size;
+
+                /* Define chunk properties */
+                ch_start = chunk[i].addr;
+                ch_size = chunk[i].size;
+                ch_end = ch_start + ch_size - 1;
+                ch_type = chunk[i].type;
+
+                /* Is memory chunk hit by memory hole? */
+                if (addr + size <= ch_start)
+                        continue; /* No: memory hole in front of chunk */
+                if (addr > ch_end)
+                        continue; /* No: memory hole after chunk */
+
+                /* Yes: Define local hole properties */
+                lh_start = max(addr, chunk[i].addr);
+                lh_end = min(addr + size - 1, ch_end);
+                lh_size = lh_end - lh_start + 1;
+
+                if (lh_start == ch_start && lh_end == ch_end) {
+                        /* Hole covers complete memory chunk */
+                        mem_chunk_init(&chunk[i], lh_start, lh_size, type);
+                } else if (lh_end == ch_end) {
+                        /* Hole starts in memory chunk and convers chunk end */
+                        mem_chunk_move(chunk, i + 1, i);
+                        mem_chunk_init(&chunk[i], ch_start, ch_size - lh_size,
+                                       ch_type);
+                        mem_chunk_init(&chunk[i + 1], lh_start, lh_size, type);
                         i += 1;
+                } else if (lh_start == ch_start) {
+                        /* Hole ends in memory chunk */
+                        mem_chunk_move(chunk, i + 1, i);
+                        mem_chunk_init(&chunk[i], lh_start, lh_size, type);
+                        mem_chunk_init(&chunk[i + 1], lh_end + 1,
+                                       ch_size - lh_size, ch_type);
+                        break;
                 } else {
-                        /* Create memory hole */
-                        if (i >= MEMORY_CHUNKS - 2)
-                                panic("Unable to create memory hole");
-                        memmove(&chunks[i + 2], &chunks[i],
-                                sizeof(struct mem_chunk) *
-                                (MEMORY_CHUNKS - (i + 2)));
-                        chunks[i + 1].addr = addr;
-                        chunks[i + 1].size = size;
-                        chunks[i + 1].type = type;
-                        chunks[i + 2].addr = addr + size;
-                        chunks[i + 2].size =
-                                chunks[i].addr + chunks[i].size - (addr + size);
-                        chunks[i + 2].type = chunks[i].type;
-                        chunks[i].size = addr - chunks[i].addr;
-                        i += 2;
+                        /* Hole splits memory chunk */
+                        mem_chunk_move(chunk, i + 2, i);
+                        mem_chunk_init(&chunk[i], ch_start,
+                                       lh_start - ch_start, ch_type);
+                        mem_chunk_init(&chunk[i + 1], lh_start, lh_size, type);
+                        mem_chunk_init(&chunk[i + 2], lh_end + 1,
+                                       ch_end - lh_end, ch_type);
+                        break;
                 }
         }
 }
diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S
index 732a793ec53..36b32658fb2 100644
--- a/arch/s390/kernel/reipl64.S
+++ b/arch/s390/kernel/reipl64.S
@@ -17,11 +17,11 @@
 #
 ENTRY(store_status)
         /* Save register one and load save area base */
-        stg     %r1,__LC_SAVE_AREA+120(%r0)
+        stg     %r1,__LC_SAVE_AREA_RESTART
         lghi    %r1,SAVE_AREA_BASE
         /* General purpose registers */
         stmg    %r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
-        lg      %r2,__LC_SAVE_AREA+120(%r0)
+        lg      %r2,__LC_SAVE_AREA_RESTART
         stg     %r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1)
         /* Control registers */
         stctg   %c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index f11d1b037c5..354de0763ef 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -95,6 +95,15 @@ struct mem_chunk __initdata memory_chunk[MEMORY_CHUNKS];
 int __initdata memory_end_set;
 unsigned long __initdata memory_end;
 
+unsigned long VMALLOC_START;
+EXPORT_SYMBOL(VMALLOC_START);
+
+unsigned long VMALLOC_END;
+EXPORT_SYMBOL(VMALLOC_END);
+
+struct page *vmemmap;
+EXPORT_SYMBOL(vmemmap);
+
 /* An array with a pointer to the lowcore of every CPU. */
 struct _lowcore *lowcore_ptr[NR_CPUS];
 EXPORT_SYMBOL(lowcore_ptr);
@@ -278,6 +287,15 @@ static int __init early_parse_mem(char *p)
 }
 early_param("mem", early_parse_mem);
 
+static int __init parse_vmalloc(char *arg)
+{
+        if (!arg)
+                return -EINVAL;
+        VMALLOC_END = (memparse(arg, &arg) + PAGE_SIZE - 1) & PAGE_MASK;
+        return 0;
+}
+early_param("vmalloc", parse_vmalloc);
+
 unsigned int user_mode = HOME_SPACE_MODE;
 EXPORT_SYMBOL_GPL(user_mode);
 
@@ -383,7 +401,6 @@ setup_lowcore(void)
                 __ctl_set_bit(14, 29);
         }
 #else
-        lc->cmf_hpp = -1ULL;
         lc->vdso_per_cpu_data = (unsigned long) &lc->paste[0];
 #endif
         lc->sync_enter_timer = S390_lowcore.sync_enter_timer;
@@ -479,8 +496,7 @@ EXPORT_SYMBOL_GPL(real_memory_size);
 
 static void __init setup_memory_end(void)
 {
-        unsigned long memory_size;
-        unsigned long max_mem;
+        unsigned long vmax, vmalloc_size, tmp;
         int i;
 
 
@@ -490,12 +506,9 @@ static void __init setup_memory_end(void)
                 memory_end_set = 1;
         }
 #endif
-        memory_size = 0;
+        real_memory_size = 0;
         memory_end &= PAGE_MASK;
 
-        max_mem = memory_end ? min(VMEM_MAX_PHYS, memory_end) : VMEM_MAX_PHYS;
-        memory_end = min(max_mem, memory_end);
-
         /*
          * Make sure all chunks are MAX_ORDER aligned so we don't need the
          * extra checks that HOLES_IN_ZONE would require.
@@ -515,23 +528,48 @@ static void __init setup_memory_end(void)
                         chunk->addr = start;
                         chunk->size = end - start;
                 }
+                real_memory_size = max(real_memory_size,
+                                       chunk->addr + chunk->size);
         }
 
+        /* Choose kernel address space layout: 2, 3, or 4 levels. */
+#ifdef CONFIG_64BIT
+        vmalloc_size = VMALLOC_END ?: 128UL << 30;
+        tmp = (memory_end ?: real_memory_size) / PAGE_SIZE;
+        tmp = tmp * (sizeof(struct page) + PAGE_SIZE) + vmalloc_size;
+        if (tmp <= (1UL << 42))
+                vmax = 1UL << 42;       /* 3-level kernel page table */
+        else
+                vmax = 1UL << 53;       /* 4-level kernel page table */
+#else
+        vmalloc_size = VMALLOC_END ?: 96UL << 20;
+        vmax = 1UL << 31;               /* 2-level kernel page table */
+#endif
+        /* vmalloc area is at the end of the kernel address space. */
+        VMALLOC_END = vmax;
+        VMALLOC_START = vmax - vmalloc_size;
+
+        /* Split remaining virtual space between 1:1 mapping & vmemmap array */
+        tmp = VMALLOC_START / (PAGE_SIZE + sizeof(struct page));
+        tmp = VMALLOC_START - tmp * sizeof(struct page);
+        tmp &= ~((vmax >> 11) - 1);     /* align to page table level */
+        tmp = min(tmp, 1UL << MAX_PHYSMEM_BITS);
+        vmemmap = (struct page *) tmp;
+
+        /* Take care that memory_end is set and <= vmemmap */
+        memory_end = min(memory_end ?: real_memory_size, tmp);
+
+        /* Fixup memory chunk array to fit into 0..memory_end */
         for (i = 0; i < MEMORY_CHUNKS; i++) {
                 struct mem_chunk *chunk = &memory_chunk[i];
 
-                real_memory_size = max(real_memory_size,
-                                       chunk->addr + chunk->size);
-                if (chunk->addr >= max_mem) {
+                if (chunk->addr >= memory_end) {
                         memset(chunk, 0, sizeof(*chunk));
                         continue;
                 }
-                if (chunk->addr + chunk->size > max_mem)
-                        chunk->size = max_mem - chunk->addr;
-                memory_size = max(memory_size, chunk->addr + chunk->size);
+                if (chunk->addr + chunk->size > memory_end)
+                        chunk->size = memory_end - chunk->addr;
         }
-        if (!memory_end)
-                memory_end = memory_size;
 }
 
 void *restart_stack __attribute__((__section__(".data")));
@@ -655,7 +693,6 @@ static int __init verify_crash_base(unsigned long crash_base,
 static void __init reserve_kdump_bootmem(unsigned long addr, unsigned long size,
                                          int type)
 {
-
         create_mem_hole(memory_chunk, addr, size, type);
 }
 
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index 7f6f9f35454..a8ba840294f 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -302,9 +302,13 @@ static int setup_frame(int sig, struct k_sigaction *ka,
 
         /* We forgot to include these in the sigcontext.
            To avoid breaking binary compatibility, they are passed as args. */
-        regs->gprs[4] = current->thread.trap_no;
-        regs->gprs[5] = current->thread.prot_addr;
-        regs->gprs[6] = task_thread_info(current)->last_break;
+        if (sig == SIGSEGV || sig == SIGBUS || sig == SIGILL ||
+            sig == SIGTRAP || sig == SIGFPE) {
+                /* set extra registers only for synchronous signals */
+                regs->gprs[4] = regs->int_code & 127;
+                regs->gprs[5] = regs->int_parm_long;
+                regs->gprs[6] = task_thread_info(current)->last_break;
+        }
 
         /* Place signal number on stack to allow backtrace from handler.  */
         if (__put_user(regs->gprs[2], (int __user *) &frame->signo))
@@ -434,13 +438,13 @@ void do_signal(struct pt_regs *regs)
          * call information.
          */
         current_thread_info()->system_call =
-                test_thread_flag(TIF_SYSCALL) ? regs->svc_code : 0;
+                test_thread_flag(TIF_SYSCALL) ? regs->int_code : 0;
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
 
         if (signr > 0) {
                 /* Whee!  Actually deliver the signal.  */
                 if (current_thread_info()->system_call) {
-                        regs->svc_code = current_thread_info()->system_call;
+                        regs->int_code = current_thread_info()->system_call;
                         /* Check for system call restarting. */
                         switch (regs->gprs[2]) {
                         case -ERESTART_RESTARTBLOCK:
@@ -457,7 +461,7 @@ void do_signal(struct pt_regs *regs)
                                 regs->gprs[2] = regs->orig_gpr2;
                                 regs->psw.addr =
                                         __rewind_psw(regs->psw,
-                                                     regs->svc_code >> 16);
+                                                     regs->int_code >> 16);
                                 break;
                         }
                 }
@@ -488,11 +492,11 @@ void do_signal(struct pt_regs *regs)
         /* No handlers present - check for system call restart */
         clear_thread_flag(TIF_SYSCALL);
         if (current_thread_info()->system_call) {
-                regs->svc_code = current_thread_info()->system_call;
+                regs->int_code = current_thread_info()->system_call;
                 switch (regs->gprs[2]) {
                 case -ERESTART_RESTARTBLOCK:
                         /* Restart with sys_restart_syscall */
-                        regs->svc_code = __NR_restart_syscall;
+                        regs->int_code = __NR_restart_syscall;
                 /* fallthrough */
                 case -ERESTARTNOHAND:
                 case -ERESTARTSYS:
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 66cca03c028..2398ce6b15a 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -69,9 +69,7 @@ enum s390_cpu_state {
 };
 
 DEFINE_MUTEX(smp_cpu_state_mutex);
-int smp_cpu_polarization[NR_CPUS];
 static int smp_cpu_state[NR_CPUS];
-static int cpu_management;
 
 static DEFINE_PER_CPU(struct cpu, cpu_devices);
 
@@ -149,29 +147,59 @@ void smp_switch_to_ipl_cpu(void (*func)(void *), void *data)
         sp -= sizeof(struct pt_regs);
         regs = (struct pt_regs *) sp;
         memcpy(&regs->gprs, &current_lc->gpregs_save_area, sizeof(regs->gprs));
-        regs->psw = lc->psw_save_area;
+        regs->psw = current_lc->psw_save_area;
         sp -= STACK_FRAME_OVERHEAD;
         sf = (struct stack_frame *) sp;
-        sf->back_chain = regs->gprs[15];
+        sf->back_chain = 0;
         smp_switch_to_cpu(func, data, sp, stap(), __cpu_logical_map[0]);
 }
 
+static void smp_stop_cpu(void)
+{
+        while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
+                cpu_relax();
+}
+
 void smp_send_stop(void)
 {
-        int cpu, rc;
+        cpumask_t cpumask;
+        int cpu;
+        u64 end;
 
         /* Disable all interrupts/machine checks */
         __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT);
         trace_hardirqs_off();
 
-        /* stop all processors */
-        for_each_online_cpu(cpu) {
-                if (cpu == smp_processor_id())
-                        continue;
-                do {
-                        rc = sigp(cpu, sigp_stop);
-                } while (rc == sigp_busy);
+        cpumask_copy(&cpumask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &cpumask);
+
+        if (oops_in_progress) {
+                /*
+                 * Give the other cpus the opportunity to complete
+                 * outstanding interrupts before stopping them.
+                 */
+                end = get_clock() + (1000000UL << 12);
+                for_each_cpu(cpu, &cpumask) {
+                        set_bit(ec_stop_cpu, (unsigned long *)
+                                &lowcore_ptr[cpu]->ext_call_fast);
+                        while (sigp(cpu, sigp_emergency_signal) == sigp_busy &&
+                               get_clock() < end)
+                                cpu_relax();
+                }
+                while (get_clock() < end) {
+                        for_each_cpu(cpu, &cpumask)
+                                if (cpu_stopped(cpu))
+                                        cpumask_clear_cpu(cpu, &cpumask);
+                        if (cpumask_empty(&cpumask))
+                                break;
+                        cpu_relax();
+                }
+        }
 
+        /* stop all processors */
+        for_each_cpu(cpu, &cpumask) {
+                while (sigp(cpu, sigp_stop) == sigp_busy)
+                        cpu_relax();
                 while (!cpu_stopped(cpu))
                         cpu_relax();
         }
@@ -187,7 +215,7 @@ static void do_ext_call_interrupt(unsigned int ext_int_code,
 {
         unsigned long bits;
 
-        if (ext_int_code == 0x1202)
+        if ((ext_int_code & 0xffff) == 0x1202)
                 kstat_cpu(smp_processor_id()).irqs[EXTINT_EXC]++;
         else
                 kstat_cpu(smp_processor_id()).irqs[EXTINT_EMS]++;
@@ -196,6 +224,9 @@ static void do_ext_call_interrupt(unsigned int ext_int_code,
          */
         bits = xchg(&S390_lowcore.ext_call_fast, 0);
 
+        if (test_bit(ec_stop_cpu, &bits))
+                smp_stop_cpu();
+
         if (test_bit(ec_schedule, &bits))
                 scheduler_ipi();
 
@@ -204,6 +235,7 @@ static void do_ext_call_interrupt(unsigned int ext_int_code,
 
         if (test_bit(ec_call_function_single, &bits))
                 generic_smp_call_function_single_interrupt();
+
 }
 
 /*
@@ -369,7 +401,7 @@ static int smp_rescan_cpus_sigp(cpumask_t avail)
                 if (cpu_known(cpu_id))
                         continue;
                 __cpu_logical_map[logical_cpu] = cpu_id;
-                smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN;
+                cpu_set_polarization(logical_cpu, POLARIZATION_UNKNOWN);
                 if (!cpu_stopped(logical_cpu))
                         continue;
                 set_cpu_present(logical_cpu, true);
@@ -403,7 +435,7 @@ static int smp_rescan_cpus_sclp(cpumask_t avail)
                 if (cpu_known(cpu_id))
                         continue;
                 __cpu_logical_map[logical_cpu] = cpu_id;
-                smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN;
+                cpu_set_polarization(logical_cpu, POLARIZATION_UNKNOWN);
                 set_cpu_present(logical_cpu, true);
                 if (cpu >= info->configured)
                         smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY;
@@ -656,7 +688,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
                                      - sizeof(struct stack_frame));
         memset(sf, 0, sizeof(struct stack_frame));
         sf->gprs[9] = (unsigned long) sf;
-        cpu_lowcore->save_area[15] = (unsigned long) sf;
+        cpu_lowcore->gpregs_save_area[15] = (unsigned long) sf;
         __ctl_store(cpu_lowcore->cregs_save_area, 0, 15);
         atomic_inc(&init_mm.context.attach_count);
         asm volatile(
@@ -806,7 +838,7 @@ void __init smp_prepare_boot_cpu(void)
         S390_lowcore.percpu_offset = __per_cpu_offset[0];
         current_set[0] = current;
         smp_cpu_state[0] = CPU_STATE_CONFIGURED;
-        smp_cpu_polarization[0] = POLARIZATION_UNKNWN;
+        cpu_set_polarization(0, POLARIZATION_UNKNOWN);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
@@ -868,7 +900,8 @@ static ssize_t cpu_configure_store(struct device *dev,
                         rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]);
                         if (!rc) {
                                 smp_cpu_state[cpu] = CPU_STATE_STANDBY;
-                                smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN;
+                                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
+                                topology_expect_change();
                         }
                 }
                 break;
@@ -877,7 +910,8 @@ static ssize_t cpu_configure_store(struct device *dev,
                         rc = sclp_cpu_configure(__cpu_logical_map[cpu]);
                         if (!rc) {
                                 smp_cpu_state[cpu] = CPU_STATE_CONFIGURED;
-                                smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN;
+                                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
+                                topology_expect_change();
                         }
                 }
                 break;
@@ -892,35 +926,6 @@ out:
 static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
 #endif /* CONFIG_HOTPLUG_CPU */
 
-static ssize_t cpu_polarization_show(struct device *dev,
-                                     struct device_attribute *attr, char *buf)
-{
-        int cpu = dev->id;
-        ssize_t count;
-
-        mutex_lock(&smp_cpu_state_mutex);
-        switch (smp_cpu_polarization[cpu]) {
-        case POLARIZATION_HRZ:
-                count = sprintf(buf, "horizontal\n");
-                break;
-        case POLARIZATION_VL:
-                count = sprintf(buf, "vertical:low\n");
-                break;
-        case POLARIZATION_VM:
-                count = sprintf(buf, "vertical:medium\n");
-                break;
-        case POLARIZATION_VH:
-                count = sprintf(buf, "vertical:high\n");
-                break;
-        default:
-                count = sprintf(buf, "unknown\n");
-                break;
-        }
-        mutex_unlock(&smp_cpu_state_mutex);
-        return count;
-}
-static DEVICE_ATTR(polarization, 0444, cpu_polarization_show, NULL);
-
 static ssize_t show_cpu_address(struct device *dev,
                                 struct device_attribute *attr, char *buf)
 {
@@ -928,13 +933,11 @@ static ssize_t show_cpu_address(struct device *dev,
 }
 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
 
-
 static struct attribute *cpu_common_attrs[] = {
 #ifdef CONFIG_HOTPLUG_CPU
         &dev_attr_configure.attr,
 #endif
         &dev_attr_address.attr,
-        &dev_attr_polarization.attr,
         NULL,
 };
 
@@ -1055,11 +1058,20 @@ static int __devinit smp_add_present_cpu(int cpu)
         rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
         if (rc)
                 goto out_cpu;
-        if (!cpu_online(cpu))
-                goto out;
-        rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
-        if (!rc)
-                return 0;
+        if (cpu_online(cpu)) {
+                rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
+                if (rc)
+                        goto out_online;
+        }
+        rc = topology_cpu_init(c);
+        if (rc)
+                goto out_topology;
+        return 0;
+
+out_topology:
+        if (cpu_online(cpu))
+                sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
+out_online:
         sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
 out_cpu:
 #ifdef CONFIG_HOTPLUG_CPU
@@ -1111,61 +1123,16 @@ static ssize_t __ref rescan_store(struct device *dev,
 static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
 #endif /* CONFIG_HOTPLUG_CPU */
 
-static ssize_t dispatching_show(struct device *dev,
-                                struct device_attribute *attr,
-                                char *buf)
-{
-        ssize_t count;
-
-        mutex_lock(&smp_cpu_state_mutex);
-        count = sprintf(buf, "%d\n", cpu_management);
-        mutex_unlock(&smp_cpu_state_mutex);
-        return count;
-}
-
-static ssize_t dispatching_store(struct device *dev,
-                                 struct device_attribute *attr,
-                                 const char *buf,
-                                 size_t count)
-{
-        int val, rc;
-        char delim;
-
-        if (sscanf(buf, "%d %c", &val, &delim) != 1)
-                return -EINVAL;
-        if (val != 0 && val != 1)
-                return -EINVAL;
-        rc = 0;
-        get_online_cpus();
-        mutex_lock(&smp_cpu_state_mutex);
-        if (cpu_management == val)
-                goto out;
-        rc = topology_set_cpu_management(val);
-        if (!rc)
-                cpu_management = val;
-out:
-        mutex_unlock(&smp_cpu_state_mutex);
-        put_online_cpus();
-        return rc ? rc : count;
-}
-static DEVICE_ATTR(dispatching, 0644, dispatching_show,
-                         dispatching_store);
-
-static int __init topology_init(void)
+static int __init s390_smp_init(void)
 {
-        int cpu;
-        int rc;
+        int cpu, rc;
 
         register_cpu_notifier(&smp_cpu_nb);
-
 #ifdef CONFIG_HOTPLUG_CPU
         rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
         if (rc)
                 return rc;
 #endif
-        rc = device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching);
-        if (rc)
-                return rc;
         for_each_present_cpu(cpu) {
                 rc = smp_add_present_cpu(cpu);
                 if (rc)
@@ -1173,4 +1140,4 @@ static int __init topology_init(void)
         }
         return 0;
 }
-subsys_initcall(topology_init);
+subsys_initcall(s390_smp_init);
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index 476081440df..78ea1948ff5 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -60,74 +60,22 @@ out:
 }
 
 /*
- * sys_ipc() is the de-multiplexer for the SysV IPC calls..
- *
- * This is really horribly ugly.
+ * sys_ipc() is the de-multiplexer for the SysV IPC calls.
  */
 SYSCALL_DEFINE5(s390_ipc, uint, call, int, first, unsigned long, second,
                 unsigned long, third, void __user *, ptr)
 {
-        struct ipc_kludge tmp;
-        int ret;
-
-        switch (call) {
-        case SEMOP:
-                return sys_semtimedop(first, (struct sembuf __user *)ptr,
-                                       (unsigned)second, NULL);
-        case SEMTIMEDOP:
-                return sys_semtimedop(first, (struct sembuf __user *)ptr,
-                                       (unsigned)second,
-                                       (const struct timespec __user *) third);
-        case SEMGET:
-                return sys_semget(first, (int)second, third);
-        case SEMCTL: {
-                union semun fourth;
-                if (!ptr)
-                        return -EINVAL;
-                if (get_user(fourth.__pad, (void __user * __user *) ptr))
-                        return -EFAULT;
-                return sys_semctl(first, (int)second, third, fourth);
-        }
-        case MSGSND:
-                return sys_msgsnd (first, (struct msgbuf __user *) ptr,
-                                   (size_t)second, third);
-                break;
-        case MSGRCV:
-                if (!ptr)
-                        return -EINVAL;
-                if (copy_from_user (&tmp, (struct ipc_kludge __user *) ptr,
-                                    sizeof (struct ipc_kludge)))
-                        return -EFAULT;
-                return sys_msgrcv (first, tmp.msgp,
-                                   (size_t)second, tmp.msgtyp, third);
-        case MSGGET:
-                return sys_msgget((key_t)first, (int)second);
-        case MSGCTL:
-                return sys_msgctl(first, (int)second,
-                                   (struct msqid_ds __user *)ptr);
-
-        case SHMAT: {
-                ulong raddr;
-                ret = do_shmat(first, (char __user *)ptr,
-                                (int)second, &raddr);
-                if (ret)
-                        return ret;
-                return put_user (raddr, (ulong __user *) third);
-                break;
-        }
-        case SHMDT:
-                return sys_shmdt ((char __user *)ptr);
-        case SHMGET:
-                return sys_shmget(first, (size_t)second, third);
-        case SHMCTL:
-                return sys_shmctl(first, (int)second,
-                                   (struct shmid_ds __user *) ptr);
-        default:
-                return -ENOSYS;
-
-        }
-
-        return -EINVAL;
+        if (call >> 16)
+                return -EINVAL;
+        /* The s390 sys_ipc variant has only five parameters instead of six
+         * like the generic variant. The only difference is the handling of
+         * the SEMTIMEDOP subcall where on s390 the third parameter is used
+         * as a pointer to a struct timespec where the generic variant uses
+         * the fifth parameter.
+         * Therefore we can call the generic variant by simply passing the
+         * third parameter also as fifth parameter.
+         */
+        return sys_ipc(call, first, second, third, ptr, third);
 }
 
 #ifdef CONFIG_64BIT
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 6e0e29b29a7..7370a41948c 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -1,22 +1,22 @@
 /*
- *    Copyright IBM Corp. 2007
+ *    Copyright IBM Corp. 2007,2011
  *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  */
 
 #define KMSG_COMPONENT "cpu"
 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
 
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/device.h>
+#include <linux/workqueue.h>
 #include <linux/bootmem.h>
+#include <linux/cpuset.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
 #include <linux/sched.h>
-#include <linux/workqueue.h>
+#include <linux/init.h>
+#include <linux/delay.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
-#include <linux/cpuset.h>
-#include <asm/delay.h>
+#include <linux/mm.h>
 
 #define PTF_HORIZONTAL  (0UL)
 #define PTF_VERTICAL    (1UL)
@@ -31,7 +31,6 @@ struct mask_info {
 static int topology_enabled = 1;
 static void topology_work_fn(struct work_struct *work);
 static struct sysinfo_15_1_x *tl_info;
-static struct timer_list topology_timer;
 static void set_topology_timer(void);
 static DECLARE_WORK(topology_work, topology_work_fn);
 /* topology_lock protects the core linked list */
@@ -41,11 +40,12 @@ static struct mask_info core_info;
 cpumask_t cpu_core_map[NR_CPUS];
 unsigned char cpu_core_id[NR_CPUS];
 
-#ifdef CONFIG_SCHED_BOOK
 static struct mask_info book_info;
 cpumask_t cpu_book_map[NR_CPUS];
 unsigned char cpu_book_id[NR_CPUS];
-#endif
+
+/* smp_cpu_state_mutex must be held when accessing this array */
+int cpu_polarization[NR_CPUS];
 
 static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu)
 {
@@ -71,7 +71,7 @@ static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu)
 static struct mask_info *add_cpus_to_mask(struct topology_cpu *tl_cpu,
                                           struct mask_info *book,
                                           struct mask_info *core,
-                                          int z10)
+                                          int one_core_per_cpu)
 {
         unsigned int cpu;
 
@@ -85,18 +85,16 @@ static struct mask_info *add_cpus_to_mask(struct topology_cpu *tl_cpu,
                 for_each_present_cpu(lcpu) {
                         if (cpu_logical_map(lcpu) != rcpu)
                                 continue;
-#ifdef CONFIG_SCHED_BOOK
                         cpumask_set_cpu(lcpu, &book->mask);
                         cpu_book_id[lcpu] = book->id;
-#endif
                         cpumask_set_cpu(lcpu, &core->mask);
-                        if (z10) {
+                        if (one_core_per_cpu) {
                                 cpu_core_id[lcpu] = rcpu;
                                 core = core->next;
                         } else {
                                 cpu_core_id[lcpu] = core->id;
                         }
-                        smp_cpu_polarization[lcpu] = tl_cpu->pp;
+                        cpu_set_polarization(lcpu, tl_cpu->pp);
                 }
         }
         return core;
@@ -111,13 +109,11 @@ static void clear_masks(void)
                 cpumask_clear(&info->mask);
                 info = info->next;
         }
-#ifdef CONFIG_SCHED_BOOK
         info = &book_info;
         while (info) {
                 cpumask_clear(&info->mask);
                 info = info->next;
         }
-#endif
 }
 
 static union topology_entry *next_tle(union topology_entry *tle)
@@ -127,66 +123,75 @@ static union topology_entry *next_tle(union topology_entry *tle)
         return (union topology_entry *)((struct topology_container *)tle + 1);
 }
 
-static void tl_to_cores(struct sysinfo_15_1_x *info)
+static void __tl_to_cores_generic(struct sysinfo_15_1_x *info)
 {
-#ifdef CONFIG_SCHED_BOOK
-        struct mask_info *book = &book_info;
-        struct cpuid cpu_id;
-#else
-        struct mask_info *book = NULL;
-#endif
         struct mask_info *core = &core_info;
+        struct mask_info *book = &book_info;
         union topology_entry *tle, *end;
-        int z10 = 0;
 
-#ifdef CONFIG_SCHED_BOOK
-        get_cpu_id(&cpu_id);
-        z10 = cpu_id.machine == 0x2097 || cpu_id.machine == 0x2098;
-#endif
-        spin_lock_irq(&topology_lock);
-        clear_masks();
         tle = info->tle;
         end = (union topology_entry *)((unsigned long)info + info->length);
         while (tle < end) {
-#ifdef CONFIG_SCHED_BOOK
-                if (z10) {
-                        switch (tle->nl) {
-                        case 1:
-                                book = book->next;
-                                book->id = tle->container.id;
-                                break;
-                        case 0:
-                                core = add_cpus_to_mask(&tle->cpu, book, core, z10);
-                                break;
-                        default:
-                                clear_masks();
-                                goto out;
-                        }
-                        tle = next_tle(tle);
-                        continue;
-                }
-#endif
                 switch (tle->nl) {
-#ifdef CONFIG_SCHED_BOOK
                 case 2:
                         book = book->next;
                         book->id = tle->container.id;
                         break;
-#endif
                 case 1:
                         core = core->next;
                         core->id = tle->container.id;
                         break;
                 case 0:
-                        add_cpus_to_mask(&tle->cpu, book, core, z10);
+                        add_cpus_to_mask(&tle->cpu, book, core, 0);
                         break;
                 default:
                         clear_masks();
-                        goto out;
+                        return;
                 }
                 tle = next_tle(tle);
         }
-out:
+}
+
+static void __tl_to_cores_z10(struct sysinfo_15_1_x *info)
+{
+        struct mask_info *core = &core_info;
+        struct mask_info *book = &book_info;
+        union topology_entry *tle, *end;
+
+        tle = info->tle;
+        end = (union topology_entry *)((unsigned long)info + info->length);
+        while (tle < end) {
+                switch (tle->nl) {
+                case 1:
+                        book = book->next;
+                        book->id = tle->container.id;
+                        break;
+                case 0:
+                        core = add_cpus_to_mask(&tle->cpu, book, core, 1);
+                        break;
+                default:
+                        clear_masks();
+                        return;
+                }
+                tle = next_tle(tle);
+        }
+}
+
+static void tl_to_cores(struct sysinfo_15_1_x *info)
+{
+        struct cpuid cpu_id;
+
+        get_cpu_id(&cpu_id);
+        spin_lock_irq(&topology_lock);
+        clear_masks();
+        switch (cpu_id.machine) {
+        case 0x2097:
+        case 0x2098:
+                __tl_to_cores_z10(info);
+                break;
+        default:
+                __tl_to_cores_generic(info);
+        }
         spin_unlock_irq(&topology_lock);
 }
 
@@ -196,7 +201,7 @@ static void topology_update_polarization_simple(void)
 
         mutex_lock(&smp_cpu_state_mutex);
         for_each_possible_cpu(cpu)
-                smp_cpu_polarization[cpu] = POLARIZATION_HRZ;
+                cpu_set_polarization(cpu, POLARIZATION_HRZ);
         mutex_unlock(&smp_cpu_state_mutex);
 }
 
@@ -215,8 +220,7 @@ static int ptf(unsigned long fc)
 
 int topology_set_cpu_management(int fc)
 {
-        int cpu;
-        int rc;
+        int cpu, rc;
 
         if (!MACHINE_HAS_TOPOLOGY)
                 return -EOPNOTSUPP;
@@ -227,7 +231,7 @@ int topology_set_cpu_management(int fc)
         if (rc)
                 return -EBUSY;
         for_each_possible_cpu(cpu)
-                smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN;
+                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
         return rc;
 }
 
@@ -239,22 +243,18 @@ static void update_cpu_core_map(void)
         spin_lock_irqsave(&topology_lock, flags);
         for_each_possible_cpu(cpu) {
                 cpu_core_map[cpu] = cpu_group_map(&core_info, cpu);
-#ifdef CONFIG_SCHED_BOOK
                 cpu_book_map[cpu] = cpu_group_map(&book_info, cpu);
-#endif
         }
         spin_unlock_irqrestore(&topology_lock, flags);
 }
 
 void store_topology(struct sysinfo_15_1_x *info)
 {
-#ifdef CONFIG_SCHED_BOOK
         int rc;
 
         rc = stsi(info, 15, 1, 3);
         if (rc != -ENOSYS)
                 return;
-#endif
         stsi(info, 15, 1, 2);
 }
 
@@ -296,12 +296,30 @@ static void topology_timer_fn(unsigned long ignored)
         set_topology_timer();
 }
 
+static struct timer_list topology_timer =
+        TIMER_DEFERRED_INITIALIZER(topology_timer_fn, 0, 0);
+
+static atomic_t topology_poll = ATOMIC_INIT(0);
+
 static void set_topology_timer(void)
 {
-        topology_timer.function = topology_timer_fn;
-        topology_timer.data = 0;
-        topology_timer.expires = jiffies + 60 * HZ;
-        add_timer(&topology_timer);
+        if (atomic_add_unless(&topology_poll, -1, 0))
+                mod_timer(&topology_timer, jiffies + HZ / 10);
+        else
+                mod_timer(&topology_timer, jiffies + HZ * 60);
+}
+
+void topology_expect_change(void)
+{
+        if (!MACHINE_HAS_TOPOLOGY)
+                return;
+        /* This is racy, but it doesn't matter since it is just a heuristic.
+         * Worst case is that we poll in a higher frequency for a bit longer.
+         */
+        if (atomic_read(&topology_poll) > 60)
+                return;
+        atomic_add(60, &topology_poll);
+        set_topology_timer();
 }
 
 static int __init early_parse_topology(char *p)
@@ -313,23 +331,6 @@ static int __init early_parse_topology(char *p)
 }
 early_param("topology", early_parse_topology);
 
-static int __init init_topology_update(void)
-{
-        int rc;
-
-        rc = 0;
-        if (!MACHINE_HAS_TOPOLOGY) {
-                topology_update_polarization_simple();
-                goto out;
-        }
-        init_timer_deferrable(&topology_timer);
-        set_topology_timer();
-out:
-        update_cpu_core_map();
-        return rc;
-}
-__initcall(init_topology_update);
-
 static void __init alloc_masks(struct sysinfo_15_1_x *info,
                                struct mask_info *mask, int offset)
 {
@@ -357,10 +358,108 @@ void __init s390_init_cpu_topology(void)
         store_topology(info);
         pr_info("The CPU configuration topology of the machine is:");
         for (i = 0; i < TOPOLOGY_NR_MAG; i++)
-                printk(" %d", info->mag[i]);
-        printk(" / %d\n", info->mnest);
+                printk(KERN_CONT " %d", info->mag[i]);
+        printk(KERN_CONT " / %d\n", info->mnest);
         alloc_masks(info, &core_info, 1);
-#ifdef CONFIG_SCHED_BOOK
         alloc_masks(info, &book_info, 2);
-#endif
 }
+
+static int cpu_management;
+
+static ssize_t dispatching_show(struct device *dev,
+                                struct device_attribute *attr,
+                                char *buf)
+{
+        ssize_t count;
+
+        mutex_lock(&smp_cpu_state_mutex);
+        count = sprintf(buf, "%d\n", cpu_management);
+        mutex_unlock(&smp_cpu_state_mutex);
+        return count;
+}
+
+static ssize_t dispatching_store(struct device *dev,
+                                 struct device_attribute *attr,
+                                 const char *buf,
+                                 size_t count)
+{
+        int val, rc;
+        char delim;
+
+        if (sscanf(buf, "%d %c", &val, &delim) != 1)
+                return -EINVAL;
+        if (val != 0 && val != 1)
+                return -EINVAL;
+        rc = 0;
+        get_online_cpus();
+        mutex_lock(&smp_cpu_state_mutex);
+        if (cpu_management == val)
+                goto out;
+        rc = topology_set_cpu_management(val);
+        if (rc)
+                goto out;
+        cpu_management = val;
+        topology_expect_change();
+out:
+        mutex_unlock(&smp_cpu_state_mutex);
+        put_online_cpus();
+        return rc ? rc : count;
+}
+static DEVICE_ATTR(dispatching, 0644, dispatching_show,
+                         dispatching_store);
+
+static ssize_t cpu_polarization_show(struct device *dev,
+                                     struct device_attribute *attr, char *buf)
+{
+        int cpu = dev->id;
+        ssize_t count;
+
+        mutex_lock(&smp_cpu_state_mutex);
+        switch (cpu_read_polarization(cpu)) {
+        case POLARIZATION_HRZ:
+                count = sprintf(buf, "horizontal\n");
+                break;
+        case POLARIZATION_VL:
+                count = sprintf(buf, "vertical:low\n");
+                break;
+        case POLARIZATION_VM:
+                count = sprintf(buf, "vertical:medium\n");
+                break;
+        case POLARIZATION_VH:
+                count = sprintf(buf, "vertical:high\n");
+                break;
+        default:
+                count = sprintf(buf, "unknown\n");
+                break;
+        }
+        mutex_unlock(&smp_cpu_state_mutex);
+        return count;
+}
+static DEVICE_ATTR(polarization, 0444, cpu_polarization_show, NULL);
+
+static struct attribute *topology_cpu_attrs[] = {
+        &dev_attr_polarization.attr,
+        NULL,
+};
+
+static struct attribute_group topology_cpu_attr_group = {
+        .attrs = topology_cpu_attrs,
+};
+
+int topology_cpu_init(struct cpu *cpu)
+{
+        return sysfs_create_group(&cpu->dev.kobj, &topology_cpu_attr_group);
+}
+
+static int __init topology_init(void)
+{
+        if (!MACHINE_HAS_TOPOLOGY) {
+                topology_update_polarization_simple();
+                goto out;
+        }
+        set_topology_timer();
+out:
+        update_cpu_core_map();
+        return device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching);
+}
+device_initcall(topology_init);
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index a9807dd8627..5ce3750b181 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -43,9 +43,9 @@
 #include <asm/debug.h>
 #include "entry.h"
 
-void (*pgm_check_table[128])(struct pt_regs *, long, unsigned long);
+void (*pgm_check_table[128])(struct pt_regs *regs);
 
-int show_unhandled_signals;
+int show_unhandled_signals = 1;
 
 #define stack_pointer ({ void **sp; asm("la %0,0(15)" : "=&d" (sp)); sp; })
 
@@ -234,7 +234,7 @@ void show_regs(struct pt_regs *regs)
 
 static DEFINE_SPINLOCK(die_lock);
 
-void die(const char * str, struct pt_regs * regs, long err)
+void die(struct pt_regs *regs, const char *str)
 {
         static int die_counter;
 
@@ -243,7 +243,7 @@ void die(const char * str, struct pt_regs * regs, long err)
         console_verbose();
         spin_lock_irq(&die_lock);
         bust_spinlocks(1);
-        printk("%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter);
+        printk("%s: %04x [#%d] ", str, regs->int_code & 0xffff, ++die_counter);
 #ifdef CONFIG_PREEMPT
         printk("PREEMPT ");
 #endif
@@ -254,7 +254,7 @@ void die(const char * str, struct pt_regs * regs, long err)
         printk("DEBUG_PAGEALLOC");
 #endif
         printk("\n");
-        notify_die(DIE_OOPS, str, regs, err, current->thread.trap_no, SIGSEGV);
+        notify_die(DIE_OOPS, str, regs, 0, regs->int_code & 0xffff, SIGSEGV);
         show_regs(regs);
         bust_spinlocks(0);
         add_taint(TAINT_DIE);
@@ -267,8 +267,7 @@ void die(const char * str, struct pt_regs * regs, long err)
         do_exit(SIGSEGV);
 }
 
-static void inline report_user_fault(struct pt_regs *regs, long int_code,
-                                     int signr)
+static inline void report_user_fault(struct pt_regs *regs, int signr)
 {
         if ((task_pid_nr(current) > 1) && !show_unhandled_signals)
                 return;
@@ -276,7 +275,7 @@ static void inline report_user_fault(struct pt_regs *regs, long int_code,
                 return;
         if (!printk_ratelimit())
                 return;
-        printk("User process fault: interruption code 0x%lX ", int_code);
+        printk("User process fault: interruption code 0x%X ", regs->int_code);
         print_vma_addr("in ", regs->psw.addr & PSW_ADDR_INSN);
         printk("\n");
         show_regs(regs);
@@ -287,19 +286,28 @@ int is_valid_bugaddr(unsigned long addr)
         return 1;
 }
 
-static inline void __kprobes do_trap(long pgm_int_code, int signr, char *str,
-                                     struct pt_regs *regs, siginfo_t *info)
+static inline void __user *get_psw_address(struct pt_regs *regs)
 {
-        if (notify_die(DIE_TRAP, str, regs, pgm_int_code,
-                       pgm_int_code, signr) == NOTIFY_STOP)
+        return (void __user *)
+                ((regs->psw.addr - (regs->int_code >> 16)) & PSW_ADDR_INSN);
+}
+
+static void __kprobes do_trap(struct pt_regs *regs,
+                              int si_signo, int si_code, char *str)
+{
+        siginfo_t info;
+
+        if (notify_die(DIE_TRAP, str, regs, 0,
+                       regs->int_code, si_signo) == NOTIFY_STOP)
                 return;
 
         if (regs->psw.mask & PSW_MASK_PSTATE) {
-                struct task_struct *tsk = current;
-
-                tsk->thread.trap_no = pgm_int_code & 0xffff;
-                force_sig_info(signr, info, tsk);
-                report_user_fault(regs, pgm_int_code, signr);
+                info.si_signo = si_signo;
+                info.si_errno = 0;
+                info.si_code = si_code;
+                info.si_addr = get_psw_address(regs);
+                force_sig_info(si_signo, &info, current);
+                report_user_fault(regs, si_signo);
         } else {
                 const struct exception_table_entry *fixup;
                 fixup = search_exception_tables(regs->psw.addr & PSW_ADDR_INSN);
@@ -311,18 +319,11 @@ static inline void __kprobes do_trap(long pgm_int_code, int signr, char *str,
                         btt = report_bug(regs->psw.addr & PSW_ADDR_INSN, regs);
                         if (btt == BUG_TRAP_TYPE_WARN)
                                 return;
-                        die(str, regs, pgm_int_code);
+                        die(regs, str);
                 }
         }
 }
 
-static inline void __user *get_psw_address(struct pt_regs *regs,
-                                           long pgm_int_code)
-{
-        return (void __user *)
-                ((regs->psw.addr - (pgm_int_code >> 16)) & PSW_ADDR_INSN);
-}
-
 void __kprobes do_per_trap(struct pt_regs *regs)
 {
         siginfo_t info;
@@ -339,26 +340,19 @@ void __kprobes do_per_trap(struct pt_regs *regs)
         force_sig_info(SIGTRAP, &info, current);
 }
 
-static void default_trap_handler(struct pt_regs *regs, long pgm_int_code,
-                                 unsigned long trans_exc_code)
+static void default_trap_handler(struct pt_regs *regs)
 {
         if (regs->psw.mask & PSW_MASK_PSTATE) {
-                report_user_fault(regs, pgm_int_code, SIGSEGV);
+                report_user_fault(regs, SIGSEGV);
                 do_exit(SIGSEGV);
         } else
-                die("Unknown program exception", regs, pgm_int_code);
+                die(regs, "Unknown program exception");
 }
 
 #define DO_ERROR_INFO(name, signr, sicode, str) \
-static void name(struct pt_regs *regs, long pgm_int_code, \
-                 unsigned long trans_exc_code) \
+static void name(struct pt_regs *regs) \
 { \
-        siginfo_t info; \
-        info.si_signo = signr; \
-        info.si_errno = 0; \
-        info.si_code = sicode; \
-        info.si_addr = get_psw_address(regs, pgm_int_code); \
-        do_trap(pgm_int_code, signr, str, regs, &info);     \
+        do_trap(regs, signr, sicode, str); \
 }
 
 DO_ERROR_INFO(addressing_exception, SIGILL, ILL_ILLADR,
@@ -388,42 +382,34 @@ DO_ERROR_INFO(special_op_exception, SIGILL, ILL_ILLOPN,
 DO_ERROR_INFO(translation_exception, SIGILL, ILL_ILLOPN,
               "translation exception")
 
-static inline void do_fp_trap(struct pt_regs *regs, void __user *location,
-                              int fpc, long pgm_int_code)
+static inline void do_fp_trap(struct pt_regs *regs, int fpc)
 {
-        siginfo_t si;
-
-        si.si_signo = SIGFPE;
-        si.si_errno = 0;
-        si.si_addr = location;
-        si.si_code = 0;
+        int si_code = 0;
         /* FPC[2] is Data Exception Code */
         if ((fpc & 0x00000300) == 0) {
                 /* bits 6 and 7 of DXC are 0 iff IEEE exception */
                 if (fpc & 0x8000) /* invalid fp operation */
-                        si.si_code = FPE_FLTINV;
+                        si_code = FPE_FLTINV;
                 else if (fpc & 0x4000) /* div by 0 */
-                        si.si_code = FPE_FLTDIV;
+                        si_code = FPE_FLTDIV;
                 else if (fpc & 0x2000) /* overflow */
-                        si.si_code = FPE_FLTOVF;
+                        si_code = FPE_FLTOVF;
                 else if (fpc & 0x1000) /* underflow */
-                        si.si_code = FPE_FLTUND;
+                        si_code = FPE_FLTUND;
                 else if (fpc & 0x0800) /* inexact */
-                        si.si_code = FPE_FLTRES;
+                        si_code = FPE_FLTRES;
         }
-        do_trap(pgm_int_code, SIGFPE,
-                "floating point exception", regs, &si);
+        do_trap(regs, SIGFPE, si_code, "floating point exception");
 }
 
-static void __kprobes illegal_op(struct pt_regs *regs, long pgm_int_code,
-                                 unsigned long trans_exc_code)
+static void __kprobes illegal_op(struct pt_regs *regs)
 {
         siginfo_t info;
         __u8 opcode[6];
         __u16 __user *location;
         int signal = 0;
 
-        location = get_psw_address(regs, pgm_int_code);
+        location = get_psw_address(regs);
 
         if (regs->psw.mask & PSW_MASK_PSTATE) {
                 if (get_user(*((__u16 *) opcode), (__u16 __user *) location))
@@ -467,44 +453,31 @@ static void __kprobes illegal_op(struct pt_regs *regs, long pgm_int_code,
                  * If we get an illegal op in kernel mode, send it through the
                  * kprobes notifier. If kprobes doesn't pick it up, SIGILL
                  */
-                if (notify_die(DIE_BPT, "bpt", regs, pgm_int_code,
+                if (notify_die(DIE_BPT, "bpt", regs, 0,
                                3, SIGTRAP) != NOTIFY_STOP)
                         signal = SIGILL;
         }
 
 #ifdef CONFIG_MATHEMU
         if (signal == SIGFPE)
-                do_fp_trap(regs, location,
-                           current->thread.fp_regs.fpc, pgm_int_code);
-        else if (signal == SIGSEGV) {
-                info.si_signo = signal;
-                info.si_errno = 0;
-                info.si_code = SEGV_MAPERR;
-                info.si_addr = (void __user *) location;
-                do_trap(pgm_int_code, signal,
-                        "user address fault", regs, &info);
-        } else
+                do_fp_trap(regs, current->thread.fp_regs.fpc);
+        else if (signal == SIGSEGV)
+                do_trap(regs, signal, SEGV_MAPERR, "user address fault");
+        else
 #endif
-        if (signal) {
-                info.si_signo = signal;
-                info.si_errno = 0;
-                info.si_code = ILL_ILLOPC;
-                info.si_addr = (void __user *) location;
-                do_trap(pgm_int_code, signal,
-                        "illegal operation", regs, &info);
-        }
+        if (signal)
+                do_trap(regs, signal, ILL_ILLOPC, "illegal operation");
 }
 
 
 #ifdef CONFIG_MATHEMU
-void specification_exception(struct pt_regs *regs, long pgm_int_code,
-                             unsigned long trans_exc_code)
+void specification_exception(struct pt_regs *regs)
 {
         __u8 opcode[6];
         __u16 __user *location = NULL;
         int signal = 0;
 
-        location = (__u16 __user *) get_psw_address(regs, pgm_int_code);
+        location = (__u16 __user *) get_psw_address(regs);
 
         if (regs->psw.mask & PSW_MASK_PSTATE) {
                 get_user(*((__u16 *) opcode), location);
@@ -539,30 +512,21 @@ void specification_exception(struct pt_regs *regs, long pgm_int_code,
                 signal = SIGILL;
 
         if (signal == SIGFPE)
-                do_fp_trap(regs, location,
-                           current->thread.fp_regs.fpc, pgm_int_code);
-        else if (signal) {
-                siginfo_t info;
-                info.si_signo = signal;
-                info.si_errno = 0;
-                info.si_code = ILL_ILLOPN;
-                info.si_addr = location;
-                do_trap(pgm_int_code, signal,
-                        "specification exception", regs, &info);
-        }
+                do_fp_trap(regs, current->thread.fp_regs.fpc);
+        else if (signal)
+                do_trap(regs, signal, ILL_ILLOPN, "specification exception");
 }
 #else
 DO_ERROR_INFO(specification_exception, SIGILL, ILL_ILLOPN,
               "specification exception");
 #endif
 
-static void data_exception(struct pt_regs *regs, long pgm_int_code,
-                           unsigned long trans_exc_code)
+static void data_exception(struct pt_regs *regs)
 {
         __u16 __user *location;
         int signal = 0;
 
-        location = get_psw_address(regs, pgm_int_code);
+        location = get_psw_address(regs);
 
         if (MACHINE_HAS_IEEE)
                 asm volatile("stfpc %0" : "=m" (current->thread.fp_regs.fpc));
@@ -627,32 +591,18 @@ static void data_exception(struct pt_regs *regs, long pgm_int_code,
         else
                 signal = SIGILL;
         if (signal == SIGFPE)
-                do_fp_trap(regs, location,
-                           current->thread.fp_regs.fpc, pgm_int_code);
-        else if (signal) {
-                siginfo_t info;
-                info.si_signo = signal;
-                info.si_errno = 0;
-                info.si_code = ILL_ILLOPN;
-                info.si_addr = location;
-                do_trap(pgm_int_code, signal, "data exception", regs, &info);
-        }
+                do_fp_trap(regs, current->thread.fp_regs.fpc);
+        else if (signal)
+                do_trap(regs, signal, ILL_ILLOPN, "data exception");
 }
 
-static void space_switch_exception(struct pt_regs *regs, long pgm_int_code,
-                                   unsigned long trans_exc_code)
+static void space_switch_exception(struct pt_regs *regs)
 {
-        siginfo_t info;
-
         /* Set user psw back to home space mode. */
         if (regs->psw.mask & PSW_MASK_PSTATE)
                 regs->psw.mask |= PSW_ASC_HOME;
         /* Send SIGILL. */
-        info.si_signo = SIGILL;
-        info.si_errno = 0;
-        info.si_code = ILL_PRVOPC;
-        info.si_addr = get_psw_address(regs, pgm_int_code);
-        do_trap(pgm_int_code, SIGILL, "space switch event", regs, &info);
+        do_trap(regs, SIGILL, ILL_PRVOPC, "space switch event");
 }
 
 void __kprobes kernel_stack_overflow(struct pt_regs * regs)
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index a9a301866b3..354dd39073e 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -125,8 +125,7 @@ static inline int user_space_fault(unsigned long trans_exc_code)
         return trans_exc_code != 3;
 }
 
-static inline void report_user_fault(struct pt_regs *regs, long int_code,
-                                     int signr, unsigned long address)
+static inline void report_user_fault(struct pt_regs *regs, long signr)
 {
         if ((task_pid_nr(current) > 1) && !show_unhandled_signals)
                 return;
@@ -134,10 +133,12 @@ static inline void report_user_fault(struct pt_regs *regs, long int_code,
                 return;
         if (!printk_ratelimit())
                 return;
-        printk("User process fault: interruption code 0x%lX ", int_code);
+        printk(KERN_ALERT "User process fault: interruption code 0x%X ",
+               regs->int_code);
         print_vma_addr(KERN_CONT "in ", regs->psw.addr & PSW_ADDR_INSN);
-        printk("\n");
-        printk("failing address: %lX\n", address);
+        printk(KERN_CONT "\n");
+        printk(KERN_ALERT "failing address: %lX\n",
+               regs->int_parm_long & __FAIL_ADDR_MASK);
         show_regs(regs);
 }
 
@@ -145,24 +146,18 @@ static inline void report_user_fault(struct pt_regs *regs, long int_code,
  * Send SIGSEGV to task.  This is an external routine
  * to keep the stack usage of do_page_fault small.
  */
-static noinline void do_sigsegv(struct pt_regs *regs, long int_code,
-                                int si_code, unsigned long trans_exc_code)
+static noinline void do_sigsegv(struct pt_regs *regs, int si_code)
 {
         struct siginfo si;
-        unsigned long address;
 
-        address = trans_exc_code & __FAIL_ADDR_MASK;
-        current->thread.prot_addr = address;
-        current->thread.trap_no = int_code;
-        report_user_fault(regs, int_code, SIGSEGV, address);
+        report_user_fault(regs, SIGSEGV);
         si.si_signo = SIGSEGV;
         si.si_code = si_code;
-        si.si_addr = (void __user *) address;
+        si.si_addr = (void __user *)(regs->int_parm_long & __FAIL_ADDR_MASK);
         force_sig_info(SIGSEGV, &si, current);
 }
 
-static noinline void do_no_context(struct pt_regs *regs, long int_code,
-                                   unsigned long trans_exc_code)
+static noinline void do_no_context(struct pt_regs *regs)
 {
         const struct exception_table_entry *fixup;
         unsigned long address;
@@ -178,55 +173,48 @@ static noinline void do_no_context(struct pt_regs *regs, long int_code,
          * Oops. The kernel tried to access some bad page. We'll have to
          * terminate things with extreme prejudice.
          */
-        address = trans_exc_code & __FAIL_ADDR_MASK;
-        if (!user_space_fault(trans_exc_code))
+        address = regs->int_parm_long & __FAIL_ADDR_MASK;
+        if (!user_space_fault(regs->int_parm_long))
                 printk(KERN_ALERT "Unable to handle kernel pointer dereference"
                        " at virtual kernel address %p\n", (void *)address);
         else
                 printk(KERN_ALERT "Unable to handle kernel paging request"
                        " at virtual user address %p\n", (void *)address);
 
-        die("Oops", regs, int_code);
+        die(regs, "Oops");
         do_exit(SIGKILL);
 }
 
-static noinline void do_low_address(struct pt_regs *regs, long int_code,
-                                    unsigned long trans_exc_code)
+static noinline void do_low_address(struct pt_regs *regs)
 {
         /* Low-address protection hit in kernel mode means
            NULL pointer write access in kernel mode.  */
         if (regs->psw.mask & PSW_MASK_PSTATE) {
                 /* Low-address protection hit in user mode 'cannot happen'. */
-                die ("Low-address protection", regs, int_code);
+                die (regs, "Low-address protection");
                 do_exit(SIGKILL);
         }
 
-        do_no_context(regs, int_code, trans_exc_code);
+        do_no_context(regs);
 }
 
-static noinline void do_sigbus(struct pt_regs *regs, long int_code,
-                               unsigned long trans_exc_code)
+static noinline void do_sigbus(struct pt_regs *regs)
 {
         struct task_struct *tsk = current;
-        unsigned long address;
         struct siginfo si;
 
         /*
          * Send a sigbus, regardless of whether we were in kernel
          * or user mode.
          */
-        address = trans_exc_code & __FAIL_ADDR_MASK;
-        tsk->thread.prot_addr = address;
-        tsk->thread.trap_no = int_code;
         si.si_signo = SIGBUS;
         si.si_errno = 0;
         si.si_code = BUS_ADRERR;
-        si.si_addr = (void __user *) address;
+        si.si_addr = (void __user *)(regs->int_parm_long & __FAIL_ADDR_MASK);
         force_sig_info(SIGBUS, &si, tsk);
 }
 
-static noinline void do_fault_error(struct pt_regs *regs, long int_code,
-                                    unsigned long trans_exc_code, int fault)
+static noinline void do_fault_error(struct pt_regs *regs, int fault)
 {
         int si_code;
 
@@ -238,24 +226,24 @@ static noinline void do_fault_error(struct pt_regs *regs, long int_code,
                         /* User mode accesses just cause a SIGSEGV */
                         si_code = (fault == VM_FAULT_BADMAP) ?
                                 SEGV_MAPERR : SEGV_ACCERR;
-                        do_sigsegv(regs, int_code, si_code, trans_exc_code);
+                        do_sigsegv(regs, si_code);
                         return;
                 }
         case VM_FAULT_BADCONTEXT:
-                do_no_context(regs, int_code, trans_exc_code);
+                do_no_context(regs);
                 break;
         default: /* fault & VM_FAULT_ERROR */
                 if (fault & VM_FAULT_OOM) {
                         if (!(regs->psw.mask & PSW_MASK_PSTATE))
-                                do_no_context(regs, int_code, trans_exc_code);
+                                do_no_context(regs);
                         else
                                 pagefault_out_of_memory();
                 } else if (fault & VM_FAULT_SIGBUS) {
                         /* Kernel mode? Handle exceptions or die */
                         if (!(regs->psw.mask & PSW_MASK_PSTATE))
-                                do_no_context(regs, int_code, trans_exc_code);
+                                do_no_context(regs);
                         else
-                                do_sigbus(regs, int_code, trans_exc_code);
+                                do_sigbus(regs);
                 } else
                         BUG();
                 break;
@@ -273,12 +261,12 @@ static noinline void do_fault_error(struct pt_regs *regs, long int_code,
  *   11       Page translation     ->  Not present       (nullification)
  *   3b       Region third trans.  ->  Not present       (nullification)
  */
-static inline int do_exception(struct pt_regs *regs, int access,
-                               unsigned long trans_exc_code)
+static inline int do_exception(struct pt_regs *regs, int access)
 {
         struct task_struct *tsk;
         struct mm_struct *mm;
         struct vm_area_struct *vma;
+        unsigned long trans_exc_code;
         unsigned long address;
         unsigned int flags;
         int fault;
@@ -288,6 +276,7 @@ static inline int do_exception(struct pt_regs *regs, int access,
 
         tsk = current;
         mm = tsk->mm;
+        trans_exc_code = regs->int_parm_long;
 
         /*
          * Verify that the fault happened in user space, that
@@ -387,45 +376,46 @@ out:
         return fault;
 }
 
-void __kprobes do_protection_exception(struct pt_regs *regs, long pgm_int_code,
-                                       unsigned long trans_exc_code)
+void __kprobes do_protection_exception(struct pt_regs *regs)
 {
+        unsigned long trans_exc_code;
         int fault;
 
+        trans_exc_code = regs->int_parm_long;
         /* Protection exception is suppressing, decrement psw address. */
-        regs->psw.addr = __rewind_psw(regs->psw, pgm_int_code >> 16);
+        regs->psw.addr = __rewind_psw(regs->psw, regs->int_code >> 16);
         /*
          * Check for low-address protection.  This needs to be treated
          * as a special case because the translation exception code
          * field is not guaranteed to contain valid data in this case.
          */
         if (unlikely(!(trans_exc_code & 4))) {
-                do_low_address(regs, pgm_int_code, trans_exc_code);
+                do_low_address(regs);
                 return;
         }
-        fault = do_exception(regs, VM_WRITE, trans_exc_code);
+        fault = do_exception(regs, VM_WRITE);
         if (unlikely(fault))
-                do_fault_error(regs, 4, trans_exc_code, fault);
+                do_fault_error(regs, fault);
 }
 
-void __kprobes do_dat_exception(struct pt_regs *regs, long pgm_int_code,
-                                unsigned long trans_exc_code)
+void __kprobes do_dat_exception(struct pt_regs *regs)
 {
         int access, fault;
 
         access = VM_READ | VM_EXEC | VM_WRITE;
-        fault = do_exception(regs, access, trans_exc_code);
+        fault = do_exception(regs, access);
         if (unlikely(fault))
-                do_fault_error(regs, pgm_int_code & 255, trans_exc_code, fault);
+                do_fault_error(regs, fault);
 }
 
 #ifdef CONFIG_64BIT
-void __kprobes do_asce_exception(struct pt_regs *regs, long pgm_int_code,
-                                 unsigned long trans_exc_code)
+void __kprobes do_asce_exception(struct pt_regs *regs)
 {
         struct mm_struct *mm = current->mm;
         struct vm_area_struct *vma;
+        unsigned long trans_exc_code;
 
+        trans_exc_code = regs->int_parm_long;
         if (unlikely(!user_space_fault(trans_exc_code) || in_atomic() || !mm))
                 goto no_context;
 
@@ -440,12 +430,12 @@ void __kprobes do_asce_exception(struct pt_regs *regs, long pgm_int_code,
 
         /* User mode accesses just cause a SIGSEGV */
         if (regs->psw.mask & PSW_MASK_PSTATE) {
-                do_sigsegv(regs, pgm_int_code, SEGV_MAPERR, trans_exc_code);
+                do_sigsegv(regs, SEGV_MAPERR);
                 return;
         }
 
 no_context:
-        do_no_context(regs, pgm_int_code, trans_exc_code);
+        do_no_context(regs);
 }
 #endif
 
@@ -459,14 +449,15 @@ int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
                 regs.psw.mask |= PSW_MASK_IO | PSW_MASK_EXT;
         regs.psw.addr = (unsigned long) __builtin_return_address(0);
         regs.psw.addr |= PSW_ADDR_AMODE;
-        uaddr &= PAGE_MASK;
+        regs.int_code = pgm_int_code;
+        regs.int_parm_long = (uaddr & PAGE_MASK) | 2;
         access = write ? VM_WRITE : VM_READ;
-        fault = do_exception(&regs, access, uaddr | 2);
+        fault = do_exception(&regs, access);
         if (unlikely(fault)) {
                 if (fault & VM_FAULT_OOM)
                         return -EFAULT;
                 else if (fault & VM_FAULT_SIGBUS)
-                        do_sigbus(&regs, pgm_int_code, uaddr);
+                        do_sigbus(&regs);
         }
         return fault ? -EFAULT : 0;
 }
@@ -509,7 +500,7 @@ int pfault_init(void)
                 .reserved = __PF_RES_FIELD };
         int rc;
 
-        if (!MACHINE_IS_VM || pfault_disable)
+        if (pfault_disable)
                 return -1;
         asm volatile(
                 "       diag    %1,%0,0x258\n"
@@ -530,7 +521,7 @@ void pfault_fini(void)
                 .refversn = 2,
         };
 
-        if (!MACHINE_IS_VM || pfault_disable)
+        if (pfault_disable)
                 return;
         asm volatile(
                 "       diag    %0,0,0x258\n"
@@ -643,8 +634,6 @@ static int __init pfault_irq_init(void)
 {
         int rc;
 
-        if (!MACHINE_IS_VM)
-                return 0;
         rc = register_external_interrupt(0x2603, pfault_interrupt);
         if (rc)
                 goto out_extint;
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index d4b9fb4d004..5d633019d8f 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -93,18 +93,22 @@ static unsigned long setup_zero_pages(void)
 void __init paging_init(void)
 {
         unsigned long max_zone_pfns[MAX_NR_ZONES];
-        unsigned long pgd_type;
+        unsigned long pgd_type, asce_bits;
 
         init_mm.pgd = swapper_pg_dir;
-        S390_lowcore.kernel_asce = __pa(init_mm.pgd) & PAGE_MASK;
 #ifdef CONFIG_64BIT
-        /* A three level page table (4TB) is enough for the kernel space. */
-        S390_lowcore.kernel_asce |= _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH;
-        pgd_type = _REGION3_ENTRY_EMPTY;
+        if (VMALLOC_END > (1UL << 42)) {
+                asce_bits = _ASCE_TYPE_REGION2 | _ASCE_TABLE_LENGTH;
+                pgd_type = _REGION2_ENTRY_EMPTY;
+        } else {
+                asce_bits = _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH;
+                pgd_type = _REGION3_ENTRY_EMPTY;
+        }
 #else
-        S390_lowcore.kernel_asce |= _ASCE_TABLE_LENGTH;
+        asce_bits = _ASCE_TABLE_LENGTH;
         pgd_type = _SEGMENT_ENTRY_EMPTY;
 #endif
+        S390_lowcore.kernel_asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
         clear_table((unsigned long *) init_mm.pgd, pgd_type,
                     sizeof(unsigned long)*2048);
         vmem_map_init();
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 301c84d3b54..9a4d02f64f1 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -33,17 +33,6 @@
 #define FRAG_MASK       0x03
 #endif
 
-unsigned long VMALLOC_START = VMALLOC_END - VMALLOC_SIZE;
-EXPORT_SYMBOL(VMALLOC_START);
-
-static int __init parse_vmalloc(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-        VMALLOC_START = (VMALLOC_END - memparse(arg, &arg)) & PAGE_MASK;
-        return 0;
-}
-early_param("vmalloc", parse_vmalloc);
 
 unsigned long *crst_table_alloc(struct mm_struct *mm)
 {
@@ -267,7 +256,10 @@ static int gmap_alloc_table(struct gmap *gmap,
         struct page *page;
         unsigned long *new;
 
+        /* since we dont free the gmap table until gmap_free we can unlock */
+        spin_unlock(&gmap->mm->page_table_lock);
         page = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
+        spin_lock(&gmap->mm->page_table_lock);
         if (!page)
                 return -ENOMEM;
         new = (unsigned long *) page_to_phys(page);
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 8b0c9464aa9..3df65d39abc 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -4,6 +4,7 @@ config SCORE
        def_bool y
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
+       select GENERIC_IOMAP
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
        select ARCH_DISCARD_MEMBLOCK
@@ -36,9 +37,6 @@ endmenu
 config CPU_SCORE7
         bool
 
-config GENERIC_IOMAP
-        def_bool y
-
 config NO_DMA
         bool
         default y
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 47a2f1c2cb0..3c8db65c89e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -85,9 +85,6 @@ config GENERIC_GPIO
 config GENERIC_CALIBRATE_DELAY
         bool
 
-config GENERIC_IOMAP
-        bool
-
 config GENERIC_CLOCKEVENTS
         def_bool y
 
@@ -861,6 +858,7 @@ config PCI
         bool "PCI support"
         depends on SYS_SUPPORTS_PCI
         select PCI_DOMAINS
+        select GENERIC_PCI_IOMAP
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index c2691afe8f7..11aaf2fdec8 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -393,29 +393,6 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
         return (void __iomem *)(chan->io_map_base + port);
 }
 
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (unlikely(!len || !start))
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-
-        if (flags & IORESOURCE_IO)
-                return ioport_map_pci(dev, start, len);
-        if (flags & IORESOURCE_MEM) {
-                if (flags & IORESOURCE_CACHEABLE)
-                        return ioremap(start, len);
-                return ioremap_nocache(start, len);
-        }
-
-        return NULL;
-}
-EXPORT_SYMBOL(pci_iomap);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
         iounmap(addr);
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 1f51225426a..ae08cbbfa56 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -15,35 +15,78 @@
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 
+/*
+ * The maximum number of pages we support up to when doing ranged dcache
+ * flushing. Anything exceeding this will simply flush the dcache in its
+ * entirety.
+ */
+#define MAX_OCACHE_PAGES        32
+#define MAX_ICACHE_PAGES        32
+
+static void sh2a_flush_oc_line(unsigned long v, int way)
+{
+        unsigned long addr = (v & 0x000007f0) | (way << 11);
+        unsigned long data;
+
+        data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
+        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                data &= ~SH_CACHE_UPDATED;
+                __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
+        }
+}
+
+static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
+{
+        /* Set associative bit to hit all ways */
+        unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
+        __raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
+}
+
+/*
+ * Write back the dirty D-caches, but not invalidate them.
+ */
 static void sh2a__flush_wback_region(void *start, int size)
 {
+#ifdef CONFIG_CACHE_WRITEBACK
         unsigned long v;
         unsigned long begin, end;
         unsigned long flags;
+        int nr_ways;
 
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
+        nr_ways = current_cpu_data.dcache.ways;
 
         local_irq_save(flags);
         jump_to_uncached();
 
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
+        /* If there are too many pages then flush the entire cache */
+        if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
+                begin = CACHE_OC_ADDRESS_ARRAY;
+                end = begin + (nr_ways * current_cpu_data.dcache.way_size);
+
+                for (v = begin; v < end; v += L1_CACHE_BYTES) {
+                        unsigned long data = __raw_readl(v);
+                        if (data & SH_CACHE_UPDATED)
+                                __raw_writel(data & ~SH_CACHE_UPDATED, v);
+                }
+        } else {
                 int way;
-                for (way = 0; way < 4; way++) {
-                        unsigned long data =  __raw_readl(addr | (way << 11));
-                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
-                                data &= ~SH_CACHE_UPDATED;
-                                __raw_writel(data, addr | (way << 11));
-                        }
+                for (way = 0; way < nr_ways; way++) {
+                        for (v = begin; v < end; v += L1_CACHE_BYTES)
+                                sh2a_flush_oc_line(v, way);
                 }
         }
 
         back_to_cached();
         local_irq_restore(flags);
+#endif
 }
 
+/*
+ * Write back the dirty D-caches and invalidate them.
+ */
 static void sh2a__flush_purge_region(void *start, int size)
 {
         unsigned long v;
@@ -58,13 +101,22 @@ static void sh2a__flush_purge_region(void *start, int size)
         jump_to_uncached();
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                __raw_writel((v & CACHE_PHYSADDR_MASK),
-                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
+#ifdef CONFIG_CACHE_WRITEBACK
+                int way;
+                int nr_ways = current_cpu_data.dcache.ways;
+                for (way = 0; way < nr_ways; way++)
+                        sh2a_flush_oc_line(v, way);
+#endif
+                sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
         }
+
         back_to_cached();
         local_irq_restore(flags);
 }
 
+/*
+ * Invalidate the D-caches, but no write back please
+ */
 static void sh2a__flush_invalidate_region(void *start, int size)
 {
         unsigned long v;
@@ -74,29 +126,25 @@ static void sh2a__flush_invalidate_region(void *start, int size)
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
+
         local_irq_save(flags);
         jump_to_uncached();
 
-#ifdef CONFIG_CACHE_WRITEBACK
-        __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
-        /* I-cache invalidate */
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                __raw_writel((v & CACHE_PHYSADDR_MASK),
-                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
-        }
-#else
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                __raw_writel((v & CACHE_PHYSADDR_MASK),
-                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
-                __raw_writel((v & CACHE_PHYSADDR_MASK),
-                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
+        /* If there are too many pages then just blow the cache */
+        if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
+                __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+        } else {
+                for (v = begin; v < end; v += L1_CACHE_BYTES)
+                        sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
         }
-#endif
+
         back_to_cached();
         local_irq_restore(flags);
 }
 
-/* WBack O-Cache and flush I-Cache */
+/*
+ * Write back the range of D-cache, and purge the I-cache.
+ */
 static void sh2a_flush_icache_range(void *args)
 {
         struct flusher_data *data = args;
@@ -107,23 +155,20 @@ static void sh2a_flush_icache_range(void *args)
         start = data->addr1 & ~(L1_CACHE_BYTES-1);
         end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
 
+#ifdef CONFIG_CACHE_WRITEBACK
+        sh2a__flush_wback_region((void *)start, end-start);
+#endif
+
         local_irq_save(flags);
         jump_to_uncached();
 
-        for (v = start; v < end; v+=L1_CACHE_BYTES) {
-                unsigned long addr = (v & 0x000007f0);
-                int way;
-                /* O-Cache writeback */
-                for (way = 0; way < 4; way++) {
-                        unsigned long data =  __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
-                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
-                                data &= ~SH_CACHE_UPDATED;
-                                __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
-                        }
-                }
-                /* I-Cache invalidate */
-                __raw_writel(addr,
-                          CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
+        /* I-Cache invalidate */
+        /* If there are too many pages then just blow the cache */
+        if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
+                __raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR);
+        } else {
+                for (v = start; v < end; v += L1_CACHE_BYTES)
+                        sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
         }
 
         back_to_cached();
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 70ae9d81870..96657992a72 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -28,9 +28,11 @@ config SPARC
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
         select USE_GENERIC_SMP_HELPERS if SMP
+        select GENERIC_PCI_IOMAP
 
 config SPARC32
         def_bool !64BIT
+        select GENERIC_ATOMIC64
 
 config SPARC64
         def_bool 64BIT
@@ -383,9 +385,7 @@ config SCHED_MC
           making when dealing with multi-core CPU chips at a cost of slightly
           increased overhead in some places. If unsure say N here.
 
-if SPARC64
 source "kernel/Kconfig.preempt"
-endif
 
 config CMDLINE_BOOL
         bool "Default bootloader kernel arguments"
diff --git a/arch/sparc/include/asm/atomic_32.h b/arch/sparc/include/asm/atomic_32.h
index 5c3c8b69884..9dd0a769fa1 100644
--- a/arch/sparc/include/asm/atomic_32.h
+++ b/arch/sparc/include/asm/atomic_32.h
@@ -13,7 +13,7 @@
 
 #include <linux/types.h>
 
-#ifdef __KERNEL__
+#include <asm-generic/atomic64.h>
 
 #include <asm/system.h>
 
@@ -52,112 +52,10 @@ extern void atomic_set(atomic_t *, int);
 #define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
 
-
-/* This is the old 24-bit implementation.  It's still used internally
- * by some sparc-specific code, notably the semaphore implementation.
- */
-typedef struct { volatile int counter; } atomic24_t;
-
-#ifndef CONFIG_SMP
-
-#define ATOMIC24_INIT(i)  { (i) }
-#define atomic24_read(v)          ((v)->counter)
-#define atomic24_set(v, i)        (((v)->counter) = i)
-
-#else
-/* We do the bulk of the actual work out of line in two common
- * routines in assembler, see arch/sparc/lib/atomic.S for the
- * "fun" details.
- *
- * For SMP the trick is you embed the spin lock byte within
- * the word, use the low byte so signedness is easily retained
- * via a quick arithmetic shift.  It looks like this:
- *
- *      ----------------------------------------
- *      | signed 24-bit counter value |  lock  |  atomic_t
- *      ----------------------------------------
- *       31                          8 7      0
- */
-
-#define ATOMIC24_INIT(i)        { ((i) << 8) }
-
-static inline int atomic24_read(const atomic24_t *v)
-{
-        int ret = v->counter;
-
-        while(ret & 0xff)
-                ret = v->counter;
-
-        return ret >> 8;
-}
-
-#define atomic24_set(v, i)      (((v)->counter) = ((i) << 8))
-#endif
-
-static inline int __atomic24_add(int i, atomic24_t *v)
-{
-        register volatile int *ptr asm("g1");
-        register int increment asm("g2");
-        register int tmp1 asm("g3");
-        register int tmp2 asm("g4");
-        register int tmp3 asm("g7");
-
-        ptr = &v->counter;
-        increment = i;
-
-        __asm__ __volatile__(
-        "mov    %%o7, %%g4\n\t"
-        "call   ___atomic24_add\n\t"
-        " add   %%o7, 8, %%o7\n"
-        : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
-        : "0" (increment), "r" (ptr)
-        : "memory", "cc");
-
-        return increment;
-}
-
-static inline int __atomic24_sub(int i, atomic24_t *v)
-{
-        register volatile int *ptr asm("g1");
-        register int increment asm("g2");
-        register int tmp1 asm("g3");
-        register int tmp2 asm("g4");
-        register int tmp3 asm("g7");
-
-        ptr = &v->counter;
-        increment = i;
-
-        __asm__ __volatile__(
-        "mov    %%o7, %%g4\n\t"
-        "call   ___atomic24_sub\n\t"
-        " add   %%o7, 8, %%o7\n"
-        : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
-        : "0" (increment), "r" (ptr)
-        : "memory", "cc");
-
-        return increment;
-}
-
-#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
-#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
-
-#define atomic24_dec_return(v) __atomic24_sub(1, (v))
-#define atomic24_inc_return(v) __atomic24_add(1, (v))
-
-#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
-#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
-
-#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
-#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
-
-#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
-
 /* Atomic operations are already serializing */
 #define smp_mb__before_atomic_dec()     barrier()
 #define smp_mb__after_atomic_dec()      barrier()
 #define smp_mb__before_atomic_inc()     barrier()
 #define smp_mb__after_atomic_inc()      barrier()
 
-#endif /* !(__KERNEL__) */
-
 #endif /* !(__ARCH_SPARC_ATOMIC__) */
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index c2ced21c9dc..2006e5d359d 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -7,6 +7,7 @@
 
 #include <asm/page.h>      /* IO address mapping routines need this */
 #include <asm/system.h>
+#include <asm-generic/pci_iomap.h>
 
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 
@@ -324,7 +325,6 @@ extern void ioport_unmap(void __iomem *);
 
 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 
 /*
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 9c8965415f0..9481e5a6fa9 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -8,6 +8,7 @@
 #include <asm/page.h>      /* IO address mapping routines need this */
 #include <asm/system.h>
 #include <asm/asi.h>
+#include <asm-generic/pci_iomap.h>
 
 /* PC crapola... */
 #define __SLOW_DOWN_IO  do { } while (0)
@@ -514,7 +515,6 @@ extern void ioport_unmap(void __iomem *);
 
 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 
 static inline int sbus_can_dma_64bit(void)
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index 156707b0f18..bb5c2ac4055 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -8,14 +8,10 @@
 #ifndef _SPARC_PAGE_H
 #define _SPARC_PAGE_H
 
-#define PAGE_SHIFT   12
+#include <linux/const.h>
 
-#ifndef __ASSEMBLY__
-/* I have my suspicions... -DaveM */
-#define PAGE_SIZE    (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE    (1 << PAGE_SHIFT)
-#endif
+#define PAGE_SHIFT   12
+#define PAGE_SIZE    (_AC(1, UL) << PAGE_SHIFT)
 #define PAGE_MASK    (~(PAGE_SIZE-1))
 
 #include <asm/btfixup.h>
diff --git a/arch/sparc/include/asm/pgtsun4.h b/arch/sparc/include/asm/pgtsun4.h
deleted file mode 100644
index 5a0d661fb82..00000000000
--- a/arch/sparc/include/asm/pgtsun4.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * pgtsun4.h:  Sun4 specific pgtable.h defines and code.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#ifndef _SPARC_PGTSUN4C_H
-#define _SPARC_PGTSUN4C_H
-
-#include <asm/contregs.h>
-
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define SUN4C_PMD_SHIFT       23
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SUN4C_PGDIR_SHIFT       23
-#define SUN4C_PGDIR_SIZE        (1UL << SUN4C_PGDIR_SHIFT)
-#define SUN4C_PGDIR_MASK        (~(SUN4C_PGDIR_SIZE-1))
-#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
-
-/* To represent how the sun4c mmu really lays things out. */
-#define SUN4C_REAL_PGDIR_SHIFT       18
-#define SUN4C_REAL_PGDIR_SIZE        (1UL << SUN4C_REAL_PGDIR_SHIFT)
-#define SUN4C_REAL_PGDIR_MASK        (~(SUN4C_REAL_PGDIR_SIZE-1))
-#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
-
-/* 19 bit PFN on sun4 */
-#define SUN4C_PFN_MASK 0x7ffff
- 
-/* Don't increase these unless the structures in sun4c.c are fixed */
-#define SUN4C_MAX_SEGMAPS 256
-#define SUN4C_MAX_CONTEXTS 16
-
-/*
- * To be efficient, and not have to worry about allocating such
- * a huge pgd, we make the kernel sun4c tables each hold 1024
- * entries and the pgd similarly just like the i386 tables.
- */
-#define SUN4C_PTRS_PER_PTE    1024
-#define SUN4C_PTRS_PER_PMD    1
-#define SUN4C_PTRS_PER_PGD    1024
-
-/*
- * Sparc SUN4C pte fields.
- */
-#define _SUN4C_PAGE_VALID        0x80000000
-#define _SUN4C_PAGE_SILENT_READ  0x80000000   /* synonym */
-#define _SUN4C_PAGE_DIRTY        0x40000000
-#define _SUN4C_PAGE_SILENT_WRITE 0x40000000   /* synonym */
-#define _SUN4C_PAGE_PRIV         0x20000000   /* privileged page */
-#define _SUN4C_PAGE_NOCACHE      0x10000000   /* non-cacheable page */
-#define _SUN4C_PAGE_PRESENT      0x08000000   /* implemented in software */
-#define _SUN4C_PAGE_IO           0x04000000   /* I/O page */
-#define _SUN4C_PAGE_FILE         0x02000000   /* implemented in software */
-#define _SUN4C_PAGE_READ         0x00800000   /* implemented in software */
-#define _SUN4C_PAGE_WRITE        0x00400000   /* implemented in software */
-#define _SUN4C_PAGE_ACCESSED     0x00200000   /* implemented in software */
-#define _SUN4C_PAGE_MODIFIED     0x00100000   /* implemented in software */
-
-#define _SUN4C_READABLE         (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
-                                 _SUN4C_PAGE_ACCESSED)
-#define _SUN4C_WRITEABLE        (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
-                                 _SUN4C_PAGE_MODIFIED)
-
-#define _SUN4C_PAGE_CHG_MASK    (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
-
-#define SUN4C_PAGE_NONE         __pgprot(_SUN4C_PAGE_PRESENT)
-#define SUN4C_PAGE_SHARED       __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
-                                         _SUN4C_PAGE_WRITE)
-#define SUN4C_PAGE_COPY         __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_READONLY     __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_KERNEL       __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
-                                         _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
-
-/* SUN4C swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset.  This gives us
- * 32 swapfiles of 4GB each.  Encoding looks like:
- *
- * RRRRRRRRooooooooooooooooooottttt
- * fedcba9876543210fedcba9876543210
- *
- * The top 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SUN4C_SWP_TYPE_MASK     0x1f
-#define SUN4C_SWP_OFF_MASK      0x7ffff
-#define SUN4C_SWP_OFF_SHIFT     5
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long sun4c_get_synchronous_error(void)
-{
-        unsigned long sync_err;
-
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (sync_err) :
-                             "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
-        return sync_err;
-}
-
-static inline unsigned long sun4c_get_synchronous_address(void)
-{
-        unsigned long sync_addr;
-
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (sync_addr) :
-                             "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
-        return sync_addr;
-}
-
-/* SUN4 pte, segmap, and context manipulation */
-static inline unsigned long sun4c_get_segmap(unsigned long addr)
-{
-  register unsigned long entry;
-
-  __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" : 
-                       "=r" (entry) :
-                       "r" (addr), "i" (ASI_SEGMAP));
-  return entry;
-}
-
-static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
-{
-  __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
-                       "r" (addr), "r" (entry),
-                       "i" (ASI_SEGMAP)
-                       : "memory");
-}
-
-static inline unsigned long sun4c_get_pte(unsigned long addr)
-{
-  register unsigned long entry;
-
-  __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 
-                       "=r" (entry) :
-                       "r" (addr), "i" (ASI_PTE));
-  return entry;
-}
-
-static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
-{
-  __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
-                       "r" (addr), 
-                       "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
-                       : "memory");
-}
-
-static inline int sun4c_get_context(void)
-{
-  register int ctx;
-
-  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
-                       "=r" (ctx) :
-                       "r" (AC_CONTEXT), "i" (ASI_CONTROL));
-
-  return ctx;
-}
-
-static inline int sun4c_set_context(int ctx)
-{
-  __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
-                       "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
-                       : "memory");
-
-  return ctx;
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_PGTSUN4_H) */
diff --git a/arch/sparc/include/asm/signal.h b/arch/sparc/include/asm/signal.h
index e49b828a247..aa42fe30d5b 100644
--- a/arch/sparc/include/asm/signal.h
+++ b/arch/sparc/include/asm/signal.h
@@ -143,10 +143,11 @@ struct sigstack {
 #define SA_ONSTACK      _SV_SSTACK
 #define SA_RESTART      _SV_INTR
 #define SA_ONESHOT      _SV_RESET
-#define SA_NOMASK       0x20u
+#define SA_NODEFER      0x20u
 #define SA_NOCLDWAIT    0x100u
 #define SA_SIGINFO      0x200u
 
+#define SA_NOMASK       SA_NODEFER
 
 #define SIG_BLOCK          0x01 /* for blocking signals */
 #define SIG_UNBLOCK        0x02 /* for unblocking signals */
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
index 5cc5888ad5a..c2a1080cdd3 100644
--- a/arch/sparc/include/asm/thread_info_32.h
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -95,7 +95,7 @@ BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
  * Observe the order of get_free_pages() in alloc_thread_info_node().
  * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
  */
-#define THREAD_SIZE             8192
+#define THREAD_SIZE             (2 * PAGE_SIZE)
 
 /*
  * Offsets in thread_info structure, used in assembly code
diff --git a/arch/sparc/lib/atomic_32.S b/arch/sparc/lib/atomic_32.S
index 178cbb8ae1b..eb6c7359cbd 100644
--- a/arch/sparc/lib/atomic_32.S
+++ b/arch/sparc/lib/atomic_32.S
@@ -40,60 +40,5 @@ ___xchg32_sun4md:
          mov    %g4, %o7
 #endif
 
-        /* Read asm-sparc/atomic.h carefully to understand how this works for SMP.
-         * Really, some things here for SMP are overly clever, go read the header.
-         */
-        .globl  ___atomic24_add
-___atomic24_add:
-        rd      %psr, %g3               ! Keep the code small, old way was stupid
-        nop; nop; nop;                  ! Let the bits set
-        or      %g3, PSR_PIL, %g7       ! Disable interrupts
-        wr      %g7, 0x0, %psr          ! Set %psr
-        nop; nop; nop;                  ! Let the bits set
-#ifdef CONFIG_SMP
-1:      ldstub  [%g1 + 3], %g7          ! Spin on the byte lock for SMP.
-        orcc    %g7, 0x0, %g0           ! Did we get it?
-        bne     1b                      ! Nope...
-         ld     [%g1], %g7              ! Load locked atomic24_t
-        sra     %g7, 8, %g7             ! Get signed 24-bit integer
-        add     %g7, %g2, %g2           ! Add in argument
-        sll     %g2, 8, %g7             ! Transpose back to atomic24_t
-        st      %g7, [%g1]              ! Clever: This releases the lock as well.
-#else
-        ld      [%g1], %g7              ! Load locked atomic24_t
-        add     %g7, %g2, %g2           ! Add in argument
-        st      %g2, [%g1]              ! Store it back
-#endif
-        wr      %g3, 0x0, %psr          ! Restore original PSR_PIL
-        nop; nop; nop;                  ! Let the bits set
-        jmpl    %o7, %g0                ! NOTE: not + 8, see callers in atomic.h
-         mov    %g4, %o7                ! Restore %o7
-
-        .globl  ___atomic24_sub
-___atomic24_sub:
-        rd      %psr, %g3               ! Keep the code small, old way was stupid
-        nop; nop; nop;                  ! Let the bits set
-        or      %g3, PSR_PIL, %g7       ! Disable interrupts
-        wr      %g7, 0x0, %psr          ! Set %psr
-        nop; nop; nop;                  ! Let the bits set
-#ifdef CONFIG_SMP
-1:      ldstub  [%g1 + 3], %g7          ! Spin on the byte lock for SMP.
-        orcc    %g7, 0x0, %g0           ! Did we get it?
-        bne     1b                      ! Nope...
-         ld     [%g1], %g7              ! Load locked atomic24_t
-        sra     %g7, 8, %g7             ! Get signed 24-bit integer
-        sub     %g7, %g2, %g2           ! Subtract argument
-        sll     %g2, 8, %g7             ! Transpose back to atomic24_t
-        st      %g7, [%g1]              ! Clever: This releases the lock as well
-#else
-        ld      [%g1], %g7              ! Load locked atomic24_t
-        sub     %g7, %g2, %g2           ! Subtract argument
-        st      %g2, [%g1]              ! Store it back
-#endif
-        wr      %g3, 0x0, %psr          ! Restore original PSR_PIL
-        nop; nop; nop;                  ! Let the bits set
-        jmpl    %o7, %g0                ! NOTE: not + 8, see callers in atomic.h
-         mov    %g4, %o7                ! Restore %o7
-
         .globl  __atomic_end
 __atomic_end:
diff --git a/arch/sparc/lib/iomap.c b/arch/sparc/lib/iomap.c
index 9ef37e13a92..c4d42a50ebc 100644
--- a/arch/sparc/lib/iomap.c
+++ b/arch/sparc/lib/iomap.c
@@ -18,31 +18,8 @@ void ioport_unmap(void __iomem *addr)
 EXPORT_SYMBOL(ioport_map);
 EXPORT_SYMBOL(ioport_unmap);
 
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len || !start)
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM) {
-                if (flags & IORESOURCE_CACHEABLE)
-                        return ioremap(start, len);
-                return ioremap_nocache(start, len);
-        }
-        /* What? */
-        return NULL;
-}
-
 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
 {
         /* nothing to do */
 }
-EXPORT_SYMBOL(pci_iomap);
 EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c
index 1b30bb3bfdb..f73c2240fe6 100644
--- a/arch/sparc/lib/ksyms.c
+++ b/arch/sparc/lib/ksyms.c
@@ -62,8 +62,6 @@ extern void ___rw_read_enter(void);
 extern void ___rw_read_try(void);
 extern void ___rw_read_exit(void);
 extern void ___rw_write_enter(void);
-extern void ___atomic24_add(void);
-extern void ___atomic24_sub(void);
 
 /* Alias functions whose names begin with "." and export the aliases.
  * The module references will be fixed up by module_frob_arch_sections.
@@ -97,10 +95,6 @@ EXPORT_SYMBOL(___rw_read_exit);
 EXPORT_SYMBOL(___rw_write_enter);
 #endif
 
-/* Atomic operations. */
-EXPORT_SYMBOL(___atomic24_add);
-EXPORT_SYMBOL(___atomic24_sub);
-
 EXPORT_SYMBOL(__ashrdi3);
 EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__lshrdi3);
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 70a0de46cd1..11270ca22c0 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -321,6 +321,7 @@ config PCI
         bool "PCI support"
         default y
         select PCI_DOMAINS
+        select GENERIC_PCI_IOMAP
         ---help---
           Enable PCI root complex support, so PCIe endpoint devices can
           be attached to the Tile chip.  Many, but not all, PCI devices
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index c9ea1652af0..d2152deb1f3 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -204,7 +204,8 @@ static inline long ioport_panic(void)
 
 static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
 {
-        return (void __iomem *) ioport_panic();
+        pr_info("ioport_map: mapping IO resources is unsupported on tile.\n");
+        return NULL;
 }
 
 static inline void ioport_unmap(void __iomem *addr)
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 7f03cefed1b..1d25fea42e5 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -16,6 +16,7 @@
 #define _ASM_TILE_PCI_H
 
 #include <linux/pci.h>
+#include <asm-generic/pci_iomap.h>
 
 /*
  * Structure of a PCI controller (host bridge)
@@ -49,7 +50,6 @@ struct pci_controller {
 int __devinit tile_pci_init(void);
 int __devinit pcibios_init(void);
 
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
 
 void __devinit pcibios_fixup_bus(struct pci_bus *bus);
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index 9d610d3fb11..25567934a21 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -466,27 +466,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return 0;
 }
 
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
-{
-        unsigned long start = pci_resource_start(dev, bar);
-        unsigned long len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-
-        if (!len)
-                return NULL;
-        if (max && len > max)
-                len = max;
-
-        if (!(flags & IORESOURCE_MEM)) {
-                pr_info("PCI: Trying to map invalid resource %#lx\n", flags);
-                start = 0;
-        }
-
-        return (void __iomem *)start;
-}
-EXPORT_SYMBOL(pci_iomap);
-
-
 /****************************************************************
  *
  * Tile PCI config space read/write routines
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index 942ed6174f1..eeb8054c7cd 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -12,6 +12,7 @@ config UNICORE32
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
         select ARCH_WANT_FRAME_POINTERS
+        select GENERIC_IOMAP
         help
           UniCore-32 is 32-bit Instruction Set Architecture,
           including a series of low-power-consumption RISC chip
@@ -30,9 +31,6 @@ config GENERIC_CLOCKEVENTS
 config GENERIC_CSUM
         def_bool y
 
-config GENERIC_IOMAP
-        def_bool y
-
 config NO_IOPORT
         bool
 
diff --git a/arch/unicore32/include/asm/io.h b/arch/unicore32/include/asm/io.h
index 1a5c5a5eb39..adddf6d6407 100644
--- a/arch/unicore32/include/asm/io.h
+++ b/arch/unicore32/include/asm/io.h
@@ -37,15 +37,9 @@ extern void __uc32_iounmap(volatile void __iomem *addr);
  */
 #define ioremap(cookie, size)           __uc32_ioremap(cookie, size)
 #define ioremap_cached(cookie, size)    __uc32_ioremap_cached(cookie, size)
+#define ioremap_nocache(cookie, size)   __uc32_ioremap(cookie, size)
 #define iounmap(cookie)                 __uc32_iounmap(cookie)
 
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#undef xlate_dev_mem_ptr
-#define xlate_dev_mem_ptr(p)    __va(p)
-
 #define HAVE_ARCH_PIO_SIZE
 #define PIO_OFFSET              (unsigned int)(PCI_IOBASE)
 #define PIO_MASK                (unsigned int)(IO_SPACE_LIMIT)
diff --git a/arch/unicore32/kernel/puv3-nb0916.c b/arch/unicore32/kernel/puv3-nb0916.c
index 37b12a06b49..181108b8ecc 100644
--- a/arch/unicore32/kernel/puv3-nb0916.c
+++ b/arch/unicore32/kernel/puv3-nb0916.c
@@ -123,7 +123,7 @@ int __init mach_nb0916_init(void)
 
         if (request_irq(gpio_to_irq(GPI_LCD_CASE_OFF),
                 &nb0916_lcdcaseoff_handler,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                 "NB0916 lcd case off", NULL) < 0) {
 
                 printk(KERN_DEBUG "LCD-Case-OFF IRQ %d not available\n",
@@ -131,7 +131,7 @@ int __init mach_nb0916_init(void)
         }
 
         if (request_irq(gpio_to_irq(GPI_OTP_INT), &nb0916_overheat_handler,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                 "NB0916 overheating protection", NULL) < 0) {
 
                 printk(KERN_DEBUG "Overheating Protection IRQ %d not available\n",
diff --git a/arch/unicore32/kernel/setup.c b/arch/unicore32/kernel/setup.c
index 673d7a89d8f..87adbf5ebfe 100644
--- a/arch/unicore32/kernel/setup.c
+++ b/arch/unicore32/kernel/setup.c
@@ -65,7 +65,7 @@ static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  */
 static struct resource mem_res[] = {
         {
-                .name = "Kernel text",
+                .name = "Kernel code",
                 .start = 0,
                 .end = 0,
                 .flags = IORESOURCE_MEM
diff --git a/arch/unicore32/kernel/signal.c b/arch/unicore32/kernel/signal.c
index b163fca5678..911b549a6df 100644
--- a/arch/unicore32/kernel/signal.c
+++ b/arch/unicore32/kernel/signal.c
@@ -63,10 +63,7 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
         err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
         if (err == 0) {
                 sigdelsetmask(&set, ~_BLOCKABLE);
-                spin_lock_irq(&current->sighand->siglock);
-                current->blocked = set;
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
+                set_current_blocked(&set);
         }
 
         err |= __get_user(regs->UCreg_00, &sf->uc.uc_mcontext.regs.UCreg_00);
@@ -321,6 +318,7 @@ static int handle_signal(unsigned long sig, struct k_sigaction *ka,
 {
         struct thread_info *thread = current_thread_info();
         struct task_struct *tsk = current;
+        sigset_t blocked;
         int usig = sig;
         int ret;
 
@@ -372,13 +370,10 @@ static int handle_signal(unsigned long sig, struct k_sigaction *ka,
         /*
          * Block the signal if we were successful.
          */
-        spin_lock_irq(&tsk->sighand->siglock);
-        sigorsets(&tsk->blocked, &tsk->blocked,
-                  &ka->sa.sa_mask);
+        sigorsets(&blocked, &tsk->blocked, &ka->sa.sa_mask);
         if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&tsk->blocked, sig);
-        recalc_sigpending();
-        spin_unlock_irq(&tsk->sighand->siglock);
+                sigaddset(&blocked, sig);
+        set_current_blocked(&blocked);
 
         return 0;
 }
diff --git a/arch/unicore32/kernel/time.c b/arch/unicore32/kernel/time.c
index 080710c0924..d3824b2ff64 100644
--- a/arch/unicore32/kernel/time.c
+++ b/arch/unicore32/kernel/time.c
@@ -86,7 +86,7 @@ static struct clocksource cksrc_puv3_oscr = {
 
 static struct irqaction puv3_timer_irq = {
         .name           = "ost0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = puv3_ost0_interrupt,
         .dev_id         = &ckevt_puv3_osmr0,
 };
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1d2a69dd36d..1a31254ceb8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -62,6 +62,7 @@ config X86
         select ANON_INODES
         select HAVE_ARCH_KMEMCHECK
         select HAVE_USER_RETURN_NOTIFIER
+        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
         select HAVE_ARCH_JUMP_LABEL
         select HAVE_TEXT_POKE_SMP
         select HAVE_GENERIC_HARDIRQS
@@ -77,6 +78,7 @@ config X86
         select HAVE_BPF_JIT if (X86_64 && NET)
         select CLKEVT_I8253
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
+        select GENERIC_IOMAP
 
 config INSTRUCTION_DECODER
         def_bool (KPROBES || PERF_EVENTS)
@@ -142,9 +144,6 @@ config NEED_SG_DMA_LENGTH
 config GENERIC_ISA_DMA
         def_bool ISA_DMA_API
 
-config GENERIC_IOMAP
-        def_bool y
-
 config GENERIC_BUG
         def_bool y
         depends on BUG
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index f3444f700f3..17c5d4bdee5 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -197,7 +197,10 @@
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
 #define X86_FEATURE_FSGSBASE    (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
+#define X86_FEATURE_BMI1        (9*32+ 3) /* 1st group bit manipulation extensions */
+#define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
 #define X86_FEATURE_SMEP        (9*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_BMI2        (9*32+ 8) /* 2nd group bit manipulation extensions */
 #define X86_FEATURE_ERMS        (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
index 345c99cef15..dffc38ee625 100644
--- a/arch/x86/include/asm/iommu.h
+++ b/arch/x86/include/asm/iommu.h
@@ -5,6 +5,7 @@ extern struct dma_map_ops nommu_dma_ops;
 extern int force_iommu, no_iommu;
 extern int iommu_detected;
 extern int iommu_pass_through;
+extern int iommu_group_mf;
 
 /* 10 seconds */
 #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000)
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index a026507893e..ab4092e3214 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -181,6 +181,7 @@ struct x86_emulate_ops {
         int (*set_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong value);
         int (*set_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 data);
         int (*get_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 *pdata);
+        int (*read_pmc)(struct x86_emulate_ctxt *ctxt, u32 pmc, u64 *pdata);
         void (*halt)(struct x86_emulate_ctxt *ctxt);
         void (*wbinvd)(struct x86_emulate_ctxt *ctxt);
         int (*fix_hypercall)(struct x86_emulate_ctxt *ctxt);
@@ -364,6 +365,7 @@ enum x86_intercept {
 #endif
 
 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len);
+bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt);
 #define EMULATION_FAILED -1
 #define EMULATION_OK 0
 #define EMULATION_RESTART 1
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index b4973f4dab9..52d6640a5ca 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -16,10 +16,12 @@
 #include <linux/mmu_notifier.h>
 #include <linux/tracepoint.h>
 #include <linux/cpumask.h>
+#include <linux/irq_work.h>
 
 #include <linux/kvm.h>
 #include <linux/kvm_para.h>
 #include <linux/kvm_types.h>
+#include <linux/perf_event.h>
 
 #include <asm/pvclock-abi.h>
 #include <asm/desc.h>
@@ -31,6 +33,8 @@
 #define KVM_MEMORY_SLOTS 32
 /* memory slots that does not exposed to userspace */
 #define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS)
+
 #define KVM_MMIO_SIZE 16
 
 #define KVM_PIO_PAGE_OFFSET 1
@@ -228,7 +232,7 @@ struct kvm_mmu_page {
          * One bit set per slot which has memory
          * in this shadow page.
          */
-        DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
+        DECLARE_BITMAP(slot_bitmap, KVM_MEM_SLOTS_NUM);
         bool unsync;
         int root_count;          /* Currently serving as active root */
         unsigned int unsync_children;
@@ -239,14 +243,9 @@ struct kvm_mmu_page {
         int clear_spte_count;
 #endif
 
-        struct rcu_head rcu;
-};
+        int write_flooding_count;
 
-struct kvm_pv_mmu_op_buffer {
-        void *ptr;
-        unsigned len;
-        unsigned processed;
-        char buf[512] __aligned(sizeof(long));
+        struct rcu_head rcu;
 };
 
 struct kvm_pio_request {
@@ -294,6 +293,37 @@ struct kvm_mmu {
         u64 pdptrs[4]; /* pae */
 };
 
+enum pmc_type {
+        KVM_PMC_GP = 0,
+        KVM_PMC_FIXED,
+};
+
+struct kvm_pmc {
+        enum pmc_type type;
+        u8 idx;
+        u64 counter;
+        u64 eventsel;
+        struct perf_event *perf_event;
+        struct kvm_vcpu *vcpu;
+};
+
+struct kvm_pmu {
+        unsigned nr_arch_gp_counters;
+        unsigned nr_arch_fixed_counters;
+        unsigned available_event_types;
+        u64 fixed_ctr_ctrl;
+        u64 global_ctrl;
+        u64 global_status;
+        u64 global_ovf_ctrl;
+        u64 counter_bitmask[2];
+        u64 global_ctrl_mask;
+        u8 version;
+        struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC];
+        struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED];
+        struct irq_work irq_work;
+        u64 reprogram_pmi;
+};
+
 struct kvm_vcpu_arch {
         /*
          * rip and regs accesses must go through
@@ -345,19 +375,10 @@ struct kvm_vcpu_arch {
          */
         struct kvm_mmu *walk_mmu;
 
-        /* only needed in kvm_pv_mmu_op() path, but it's hot so
-         * put it here to avoid allocation */
-        struct kvm_pv_mmu_op_buffer mmu_op_buffer;
-
         struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
         struct kvm_mmu_memory_cache mmu_page_cache;
         struct kvm_mmu_memory_cache mmu_page_header_cache;
 
-        gfn_t last_pt_write_gfn;
-        int   last_pt_write_count;
-        u64  *last_pte_updated;
-        gfn_t last_pte_gfn;
-
         struct fpu guest_fpu;
         u64 xcr0;
 
@@ -436,6 +457,8 @@ struct kvm_vcpu_arch {
         unsigned access;
         gfn_t mmio_gfn;
 
+        struct kvm_pmu pmu;
+
         /* used for guest single stepping over the given code position */
         unsigned long singlestep_rip;
 
@@ -444,6 +467,9 @@ struct kvm_vcpu_arch {
 
         cpumask_var_t wbinvd_dirty_mask;
 
+        unsigned long last_retry_eip;
+        unsigned long last_retry_addr;
+
         struct {
                 bool halted;
                 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
@@ -459,7 +485,6 @@ struct kvm_arch {
         unsigned int n_requested_mmu_pages;
         unsigned int n_max_mmu_pages;
         unsigned int indirect_shadow_pages;
-        atomic_t invlpg_counter;
         struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
         /*
          * Hash table of struct kvm_mmu_page.
@@ -660,6 +685,8 @@ void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
 
 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
+int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
+                               struct kvm_memory_slot *slot);
 void kvm_mmu_zap_all(struct kvm *kvm);
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
@@ -668,8 +695,6 @@ int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
 
 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
                           const void *val, int bytes);
-int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
-                  gpa_t addr, unsigned long *ret);
 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
 
 extern bool tdp_enabled;
@@ -692,6 +717,7 @@ enum emulation_result {
 #define EMULTYPE_NO_DECODE          (1 << 0)
 #define EMULTYPE_TRAP_UD            (1 << 1)
 #define EMULTYPE_SKIP               (1 << 2)
+#define EMULTYPE_RETRY              (1 << 3)
 int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
                             int emulation_type, void *insn, int insn_len);
 
@@ -734,6 +760,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 
 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
+bool kvm_rdpmc(struct kvm_vcpu *vcpu);
 
 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
@@ -754,13 +781,14 @@ int fx_init(struct kvm_vcpu *vcpu);
 
 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
-                       const u8 *new, int bytes,
-                       bool guest_initiated);
+                       const u8 *new, int bytes);
+int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
 int kvm_mmu_load(struct kvm_vcpu *vcpu);
 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
+gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
                               struct x86_exception *exception);
 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
@@ -782,6 +810,11 @@ void kvm_disable_tdp(void);
 int complete_pio(struct kvm_vcpu *vcpu);
 bool kvm_check_iopl(struct kvm_vcpu *vcpu);
 
+static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
+{
+        return gpa;
+}
+
 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
 {
         struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
@@ -894,4 +927,17 @@ extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
 
 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
 
+int kvm_is_in_guest(void);
+
+void kvm_pmu_init(struct kvm_vcpu *vcpu);
+void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
+void kvm_pmu_reset(struct kvm_vcpu *vcpu);
+void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu);
+bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr);
+int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
+int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
+int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
+void kvm_handle_pmu_event(struct kvm_vcpu *vcpu);
+void kvm_deliver_pmi(struct kvm_vcpu *vcpu);
+
 #endif /* _ASM_X86_KVM_HOST_H */
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 93f79094c22..0a0a9546043 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -67,7 +67,7 @@ extern struct console early_mrst_console;
 extern void mrst_early_console_init(void);
 
 extern struct console early_hsu_console;
-extern void hsu_early_console_init(void);
+extern void hsu_early_console_init(const char *);
 
 extern void intel_scu_devices_create(void);
 extern void intel_scu_devices_destroy(void);
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 529bf07e806..7a11910a63c 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -414,22 +414,6 @@ do {									\
 #define this_cpu_xchg_2(pcp, nval)      percpu_xchg_op(pcp, nval)
 #define this_cpu_xchg_4(pcp, nval)      percpu_xchg_op(pcp, nval)
 
-#define irqsafe_cpu_add_1(pcp, val)     percpu_add_op((pcp), val)
-#define irqsafe_cpu_add_2(pcp, val)     percpu_add_op((pcp), val)
-#define irqsafe_cpu_add_4(pcp, val)     percpu_add_op((pcp), val)
-#define irqsafe_cpu_and_1(pcp, val)     percpu_to_op("and", (pcp), val)
-#define irqsafe_cpu_and_2(pcp, val)     percpu_to_op("and", (pcp), val)
-#define irqsafe_cpu_and_4(pcp, val)     percpu_to_op("and", (pcp), val)
-#define irqsafe_cpu_or_1(pcp, val)      percpu_to_op("or", (pcp), val)
-#define irqsafe_cpu_or_2(pcp, val)      percpu_to_op("or", (pcp), val)
-#define irqsafe_cpu_or_4(pcp, val)      percpu_to_op("or", (pcp), val)
-#define irqsafe_cpu_xor_1(pcp, val)     percpu_to_op("xor", (pcp), val)
-#define irqsafe_cpu_xor_2(pcp, val)     percpu_to_op("xor", (pcp), val)
-#define irqsafe_cpu_xor_4(pcp, val)     percpu_to_op("xor", (pcp), val)
-#define irqsafe_cpu_xchg_1(pcp, nval)   percpu_xchg_op(pcp, nval)
-#define irqsafe_cpu_xchg_2(pcp, nval)   percpu_xchg_op(pcp, nval)
-#define irqsafe_cpu_xchg_4(pcp, nval)   percpu_xchg_op(pcp, nval)
-
 #ifndef CONFIG_M386
 #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
 #define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
@@ -445,9 +429,6 @@ do {									\
 #define this_cpu_cmpxchg_2(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 #define this_cpu_cmpxchg_4(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 
-#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
-#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
-#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
 #endif /* !CONFIG_M386 */
 
 #ifdef CONFIG_X86_CMPXCHG64
@@ -464,7 +445,6 @@ do {									\
 
 #define __this_cpu_cmpxchg_double_4     percpu_cmpxchg8b_double
 #define this_cpu_cmpxchg_double_4       percpu_cmpxchg8b_double
-#define irqsafe_cpu_cmpxchg_double_4    percpu_cmpxchg8b_double
 #endif /* CONFIG_X86_CMPXCHG64 */
 
 /*
@@ -492,13 +472,6 @@ do {									\
 #define this_cpu_xchg_8(pcp, nval)      percpu_xchg_op(pcp, nval)
 #define this_cpu_cmpxchg_8(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 
-#define irqsafe_cpu_add_8(pcp, val)     percpu_add_op((pcp), val)
-#define irqsafe_cpu_and_8(pcp, val)     percpu_to_op("and", (pcp), val)
-#define irqsafe_cpu_or_8(pcp, val)      percpu_to_op("or", (pcp), val)
-#define irqsafe_cpu_xor_8(pcp, val)     percpu_to_op("xor", (pcp), val)
-#define irqsafe_cpu_xchg_8(pcp, nval)   percpu_xchg_op(pcp, nval)
-#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
-
 /*
  * Pretty complex macro to generate cmpxchg16 instruction.  The instruction
  * is not supported on early AMD64 processors so we must be able to emulate
@@ -521,7 +494,6 @@ do {									\
 
 #define __this_cpu_cmpxchg_double_8     percpu_cmpxchg16b_double
 #define this_cpu_cmpxchg_double_8       percpu_cmpxchg16b_double
-#define irqsafe_cpu_cmpxchg_double_8    percpu_cmpxchg16b_double
 
 #endif
 
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index cd28a350f7f..9d42a52d233 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -247,7 +247,7 @@ static int __init setup_early_printk(char *buf)
                 }
 
                 if (!strncmp(buf, "hsu", 3)) {
-                        hsu_early_console_init();
+                        hsu_early_console_init(buf + 3);
                         early_console_register(&early_hsu_console, keep);
                 }
 #endif
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index a9c2116001d..f0c6fd6f176 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -39,8 +39,6 @@
 #include <asm/desc.h>
 #include <asm/tlbflush.h>
 
-#define MMU_QUEUE_SIZE 1024
-
 static int kvmapf = 1;
 
 static int parse_no_kvmapf(char *arg)
@@ -60,21 +58,10 @@ static int parse_no_stealacc(char *arg)
 
 early_param("no-steal-acc", parse_no_stealacc);
 
-struct kvm_para_state {
-        u8 mmu_queue[MMU_QUEUE_SIZE];
-        int mmu_queue_len;
-};
-
-static DEFINE_PER_CPU(struct kvm_para_state, para_state);
 static DEFINE_PER_CPU(struct kvm_vcpu_pv_apf_data, apf_reason) __aligned(64);
 static DEFINE_PER_CPU(struct kvm_steal_time, steal_time) __aligned(64);
 static int has_steal_clock = 0;
 
-static struct kvm_para_state *kvm_para_state(void)
-{
-        return &per_cpu(para_state, raw_smp_processor_id());
-}
-
 /*
  * No need for any "IO delay" on KVM
  */
@@ -271,151 +258,6 @@ do_async_page_fault(struct pt_regs *regs, unsigned long error_code)
         }
 }
 
-static void kvm_mmu_op(void *buffer, unsigned len)
-{
-        int r;
-        unsigned long a1, a2;
-
-        do {
-                a1 = __pa(buffer);
-                a2 = 0;   /* on i386 __pa() always returns <4G */
-                r = kvm_hypercall3(KVM_HC_MMU_OP, len, a1, a2);
-                buffer += r;
-                len -= r;
-        } while (len);
-}
-
-static void mmu_queue_flush(struct kvm_para_state *state)
-{
-        if (state->mmu_queue_len) {
-                kvm_mmu_op(state->mmu_queue, state->mmu_queue_len);
-                state->mmu_queue_len = 0;
-        }
-}
-
-static void kvm_deferred_mmu_op(void *buffer, int len)
-{
-        struct kvm_para_state *state = kvm_para_state();
-
-        if (paravirt_get_lazy_mode() != PARAVIRT_LAZY_MMU) {
-                kvm_mmu_op(buffer, len);
-                return;
-        }
-        if (state->mmu_queue_len + len > sizeof state->mmu_queue)
-                mmu_queue_flush(state);
-        memcpy(state->mmu_queue + state->mmu_queue_len, buffer, len);
-        state->mmu_queue_len += len;
-}
-
-static void kvm_mmu_write(void *dest, u64 val)
-{
-        __u64 pte_phys;
-        struct kvm_mmu_op_write_pte wpte;
-
-#ifdef CONFIG_HIGHPTE
-        struct page *page;
-        unsigned long dst = (unsigned long) dest;
-
-        page = kmap_atomic_to_page(dest);
-        pte_phys = page_to_pfn(page);
-        pte_phys <<= PAGE_SHIFT;
-        pte_phys += (dst & ~(PAGE_MASK));
-#else
-        pte_phys = (unsigned long)__pa(dest);
-#endif
-        wpte.header.op = KVM_MMU_OP_WRITE_PTE;
-        wpte.pte_val = val;
-        wpte.pte_phys = pte_phys;
-
-        kvm_deferred_mmu_op(&wpte, sizeof wpte);
-}
-
-/*
- * We only need to hook operations that are MMU writes.  We hook these so that
- * we can use lazy MMU mode to batch these operations.  We could probably
- * improve the performance of the host code if we used some of the information
- * here to simplify processing of batched writes.
- */
-static void kvm_set_pte(pte_t *ptep, pte_t pte)
-{
-        kvm_mmu_write(ptep, pte_val(pte));
-}
-
-static void kvm_set_pte_at(struct mm_struct *mm, unsigned long addr,
-                           pte_t *ptep, pte_t pte)
-{
-        kvm_mmu_write(ptep, pte_val(pte));
-}
-
-static void kvm_set_pmd(pmd_t *pmdp, pmd_t pmd)
-{
-        kvm_mmu_write(pmdp, pmd_val(pmd));
-}
-
-#if PAGETABLE_LEVELS >= 3
-#ifdef CONFIG_X86_PAE
-static void kvm_set_pte_atomic(pte_t *ptep, pte_t pte)
-{
-        kvm_mmu_write(ptep, pte_val(pte));
-}
-
-static void kvm_pte_clear(struct mm_struct *mm,
-                          unsigned long addr, pte_t *ptep)
-{
-        kvm_mmu_write(ptep, 0);
-}
-
-static void kvm_pmd_clear(pmd_t *pmdp)
-{
-        kvm_mmu_write(pmdp, 0);
-}
-#endif
-
-static void kvm_set_pud(pud_t *pudp, pud_t pud)
-{
-        kvm_mmu_write(pudp, pud_val(pud));
-}
-
-#if PAGETABLE_LEVELS == 4
-static void kvm_set_pgd(pgd_t *pgdp, pgd_t pgd)
-{
-        kvm_mmu_write(pgdp, pgd_val(pgd));
-}
-#endif
-#endif /* PAGETABLE_LEVELS >= 3 */
-
-static void kvm_flush_tlb(void)
-{
-        struct kvm_mmu_op_flush_tlb ftlb = {
-                .header.op = KVM_MMU_OP_FLUSH_TLB,
-        };
-
-        kvm_deferred_mmu_op(&ftlb, sizeof ftlb);
-}
-
-static void kvm_release_pt(unsigned long pfn)
-{
-        struct kvm_mmu_op_release_pt rpt = {
-                .header.op = KVM_MMU_OP_RELEASE_PT,
-                .pt_phys = (u64)pfn << PAGE_SHIFT,
-        };
-
-        kvm_mmu_op(&rpt, sizeof rpt);
-}
-
-static void kvm_enter_lazy_mmu(void)
-{
-        paravirt_enter_lazy_mmu();
-}
-
-static void kvm_leave_lazy_mmu(void)
-{
-        struct kvm_para_state *state = kvm_para_state();
-
-        mmu_queue_flush(state);
-        paravirt_leave_lazy_mmu();
-}
-
 static void __init paravirt_ops_setup(void)
 {
         pv_info.name = "KVM";
@@ -424,29 +266,6 @@ static void __init paravirt_ops_setup(void)
         if (kvm_para_has_feature(KVM_FEATURE_NOP_IO_DELAY))
                 pv_cpu_ops.io_delay = kvm_io_delay;
 
-        if (kvm_para_has_feature(KVM_FEATURE_MMU_OP)) {
-                pv_mmu_ops.set_pte = kvm_set_pte;
-                pv_mmu_ops.set_pte_at = kvm_set_pte_at;
-                pv_mmu_ops.set_pmd = kvm_set_pmd;
-#if PAGETABLE_LEVELS >= 3
-#ifdef CONFIG_X86_PAE
-                pv_mmu_ops.set_pte_atomic = kvm_set_pte_atomic;
-                pv_mmu_ops.pte_clear = kvm_pte_clear;
-                pv_mmu_ops.pmd_clear = kvm_pmd_clear;
-#endif
-                pv_mmu_ops.set_pud = kvm_set_pud;
-#if PAGETABLE_LEVELS == 4
-                pv_mmu_ops.set_pgd = kvm_set_pgd;
-#endif
-#endif
-                pv_mmu_ops.flush_tlb_user = kvm_flush_tlb;
-                pv_mmu_ops.release_pte = kvm_release_pt;
-                pv_mmu_ops.release_pmd = kvm_release_pt;
-                pv_mmu_ops.release_pud = kvm_release_pt;
-
-                pv_mmu_ops.lazy_mode.enter = kvm_enter_lazy_mmu;
-                pv_mmu_ops.lazy_mode.leave = kvm_leave_lazy_mmu;
-        }
 #ifdef CONFIG_X86_IO_APIC
         no_timer_check = 1;
 #endif
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 80dc793b3f6..1c4d769e21e 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -45,6 +45,15 @@ int iommu_detected __read_mostly = 0;
  */
 int iommu_pass_through __read_mostly;
 
+/*
+ * Group multi-function PCI devices into a single device-group for the
+ * iommu_device_group interface.  This tells the iommu driver to pretend
+ * it cannot distinguish between functions of a device, exposing only one
+ * group for the device.  Useful for disallowing use of individual PCI
+ * functions from userspace drivers.
+ */
+int iommu_group_mf __read_mostly;
+
 extern struct iommu_table_entry __iommu_table[], __iommu_table_end[];
 
 /* Dummy device used for NULL arguments (normally ISA). */
@@ -169,6 +178,8 @@ static __init int iommu_setup(char *p)
 #endif
                 if (!strncmp(p, "pt", 2))
                         iommu_pass_through = 1;
+                if (!strncmp(p, "group_mf", 8))
+                        iommu_group_mf = 1;
 
                 gart_parse_options(p);
 
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 54ddaeb221c..46a01bdc27e 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -682,7 +682,6 @@ static int
 handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
                 struct pt_regs *regs)
 {
-        sigset_t blocked;
         int ret;
 
         /* Are we from a system call? */
@@ -733,10 +732,7 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
          */
         regs->flags &= ~X86_EFLAGS_TF;
 
-        sigorsets(&blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&blocked, sig);
-        set_current_blocked(&blocked);
+        block_sigmask(ka, sig);
 
         tracehook_signal_handler(sig, info, ka, regs,
                                  test_thread_flag(TIF_SINGLESTEP));
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index ff5790d8e99..1a7fe868f37 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -35,6 +35,7 @@ config KVM
         select KVM_MMIO
         select TASKSTATS
         select TASK_DELAY_ACCT
+        select PERF_EVENTS
         ---help---
           Support hosting fully virtualized guest machines using hardware
           virtualization extensions.  You will need a fairly recent
@@ -52,6 +53,8 @@ config KVM
 config KVM_INTEL
         tristate "KVM for Intel processors support"
         depends on KVM
+        # for perf_guest_get_msrs():
+        depends on CPU_SUP_INTEL
         ---help---
           Provides support for KVM on Intel processors equipped with the VT
           extensions.
diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
index f15501f431c..4f579e8dcac 100644
--- a/arch/x86/kvm/Makefile
+++ b/arch/x86/kvm/Makefile
@@ -12,7 +12,7 @@ kvm-$(CONFIG_IOMMU_API)	+= $(addprefix ../../../virt/kvm/, iommu.o)
 kvm-$(CONFIG_KVM_ASYNC_PF)      += $(addprefix ../../../virt/kvm/, async_pf.o)
 
 kvm-y                   += x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
-                           i8254.o timer.o
+                           i8254.o timer.o cpuid.o pmu.o
 kvm-intel-y             += vmx.o
 kvm-amd-y               += svm.o
 
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
new file mode 100644
index 00000000000..89b02bfaaca
--- /dev/null
+++ b/arch/x86/kvm/cpuid.c
@@ -0,0 +1,670 @@
+/*
+ * Kernel-based Virtual Machine driver for Linux
+ * cpuid support routines
+ *
+ * derived from arch/x86/kvm/x86.c
+ *
+ * Copyright 2011 Red Hat, Inc. and/or its affiliates.
+ * Copyright IBM Corporation, 2008
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/uaccess.h>
+#include <asm/user.h>
+#include <asm/xsave.h>
+#include "cpuid.h"
+#include "lapic.h"
+#include "mmu.h"
+#include "trace.h"
+
+void kvm_update_cpuid(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+        struct kvm_lapic *apic = vcpu->arch.apic;
+
+        best = kvm_find_cpuid_entry(vcpu, 1, 0);
+        if (!best)
+                return;
+
+        /* Update OSXSAVE bit */
+        if (cpu_has_xsave && best->function == 0x1) {
+                best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
+                if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
+                        best->ecx |= bit(X86_FEATURE_OSXSAVE);
+        }
+
+        if (apic) {
+                if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
+                        apic->lapic_timer.timer_mode_mask = 3 << 17;
+                else
+                        apic->lapic_timer.timer_mode_mask = 1 << 17;
+        }
+
+        kvm_pmu_cpuid_update(vcpu);
+}
+
+static int is_efer_nx(void)
+{
+        unsigned long long efer = 0;
+
+        rdmsrl_safe(MSR_EFER, &efer);
+        return efer & EFER_NX;
+}
+
+static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
+{
+        int i;
+        struct kvm_cpuid_entry2 *e, *entry;
+
+        entry = NULL;
+        for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
+                e = &vcpu->arch.cpuid_entries[i];
+                if (e->function == 0x80000001) {
+                        entry = e;
+                        break;
+                }
+        }
+        if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
+                entry->edx &= ~(1 << 20);
+                printk(KERN_INFO "kvm: guest NX capability removed\n");
+        }
+}
+
+/* when an old userspace process fills a new kernel module */
+int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
+                             struct kvm_cpuid *cpuid,
+                             struct kvm_cpuid_entry __user *entries)
+{
+        int r, i;
+        struct kvm_cpuid_entry *cpuid_entries;
+
+        r = -E2BIG;
+        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
+                goto out;
+        r = -ENOMEM;
+        cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
+        if (!cpuid_entries)
+                goto out;
+        r = -EFAULT;
+        if (copy_from_user(cpuid_entries, entries,
+                           cpuid->nent * sizeof(struct kvm_cpuid_entry)))
+                goto out_free;
+        for (i = 0; i < cpuid->nent; i++) {
+                vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
+                vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
+                vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
+                vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
+                vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
+                vcpu->arch.cpuid_entries[i].index = 0;
+                vcpu->arch.cpuid_entries[i].flags = 0;
+                vcpu->arch.cpuid_entries[i].padding[0] = 0;
+                vcpu->arch.cpuid_entries[i].padding[1] = 0;
+                vcpu->arch.cpuid_entries[i].padding[2] = 0;
+        }
+        vcpu->arch.cpuid_nent = cpuid->nent;
+        cpuid_fix_nx_cap(vcpu);
+        r = 0;
+        kvm_apic_set_version(vcpu);
+        kvm_x86_ops->cpuid_update(vcpu);
+        kvm_update_cpuid(vcpu);
+
+out_free:
+        vfree(cpuid_entries);
+out:
+        return r;
+}
+
+int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
+                              struct kvm_cpuid2 *cpuid,
+                              struct kvm_cpuid_entry2 __user *entries)
+{
+        int r;
+
+        r = -E2BIG;
+        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
+                goto out;
+        r = -EFAULT;
+        if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
+                           cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
+                goto out;
+        vcpu->arch.cpuid_nent = cpuid->nent;
+        kvm_apic_set_version(vcpu);
+        kvm_x86_ops->cpuid_update(vcpu);
+        kvm_update_cpuid(vcpu);
+        return 0;
+
+out:
+        return r;
+}
+
+int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
+                              struct kvm_cpuid2 *cpuid,
+                              struct kvm_cpuid_entry2 __user *entries)
+{
+        int r;
+
+        r = -E2BIG;
+        if (cpuid->nent < vcpu->arch.cpuid_nent)
+                goto out;
+        r = -EFAULT;
+        if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
+                         vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
+                goto out;
+        return 0;
+
+out:
+        cpuid->nent = vcpu->arch.cpuid_nent;
+        return r;
+}
+
+static void cpuid_mask(u32 *word, int wordnum)
+{
+        *word &= boot_cpu_data.x86_capability[wordnum];
+}
+
+static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+                           u32 index)
+{
+        entry->function = function;
+        entry->index = index;
+        cpuid_count(entry->function, entry->index,
+                    &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
+        entry->flags = 0;
+}
+
+static bool supported_xcr0_bit(unsigned bit)
+{
+        u64 mask = ((u64)1 << bit);
+
+        return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
+}
+
+#define F(x) bit(X86_FEATURE_##x)
+
+static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+                         u32 index, int *nent, int maxnent)
+{
+        int r;
+        unsigned f_nx = is_efer_nx() ? F(NX) : 0;
+#ifdef CONFIG_X86_64
+        unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
+                                ? F(GBPAGES) : 0;
+        unsigned f_lm = F(LM);
+#else
+        unsigned f_gbpages = 0;
+        unsigned f_lm = 0;
+#endif
+        unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
+
+        /* cpuid 1.edx */
+        const u32 kvm_supported_word0_x86_features =
+                F(FPU) | F(VME) | F(DE) | F(PSE) |
+                F(TSC) | F(MSR) | F(PAE) | F(MCE) |
+                F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
+                F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
+                F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
+                0 /* Reserved, DS, ACPI */ | F(MMX) |
+                F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
+                0 /* HTT, TM, Reserved, PBE */;
+        /* cpuid 0x80000001.edx */
+        const u32 kvm_supported_word1_x86_features =
+                F(FPU) | F(VME) | F(DE) | F(PSE) |
+                F(TSC) | F(MSR) | F(PAE) | F(MCE) |
+                F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
+                F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
+                F(PAT) | F(PSE36) | 0 /* Reserved */ |
+                f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
+                F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
+                0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
+        /* cpuid 1.ecx */
+        const u32 kvm_supported_word4_x86_features =
+                F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
+                0 /* DS-CPL, VMX, SMX, EST */ |
+                0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
+                F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
+                0 /* Reserved, DCA */ | F(XMM4_1) |
+                F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
+                0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
+                F(F16C) | F(RDRAND);
+        /* cpuid 0x80000001.ecx */
+        const u32 kvm_supported_word6_x86_features =
+                F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
+                F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
+                F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
+                0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
+
+        /* cpuid 0xC0000001.edx */
+        const u32 kvm_supported_word5_x86_features =
+                F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
+                F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
+                F(PMM) | F(PMM_EN);
+
+        /* cpuid 7.0.ebx */
+        const u32 kvm_supported_word9_x86_features =
+                F(FSGSBASE) | F(BMI1) | F(AVX2) | F(SMEP) | F(BMI2) | F(ERMS);
+
+        /* all calls to cpuid_count() should be made on the same cpu */
+        get_cpu();
+
+        r = -E2BIG;
+
+        if (*nent >= maxnent)
+                goto out;
+
+        do_cpuid_1_ent(entry, function, index);
+        ++*nent;
+
+        switch (function) {
+        case 0:
+                entry->eax = min(entry->eax, (u32)0xd);
+                break;
+        case 1:
+                entry->edx &= kvm_supported_word0_x86_features;
+                cpuid_mask(&entry->edx, 0);
+                entry->ecx &= kvm_supported_word4_x86_features;
+                cpuid_mask(&entry->ecx, 4);
+                /* we support x2apic emulation even if host does not support
+                 * it since we emulate x2apic in software */
+                entry->ecx |= F(X2APIC);
+                break;
+        /* function 2 entries are STATEFUL. That is, repeated cpuid commands
+         * may return different values. This forces us to get_cpu() before
+         * issuing the first command, and also to emulate this annoying behavior
+         * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
+        case 2: {
+                int t, times = entry->eax & 0xff;
+
+                entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
+                entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
+                for (t = 1; t < times; ++t) {
+                        if (*nent >= maxnent)
+                                goto out;
+
+                        do_cpuid_1_ent(&entry[t], function, 0);
+                        entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
+                        ++*nent;
+                }
+                break;
+        }
+        /* function 4 has additional index. */
+        case 4: {
+                int i, cache_type;
+
+                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                /* read more entries until cache_type is zero */
+                for (i = 1; ; ++i) {
+                        if (*nent >= maxnent)
+                                goto out;
+
+                        cache_type = entry[i - 1].eax & 0x1f;
+                        if (!cache_type)
+                                break;
+                        do_cpuid_1_ent(&entry[i], function, i);
+                        entry[i].flags |=
+                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                        ++*nent;
+                }
+                break;
+        }
+        case 7: {
+                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                /* Mask ebx against host capbability word 9 */
+                if (index == 0) {
+                        entry->ebx &= kvm_supported_word9_x86_features;
+                        cpuid_mask(&entry->ebx, 9);
+                } else
+                        entry->ebx = 0;
+                entry->eax = 0;
+                entry->ecx = 0;
+                entry->edx = 0;
+                break;
+        }
+        case 9:
+                break;
+        case 0xa: { /* Architectural Performance Monitoring */
+                struct x86_pmu_capability cap;
+                union cpuid10_eax eax;
+                union cpuid10_edx edx;
+
+                perf_get_x86_pmu_capability(&cap);
+
+                /*
+                 * Only support guest architectural pmu on a host
+                 * with architectural pmu.
+                 */
+                if (!cap.version)
+                        memset(&cap, 0, sizeof(cap));
+
+                eax.split.version_id = min(cap.version, 2);
+                eax.split.num_counters = cap.num_counters_gp;
+                eax.split.bit_width = cap.bit_width_gp;
+                eax.split.mask_length = cap.events_mask_len;
+
+                edx.split.num_counters_fixed = cap.num_counters_fixed;
+                edx.split.bit_width_fixed = cap.bit_width_fixed;
+                edx.split.reserved = 0;
+
+                entry->eax = eax.full;
+                entry->ebx = cap.events_mask;
+                entry->ecx = 0;
+                entry->edx = edx.full;
+                break;
+        }
+        /* function 0xb has additional index. */
+        case 0xb: {
+                int i, level_type;
+
+                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                /* read more entries until level_type is zero */
+                for (i = 1; ; ++i) {
+                        if (*nent >= maxnent)
+                                goto out;
+
+                        level_type = entry[i - 1].ecx & 0xff00;
+                        if (!level_type)
+                                break;
+                        do_cpuid_1_ent(&entry[i], function, i);
+                        entry[i].flags |=
+                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                        ++*nent;
+                }
+                break;
+        }
+        case 0xd: {
+                int idx, i;
+
+                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                for (idx = 1, i = 1; idx < 64; ++idx) {
+                        if (*nent >= maxnent)
+                                goto out;
+
+                        do_cpuid_1_ent(&entry[i], function, idx);
+                        if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
+                                continue;
+                        entry[i].flags |=
+                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                        ++*nent;
+                        ++i;
+                }
+                break;
+        }
+        case KVM_CPUID_SIGNATURE: {
+                char signature[12] = "KVMKVMKVM\0\0";
+                u32 *sigptr = (u32 *)signature;
+                entry->eax = 0;
+                entry->ebx = sigptr[0];
+                entry->ecx = sigptr[1];
+                entry->edx = sigptr[2];
+                break;
+        }
+        case KVM_CPUID_FEATURES:
+                entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
+                             (1 << KVM_FEATURE_NOP_IO_DELAY) |
+                             (1 << KVM_FEATURE_CLOCKSOURCE2) |
+                             (1 << KVM_FEATURE_ASYNC_PF) |
+                             (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
+
+                if (sched_info_on())
+                        entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
+
+                entry->ebx = 0;
+                entry->ecx = 0;
+                entry->edx = 0;
+                break;
+        case 0x80000000:
+                entry->eax = min(entry->eax, 0x8000001a);
+                break;
+        case 0x80000001:
+                entry->edx &= kvm_supported_word1_x86_features;
+                cpuid_mask(&entry->edx, 1);
+                entry->ecx &= kvm_supported_word6_x86_features;
+                cpuid_mask(&entry->ecx, 6);
+                break;
+        case 0x80000008: {
+                unsigned g_phys_as = (entry->eax >> 16) & 0xff;
+                unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
+                unsigned phys_as = entry->eax & 0xff;
+
+                if (!g_phys_as)
+                        g_phys_as = phys_as;
+                entry->eax = g_phys_as | (virt_as << 8);
+                entry->ebx = entry->edx = 0;
+                break;
+        }
+        case 0x80000019:
+                entry->ecx = entry->edx = 0;
+                break;
+        case 0x8000001a:
+                break;
+        case 0x8000001d:
+                break;
+        /*Add support for Centaur's CPUID instruction*/
+        case 0xC0000000:
+                /*Just support up to 0xC0000004 now*/
+                entry->eax = min(entry->eax, 0xC0000004);
+                break;
+        case 0xC0000001:
+                entry->edx &= kvm_supported_word5_x86_features;
+                cpuid_mask(&entry->edx, 5);
+                break;
+        case 3: /* Processor serial number */
+        case 5: /* MONITOR/MWAIT */
+        case 6: /* Thermal management */
+        case 0x80000007: /* Advanced power management */
+        case 0xC0000002:
+        case 0xC0000003:
+        case 0xC0000004:
+        default:
+                entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
+                break;
+        }
+
+        kvm_x86_ops->set_supported_cpuid(function, entry);
+
+        r = 0;
+
+out:
+        put_cpu();
+
+        return r;
+}
+
+#undef F
+
+struct kvm_cpuid_param {
+        u32 func;
+        u32 idx;
+        bool has_leaf_count;
+        bool (*qualifier)(struct kvm_cpuid_param *param);
+};
+
+static bool is_centaur_cpu(struct kvm_cpuid_param *param)
+{
+        return boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR;
+}
+
+int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
+                                      struct kvm_cpuid_entry2 __user *entries)
+{
+        struct kvm_cpuid_entry2 *cpuid_entries;
+        int limit, nent = 0, r = -E2BIG, i;
+        u32 func;
+        static struct kvm_cpuid_param param[] = {
+                { .func = 0, .has_leaf_count = true },
+                { .func = 0x80000000, .has_leaf_count = true },
+                { .func = 0xC0000000, .qualifier = is_centaur_cpu, .has_leaf_count = true },
+                { .func = KVM_CPUID_SIGNATURE },
+                { .func = KVM_CPUID_FEATURES },
+        };
+
+        if (cpuid->nent < 1)
+                goto out;
+        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
+                cpuid->nent = KVM_MAX_CPUID_ENTRIES;
+        r = -ENOMEM;
+        cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
+        if (!cpuid_entries)
+                goto out;
+
+        r = 0;
+        for (i = 0; i < ARRAY_SIZE(param); i++) {
+                struct kvm_cpuid_param *ent = &param[i];
+
+                if (ent->qualifier && !ent->qualifier(ent))
+                        continue;
+
+                r = do_cpuid_ent(&cpuid_entries[nent], ent->func, ent->idx,
+                                &nent, cpuid->nent);
+
+                if (r)
+                        goto out_free;
+
+                if (!ent->has_leaf_count)
+                        continue;
+
+                limit = cpuid_entries[nent - 1].eax;
+                for (func = ent->func + 1; func <= limit && nent < cpuid->nent && r == 0; ++func)
+                        r = do_cpuid_ent(&cpuid_entries[nent], func, ent->idx,
+                                     &nent, cpuid->nent);
+
+                if (r)
+                        goto out_free;
+        }
+
+        r = -EFAULT;
+        if (copy_to_user(entries, cpuid_entries,
+                         nent * sizeof(struct kvm_cpuid_entry2)))
+                goto out_free;
+        cpuid->nent = nent;
+        r = 0;
+
+out_free:
+        vfree(cpuid_entries);
+out:
+        return r;
+}
+
+static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
+{
+        struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
+        int j, nent = vcpu->arch.cpuid_nent;
+
+        e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
+        /* when no next entry is found, the current entry[i] is reselected */
+        for (j = i + 1; ; j = (j + 1) % nent) {
+                struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
+                if (ej->function == e->function) {
+                        ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
+                        return j;
+                }
+        }
+        return 0; /* silence gcc, even though control never reaches here */
+}
+
+/* find an entry with matching function, matching index (if needed), and that
+ * should be read next (if it's stateful) */
+static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
+        u32 function, u32 index)
+{
+        if (e->function != function)
+                return 0;
+        if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
+                return 0;
+        if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
+            !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
+                return 0;
+        return 1;
+}
+
+struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
+                                              u32 function, u32 index)
+{
+        int i;
+        struct kvm_cpuid_entry2 *best = NULL;
+
+        for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
+                struct kvm_cpuid_entry2 *e;
+
+                e = &vcpu->arch.cpuid_entries[i];
+                if (is_matching_cpuid_entry(e, function, index)) {
+                        if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
+                                move_to_next_stateful_cpuid_entry(vcpu, i);
+                        best = e;
+                        break;
+                }
+        }
+        return best;
+}
+EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
+
+int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
+        if (!best || best->eax < 0x80000008)
+                goto not_found;
+        best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
+        if (best)
+                return best->eax & 0xff;
+not_found:
+        return 36;
+}
+
+/*
+ * If no match is found, check whether we exceed the vCPU's limit
+ * and return the content of the highest valid _standard_ leaf instead.
+ * This is to satisfy the CPUID specification.
+ */
+static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
+                                                  u32 function, u32 index)
+{
+        struct kvm_cpuid_entry2 *maxlevel;
+
+        maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
+        if (!maxlevel || maxlevel->eax >= function)
+                return NULL;
+        if (function & 0x80000000) {
+                maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
+                if (!maxlevel)
+                        return NULL;
+        }
+        return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
+}
+
+void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
+{
+        u32 function, index;
+        struct kvm_cpuid_entry2 *best;
+
+        function = kvm_register_read(vcpu, VCPU_REGS_RAX);
+        index = kvm_register_read(vcpu, VCPU_REGS_RCX);
+        kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
+        kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
+        kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
+        kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
+        best = kvm_find_cpuid_entry(vcpu, function, index);
+
+        if (!best)
+                best = check_cpuid_limit(vcpu, function, index);
+
+        if (best) {
+                kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
+                kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
+                kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
+                kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
+        }
+        kvm_x86_ops->skip_emulated_instruction(vcpu);
+        trace_kvm_cpuid(function,
+                        kvm_register_read(vcpu, VCPU_REGS_RAX),
+                        kvm_register_read(vcpu, VCPU_REGS_RBX),
+                        kvm_register_read(vcpu, VCPU_REGS_RCX),
+                        kvm_register_read(vcpu, VCPU_REGS_RDX));
+}
+EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
new file mode 100644
index 00000000000..5b97e1797a6
--- /dev/null
+++ b/arch/x86/kvm/cpuid.h
@@ -0,0 +1,46 @@
+#ifndef ARCH_X86_KVM_CPUID_H
+#define ARCH_X86_KVM_CPUID_H
+
+#include "x86.h"
+
+void kvm_update_cpuid(struct kvm_vcpu *vcpu);
+struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
+                                              u32 function, u32 index);
+int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
+                                      struct kvm_cpuid_entry2 __user *entries);
+int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
+                             struct kvm_cpuid *cpuid,
+                             struct kvm_cpuid_entry __user *entries);
+int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
+                              struct kvm_cpuid2 *cpuid,
+                              struct kvm_cpuid_entry2 __user *entries);
+int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
+                              struct kvm_cpuid2 *cpuid,
+                              struct kvm_cpuid_entry2 __user *entries);
+
+
+static inline bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 1, 0);
+        return best && (best->ecx & bit(X86_FEATURE_XSAVE));
+}
+
+static inline bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 7, 0);
+        return best && (best->ebx & bit(X86_FEATURE_SMEP));
+}
+
+static inline bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 7, 0);
+        return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
+}
+
+#endif
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index f1e3be18a08..05a562b8502 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -125,8 +125,9 @@
 #define Lock        (1<<26) /* lock prefix is allowed for the instruction */
 #define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
 #define No64        (1<<28)
+#define PageTable   (1 << 29)   /* instruction used to write page table */
 /* Source 2 operand type */
-#define Src2Shift   (29)
+#define Src2Shift   (30)
 #define Src2None    (OpNone << Src2Shift)
 #define Src2CL      (OpCL << Src2Shift)
 #define Src2ImmByte (OpImmByte << Src2Shift)
@@ -1674,11 +1675,6 @@ static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
-static int em_grp1a(struct x86_emulate_ctxt *ctxt)
-{
-        return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
-}
-
 static int em_grp2(struct x86_emulate_ctxt *ctxt)
 {
         switch (ctxt->modrm_reg) {
@@ -1788,7 +1784,7 @@ static int em_grp45(struct x86_emulate_ctxt *ctxt)
         return rc;
 }
 
-static int em_grp9(struct x86_emulate_ctxt *ctxt)
+static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
 {
         u64 old = ctxt->dst.orig_val64;
 
@@ -1831,6 +1827,24 @@ static int em_ret_far(struct x86_emulate_ctxt *ctxt)
         return rc;
 }
 
+static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
+{
+        /* Save real source value, then compare EAX against destination. */
+        ctxt->src.orig_val = ctxt->src.val;
+        ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
+        emulate_2op_SrcV(ctxt, "cmp");
+
+        if (ctxt->eflags & EFLG_ZF) {
+                /* Success: write back to memory. */
+                ctxt->dst.val = ctxt->src.orig_val;
+        } else {
+                /* Failure: write the value we saw to EAX. */
+                ctxt->dst.type = OP_REG;
+                ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
+        }
+        return X86EMUL_CONTINUE;
+}
+
 static int em_lseg(struct x86_emulate_ctxt *ctxt)
 {
         int seg = ctxt->src2.val;
@@ -2481,6 +2495,15 @@ static int em_das(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
+static int em_call(struct x86_emulate_ctxt *ctxt)
+{
+        long rel = ctxt->src.val;
+
+        ctxt->src.val = (unsigned long)ctxt->_eip;
+        jmp_rel(ctxt, rel);
+        return em_push(ctxt);
+}
+
 static int em_call_far(struct x86_emulate_ctxt *ctxt)
 {
         u16 sel, old_cs;
@@ -2622,12 +2645,75 @@ static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
+static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
+{
+        u64 pmc;
+
+        if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
+                return emulate_gp(ctxt, 0);
+        ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
+        ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
+        return X86EMUL_CONTINUE;
+}
+
 static int em_mov(struct x86_emulate_ctxt *ctxt)
 {
         ctxt->dst.val = ctxt->src.val;
         return X86EMUL_CONTINUE;
 }
 
+static int em_cr_write(struct x86_emulate_ctxt *ctxt)
+{
+        if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
+                return emulate_gp(ctxt, 0);
+
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        return X86EMUL_CONTINUE;
+}
+
+static int em_dr_write(struct x86_emulate_ctxt *ctxt)
+{
+        unsigned long val;
+
+        if (ctxt->mode == X86EMUL_MODE_PROT64)
+                val = ctxt->src.val & ~0ULL;
+        else
+                val = ctxt->src.val & ~0U;
+
+        /* #UD condition is already handled. */
+        if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
+                return emulate_gp(ctxt, 0);
+
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        return X86EMUL_CONTINUE;
+}
+
+static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
+{
+        u64 msr_data;
+
+        msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
+                | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
+        if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
+                return emulate_gp(ctxt, 0);
+
+        return X86EMUL_CONTINUE;
+}
+
+static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
+{
+        u64 msr_data;
+
+        if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
+                return emulate_gp(ctxt, 0);
+
+        ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
+        ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
+        return X86EMUL_CONTINUE;
+}
+
 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
 {
         if (ctxt->modrm_reg > VCPU_SREG_GS)
@@ -2775,6 +2861,24 @@ static int em_jcxz(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
+static int em_in(struct x86_emulate_ctxt *ctxt)
+{
+        if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
+                             &ctxt->dst.val))
+                return X86EMUL_IO_NEEDED;
+
+        return X86EMUL_CONTINUE;
+}
+
+static int em_out(struct x86_emulate_ctxt *ctxt)
+{
+        ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
+                                    &ctxt->src.val, 1);
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        return X86EMUL_CONTINUE;
+}
+
 static int em_cli(struct x86_emulate_ctxt *ctxt)
 {
         if (emulator_bad_iopl(ctxt))
@@ -2794,6 +2898,69 @@ static int em_sti(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
+static int em_bt(struct x86_emulate_ctxt *ctxt)
+{
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        /* only subword offset */
+        ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
+
+        emulate_2op_SrcV_nobyte(ctxt, "bt");
+        return X86EMUL_CONTINUE;
+}
+
+static int em_bts(struct x86_emulate_ctxt *ctxt)
+{
+        emulate_2op_SrcV_nobyte(ctxt, "bts");
+        return X86EMUL_CONTINUE;
+}
+
+static int em_btr(struct x86_emulate_ctxt *ctxt)
+{
+        emulate_2op_SrcV_nobyte(ctxt, "btr");
+        return X86EMUL_CONTINUE;
+}
+
+static int em_btc(struct x86_emulate_ctxt *ctxt)
+{
+        emulate_2op_SrcV_nobyte(ctxt, "btc");
+        return X86EMUL_CONTINUE;
+}
+
+static int em_bsf(struct x86_emulate_ctxt *ctxt)
+{
+        u8 zf;
+
+        __asm__ ("bsf %2, %0; setz %1"
+                 : "=r"(ctxt->dst.val), "=q"(zf)
+                 : "r"(ctxt->src.val));
+
+        ctxt->eflags &= ~X86_EFLAGS_ZF;
+        if (zf) {
+                ctxt->eflags |= X86_EFLAGS_ZF;
+                /* Disable writeback. */
+                ctxt->dst.type = OP_NONE;
+        }
+        return X86EMUL_CONTINUE;
+}
+
+static int em_bsr(struct x86_emulate_ctxt *ctxt)
+{
+        u8 zf;
+
+        __asm__ ("bsr %2, %0; setz %1"
+                 : "=r"(ctxt->dst.val), "=q"(zf)
+                 : "r"(ctxt->src.val));
+
+        ctxt->eflags &= ~X86_EFLAGS_ZF;
+        if (zf) {
+                ctxt->eflags |= X86_EFLAGS_ZF;
+                /* Disable writeback. */
+                ctxt->dst.type = OP_NONE;
+        }
+        return X86EMUL_CONTINUE;
+}
+
 static bool valid_cr(int nr)
 {
         switch (nr) {
@@ -2867,9 +3034,6 @@ static int check_cr_write(struct x86_emulate_ctxt *ctxt)
                 break;
                 }
         case 4: {
-                u64 cr4;
-
-                cr4 = ctxt->ops->get_cr(ctxt, 4);
                 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
 
                 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
@@ -3003,6 +3167,8 @@ static int check_perm_out(struct x86_emulate_ctxt *ctxt)
 #define D2bv(_f)      D((_f) | ByteOp), D(_f)
 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
 #define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
+#define I2bvIP(_f, _e, _i, _p) \
+        IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
 
 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e),         \
                 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),     \
@@ -3033,17 +3199,17 @@ static struct opcode group7_rm7[] = {
 
 static struct opcode group1[] = {
         I(Lock, em_add),
-        I(Lock, em_or),
+        I(Lock | PageTable, em_or),
         I(Lock, em_adc),
         I(Lock, em_sbb),
-        I(Lock, em_and),
+        I(Lock | PageTable, em_and),
         I(Lock, em_sub),
         I(Lock, em_xor),
         I(0, em_cmp),
 };
 
 static struct opcode group1A[] = {
-        D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
+        I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N,
 };
 
 static struct opcode group3[] = {
@@ -3058,16 +3224,19 @@ static struct opcode group3[] = {
 };
 
 static struct opcode group4[] = {
-        D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
+        I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
+        I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
         N, N, N, N, N, N,
 };
 
 static struct opcode group5[] = {
-        D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
-        D(SrcMem | ModRM | Stack),
+        I(DstMem | SrcNone | ModRM | Lock, em_grp45),
+        I(DstMem | SrcNone | ModRM | Lock, em_grp45),
+        I(SrcMem | ModRM | Stack, em_grp45),
         I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
-        D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
-        D(SrcMem | ModRM | Stack), N,
+        I(SrcMem | ModRM | Stack, em_grp45),
+        I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45),
+        I(SrcMem | ModRM | Stack, em_grp45), N,
 };
 
 static struct opcode group6[] = {
@@ -3096,18 +3265,21 @@ static struct group_dual group7 = { {
 
 static struct opcode group8[] = {
         N, N, N, N,
-        D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
-        D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
+        I(DstMem | SrcImmByte | ModRM, em_bt),
+        I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts),
+        I(DstMem | SrcImmByte | ModRM | Lock, em_btr),
+        I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc),
 };
 
 static struct group_dual group9 = { {
-        N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
+        N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
 }, {
         N, N, N, N, N, N, N, N,
 } };
 
 static struct opcode group11[] = {
-        I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
+        I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov),
+        X7(D(Undefined)),
 };
 
 static struct gprefix pfx_0f_6f_0f_7f = {
@@ -3120,7 +3292,7 @@ static struct opcode opcode_table[256] = {
         I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
         I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
         /* 0x08 - 0x0F */
-        I6ALU(Lock, em_or),
+        I6ALU(Lock | PageTable, em_or),
         I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
         N,
         /* 0x10 - 0x17 */
@@ -3132,7 +3304,7 @@ static struct opcode opcode_table[256] = {
         I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
         I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
         /* 0x20 - 0x27 */
-        I6ALU(Lock, em_and), N, N,
+        I6ALU(Lock | PageTable, em_and), N, N,
         /* 0x28 - 0x2F */
         I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
         /* 0x30 - 0x37 */
@@ -3155,8 +3327,8 @@ static struct opcode opcode_table[256] = {
         I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
         I(SrcImmByte | Mov | Stack, em_push),
         I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
-        D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
-        D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
+        I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
+        I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
         /* 0x70 - 0x7F */
         X16(D(SrcImmByte)),
         /* 0x80 - 0x87 */
@@ -3165,11 +3337,11 @@ static struct opcode opcode_table[256] = {
         G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
         G(DstMem | SrcImmByte | ModRM | Group, group1),
         I2bv(DstMem | SrcReg | ModRM, em_test),
-        I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
+        I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
         /* 0x88 - 0x8F */
-        I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
+        I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
         I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
-        I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
+        I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
         D(ModRM | SrcMem | NoAccess | DstReg),
         I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
         G(0, group1A),
@@ -3182,7 +3354,7 @@ static struct opcode opcode_table[256] = {
         II(ImplicitOps | Stack, em_popf, popf), N, N,
         /* 0xA0 - 0xA7 */
         I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
-        I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
+        I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
         I2bv(SrcSI | DstDI | Mov | String, em_mov),
         I2bv(SrcSI | DstDI | String, em_cmp),
         /* 0xA8 - 0xAF */
@@ -3213,13 +3385,13 @@ static struct opcode opcode_table[256] = {
         /* 0xE0 - 0xE7 */
         X3(I(SrcImmByte, em_loop)),
         I(SrcImmByte, em_jcxz),
-        D2bvIP(SrcImmUByte | DstAcc, in,  check_perm_in),
-        D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
+        I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
+        I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
         /* 0xE8 - 0xEF */
-        D(SrcImm | Stack), D(SrcImm | ImplicitOps),
+        I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
         I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
-        D2bvIP(SrcDX | DstAcc, in,  check_perm_in),
-        D2bvIP(SrcAcc | DstDX, out, check_perm_out),
+        I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
+        I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
         /* 0xF0 - 0xF7 */
         N, DI(ImplicitOps, icebp), N, N,
         DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
@@ -3242,15 +3414,15 @@ static struct opcode twobyte_table[256] = {
         /* 0x20 - 0x2F */
         DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
         DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
-        DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
-        DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
+        IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
+        IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
         N, N, N, N,
         N, N, N, N, N, N, N, N,
         /* 0x30 - 0x3F */
-        DI(ImplicitOps | Priv, wrmsr),
+        II(ImplicitOps | Priv, em_wrmsr, wrmsr),
         IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
-        DI(ImplicitOps | Priv, rdmsr),
-        DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
+        II(ImplicitOps | Priv, em_rdmsr, rdmsr),
+        IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
         I(ImplicitOps | VendorSpecific, em_sysenter),
         I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
         N, N,
@@ -3275,26 +3447,28 @@ static struct opcode twobyte_table[256] = {
         X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
         /* 0xA0 - 0xA7 */
         I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
-        DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
+        DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
         D(DstMem | SrcReg | Src2ImmByte | ModRM),
         D(DstMem | SrcReg | Src2CL | ModRM), N, N,
         /* 0xA8 - 0xAF */
         I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
-        DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
+        DI(ImplicitOps, rsm),
+        I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
         D(DstMem | SrcReg | Src2ImmByte | ModRM),
         D(DstMem | SrcReg | Src2CL | ModRM),
         D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
         /* 0xB0 - 0xB7 */
-        D2bv(DstMem | SrcReg | ModRM | Lock),
+        I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
         I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
-        D(DstMem | SrcReg | ModRM | BitOp | Lock),
+        I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
         I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
         I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
         D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
         /* 0xB8 - 0xBF */
         N, N,
-        G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
-        D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
+        G(BitOp, group8),
+        I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
+        I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
         D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
         /* 0xC0 - 0xCF */
         D2bv(DstMem | SrcReg | ModRM | Lock),
@@ -3320,6 +3494,7 @@ static struct opcode twobyte_table[256] = {
 #undef D2bv
 #undef D2bvIP
 #undef I2bv
+#undef I2bvIP
 #undef I6ALU
 
 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
@@ -3697,6 +3872,11 @@ done:
         return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
 }
 
+bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
+{
+        return ctxt->d & PageTable;
+}
+
 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
 {
         /* The second termination condition only applies for REPE
@@ -3720,7 +3900,6 @@ static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
 {
         struct x86_emulate_ops *ops = ctxt->ops;
-        u64 msr_data;
         int rc = X86EMUL_CONTINUE;
         int saved_dst_type = ctxt->dst.type;
 
@@ -3854,15 +4033,6 @@ special_insn:
                         goto cannot_emulate;
                 ctxt->dst.val = (s32) ctxt->src.val;
                 break;
-        case 0x6c:              /* insb */
-        case 0x6d:              /* insw/insd */
-                ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
-                goto do_io_in;
-        case 0x6e:              /* outsb */
-        case 0x6f:              /* outsw/outsd */
-                ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
-                goto do_io_out;
-                break;
         case 0x70 ... 0x7f: /* jcc (short) */
                 if (test_cc(ctxt->b, ctxt->eflags))
                         jmp_rel(ctxt, ctxt->src.val);
@@ -3870,9 +4040,6 @@ special_insn:
         case 0x8d: /* lea r16/r32, m */
                 ctxt->dst.val = ctxt->src.addr.mem.ea;
                 break;
-        case 0x8f:              /* pop (sole member of Grp1a) */
-                rc = em_grp1a(ctxt);
-                break;
         case 0x90 ... 0x97: /* nop / xchg reg, rax */
                 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
                         break;
@@ -3905,38 +4072,11 @@ special_insn:
                 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
                 rc = em_grp2(ctxt);
                 break;
-        case 0xe4:      /* inb */
-        case 0xe5:      /* in */
-                goto do_io_in;
-        case 0xe6: /* outb */
-        case 0xe7: /* out */
-                goto do_io_out;
-        case 0xe8: /* call (near) */ {
-                long int rel = ctxt->src.val;
-                ctxt->src.val = (unsigned long) ctxt->_eip;
-                jmp_rel(ctxt, rel);
-                rc = em_push(ctxt);
-                break;
-        }
         case 0xe9: /* jmp rel */
         case 0xeb: /* jmp rel short */
                 jmp_rel(ctxt, ctxt->src.val);
                 ctxt->dst.type = OP_NONE; /* Disable writeback. */
                 break;
-        case 0xec: /* in al,dx */
-        case 0xed: /* in (e/r)ax,dx */
-        do_io_in:
-                if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
-                                     &ctxt->dst.val))
-                        goto done; /* IO is needed */
-                break;
-        case 0xee: /* out dx,al */
-        case 0xef: /* out dx,(e/r)ax */
-        do_io_out:
-                ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
-                                      &ctxt->src.val, 1);
-                ctxt->dst.type = OP_NONE;       /* Disable writeback. */
-                break;
         case 0xf4:              /* hlt */
                 ctxt->ops->halt(ctxt);
                 break;
@@ -3956,12 +4096,6 @@ special_insn:
         case 0xfd: /* std */
                 ctxt->eflags |= EFLG_DF;
                 break;
-        case 0xfe: /* Grp4 */
-                rc = em_grp45(ctxt);
-                break;
-        case 0xff: /* Grp5 */
-                rc = em_grp45(ctxt);
-                break;
         default:
                 goto cannot_emulate;
         }
@@ -4036,49 +4170,6 @@ twobyte_insn:
         case 0x21: /* mov from dr to reg */
                 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
                 break;
-        case 0x22: /* mov reg, cr */
-                if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
-                        emulate_gp(ctxt, 0);
-                        rc = X86EMUL_PROPAGATE_FAULT;
-                        goto done;
-                }
-                ctxt->dst.type = OP_NONE;
-                break;
-        case 0x23: /* mov from reg to dr */
-                if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
-                                ((ctxt->mode == X86EMUL_MODE_PROT64) ?
-                                 ~0ULL : ~0U)) < 0) {
-                        /* #UD condition is already handled by the code above */
-                        emulate_gp(ctxt, 0);
-                        rc = X86EMUL_PROPAGATE_FAULT;
-                        goto done;
-                }
-
-                ctxt->dst.type = OP_NONE;       /* no writeback */
-                break;
-        case 0x30:
-                /* wrmsr */
-                msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
-                        | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
-                if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
-                        emulate_gp(ctxt, 0);
-                        rc = X86EMUL_PROPAGATE_FAULT;
-                        goto done;
-                }
-                rc = X86EMUL_CONTINUE;
-                break;
-        case 0x32:
-                /* rdmsr */
-                if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
-                        emulate_gp(ctxt, 0);
-                        rc = X86EMUL_PROPAGATE_FAULT;
-                        goto done;
-                } else {
-                        ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
-                        ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
-                }
-                rc = X86EMUL_CONTINUE;
-                break;
         case 0x40 ... 0x4f:     /* cmov */
                 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
                 if (!test_cc(ctxt->b, ctxt->eflags))
@@ -4091,93 +4182,21 @@ twobyte_insn:
         case 0x90 ... 0x9f:     /* setcc r/m8 */
                 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
                 break;
-        case 0xa3:
-              bt:               /* bt */
-                ctxt->dst.type = OP_NONE;
-                /* only subword offset */
-                ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
-                emulate_2op_SrcV_nobyte(ctxt, "bt");
-                break;
         case 0xa4: /* shld imm8, r, r/m */
         case 0xa5: /* shld cl, r, r/m */
                 emulate_2op_cl(ctxt, "shld");
                 break;
-        case 0xab:
-              bts:              /* bts */
-                emulate_2op_SrcV_nobyte(ctxt, "bts");
-                break;
         case 0xac: /* shrd imm8, r, r/m */
         case 0xad: /* shrd cl, r, r/m */
                 emulate_2op_cl(ctxt, "shrd");
                 break;
         case 0xae:              /* clflush */
                 break;
-        case 0xb0 ... 0xb1:     /* cmpxchg */
-                /*
-                 * Save real source value, then compare EAX against
-                 * destination.
-                 */
-                ctxt->src.orig_val = ctxt->src.val;
-                ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
-                emulate_2op_SrcV(ctxt, "cmp");
-                if (ctxt->eflags & EFLG_ZF) {
-                        /* Success: write back to memory. */
-                        ctxt->dst.val = ctxt->src.orig_val;
-                } else {
-                        /* Failure: write the value we saw to EAX. */
-                        ctxt->dst.type = OP_REG;
-                        ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
-                }
-                break;
-        case 0xb3:
-              btr:              /* btr */
-                emulate_2op_SrcV_nobyte(ctxt, "btr");
-                break;
         case 0xb6 ... 0xb7:     /* movzx */
                 ctxt->dst.bytes = ctxt->op_bytes;
                 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
                                                        : (u16) ctxt->src.val;
                 break;
-        case 0xba:              /* Grp8 */
-                switch (ctxt->modrm_reg & 3) {
-                case 0:
-                        goto bt;
-                case 1:
-                        goto bts;
-                case 2:
-                        goto btr;
-                case 3:
-                        goto btc;
-                }
-                break;
-        case 0xbb:
-              btc:              /* btc */
-                emulate_2op_SrcV_nobyte(ctxt, "btc");
-                break;
-        case 0xbc: {            /* bsf */
-                u8 zf;
-                __asm__ ("bsf %2, %0; setz %1"
-                         : "=r"(ctxt->dst.val), "=q"(zf)
-                         : "r"(ctxt->src.val));
-                ctxt->eflags &= ~X86_EFLAGS_ZF;
-                if (zf) {
-                        ctxt->eflags |= X86_EFLAGS_ZF;
-                        ctxt->dst.type = OP_NONE;       /* Disable writeback. */
-                }
-                break;
-        }
-        case 0xbd: {            /* bsr */
-                u8 zf;
-                __asm__ ("bsr %2, %0; setz %1"
-                         : "=r"(ctxt->dst.val), "=q"(zf)
-                         : "r"(ctxt->src.val));
-                ctxt->eflags &= ~X86_EFLAGS_ZF;
-                if (zf) {
-                        ctxt->eflags |= X86_EFLAGS_ZF;
-                        ctxt->dst.type = OP_NONE;       /* Disable writeback. */
-                }
-                break;
-        }
         case 0xbe ... 0xbf:     /* movsx */
                 ctxt->dst.bytes = ctxt->op_bytes;
                 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
@@ -4194,9 +4213,6 @@ twobyte_insn:
                 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
                                                         (u64) ctxt->src.val;
                 break;
-        case 0xc7:              /* Grp9 (cmpxchg8b) */
-                rc = em_grp9(ctxt);
-                break;
         default:
                 goto cannot_emulate;
         }
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 405f2620392..d68f99df690 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -344,7 +344,7 @@ static void create_pit_timer(struct kvm *kvm, u32 val, int is_period)
         struct kvm_timer *pt = &ps->pit_timer;
         s64 interval;
 
-        if (!irqchip_in_kernel(kvm))
+        if (!irqchip_in_kernel(kvm) || ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)
                 return;
 
         interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
@@ -397,15 +397,11 @@ static void pit_load_count(struct kvm *kvm, int channel, u32 val)
         case 1:
         /* FIXME: enhance mode 4 precision */
         case 4:
-                if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)) {
-                        create_pit_timer(kvm, val, 0);
-                }
+                create_pit_timer(kvm, val, 0);
                 break;
         case 2:
         case 3:
-                if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)){
-                        create_pit_timer(kvm, val, 1);
-                }
+                create_pit_timer(kvm, val, 1);
                 break;
         default:
                 destroy_pit_timer(kvm->arch.vpit);
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index cac4746d7ff..b6a73537e1e 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -262,9 +262,10 @@ int kvm_pic_read_irq(struct kvm *kvm)
 
 void kvm_pic_reset(struct kvm_kpic_state *s)
 {
-        int irq;
-        struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
+        int irq, i;
+        struct kvm_vcpu *vcpu;
         u8 irr = s->irr, isr = s->imr;
+        bool found = false;
 
         s->last_irr = 0;
         s->irr = 0;
@@ -281,12 +282,19 @@ void kvm_pic_reset(struct kvm_kpic_state *s)
         s->special_fully_nested_mode = 0;
         s->init4 = 0;
 
-        for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
-                if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
-                        if (irr & (1 << irq) || isr & (1 << irq)) {
-                                pic_clear_isr(s, irq);
-                        }
-        }
+        kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
+                if (kvm_apic_accept_pic_intr(vcpu)) {
+                        found = true;
+                        break;
+                }
+
+
+        if (!found)
+                return;
+
+        for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
+                if (irr & (1 << irq) || isr & (1 << irq))
+                        pic_clear_isr(s, irq);
 }
 
 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 54abb40199d..cfdc6e0ef00 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -38,6 +38,7 @@
 #include "irq.h"
 #include "trace.h"
 #include "x86.h"
+#include "cpuid.h"
 
 #ifndef CONFIG_X86_64
 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
@@ -1120,7 +1121,7 @@ int apic_has_pending_timer(struct kvm_vcpu *vcpu)
         return 0;
 }
 
-static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
+int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 {
         u32 reg = apic_get_reg(apic, lvt_type);
         int vector, mode, trig_mode;
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 138e8cc6fea..6f4ce2575d0 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -34,6 +34,7 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu);
 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
+int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
 
 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index f1b36cf3e3d..2a2a9b40db1 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -59,15 +59,6 @@ enum {
         AUDIT_POST_SYNC
 };
 
-char *audit_point_name[] = {
-        "pre page fault",
-        "post page fault",
-        "pre pte write",
-        "post pte write",
-        "pre sync",
-        "post sync"
-};
-
 #undef MMU_DEBUG
 
 #ifdef MMU_DEBUG
@@ -87,9 +78,6 @@ static int dbg = 0;
 module_param(dbg, bool, 0644);
 #endif
 
-static int oos_shadow = 1;
-module_param(oos_shadow, bool, 0644);
-
 #ifndef MMU_DEBUG
 #define ASSERT(x) do { } while (0)
 #else
@@ -593,6 +581,11 @@ static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
         return 0;
 }
 
+static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
+{
+        return cache->nobjs;
+}
+
 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
                                   struct kmem_cache *cache)
 {
@@ -953,21 +946,35 @@ static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
         }
 }
 
+static unsigned long *__gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level,
+                                    struct kvm_memory_slot *slot)
+{
+        struct kvm_lpage_info *linfo;
+
+        if (likely(level == PT_PAGE_TABLE_LEVEL))
+                return &slot->rmap[gfn - slot->base_gfn];
+
+        linfo = lpage_info_slot(gfn, slot, level);
+        return &linfo->rmap_pde;
+}
+
 /*
  * Take gfn and return the reverse mapping to it.
  */
 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
 {
         struct kvm_memory_slot *slot;
-        struct kvm_lpage_info *linfo;
 
         slot = gfn_to_memslot(kvm, gfn);
-        if (likely(level == PT_PAGE_TABLE_LEVEL))
-                return &slot->rmap[gfn - slot->base_gfn];
+        return __gfn_to_rmap(kvm, gfn, level, slot);
+}
 
-        linfo = lpage_info_slot(gfn, slot, level);
+static bool rmap_can_add(struct kvm_vcpu *vcpu)
+{
+        struct kvm_mmu_memory_cache *cache;
 
-        return &linfo->rmap_pde;
+        cache = &vcpu->arch.mmu_pte_list_desc_cache;
+        return mmu_memory_cache_free_objects(cache);
 }
 
 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
@@ -1004,17 +1011,16 @@ static void drop_spte(struct kvm *kvm, u64 *sptep)
                 rmap_remove(kvm, sptep);
 }
 
-static int rmap_write_protect(struct kvm *kvm, u64 gfn)
+int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
+                               struct kvm_memory_slot *slot)
 {
         unsigned long *rmapp;
         u64 *spte;
         int i, write_protected = 0;
 
-        rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
-
+        rmapp = __gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL, slot);
         spte = rmap_next(kvm, rmapp, NULL);
         while (spte) {
-                BUG_ON(!spte);
                 BUG_ON(!(*spte & PT_PRESENT_MASK));
                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
                 if (is_writable_pte(*spte)) {
@@ -1027,12 +1033,11 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
         /* check for huge page mappings */
         for (i = PT_DIRECTORY_LEVEL;
              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
-                rmapp = gfn_to_rmap(kvm, gfn, i);
+                rmapp = __gfn_to_rmap(kvm, gfn, i, slot);
                 spte = rmap_next(kvm, rmapp, NULL);
                 while (spte) {
-                        BUG_ON(!spte);
                         BUG_ON(!(*spte & PT_PRESENT_MASK));
-                        BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
+                        BUG_ON(!is_large_pte(*spte));
                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
                         if (is_writable_pte(*spte)) {
                                 drop_spte(kvm, spte);
@@ -1047,6 +1052,14 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
         return write_protected;
 }
 
+static int rmap_write_protect(struct kvm *kvm, u64 gfn)
+{
+        struct kvm_memory_slot *slot;
+
+        slot = gfn_to_memslot(kvm, gfn);
+        return kvm_mmu_rmap_write_protect(kvm, gfn, slot);
+}
+
 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
                            unsigned long data)
 {
@@ -1103,15 +1116,15 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
                                          unsigned long data))
 {
-        int i, j;
+        int j;
         int ret;
         int retval = 0;
         struct kvm_memslots *slots;
+        struct kvm_memory_slot *memslot;
 
         slots = kvm_memslots(kvm);
 
-        for (i = 0; i < slots->nmemslots; i++) {
-                struct kvm_memory_slot *memslot = &slots->memslots[i];
+        kvm_for_each_memslot(memslot, slots) {
                 unsigned long start = memslot->userspace_addr;
                 unsigned long end;
 
@@ -1324,7 +1337,7 @@ static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
                                                   PAGE_SIZE);
         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
-        bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
+        bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
         sp->parent_ptes = 0;
         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
@@ -1511,6 +1524,13 @@ static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
         return ret;
 }
 
+#ifdef CONFIG_KVM_MMU_AUDIT
+#include "mmu_audit.c"
+#else
+static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
+static void mmu_audit_disable(void) { }
+#endif
+
 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
                          struct list_head *invalid_list)
 {
@@ -1640,6 +1660,18 @@ static void init_shadow_page_table(struct kvm_mmu_page *sp)
                 sp->spt[i] = 0ull;
 }
 
+static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
+{
+        sp->write_flooding_count = 0;
+}
+
+static void clear_sp_write_flooding_count(u64 *spte)
+{
+        struct kvm_mmu_page *sp =  page_header(__pa(spte));
+
+        __clear_sp_write_flooding_count(sp);
+}
+
 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                                              gfn_t gfn,
                                              gva_t gaddr,
@@ -1683,6 +1715,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                 } else if (sp->unsync)
                         kvm_mmu_mark_parents_unsync(sp);
 
+                __clear_sp_write_flooding_count(sp);
                 trace_kvm_mmu_get_page(sp, false);
                 return sp;
         }
@@ -1796,7 +1829,7 @@ static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         }
 }
 
-static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
+static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
                              u64 *spte)
 {
         u64 pte;
@@ -1804,17 +1837,21 @@ static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
 
         pte = *spte;
         if (is_shadow_present_pte(pte)) {
-                if (is_last_spte(pte, sp->role.level))
+                if (is_last_spte(pte, sp->role.level)) {
                         drop_spte(kvm, spte);
-                else {
+                        if (is_large_pte(pte))
+                                --kvm->stat.lpages;
+                } else {
                         child = page_header(pte & PT64_BASE_ADDR_MASK);
                         drop_parent_pte(child, spte);
                 }
-        } else if (is_mmio_spte(pte))
+                return true;
+        }
+
+        if (is_mmio_spte(pte))
                 mmu_spte_clear_no_track(spte);
 
-        if (is_large_pte(pte))
-                --kvm->stat.lpages;
+        return false;
 }
 
 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
@@ -1831,15 +1868,6 @@ static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
         mmu_page_remove_parent_pte(sp, parent_pte);
 }
 
-static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
-{
-        int i;
-        struct kvm_vcpu *vcpu;
-
-        kvm_for_each_vcpu(i, vcpu, kvm)
-                vcpu->arch.last_pte_updated = NULL;
-}
-
 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
 {
         u64 *parent_pte;
@@ -1899,7 +1927,6 @@ static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
         }
 
         sp->role.invalid = 1;
-        kvm_mmu_reset_last_pte_updated(kvm);
         return ret;
 }
 
@@ -1985,7 +2012,7 @@ void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
 }
 
-static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
+int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
 {
         struct kvm_mmu_page *sp;
         struct hlist_node *node;
@@ -1994,7 +2021,7 @@ static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
 
         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
         r = 0;
-
+        spin_lock(&kvm->mmu_lock);
         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
                          sp->role.word);
@@ -2002,22 +2029,11 @@ static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
         }
         kvm_mmu_commit_zap_page(kvm, &invalid_list);
-        return r;
-}
-
-static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
-{
-        struct kvm_mmu_page *sp;
-        struct hlist_node *node;
-        LIST_HEAD(invalid_list);
+        spin_unlock(&kvm->mmu_lock);
 
-        for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
-                pgprintk("%s: zap %llx %x\n",
-                         __func__, gfn, sp->role.word);
-                kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
-        }
-        kvm_mmu_commit_zap_page(kvm, &invalid_list);
+        return r;
 }
+EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
 
 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
 {
@@ -2169,8 +2185,6 @@ static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
                         return 1;
 
                 if (!need_unsync && !s->unsync) {
-                        if (!oos_shadow)
-                                return 1;
                         need_unsync = true;
                 }
         }
@@ -2191,11 +2205,6 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
                 return 0;
 
-        /*
-         * We don't set the accessed bit, since we sometimes want to see
-         * whether the guest actually used the pte (in order to detect
-         * demand paging).
-         */
         spte = PT_PRESENT_MASK;
         if (!speculative)
                 spte |= shadow_accessed_mask;
@@ -2346,10 +2355,6 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                 }
         }
         kvm_release_pfn_clean(pfn);
-        if (speculative) {
-                vcpu->arch.last_pte_updated = sptep;
-                vcpu->arch.last_pte_gfn = gfn;
-        }
 }
 
 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
@@ -2840,12 +2845,12 @@ static void mmu_sync_roots(struct kvm_vcpu *vcpu)
                 return;
 
         vcpu_clear_mmio_info(vcpu, ~0ul);
-        trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
+        kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
                 hpa_t root = vcpu->arch.mmu.root_hpa;
                 sp = page_header(root);
                 mmu_sync_children(vcpu, sp);
-                trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
+                kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
                 return;
         }
         for (i = 0; i < 4; ++i) {
@@ -2857,7 +2862,7 @@ static void mmu_sync_roots(struct kvm_vcpu *vcpu)
                         mmu_sync_children(vcpu, sp);
                 }
         }
-        trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
+        kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
 }
 
 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
@@ -3510,28 +3515,119 @@ static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
                 kvm_mmu_flush_tlb(vcpu);
 }
 
-static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
+static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
+                                    const u8 *new, int *bytes)
 {
-        u64 *spte = vcpu->arch.last_pte_updated;
+        u64 gentry;
+        int r;
+
+        /*
+         * Assume that the pte write on a page table of the same type
+         * as the current vcpu paging mode since we update the sptes only
+         * when they have the same mode.
+         */
+        if (is_pae(vcpu) && *bytes == 4) {
+                /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
+                *gpa &= ~(gpa_t)7;
+                *bytes = 8;
+                r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
+                if (r)
+                        gentry = 0;
+                new = (const u8 *)&gentry;
+        }
 
-        return !!(spte && (*spte & shadow_accessed_mask));
+        switch (*bytes) {
+        case 4:
+                gentry = *(const u32 *)new;
+                break;
+        case 8:
+                gentry = *(const u64 *)new;
+                break;
+        default:
+                gentry = 0;
+                break;
+        }
+
+        return gentry;
 }
 
-static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
+/*
+ * If we're seeing too many writes to a page, it may no longer be a page table,
+ * or we may be forking, in which case it is better to unmap the page.
+ */
+static bool detect_write_flooding(struct kvm_mmu_page *sp, u64 *spte)
 {
-        u64 *spte = vcpu->arch.last_pte_updated;
+        /*
+         * Skip write-flooding detected for the sp whose level is 1, because
+         * it can become unsync, then the guest page is not write-protected.
+         */
+        if (sp->role.level == 1)
+                return false;
 
-        if (spte
-            && vcpu->arch.last_pte_gfn == gfn
-            && shadow_accessed_mask
-            && !(*spte & shadow_accessed_mask)
-            && is_shadow_present_pte(*spte))
-                set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
+        return ++sp->write_flooding_count >= 3;
+}
+
+/*
+ * Misaligned accesses are too much trouble to fix up; also, they usually
+ * indicate a page is not used as a page table.
+ */
+static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
+                                    int bytes)
+{
+        unsigned offset, pte_size, misaligned;
+
+        pgprintk("misaligned: gpa %llx bytes %d role %x\n",
+                 gpa, bytes, sp->role.word);
+
+        offset = offset_in_page(gpa);
+        pte_size = sp->role.cr4_pae ? 8 : 4;
+
+        /*
+         * Sometimes, the OS only writes the last one bytes to update status
+         * bits, for example, in linux, andb instruction is used in clear_bit().
+         */
+        if (!(offset & (pte_size - 1)) && bytes == 1)
+                return false;
+
+        misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
+        misaligned |= bytes < 4;
+
+        return misaligned;
+}
+
+static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
+{
+        unsigned page_offset, quadrant;
+        u64 *spte;
+        int level;
+
+        page_offset = offset_in_page(gpa);
+        level = sp->role.level;
+        *nspte = 1;
+        if (!sp->role.cr4_pae) {
+                page_offset <<= 1;      /* 32->64 */
+                /*
+                 * A 32-bit pde maps 4MB while the shadow pdes map
+                 * only 2MB.  So we need to double the offset again
+                 * and zap two pdes instead of one.
+                 */
+                if (level == PT32_ROOT_LEVEL) {
+                        page_offset &= ~7; /* kill rounding error */
+                        page_offset <<= 1;
+                        *nspte = 2;
+                }
+                quadrant = page_offset >> PAGE_SHIFT;
+                page_offset &= ~PAGE_MASK;
+                if (quadrant != sp->role.quadrant)
+                        return NULL;
+        }
+
+        spte = &sp->spt[page_offset / sizeof(*spte)];
+        return spte;
 }
 
 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
-                       const u8 *new, int bytes,
-                       bool guest_initiated)
+                       const u8 *new, int bytes)
 {
         gfn_t gfn = gpa >> PAGE_SHIFT;
         union kvm_mmu_page_role mask = { .word = 0 };
@@ -3539,8 +3635,7 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
         struct hlist_node *node;
         LIST_HEAD(invalid_list);
         u64 entry, gentry, *spte;
-        unsigned pte_size, page_offset, misaligned, quadrant, offset;
-        int level, npte, invlpg_counter, r, flooded = 0;
+        int npte;
         bool remote_flush, local_flush, zap_page;
 
         /*
@@ -3551,112 +3646,45 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
                 return;
 
         zap_page = remote_flush = local_flush = false;
-        offset = offset_in_page(gpa);
 
         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
 
-        invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
+        gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
 
         /*
-         * Assume that the pte write on a page table of the same type
-         * as the current vcpu paging mode since we update the sptes only
-         * when they have the same mode.
+         * No need to care whether allocation memory is successful
+         * or not since pte prefetch is skiped if it does not have
+         * enough objects in the cache.
          */
-        if ((is_pae(vcpu) && bytes == 4) || !new) {
-                /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
-                if (is_pae(vcpu)) {
-                        gpa &= ~(gpa_t)7;
-                        bytes = 8;
-                }
-                r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
-                if (r)
-                        gentry = 0;
-                new = (const u8 *)&gentry;
-        }
-
-        switch (bytes) {
-        case 4:
-                gentry = *(const u32 *)new;
-                break;
-        case 8:
-                gentry = *(const u64 *)new;
-                break;
-        default:
-                gentry = 0;
-                break;
-        }
+        mmu_topup_memory_caches(vcpu);
 
         spin_lock(&vcpu->kvm->mmu_lock);
-        if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
-                gentry = 0;
-        kvm_mmu_free_some_pages(vcpu);
         ++vcpu->kvm->stat.mmu_pte_write;
-        trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
-        if (guest_initiated) {
-                kvm_mmu_access_page(vcpu, gfn);
-                if (gfn == vcpu->arch.last_pt_write_gfn
-                    && !last_updated_pte_accessed(vcpu)) {
-                        ++vcpu->arch.last_pt_write_count;
-                        if (vcpu->arch.last_pt_write_count >= 3)
-                                flooded = 1;
-                } else {
-                        vcpu->arch.last_pt_write_gfn = gfn;
-                        vcpu->arch.last_pt_write_count = 1;
-                        vcpu->arch.last_pte_updated = NULL;
-                }
-        }
+        kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
 
         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
-                pte_size = sp->role.cr4_pae ? 8 : 4;
-                misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
-                misaligned |= bytes < 4;
-                if (misaligned || flooded) {
-                        /*
-                         * Misaligned accesses are too much trouble to fix
-                         * up; also, they usually indicate a page is not used
-                         * as a page table.
-                         *
-                         * If we're seeing too many writes to a page,
-                         * it may no longer be a page table, or we may be
-                         * forking, in which case it is better to unmap the
-                         * page.
-                         */
-                        pgprintk("misaligned: gpa %llx bytes %d role %x\n",
-                                 gpa, bytes, sp->role.word);
+                spte = get_written_sptes(sp, gpa, &npte);
+
+                if (detect_write_misaligned(sp, gpa, bytes) ||
+                      detect_write_flooding(sp, spte)) {
                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
                                                      &invalid_list);
                         ++vcpu->kvm->stat.mmu_flooded;
                         continue;
                 }
-                page_offset = offset;
-                level = sp->role.level;
-                npte = 1;
-                if (!sp->role.cr4_pae) {
-                        page_offset <<= 1;      /* 32->64 */
-                        /*
-                         * A 32-bit pde maps 4MB while the shadow pdes map
-                         * only 2MB.  So we need to double the offset again
-                         * and zap two pdes instead of one.
-                         */
-                        if (level == PT32_ROOT_LEVEL) {
-                                page_offset &= ~7; /* kill rounding error */
-                                page_offset <<= 1;
-                                npte = 2;
-                        }
-                        quadrant = page_offset >> PAGE_SHIFT;
-                        page_offset &= ~PAGE_MASK;
-                        if (quadrant != sp->role.quadrant)
-                                continue;
-                }
+
+                spte = get_written_sptes(sp, gpa, &npte);
+                if (!spte)
+                        continue;
+
                 local_flush = true;
-                spte = &sp->spt[page_offset / sizeof(*spte)];
                 while (npte--) {
                         entry = *spte;
                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
                         if (gentry &&
                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
-                              & mask.word))
+                              & mask.word) && rmap_can_add(vcpu))
                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
                         if (!remote_flush && need_remote_flush(entry, *spte))
                                 remote_flush = true;
@@ -3665,7 +3693,7 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
         }
         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
-        trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
+        kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
         spin_unlock(&vcpu->kvm->mmu_lock);
 }
 
@@ -3679,9 +3707,8 @@ int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
 
         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
 
-        spin_lock(&vcpu->kvm->mmu_lock);
         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
-        spin_unlock(&vcpu->kvm->mmu_lock);
+
         return r;
 }
 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
@@ -3702,10 +3729,18 @@ void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
 }
 
+static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
+{
+        if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
+                return vcpu_match_mmio_gpa(vcpu, addr);
+
+        return vcpu_match_mmio_gva(vcpu, addr);
+}
+
 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
                        void *insn, int insn_len)
 {
-        int r;
+        int r, emulation_type = EMULTYPE_RETRY;
         enum emulation_result er;
 
         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
@@ -3717,11 +3752,10 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
                 goto out;
         }
 
-        r = mmu_topup_memory_caches(vcpu);
-        if (r)
-                goto out;
+        if (is_mmio_page_fault(vcpu, cr2))
+                emulation_type = 0;
 
-        er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
+        er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
 
         switch (er) {
         case EMULATE_DONE:
@@ -3792,7 +3826,11 @@ static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
 int kvm_mmu_create(struct kvm_vcpu *vcpu)
 {
         ASSERT(vcpu);
-        ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
+
+        vcpu->arch.walk_mmu = &vcpu->arch.mmu;
+        vcpu->arch.mmu.root_hpa = INVALID_PAGE;
+        vcpu->arch.mmu.translate_gpa = translate_gpa;
+        vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
 
         return alloc_mmu_pages(vcpu);
 }
@@ -3852,14 +3890,14 @@ restart:
         spin_unlock(&kvm->mmu_lock);
 }
 
-static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
-                                               struct list_head *invalid_list)
+static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
+                                                struct list_head *invalid_list)
 {
         struct kvm_mmu_page *page;
 
         page = container_of(kvm->arch.active_mmu_pages.prev,
                             struct kvm_mmu_page, link);
-        return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
+        kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
 }
 
 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
@@ -3874,15 +3912,15 @@ static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
         raw_spin_lock(&kvm_lock);
 
         list_for_each_entry(kvm, &vm_list, vm_list) {
-                int idx, freed_pages;
+                int idx;
                 LIST_HEAD(invalid_list);
 
                 idx = srcu_read_lock(&kvm->srcu);
                 spin_lock(&kvm->mmu_lock);
                 if (!kvm_freed && nr_to_scan > 0 &&
                     kvm->arch.n_used_mmu_pages > 0) {
-                        freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
-                                                          &invalid_list);
+                        kvm_mmu_remove_some_alloc_mmu_pages(kvm,
+                                                            &invalid_list);
                         kvm_freed = kvm;
                 }
                 nr_to_scan--;
@@ -3944,15 +3982,15 @@ nomem:
  */
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
 {
-        int i;
         unsigned int nr_mmu_pages;
         unsigned int  nr_pages = 0;
         struct kvm_memslots *slots;
+        struct kvm_memory_slot *memslot;
 
         slots = kvm_memslots(kvm);
 
-        for (i = 0; i < slots->nmemslots; i++)
-                nr_pages += slots->memslots[i].npages;
+        kvm_for_each_memslot(memslot, slots)
+                nr_pages += memslot->npages;
 
         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
         nr_mmu_pages = max(nr_mmu_pages,
@@ -3961,127 +3999,6 @@ unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
         return nr_mmu_pages;
 }
 
-static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
-                                unsigned len)
-{
-        if (len > buffer->len)
-                return NULL;
-        return buffer->ptr;
-}
-
-static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
-                                unsigned len)
-{
-        void *ret;
-
-        ret = pv_mmu_peek_buffer(buffer, len);
-        if (!ret)
-                return ret;
-        buffer->ptr += len;
-        buffer->len -= len;
-        buffer->processed += len;
-        return ret;
-}
-
-static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
-                             gpa_t addr, gpa_t value)
-{
-        int bytes = 8;
-        int r;
-
-        if (!is_long_mode(vcpu) && !is_pae(vcpu))
-                bytes = 4;
-
-        r = mmu_topup_memory_caches(vcpu);
-        if (r)
-                return r;
-
-        if (!emulator_write_phys(vcpu, addr, &value, bytes))
-                return -EFAULT;
-
-        return 1;
-}
-
-static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
-{
-        (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
-        return 1;
-}
-
-static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
-{
-        spin_lock(&vcpu->kvm->mmu_lock);
-        mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
-        spin_unlock(&vcpu->kvm->mmu_lock);
-        return 1;
-}
-
-static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
-                             struct kvm_pv_mmu_op_buffer *buffer)
-{
-        struct kvm_mmu_op_header *header;
-
-        header = pv_mmu_peek_buffer(buffer, sizeof *header);
-        if (!header)
-                return 0;
-        switch (header->op) {
-        case KVM_MMU_OP_WRITE_PTE: {
-                struct kvm_mmu_op_write_pte *wpte;
-
-                wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
-                if (!wpte)
-                        return 0;
-                return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
-                                        wpte->pte_val);
-        }
-        case KVM_MMU_OP_FLUSH_TLB: {
-                struct kvm_mmu_op_flush_tlb *ftlb;
-
-                ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
-                if (!ftlb)
-                        return 0;
-                return kvm_pv_mmu_flush_tlb(vcpu);
-        }
-        case KVM_MMU_OP_RELEASE_PT: {
-                struct kvm_mmu_op_release_pt *rpt;
-
-                rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
-                if (!rpt)
-                        return 0;
-                return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
-        }
-        default: return 0;
-        }
-}
-
-int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
-                  gpa_t addr, unsigned long *ret)
-{
-        int r;
-        struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
-
-        buffer->ptr = buffer->buf;
-        buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
-        buffer->processed = 0;
-
-        r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
-        if (r)
-                goto out;
-
-        while (buffer->len) {
-                r = kvm_pv_mmu_op_one(vcpu, buffer);
-                if (r < 0)
-                        goto out;
-                if (r == 0)
-                        break;
-        }
-
-        r = 1;
-out:
-        *ret = buffer->processed;
-        return r;
-}
-
 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
 {
         struct kvm_shadow_walk_iterator iterator;
@@ -4110,12 +4027,6 @@ void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
         mmu_free_memory_caches(vcpu);
 }
 
-#ifdef CONFIG_KVM_MMU_AUDIT
-#include "mmu_audit.c"
-#else
-static void mmu_audit_disable(void) { }
-#endif
-
 void kvm_mmu_module_exit(void)
 {
         mmu_destroy_caches();
diff --git a/arch/x86/kvm/mmu_audit.c b/arch/x86/kvm/mmu_audit.c
index 746ec259d02..fe15dcc07a6 100644
--- a/arch/x86/kvm/mmu_audit.c
+++ b/arch/x86/kvm/mmu_audit.c
@@ -19,6 +19,15 @@
 
 #include <linux/ratelimit.h>
 
+char const *audit_point_name[] = {
+        "pre page fault",
+        "post page fault",
+        "pre pte write",
+        "post pte write",
+        "pre sync",
+        "post sync"
+};
+
 #define audit_printk(kvm, fmt, args...)         \
         printk(KERN_ERR "audit: (%s) error: "   \
                 fmt, audit_point_name[kvm->arch.audit_point], ##args)
@@ -224,7 +233,10 @@ static void audit_vcpu_spte(struct kvm_vcpu *vcpu)
         mmu_spte_walk(vcpu, audit_spte);
 }
 
-static void kvm_mmu_audit(void *ignore, struct kvm_vcpu *vcpu, int point)
+static bool mmu_audit;
+static struct jump_label_key mmu_audit_key;
+
+static void __kvm_mmu_audit(struct kvm_vcpu *vcpu, int point)
 {
         static DEFINE_RATELIMIT_STATE(ratelimit_state, 5 * HZ, 10);
 
@@ -236,18 +248,18 @@ static void kvm_mmu_audit(void *ignore, struct kvm_vcpu *vcpu, int point)
         audit_vcpu_spte(vcpu);
 }
 
-static bool mmu_audit;
+static inline void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point)
+{
+        if (static_branch((&mmu_audit_key)))
+                __kvm_mmu_audit(vcpu, point);
+}
 
 static void mmu_audit_enable(void)
 {
-        int ret;
-
         if (mmu_audit)
                 return;
 
-        ret = register_trace_kvm_mmu_audit(kvm_mmu_audit, NULL);
-        WARN_ON(ret);
-
+        jump_label_inc(&mmu_audit_key);
         mmu_audit = true;
 }
 
@@ -256,8 +268,7 @@ static void mmu_audit_disable(void)
         if (!mmu_audit)
                 return;
 
-        unregister_trace_kvm_mmu_audit(kvm_mmu_audit, NULL);
-        tracepoint_synchronize_unregister();
+        jump_label_dec(&mmu_audit_key);
         mmu_audit = false;
 }
 
diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
index eed67f34146..89fb0e81322 100644
--- a/arch/x86/kvm/mmutrace.h
+++ b/arch/x86/kvm/mmutrace.h
@@ -243,25 +243,6 @@ TRACE_EVENT(
         TP_printk("addr:%llx gfn %llx access %x", __entry->addr, __entry->gfn,
                   __entry->access)
 );
-
-TRACE_EVENT(
-        kvm_mmu_audit,
-        TP_PROTO(struct kvm_vcpu *vcpu, int audit_point),
-        TP_ARGS(vcpu, audit_point),
-
-        TP_STRUCT__entry(
-                __field(struct kvm_vcpu *, vcpu)
-                __field(int, audit_point)
-        ),
-
-        TP_fast_assign(
-                __entry->vcpu = vcpu;
-                __entry->audit_point = audit_point;
-        ),
-
-        TP_printk("vcpu:%d %s", __entry->vcpu->cpu,
-                  audit_point_name[__entry->audit_point])
-);
 #endif /* _TRACE_KVMMMU_H */
 
 #undef TRACE_INCLUDE_PATH
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 92994100638..15610285ebb 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -497,6 +497,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
              shadow_walk_next(&it)) {
                 gfn_t table_gfn;
 
+                clear_sp_write_flooding_count(it.sptep);
                 drop_large_spte(vcpu, it.sptep);
 
                 sp = NULL;
@@ -522,6 +523,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
              shadow_walk_next(&it)) {
                 gfn_t direct_gfn;
 
+                clear_sp_write_flooding_count(it.sptep);
                 validate_direct_spte(vcpu, it.sptep, direct_access);
 
                 drop_large_spte(vcpu, it.sptep);
@@ -536,6 +538,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
                 link_shadow_page(it.sptep, sp);
         }
 
+        clear_sp_write_flooding_count(it.sptep);
         mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
                      user_fault, write_fault, emulate, it.level,
                      gw->gfn, pfn, prefault, map_writable);
@@ -599,11 +602,9 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
          */
         if (!r) {
                 pgprintk("%s: guest page fault\n", __func__);
-                if (!prefault) {
+                if (!prefault)
                         inject_page_fault(vcpu, &walker.fault);
-                        /* reset fork detector */
-                        vcpu->arch.last_pt_write_count = 0;
-                }
+
                 return 0;
         }
 
@@ -631,7 +632,7 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
         if (mmu_notifier_retry(vcpu, mmu_seq))
                 goto out_unlock;
 
-        trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
+        kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
         kvm_mmu_free_some_pages(vcpu);
         if (!force_pt_level)
                 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
@@ -641,11 +642,8 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
         pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__,
                  sptep, *sptep, emulate);
 
-        if (!emulate)
-                vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
-
         ++vcpu->stat.pf_fixed;
-        trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
+        kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
         spin_unlock(&vcpu->kvm->mmu_lock);
 
         return emulate;
@@ -656,65 +654,66 @@ out_unlock:
         return 0;
 }
 
+static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
+{
+        int offset = 0;
+
+        WARN_ON(sp->role.level != 1);
+
+        if (PTTYPE == 32)
+                offset = sp->role.quadrant << PT64_LEVEL_BITS;
+
+        return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
+}
+
 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 {
         struct kvm_shadow_walk_iterator iterator;
         struct kvm_mmu_page *sp;
-        gpa_t pte_gpa = -1;
         int level;
         u64 *sptep;
-        int need_flush = 0;
 
         vcpu_clear_mmio_info(vcpu, gva);
 
-        spin_lock(&vcpu->kvm->mmu_lock);
+        /*
+         * No need to check return value here, rmap_can_add() can
+         * help us to skip pte prefetch later.
+         */
+        mmu_topup_memory_caches(vcpu);
 
+        spin_lock(&vcpu->kvm->mmu_lock);
         for_each_shadow_entry(vcpu, gva, iterator) {
                 level = iterator.level;
                 sptep = iterator.sptep;
 
                 sp = page_header(__pa(sptep));
                 if (is_last_spte(*sptep, level)) {
-                        int offset, shift;
+                        pt_element_t gpte;
+                        gpa_t pte_gpa;
 
                         if (!sp->unsync)
                                 break;
 
-                        shift = PAGE_SHIFT -
-                                  (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
-                        offset = sp->role.quadrant << shift;
-
-                        pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
+                        pte_gpa = FNAME(get_level1_sp_gpa)(sp);
                         pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
 
-                        if (is_shadow_present_pte(*sptep)) {
-                                if (is_large_pte(*sptep))
-                                        --vcpu->kvm->stat.lpages;
-                                drop_spte(vcpu->kvm, sptep);
-                                need_flush = 1;
-                        } else if (is_mmio_spte(*sptep))
-                                mmu_spte_clear_no_track(sptep);
+                        if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
+                                kvm_flush_remote_tlbs(vcpu->kvm);
 
-                        break;
+                        if (!rmap_can_add(vcpu))
+                                break;
+
+                        if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
+                                                  sizeof(pt_element_t)))
+                                break;
+
+                        FNAME(update_pte)(vcpu, sp, sptep, &gpte);
                 }
 
                 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
                         break;
         }
-
-        if (need_flush)
-                kvm_flush_remote_tlbs(vcpu->kvm);
-
-        atomic_inc(&vcpu->kvm->arch.invlpg_counter);
-
         spin_unlock(&vcpu->kvm->mmu_lock);
-
-        if (pte_gpa == -1)
-                return;
-
-        if (mmu_topup_memory_caches(vcpu))
-                return;
-        kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
 }
 
 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
@@ -769,19 +768,14 @@ static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
  */
 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 {
-        int i, offset, nr_present;
+        int i, nr_present = 0;
         bool host_writable;
         gpa_t first_pte_gpa;
 
-        offset = nr_present = 0;
-
         /* direct kvm_mmu_page can not be unsync. */
         BUG_ON(sp->role.direct);
 
-        if (PTTYPE == 32)
-                offset = sp->role.quadrant << PT64_LEVEL_BITS;
-
-        first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
+        first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
 
         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
                 unsigned pte_access;
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
new file mode 100644
index 00000000000..7aad5446f39
--- /dev/null
+++ b/arch/x86/kvm/pmu.c
@@ -0,0 +1,533 @@
+/*
+ * Kernel-based Virtual Machine -- Performane Monitoring Unit support
+ *
+ * Copyright 2011 Red Hat, Inc. and/or its affiliates.
+ *
+ * Authors:
+ *   Avi Kivity   <avi@redhat.com>
+ *   Gleb Natapov <gleb@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/kvm_host.h>
+#include <linux/perf_event.h>
+#include "x86.h"
+#include "cpuid.h"
+#include "lapic.h"
+
+static struct kvm_arch_event_perf_mapping {
+        u8 eventsel;
+        u8 unit_mask;
+        unsigned event_type;
+        bool inexact;
+} arch_events[] = {
+        /* Index must match CPUID 0x0A.EBX bit vector */
+        [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
+        [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
+        [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES  },
+        [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
+        [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
+        [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
+        [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
+};
+
+/* mapping between fixed pmc index and arch_events array */
+int fixed_pmc_events[] = {1, 0, 2};
+
+static bool pmc_is_gp(struct kvm_pmc *pmc)
+{
+        return pmc->type == KVM_PMC_GP;
+}
+
+static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
+{
+        struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
+
+        return pmu->counter_bitmask[pmc->type];
+}
+
+static inline bool pmc_enabled(struct kvm_pmc *pmc)
+{
+        struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
+        return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
+}
+
+static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
+                                         u32 base)
+{
+        if (msr >= base && msr < base + pmu->nr_arch_gp_counters)
+                return &pmu->gp_counters[msr - base];
+        return NULL;
+}
+
+static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
+{
+        int base = MSR_CORE_PERF_FIXED_CTR0;
+        if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
+                return &pmu->fixed_counters[msr - base];
+        return NULL;
+}
+
+static inline struct kvm_pmc *get_fixed_pmc_idx(struct kvm_pmu *pmu, int idx)
+{
+        return get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + idx);
+}
+
+static struct kvm_pmc *global_idx_to_pmc(struct kvm_pmu *pmu, int idx)
+{
+        if (idx < X86_PMC_IDX_FIXED)
+                return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0);
+        else
+                return get_fixed_pmc_idx(pmu, idx - X86_PMC_IDX_FIXED);
+}
+
+void kvm_deliver_pmi(struct kvm_vcpu *vcpu)
+{
+        if (vcpu->arch.apic)
+                kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
+}
+
+static void trigger_pmi(struct irq_work *irq_work)
+{
+        struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu,
+                        irq_work);
+        struct kvm_vcpu *vcpu = container_of(pmu, struct kvm_vcpu,
+                        arch.pmu);
+
+        kvm_deliver_pmi(vcpu);
+}
+
+static void kvm_perf_overflow(struct perf_event *perf_event,
+                              struct perf_sample_data *data,
+                              struct pt_regs *regs)
+{
+        struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+        struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
+        __set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
+}
+
+static void kvm_perf_overflow_intr(struct perf_event *perf_event,
+                struct perf_sample_data *data, struct pt_regs *regs)
+{
+        struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+        struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu;
+        if (!test_and_set_bit(pmc->idx, (unsigned long *)&pmu->reprogram_pmi)) {
+                kvm_perf_overflow(perf_event, data, regs);
+                kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
+                /*
+                 * Inject PMI. If vcpu was in a guest mode during NMI PMI
+                 * can be ejected on a guest mode re-entry. Otherwise we can't
+                 * be sure that vcpu wasn't executing hlt instruction at the
+                 * time of vmexit and is not going to re-enter guest mode until,
+                 * woken up. So we should wake it, but this is impossible from
+                 * NMI context. Do it from irq work instead.
+                 */
+                if (!kvm_is_in_guest())
+                        irq_work_queue(&pmc->vcpu->arch.pmu.irq_work);
+                else
+                        kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
+        }
+}
+
+static u64 read_pmc(struct kvm_pmc *pmc)
+{
+        u64 counter, enabled, running;
+
+        counter = pmc->counter;
+
+        if (pmc->perf_event)
+                counter += perf_event_read_value(pmc->perf_event,
+                                                 &enabled, &running);
+
+        /* FIXME: Scaling needed? */
+
+        return counter & pmc_bitmask(pmc);
+}
+
+static void stop_counter(struct kvm_pmc *pmc)
+{
+        if (pmc->perf_event) {
+                pmc->counter = read_pmc(pmc);
+                perf_event_release_kernel(pmc->perf_event);
+                pmc->perf_event = NULL;
+        }
+}
+
+static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
+                unsigned config, bool exclude_user, bool exclude_kernel,
+                bool intr)
+{
+        struct perf_event *event;
+        struct perf_event_attr attr = {
+                .type = type,
+                .size = sizeof(attr),
+                .pinned = true,
+                .exclude_idle = true,
+                .exclude_host = 1,
+                .exclude_user = exclude_user,
+                .exclude_kernel = exclude_kernel,
+                .config = config,
+        };
+
+        attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
+
+        event = perf_event_create_kernel_counter(&attr, -1, current,
+                                                 intr ? kvm_perf_overflow_intr :
+                                                 kvm_perf_overflow, pmc);
+        if (IS_ERR(event)) {
+                printk_once("kvm: pmu event creation failed %ld\n",
+                                PTR_ERR(event));
+                return;
+        }
+
+        pmc->perf_event = event;
+        clear_bit(pmc->idx, (unsigned long*)&pmc->vcpu->arch.pmu.reprogram_pmi);
+}
+
+static unsigned find_arch_event(struct kvm_pmu *pmu, u8 event_select,
+                u8 unit_mask)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(arch_events); i++)
+                if (arch_events[i].eventsel == event_select
+                                && arch_events[i].unit_mask == unit_mask
+                                && (pmu->available_event_types & (1 << i)))
+                        break;
+
+        if (i == ARRAY_SIZE(arch_events))
+                return PERF_COUNT_HW_MAX;
+
+        return arch_events[i].event_type;
+}
+
+static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
+{
+        unsigned config, type = PERF_TYPE_RAW;
+        u8 event_select, unit_mask;
+
+        pmc->eventsel = eventsel;
+
+        stop_counter(pmc);
+
+        if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_enabled(pmc))
+                return;
+
+        event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
+        unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
+
+        if (!(event_select & (ARCH_PERFMON_EVENTSEL_EDGE |
+                                ARCH_PERFMON_EVENTSEL_INV |
+                                ARCH_PERFMON_EVENTSEL_CMASK))) {
+                config = find_arch_event(&pmc->vcpu->arch.pmu, event_select,
+                                unit_mask);
+                if (config != PERF_COUNT_HW_MAX)
+                        type = PERF_TYPE_HARDWARE;
+        }
+
+        if (type == PERF_TYPE_RAW)
+                config = eventsel & X86_RAW_EVENT_MASK;
+
+        reprogram_counter(pmc, type, config,
+                        !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
+                        !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
+                        eventsel & ARCH_PERFMON_EVENTSEL_INT);
+}
+
+static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
+{
+        unsigned en = en_pmi & 0x3;
+        bool pmi = en_pmi & 0x8;
+
+        stop_counter(pmc);
+
+        if (!en || !pmc_enabled(pmc))
+                return;
+
+        reprogram_counter(pmc, PERF_TYPE_HARDWARE,
+                        arch_events[fixed_pmc_events[idx]].event_type,
+                        !(en & 0x2), /* exclude user */
+                        !(en & 0x1), /* exclude kernel */
+                        pmi);
+}
+
+static inline u8 fixed_en_pmi(u64 ctrl, int idx)
+{
+        return (ctrl >> (idx * 4)) & 0xf;
+}
+
+static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
+{
+        int i;
+
+        for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
+                u8 en_pmi = fixed_en_pmi(data, i);
+                struct kvm_pmc *pmc = get_fixed_pmc_idx(pmu, i);
+
+                if (fixed_en_pmi(pmu->fixed_ctr_ctrl, i) == en_pmi)
+                        continue;
+
+                reprogram_fixed_counter(pmc, en_pmi, i);
+        }
+
+        pmu->fixed_ctr_ctrl = data;
+}
+
+static void reprogram_idx(struct kvm_pmu *pmu, int idx)
+{
+        struct kvm_pmc *pmc = global_idx_to_pmc(pmu, idx);
+
+        if (!pmc)
+                return;
+
+        if (pmc_is_gp(pmc))
+                reprogram_gp_counter(pmc, pmc->eventsel);
+        else {
+                int fidx = idx - X86_PMC_IDX_FIXED;
+                reprogram_fixed_counter(pmc,
+                                fixed_en_pmi(pmu->fixed_ctr_ctrl, fidx), fidx);
+        }
+}
+
+static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
+{
+        int bit;
+        u64 diff = pmu->global_ctrl ^ data;
+
+        pmu->global_ctrl = data;
+
+        for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
+                reprogram_idx(pmu, bit);
+}
+
+bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        int ret;
+
+        switch (msr) {
+        case MSR_CORE_PERF_FIXED_CTR_CTRL:
+        case MSR_CORE_PERF_GLOBAL_STATUS:
+        case MSR_CORE_PERF_GLOBAL_CTRL:
+        case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+                ret = pmu->version > 1;
+                break;
+        default:
+                ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)
+                        || get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0)
+                        || get_fixed_pmc(pmu, msr);
+                break;
+        }
+        return ret;
+}
+
+int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        struct kvm_pmc *pmc;
+
+        switch (index) {
+        case MSR_CORE_PERF_FIXED_CTR_CTRL:
+                *data = pmu->fixed_ctr_ctrl;
+                return 0;
+        case MSR_CORE_PERF_GLOBAL_STATUS:
+                *data = pmu->global_status;
+                return 0;
+        case MSR_CORE_PERF_GLOBAL_CTRL:
+                *data = pmu->global_ctrl;
+                return 0;
+        case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+                *data = pmu->global_ovf_ctrl;
+                return 0;
+        default:
+                if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
+                                (pmc = get_fixed_pmc(pmu, index))) {
+                        *data = read_pmc(pmc);
+                        return 0;
+                } else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
+                        *data = pmc->eventsel;
+                        return 0;
+                }
+        }
+        return 1;
+}
+
+int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        struct kvm_pmc *pmc;
+
+        switch (index) {
+        case MSR_CORE_PERF_FIXED_CTR_CTRL:
+                if (pmu->fixed_ctr_ctrl == data)
+                        return 0;
+                if (!(data & 0xfffffffffffff444)) {
+                        reprogram_fixed_counters(pmu, data);
+                        return 0;
+                }
+                break;
+        case MSR_CORE_PERF_GLOBAL_STATUS:
+                break; /* RO MSR */
+        case MSR_CORE_PERF_GLOBAL_CTRL:
+                if (pmu->global_ctrl == data)
+                        return 0;
+                if (!(data & pmu->global_ctrl_mask)) {
+                        global_ctrl_changed(pmu, data);
+                        return 0;
+                }
+                break;
+        case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+                if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
+                        pmu->global_status &= ~data;
+                        pmu->global_ovf_ctrl = data;
+                        return 0;
+                }
+                break;
+        default:
+                if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
+                                (pmc = get_fixed_pmc(pmu, index))) {
+                        data = (s64)(s32)data;
+                        pmc->counter += data - read_pmc(pmc);
+                        return 0;
+                } else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
+                        if (data == pmc->eventsel)
+                                return 0;
+                        if (!(data & 0xffffffff00200000ull)) {
+                                reprogram_gp_counter(pmc, data);
+                                return 0;
+                        }
+                }
+        }
+        return 1;
+}
+
+int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        bool fast_mode = pmc & (1u << 31);
+        bool fixed = pmc & (1u << 30);
+        struct kvm_pmc *counters;
+        u64 ctr;
+
+        pmc &= (3u << 30) - 1;
+        if (!fixed && pmc >= pmu->nr_arch_gp_counters)
+                return 1;
+        if (fixed && pmc >= pmu->nr_arch_fixed_counters)
+                return 1;
+        counters = fixed ? pmu->fixed_counters : pmu->gp_counters;
+        ctr = read_pmc(&counters[pmc]);
+        if (fast_mode)
+                ctr = (u32)ctr;
+        *data = ctr;
+
+        return 0;
+}
+
+void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        struct kvm_cpuid_entry2 *entry;
+        unsigned bitmap_len;
+
+        pmu->nr_arch_gp_counters = 0;
+        pmu->nr_arch_fixed_counters = 0;
+        pmu->counter_bitmask[KVM_PMC_GP] = 0;
+        pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
+        pmu->version = 0;
+
+        entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
+        if (!entry)
+                return;
+
+        pmu->version = entry->eax & 0xff;
+        if (!pmu->version)
+                return;
+
+        pmu->nr_arch_gp_counters = min((int)(entry->eax >> 8) & 0xff,
+                        X86_PMC_MAX_GENERIC);
+        pmu->counter_bitmask[KVM_PMC_GP] =
+                ((u64)1 << ((entry->eax >> 16) & 0xff)) - 1;
+        bitmap_len = (entry->eax >> 24) & 0xff;
+        pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1);
+
+        if (pmu->version == 1) {
+                pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1;
+                return;
+        }
+
+        pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
+                        X86_PMC_MAX_FIXED);
+        pmu->counter_bitmask[KVM_PMC_FIXED] =
+                ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
+        pmu->global_ctrl_mask = ~(((1 << pmu->nr_arch_gp_counters) - 1)
+                        | (((1ull << pmu->nr_arch_fixed_counters) - 1)
+                                << X86_PMC_IDX_FIXED));
+}
+
+void kvm_pmu_init(struct kvm_vcpu *vcpu)
+{
+        int i;
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+
+        memset(pmu, 0, sizeof(*pmu));
+        for (i = 0; i < X86_PMC_MAX_GENERIC; i++) {
+                pmu->gp_counters[i].type = KVM_PMC_GP;
+                pmu->gp_counters[i].vcpu = vcpu;
+                pmu->gp_counters[i].idx = i;
+        }
+        for (i = 0; i < X86_PMC_MAX_FIXED; i++) {
+                pmu->fixed_counters[i].type = KVM_PMC_FIXED;
+                pmu->fixed_counters[i].vcpu = vcpu;
+                pmu->fixed_counters[i].idx = i + X86_PMC_IDX_FIXED;
+        }
+        init_irq_work(&pmu->irq_work, trigger_pmi);
+        kvm_pmu_cpuid_update(vcpu);
+}
+
+void kvm_pmu_reset(struct kvm_vcpu *vcpu)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        int i;
+
+        irq_work_sync(&pmu->irq_work);
+        for (i = 0; i < X86_PMC_MAX_GENERIC; i++) {
+                struct kvm_pmc *pmc = &pmu->gp_counters[i];
+                stop_counter(pmc);
+                pmc->counter = pmc->eventsel = 0;
+        }
+
+        for (i = 0; i < X86_PMC_MAX_FIXED; i++)
+                stop_counter(&pmu->fixed_counters[i]);
+
+        pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
+                pmu->global_ovf_ctrl = 0;
+}
+
+void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
+{
+        kvm_pmu_reset(vcpu);
+}
+
+void kvm_handle_pmu_event(struct kvm_vcpu *vcpu)
+{
+        struct kvm_pmu *pmu = &vcpu->arch.pmu;
+        u64 bitmask;
+        int bit;
+
+        bitmask = pmu->reprogram_pmi;
+
+        for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) {
+                struct kvm_pmc *pmc = global_idx_to_pmc(pmu, bit);
+
+                if (unlikely(!pmc || !pmc->perf_event)) {
+                        clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi);
+                        continue;
+                }
+
+                reprogram_idx(pmu, bit);
+        }
+}
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index e32243eac2f..5fa553babe5 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1014,6 +1014,7 @@ static void init_vmcb(struct vcpu_svm *svm)
         set_intercept(svm, INTERCEPT_NMI);
         set_intercept(svm, INTERCEPT_SMI);
         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
+        set_intercept(svm, INTERCEPT_RDPMC);
         set_intercept(svm, INTERCEPT_CPUID);
         set_intercept(svm, INTERCEPT_INVD);
         set_intercept(svm, INTERCEPT_HLT);
@@ -2770,6 +2771,19 @@ static int emulate_on_interception(struct vcpu_svm *svm)
         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
 }
 
+static int rdpmc_interception(struct vcpu_svm *svm)
+{
+        int err;
+
+        if (!static_cpu_has(X86_FEATURE_NRIPS))
+                return emulate_on_interception(svm);
+
+        err = kvm_rdpmc(&svm->vcpu);
+        kvm_complete_insn_gp(&svm->vcpu, err);
+
+        return 1;
+}
+
 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
 {
         unsigned long cr0 = svm->vcpu.arch.cr0;
@@ -3190,6 +3204,7 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
         [SVM_EXIT_SMI]                          = nop_on_interception,
         [SVM_EXIT_INIT]                         = nop_on_interception,
         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
+        [SVM_EXIT_RDPMC]                        = rdpmc_interception,
         [SVM_EXIT_CPUID]                        = cpuid_interception,
         [SVM_EXIT_IRET]                         = iret_interception,
         [SVM_EXIT_INVD]                         = emulate_on_interception,
diff --git a/arch/x86/kvm/timer.c b/arch/x86/kvm/timer.c
index ae432ea1cd8..6b85cc647f3 100644
--- a/arch/x86/kvm/timer.c
+++ b/arch/x86/kvm/timer.c
@@ -18,9 +18,10 @@
 #include <linux/atomic.h>
 #include "kvm_timer.h"
 
-static int __kvm_timer_fn(struct kvm_vcpu *vcpu, struct kvm_timer *ktimer)
+enum hrtimer_restart kvm_timer_fn(struct hrtimer *data)
 {
-        int restart_timer = 0;
+        struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
+        struct kvm_vcpu *vcpu = ktimer->vcpu;
         wait_queue_head_t *q = &vcpu->wq;
 
         /*
@@ -40,26 +41,7 @@ static int __kvm_timer_fn(struct kvm_vcpu *vcpu, struct kvm_timer *ktimer)
 
         if (ktimer->t_ops->is_periodic(ktimer)) {
                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
-                restart_timer = 1;
-        }
-
-        return restart_timer;
-}
-
-enum hrtimer_restart kvm_timer_fn(struct hrtimer *data)
-{
-        int restart_timer;
-        struct kvm_vcpu *vcpu;
-        struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
-
-        vcpu = ktimer->vcpu;
-        if (!vcpu)
-                return HRTIMER_NORESTART;
-
-        restart_timer = __kvm_timer_fn(vcpu, ktimer);
-        if (restart_timer)
                 return HRTIMER_RESTART;
-        else
+        } else
                 return HRTIMER_NORESTART;
 }
-
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 579a0b51696..906a7e84200 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -18,6 +18,7 @@
 
 #include "irq.h"
 #include "mmu.h"
+#include "cpuid.h"
 
 #include <linux/kvm_host.h>
 #include <linux/module.h>
@@ -1747,7 +1748,6 @@ static void setup_msrs(struct vcpu_vmx *vmx)
         int save_nmsrs, index;
         unsigned long *msr_bitmap;
 
-        vmx_load_host_state(vmx);
         save_nmsrs = 0;
 #ifdef CONFIG_X86_64
         if (is_long_mode(&vmx->vcpu)) {
@@ -1956,6 +1956,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
 #endif
                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
+                CPU_BASED_RDPMC_EXITING |
                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
         /*
          * We can allow some features even when not supported by the
@@ -2142,12 +2143,10 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
                         return 1;
                 /* Otherwise falls through */
         default:
-                vmx_load_host_state(to_vmx(vcpu));
                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
                         return 0;
                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
                 if (msr) {
-                        vmx_load_host_state(to_vmx(vcpu));
                         data = msr->data;
                         break;
                 }
@@ -2171,7 +2170,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 
         switch (msr_index) {
         case MSR_EFER:
-                vmx_load_host_state(vmx);
                 ret = kvm_set_msr_common(vcpu, msr_index, data);
                 break;
 #ifdef CONFIG_X86_64
@@ -2220,7 +2218,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
                         break;
                 msr = find_msr_entry(vmx, msr_index);
                 if (msr) {
-                        vmx_load_host_state(vmx);
                         msr->data = data;
                         break;
                 }
@@ -2414,7 +2411,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
               CPU_BASED_USE_TSC_OFFSETING |
               CPU_BASED_MWAIT_EXITING |
               CPU_BASED_MONITOR_EXITING |
-              CPU_BASED_INVLPG_EXITING;
+              CPU_BASED_INVLPG_EXITING |
+              CPU_BASED_RDPMC_EXITING;
 
         if (yield_on_hlt)
                 min |= CPU_BASED_HLT_EXITING;
@@ -2716,11 +2714,13 @@ static gva_t rmode_tss_base(struct kvm *kvm)
 {
         if (!kvm->arch.tss_addr) {
                 struct kvm_memslots *slots;
+                struct kvm_memory_slot *slot;
                 gfn_t base_gfn;
 
                 slots = kvm_memslots(kvm);
-                base_gfn = slots->memslots[0].base_gfn +
-                                 kvm->memslots->memslots[0].npages - 3;
+                slot = id_to_memslot(slots, 0);
+                base_gfn = slot->base_gfn + slot->npages - 3;
+
                 return base_gfn << PAGE_SHIFT;
         }
         return kvm->arch.tss_addr;
@@ -3945,12 +3945,15 @@ static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
 static void enable_irq_window(struct kvm_vcpu *vcpu)
 {
         u32 cpu_based_vm_exec_control;
-        if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
-                /* We can get here when nested_run_pending caused
-                 * vmx_interrupt_allowed() to return false. In this case, do
-                 * nothing - the interrupt will be injected later.
+        if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
+                /*
+                 * We get here if vmx_interrupt_allowed() said we can't
+                 * inject to L1 now because L2 must run. Ask L2 to exit
+                 * right after entry, so we can inject to L1 more promptly.
                  */
+                kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
                 return;
+        }
 
         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
@@ -4077,11 +4080,12 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
 {
         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
-                struct vmcs12 *vmcs12;
-                if (to_vmx(vcpu)->nested.nested_run_pending)
+                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+                if (to_vmx(vcpu)->nested.nested_run_pending ||
+                    (vmcs12->idt_vectoring_info_field &
+                     VECTORING_INFO_VALID_MASK))
                         return 0;
                 nested_vmx_vmexit(vcpu);
-                vmcs12 = get_vmcs12(vcpu);
                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
                 vmcs12->vm_exit_intr_info = 0;
                 /* fall through to normal code, but now in L1, not L2 */
@@ -4611,6 +4615,16 @@ static int handle_invlpg(struct kvm_vcpu *vcpu)
         return 1;
 }
 
+static int handle_rdpmc(struct kvm_vcpu *vcpu)
+{
+        int err;
+
+        err = kvm_rdpmc(vcpu);
+        kvm_complete_insn_gp(vcpu, err);
+
+        return 1;
+}
+
 static int handle_wbinvd(struct kvm_vcpu *vcpu)
 {
         skip_emulated_instruction(vcpu);
@@ -5561,6 +5575,7 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
         [EXIT_REASON_HLT]                     = handle_halt,
         [EXIT_REASON_INVD]                    = handle_invd,
         [EXIT_REASON_INVLPG]                  = handle_invlpg,
+        [EXIT_REASON_RDPMC]                   = handle_rdpmc,
         [EXIT_REASON_VMCALL]                  = handle_vmcall,
         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 4c938da2ba0..1171def5f96 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -26,6 +26,7 @@
 #include "tss.h"
 #include "kvm_cache_regs.h"
 #include "x86.h"
+#include "cpuid.h"
 
 #include <linux/clocksource.h>
 #include <linux/interrupt.h>
@@ -82,8 +83,6 @@ static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
 
 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
-static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
-                                    struct kvm_cpuid_entry2 __user *entries);
 static void process_nmi(struct kvm_vcpu *vcpu);
 
 struct kvm_x86_ops *kvm_x86_ops;
@@ -574,54 +573,6 @@ int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 }
 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 
-static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
-{
-        struct kvm_cpuid_entry2 *best;
-
-        best = kvm_find_cpuid_entry(vcpu, 1, 0);
-        return best && (best->ecx & bit(X86_FEATURE_XSAVE));
-}
-
-static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
-{
-        struct kvm_cpuid_entry2 *best;
-
-        best = kvm_find_cpuid_entry(vcpu, 7, 0);
-        return best && (best->ebx & bit(X86_FEATURE_SMEP));
-}
-
-static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
-{
-        struct kvm_cpuid_entry2 *best;
-
-        best = kvm_find_cpuid_entry(vcpu, 7, 0);
-        return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
-}
-
-static void update_cpuid(struct kvm_vcpu *vcpu)
-{
-        struct kvm_cpuid_entry2 *best;
-        struct kvm_lapic *apic = vcpu->arch.apic;
-
-        best = kvm_find_cpuid_entry(vcpu, 1, 0);
-        if (!best)
-                return;
-
-        /* Update OSXSAVE bit */
-        if (cpu_has_xsave && best->function == 0x1) {
-                best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
-                if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
-                        best->ecx |= bit(X86_FEATURE_OSXSAVE);
-        }
-
-        if (apic) {
-                if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
-                        apic->lapic_timer.timer_mode_mask = 3 << 17;
-                else
-                        apic->lapic_timer.timer_mode_mask = 1 << 17;
-        }
-}
-
 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 {
         unsigned long old_cr4 = kvm_read_cr4(vcpu);
@@ -655,7 +606,7 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
                 kvm_mmu_reset_context(vcpu);
 
         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
-                update_cpuid(vcpu);
+                kvm_update_cpuid(vcpu);
 
         return 0;
 }
@@ -809,6 +760,21 @@ int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 }
 EXPORT_SYMBOL_GPL(kvm_get_dr);
 
+bool kvm_rdpmc(struct kvm_vcpu *vcpu)
+{
+        u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
+        u64 data;
+        int err;
+
+        err = kvm_pmu_read_pmc(vcpu, ecx, &data);
+        if (err)
+                return err;
+        kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
+        kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
+        return err;
+}
+EXPORT_SYMBOL_GPL(kvm_rdpmc);
+
 /*
  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
@@ -1358,12 +1324,11 @@ static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
         if (page_num >= blob_size)
                 goto out;
         r = -ENOMEM;
-        page = kzalloc(PAGE_SIZE, GFP_KERNEL);
-        if (!page)
+        page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
+        if (IS_ERR(page)) {
+                r = PTR_ERR(page);
                 goto out;
-        r = -EFAULT;
-        if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
-                goto out_free;
+        }
         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
                 goto out_free;
         r = 0;
@@ -1652,8 +1617,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
          * which we perfectly emulate ;-). Any other value should be at least
          * reported, some guests depend on them.
          */
-        case MSR_P6_EVNTSEL0:
-        case MSR_P6_EVNTSEL1:
         case MSR_K7_EVNTSEL0:
         case MSR_K7_EVNTSEL1:
         case MSR_K7_EVNTSEL2:
@@ -1665,8 +1628,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         /* at least RHEL 4 unconditionally writes to the perfctr registers,
          * so we ignore writes to make it happy.
          */
-        case MSR_P6_PERFCTR0:
-        case MSR_P6_PERFCTR1:
         case MSR_K7_PERFCTR0:
         case MSR_K7_PERFCTR1:
         case MSR_K7_PERFCTR2:
@@ -1703,6 +1664,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         default:
                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
                         return xen_hvm_config(vcpu, data);
+                if (kvm_pmu_msr(vcpu, msr))
+                        return kvm_pmu_set_msr(vcpu, msr, data);
                 if (!ignore_msrs) {
                         pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
                                 msr, data);
@@ -1865,10 +1828,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
         case MSR_K8_SYSCFG:
         case MSR_K7_HWCR:
         case MSR_VM_HSAVE_PA:
-        case MSR_P6_PERFCTR0:
-        case MSR_P6_PERFCTR1:
-        case MSR_P6_EVNTSEL0:
-        case MSR_P6_EVNTSEL1:
         case MSR_K7_EVNTSEL0:
         case MSR_K7_PERFCTR0:
         case MSR_K8_INT_PENDING_MSG:
@@ -1979,6 +1938,8 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
                 data = 0xbe702111;
                 break;
         default:
+                if (kvm_pmu_msr(vcpu, msr))
+                        return kvm_pmu_get_msr(vcpu, msr, pdata);
                 if (!ignore_msrs) {
                         pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
                         return 1;
@@ -2037,15 +1998,12 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
         if (msrs.nmsrs >= MAX_IO_MSRS)
                 goto out;
 
-        r = -ENOMEM;
         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
-        entries = kmalloc(size, GFP_KERNEL);
-        if (!entries)
+        entries = memdup_user(user_msrs->entries, size);
+        if (IS_ERR(entries)) {
+                r = PTR_ERR(entries);
                 goto out;
-
-        r = -EFAULT;
-        if (copy_from_user(entries, user_msrs->entries, size))
-                goto out_free;
+        }
 
         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
         if (r < 0)
@@ -2265,466 +2223,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
 }
 
-static int is_efer_nx(void)
-{
-        unsigned long long efer = 0;
-
-        rdmsrl_safe(MSR_EFER, &efer);
-        return efer & EFER_NX;
-}
-
-static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
-{
-        int i;
-        struct kvm_cpuid_entry2 *e, *entry;
-
-        entry = NULL;
-        for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
-                e = &vcpu->arch.cpuid_entries[i];
-                if (e->function == 0x80000001) {
-                        entry = e;
-                        break;
-                }
-        }
-        if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
-                entry->edx &= ~(1 << 20);
-                printk(KERN_INFO "kvm: guest NX capability removed\n");
-        }
-}
-
-/* when an old userspace process fills a new kernel module */
-static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
-                                    struct kvm_cpuid *cpuid,
-                                    struct kvm_cpuid_entry __user *entries)
-{
-        int r, i;
-        struct kvm_cpuid_entry *cpuid_entries;
-
-        r = -E2BIG;
-        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
-                goto out;
-        r = -ENOMEM;
-        cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
-        if (!cpuid_entries)
-                goto out;
-        r = -EFAULT;
-        if (copy_from_user(cpuid_entries, entries,
-                           cpuid->nent * sizeof(struct kvm_cpuid_entry)))
-                goto out_free;
-        for (i = 0; i < cpuid->nent; i++) {
-                vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
-                vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
-                vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
-                vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
-                vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
-                vcpu->arch.cpuid_entries[i].index = 0;
-                vcpu->arch.cpuid_entries[i].flags = 0;
-                vcpu->arch.cpuid_entries[i].padding[0] = 0;
-                vcpu->arch.cpuid_entries[i].padding[1] = 0;
-                vcpu->arch.cpuid_entries[i].padding[2] = 0;
-        }
-        vcpu->arch.cpuid_nent = cpuid->nent;
-        cpuid_fix_nx_cap(vcpu);
-        r = 0;
-        kvm_apic_set_version(vcpu);
-        kvm_x86_ops->cpuid_update(vcpu);
-        update_cpuid(vcpu);
-
-out_free:
-        vfree(cpuid_entries);
-out:
-        return r;
-}
-
-static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
-                                     struct kvm_cpuid2 *cpuid,
-                                     struct kvm_cpuid_entry2 __user *entries)
-{
-        int r;
-
-        r = -E2BIG;
-        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
-                goto out;
-        r = -EFAULT;
-        if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
-                           cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
-                goto out;
-        vcpu->arch.cpuid_nent = cpuid->nent;
-        kvm_apic_set_version(vcpu);
-        kvm_x86_ops->cpuid_update(vcpu);
-        update_cpuid(vcpu);
-        return 0;
-
-out:
-        return r;
-}
-
-static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
-                                     struct kvm_cpuid2 *cpuid,
-                                     struct kvm_cpuid_entry2 __user *entries)
-{
-        int r;
-
-        r = -E2BIG;
-        if (cpuid->nent < vcpu->arch.cpuid_nent)
-                goto out;
-        r = -EFAULT;
-        if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
-                         vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
-                goto out;
-        return 0;
-
-out:
-        cpuid->nent = vcpu->arch.cpuid_nent;
-        return r;
-}
-
-static void cpuid_mask(u32 *word, int wordnum)
-{
-        *word &= boot_cpu_data.x86_capability[wordnum];
-}
-
-static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
-                           u32 index)
-{
-        entry->function = function;
-        entry->index = index;
-        cpuid_count(entry->function, entry->index,
-                    &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
-        entry->flags = 0;
-}
-
-static bool supported_xcr0_bit(unsigned bit)
-{
-        u64 mask = ((u64)1 << bit);
-
-        return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
-}
-
-#define F(x) bit(X86_FEATURE_##x)
-
-static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
-                         u32 index, int *nent, int maxnent)
-{
-        unsigned f_nx = is_efer_nx() ? F(NX) : 0;
-#ifdef CONFIG_X86_64
-        unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
-                                ? F(GBPAGES) : 0;
-        unsigned f_lm = F(LM);
-#else
-        unsigned f_gbpages = 0;
-        unsigned f_lm = 0;
-#endif
-        unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
-
-        /* cpuid 1.edx */
-        const u32 kvm_supported_word0_x86_features =
-                F(FPU) | F(VME) | F(DE) | F(PSE) |
-                F(TSC) | F(MSR) | F(PAE) | F(MCE) |
-                F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
-                F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
-                F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
-                0 /* Reserved, DS, ACPI */ | F(MMX) |
-                F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
-                0 /* HTT, TM, Reserved, PBE */;
-        /* cpuid 0x80000001.edx */
-        const u32 kvm_supported_word1_x86_features =
-                F(FPU) | F(VME) | F(DE) | F(PSE) |
-                F(TSC) | F(MSR) | F(PAE) | F(MCE) |
-                F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
-                F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
-                F(PAT) | F(PSE36) | 0 /* Reserved */ |
-                f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
-                F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
-                0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
-        /* cpuid 1.ecx */
-        const u32 kvm_supported_word4_x86_features =
-                F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
-                0 /* DS-CPL, VMX, SMX, EST */ |
-                0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
-                0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
-                0 /* Reserved, DCA */ | F(XMM4_1) |
-                F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
-                0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
-                F(F16C) | F(RDRAND);
-        /* cpuid 0x80000001.ecx */
-        const u32 kvm_supported_word6_x86_features =
-                F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
-                F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
-                F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
-                0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
-
-        /* cpuid 0xC0000001.edx */
-        const u32 kvm_supported_word5_x86_features =
-                F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
-                F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
-                F(PMM) | F(PMM_EN);
-
-        /* cpuid 7.0.ebx */
-        const u32 kvm_supported_word9_x86_features =
-                F(SMEP) | F(FSGSBASE) | F(ERMS);
-
-        /* all calls to cpuid_count() should be made on the same cpu */
-        get_cpu();
-        do_cpuid_1_ent(entry, function, index);
-        ++*nent;
-
-        switch (function) {
-        case 0:
-                entry->eax = min(entry->eax, (u32)0xd);
-                break;
-        case 1:
-                entry->edx &= kvm_supported_word0_x86_features;
-                cpuid_mask(&entry->edx, 0);
-                entry->ecx &= kvm_supported_word4_x86_features;
-                cpuid_mask(&entry->ecx, 4);
-                /* we support x2apic emulation even if host does not support
-                 * it since we emulate x2apic in software */
-                entry->ecx |= F(X2APIC);
-                break;
-        /* function 2 entries are STATEFUL. That is, repeated cpuid commands
-         * may return different values. This forces us to get_cpu() before
-         * issuing the first command, and also to emulate this annoying behavior
-         * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
-        case 2: {
-                int t, times = entry->eax & 0xff;
-
-                entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
-                entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
-                for (t = 1; t < times && *nent < maxnent; ++t) {
-                        do_cpuid_1_ent(&entry[t], function, 0);
-                        entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
-                        ++*nent;
-                }
-                break;
-        }
-        /* function 4 has additional index. */
-        case 4: {
-                int i, cache_type;
-
-                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                /* read more entries until cache_type is zero */
-                for (i = 1; *nent < maxnent; ++i) {
-                        cache_type = entry[i - 1].eax & 0x1f;
-                        if (!cache_type)
-                                break;
-                        do_cpuid_1_ent(&entry[i], function, i);
-                        entry[i].flags |=
-                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                        ++*nent;
-                }
-                break;
-        }
-        case 7: {
-                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                /* Mask ebx against host capbability word 9 */
-                if (index == 0) {
-                        entry->ebx &= kvm_supported_word9_x86_features;
-                        cpuid_mask(&entry->ebx, 9);
-                } else
-                        entry->ebx = 0;
-                entry->eax = 0;
-                entry->ecx = 0;
-                entry->edx = 0;
-                break;
-        }
-        case 9:
-                break;
-        /* function 0xb has additional index. */
-        case 0xb: {
-                int i, level_type;
-
-                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                /* read more entries until level_type is zero */
-                for (i = 1; *nent < maxnent; ++i) {
-                        level_type = entry[i - 1].ecx & 0xff00;
-                        if (!level_type)
-                                break;
-                        do_cpuid_1_ent(&entry[i], function, i);
-                        entry[i].flags |=
-                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                        ++*nent;
-                }
-                break;
-        }
-        case 0xd: {
-                int idx, i;
-
-                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
-                        do_cpuid_1_ent(&entry[i], function, idx);
-                        if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
-                                continue;
-                        entry[i].flags |=
-                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                        ++*nent;
-                        ++i;
-                }
-                break;
-        }
-        case KVM_CPUID_SIGNATURE: {
-                char signature[12] = "KVMKVMKVM\0\0";
-                u32 *sigptr = (u32 *)signature;
-                entry->eax = 0;
-                entry->ebx = sigptr[0];
-                entry->ecx = sigptr[1];
-                entry->edx = sigptr[2];
-                break;
-        }
-        case KVM_CPUID_FEATURES:
-                entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
-                             (1 << KVM_FEATURE_NOP_IO_DELAY) |
-                             (1 << KVM_FEATURE_CLOCKSOURCE2) |
-                             (1 << KVM_FEATURE_ASYNC_PF) |
-                             (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
-
-                if (sched_info_on())
-                        entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
-
-                entry->ebx = 0;
-                entry->ecx = 0;
-                entry->edx = 0;
-                break;
-        case 0x80000000:
-                entry->eax = min(entry->eax, 0x8000001a);
-                break;
-        case 0x80000001:
-                entry->edx &= kvm_supported_word1_x86_features;
-                cpuid_mask(&entry->edx, 1);
-                entry->ecx &= kvm_supported_word6_x86_features;
-                cpuid_mask(&entry->ecx, 6);
-                break;
-        case 0x80000008: {
-                unsigned g_phys_as = (entry->eax >> 16) & 0xff;
-                unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
-                unsigned phys_as = entry->eax & 0xff;
-
-                if (!g_phys_as)
-                        g_phys_as = phys_as;
-                entry->eax = g_phys_as | (virt_as << 8);
-                entry->ebx = entry->edx = 0;
-                break;
-        }
-        case 0x80000019:
-                entry->ecx = entry->edx = 0;
-                break;
-        case 0x8000001a:
-                break;
-        case 0x8000001d:
-                break;
-        /*Add support for Centaur's CPUID instruction*/
-        case 0xC0000000:
-                /*Just support up to 0xC0000004 now*/
-                entry->eax = min(entry->eax, 0xC0000004);
-                break;
-        case 0xC0000001:
-                entry->edx &= kvm_supported_word5_x86_features;
-                cpuid_mask(&entry->edx, 5);
-                break;
-        case 3: /* Processor serial number */
-        case 5: /* MONITOR/MWAIT */
-        case 6: /* Thermal management */
-        case 0xA: /* Architectural Performance Monitoring */
-        case 0x80000007: /* Advanced power management */
-        case 0xC0000002:
-        case 0xC0000003:
-        case 0xC0000004:
-        default:
-                entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
-                break;
-        }
-
-        kvm_x86_ops->set_supported_cpuid(function, entry);
-
-        put_cpu();
-}
-
-#undef F
-
-static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
-                                     struct kvm_cpuid_entry2 __user *entries)
-{
-        struct kvm_cpuid_entry2 *cpuid_entries;
-        int limit, nent = 0, r = -E2BIG;
-        u32 func;
-
-        if (cpuid->nent < 1)
-                goto out;
-        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
-                cpuid->nent = KVM_MAX_CPUID_ENTRIES;
-        r = -ENOMEM;
-        cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
-        if (!cpuid_entries)
-                goto out;
-
-        do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
-        limit = cpuid_entries[0].eax;
-        for (func = 1; func <= limit && nent < cpuid->nent; ++func)
-                do_cpuid_ent(&cpuid_entries[nent], func, 0,
-                             &nent, cpuid->nent);
-        r = -E2BIG;
-        if (nent >= cpuid->nent)
-                goto out_free;
-
-        do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
-        limit = cpuid_entries[nent - 1].eax;
-        for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
-                do_cpuid_ent(&cpuid_entries[nent], func, 0,
-                             &nent, cpuid->nent);
-
-
-
-        r = -E2BIG;
-        if (nent >= cpuid->nent)
-                goto out_free;
-
-        /* Add support for Centaur's CPUID instruction. */
-        if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
-                do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
-                                &nent, cpuid->nent);
-
-                r = -E2BIG;
-                if (nent >= cpuid->nent)
-                        goto out_free;
-
-                limit = cpuid_entries[nent - 1].eax;
-                for (func = 0xC0000001;
-                        func <= limit && nent < cpuid->nent; ++func)
-                        do_cpuid_ent(&cpuid_entries[nent], func, 0,
-                                        &nent, cpuid->nent);
-
-                r = -E2BIG;
-                if (nent >= cpuid->nent)
-                        goto out_free;
-        }
-
-        do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
-                     cpuid->nent);
-
-        r = -E2BIG;
-        if (nent >= cpuid->nent)
-                goto out_free;
-
-        do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
-                     cpuid->nent);
-
-        r = -E2BIG;
-        if (nent >= cpuid->nent)
-                goto out_free;
-
-        r = -EFAULT;
-        if (copy_to_user(entries, cpuid_entries,
-                         nent * sizeof(struct kvm_cpuid_entry2)))
-                goto out_free;
-        cpuid->nent = nent;
-        r = 0;
-
-out_free:
-        vfree(cpuid_entries);
-out:
-        return r;
-}
-
 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
                                     struct kvm_lapic_state *s)
 {
@@ -3042,13 +2540,12 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 r = -EINVAL;
                 if (!vcpu->arch.apic)
                         goto out;
-                u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
-                r = -ENOMEM;
-                if (!u.lapic)
-                        goto out;
-                r = -EFAULT;
-                if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
+                u.lapic = memdup_user(argp, sizeof(*u.lapic));
+                if (IS_ERR(u.lapic)) {
+                        r = PTR_ERR(u.lapic);
                         goto out;
+                }
+
                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
                 if (r)
                         goto out;
@@ -3227,14 +2724,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 break;
         }
         case KVM_SET_XSAVE: {
-                u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
-                r = -ENOMEM;
-                if (!u.xsave)
-                        break;
-
-                r = -EFAULT;
-                if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
-                        break;
+                u.xsave = memdup_user(argp, sizeof(*u.xsave));
+                if (IS_ERR(u.xsave)) {
+                        r = PTR_ERR(u.xsave);
+                        goto out;
+                }
 
                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
                 break;
@@ -3255,15 +2749,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 break;
         }
         case KVM_SET_XCRS: {
-                u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
-                r = -ENOMEM;
-                if (!u.xcrs)
-                        break;
-
-                r = -EFAULT;
-                if (copy_from_user(u.xcrs, argp,
-                                   sizeof(struct kvm_xcrs)))
-                        break;
+                u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
+                if (IS_ERR(u.xcrs)) {
+                        r = PTR_ERR(u.xcrs);
+                        goto out;
+                }
 
                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
                 break;
@@ -3460,16 +2950,59 @@ static int kvm_vm_ioctl_reinject(struct kvm *kvm,
         return 0;
 }
 
+/**
+ * write_protect_slot - write protect a slot for dirty logging
+ * @kvm: the kvm instance
+ * @memslot: the slot we protect
+ * @dirty_bitmap: the bitmap indicating which pages are dirty
+ * @nr_dirty_pages: the number of dirty pages
+ *
+ * We have two ways to find all sptes to protect:
+ * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
+ *    checks ones that have a spte mapping a page in the slot.
+ * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
+ *
+ * Generally speaking, if there are not so many dirty pages compared to the
+ * number of shadow pages, we should use the latter.
+ *
+ * Note that letting others write into a page marked dirty in the old bitmap
+ * by using the remaining tlb entry is not a problem.  That page will become
+ * write protected again when we flush the tlb and then be reported dirty to
+ * the user space by copying the old bitmap.
+ */
+static void write_protect_slot(struct kvm *kvm,
+                               struct kvm_memory_slot *memslot,
+                               unsigned long *dirty_bitmap,
+                               unsigned long nr_dirty_pages)
+{
+        /* Not many dirty pages compared to # of shadow pages. */
+        if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
+                unsigned long gfn_offset;
+
+                for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
+                        unsigned long gfn = memslot->base_gfn + gfn_offset;
+
+                        spin_lock(&kvm->mmu_lock);
+                        kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
+                        spin_unlock(&kvm->mmu_lock);
+                }
+                kvm_flush_remote_tlbs(kvm);
+        } else {
+                spin_lock(&kvm->mmu_lock);
+                kvm_mmu_slot_remove_write_access(kvm, memslot->id);
+                spin_unlock(&kvm->mmu_lock);
+        }
+}
+
 /*
  * Get (and clear) the dirty memory log for a memory slot.
  */
 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
                                       struct kvm_dirty_log *log)
 {
-        int r, i;
+        int r;
         struct kvm_memory_slot *memslot;
-        unsigned long n;
-        unsigned long is_dirty = 0;
+        unsigned long n, nr_dirty_pages;
 
         mutex_lock(&kvm->slots_lock);
 
@@ -3477,43 +3010,41 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
         if (log->slot >= KVM_MEMORY_SLOTS)
                 goto out;
 
-        memslot = &kvm->memslots->memslots[log->slot];
+        memslot = id_to_memslot(kvm->memslots, log->slot);
         r = -ENOENT;
         if (!memslot->dirty_bitmap)
                 goto out;
 
         n = kvm_dirty_bitmap_bytes(memslot);
-
-        for (i = 0; !is_dirty && i < n/sizeof(long); i++)
-                is_dirty = memslot->dirty_bitmap[i];
+        nr_dirty_pages = memslot->nr_dirty_pages;
 
         /* If nothing is dirty, don't bother messing with page tables. */
-        if (is_dirty) {
+        if (nr_dirty_pages) {
                 struct kvm_memslots *slots, *old_slots;
-                unsigned long *dirty_bitmap;
+                unsigned long *dirty_bitmap, *dirty_bitmap_head;
 
-                dirty_bitmap = memslot->dirty_bitmap_head;
-                if (memslot->dirty_bitmap == dirty_bitmap)
-                        dirty_bitmap += n / sizeof(long);
-                memset(dirty_bitmap, 0, n);
+                dirty_bitmap = memslot->dirty_bitmap;
+                dirty_bitmap_head = memslot->dirty_bitmap_head;
+                if (dirty_bitmap == dirty_bitmap_head)
+                        dirty_bitmap_head += n / sizeof(long);
+                memset(dirty_bitmap_head, 0, n);
 
                 r = -ENOMEM;
-                slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
+                slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
                 if (!slots)
                         goto out;
-                memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
-                slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
-                slots->generation++;
+
+                memslot = id_to_memslot(slots, log->slot);
+                memslot->nr_dirty_pages = 0;
+                memslot->dirty_bitmap = dirty_bitmap_head;
+                update_memslots(slots, NULL);
 
                 old_slots = kvm->memslots;
                 rcu_assign_pointer(kvm->memslots, slots);
                 synchronize_srcu_expedited(&kvm->srcu);
-                dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
                 kfree(old_slots);
 
-                spin_lock(&kvm->mmu_lock);
-                kvm_mmu_slot_remove_write_access(kvm, log->slot);
-                spin_unlock(&kvm->mmu_lock);
+                write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
 
                 r = -EFAULT;
                 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
@@ -3658,14 +3189,14 @@ long kvm_arch_vm_ioctl(struct file *filp,
         }
         case KVM_GET_IRQCHIP: {
                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
-                struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
+                struct kvm_irqchip *chip;
 
-                r = -ENOMEM;
-                if (!chip)
+                chip = memdup_user(argp, sizeof(*chip));
+                if (IS_ERR(chip)) {
+                        r = PTR_ERR(chip);
                         goto out;
-                r = -EFAULT;
-                if (copy_from_user(chip, argp, sizeof *chip))
-                        goto get_irqchip_out;
+                }
+
                 r = -ENXIO;
                 if (!irqchip_in_kernel(kvm))
                         goto get_irqchip_out;
@@ -3684,14 +3215,14 @@ long kvm_arch_vm_ioctl(struct file *filp,
         }
         case KVM_SET_IRQCHIP: {
                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
-                struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
+                struct kvm_irqchip *chip;
 
-                r = -ENOMEM;
-                if (!chip)
+                chip = memdup_user(argp, sizeof(*chip));
+                if (IS_ERR(chip)) {
+                        r = PTR_ERR(chip);
                         goto out;
-                r = -EFAULT;
-                if (copy_from_user(chip, argp, sizeof *chip))
-                        goto set_irqchip_out;
+                }
+
                 r = -ENXIO;
                 if (!irqchip_in_kernel(kvm))
                         goto set_irqchip_out;
@@ -3898,12 +3429,7 @@ void kvm_get_segment(struct kvm_vcpu *vcpu,
         kvm_x86_ops->get_segment(vcpu, var, seg);
 }
 
-static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
-{
-        return gpa;
-}
-
-static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
+gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
 {
         gpa_t t_gpa;
         struct x86_exception exception;
@@ -4087,7 +3613,7 @@ int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
         if (ret < 0)
                 return 0;
-        kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
+        kvm_mmu_pte_write(vcpu, gpa, val, bytes);
         return 1;
 }
 
@@ -4324,7 +3850,7 @@ static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
         if (!exchanged)
                 return X86EMUL_CMPXCHG_FAILED;
 
-        kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
+        kvm_mmu_pte_write(vcpu, gpa, new, bytes);
 
         return X86EMUL_CONTINUE;
 
@@ -4349,32 +3875,24 @@ static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
         return r;
 }
 
-
-static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
-                                    int size, unsigned short port, void *val,
-                                    unsigned int count)
+static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
+                               unsigned short port, void *val,
+                               unsigned int count, bool in)
 {
-        struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
-
-        if (vcpu->arch.pio.count)
-                goto data_avail;
-
-        trace_kvm_pio(0, port, size, count);
+        trace_kvm_pio(!in, port, size, count);
 
         vcpu->arch.pio.port = port;
-        vcpu->arch.pio.in = 1;
+        vcpu->arch.pio.in = in;
         vcpu->arch.pio.count  = count;
         vcpu->arch.pio.size = size;
 
         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
-        data_avail:
-                memcpy(val, vcpu->arch.pio_data, size * count);
                 vcpu->arch.pio.count = 0;
                 return 1;
         }
 
         vcpu->run->exit_reason = KVM_EXIT_IO;
-        vcpu->run->io.direction = KVM_EXIT_IO_IN;
+        vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
         vcpu->run->io.size = size;
         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
         vcpu->run->io.count = count;
@@ -4383,36 +3901,37 @@ static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
         return 0;
 }
 
-static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
-                                     int size, unsigned short port,
-                                     const void *val, unsigned int count)
+static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
+                                    int size, unsigned short port, void *val,
+                                    unsigned int count)
 {
         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
+        int ret;
 
-        trace_kvm_pio(1, port, size, count);
-
-        vcpu->arch.pio.port = port;
-        vcpu->arch.pio.in = 0;
-        vcpu->arch.pio.count = count;
-        vcpu->arch.pio.size = size;
-
-        memcpy(vcpu->arch.pio_data, val, size * count);
+        if (vcpu->arch.pio.count)
+                goto data_avail;
 
-        if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
+        ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
+        if (ret) {
+data_avail:
+                memcpy(val, vcpu->arch.pio_data, size * count);
                 vcpu->arch.pio.count = 0;
                 return 1;
         }
 
-        vcpu->run->exit_reason = KVM_EXIT_IO;
-        vcpu->run->io.direction = KVM_EXIT_IO_OUT;
-        vcpu->run->io.size = size;
-        vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
-        vcpu->run->io.count = count;
-        vcpu->run->io.port = port;
-
         return 0;
 }
 
+static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
+                                     int size, unsigned short port,
+                                     const void *val, unsigned int count)
+{
+        struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
+
+        memcpy(vcpu->arch.pio_data, val, size * count);
+        return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
+}
+
 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
 {
         return kvm_x86_ops->get_segment_base(vcpu, seg);
@@ -4627,6 +4146,12 @@ static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
 }
 
+static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
+                             u32 pmc, u64 *pdata)
+{
+        return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
+}
+
 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
 {
         emul_to_vcpu(ctxt)->arch.halt_request = 1;
@@ -4679,6 +4204,7 @@ static struct x86_emulate_ops emulate_ops = {
         .set_dr              = emulator_set_dr,
         .set_msr             = emulator_set_msr,
         .get_msr             = emulator_get_msr,
+        .read_pmc            = emulator_read_pmc,
         .halt                = emulator_halt,
         .wbinvd              = emulator_wbinvd,
         .fix_hypercall       = emulator_fix_hypercall,
@@ -4836,6 +4362,50 @@ static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
         return false;
 }
 
+static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
+                              unsigned long cr2,  int emulation_type)
+{
+        struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
+        unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
+
+        last_retry_eip = vcpu->arch.last_retry_eip;
+        last_retry_addr = vcpu->arch.last_retry_addr;
+
+        /*
+         * If the emulation is caused by #PF and it is non-page_table
+         * writing instruction, it means the VM-EXIT is caused by shadow
+         * page protected, we can zap the shadow page and retry this
+         * instruction directly.
+         *
+         * Note: if the guest uses a non-page-table modifying instruction
+         * on the PDE that points to the instruction, then we will unmap
+         * the instruction and go to an infinite loop. So, we cache the
+         * last retried eip and the last fault address, if we meet the eip
+         * and the address again, we can break out of the potential infinite
+         * loop.
+         */
+        vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
+
+        if (!(emulation_type & EMULTYPE_RETRY))
+                return false;
+
+        if (x86_page_table_writing_insn(ctxt))
+                return false;
+
+        if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
+                return false;
+
+        vcpu->arch.last_retry_eip = ctxt->eip;
+        vcpu->arch.last_retry_addr = cr2;
+
+        if (!vcpu->arch.mmu.direct_map)
+                gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
+
+        kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
+
+        return true;
+}
+
 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
                             unsigned long cr2,
                             int emulation_type,
@@ -4877,6 +4447,9 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
                 return EMULATE_DONE;
         }
 
+        if (retry_instruction(ctxt, cr2, emulation_type))
+                return EMULATE_DONE;
+
         /* this is needed for vmware backdoor interface to work since it
            changes registers values  during IO operation */
         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
@@ -5095,17 +4668,17 @@ static void kvm_timer_init(void)
 
 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
 
-static int kvm_is_in_guest(void)
+int kvm_is_in_guest(void)
 {
-        return percpu_read(current_vcpu) != NULL;
+        return __this_cpu_read(current_vcpu) != NULL;
 }
 
 static int kvm_is_user_mode(void)
 {
         int user_mode = 3;
 
-        if (percpu_read(current_vcpu))
-                user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
+        if (__this_cpu_read(current_vcpu))
+                user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
 
         return user_mode != 0;
 }
@@ -5114,8 +4687,8 @@ static unsigned long kvm_get_guest_ip(void)
 {
         unsigned long ip = 0;
 
-        if (percpu_read(current_vcpu))
-                ip = kvm_rip_read(percpu_read(current_vcpu));
+        if (__this_cpu_read(current_vcpu))
+                ip = kvm_rip_read(__this_cpu_read(current_vcpu));
 
         return ip;
 }
@@ -5128,13 +4701,13 @@ static struct perf_guest_info_callbacks kvm_guest_cbs = {
 
 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
 {
-        percpu_write(current_vcpu, vcpu);
+        __this_cpu_write(current_vcpu, vcpu);
 }
 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
 
 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
 {
-        percpu_write(current_vcpu, NULL);
+        __this_cpu_write(current_vcpu, NULL);
 }
 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
 
@@ -5233,15 +4806,6 @@ int kvm_emulate_halt(struct kvm_vcpu *vcpu)
 }
 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
 
-static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
-                           unsigned long a1)
-{
-        if (is_long_mode(vcpu))
-                return a0;
-        else
-                return a0 | ((gpa_t)a1 << 32);
-}
-
 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
 {
         u64 param, ingpa, outgpa, ret;
@@ -5337,9 +4901,6 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
         case KVM_HC_VAPIC_POLL_IRQ:
                 ret = 0;
                 break;
-        case KVM_HC_MMU_OP:
-                r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
-                break;
         default:
                 ret = -KVM_ENOSYS;
                 break;
@@ -5369,125 +4930,6 @@ int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
 }
 
-static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
-{
-        struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
-        int j, nent = vcpu->arch.cpuid_nent;
-
-        e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
-        /* when no next entry is found, the current entry[i] is reselected */
-        for (j = i + 1; ; j = (j + 1) % nent) {
-                struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
-                if (ej->function == e->function) {
-                        ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
-                        return j;
-                }
-        }
-        return 0; /* silence gcc, even though control never reaches here */
-}
-
-/* find an entry with matching function, matching index (if needed), and that
- * should be read next (if it's stateful) */
-static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
-        u32 function, u32 index)
-{
-        if (e->function != function)
-                return 0;
-        if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
-                return 0;
-        if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
-            !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
-                return 0;
-        return 1;
-}
-
-struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
-                                              u32 function, u32 index)
-{
-        int i;
-        struct kvm_cpuid_entry2 *best = NULL;
-
-        for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
-                struct kvm_cpuid_entry2 *e;
-
-                e = &vcpu->arch.cpuid_entries[i];
-                if (is_matching_cpuid_entry(e, function, index)) {
-                        if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
-                                move_to_next_stateful_cpuid_entry(vcpu, i);
-                        best = e;
-                        break;
-                }
-        }
-        return best;
-}
-EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
-
-int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
-{
-        struct kvm_cpuid_entry2 *best;
-
-        best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
-        if (!best || best->eax < 0x80000008)
-                goto not_found;
-        best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
-        if (best)
-                return best->eax & 0xff;
-not_found:
-        return 36;
-}
-
-/*
- * If no match is found, check whether we exceed the vCPU's limit
- * and return the content of the highest valid _standard_ leaf instead.
- * This is to satisfy the CPUID specification.
- */
-static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
-                                                  u32 function, u32 index)
-{
-        struct kvm_cpuid_entry2 *maxlevel;
-
-        maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
-        if (!maxlevel || maxlevel->eax >= function)
-                return NULL;
-        if (function & 0x80000000) {
-                maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
-                if (!maxlevel)
-                        return NULL;
-        }
-        return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
-}
-
-void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
-{
-        u32 function, index;
-        struct kvm_cpuid_entry2 *best;
-
-        function = kvm_register_read(vcpu, VCPU_REGS_RAX);
-        index = kvm_register_read(vcpu, VCPU_REGS_RCX);
-        kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
-        kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
-        kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
-        kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
-        best = kvm_find_cpuid_entry(vcpu, function, index);
-
-        if (!best)
-                best = check_cpuid_limit(vcpu, function, index);
-
-        if (best) {
-                kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
-                kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
-                kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
-                kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
-        }
-        kvm_x86_ops->skip_emulated_instruction(vcpu);
-        trace_kvm_cpuid(function,
-                        kvm_register_read(vcpu, VCPU_REGS_RAX),
-                        kvm_register_read(vcpu, VCPU_REGS_RBX),
-                        kvm_register_read(vcpu, VCPU_REGS_RCX),
-                        kvm_register_read(vcpu, VCPU_REGS_RDX));
-}
-EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
-
 /*
  * Check if userspace requested an interrupt window, and that the
  * interrupt window is open.
@@ -5648,6 +5090,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
         int r;
         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
                 vcpu->run->request_interrupt_window;
+        bool req_immediate_exit = 0;
 
         if (vcpu->requests) {
                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
@@ -5687,7 +5130,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                         record_steal_time(vcpu);
                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
                         process_nmi(vcpu);
-
+                req_immediate_exit =
+                        kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
+                if (kvm_check_request(KVM_REQ_PMU, vcpu))
+                        kvm_handle_pmu_event(vcpu);
+                if (kvm_check_request(KVM_REQ_PMI, vcpu))
+                        kvm_deliver_pmi(vcpu);
         }
 
         r = kvm_mmu_reload(vcpu);
@@ -5738,6 +5186,9 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
 
         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
 
+        if (req_immediate_exit)
+                smp_send_reschedule(vcpu->cpu);
+
         kvm_guest_enter();
 
         if (unlikely(vcpu->arch.switch_db_regs)) {
@@ -5943,10 +5394,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
         if (r <= 0)
                 goto out;
 
-        if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
-                kvm_register_write(vcpu, VCPU_REGS_RAX,
-                                     kvm_run->hypercall.ret);
-
         r = __vcpu_run(vcpu);
 
 out:
@@ -6148,7 +5595,7 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
         if (sregs->cr4 & X86_CR4_OSXSAVE)
-                update_cpuid(vcpu);
+                kvm_update_cpuid(vcpu);
 
         idx = srcu_read_lock(&vcpu->kvm->srcu);
         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
@@ -6425,6 +5872,8 @@ int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
         kvm_async_pf_hash_reset(vcpu);
         vcpu->arch.apf.halted = false;
 
+        kvm_pmu_reset(vcpu);
+
         return kvm_x86_ops->vcpu_reset(vcpu);
 }
 
@@ -6473,10 +5922,6 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         kvm = vcpu->kvm;
 
         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
-        vcpu->arch.walk_mmu = &vcpu->arch.mmu;
-        vcpu->arch.mmu.root_hpa = INVALID_PAGE;
-        vcpu->arch.mmu.translate_gpa = translate_gpa;
-        vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
         else
@@ -6513,6 +5958,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
                 goto fail_free_mce_banks;
 
         kvm_async_pf_hash_reset(vcpu);
+        kvm_pmu_init(vcpu);
 
         return 0;
 fail_free_mce_banks:
@@ -6531,6 +5977,7 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
 {
         int idx;
 
+        kvm_pmu_destroy(vcpu);
         kfree(vcpu->arch.mce_banks);
         kvm_free_lapic(vcpu);
         idx = srcu_read_lock(&vcpu->kvm->srcu);
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index d36fe237c66..cb80c293cdd 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -33,9 +33,6 @@ static inline bool kvm_exception_is_soft(unsigned int nr)
         return (nr == BP_VECTOR) || (nr == OF_VECTOR);
 }
 
-struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
-                                             u32 function, u32 index);
-
 static inline bool is_protmode(struct kvm_vcpu *vcpu)
 {
         return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
@@ -125,4 +122,6 @@ int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
         gva_t addr, void *val, unsigned int bytes,
         struct x86_exception *exception);
 
+extern u64 host_xcr0;
+
 #endif
diff --git a/arch/x86/platform/mrst/early_printk_mrst.c b/arch/x86/platform/mrst/early_printk_mrst.c
index 25bfdbb5b13..3c6e328483c 100644
--- a/arch/x86/platform/mrst/early_printk_mrst.c
+++ b/arch/x86/platform/mrst/early_printk_mrst.c
@@ -245,16 +245,24 @@ struct console early_mrst_console = {
  * Following is the early console based on Medfield HSU (High
  * Speed UART) device.
  */
-#define HSU_PORT2_PADDR         0xffa28180
+#define HSU_PORT_BASE           0xffa28080
 
 static void __iomem *phsu;
 
-void hsu_early_console_init(void)
+void hsu_early_console_init(const char *s)
 {
+        unsigned long paddr, port = 0;
         u8 lcr;
 
-        phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
-                                                        HSU_PORT2_PADDR);
+        /*
+         * Select the early HSU console port if specified by user in the
+         * kernel command line.
+         */
+        if (*s && !kstrtoul(s, 10, &port))
+                port = clamp_val(port, 0, 2);
+
+        paddr = HSU_PORT_BASE + port * 0x80;
+        phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
 
         /* Disable FIFO */
         writeb(0x0, phsu + UART_FCR);
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 26c731a106a..fdce49c7aff 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -29,7 +29,8 @@ config XEN_PVHVM
 
 config XEN_MAX_DOMAIN_MEMORY
        int
-       default 128
+       default 500 if X86_64
+       default 64 if X86_32
        depends on XEN
        help
          This only affects the sizing of some bss arrays, the unused
@@ -48,3 +49,4 @@ config XEN_DEBUG_FS
         help
           Enable statistics output and various tuning options in debugfs.
           Enabling this option may incur a significant performance overhead.
+
diff --git a/arch/x86/xen/grant-table.c b/arch/x86/xen/grant-table.c
index 5a40d24ba33..3a5f55d5190 100644
--- a/arch/x86/xen/grant-table.c
+++ b/arch/x86/xen/grant-table.c
@@ -54,6 +54,20 @@ static int map_pte_fn(pte_t *pte, struct page *pmd_page,
         return 0;
 }
 
+/*
+ * This function is used to map shared frames to store grant status. It is
+ * different from map_pte_fn above, the frames type here is uint64_t.
+ */
+static int map_pte_fn_status(pte_t *pte, struct page *pmd_page,
+                             unsigned long addr, void *data)
+{
+        uint64_t **frames = (uint64_t **)data;
+
+        set_pte_at(&init_mm, addr, pte, mfn_pte((*frames)[0], PAGE_KERNEL));
+        (*frames)++;
+        return 0;
+}
+
 static int unmap_pte_fn(pte_t *pte, struct page *pmd_page,
                         unsigned long addr, void *data)
 {
@@ -64,10 +78,10 @@ static int unmap_pte_fn(pte_t *pte, struct page *pmd_page,
 
 int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
                            unsigned long max_nr_gframes,
-                           struct grant_entry **__shared)
+                           void **__shared)
 {
         int rc;
-        struct grant_entry *shared = *__shared;
+        void *shared = *__shared;
 
         if (shared == NULL) {
                 struct vm_struct *area =
@@ -83,8 +97,30 @@ int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
         return rc;
 }
 
-void arch_gnttab_unmap_shared(struct grant_entry *shared,
-                              unsigned long nr_gframes)
+int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           grant_status_t **__shared)
+{
+        int rc;
+        grant_status_t *shared = *__shared;
+
+        if (shared == NULL) {
+                /* No need to pass in PTE as we are going to do it
+                 * in apply_to_page_range anyhow. */
+                struct vm_struct *area =
+                        alloc_vm_area(PAGE_SIZE * max_nr_gframes, NULL);
+                BUG_ON(area == NULL);
+                shared = area->addr;
+                *__shared = shared;
+        }
+
+        rc = apply_to_page_range(&init_mm, (unsigned long)shared,
+                                 PAGE_SIZE * nr_gframes,
+                                 map_pte_fn_status, &frames);
+        return rc;
+}
+
+void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
 {
         apply_to_page_range(&init_mm, (unsigned long)shared,
                             PAGE_SIZE * nr_gframes, unmap_pte_fn, NULL);
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index f4bf8aa574f..58a0e46c404 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -1852,7 +1852,7 @@ pgd_t * __init xen_setup_kernel_pagetable(pgd_t *pgd,
         xen_write_cr3(__pa(initial_page_table));
 
         memblock_reserve(__pa(xen_start_info->pt_base),
-                         xen_start_info->nr_pt_frames * PAGE_SIZE));
+                         xen_start_info->nr_pt_frames * PAGE_SIZE);
 
         return initial_page_table;
 }