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-rw-r--r--arch/arm/mach-s5pc100/clock.c287
1 files changed, 175 insertions, 112 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index c4c74893f53..247194dd366 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -427,24 +427,6 @@ static struct clk init_clocks_off[] = {
427 .enable = s5pc100_d0_2_ctrl, 427 .enable = s5pc100_d0_2_ctrl,
428 .ctrlbit = (1 << 1), 428 .ctrlbit = (1 << 1),
429 }, { 429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.2",
432 .parent = &clk_div_d1_bus.clk,
433 .enable = s5pc100_d1_0_ctrl,
434 .ctrlbit = (1 << 7),
435 }, {
436 .name = "hsmmc",
437 .devname = "s3c-sdhci.1",
438 .parent = &clk_div_d1_bus.clk,
439 .enable = s5pc100_d1_0_ctrl,
440 .ctrlbit = (1 << 6),
441 }, {
442 .name = "hsmmc",
443 .devname = "s3c-sdhci.0",
444 .parent = &clk_div_d1_bus.clk,
445 .enable = s5pc100_d1_0_ctrl,
446 .ctrlbit = (1 << 5),
447 }, {
448 .name = "modemif", 430 .name = "modemif",
449 .parent = &clk_div_d1_bus.clk, 431 .parent = &clk_div_d1_bus.clk,
450 .enable = s5pc100_d1_0_ctrl, 432 .enable = s5pc100_d1_0_ctrl,
@@ -674,24 +656,6 @@ static struct clk init_clocks_off[] = {
674 .enable = s5pc100_d1_5_ctrl, 656 .enable = s5pc100_d1_5_ctrl,
675 .ctrlbit = (1 << 8), 657 .ctrlbit = (1 << 8),
676 }, { 658 }, {
677 .name = "spi_48m",
678 .devname = "s3c64xx-spi.0",
679 .parent = &clk_mout_48m.clk,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = (1 << 7),
682 }, {
683 .name = "spi_48m",
684 .devname = "s3c64xx-spi.1",
685 .parent = &clk_mout_48m.clk,
686 .enable = s5pc100_sclk0_ctrl,
687 .ctrlbit = (1 << 8),
688 }, {
689 .name = "spi_48m",
690 .devname = "s3c64xx-spi.2",
691 .parent = &clk_mout_48m.clk,
692 .enable = s5pc100_sclk0_ctrl,
693 .ctrlbit = (1 << 9),
694 }, {
695 .name = "mmc_48m", 659 .name = "mmc_48m",
696 .devname = "s3c-sdhci.0", 660 .devname = "s3c-sdhci.0",
697 .parent = &clk_mout_48m.clk, 661 .parent = &clk_mout_48m.clk,
@@ -712,6 +676,54 @@ static struct clk init_clocks_off[] = {
712 }, 676 },
713}; 677};
714 678
679static struct clk clk_hsmmc2 = {
680 .name = "hsmmc",
681 .devname = "s3c-sdhci.2",
682 .parent = &clk_div_d1_bus.clk,
683 .enable = s5pc100_d1_0_ctrl,
684 .ctrlbit = (1 << 7),
685};
686
687static struct clk clk_hsmmc1 = {
688 .name = "hsmmc",
689 .devname = "s3c-sdhci.1",
690 .parent = &clk_div_d1_bus.clk,
691 .enable = s5pc100_d1_0_ctrl,
692 .ctrlbit = (1 << 6),
693};
694
695static struct clk clk_hsmmc0 = {
696 .name = "hsmmc",
697 .devname = "s3c-sdhci.0",
698 .parent = &clk_div_d1_bus.clk,
699 .enable = s5pc100_d1_0_ctrl,
700 .ctrlbit = (1 << 5),
701};
702
703static struct clk clk_48m_spi0 = {
704 .name = "spi_48m",
705 .devname = "s3c64xx-spi.0",
706 .parent = &clk_mout_48m.clk,
707 .enable = s5pc100_sclk0_ctrl,
708 .ctrlbit = (1 << 7),
709};
710
711static struct clk clk_48m_spi1 = {
712 .name = "spi_48m",
713 .devname = "s3c64xx-spi.1",
714 .parent = &clk_mout_48m.clk,
715 .enable = s5pc100_sclk0_ctrl,
716 .ctrlbit = (1 << 8),
717};
718
719static struct clk clk_48m_spi2 = {
720 .name = "spi_48m",
721 .devname = "s3c64xx-spi.2",
722 .parent = &clk_mout_48m.clk,
723 .enable = s5pc100_sclk0_ctrl,
724 .ctrlbit = (1 << 9),
725};
726
715static struct clk clk_vclk54m = { 727static struct clk clk_vclk54m = {
716 .name = "vclk_54m", 728 .name = "vclk_54m",
717 .rate = 54000000, 729 .rate = 54000000,
@@ -930,49 +942,6 @@ static struct clksrc_clk clk_sclk_spdif = {
930static struct clksrc_clk clksrcs[] = { 942static struct clksrc_clk clksrcs[] = {
931 { 943 {
932 .clk = { 944 .clk = {
933 .name = "sclk_spi",
934 .devname = "s3c64xx-spi.0",
935 .ctrlbit = (1 << 4),
936 .enable = s5pc100_sclk0_ctrl,
937
938 },
939 .sources = &clk_src_group1,
940 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
941 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
942 }, {
943 .clk = {
944 .name = "sclk_spi",
945 .devname = "s3c64xx-spi.1",
946 .ctrlbit = (1 << 5),
947 .enable = s5pc100_sclk0_ctrl,
948
949 },
950 .sources = &clk_src_group1,
951 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
952 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
953 }, {
954 .clk = {
955 .name = "sclk_spi",
956 .devname = "s3c64xx-spi.2",
957 .ctrlbit = (1 << 6),
958 .enable = s5pc100_sclk0_ctrl,
959
960 },
961 .sources = &clk_src_group1,
962 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
963 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
964 }, {
965 .clk = {
966 .name = "uclk1",
967 .ctrlbit = (1 << 3),
968 .enable = s5pc100_sclk0_ctrl,
969
970 },
971 .sources = &clk_src_group2,
972 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
973 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
974 }, {
975 .clk = {
976 .name = "sclk_mixer", 945 .name = "sclk_mixer",
977 .ctrlbit = (1 << 6), 946 .ctrlbit = (1 << 6),
978 .enable = s5pc100_sclk0_ctrl, 947 .enable = s5pc100_sclk0_ctrl,
@@ -1025,39 +994,6 @@ static struct clksrc_clk clksrcs[] = {
1025 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 994 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1026 }, { 995 }, {
1027 .clk = { 996 .clk = {
1028 .name = "sclk_mmc",
1029 .devname = "s3c-sdhci.0",
1030 .ctrlbit = (1 << 12),
1031 .enable = s5pc100_sclk1_ctrl,
1032
1033 },
1034 .sources = &clk_src_mmc0,
1035 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1036 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1037 }, {
1038 .clk = {
1039 .name = "sclk_mmc",
1040 .devname = "s3c-sdhci.1",
1041 .ctrlbit = (1 << 13),
1042 .enable = s5pc100_sclk1_ctrl,
1043
1044 },
1045 .sources = &clk_src_mmc12,
1046 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1047 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1048 }, {
1049 .clk = {
1050 .name = "sclk_mmc",
1051 .devname = "s3c-sdhci.2",
1052 .ctrlbit = (1 << 14),
1053 .enable = s5pc100_sclk1_ctrl,
1054
1055 },
1056 .sources = &clk_src_mmc12,
1057 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1058 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1059 }, {
1060 .clk = {
1061 .name = "sclk_irda", 997 .name = "sclk_irda",
1062 .ctrlbit = (1 << 10), 998 .ctrlbit = (1 << 10),
1063 .enable = s5pc100_sclk0_ctrl, 999 .enable = s5pc100_sclk0_ctrl,
@@ -1099,6 +1035,89 @@ static struct clksrc_clk clksrcs[] = {
1099 }, 1035 },
1100}; 1036};
1101 1037
1038static struct clksrc_clk clk_sclk_uart = {
1039 .clk = {
1040 .name = "uclk1",
1041 .ctrlbit = (1 << 3),
1042 .enable = s5pc100_sclk0_ctrl,
1043 },
1044 .sources = &clk_src_group2,
1045 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1046 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1047};
1048
1049static struct clksrc_clk clk_sclk_mmc0 = {
1050 .clk = {
1051 .name = "sclk_mmc",
1052 .devname = "s3c-sdhci.0",
1053 .ctrlbit = (1 << 12),
1054 .enable = s5pc100_sclk1_ctrl,
1055 },
1056 .sources = &clk_src_mmc0,
1057 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1058 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1059};
1060
1061static struct clksrc_clk clk_sclk_mmc1 = {
1062 .clk = {
1063 .name = "sclk_mmc",
1064 .devname = "s3c-sdhci.1",
1065 .ctrlbit = (1 << 13),
1066 .enable = s5pc100_sclk1_ctrl,
1067 },
1068 .sources = &clk_src_mmc12,
1069 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1070 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1071};
1072
1073static struct clksrc_clk clk_sclk_mmc2 = {
1074 .clk = {
1075 .name = "sclk_mmc",
1076 .devname = "s3c-sdhci.2",
1077 .ctrlbit = (1 << 14),
1078 .enable = s5pc100_sclk1_ctrl,
1079 },
1080 .sources = &clk_src_mmc12,
1081 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1082 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1083};
1084
1085static struct clksrc_clk clk_sclk_spi0 = {
1086 .clk = {
1087 .name = "sclk_spi",
1088 .devname = "s3c64xx-spi.0",
1089 .ctrlbit = (1 << 4),
1090 .enable = s5pc100_sclk0_ctrl,
1091 },
1092 .sources = &clk_src_group1,
1093 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1094 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1095};
1096
1097static struct clksrc_clk clk_sclk_spi1 = {
1098 .clk = {
1099 .name = "sclk_spi",
1100 .devname = "s3c64xx-spi.1",
1101 .ctrlbit = (1 << 5),
1102 .enable = s5pc100_sclk0_ctrl,
1103 },
1104 .sources = &clk_src_group1,
1105 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1106 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1107};
1108
1109static struct clksrc_clk clk_sclk_spi2 = {
1110 .clk = {
1111 .name = "sclk_spi",
1112 .devname = "s3c64xx-spi.2",
1113 .ctrlbit = (1 << 6),
1114 .enable = s5pc100_sclk0_ctrl,
1115 },
1116 .sources = &clk_src_group1,
1117 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1118 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1119};
1120
1102/* Clock initialisation code */ 1121/* Clock initialisation code */
1103static struct clksrc_clk *sysclks[] = { 1122static struct clksrc_clk *sysclks[] = {
1104 &clk_mout_apll, 1123 &clk_mout_apll,
@@ -1128,6 +1147,25 @@ static struct clksrc_clk *sysclks[] = {
1128 &clk_sclk_spdif, 1147 &clk_sclk_spdif,
1129}; 1148};
1130 1149
1150static struct clk *clk_cdev[] = {
1151 &clk_hsmmc0,
1152 &clk_hsmmc1,
1153 &clk_hsmmc2,
1154 &clk_48m_spi0,
1155 &clk_48m_spi1,
1156 &clk_48m_spi2,
1157};
1158
1159static struct clksrc_clk *clksrc_cdev[] = {
1160 &clk_sclk_uart,
1161 &clk_sclk_mmc0,
1162 &clk_sclk_mmc1,
1163 &clk_sclk_mmc2,
1164 &clk_sclk_spi0,
1165 &clk_sclk_spi1,
1166 &clk_sclk_spi2,
1167};
1168
1131void __init_or_cpufreq s5pc100_setup_clocks(void) 1169void __init_or_cpufreq s5pc100_setup_clocks(void)
1132{ 1170{
1133 unsigned long xtal; 1171 unsigned long xtal;
@@ -1267,6 +1305,24 @@ static struct clk *clks[] __initdata = {
1267 &clk_pcmcdclk1, 1305 &clk_pcmcdclk1,
1268}; 1306};
1269 1307
1308static struct clk_lookup s5pc100_clk_lookup[] = {
1309 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1310 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1311 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1312 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1313 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1314 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1319 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1321 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1323 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1324};
1325
1270void __init s5pc100_register_clocks(void) 1326void __init s5pc100_register_clocks(void)
1271{ 1327{
1272 int ptr; 1328 int ptr;
@@ -1278,9 +1334,16 @@ void __init s5pc100_register_clocks(void)
1278 1334
1279 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1335 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1280 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1336 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1337 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1338 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1281 1339
1282 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1340 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1283 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1341 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1342 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1343
1344 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1345 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1346 s3c_disable_clocks(clk_cdev[ptr], 1);
1284 1347
1285 s3c24xx_register_clock(&dummy_apb_pclk); 1348 s3c24xx_register_clock(&dummy_apb_pclk);
1286 1349
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 05:38:46 -0400