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authorPaul Walmsley <paul@pwsan.com>2011-10-06 15:43:23 -0400
committerKevin Hilman <khilman@ti.com>2011-10-07 16:42:03 -0400
commit3047454475adca98e30e00dfca21021a0de99d78 (patch)
treecb977e689b5a7b67f9b9aed550d14c6cef702e95 /arch
parentb02b917211d50ad5dc13e49c933ef916b10e0d00 (diff)
ARM: OMAP3: PM: restrict erratum i443 handling to OMAP3430 only
Based on the documents that I have here, there doesn't appear to be an equivalent to erratum i443 for OMAP3630, so restrict this one to OMAP34xx chips. Also, explicitly restrict this erratum to EMU and HS devices. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/pm34xx.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index bfa8b8c8171..b2740c5e050 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -407,13 +407,14 @@ void omap_sram_idle(void)
407 omap3_intc_prepare_idle(); 407 omap3_intc_prepare_idle();
408 408
409 /* 409 /*
410 * On EMU/HS devices ROM code restores a SRDC value 410 * On EMU/HS devices ROM code restores a SRDC value
411 * from scratchpad which has automatic self refresh on timeout 411 * from scratchpad which has automatic self refresh on timeout
412 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 412 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
413 * Hence store/restore the SDRC_POWER register here. 413 * Hence store/restore the SDRC_POWER register here.
414 */ 414 */
415 if (omap_rev() >= OMAP3430_REV_ES3_0 && 415 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
416 omap_type() != OMAP2_DEVICE_TYPE_GP && 416 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
417 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
417 core_next_state == PWRDM_POWER_OFF) 418 core_next_state == PWRDM_POWER_OFF)
418 sdrc_pwr = sdrc_read_reg(SDRC_POWER); 419 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
419 420
@@ -430,8 +431,9 @@ void omap_sram_idle(void)
430 omap34xx_do_sram_idle(save_state); 431 omap34xx_do_sram_idle(save_state);
431 432
432 /* Restore normal SDRC POWER settings */ 433 /* Restore normal SDRC POWER settings */
433 if (omap_rev() >= OMAP3430_REV_ES3_0 && 434 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
434 omap_type() != OMAP2_DEVICE_TYPE_GP && 435 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
436 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
435 core_next_state == PWRDM_POWER_OFF) 437 core_next_state == PWRDM_POWER_OFF)
436 sdrc_write_reg(sdrc_pwr, SDRC_POWER); 438 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
437 439