Patched in Tegra support.

1 files changed, 128 insertions, 8 deletions

diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h
index 79da17866fa..f6ae2b2b687 100644
--- a/arch/sparc/include/asm/pgtsrmmu.h
+++ b/arch/sparc/include/asm/pgtsrmmu.h
@@ -139,7 +139,6 @@
          restore %g0, %g0, %g0;
 
 #ifndef __ASSEMBLY__
-extern unsigned long last_valid_pfn;
 
 /* This makes sense. Honest it does - Anton */
 /* XXX Yes but it's ugly as sin.  FIXME. -KMW */
@@ -149,13 +148,78 @@ extern void *srmmu_nocache_pool;
 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
 
 /* Accessing the MMU control register. */
-unsigned int srmmu_get_mmureg(void);
-void srmmu_set_mmureg(unsigned long regval);
-void srmmu_set_ctable_ptr(unsigned long paddr);
-void srmmu_set_context(int context);
-int srmmu_get_context(void);
-unsigned int srmmu_get_fstatus(void);
-unsigned int srmmu_get_faddr(void);
+static inline unsigned int srmmu_get_mmureg(void)
+{
+        unsigned int retval;
+        __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
+                             "=r" (retval) :
+                             "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+static inline void srmmu_set_mmureg(unsigned long regval)
+{
+        __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
+                             "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
+
+}
+
+static inline void srmmu_set_ctable_ptr(unsigned long paddr)
+{
+        paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+                             "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
+                             "i" (ASI_M_MMUREGS) :
+                             "memory");
+}
+
+static inline unsigned long srmmu_get_ctable_ptr(void)
+{
+        unsigned int retval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_CTXTBL_PTR),
+                             "i" (ASI_M_MMUREGS));
+        return (retval & SRMMU_CTX_PMASK) << 4;
+}
+
+static inline void srmmu_set_context(int context)
+{
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+                             "r" (context), "r" (SRMMU_CTX_REG),
+                             "i" (ASI_M_MMUREGS) : "memory");
+}
+
+static inline int srmmu_get_context(void)
+{
+        register int retval;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_CTX_REG),
+                             "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+static inline unsigned int srmmu_get_fstatus(void)
+{
+        unsigned int retval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+static inline unsigned int srmmu_get_faddr(void)
+{
+        unsigned int retval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
+        return retval;
+}
 
 /* This is guaranteed on all SRMMU's. */
 static inline void srmmu_flush_whole_tlb(void)
@@ -166,6 +230,59 @@ static inline void srmmu_flush_whole_tlb(void)
 
 }
 
+/* These flush types are not available on all chips... */
+static inline void srmmu_flush_tlb_ctx(void)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (0x300),        /* Flush TLB ctx.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline void srmmu_flush_tlb_region(unsigned long addr)
+{
+        addr &= SRMMU_PGDIR_MASK;
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (addr | 0x200), /* Flush TLB region.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+
+static inline void srmmu_flush_tlb_segment(unsigned long addr)
+{
+        addr &= SRMMU_REAL_PMD_MASK;
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (addr | 0x100), /* Flush TLB segment.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline void srmmu_flush_tlb_page(unsigned long page)
+{
+        page &= PAGE_MASK;
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (page),        /* Flush TLB page.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+#ifndef CONFIG_SPARC_LEON
+static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
+{
+        unsigned long retval;
+
+        vaddr &= PAGE_MASK;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
+
+        return retval;
+}
+#else
+#define srmmu_hwprobe(addr) srmmu_swprobe(addr, 0)
+#endif
+
 static inline int
 srmmu_get_pte (unsigned long addr)
 {
@@ -177,6 +294,9 @@ srmmu_get_pte (unsigned long addr)
         return entry;
 }
 
+extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
+extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
+
 #endif /* !(__ASSEMBLY__) */
 
 #endif /* !(_SPARC_PGTSRMMU_H) */