Merge commit 'kumar/next' into next

12 files changed, 669 insertions, 117 deletions

diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index f49a2548c5f..021763a32c2 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -9,6 +9,14 @@ menuconfig PPC_83xx
 
 if PPC_83xx
 
+config MPC830x_RDB
+        bool "Freescale MPC830x RDB"
+        select DEFAULT_UIMAGE
+        select PPC_MPC831x
+        select FSL_GTM
+        help
+          This option enables support for the MPC8308 RDB board.
+
 config MPC831x_RDB
         bool "Freescale MPC831x RDB"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index e139c36572e..6e8bbbbcfdf 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -4,6 +4,7 @@
 obj-y                           := misc.o usb.o
 obj-$(CONFIG_SUSPEND)           += suspend.o suspend-asm.o
 obj-$(CONFIG_MCU_MPC8349EMITX)  += mcu_mpc8349emitx.o
+obj-$(CONFIG_MPC830x_RDB)       += mpc830x_rdb.o
 obj-$(CONFIG_MPC831x_RDB)       += mpc831x_rdb.o
 obj-$(CONFIG_MPC832x_RDB)       += mpc832x_rdb.o
 obj-$(CONFIG_MPC834x_MDS)       += mpc834x_mds.o
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
new file mode 100644
index 00000000000..ac102ee9abe
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -0,0 +1,94 @@
+/*
+ * arch/powerpc/platforms/83xx/mpc830x_rdb.c
+ *
+ * Description: MPC830x RDB board specific routines.
+ * This file is based on mpc831x_rdb.c
+ *
+ * Copyright (C) Freescale Semiconductor, Inc. 2009. All rights reserved.
+ * Copyright (C) 2010. Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <asm/time.h>
+#include <asm/ipic.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_pci.h>
+#include <sysdev/fsl_soc.h>
+#include "mpc83xx.h"
+
+/*
+ * Setup the architecture
+ */
+static void __init mpc830x_rdb_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,mpc8308-pcie")
+                mpc83xx_add_bridge(np);
+#endif
+        mpc831x_usb_cfg();
+}
+
+static void __init mpc830x_rdb_init_IRQ(void)
+{
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "ipic");
+        if (!np)
+                return;
+
+        ipic_init(np, 0);
+
+        /* Initialize the default interrupt mapping priorities,
+         * in case the boot rom changed something on us.
+         */
+        ipic_set_default_priority();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc830x_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "MPC8308RDB") ||
+               of_flat_dt_is_compatible(root, "fsl,mpc8308rdb");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .compatible = "simple-bus" },
+        { .compatible = "gianfar" },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+        return 0;
+}
+machine_device_initcall(mpc830x_rdb, declare_of_platform_devices);
+
+define_machine(mpc830x_rdb) {
+        .name                   = "MPC830x RDB",
+        .probe                  = mpc830x_rdb_probe,
+        .setup_arch             = mpc830x_rdb_setup_arch,
+        .init_IRQ               = mpc830x_rdb_init_IRQ,
+        .get_irq                = ipic_get_irq,
+        .restart                = mpc83xx_restart,
+        .time_init              = mpc83xx_time_init,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 3a2ade2e443..bea1f5905ad 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -65,6 +65,14 @@ config MPC85xx_RDB
         help
           This option enables support for the MPC85xx RDB (P2020 RDB) board
 
+config P1022_DS
+        bool "Freescale P1022 DS"
+        select DEFAULT_UIMAGE
+        select CONFIG_PHYS_64BIT        # The DTS has 36-bit addresses
+        select SWIOTLB
+        help
+          This option enables support for the Freescale P1022DS reference board.
+
 config SOCRATES
         bool "Socrates"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 387c128f2c8..a2ec3f8f4d0 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
 obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
 obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
 obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
+obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 494513682d7..da64be19d09 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -158,51 +158,108 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
 extern void __init mpc85xx_smp_init(void);
 #endif
 
-static void __init mpc85xx_mds_setup_arch(void)
+#ifdef CONFIG_QUICC_ENGINE
+static struct of_device_id mpc85xx_qe_ids[] __initdata = {
+        { .type = "qe", },
+        { .compatible = "fsl,qe", },
+        { },
+};
+
+static void __init mpc85xx_publish_qe_devices(void)
 {
         struct device_node *np;
-        static u8 __iomem *bcsr_regs = NULL;
-#ifdef CONFIG_PCI
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
 
-        if (ppc_md.progress)
-                ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
+}
+
+static void __init mpc85xx_mds_reset_ucc_phys(void)
+{
+        struct device_node *np;
+        static u8 __iomem *bcsr_regs;
 
         /* Map BCSR area */
         np = of_find_node_by_name(NULL, "bcsr");
-        if (np != NULL) {
-                struct resource res;
+        if (!np)
+                return;
 
-                of_address_to_resource(np, 0, &res);
-                bcsr_regs = ioremap(res.start, res.end - res.start +1);
-                of_node_put(np);
-        }
+        bcsr_regs = of_iomap(np, 0);
+        of_node_put(np);
+        if (!bcsr_regs)
+                return;
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
+        if (machine_is(mpc8568_mds)) {
+#define BCSR_UCC1_GETH_EN       (0x1 << 7)
+#define BCSR_UCC2_GETH_EN       (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK      (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
+                /* Turn off UCC1 & UCC2 */
+                clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+
+                /* Mode is RGMII, all bits clear */
+                clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+                                         BCSR_UCC2_MODE_MSK);
+
+                /* Turn UCC1 & UCC2 on */
+                setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+        } else if (machine_is(mpc8569_mds)) {
+#define BCSR7_UCC12_GETHnRST    (0x1 << 2)
+#define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
+#define BCSR_UCC_RGMII          (0x1 << 6)
+#define BCSR_UCC_RTBI           (0x1 << 5)
+                /*
+                 * U-Boot mangles interrupt polarity for Marvell PHYs,
+                 * so reset built-in and UEM Marvell PHYs, this puts
+                 * the PHYs into their normal state.
+                 */
+                clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+                setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+                setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+                clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+                for (np = NULL; (np = of_find_compatible_node(np,
+                                                "network",
+                                                "ucc_geth")) != NULL;) {
+                        const unsigned int *prop;
+                        int ucc_num;
+
+                        prop = of_get_property(np, "cell-index", NULL);
+                        if (prop == NULL)
+                                continue;
+
+                        ucc_num = *prop - 1;
+
+                        prop = of_get_property(np, "phy-connection-type", NULL);
+                        if (prop == NULL)
+                                continue;
+
+                        if (strcmp("rtbi", (const char *)prop) == 0)
+                                clrsetbits_8(&bcsr_regs[7 + ucc_num],
+                                        BCSR_UCC_RGMII, BCSR_UCC_RTBI);
                 }
+        } else if (machine_is(p1021_mds)) {
+#define BCSR11_ENET_MICRST     (0x1 << 5)
+                /* Reset Micrel PHY */
+                clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
+                setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
         }
-#endif
 
-#ifdef CONFIG_SMP
-        mpc85xx_smp_init();
-#endif
+        iounmap(bcsr_regs);
+}
+
+static void __init mpc85xx_mds_qe_init(void)
+{
+        struct device_node *np;
 
-#ifdef CONFIG_QUICC_ENGINE
         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
         if (!np) {
                 np = of_find_node_by_name(NULL, "qe");
@@ -210,6 +267,11 @@ static void __init mpc85xx_mds_setup_arch(void)
                         return;
         }
 
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
         qe_reset();
         of_node_put(np);
 
@@ -224,70 +286,7 @@ static void __init mpc85xx_mds_setup_arch(void)
                         par_io_of_config(ucc);
         }
 
-        if (bcsr_regs) {
-                if (machine_is(mpc8568_mds)) {
-#define BCSR_UCC1_GETH_EN       (0x1 << 7)
-#define BCSR_UCC2_GETH_EN       (0x1 << 7)
-#define BCSR_UCC1_MODE_MSK      (0x3 << 4)
-#define BCSR_UCC2_MODE_MSK      (0x3 << 0)
-
-                        /* Turn off UCC1 & UCC2 */
-                        clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                        clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-
-                        /* Mode is RGMII, all bits clear */
-                        clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
-                                                 BCSR_UCC2_MODE_MSK);
-
-                        /* Turn UCC1 & UCC2 on */
-                        setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                        setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-                } else if (machine_is(mpc8569_mds)) {
-#define BCSR7_UCC12_GETHnRST    (0x1 << 2)
-#define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
-#define BCSR_UCC_RGMII          (0x1 << 6)
-#define BCSR_UCC_RTBI           (0x1 << 5)
-                        /*
-                         * U-Boot mangles interrupt polarity for Marvell PHYs,
-                         * so reset built-in and UEM Marvell PHYs, this puts
-                         * the PHYs into their normal state.
-                         */
-                        clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
-                        setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
-
-                        setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
-                        clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
-
-                        for (np = NULL; (np = of_find_compatible_node(np,
-                                                        "network",
-                                                        "ucc_geth")) != NULL;) {
-                                const unsigned int *prop;
-                                int ucc_num;
-
-                                prop = of_get_property(np, "cell-index", NULL);
-                                if (prop == NULL)
-                                        continue;
-
-                                ucc_num = *prop - 1;
-
-                                prop = of_get_property(np, "phy-connection-type", NULL);
-                                if (prop == NULL)
-                                        continue;
-
-                                if (strcmp("rtbi", (const char *)prop) == 0)
-                                        clrsetbits_8(&bcsr_regs[7 + ucc_num],
-                                                BCSR_UCC_RGMII, BCSR_UCC_RTBI);
-                        }
-
-                } else if (machine_is(p1021_mds)) {
-#define BCSR11_ENET_MICRST     (0x1 << 5)
-                        /* Reset Micrel PHY */
-                        clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
-                        setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
-                }
-
-                iounmap(bcsr_regs);
-        }
+        mpc85xx_mds_reset_ucc_phys();
 
         if (machine_is(p1021_mds)) {
 #define MPC85xx_PMUXCR_OFFSET           0x60
@@ -322,8 +321,72 @@ static void __init mpc85xx_mds_setup_arch(void)
                 }
 
         }
+}
+
+static void __init mpc85xx_mds_qeic_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (!np) {
+                np = of_find_node_by_type(NULL, "qeic");
+                if (!np)
+                        return;
+        }
+
+        if (machine_is(p1021_mds))
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+        else
+                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+        of_node_put(np);
+}
+#else
+static void __init mpc85xx_publish_qe_devices(void) { }
+static void __init mpc85xx_mds_qe_init(void) { }
+static void __init mpc85xx_mds_qeic_init(void) { }
 #endif  /* CONFIG_QUICC_ENGINE */
 
+static void __init mpc85xx_mds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct pci_controller *hose;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_node_by_type(np, "pci") {
+                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+                        struct resource rsrc;
+                        of_address_to_resource(np, 0, &rsrc);
+                        if ((rsrc.start & 0xfffff) == 0x8000)
+                                fsl_add_bridge(np, 1);
+                        else
+                                fsl_add_bridge(np, 0);
+
+                        hose = pci_find_hose_for_OF_device(np);
+                        max = min(max, hose->dma_window_base_cur +
+                                        hose->dma_window_size);
+                }
+        }
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+        mpc85xx_mds_qe_init();
+
 #ifdef CONFIG_SWIOTLB
         if (memblock_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
@@ -369,8 +432,6 @@ static struct of_device_id mpc85xx_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
         { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         { .compatible = "fsl,rapidio-delta", },
         { .compatible = "fsl,mpc8548-guts", },
@@ -382,8 +443,6 @@ static struct of_device_id p1021_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
         { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         {},
 };
@@ -395,16 +454,16 @@ static int __init mpc85xx_publish_devices(void)
         if (machine_is(mpc8569_mds))
                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-        /* Publish the QE devices */
         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
+        mpc85xx_publish_qe_devices();
 
         return 0;
 }
 
 static int __init p1021_publish_devices(void)
 {
-        /* Publish the QE devices */
         of_platform_bus_probe(NULL, p1021_ids, NULL);
+        mpc85xx_publish_qe_devices();
 
         return 0;
 }
@@ -441,21 +500,7 @@ static void __init mpc85xx_mds_pic_init(void)
         of_node_put(np);
 
         mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        if (machine_is(p1021_mds))
-                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-                                qe_ic_cascade_high_mpic);
-        else
-                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
+        mpc85xx_mds_qeic_init();
 }
 
 static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
new file mode 100644
index 00000000000..e1467c93745
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -0,0 +1,148 @@
+/*
+ * P1022DS board specific routines
+ *
+ * Authors: Travis Wheatley <travis.wheatley@freescale.com>
+ *          Dave Liu <daveliu@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is taken from the Freescale P1022DS BSP, with modifications:
+ * 1) No DIU support (pending rewrite of DIU code)
+ * 2) No AMP support
+ * 3) No PCI endpoint support
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <linux/lmb.h>
+
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+void __init p1022_ds_pic_init(void)
+{
+        struct mpic *mpic;
+        struct resource r;
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "open-pic");
+        if (!np) {
+                pr_err("Could not find open-pic node\n");
+                return;
+        }
+
+        if (of_address_to_resource(np, 0, &r)) {
+                pr_err("Failed to map mpic register space\n");
+                of_node_put(np);
+                return;
+        }
+
+        mpic = mpic_alloc(np, r.start,
+                MPIC_PRIMARY | MPIC_WANTS_RESET |
+                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                MPIC_SINGLE_DEST_CPU,
+                0, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        of_node_put(np);
+
+        mpic_init(mpic);
+}
+
+#ifdef CONFIG_SMP
+void __init mpc85xx_smp_init(void);
+#endif
+
+/*
+ * Setup the architecture
+ */
+static void __init p1022_ds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("p1022_ds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
+                struct resource rsrc;
+                struct pci_controller *hose;
+
+                of_address_to_resource(np, 0, &rsrc);
+
+                if ((rsrc.start & 0xfffff) == 0x8000)
+                        fsl_add_bridge(np, 1);
+                else
+                        fsl_add_bridge(np, 0);
+
+                hose = pci_find_hose_for_OF_device(np);
+                max = min(max, hose->dma_window_base_cur +
+                          hose->dma_window_size);
+        }
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+#ifdef CONFIG_SWIOTLB
+        if (lmb_end_of_DRAM() > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+
+        pr_info("Freescale P1022 DS reference board\n");
+}
+
+static struct of_device_id __initdata p1022_ds_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus", },
+        { .compatible = "gianfar", },
+        {},
+};
+
+static int __init p1022_ds_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
+}
+machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+
+machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p1022_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,p1022ds");
+}
+
+define_machine(p1022_ds) {
+        .name                   = "P1022 DS",
+        .probe                  = p1022_ds_probe,
+        .setup_arch             = p1022_ds_setup_arch,
+        .init_IRQ               = p1022_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 4c3cde911c7..a6b106557be 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/of.h>
+#include <linux/kexec.h>
 
 #include <asm/machdep.h>
 #include <asm/pgtable.h>
@@ -24,6 +25,7 @@
 #include <asm/dbell.h>
 
 #include <sysdev/fsl_soc.h>
+#include <sysdev/mpic.h>
 
 extern void __early_start(void);
 
@@ -105,8 +107,64 @@ smp_85xx_setup_cpu(int cpu_nr)
 
 struct smp_ops_t smp_85xx_ops = {
         .kick_cpu = smp_85xx_kick_cpu,
+#ifdef CONFIG_KEXEC
+        .give_timebase  = smp_generic_give_timebase,
+        .take_timebase  = smp_generic_take_timebase,
+#endif
 };
 
+#ifdef CONFIG_KEXEC
+static int kexec_down_cpus = 0;
+
+void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
+{
+        mpic_teardown_this_cpu(1);
+
+        /* When crashing, this gets called on all CPU's we only
+         * take down the non-boot cpus */
+        if (smp_processor_id() != boot_cpuid)
+        {
+                local_irq_disable();
+                kexec_down_cpus++;
+
+                while (1);
+        }
+}
+
+static void mpc85xx_smp_kexec_down(void *arg)
+{
+        if (ppc_md.kexec_cpu_down)
+                ppc_md.kexec_cpu_down(0,1);
+}
+
+static void mpc85xx_smp_machine_kexec(struct kimage *image)
+{
+        int timeout = 2000;
+        int i;
+
+        set_cpus_allowed(current, cpumask_of_cpu(boot_cpuid));
+
+        smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
+
+        while ( (kexec_down_cpus != (num_online_cpus() - 1)) &&
+                ( timeout > 0 ) )
+        {
+                timeout--;
+        }
+
+        if ( !timeout )
+                printk(KERN_ERR "Unable to bring down secondary cpu(s)");
+
+        for (i = 0; i < num_present_cpus(); i++)
+        {
+                if ( i == smp_processor_id() ) continue;
+                mpic_reset_core(i);
+        }
+
+        default_machine_kexec(image);
+}
+#endif /* CONFIG_KEXEC */
+
 void __init mpc85xx_smp_init(void)
 {
         struct device_node *np;
@@ -124,4 +182,9 @@ void __init mpc85xx_smp_init(void)
         BUG_ON(!smp_85xx_ops.message_pass);
 
         smp_ops = &smp_85xx_ops;
+
+#ifdef CONFIG_KEXEC
+        ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
+        ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
+#endif
 }
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 5b0ab9966e9..8f29bbce536 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -151,6 +151,27 @@ static void tqm85xx_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
+static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
+{
+        unsigned int val;
+
+        /* Do not do the fixup on other platforms! */
+        if (!machine_is(tqm85xx))
+                return;
+
+        dev_info(&pdev->dev, "Using TI 1520 fixup on TQM85xx\n");
+
+        /*
+         * Enable P2CCLK bit in system control register
+         * to enable CLOCK output to power chip
+         */
+        pci_read_config_dword(pdev, 0x80, &val);
+        pci_write_config_dword(pdev, 0x80, val | (1 << 27));
+
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
+                tqm85xx_ti1520_fixup);
+
 static struct of_device_id __initdata of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 48a920a98e7..dd35ce081cf 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -55,6 +55,12 @@ config PPC_MGSUVD
         help
           This enables support for the Keymile MGSUVD board.
 
+config TQM8XX
+        bool "TQM8XX"
+        select CPM1
+        help
+          support for the mpc8xx based boards from TQM.
+
 endchoice
 
 menu "Freescale Ethernet driver platform-specific options"
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile
index bdbfd749601..a491fe6b94f 100644
--- a/arch/powerpc/platforms/8xx/Makefile
+++ b/arch/powerpc/platforms/8xx/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_MPC86XADS)   += mpc86xads_setup.o
 obj-$(CONFIG_PPC_EP88XC)  += ep88xc.o
 obj-$(CONFIG_PPC_ADDER875) += adder875.o
 obj-$(CONFIG_PPC_MGSUVD) += mgsuvd.o
+obj-$(CONFIG_TQM8XX)      += tqm8xx_setup.o
diff --git a/arch/powerpc/platforms/8xx/tqm8xx_setup.c b/arch/powerpc/platforms/8xx/tqm8xx_setup.c
new file mode 100644
index 00000000000..b71c650fbb1
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/tqm8xx_setup.c
@@ -0,0 +1,156 @@
+/*
+ * Platform setup for the MPC8xx based boards from TQM.
+ *
+ * Heiko Schocher <hs@denx.de>
+ * Copyright 2010 DENX Software Engineering GmbH
+ *
+ * based on:
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * Heavily modified by Scott Wood <scottwood@freescale.com>
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/fs_uart_pd.h>
+#include <linux/fsl_devices.h>
+#include <linux/mii.h>
+#include <linux/of_platform.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <asm/cpm1.h>
+#include <asm/fs_pd.h>
+#include <asm/udbg.h>
+
+#include "mpc8xx.h"
+
+struct cpm_pin {
+        int port, pin, flags;
+};
+
+static struct __initdata cpm_pin tqm8xx_pins[] = {
+        /* SMC1 */
+        {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
+        {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
+
+        /* SCC1 */
+        {CPM_PORTA, 5, CPM_PIN_INPUT}, /* CLK1 */
+        {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
+        {CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
+        {CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
+        {CPM_PORTC, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
+        {CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
+        {CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
+};
+
+static struct __initdata cpm_pin tqm8xx_fec_pins[] = {
+        /* MII */
+        {CPM_PORTD, 3, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 4, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 5, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 6, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 7, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 8, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 9, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 10, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 11, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 12, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 13, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 14, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 15, CPM_PIN_OUTPUT},
+};
+
+static void __init init_pins(int n, struct cpm_pin *pin)
+{
+        int i;
+
+        for (i = 0; i < n; i++) {
+                cpm1_set_pin(pin->port, pin->pin, pin->flags);
+                pin++;
+        }
+}
+
+static void __init init_ioports(void)
+{
+        struct device_node *dnode;
+        struct property *prop;
+        int     len;
+
+        init_pins(ARRAY_SIZE(tqm8xx_pins), &tqm8xx_pins[0]);
+
+        cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
+
+        dnode = of_find_node_by_name(NULL, "aliases");
+        if (dnode == NULL)
+                return;
+        prop = of_find_property(dnode, "ethernet1", &len);
+        if (prop == NULL)
+                return;
+
+        /* init FEC pins */
+        init_pins(ARRAY_SIZE(tqm8xx_fec_pins), &tqm8xx_fec_pins[0]);
+}
+
+static void __init tqm8xx_setup_arch(void)
+{
+        cpm_reset();
+        init_ioports();
+}
+
+static int __init tqm8xx_probe(void)
+{
+        unsigned long node = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(node, "tqc,tqm8xx");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .name = "soc", },
+        { .name = "cpm", },
+        { .name = "localbus", },
+        { .compatible = "simple-bus" },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+        return 0;
+}
+machine_device_initcall(tqm8xx, declare_of_platform_devices);
+
+define_machine(tqm8xx) {
+        .name                   = "TQM8xx",
+        .probe                  = tqm8xx_probe,
+        .setup_arch             = tqm8xx_setup_arch,
+        .init_IRQ               = mpc8xx_pics_init,
+        .get_irq                = mpc8xx_get_irq,
+        .restart                = mpc8xx_restart,
+        .calibrate_decr         = mpc8xx_calibrate_decr,
+        .set_rtc_time           = mpc8xx_set_rtc_time,
+        .get_rtc_time           = mpc8xx_get_rtc_time,
+        .progress               = udbg_progress,
+};