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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-09-01 09:22:39 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:49 -0400
commit0dcdbe6add26719e956299eb519542f7d2f7d0a8 (patch)
tree25e77163c868914e5529670616cba8955942b0ea /arch/mips/txx9
parentae027ead87b13cff99b4f48da7696aa4fe75393b (diff)
MIPS: TXx9: Add TX4939 SoC support
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/pci/pci-tx4939.c create mode 100644 arch/mips/txx9/generic/irq_tx4939.c create mode 100644 arch/mips/txx9/generic/setup_tx4939.c create mode 100644 include/asm-mips/txx9/tx4939.h
Diffstat (limited to 'arch/mips/txx9')
-rw-r--r--arch/mips/txx9/Kconfig7
-rw-r--r--arch/mips/txx9/generic/Makefile1
-rw-r--r--arch/mips/txx9/generic/irq_tx4939.c215
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c460
4 files changed, 683 insertions, 0 deletions
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index aade3348af2..58691a1fe77 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -71,6 +71,13 @@ config SOC_TX4938
71 select PCI_TX4927 71 select PCI_TX4927
72 select GPIO_TXX9 72 select GPIO_TXX9
73 73
74config SOC_TX4939
75 bool
76 select CEVT_TXX9
77 select HAS_TXX9_SERIAL
78 select HW_HAS_PCI
79 select PCI_TX4927
80
74config TOSHIBA_FPCIB0 81config TOSHIBA_FPCIB0
75 bool "FPCIB0 Backplane Support" 82 bool "FPCIB0 Backplane Support"
76 depends on PCI && MACH_TXX9 83 depends on PCI && MACH_TXX9
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 986852cc774..0030d23bef5 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o 7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o 8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o 9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
10obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
10obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
11obj-$(CONFIG_SPI) += spi_eeprom.o 12obj-$(CONFIG_SPI) += spi_eeprom.o
12 13
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
new file mode 100644
index 00000000000..013213a8706
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -0,0 +1,215 @@
1/*
2 * TX4939 irq routines
3 * Based on linux/arch/mips/kernel/irq_txx9.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright 2001, 2003-2005 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ahennessy@mvista.com
9 * source@mvista.com
10 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16/*
17 * TX4939 defines 64 IRQs.
18 * Similer to irq_txx9.c but different register layouts.
19 */
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <asm/irq_cpu.h>
24#include <asm/txx9irq.h>
25#include <asm/txx9/tx4939.h>
26
27/* IRCER : Int. Control Enable */
28#define TXx9_IRCER_ICE 0x00000001
29
30/* IRCR : Int. Control */
31#define TXx9_IRCR_LOW 0x00000000
32#define TXx9_IRCR_HIGH 0x00000001
33#define TXx9_IRCR_DOWN 0x00000002
34#define TXx9_IRCR_UP 0x00000003
35#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
36
37/* IRSCR : Int. Status Control */
38#define TXx9_IRSCR_EIClrE 0x00000100
39#define TXx9_IRSCR_EIClr_MASK 0x0000000f
40
41/* IRCSR : Int. Current Status */
42#define TXx9_IRCSR_IF 0x00010000
43
44#define irc_dlevel 0
45#define irc_elevel 1
46
47static struct {
48 unsigned char level;
49 unsigned char mode;
50} tx4939irq[TX4939_NUM_IR] __read_mostly;
51
52static void tx4939_irq_unmask(unsigned int irq)
53{
54 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
55 u32 __iomem *lvlp;
56 int ofs;
57 if (irq_nr < 32) {
58 irq_nr--;
59 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
60 } else {
61 irq_nr -= 32;
62 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
63 }
64 ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
65 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
66 | (tx4939irq[irq_nr].level << ofs),
67 lvlp);
68}
69
70static inline void tx4939_irq_mask(unsigned int irq)
71{
72 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
73 u32 __iomem *lvlp;
74 int ofs;
75 if (irq_nr < 32) {
76 irq_nr--;
77 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
78 } else {
79 irq_nr -= 32;
80 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
81 }
82 ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
83 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
84 | (irc_dlevel << ofs),
85 lvlp);
86 mmiowb();
87}
88
89static void tx4939_irq_mask_ack(unsigned int irq)
90{
91 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
92
93 tx4939_irq_mask(irq);
94 if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
95 irq_nr--;
96 /* clear edge detection */
97 __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
98 << (irq_nr & 0x10),
99 &tx4939_ircptr->edc.r);
100 }
101}
102
103static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
104{
105 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
106 u32 cr;
107 u32 __iomem *crp;
108 int ofs;
109 int mode;
110
111 if (flow_type & IRQF_TRIGGER_PROBE)
112 return 0;
113 switch (flow_type & IRQF_TRIGGER_MASK) {
114 case IRQF_TRIGGER_RISING:
115 mode = TXx9_IRCR_UP;
116 break;
117 case IRQF_TRIGGER_FALLING:
118 mode = TXx9_IRCR_DOWN;
119 break;
120 case IRQF_TRIGGER_HIGH:
121 mode = TXx9_IRCR_HIGH;
122 break;
123 case IRQF_TRIGGER_LOW:
124 mode = TXx9_IRCR_LOW;
125 break;
126 default:
127 return -EINVAL;
128 }
129 if (irq_nr < 32) {
130 irq_nr--;
131 crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
132 } else {
133 irq_nr -= 32;
134 crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
135 }
136 ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
137 cr = __raw_readl(crp);
138 cr &= ~(0x3 << ofs);
139 cr |= (mode & 0x3) << ofs;
140 __raw_writel(cr, crp);
141 tx4939irq[irq_nr].mode = mode;
142 return 0;
143}
144
145static struct irq_chip tx4939_irq_chip = {
146 .name = "TX4939",
147 .ack = tx4939_irq_mask_ack,
148 .mask = tx4939_irq_mask,
149 .mask_ack = tx4939_irq_mask_ack,
150 .unmask = tx4939_irq_unmask,
151 .set_type = tx4939_irq_set_type,
152};
153
154static int tx4939_irq_set_pri(int irc_irq, int new_pri)
155{
156 int old_pri;
157
158 if ((unsigned int)irc_irq >= TX4939_NUM_IR)
159 return 0;
160 old_pri = tx4939irq[irc_irq].level;
161 tx4939irq[irc_irq].level = new_pri;
162 return old_pri;
163}
164
165void __init tx4939_irq_init(void)
166{
167 int i;
168
169 mips_cpu_irq_init();
170 /* disable interrupt control */
171 __raw_writel(0, &tx4939_ircptr->den.r);
172 __raw_writel(0, &tx4939_ircptr->maskint.r);
173 __raw_writel(0, &tx4939_ircptr->maskext.r);
174 /* irq_base + 0 is not used */
175 for (i = 1; i < TX4939_NUM_IR; i++) {
176 tx4939irq[i].level = 4; /* middle level */
177 tx4939irq[i].mode = TXx9_IRCR_LOW;
178 set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
179 &tx4939_irq_chip, handle_level_irq);
180 }
181
182 /* mask all IRC interrupts */
183 __raw_writel(0, &tx4939_ircptr->msk.r);
184 for (i = 0; i < 16; i++)
185 __raw_writel(0, &tx4939_ircptr->lvl[i].r);
186 /* setup IRC interrupt mode (Low Active) */
187 for (i = 0; i < 2; i++)
188 __raw_writel(0, &tx4939_ircptr->dm[i].r);
189 for (i = 0; i < 2; i++)
190 __raw_writel(0, &tx4939_ircptr->dm2[i].r);
191 /* enable interrupt control */
192 __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
193 __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
194
195 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
196 handle_simple_irq);
197
198 /* raise priority for errors, timers, sio */
199 tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
200 tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
201 tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
202 for (i = 0; i < TX4939_NUM_IR_TMR; i++)
203 tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
204 for (i = 0; i < TX4939_NUM_IR_SIO; i++)
205 tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
206}
207
208int tx4939_irq(void)
209{
210 u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
211
212 if (likely(!(csr & TXx9_IRCSR_IF)))
213 return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
214 return -1;
215}
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
new file mode 100644
index 00000000000..f14a497077d
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -0,0 +1,460 @@
1/*
2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/netdevice.h>
17#include <linux/notifier.h>
18#include <linux/sysdev.h>
19#include <linux/ethtool.h>
20#include <linux/param.h>
21#include <linux/ptrace.h>
22#include <linux/mtd/physmap.h>
23#include <asm/bootinfo.h>
24#include <asm/reboot.h>
25#include <asm/traps.h>
26#include <asm/txx9irq.h>
27#include <asm/txx9tmr.h>
28#include <asm/txx9/generic.h>
29#include <asm/txx9/tx4939.h>
30
31static void __init tx4939_wdr_init(void)
32{
33 /* report watchdog reset status */
34 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
35 pr_warning("Watchdog reset detected at 0x%lx\n",
36 read_c0_errorepc());
37 /* clear WatchDogReset (W1C) */
38 tx4939_ccfg_set(TX4939_CCFG_WDRST);
39 /* do reset on watchdog */
40 tx4939_ccfg_set(TX4939_CCFG_WR);
41}
42
43void __init tx4939_wdt_init(void)
44{
45 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
46}
47
48static void tx4939_machine_restart(char *command)
49{
50 local_irq_disable();
51 pr_emerg("Rebooting (with %s watchdog reset)...\n",
52 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
53 "external" : "internal");
54 /* clear watchdog status */
55 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
56 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
57 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
58 ;
59 mdelay(10);
60 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
61 pr_emerg("Rebooting (with internal watchdog reset)...\n");
62 /* External WDRST failed. Do internal watchdog reset */
63 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
64 }
65 /* fallback */
66 (*_machine_halt)();
67}
68
69void show_registers(struct pt_regs *regs);
70static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
71{
72 int data = regs->cp0_cause & 4;
73 console_verbose();
74 pr_err("%cBE exception at %#lx\n",
75 data ? 'D' : 'I', regs->cp0_epc);
76 pr_err("ccfg:%llx, toea:%llx\n",
77 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
78 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
79#ifdef CONFIG_PCI
80 tx4927_report_pcic_status();
81#endif
82 show_registers(regs);
83 panic("BusError!");
84}
85static void __init tx4939_be_init(void)
86{
87 board_be_handler = tx4939_be_handler;
88}
89
90static struct resource tx4939_sdram_resource[4];
91static struct resource tx4939_sram_resource;
92#define TX4939_SRAM_SIZE 0x800
93
94void __init tx4939_add_memory_regions(void)
95{
96 int i;
97 unsigned long start, size;
98 u64 win;
99
100 for (i = 0; i < 4; i++) {
101 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
102 continue;
103 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
104 start = (unsigned long)(win >> 48);
105 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
106 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
107 }
108}
109
110void __init tx4939_setup(void)
111{
112 int i;
113 __u32 divmode;
114 __u64 pcfg;
115 int cpuclk = 0;
116
117 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
118 TX4939_REG_SIZE);
119 set_c0_config(TX49_CONF_CWFON);
120
121 /* SDRAMC,EBUSC are configured by PROM */
122 for (i = 0; i < 4; i++) {
123 if (!(TX4939_EBUSC_CR(i) & 0x8))
124 continue; /* disabled */
125 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
126 txx9_ce_res[i].end =
127 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
128 request_resource(&iomem_resource, &txx9_ce_res[i]);
129 }
130
131 /* clocks */
132 if (txx9_master_clock) {
133 /* calculate cpu_clock from master_clock */
134 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
135 TX4939_CCFG_MULCLK_MASK;
136 cpuclk = txx9_master_clock * 20 / 2;
137 switch (divmode) {
138 case TX4939_CCFG_MULCLK_8:
139 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
140 case TX4939_CCFG_MULCLK_9:
141 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
142 case TX4939_CCFG_MULCLK_10:
143 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
144 case TX4939_CCFG_MULCLK_11:
145 cpuclk = cpuclk / 6 * 11; break;
146 case TX4939_CCFG_MULCLK_12:
147 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
148 case TX4939_CCFG_MULCLK_13:
149 cpuclk = cpuclk / 6 * 13; break;
150 case TX4939_CCFG_MULCLK_14:
151 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
152 case TX4939_CCFG_MULCLK_15:
153 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
154 }
155 txx9_cpu_clock = cpuclk;
156 } else {
157 if (txx9_cpu_clock == 0)
158 txx9_cpu_clock = 400000000; /* 400MHz */
159 /* calculate master_clock from cpu_clock */
160 cpuclk = txx9_cpu_clock;
161 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
162 TX4939_CCFG_MULCLK_MASK;
163 switch (divmode) {
164 case TX4939_CCFG_MULCLK_8:
165 txx9_master_clock = cpuclk * 6 / 8; break;
166 case TX4939_CCFG_MULCLK_9:
167 txx9_master_clock = cpuclk * 6 / 9; break;
168 case TX4939_CCFG_MULCLK_10:
169 txx9_master_clock = cpuclk * 6 / 10; break;
170 case TX4939_CCFG_MULCLK_11:
171 txx9_master_clock = cpuclk * 6 / 11; break;
172 case TX4939_CCFG_MULCLK_12:
173 txx9_master_clock = cpuclk * 6 / 12; break;
174 case TX4939_CCFG_MULCLK_13:
175 txx9_master_clock = cpuclk * 6 / 13; break;
176 case TX4939_CCFG_MULCLK_14:
177 txx9_master_clock = cpuclk * 6 / 14; break;
178 case TX4939_CCFG_MULCLK_15:
179 txx9_master_clock = cpuclk * 6 / 15; break;
180 }
181 txx9_master_clock /= 10; /* * 2 / 20 */
182 }
183 /* calculate gbus_clock from cpu_clock */
184 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
185 TX4939_CCFG_YDIVMODE_MASK;
186 txx9_gbus_clock = txx9_cpu_clock;
187 switch (divmode) {
188 case TX4939_CCFG_YDIVMODE_2:
189 txx9_gbus_clock /= 2; break;
190 case TX4939_CCFG_YDIVMODE_3:
191 txx9_gbus_clock /= 3; break;
192 case TX4939_CCFG_YDIVMODE_5:
193 txx9_gbus_clock /= 5; break;
194 case TX4939_CCFG_YDIVMODE_6:
195 txx9_gbus_clock /= 6; break;
196 }
197 /* change default value to udelay/mdelay take reasonable time */
198 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
199
200 /* CCFG */
201 tx4939_wdr_init();
202 /* clear BusErrorOnWrite flag (W1C) */
203 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
204 /* enable Timeout BusError */
205 if (txx9_ccfg_toeon)
206 tx4939_ccfg_set(TX4939_CCFG_TOE);
207
208 /* DMA selection */
209 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
210
211 /* Use external clock for external arbiter */
212 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
213 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
214
215 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
216 txx9_pcode_str,
217 (cpuclk + 500000) / 1000000,
218 (txx9_master_clock + 500000) / 1000000,
219 (txx9_gbus_clock + 500000) / 1000000,
220 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
221 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
222 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
223
224 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
225 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
226 for (i = 0; i < 4; i++) {
227 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
228 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
229 continue; /* disabled */
230 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
231 tx4939_sdram_resource[i].name = "DDR SDRAM";
232 tx4939_sdram_resource[i].start =
233 (unsigned long)(win >> 48) << 20;
234 tx4939_sdram_resource[i].end =
235 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
236 20) - 1;
237 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
238 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
239 }
240 printk(KERN_CONT "\n");
241
242 /* SRAM */
243 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
244 unsigned int size = TX4939_SRAM_SIZE;
245 tx4939_sram_resource.name = "SRAM";
246 tx4939_sram_resource.start =
247 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
248 & ~(size - 1);
249 tx4939_sram_resource.end =
250 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
251 tx4939_sram_resource.flags = IORESOURCE_MEM;
252 request_resource(&iomem_resource, &tx4939_sram_resource);
253 }
254
255 /* TMR */
256 /* disable all timers */
257 for (i = 0; i < TX4939_NR_TMR; i++)
258 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
259
260 /* DMA */
261 for (i = 0; i < 2; i++)
262 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
263 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
264
265 /* set PCIC1 reset (required to prevent hangup on BIST) */
266 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
267 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
268 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
269 mdelay(1); /* at least 128 cpu clock */
270 /* clear PCIC1 reset */
271 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
272 } else {
273 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
274 /* stop PCIC1 */
275 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
276 }
277 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
278 pr_info("%s: stop ETH0\n", txx9_pcode_str);
279 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
280 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
281 }
282 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
283 pr_info("%s: stop ETH1\n", txx9_pcode_str);
284 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
285 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
286 }
287
288 _machine_restart = tx4939_machine_restart;
289 board_be_init = tx4939_be_init;
290}
291
292void __init tx4939_time_init(unsigned int tmrnr)
293{
294 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
295 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
296 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
297 TXX9_IMCLK);
298}
299
300void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
301{
302 int i;
303 unsigned int ch_mask = 0;
304 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
305
306 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
307 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
308 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
309 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
310 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
311 if (pcfg & TX4939_PCFG_SIO3MODE)
312 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
313 for (i = 0; i < 4; i++) {
314 if ((1 << i) & ch_mask)
315 continue;
316 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
317 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
318 i, sclk, (1 << i) & cts_mask);
319 }
320}
321
322#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
323static int tx4939_get_eth_speed(struct net_device *dev)
324{
325 struct ethtool_cmd cmd = { ETHTOOL_GSET };
326 int speed = 100; /* default 100Mbps */
327 int err;
328 if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
329 return speed;
330 err = dev->ethtool_ops->get_settings(dev, &cmd);
331 if (err < 0)
332 return speed;
333 speed = cmd.speed == SPEED_100 ? 100 : 10;
334 return speed;
335}
336static int tx4939_netdev_event(struct notifier_block *this,
337 unsigned long event,
338 void *ptr)
339{
340 struct net_device *dev = ptr;
341 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
342 __u64 bit = 0;
343 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
344 bit = TX4939_PCFG_SPEED0;
345 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
346 bit = TX4939_PCFG_SPEED1;
347 if (bit) {
348 int speed = tx4939_get_eth_speed(dev);
349 if (speed == 100)
350 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
351 else
352 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
353 }
354 }
355 return NOTIFY_DONE;
356}
357
358static struct notifier_block tx4939_netdev_notifier = {
359 .notifier_call = tx4939_netdev_event,
360 .priority = 1,
361};
362
363void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
364{
365 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
366
367 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
368 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
369 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
370 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
371 register_netdevice_notifier(&tx4939_netdev_notifier);
372}
373#else
374void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
375{
376}
377#endif
378
379void __init tx4939_mtd_init(int ch)
380{
381 struct physmap_flash_data pdata = {
382 .width = TX4939_EBUSC_WIDTH(ch) / 8,
383 };
384 unsigned long start = txx9_ce_res[ch].start;
385 unsigned long size = txx9_ce_res[ch].end - start + 1;
386
387 if (!(TX4939_EBUSC_CR(ch) & 0x8))
388 return; /* disabled */
389 txx9_physmap_flash_init(ch, start, size, &pdata);
390}
391
392static void __init tx4939_stop_unused_modules(void)
393{
394 __u64 pcfg, rst = 0, ckd = 0;
395 char buf[128];
396
397 buf[0] = '\0';
398 local_irq_disable();
399 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
400 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
401 TX4939_PCFG_I2SMODE_ACLC) {
402 rst |= TX4939_CLKCTR_ACLRST;
403 ckd |= TX4939_CLKCTR_ACLCKD;
404 strcat(buf, " ACLC");
405 }
406 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
407 TX4939_PCFG_I2SMODE_I2S &&
408 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
409 TX4939_PCFG_I2SMODE_I2S_ALT) {
410 rst |= TX4939_CLKCTR_I2SRST;
411 ckd |= TX4939_CLKCTR_I2SCKD;
412 strcat(buf, " I2S");
413 }
414 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
415 rst |= TX4939_CLKCTR_ATA0RST;
416 ckd |= TX4939_CLKCTR_ATA0CKD;
417 strcat(buf, " ATA0");
418 }
419 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
420 rst |= TX4939_CLKCTR_ATA1RST;
421 ckd |= TX4939_CLKCTR_ATA1CKD;
422 strcat(buf, " ATA1");
423 }
424 if (pcfg & TX4939_PCFG_SPIMODE) {
425 rst |= TX4939_CLKCTR_SPIRST;
426 ckd |= TX4939_CLKCTR_SPICKD;
427 strcat(buf, " SPI");
428 }
429 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
430 rst |= TX4939_CLKCTR_VPCRST;
431 ckd |= TX4939_CLKCTR_VPCCKD;
432 strcat(buf, " VPC");
433 }
434 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
435 rst |= TX4939_CLKCTR_SIO2RST;
436 ckd |= TX4939_CLKCTR_SIO2CKD;
437 strcat(buf, " SIO2");
438 }
439 if (pcfg & TX4939_PCFG_SIO3MODE) {
440 rst |= TX4939_CLKCTR_SIO3RST;
441 ckd |= TX4939_CLKCTR_SIO3CKD;
442 strcat(buf, " SIO3");
443 }
444 if (rst | ckd) {
445 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
446 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
447 }
448 local_irq_enable();
449 if (buf[0])
450 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
451}
452
453static int __init tx4939_late_init(void)
454{
455 if (txx9_pcode != 0x4939)
456 return -ENODEV;
457 tx4939_stop_unused_modules();
458 return 0;
459}
460late_initcall(tx4939_late_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 03:44:02 -0500