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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-09-01 09:22:39 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:49 -0400
commit0dcdbe6add26719e956299eb519542f7d2f7d0a8 (patch)
tree25e77163c868914e5529670616cba8955942b0ea
parentae027ead87b13cff99b4f48da7696aa4fe75393b (diff)
MIPS: TXx9: Add TX4939 SoC support
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/pci/pci-tx4939.c create mode 100644 arch/mips/txx9/generic/irq_tx4939.c create mode 100644 arch/mips/txx9/generic/setup_tx4939.c create mode 100644 include/asm-mips/txx9/tx4939.h
Diffstat
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/pci-tx4939.c109
-rw-r--r--arch/mips/txx9/Kconfig7
-rw-r--r--arch/mips/txx9/generic/Makefile1
-rw-r--r--arch/mips/txx9/generic/irq_tx4939.c215
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c460
-rw-r--r--include/asm-mips/txx9/tx4939.h544
7 files changed, 1337 insertions, 0 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c8c32f417b6..b1886244ced 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
45obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o 45obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
46obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o 46obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
47obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o 47obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
48obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o
48obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o 49obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
49obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o 50obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
50obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 51obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
new file mode 100644
index 00000000000..5fecf1cdc32
--- /dev/null
+++ b/arch/mips/pci/pci-tx4939.c
@@ -0,0 +1,109 @@
1/*
2 * linux/arch/mips/pci/pci-tx4939.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * Copyright 2001, 2003-2005 MontaVista Software Inc.
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <asm/txx9/generic.h>
20#include <asm/txx9/tx4939.h>
21
22int __init tx4939_report_pciclk(void)
23{
24 int pciclk = 0;
25
26 pr_info("PCIC --%s PCICLK:",
27 (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
28 " PCI66" : "");
29 if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
30 pciclk = txx9_master_clock * 20 / 6;
31 if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
32 pciclk /= 2;
33 printk(KERN_CONT "Internal(%u.%uMHz)",
34 (pciclk + 50000) / 1000000,
35 ((pciclk + 50000) / 100000) % 10);
36 } else {
37 printk(KERN_CONT "External");
38 pciclk = -1;
39 }
40 printk(KERN_CONT "\n");
41 return pciclk;
42}
43
44void __init tx4939_report_pci1clk(void)
45{
46 unsigned int pciclk = txx9_master_clock * 20 / 6;
47
48 pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
49 (pciclk + 50000) / 1000000,
50 ((pciclk + 50000) / 100000) % 10);
51}
52
53int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
54{
55 if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
56 switch (slot) {
57 case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
58 if (__raw_readq(&tx4939_ccfgptr->pcfg) &
59 TX4939_PCFG_ET0MODE)
60 return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
61 break;
62 case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
63 if (__raw_readq(&tx4939_ccfgptr->pcfg) &
64 TX4939_PCFG_ET1MODE)
65 return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
66 break;
67 }
68 return 0;
69 }
70 return -1;
71}
72
73int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
74{
75 int irq = tx4939_pcic1_map_irq(dev, slot);
76
77 if (irq >= 0)
78 return irq;
79 irq = pin;
80 /* IRQ rotation */
81 irq--; /* 0-3 */
82 irq = (irq + 33 - slot) % 4;
83 irq++; /* 1-4 */
84
85 switch (irq) {
86 case 1:
87 irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
88 break;
89 case 2:
90 irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
91 break;
92 case 3:
93 irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
94 break;
95 case 4:
96 irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
97 break;
98 }
99 return irq;
100}
101
102void __init tx4939_setup_pcierr_irq(void)
103{
104 if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
105 tx4927_pcierr_interrupt,
106 IRQF_DISABLED, "PCI error",
107 (void *)TX4939_PCIC_REG))
108 pr_warning("Failed to request irq for PCIERR\n");
109}
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index aade3348af2..58691a1fe77 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -71,6 +71,13 @@ config SOC_TX4938
71 select PCI_TX4927 71 select PCI_TX4927
72 select GPIO_TXX9 72 select GPIO_TXX9
73 73
74config SOC_TX4939
75 bool
76 select CEVT_TXX9
77 select HAS_TXX9_SERIAL
78 select HW_HAS_PCI
79 select PCI_TX4927
80
74config TOSHIBA_FPCIB0 81config TOSHIBA_FPCIB0
75 bool "FPCIB0 Backplane Support" 82 bool "FPCIB0 Backplane Support"
76 depends on PCI && MACH_TXX9 83 depends on PCI && MACH_TXX9
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 986852cc774..0030d23bef5 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o 7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o 8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o 9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
10obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
10obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
11obj-$(CONFIG_SPI) += spi_eeprom.o 12obj-$(CONFIG_SPI) += spi_eeprom.o
12 13
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
new file mode 100644
index 00000000000..013213a8706
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -0,0 +1,215 @@
1/*
2 * TX4939 irq routines
3 * Based on linux/arch/mips/kernel/irq_txx9.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright 2001, 2003-2005 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ahennessy@mvista.com
9 * source@mvista.com
10 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16/*
17 * TX4939 defines 64 IRQs.
18 * Similer to irq_txx9.c but different register layouts.
19 */
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <asm/irq_cpu.h>
24#include <asm/txx9irq.h>
25#include <asm/txx9/tx4939.h>
26
27/* IRCER : Int. Control Enable */
28#define TXx9_IRCER_ICE 0x00000001
29
30/* IRCR : Int. Control */
31#define TXx9_IRCR_LOW 0x00000000
32#define TXx9_IRCR_HIGH 0x00000001
33#define TXx9_IRCR_DOWN 0x00000002
34#define TXx9_IRCR_UP 0x00000003
35#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
36
37/* IRSCR : Int. Status Control */
38#define TXx9_IRSCR_EIClrE 0x00000100
39#define TXx9_IRSCR_EIClr_MASK 0x0000000f
40
41/* IRCSR : Int. Current Status */
42#define TXx9_IRCSR_IF 0x00010000
43
44#define irc_dlevel 0
45#define irc_elevel 1
46
47static struct {
48 unsigned char level;
49 unsigned char mode;
50} tx4939irq[TX4939_NUM_IR] __read_mostly;
51
52static void tx4939_irq_unmask(unsigned int irq)
53{
54 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
55 u32 __iomem *lvlp;
56 int ofs;
57 if (irq_nr < 32) {
58 irq_nr--;
59 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
60 } else {
61 irq_nr -= 32;
62 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
63 }
64 ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
65 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
66 | (tx4939irq[irq_nr].level << ofs),
67 lvlp);
68}
69
70static inline void tx4939_irq_mask(unsigned int irq)
71{
72 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
73 u32 __iomem *lvlp;
74 int ofs;
75 if (irq_nr < 32) {
76 irq_nr--;
77 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
78 } else {
79 irq_nr -= 32;
80 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
81 }
82 ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
83 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
84 | (irc_dlevel << ofs),
85 lvlp);
86 mmiowb();
87}
88
89static void tx4939_irq_mask_ack(unsigned int irq)
90{
91 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
92
93 tx4939_irq_mask(irq);
94 if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
95 irq_nr--;
96 /* clear edge detection */
97 __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
98 << (irq_nr & 0x10),
99 &tx4939_ircptr->edc.r);
100 }
101}
102
103static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
104{
105 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
106 u32 cr;
107 u32 __iomem *crp;
108 int ofs;
109 int mode;
110
111 if (flow_type & IRQF_TRIGGER_PROBE)
112 return 0;
113 switch (flow_type & IRQF_TRIGGER_MASK) {
114 case IRQF_TRIGGER_RISING:
115 mode = TXx9_IRCR_UP;
116 break;
117 case IRQF_TRIGGER_FALLING:
118 mode = TXx9_IRCR_DOWN;
119 break;
120 case IRQF_TRIGGER_HIGH:
121 mode = TXx9_IRCR_HIGH;
122 break;
123 case IRQF_TRIGGER_LOW:
124 mode = TXx9_IRCR_LOW;
125 break;
126 default:
127 return -EINVAL;
128 }
129 if (irq_nr < 32) {
130 irq_nr--;
131 crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
132 } else {
133 irq_nr -= 32;
134 crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
135 }
136 ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
137 cr = __raw_readl(crp);
138 cr &= ~(0x3 << ofs);
139 cr |= (mode & 0x3) << ofs;
140 __raw_writel(cr, crp);
141 tx4939irq[irq_nr].mode = mode;
142 return 0;
143}
144
145static struct irq_chip tx4939_irq_chip = {
146 .name = "TX4939",
147 .ack = tx4939_irq_mask_ack,
148 .mask = tx4939_irq_mask,
149 .mask_ack = tx4939_irq_mask_ack,
150 .unmask = tx4939_irq_unmask,
151 .set_type = tx4939_irq_set_type,
152};
153
154static int tx4939_irq_set_pri(int irc_irq, int new_pri)
155{
156 int old_pri;
157
158 if ((unsigned int)irc_irq >= TX4939_NUM_IR)
159 return 0;
160 old_pri = tx4939irq[irc_irq].level;
161 tx4939irq[irc_irq].level = new_pri;
162 return old_pri;
163}
164
165void __init tx4939_irq_init(void)
166{
167 int i;
168
169 mips_cpu_irq_init();
170 /* disable interrupt control */
171 __raw_writel(0, &tx4939_ircptr->den.r);
172 __raw_writel(0, &tx4939_ircptr->maskint.r);
173 __raw_writel(0, &tx4939_ircptr->maskext.r);
174 /* irq_base + 0 is not used */
175 for (i = 1; i < TX4939_NUM_IR; i++) {
176 tx4939irq[i].level = 4; /* middle level */
177 tx4939irq[i].mode = TXx9_IRCR_LOW;
178 set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
179 &tx4939_irq_chip, handle_level_irq);
180 }
181
182 /* mask all IRC interrupts */
183 __raw_writel(0, &tx4939_ircptr->msk.r);
184 for (i = 0; i < 16; i++)
185 __raw_writel(0, &tx4939_ircptr->lvl[i].r);
186 /* setup IRC interrupt mode (Low Active) */
187 for (i = 0; i < 2; i++)
188 __raw_writel(0, &tx4939_ircptr->dm[i].r);
189 for (i = 0; i < 2; i++)
190 __raw_writel(0, &tx4939_ircptr->dm2[i].r);
191 /* enable interrupt control */
192 __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
193 __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
194
195 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
196 handle_simple_irq);
197
198 /* raise priority for errors, timers, sio */
199 tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
200 tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
201 tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
202 for (i = 0; i < TX4939_NUM_IR_TMR; i++)
203 tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
204 for (i = 0; i < TX4939_NUM_IR_SIO; i++)
205 tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
206}
207
208int tx4939_irq(void)
209{
210 u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
211
212 if (likely(!(csr & TXx9_IRCSR_IF)))
213 return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
214 return -1;
215}
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
new file mode 100644
index 00000000000..f14a497077d
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -0,0 +1,460 @@
1/*
2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/netdevice.h>
17#include <linux/notifier.h>
18#include <linux/sysdev.h>
19#include <linux/ethtool.h>
20#include <linux/param.h>
21#include <linux/ptrace.h>
22#include <linux/mtd/physmap.h>
23#include <asm/bootinfo.h>
24#include <asm/reboot.h>
25#include <asm/traps.h>
26#include <asm/txx9irq.h>
27#include <asm/txx9tmr.h>
28#include <asm/txx9/generic.h>
29#include <asm/txx9/tx4939.h>
30
31static void __init tx4939_wdr_init(void)
32{
33 /* report watchdog reset status */
34 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
35 pr_warning("Watchdog reset detected at 0x%lx\n",
36 read_c0_errorepc());
37 /* clear WatchDogReset (W1C) */
38 tx4939_ccfg_set(TX4939_CCFG_WDRST);
39 /* do reset on watchdog */
40 tx4939_ccfg_set(TX4939_CCFG_WR);
41}
42
43void __init tx4939_wdt_init(void)
44{
45 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
46}
47
48static void tx4939_machine_restart(char *command)
49{
50 local_irq_disable();
51 pr_emerg("Rebooting (with %s watchdog reset)...\n",
52 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
53 "external" : "internal");
54 /* clear watchdog status */
55 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
56 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
57 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
58 ;
59 mdelay(10);
60 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
61 pr_emerg("Rebooting (with internal watchdog reset)...\n");
62 /* External WDRST failed. Do internal watchdog reset */
63 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
64 }
65 /* fallback */
66 (*_machine_halt)();
67}
68
69void show_registers(struct pt_regs *regs);
70static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
71{
72 int data = regs->cp0_cause & 4;
73 console_verbose();
74 pr_err("%cBE exception at %#lx\n",
75 data ? 'D' : 'I', regs->cp0_epc);
76 pr_err("ccfg:%llx, toea:%llx\n",
77 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
78 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
79#ifdef CONFIG_PCI
80 tx4927_report_pcic_status();
81#endif
82 show_registers(regs);
83 panic("BusError!");
84}
85static void __init tx4939_be_init(void)
86{
87 board_be_handler = tx4939_be_handler;
88}
89
90static struct resource tx4939_sdram_resource[4];
91static struct resource tx4939_sram_resource;
92#define TX4939_SRAM_SIZE 0x800
93
94void __init tx4939_add_memory_regions(void)
95{
96 int i;
97 unsigned long start, size;
98 u64 win;
99
100 for (i = 0; i < 4; i++) {
101 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
102 continue;
103 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
104 start = (unsigned long)(win >> 48);
105 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
106 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
107 }
108}
109
110void __init tx4939_setup(void)
111{
112 int i;
113 __u32 divmode;
114 __u64 pcfg;
115 int cpuclk = 0;
116
117 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
118 TX4939_REG_SIZE);
119 set_c0_config(TX49_CONF_CWFON);
120
121 /* SDRAMC,EBUSC are configured by PROM */
122 for (i = 0; i < 4; i++) {
123 if (!(TX4939_EBUSC_CR(i) & 0x8))
124 continue; /* disabled */
125 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
126 txx9_ce_res[i].end =
127 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
128 request_resource(&iomem_resource, &txx9_ce_res[i]);
129 }
130
131 /* clocks */
132 if (txx9_master_clock) {
133 /* calculate cpu_clock from master_clock */
134 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
135 TX4939_CCFG_MULCLK_MASK;
136 cpuclk = txx9_master_clock * 20 / 2;
137 switch (divmode) {
138 case TX4939_CCFG_MULCLK_8:
139 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
140 case TX4939_CCFG_MULCLK_9:
141 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
142 case TX4939_CCFG_MULCLK_10:
143 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
144 case TX4939_CCFG_MULCLK_11:
145 cpuclk = cpuclk / 6 * 11; break;
146 case TX4939_CCFG_MULCLK_12:
147 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
148 case TX4939_CCFG_MULCLK_13:
149 cpuclk = cpuclk / 6 * 13; break;
150 case TX4939_CCFG_MULCLK_14:
151 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
152 case TX4939_CCFG_MULCLK_15:
153 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
154 }
155 txx9_cpu_clock = cpuclk;
156 } else {
157 if (txx9_cpu_clock == 0)
158 txx9_cpu_clock = 400000000; /* 400MHz */
159 /* calculate master_clock from cpu_clock */
160 cpuclk = txx9_cpu_clock;
161 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
162 TX4939_CCFG_MULCLK_MASK;
163 switch (divmode) {
164 case TX4939_CCFG_MULCLK_8:
165 txx9_master_clock = cpuclk * 6 / 8; break;
166 case TX4939_CCFG_MULCLK_9:
167 txx9_master_clock = cpuclk * 6 / 9; break;
168 case TX4939_CCFG_MULCLK_10:
169 txx9_master_clock = cpuclk * 6 / 10; break;
170 case TX4939_CCFG_MULCLK_11:
171 txx9_master_clock = cpuclk * 6 / 11; break;
172 case TX4939_CCFG_MULCLK_12:
173 txx9_master_clock = cpuclk * 6 / 12; break;
174 case TX4939_CCFG_MULCLK_13:
175 txx9_master_clock = cpuclk * 6 / 13; break;
176 case TX4939_CCFG_MULCLK_14:
177 txx9_master_clock = cpuclk * 6 / 14; break;
178 case TX4939_CCFG_MULCLK_15:
179 txx9_master_clock = cpuclk * 6 / 15; break;
180 }
181 txx9_master_clock /= 10; /* * 2 / 20 */
182 }
183 /* calculate gbus_clock from cpu_clock */
184 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
185 TX4939_CCFG_YDIVMODE_MASK;
186 txx9_gbus_clock = txx9_cpu_clock;
187 switch (divmode) {
188 case TX4939_CCFG_YDIVMODE_2:
189 txx9_gbus_clock /= 2; break;
190 case TX4939_CCFG_YDIVMODE_3:
191 txx9_gbus_clock /= 3; break;
192 case TX4939_CCFG_YDIVMODE_5:
193 txx9_gbus_clock /= 5; break;
194 case TX4939_CCFG_YDIVMODE_6:
195 txx9_gbus_clock /= 6; break;
196 }
197 /* change default value to udelay/mdelay take reasonable time */
198 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
199
200 /* CCFG */
201 tx4939_wdr_init();
202 /* clear BusErrorOnWrite flag (W1C) */
203 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
204 /* enable Timeout BusError */
205 if (txx9_ccfg_toeon)
206 tx4939_ccfg_set(TX4939_CCFG_TOE);
207
208 /* DMA selection */
209 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
210
211 /* Use external clock for external arbiter */
212 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
213 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
214
215 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
216 txx9_pcode_str,
217 (cpuclk + 500000) / 1000000,
218 (txx9_master_clock + 500000) / 1000000,
219 (txx9_gbus_clock + 500000) / 1000000,
220 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
221 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
222 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
223
224 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
225 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
226 for (i = 0; i < 4; i++) {
227 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
228 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
229 continue; /* disabled */
230 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
231 tx4939_sdram_resource[i].name = "DDR SDRAM";
232 tx4939_sdram_resource[i].start =
233 (unsigned long)(win >> 48) << 20;
234 tx4939_sdram_resource[i].end =
235 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
236 20) - 1;
237 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
238 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
239 }
240 printk(KERN_CONT "\n");
241
242 /* SRAM */
243 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
244 unsigned int size = TX4939_SRAM_SIZE;
245 tx4939_sram_resource.name = "SRAM";
246 tx4939_sram_resource.start =
247 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
248 & ~(size - 1);
249 tx4939_sram_resource.end =
250 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
251 tx4939_sram_resource.flags = IORESOURCE_MEM;
252 request_resource(&iomem_resource, &tx4939_sram_resource);
253 }
254
255 /* TMR */
256 /* disable all timers */
257 for (i = 0; i < TX4939_NR_TMR; i++)
258 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
259
260 /* DMA */
261 for (i = 0; i < 2; i++)
262 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
263 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
264
265 /* set PCIC1 reset (required to prevent hangup on BIST) */
266 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
267 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
268 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
269 mdelay(1); /* at least 128 cpu clock */
270 /* clear PCIC1 reset */
271 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
272 } else {
273 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
274 /* stop PCIC1 */
275 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
276 }
277 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
278 pr_info("%s: stop ETH0\n", txx9_pcode_str);
279 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
280 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
281 }
282 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
283 pr_info("%s: stop ETH1\n", txx9_pcode_str);
284 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
285 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
286 }
287
288 _machine_restart = tx4939_machine_restart;
289 board_be_init = tx4939_be_init;
290}
291
292void __init tx4939_time_init(unsigned int tmrnr)
293{
294 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
295 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
296 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
297 TXX9_IMCLK);
298}
299
300void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
301{
302 int i;
303 unsigned int ch_mask = 0;
304 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
305
306 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
307 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
308 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
309 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
310 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
311 if (pcfg & TX4939_PCFG_SIO3MODE)
312 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
313 for (i = 0; i < 4; i++) {
314 if ((1 << i) & ch_mask)
315 continue;
316 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
317 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
318 i, sclk, (1 << i) & cts_mask);
319 }
320}
321
322#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
323static int tx4939_get_eth_speed(struct net_device *dev)
324{
325 struct ethtool_cmd cmd = { ETHTOOL_GSET };
326 int speed = 100; /* default 100Mbps */
327 int err;
328 if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
329 return speed;
330 err = dev->ethtool_ops->get_settings(dev, &cmd);
331 if (err < 0)
332 return speed;
333 speed = cmd.speed == SPEED_100 ? 100 : 10;
334 return speed;
335}
336static int tx4939_netdev_event(struct notifier_block *this,
337 unsigned long event,
338 void *ptr)
339{
340 struct net_device *dev = ptr;
341 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
342 __u64 bit = 0;
343 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
344 bit = TX4939_PCFG_SPEED0;
345 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
346 bit = TX4939_PCFG_SPEED1;
347 if (bit) {
348 int speed = tx4939_get_eth_speed(dev);
349 if (speed == 100)
350 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
351 else
352 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
353 }
354 }
355 return NOTIFY_DONE;
356}
357
358static struct notifier_block tx4939_netdev_notifier = {
359 .notifier_call = tx4939_netdev_event,
360 .priority = 1,
361};
362
363void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
364{
365 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
366
367 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
368 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
369 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
370 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
371 register_netdevice_notifier(&tx4939_netdev_notifier);
372}
373#else
374void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
375{
376}
377#endif
378
379void __init tx4939_mtd_init(int ch)
380{
381 struct physmap_flash_data pdata = {
382 .width = TX4939_EBUSC_WIDTH(ch) / 8,
383 };
384 unsigned long start = txx9_ce_res[ch].start;
385 unsigned long size = txx9_ce_res[ch].end - start + 1;
386
387 if (!(TX4939_EBUSC_CR(ch) & 0x8))
388 return; /* disabled */
389 txx9_physmap_flash_init(ch, start, size, &pdata);
390}
391
392static void __init tx4939_stop_unused_modules(void)
393{
394 __u64 pcfg, rst = 0, ckd = 0;
395 char buf[128];
396
397 buf[0] = '\0';
398 local_irq_disable();
399 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
400 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
401 TX4939_PCFG_I2SMODE_ACLC) {
402 rst |= TX4939_CLKCTR_ACLRST;
403 ckd |= TX4939_CLKCTR_ACLCKD;
404 strcat(buf, " ACLC");
405 }
406 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
407 TX4939_PCFG_I2SMODE_I2S &&
408 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
409 TX4939_PCFG_I2SMODE_I2S_ALT) {
410 rst |= TX4939_CLKCTR_I2SRST;
411 ckd |= TX4939_CLKCTR_I2SCKD;
412 strcat(buf, " I2S");
413 }
414 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
415 rst |= TX4939_CLKCTR_ATA0RST;
416 ckd |= TX4939_CLKCTR_ATA0CKD;
417 strcat(buf, " ATA0");
418 }
419 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
420 rst |= TX4939_CLKCTR_ATA1RST;
421 ckd |= TX4939_CLKCTR_ATA1CKD;
422 strcat(buf, " ATA1");
423 }
424 if (pcfg & TX4939_PCFG_SPIMODE) {
425 rst |= TX4939_CLKCTR_SPIRST;
426 ckd |= TX4939_CLKCTR_SPICKD;
427 strcat(buf, " SPI");
428 }
429 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
430 rst |= TX4939_CLKCTR_VPCRST;
431 ckd |= TX4939_CLKCTR_VPCCKD;
432 strcat(buf, " VPC");
433 }
434 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
435 rst |= TX4939_CLKCTR_SIO2RST;
436 ckd |= TX4939_CLKCTR_SIO2CKD;
437 strcat(buf, " SIO2");
438 }
439 if (pcfg & TX4939_PCFG_SIO3MODE) {
440 rst |= TX4939_CLKCTR_SIO3RST;
441 ckd |= TX4939_CLKCTR_SIO3CKD;
442 strcat(buf, " SIO3");
443 }
444 if (rst | ckd) {
445 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
446 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
447 }
448 local_irq_enable();
449 if (buf[0])
450 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
451}
452
453static int __init tx4939_late_init(void)
454{
455 if (txx9_pcode != 0x4939)
456 return -ENODEV;
457 tx4939_stop_unused_modules();
458 return 0;
459}
460late_initcall(tx4939_late_init);
diff --git a/include/asm-mips/txx9/tx4939.h b/include/asm-mips/txx9/tx4939.h
new file mode 100644
index 00000000000..7ce2dff3b7c
--- /dev/null
+++ b/include/asm-mips/txx9/tx4939.h
@@ -0,0 +1,544 @@
1/*
2 * Definitions for TX4939
3 *
4 * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 */
10#ifndef __ASM_TXX9_TX4939_H
11#define __ASM_TXX9_TX4939_H
12
13/* some controllers are compatible with 4927/4938 */
14#include <asm/txx9/tx4938.h>
15
16#ifdef CONFIG_64BIT
17#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
18#else
19#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
20#endif
21#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
22
23#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
24#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
25#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000)
26#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800)
27#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000)
28#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000)
29#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000)
30#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000)
31#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
32#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000)
33#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000)
34#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800)
35#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
36#define TX4939_TMR_REG(ch) \
37 (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
38#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */
39#define TX4939_SIO_REG(ch) \
40 (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
41#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700)
42#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800)
43#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900)
44#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00)
45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
47
48struct tx4939_le_reg {
49 __u32 r;
50 __u32 unused;
51};
52
53struct tx4939_ddrc_reg {
54 struct tx4939_le_reg ctl[47];
55 __u64 unused0[17];
56 __u64 winen;
57 __u64 win[4];
58};
59
60struct tx4939_ccfg_reg {
61 __u64 ccfg;
62 __u64 crir;
63 __u64 pcfg;
64 __u64 toea;
65 __u64 clkctr;
66 __u64 unused0;
67 __u64 garbc;
68 __u64 unused1[2];
69 __u64 ramp;
70 __u64 unused2[2];
71 __u64 dskwctrl;
72 __u64 mclkosc;
73 __u64 mclkctl;
74 __u64 unused3[17];
75 struct {
76 __u64 mr;
77 __u64 dr;
78 } gpio[2];
79};
80
81struct tx4939_irc_reg {
82 struct tx4939_le_reg den;
83 struct tx4939_le_reg scipb;
84 struct tx4939_le_reg dm[2];
85 struct tx4939_le_reg lvl[16];
86 struct tx4939_le_reg msk;
87 struct tx4939_le_reg edc;
88 struct tx4939_le_reg pnd0;
89 struct tx4939_le_reg cs;
90 struct tx4939_le_reg pnd1;
91 struct tx4939_le_reg dm2[2];
92 struct tx4939_le_reg dbr[2];
93 struct tx4939_le_reg dben;
94 struct tx4939_le_reg unused0[2];
95 struct tx4939_le_reg flag[2];
96 struct tx4939_le_reg pol;
97 struct tx4939_le_reg cnt;
98 struct tx4939_le_reg maskint;
99 struct tx4939_le_reg maskext;
100};
101
102struct tx4939_rtc_reg {
103 __u32 ctl;
104 __u32 adr;
105 __u32 dat;
106 __u32 tbc;
107};
108
109struct tx4939_crypto_reg {
110 struct tx4939_le_reg csr;
111 struct tx4939_le_reg idesptr;
112 struct tx4939_le_reg cdesptr;
113 struct tx4939_le_reg buserr;
114 struct tx4939_le_reg cip_tout;
115 struct tx4939_le_reg cir;
116 union {
117 struct {
118 struct tx4939_le_reg data[8];
119 struct tx4939_le_reg ctrl;
120 } gen;
121 struct {
122 struct {
123 struct tx4939_le_reg l;
124 struct tx4939_le_reg u;
125 } key[3], ini;
126 struct tx4939_le_reg ctrl;
127 } des;
128 struct {
129 struct tx4939_le_reg key[4];
130 struct tx4939_le_reg ini[4];
131 struct tx4939_le_reg ctrl;
132 } aes;
133 struct {
134 struct {
135 struct tx4939_le_reg l;
136 struct tx4939_le_reg u;
137 } cnt;
138 struct tx4939_le_reg ini[5];
139 struct tx4939_le_reg unused;
140 struct tx4939_le_reg ctrl;
141 } hash;
142 } cdr;
143 struct tx4939_le_reg unused0[7];
144 struct tx4939_le_reg rcsr;
145 struct tx4939_le_reg rpr;
146 __u64 rdr;
147 __u64 ror[3];
148 struct tx4939_le_reg unused1[2];
149 struct tx4939_le_reg xorslr;
150 struct tx4939_le_reg xorsur;
151};
152
153struct tx4939_crypto_desc {
154 __u32 src;
155 __u32 dst;
156 __u32 next;
157 __u32 ctrl;
158 __u32 index;
159 __u32 xor;
160};
161
162struct tx4939_vpc_reg {
163 struct tx4939_le_reg csr;
164 struct {
165 struct tx4939_le_reg ctrlA;
166 struct tx4939_le_reg ctrlB;
167 struct tx4939_le_reg idesptr;
168 struct tx4939_le_reg cdesptr;
169 } port[3];
170 struct tx4939_le_reg buserr;
171};
172
173struct tx4939_vpc_desc {
174 __u32 src;
175 __u32 next;
176 __u32 ctrl1;
177 __u32 ctrl2;
178};
179
180/*
181 * IRC
182 */
183#define TX4939_IR_NONE 0
184#define TX4939_IR_DDR 1
185#define TX4939_IR_WTOERR 2
186#define TX4939_NUM_IR_INT 3
187#define TX4939_IR_INT(n) (3 + (n))
188#define TX4939_NUM_IR_ETH 2
189#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
190#define TX4939_IR_VIDEO 7
191#define TX4939_IR_CIR 8
192#define TX4939_NUM_IR_SIO 4
193#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
194#define TX4939_NUM_IR_DMA 4
195#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
196#define TX4939_IR_IRC 14
197#define TX4939_IR_PDMAC 15
198#define TX4939_NUM_IR_TMR 6
199#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
200#define TX4939_NUM_IR_ATA 2
201#define TX4939_IR_ATA(n) (19 + (n))
202#define TX4939_IR_ACLC 21
203#define TX4939_IR_CIPHER 26
204#define TX4939_IR_INTA 27
205#define TX4939_IR_INTB 28
206#define TX4939_IR_INTC 29
207#define TX4939_IR_INTD 30
208#define TX4939_IR_I2C 33
209#define TX4939_IR_SPI 34
210#define TX4939_IR_PCIC 35
211#define TX4939_IR_PCIC1 36
212#define TX4939_IR_PCIERR 37
213#define TX4939_IR_PCIPME 38
214#define TX4939_IR_NDFMC 39
215#define TX4939_IR_ACLCPME 40
216#define TX4939_IR_RTC 41
217#define TX4939_IR_RND 42
218#define TX4939_IR_I2S 47
219#define TX4939_NUM_IR 64
220
221#define TX4939_IRC_INT 2 /* IP[2] in Status register */
222
223/*
224 * CCFG
225 */
226/* CCFG : Chip Configuration */
227#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL
228#define TX4939_CCFG_WDRST 0x0000020000000000ULL
229#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL
230#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL
231#define TX4939_CCFG_GTOT_MASK 0x06000000
232#define TX4939_CCFG_GTOT_4096 0x06000000
233#define TX4939_CCFG_GTOT_2048 0x04000000
234#define TX4939_CCFG_GTOT_1024 0x02000000
235#define TX4939_CCFG_GTOT_512 0x00000000
236#define TX4939_CCFG_TINTDIS 0x01000000
237#define TX4939_CCFG_PCI66 0x00800000
238#define TX4939_CCFG_PCIMODE 0x00400000
239#define TX4939_CCFG_SSCG 0x00100000
240#define TX4939_CCFG_MULCLK_MASK 0x000e0000
241#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
242#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
243#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
244#define TX4939_CCFG_MULCLK_11 (0x2 << 17)
245#define TX4939_CCFG_MULCLK_12 (0x3 << 17)
246#define TX4939_CCFG_MULCLK_13 (0x4 << 17)
247#define TX4939_CCFG_MULCLK_14 (0x5 << 17)
248#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
249#define TX4939_CCFG_BEOW 0x00010000
250#define TX4939_CCFG_WR 0x00008000
251#define TX4939_CCFG_TOE 0x00004000
252#define TX4939_CCFG_PCIARB 0x00002000
253#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
254#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
255#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10)
256#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10)
257#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10)
258#define TX4939_CCFG_PTSEL 0x00000200
259#define TX4939_CCFG_BESEL 0x00000100
260#define TX4939_CCFG_SYSSP_MASK 0x000000c0
261#define TX4939_CCFG_ACKSEL 0x00000020
262#define TX4939_CCFG_ROMW 0x00000010
263#define TX4939_CCFG_ENDIAN 0x00000004
264#define TX4939_CCFG_ARMODE 0x00000002
265#define TX4939_CCFG_ACEHOLD 0x00000001
266
267/* PCFG : Pin Configuration */
268#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL
269#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL
270#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL
271#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL
272#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL
273#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
274#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
275#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
276#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
277#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
278#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
279#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
280#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL
281#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL
282#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL
283#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL
284#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL
285#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL
286#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL
287#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL
288#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL
289#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL
290
291#define TX4939_PCFG_SYSCLKEN 0x08000000
292#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000
293#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
294#define TX4939_PCFG_SPEED1 0x00002000
295#define TX4939_PCFG_SPEED0 0x00001000
296#define TX4939_PCFG_ITMODE 0x00000300
297#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3)
298#define TX4939_PCFG_DMASEL2 0x00000004
299#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000
300#define TX4939_PCFG_DMASEL2_SIO0 0x00000004
301#define TX4939_PCFG_DMASEL1 0x00000002
302#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000
303#define TX4939_PCFG_DMASEL0 0x00000001
304#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000
305
306/* CLKCTR : Clock Control */
307#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL
308#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL
309#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL
310#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL
311#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL
312#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL
313#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL
314#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL
315#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL
316#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL
317#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL
318#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL
319#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL
320#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL
321#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL
322#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL
323#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL
324#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL
325#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL
326#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL
327#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL
328#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL
329#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL
330#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL
331#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL
332#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL
333#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL
334#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL
335#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL
336#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL
337#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL
338#define TX4939_CLKCTR_IOSRST 0x80000000
339#define TX4939_CLKCTR_SYSRST 0x40000000
340#define TX4939_CLKCTR_TM5RST 0x20000000
341#define TX4939_CLKCTR_TM4RST 0x10000000
342#define TX4939_CLKCTR_TM3RST 0x08000000
343#define TX4939_CLKCTR_CIRRST 0x04000000
344#define TX4939_CLKCTR_SIO3RST 0x02000000
345#define TX4939_CLKCTR_SIO2RST 0x01000000
346#define TX4939_CLKCTR_SIO1RST 0x00800000
347#define TX4939_CLKCTR_VPCRST 0x00400000
348#define TX4939_CLKCTR_EPCIRST 0x00200000
349#define TX4939_CLKCTR_ETH1RST 0x00080000
350#define TX4939_CLKCTR_ATA1RST 0x00040000
351#define TX4939_CLKCTR_BROMRST 0x00020000
352#define TX4939_CLKCTR_NDCRST 0x00010000
353#define TX4939_CLKCTR_I2CRST 0x00008000
354#define TX4939_CLKCTR_ETH0RST 0x00004000
355#define TX4939_CLKCTR_SPIRST 0x00002000
356#define TX4939_CLKCTR_SRAMRST 0x00001000
357#define TX4939_CLKCTR_PCI1RST 0x00000800
358#define TX4939_CLKCTR_DMA1RST 0x00000400
359#define TX4939_CLKCTR_ACLRST 0x00000200
360#define TX4939_CLKCTR_ATA0RST 0x00000100
361#define TX4939_CLKCTR_DMA0RST 0x00000080
362#define TX4939_CLKCTR_PCICRST 0x00000040
363#define TX4939_CLKCTR_I2SRST 0x00000020
364#define TX4939_CLKCTR_TM0RST 0x00000010
365#define TX4939_CLKCTR_TM1RST 0x00000008
366#define TX4939_CLKCTR_TM2RST 0x00000004
367#define TX4939_CLKCTR_SIO0RST 0x00000002
368#define TX4939_CLKCTR_CYPRST 0x00000001
369
370/*
371 * RTC
372 */
373#define TX4939_RTCCTL_ALME 0x00000080
374#define TX4939_RTCCTL_ALMD 0x00000040
375#define TX4939_RTCCTL_BUSY 0x00000020
376
377#define TX4939_RTCCTL_COMMAND 0x00000007
378#define TX4939_RTCCTL_COMMAND_NOP 0x00000000
379#define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001
380#define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002
381#define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003
382#define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004
383
384#define TX4939_RTCTBC_PM 0x00000080
385#define TX4939_RTCTBC_COMP 0x0000007f
386
387#define TX4939_RTC_REG_RAMSIZE 0x00000100
388#define TX4939_RTC_REG_RWBSIZE 0x00000006
389
390/*
391 * CRYPTO
392 */
393#define TX4939_CRYPTO_CSR_SAESO 0x08000000
394#define TX4939_CRYPTO_CSR_SAESI 0x04000000
395#define TX4939_CRYPTO_CSR_SDESO 0x02000000
396#define TX4939_CRYPTO_CSR_SDESI 0x01000000
397#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
398#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
399#define TX4939_CRYPTO_CSR_TOINT 0x00080000
400#define TX4939_CRYPTO_CSR_DCINT 0x00040000
401#define TX4939_CRYPTO_CSR_GBINT 0x00010000
402#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
403#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
404#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
405#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000
406#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800
407#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000
408#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800
409#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600
410#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000
411#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200
412#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400
413#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600
414#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0
415#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000
416#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
417#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
418#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
419#define TX4939_CRYPTO_CSR_GINTE 0x00000008
420#define TX4939_CRYPTO_CSR_RSTD 0x00000004
421#define TX4939_CRYPTO_CSR_RSTC 0x00000002
422#define TX4939_CRYPTO_CSR_ENCR 0x00000001
423
424/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
425#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003
426#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000
427#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001
428#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002
429#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003
430#define TX4939_CRYPTO_CTX_TDMS 0x00000010
431#define TX4939_CRYPTO_CTX_CMS 0x00000020
432#define TX4939_CRYPTO_CTX_DMS 0x00000040
433#define TX4939_CRYPTO_CTX_UPDATE 0x00000080
434
435/* bits for tx4939_crypto_desc.ctrl */
436#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000
437#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21)
438#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00
439#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10)
440#define TX4939_CRYPTO_DESC_START 0x00000200
441#define TX4939_CRYPTO_DESC_END 0x00000100
442#define TX4939_CRYPTO_DESC_XOR 0x00000010
443#define TX4939_CRYPTO_DESC_LAST 0x00000008
444#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
445#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
446#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
447#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004
448#define TX4939_CRYPTO_DESC_OWN 0x00000001
449
450/* bits for tx4939_crypto_desc.index */
451#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070
452#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4)
453#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007
454#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0)
455
456#define TX4939_CRYPTO_NR_SET 6
457
458#define TX4939_CRYPTO_RCSR_INTE 0x00000008
459#define TX4939_CRYPTO_RCSR_RST 0x00000004
460#define TX4939_CRYPTO_RCSR_FIN 0x00000002
461#define TX4939_CRYPTO_RCSR_ST 0x00000001
462
463/*
464 * VPC
465 */
466#define TX4939_VPC_CSR_GBINT 0x00010000
467#define TX4939_VPC_CSR_SWAPO 0x00000020
468#define TX4939_VPC_CSR_SWAPI 0x00000010
469#define TX4939_VPC_CSR_GINTE 0x00000008
470#define TX4939_VPC_CSR_RSTD 0x00000004
471#define TX4939_VPC_CSR_RSTVPC 0x00000002
472
473#define TX4939_VPC_CTRLA_VDPSN 0x00000200
474#define TX4939_VPC_CTRLA_PBUSY 0x00000100
475#define TX4939_VPC_CTRLA_DCINT 0x00000080
476#define TX4939_VPC_CTRLA_UOINT 0x00000040
477#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030
478#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
479#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
480#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
481#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
482#define TX4939_VPC_CTRLA_VDMODE 0x00000004
483#define TX4939_VPC_CTRLA_VDFOR 0x00000002
484#define TX4939_VPC_CTRLA_ENVPC 0x00000001
485
486/* bits for tx4939_vpc_desc.ctrl1 */
487#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006
488#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001
489
490#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
491#define tx4939_ebuscptr tx4938_ebuscptr
492#define tx4939_ircptr \
493 ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
494#define tx4939_pcicptr tx4938_pcicptr
495#define tx4939_pcic1ptr tx4938_pcic1ptr
496#define tx4939_ccfgptr \
497 ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
498#define tx4939_sramcptr tx4938_sramcptr
499#define tx4939_rtcptr \
500 ((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
501#define tx4939_cryptoptr \
502 ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
503#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
504
505#define TX4939_REV_MAJ_MIN() \
506 ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
507#define TX4939_REV_PCODE() \
508 ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
509#define TX4939_CCFG_BCFG() \
510 ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
511 >> 32))
512
513#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
514#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
515#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
516
517#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
518#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
519#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
520#define TX4939_EBUSC_WIDTH(ch) \
521 (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
522
523/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
524#define TX4939_SCLK0(mst) \
525 ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
526
527void tx4939_wdt_init(void);
528void tx4939_add_memory_regions(void);
529void tx4939_setup(void);
530void tx4939_time_init(unsigned int tmrnr);
531void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
532void tx4939_spi_init(int busid);
533void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
534int tx4939_report_pciclk(void);
535void tx4939_report_pci1clk(void);
536struct pci_dev;
537int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
538int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
539void tx4939_setup_pcierr_irq(void);
540void tx4939_irq_init(void);
541int tx4939_irq(void);
542void tx4939_mtd_init(int ch);
543
544#endif /* __ASM_TXX9_TX4939_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 21:25:05 -0500