Added missing tegra files.HEADmaster

2 files changed, 313 insertions, 0 deletions

diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c
new file mode 100644
index 00000000000..a26a6faec9a
--- /dev/null
+++ b/arch/mips/jz4740/pwm.c
@@ -0,0 +1,177 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform PWM support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/gpio.h>
+#include "timer.h"
+
+static struct clk *jz4740_pwm_clk;
+
+DEFINE_MUTEX(jz4740_pwm_mutex);
+
+struct pwm_device {
+        unsigned int id;
+        unsigned int gpio;
+        bool used;
+};
+
+static struct pwm_device jz4740_pwm_list[] = {
+        { 2, JZ_GPIO_PWM2, false },
+        { 3, JZ_GPIO_PWM3, false },
+        { 4, JZ_GPIO_PWM4, false },
+        { 5, JZ_GPIO_PWM5, false },
+        { 6, JZ_GPIO_PWM6, false },
+        { 7, JZ_GPIO_PWM7, false },
+};
+
+struct pwm_device *pwm_request(int id, const char *label)
+{
+        int ret = 0;
+        struct pwm_device *pwm;
+
+        if (id < 2 || id > 7 || !jz4740_pwm_clk)
+                return ERR_PTR(-ENODEV);
+
+        mutex_lock(&jz4740_pwm_mutex);
+
+        pwm = &jz4740_pwm_list[id - 2];
+        if (pwm->used)
+                ret = -EBUSY;
+        else
+                pwm->used = true;
+
+        mutex_unlock(&jz4740_pwm_mutex);
+
+        if (ret)
+                return ERR_PTR(ret);
+
+        ret = gpio_request(pwm->gpio, label);
+
+        if (ret) {
+                printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
+                pwm->used = false;
+                return ERR_PTR(ret);
+        }
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
+
+        jz4740_timer_start(id);
+
+        return pwm;
+}
+
+void pwm_free(struct pwm_device *pwm)
+{
+        pwm_disable(pwm);
+        jz4740_timer_set_ctrl(pwm->id, 0);
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
+        gpio_free(pwm->gpio);
+
+        jz4740_timer_stop(pwm->id);
+
+        pwm->used = false;
+}
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long tmp;
+        unsigned long period, duty;
+        unsigned int prescaler = 0;
+        unsigned int id = pwm->id;
+        uint16_t ctrl;
+        bool is_enabled;
+
+        if (duty_ns < 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
+        do_div(tmp, 1000000000);
+        period = tmp;
+
+        while (period > 0xffff && prescaler < 6) {
+                period >>= 2;
+                ++prescaler;
+        }
+
+        if (prescaler == 6)
+                return -EINVAL;
+
+        tmp = (unsigned long long)period * duty_ns;
+        do_div(tmp, period_ns);
+        duty = period - tmp;
+
+        if (duty >= period)
+                duty = period - 1;
+
+        is_enabled = jz4740_timer_is_enabled(id);
+        if (is_enabled)
+                pwm_disable(pwm);
+
+        jz4740_timer_set_count(id, 0);
+        jz4740_timer_set_duty(id, duty);
+        jz4740_timer_set_period(id, period);
+
+        ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
+                JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
+
+        jz4740_timer_set_ctrl(id, ctrl);
+
+        if (is_enabled)
+                pwm_enable(pwm);
+
+        return 0;
+}
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+        jz4740_timer_enable(pwm->id);
+
+        return 0;
+}
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_disable(pwm->id);
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+}
+
+static int __init jz4740_pwm_init(void)
+{
+        int ret = 0;
+
+        jz4740_pwm_clk = clk_get(NULL, "ext");
+
+        if (IS_ERR(jz4740_pwm_clk)) {
+                ret = PTR_ERR(jz4740_pwm_clk);
+                jz4740_pwm_clk = NULL;
+        }
+
+        return ret;
+}
+subsys_initcall(jz4740_pwm_init);
diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h
new file mode 100644
index 00000000000..fca3994f2e6
--- /dev/null
+++ b/arch/mips/jz4740/timer.h
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_TIMER_H__
+#define __MIPS_JZ4740_TIMER_H__
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#define JZ_REG_TIMER_STOP               0x0C
+#define JZ_REG_TIMER_STOP_SET           0x1C
+#define JZ_REG_TIMER_STOP_CLEAR         0x2C
+#define JZ_REG_TIMER_ENABLE             0x00
+#define JZ_REG_TIMER_ENABLE_SET         0x04
+#define JZ_REG_TIMER_ENABLE_CLEAR       0x08
+#define JZ_REG_TIMER_FLAG               0x10
+#define JZ_REG_TIMER_FLAG_SET           0x14
+#define JZ_REG_TIMER_FLAG_CLEAR         0x18
+#define JZ_REG_TIMER_MASK               0x20
+#define JZ_REG_TIMER_MASK_SET           0x24
+#define JZ_REG_TIMER_MASK_CLEAR         0x28
+
+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
+
+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
+
+#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN      BIT(9)
+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW            BIT(8)
+#define JZ_TIMER_CTRL_PWM_ENABLE                BIT(7)
+#define JZ_TIMER_CTRL_PRESCALE_MASK             0x1c
+#define JZ_TIMER_CTRL_PRESCALE_OFFSET           0x3
+#define JZ_TIMER_CTRL_PRESCALE_1                (0 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_4                (1 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_16               (2 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_64               (3 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_256              (4 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_1024             (5 << 3)
+
+#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
+
+#define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
+#define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
+#define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
+
+extern void __iomem *jz4740_timer_base;
+void __init jz4740_timer_init(void);
+
+static inline void jz4740_timer_stop(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static inline void jz4740_timer_start(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+static inline bool jz4740_timer_is_enabled(unsigned int timer)
+{
+        return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
+}
+
+static inline void jz4740_timer_enable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static inline void jz4740_timer_disable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+}
+
+
+static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
+{
+        writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
+}
+
+static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
+{
+        writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
+}
+
+static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
+{
+        writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline uint16_t jz4740_timer_get_count(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline void jz4740_timer_ack_full(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_enable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_disable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
+{
+        writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+#endif