diff options
| author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
|---|---|---|
| committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
| commit | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch) | |
| tree | a8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/mips/include/asm/mach-ip28 | |
| parent | 406089d01562f1e2bf9f089fd7637009ebaad589 (diff) | |
Patched in Tegra support.
Diffstat (limited to 'arch/mips/include/asm/mach-ip28')
| -rw-r--r-- | arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-ip28/war.h | 1 |
2 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index 50d344ca60a..9a53b326f84 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #define cpu_has_dc_aliases 0 /* see probe_pcache() */ | 27 | #define cpu_has_dc_aliases 0 /* see probe_pcache() */ |
| 28 | #define cpu_has_ic_fills_f_dc 0 | 28 | #define cpu_has_ic_fills_f_dc 0 |
| 29 | #define cpu_has_dsp 0 | 29 | #define cpu_has_dsp 0 |
| 30 | #define cpu_has_dsp2 0 | ||
| 31 | #define cpu_icache_snoops_remote_store 1 | 30 | #define cpu_icache_snoops_remote_store 1 |
| 32 | #define cpu_has_mipsmt 0 | 31 | #define cpu_has_mipsmt 0 |
| 33 | #define cpu_has_userlocal 0 | 32 | #define cpu_has_userlocal 0 |
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h index 4821c7b7a38..a1baafab486 100644 --- a/arch/mips/include/asm/mach-ip28/war.h +++ b/arch/mips/include/asm/mach-ip28/war.h | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | 17 | #define MIPS4K_ICACHE_REFILL_WAR 0 |
| 18 | #define MIPS_CACHE_SYNC_WAR 0 | 18 | #define MIPS_CACHE_SYNC_WAR 0 |
| 19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | 19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 |
| 20 | #define RM9000_CDEX_SMP_WAR 0 | ||
| 20 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | 21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 |
| 21 | #define R10000_LLSC_WAR 1 | 22 | #define R10000_LLSC_WAR 1 |
| 22 | #define MIPS34K_MISSED_ITLB_WAR 0 | 23 | #define MIPS34K_MISSED_ITLB_WAR 0 |
