diff options
author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-08-12 14:12:33 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-10-24 18:34:23 -0400 |
commit | ce6bc92285cabd0df1f154a9ef5aeb937b6de57e (patch) | |
tree | fc2313d5a921624d512020ab5825861b6b3e1f8b /arch/mips/alchemy/common | |
parent | 694b8c35e95078bfe1cb1388bf0cf7942e32f009 (diff) |
MIPS: Alchemy: abstract USB block control register access
Alchemy chips have one or more registers which control access
to the usb blocks as well as PHY configuration. I don't want
the OHCI/EHCI glues to know about the different registers and bits;
new code hides the gory details of USB configuration from them.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: linux-usb@vger.kernel.org
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Patchwork: https://patchwork.linux-mips.org/patch/2709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
create mode 100644 drivers/usb/host/alchemy-common.c
Diffstat (limited to 'arch/mips/alchemy/common')
-rw-r--r-- | arch/mips/alchemy/common/dma.c | 12 | ||||
-rw-r--r-- | arch/mips/alchemy/common/power.c | 42 |
2 files changed, 6 insertions, 48 deletions
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index 347980e79a8..6652a237b92 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c | |||
@@ -88,12 +88,12 @@ static const struct dma_dev { | |||
88 | { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ | 88 | { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ |
89 | { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ | 89 | { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ |
90 | { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ | 90 | { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ |
91 | { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ | 91 | { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ |
92 | { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ | 92 | { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ |
93 | { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ | 93 | { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ |
94 | { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ | 94 | { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ |
95 | { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ | 95 | { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ |
96 | { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ | 96 | { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ |
97 | /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ | 97 | /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ |
98 | { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ | 98 | { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ |
99 | { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ | 99 | { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ |
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 9ec85597bbf..bdd6651e9a4 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c | |||
@@ -47,7 +47,6 @@ | |||
47 | * We only have to save/restore registers that aren't otherwise | 47 | * We only have to save/restore registers that aren't otherwise |
48 | * done as part of a driver pm_* function. | 48 | * done as part of a driver pm_* function. |
49 | */ | 49 | */ |
50 | static unsigned int sleep_usb[2]; | ||
51 | static unsigned int sleep_sys_clocks[5]; | 50 | static unsigned int sleep_sys_clocks[5]; |
52 | static unsigned int sleep_sys_pinfunc; | 51 | static unsigned int sleep_sys_pinfunc; |
53 | static unsigned int sleep_static_memctlr[4][3]; | 52 | static unsigned int sleep_static_memctlr[4][3]; |
@@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3]; | |||
55 | 54 | ||
56 | static void save_core_regs(void) | 55 | static void save_core_regs(void) |
57 | { | 56 | { |
58 | #ifndef CONFIG_SOC_AU1200 | ||
59 | /* Shutdown USB host/device. */ | ||
60 | sleep_usb[0] = au_readl(USB_HOST_CONFIG); | ||
61 | |||
62 | /* There appears to be some undocumented reset register.... */ | ||
63 | au_writel(0, 0xb0100004); | ||
64 | au_sync(); | ||
65 | au_writel(0, USB_HOST_CONFIG); | ||
66 | au_sync(); | ||
67 | |||
68 | sleep_usb[1] = au_readl(USBD_ENABLE); | ||
69 | au_writel(0, USBD_ENABLE); | ||
70 | au_sync(); | ||
71 | |||
72 | #else /* AU1200 */ | ||
73 | |||
74 | /* enable access to OTG mmio so we can save OTG CAP/MUX. | ||
75 | * FIXME: write an OTG driver and move this stuff there! | ||
76 | */ | ||
77 | au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); | ||
78 | au_sync(); | ||
79 | sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ | ||
80 | sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ | ||
81 | #endif | ||
82 | |||
83 | /* Clocks and PLLs. */ | 57 | /* Clocks and PLLs. */ |
84 | sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); | 58 | sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); |
85 | sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); | 59 | sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); |
@@ -123,22 +97,6 @@ static void restore_core_regs(void) | |||
123 | au_writel(sleep_sys_pinfunc, SYS_PINFUNC); | 97 | au_writel(sleep_sys_pinfunc, SYS_PINFUNC); |
124 | au_sync(); | 98 | au_sync(); |
125 | 99 | ||
126 | #ifndef CONFIG_SOC_AU1200 | ||
127 | au_writel(sleep_usb[0], USB_HOST_CONFIG); | ||
128 | au_writel(sleep_usb[1], USBD_ENABLE); | ||
129 | au_sync(); | ||
130 | #else | ||
131 | /* enable access to OTG memory */ | ||
132 | au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); | ||
133 | au_sync(); | ||
134 | |||
135 | /* restore OTG caps and port mux. */ | ||
136 | au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ | ||
137 | au_sync(); | ||
138 | au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ | ||
139 | au_sync(); | ||
140 | #endif | ||
141 | |||
142 | /* Restore the static memory controller configuration. */ | 100 | /* Restore the static memory controller configuration. */ |
143 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); | 101 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); |
144 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); | 102 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); |