diff options
Diffstat (limited to 'arch/mips/alchemy/common/power.c')
-rw-r--r-- | arch/mips/alchemy/common/power.c | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 9ec85597bbf..bdd6651e9a4 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c | |||
@@ -47,7 +47,6 @@ | |||
47 | * We only have to save/restore registers that aren't otherwise | 47 | * We only have to save/restore registers that aren't otherwise |
48 | * done as part of a driver pm_* function. | 48 | * done as part of a driver pm_* function. |
49 | */ | 49 | */ |
50 | static unsigned int sleep_usb[2]; | ||
51 | static unsigned int sleep_sys_clocks[5]; | 50 | static unsigned int sleep_sys_clocks[5]; |
52 | static unsigned int sleep_sys_pinfunc; | 51 | static unsigned int sleep_sys_pinfunc; |
53 | static unsigned int sleep_static_memctlr[4][3]; | 52 | static unsigned int sleep_static_memctlr[4][3]; |
@@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3]; | |||
55 | 54 | ||
56 | static void save_core_regs(void) | 55 | static void save_core_regs(void) |
57 | { | 56 | { |
58 | #ifndef CONFIG_SOC_AU1200 | ||
59 | /* Shutdown USB host/device. */ | ||
60 | sleep_usb[0] = au_readl(USB_HOST_CONFIG); | ||
61 | |||
62 | /* There appears to be some undocumented reset register.... */ | ||
63 | au_writel(0, 0xb0100004); | ||
64 | au_sync(); | ||
65 | au_writel(0, USB_HOST_CONFIG); | ||
66 | au_sync(); | ||
67 | |||
68 | sleep_usb[1] = au_readl(USBD_ENABLE); | ||
69 | au_writel(0, USBD_ENABLE); | ||
70 | au_sync(); | ||
71 | |||
72 | #else /* AU1200 */ | ||
73 | |||
74 | /* enable access to OTG mmio so we can save OTG CAP/MUX. | ||
75 | * FIXME: write an OTG driver and move this stuff there! | ||
76 | */ | ||
77 | au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); | ||
78 | au_sync(); | ||
79 | sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ | ||
80 | sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ | ||
81 | #endif | ||
82 | |||
83 | /* Clocks and PLLs. */ | 57 | /* Clocks and PLLs. */ |
84 | sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); | 58 | sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); |
85 | sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); | 59 | sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); |
@@ -123,22 +97,6 @@ static void restore_core_regs(void) | |||
123 | au_writel(sleep_sys_pinfunc, SYS_PINFUNC); | 97 | au_writel(sleep_sys_pinfunc, SYS_PINFUNC); |
124 | au_sync(); | 98 | au_sync(); |
125 | 99 | ||
126 | #ifndef CONFIG_SOC_AU1200 | ||
127 | au_writel(sleep_usb[0], USB_HOST_CONFIG); | ||
128 | au_writel(sleep_usb[1], USBD_ENABLE); | ||
129 | au_sync(); | ||
130 | #else | ||
131 | /* enable access to OTG memory */ | ||
132 | au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); | ||
133 | au_sync(); | ||
134 | |||
135 | /* restore OTG caps and port mux. */ | ||
136 | au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ | ||
137 | au_sync(); | ||
138 | au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ | ||
139 | au_sync(); | ||
140 | #endif | ||
141 | |||
142 | /* Restore the static memory controller configuration. */ | 100 | /* Restore the static memory controller configuration. */ |
143 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); | 101 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); |
144 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); | 102 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); |