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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/mips/alchemy
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/gpiolib-au1000.c126
-rw-r--r--arch/mips/alchemy/common/pci.c104
-rw-r--r--arch/mips/alchemy/devboards/db1200/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c567
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c81
-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c255
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c118
-rw-r--r--arch/mips/alchemy/devboards/pb1000/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c209
-rw-r--r--arch/mips/alchemy/devboards/pb1100/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c127
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c50
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile5
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c174
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c203
-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c148
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c49
-rw-r--r--arch/mips/alchemy/devboards/pb1550/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c86
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c69
-rw-r--r--arch/mips/alchemy/devboards/prom.c66
-rw-r--r--arch/mips/alchemy/gpr/Makefile8
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c87
-rw-r--r--arch/mips/alchemy/gpr/init.c63
-rw-r--r--arch/mips/alchemy/gpr/platform.c183
-rw-r--r--arch/mips/alchemy/mtx-1/Makefile9
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c134
-rw-r--r--arch/mips/alchemy/mtx-1/init.c66
-rw-r--r--arch/mips/alchemy/mtx-1/platform.c168
-rw-r--r--arch/mips/alchemy/xxs1500/Makefile8
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c101
-rw-r--r--arch/mips/alchemy/xxs1500/init.c63
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c63
35 files changed, 3431 insertions, 0 deletions
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
new file mode 100644
index 00000000000..c8e1a94d4a9
--- /dev/null
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO block : GPIO1
27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
35
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h>
38
39static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{
41 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
42}
43
44static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
45{
46 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
47}
48
49static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
50{
51 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
52}
53
54static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
55 int value)
56{
57 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
58 value);
59}
60
61static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
62{
63 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
64}
65
66
67static int gpio1_get(struct gpio_chip *chip, unsigned offset)
68{
69 return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
70}
71
72static void gpio1_set(struct gpio_chip *chip,
73 unsigned offset, int value)
74{
75 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
76}
77
78static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
79{
80 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
81}
82
83static int gpio1_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
85{
86 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
87 value);
88}
89
90static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
91{
92 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
93}
94
95struct gpio_chip alchemy_gpio_chip[] = {
96 [0] = {
97 .label = "alchemy-gpio1",
98 .direction_input = gpio1_direction_input,
99 .direction_output = gpio1_direction_output,
100 .get = gpio1_get,
101 .set = gpio1_set,
102 .to_irq = gpio1_to_irq,
103 .base = ALCHEMY_GPIO1_BASE,
104 .ngpio = ALCHEMY_GPIO1_NUM,
105 },
106 [1] = {
107 .label = "alchemy-gpio2",
108 .direction_input = gpio2_direction_input,
109 .direction_output = gpio2_direction_output,
110 .get = gpio2_get,
111 .set = gpio2_set,
112 .to_irq = gpio2_to_irq,
113 .base = ALCHEMY_GPIO2_BASE,
114 .ngpio = ALCHEMY_GPIO2_NUM,
115 },
116};
117
118static int __init alchemy_gpiolib_init(void)
119{
120 gpiochip_add(&alchemy_gpio_chip[0]);
121 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
122 gpiochip_add(&alchemy_gpio_chip[1]);
123
124 return 0;
125}
126arch_initcall(alchemy_gpiolib_init);
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
new file mode 100644
index 00000000000..7866cf50cf9
--- /dev/null
+++ b/arch/mips/alchemy/common/pci.c
@@ -0,0 +1,104 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Alchemy/AMD Au1x00 PCI support.
4 *
5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 *
10 * Support for all devices (greater than 16) added by David Gathright.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#include <linux/pci.h>
34#include <linux/kernel.h>
35#include <linux/init.h>
36
37#include <asm/mach-au1x00/au1000.h>
38
39/* TBD */
40static struct resource pci_io_resource = {
41 .start = PCI_IO_START,
42 .end = PCI_IO_END,
43 .name = "PCI IO space",
44 .flags = IORESOURCE_IO
45};
46
47static struct resource pci_mem_resource = {
48 .start = PCI_MEM_START,
49 .end = PCI_MEM_END,
50 .name = "PCI memory space",
51 .flags = IORESOURCE_MEM
52};
53
54extern struct pci_ops au1x_pci_ops;
55
56static struct pci_controller au1x_controller = {
57 .pci_ops = &au1x_pci_ops,
58 .io_resource = &pci_io_resource,
59 .mem_resource = &pci_mem_resource,
60};
61
62#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
63static unsigned long virt_io_addr;
64#endif
65
66static int __init au1x_pci_setup(void)
67{
68 extern void au1x_pci_cfg_init(void);
69
70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
73
74 if (!virt_io_addr) {
75 printk(KERN_ERR "Unable to ioremap pci space\n");
76 return 1;
77 }
78 au1x_controller.io_map_base = virt_io_addr;
79
80#ifdef CONFIG_DMA_NONCOHERENT
81 {
82 /*
83 * Set the NC bit in controller for Au1500 pre-AC silicon
84 */
85 u32 prid = read_c0_prid();
86
87 if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
88 au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
89 Au1500_PCI_CFG);
90 printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
91 }
92 }
93#endif
94
95 set_io_port_base(virt_io_addr);
96#endif
97
98 au1x_pci_cfg_init();
99
100 register_pci_controller(&au1x_controller);
101 return 0;
102}
103
104arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
new file mode 100644
index 00000000000..17840a5e273
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/Makefile
@@ -0,0 +1 @@
obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
new file mode 100644
index 00000000000..fbb55935b99
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -0,0 +1,567 @@
1/*
2 * DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008-2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/platform_device.h>
32#include <linux/serial_8250.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/flash.h>
35#include <linux/smc91x.h>
36
37#include <asm/mach-au1x00/au1100_mmc.h>
38#include <asm/mach-au1x00/au1xxx_dbdma.h>
39#include <asm/mach-au1x00/au1550_spi.h>
40#include <asm/mach-db1x00/bcsr.h>
41#include <asm/mach-db1x00/db1200.h>
42
43#include "../platform.h"
44
45static struct mtd_partition db1200_spiflash_parts[] = {
46 {
47 .name = "DB1200 SPI flash",
48 .offset = 0,
49 .size = MTDPART_SIZ_FULL,
50 },
51};
52
53static struct flash_platform_data db1200_spiflash_data = {
54 .name = "s25fl001",
55 .parts = db1200_spiflash_parts,
56 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
57 .type = "m25p10",
58};
59
60static struct spi_board_info db1200_spi_devs[] __initdata = {
61 {
62 /* TI TMP121AIDBVR temp sensor */
63 .modalias = "tmp121",
64 .max_speed_hz = 2000000,
65 .bus_num = 0,
66 .chip_select = 0,
67 .mode = 0,
68 },
69 {
70 /* Spansion S25FL001D0FMA SPI flash */
71 .modalias = "m25p80",
72 .max_speed_hz = 50000000,
73 .bus_num = 0,
74 .chip_select = 1,
75 .mode = 0,
76 .platform_data = &db1200_spiflash_data,
77 },
78};
79
80static struct i2c_board_info db1200_i2c_devs[] __initdata = {
81 {
82 /* AT24C04-10 I2C eeprom */
83 I2C_BOARD_INFO("24c04", 0x52),
84 },
85 {
86 /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
87 I2C_BOARD_INFO("ne1619", 0x2d),
88 },
89 {
90 /* I2S audio codec WM8731 */
91 I2C_BOARD_INFO("wm8731", 0x1b),
92 },
93};
94
95/**********************************************************************/
96
97static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 struct nand_chip *this = mtd->priv;
101 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
102
103 ioaddr &= 0xffffff00;
104
105 if (ctrl & NAND_CLE) {
106 ioaddr += MEM_STNAND_CMD;
107 } else if (ctrl & NAND_ALE) {
108 ioaddr += MEM_STNAND_ADDR;
109 } else {
110 /* assume we want to r/w real data by default */
111 ioaddr += MEM_STNAND_DATA;
112 }
113 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
114 if (cmd != NAND_CMD_NONE) {
115 __raw_writeb(cmd, this->IO_ADDR_W);
116 wmb();
117 }
118}
119
120static int au1200_nand_device_ready(struct mtd_info *mtd)
121{
122 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
123}
124
125static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
126
127static struct mtd_partition db1200_nand_parts[] = {
128 {
129 .name = "NAND FS 0",
130 .offset = 0,
131 .size = 8 * 1024 * 1024,
132 },
133 {
134 .name = "NAND FS 1",
135 .offset = MTDPART_OFS_APPEND,
136 .size = MTDPART_SIZ_FULL
137 },
138};
139
140struct platform_nand_data db1200_nand_platdata = {
141 .chip = {
142 .nr_chips = 1,
143 .chip_offset = 0,
144 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
145 .partitions = db1200_nand_parts,
146 .chip_delay = 20,
147 .part_probe_types = db1200_part_probes,
148 },
149 .ctrl = {
150 .dev_ready = au1200_nand_device_ready,
151 .cmd_ctrl = au1200_nand_cmd_ctrl,
152 },
153};
154
155static struct resource db1200_nand_res[] = {
156 [0] = {
157 .start = DB1200_NAND_PHYS_ADDR,
158 .end = DB1200_NAND_PHYS_ADDR + 0xff,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device db1200_nand_dev = {
164 .name = "gen_nand",
165 .num_resources = ARRAY_SIZE(db1200_nand_res),
166 .resource = db1200_nand_res,
167 .id = -1,
168 .dev = {
169 .platform_data = &db1200_nand_platdata,
170 }
171};
172
173/**********************************************************************/
174
175static struct smc91x_platdata db1200_eth_data = {
176 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
177 .leda = RPC_LED_100_10,
178 .ledb = RPC_LED_TX_RX,
179};
180
181static struct resource db1200_eth_res[] = {
182 [0] = {
183 .start = DB1200_ETH_PHYS_ADDR,
184 .end = DB1200_ETH_PHYS_ADDR + 0xf,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = DB1200_ETH_INT,
189 .end = DB1200_ETH_INT,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device db1200_eth_dev = {
195 .dev = {
196 .platform_data = &db1200_eth_data,
197 },
198 .name = "smc91x",
199 .id = -1,
200 .num_resources = ARRAY_SIZE(db1200_eth_res),
201 .resource = db1200_eth_res,
202};
203
204/**********************************************************************/
205
206static struct resource db1200_ide_res[] = {
207 [0] = {
208 .start = DB1200_IDE_PHYS_ADDR,
209 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = DB1200_IDE_INT,
214 .end = DB1200_IDE_INT,
215 .flags = IORESOURCE_IRQ,
216 }
217};
218
219static u64 ide_dmamask = DMA_BIT_MASK(32);
220
221static struct platform_device db1200_ide_dev = {
222 .name = "au1200-ide",
223 .id = 0,
224 .dev = {
225 .dma_mask = &ide_dmamask,
226 .coherent_dma_mask = DMA_BIT_MASK(32),
227 },
228 .num_resources = ARRAY_SIZE(db1200_ide_res),
229 .resource = db1200_ide_res,
230};
231
232/**********************************************************************/
233
234static struct platform_device db1200_rtc_dev = {
235 .name = "rtc-au1xxx",
236 .id = -1,
237};
238
239/**********************************************************************/
240
241/* SD carddetects: they're supposed to be edge-triggered, but ack
242 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
243 * is disabled and its counterpart enabled. The 500ms timeout is
244 * because the carddetect isn't debounced in hardware.
245 */
246static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
247{
248 void(*mmc_cd)(struct mmc_host *, unsigned long);
249
250 if (irq == DB1200_SD0_INSERT_INT) {
251 disable_irq_nosync(DB1200_SD0_INSERT_INT);
252 enable_irq(DB1200_SD0_EJECT_INT);
253 } else {
254 disable_irq_nosync(DB1200_SD0_EJECT_INT);
255 enable_irq(DB1200_SD0_INSERT_INT);
256 }
257
258 /* link against CONFIG_MMC=m */
259 mmc_cd = symbol_get(mmc_detect_change);
260 if (mmc_cd) {
261 mmc_cd(ptr, msecs_to_jiffies(500));
262 symbol_put(mmc_detect_change);
263 }
264
265 return IRQ_HANDLED;
266}
267
268static int db1200_mmc_cd_setup(void *mmc_host, int en)
269{
270 int ret;
271
272 if (en) {
273 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
274 IRQF_DISABLED, "sd_insert", mmc_host);
275 if (ret)
276 goto out;
277
278 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
279 IRQF_DISABLED, "sd_eject", mmc_host);
280 if (ret) {
281 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
282 goto out;
283 }
284
285 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
286 enable_irq(DB1200_SD0_EJECT_INT);
287 else
288 enable_irq(DB1200_SD0_INSERT_INT);
289
290 } else {
291 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
292 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
293 }
294 ret = 0;
295out:
296 return ret;
297}
298
299static void db1200_mmc_set_power(void *mmc_host, int state)
300{
301 if (state) {
302 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
303 msleep(400); /* stabilization time */
304 } else
305 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
306}
307
308static int db1200_mmc_card_readonly(void *mmc_host)
309{
310 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
311}
312
313static int db1200_mmc_card_inserted(void *mmc_host)
314{
315 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
316}
317
318static void db1200_mmcled_set(struct led_classdev *led,
319 enum led_brightness brightness)
320{
321 if (brightness != LED_OFF)
322 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
323 else
324 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
325}
326
327static struct led_classdev db1200_mmc_led = {
328 .brightness_set = db1200_mmcled_set,
329};
330
331/* needed by arch/mips/alchemy/common/platform.c */
332struct au1xmmc_platform_data au1xmmc_platdata[] = {
333 [0] = {
334 .cd_setup = db1200_mmc_cd_setup,
335 .set_power = db1200_mmc_set_power,
336 .card_inserted = db1200_mmc_card_inserted,
337 .card_readonly = db1200_mmc_card_readonly,
338 .led = &db1200_mmc_led,
339 },
340};
341
342/**********************************************************************/
343
344static struct resource au1200_psc0_res[] = {
345 [0] = {
346 .start = PSC0_PHYS_ADDR,
347 .end = PSC0_PHYS_ADDR + 0x000fffff,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AU1200_PSC0_INT,
352 .end = AU1200_PSC0_INT,
353 .flags = IORESOURCE_IRQ,
354 },
355 [2] = {
356 .start = DSCR_CMD0_PSC0_TX,
357 .end = DSCR_CMD0_PSC0_TX,
358 .flags = IORESOURCE_DMA,
359 },
360 [3] = {
361 .start = DSCR_CMD0_PSC0_RX,
362 .end = DSCR_CMD0_PSC0_RX,
363 .flags = IORESOURCE_DMA,
364 },
365};
366
367static struct platform_device db1200_i2c_dev = {
368 .name = "au1xpsc_smbus",
369 .id = 0, /* bus number */
370 .num_resources = ARRAY_SIZE(au1200_psc0_res),
371 .resource = au1200_psc0_res,
372};
373
374static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
375{
376 if (cs)
377 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
378 else
379 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
380}
381
382static struct au1550_spi_info db1200_spi_platdata = {
383 .mainclk_hz = 50000000, /* PSC0 clock */
384 .num_chipselect = 2,
385 .activate_cs = db1200_spi_cs_en,
386};
387
388static u64 spi_dmamask = DMA_BIT_MASK(32);
389
390static struct platform_device db1200_spi_dev = {
391 .dev = {
392 .dma_mask = &spi_dmamask,
393 .coherent_dma_mask = DMA_BIT_MASK(32),
394 .platform_data = &db1200_spi_platdata,
395 },
396 .name = "au1550-spi",
397 .id = 0, /* bus number */
398 .num_resources = ARRAY_SIZE(au1200_psc0_res),
399 .resource = au1200_psc0_res,
400};
401
402static struct resource au1200_psc1_res[] = {
403 [0] = {
404 .start = PSC1_PHYS_ADDR,
405 .end = PSC1_PHYS_ADDR + 0x000fffff,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = AU1200_PSC1_INT,
410 .end = AU1200_PSC1_INT,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 .start = DSCR_CMD0_PSC1_TX,
415 .end = DSCR_CMD0_PSC1_TX,
416 .flags = IORESOURCE_DMA,
417 },
418 [3] = {
419 .start = DSCR_CMD0_PSC1_RX,
420 .end = DSCR_CMD0_PSC1_RX,
421 .flags = IORESOURCE_DMA,
422 },
423};
424
425static struct platform_device db1200_audio_dev = {
426 /* name assigned later based on switch setting */
427 .id = 1, /* PSC ID */
428 .num_resources = ARRAY_SIZE(au1200_psc1_res),
429 .resource = au1200_psc1_res,
430};
431
432static struct platform_device db1200_stac_dev = {
433 .name = "ac97-codec",
434 .id = 1, /* on PSC1 */
435};
436
437static struct platform_device *db1200_devs[] __initdata = {
438 NULL, /* PSC0, selected by S6.8 */
439 &db1200_ide_dev,
440 &db1200_eth_dev,
441 &db1200_rtc_dev,
442 &db1200_nand_dev,
443 &db1200_audio_dev,
444 &db1200_stac_dev,
445};
446
447static int __init db1200_dev_init(void)
448{
449 unsigned long pfc;
450 unsigned short sw;
451 int swapped;
452
453 i2c_register_board_info(0, db1200_i2c_devs,
454 ARRAY_SIZE(db1200_i2c_devs));
455 spi_register_board_info(db1200_spi_devs,
456 ARRAY_SIZE(db1200_i2c_devs));
457
458 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
459 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
460 */
461
462 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
463 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
464 * allow to free it without crippling the SPI interface).
465 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
466 * it as an input pin which is pulled high on the boards).
467 */
468 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
469
470 /* switch off OTG VBUS supply */
471 gpio_request(215, "otg-vbus");
472 gpio_direction_output(215, 1);
473
474 printk(KERN_INFO "DB1200 device configuration:\n");
475
476 sw = bcsr_read(BCSR_SWITCHES);
477 if (sw & BCSR_SWITCHES_DIP_8) {
478 db1200_devs[0] = &db1200_i2c_dev;
479 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
480
481 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
482
483 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
484 printk(KERN_INFO " OTG port VBUS supply available!\n");
485 } else {
486 db1200_devs[0] = &db1200_spi_dev;
487 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
488
489 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
490
491 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
492 printk(KERN_INFO " OTG port VBUS supply disabled\n");
493 }
494 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
495 wmb();
496
497 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
498 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
499 */
500 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
501 if (sw == BCSR_SWITCHES_DIP_8) {
502 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
503 db1200_audio_dev.name = "au1xpsc_i2s";
504 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
505 } else {
506 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
507 db1200_audio_dev.name = "au1xpsc_ac97";
508 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
509 }
510
511 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
512 __raw_writel(PSC_SEL_CLK_SERCLK,
513 (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
514 wmb();
515
516 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
517 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
518 PCMCIA_MEM_PHYS_ADDR,
519 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
520 PCMCIA_IO_PHYS_ADDR,
521 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
522 DB1200_PC0_INT,
523 DB1200_PC0_INSERT_INT,
524 /*DB1200_PC0_STSCHG_INT*/0,
525 DB1200_PC0_EJECT_INT,
526 0);
527
528 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
529 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
530 PCMCIA_MEM_PHYS_ADDR + 0x004000000,
531 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
532 PCMCIA_IO_PHYS_ADDR + 0x004000000,
533 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
534 DB1200_PC1_INT,
535 DB1200_PC1_INSERT_INT,
536 /*DB1200_PC1_STSCHG_INT*/0,
537 DB1200_PC1_EJECT_INT,
538 1);
539
540 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
541 db1x_register_norflash(64 << 20, 2, swapped);
542
543 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
544}
545device_initcall(db1200_dev_init);
546
547/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
548int board_au1200fb_panel(void)
549{
550 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
551}
552
553int board_au1200fb_panel_init(void)
554{
555 /* Apply power */
556 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
557 BCSR_BOARD_LCDBL);
558 return 0;
559}
560
561int board_au1200fb_panel_shutdown(void)
562{
563 /* Remove power */
564 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
565 BCSR_BOARD_LCDBL, 0);
566 return 0;
567}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
new file mode 100644
index 00000000000..4a8980027ec
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -0,0 +1,81 @@
1/*
2 * Alchemy/AMD/RMI DB1200 board setup.
3 *
4 * Licensed under the terms outlined in the file COPYING in the root of
5 * this source archive.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <asm/mach-au1x00/au1000.h>
13#include <asm/mach-db1x00/bcsr.h>
14#include <asm/mach-db1x00/db1200.h>
15
16const char *get_system_type(void)
17{
18 return "Alchemy Db1200";
19}
20
21void __init board_setup(void)
22{
23 unsigned long freq0, clksrc, div, pfc;
24 unsigned short whoami;
25
26 bcsr_init(DB1200_BCSR_PHYS_ADDR,
27 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
28
29 whoami = bcsr_read(BCSR_WHOAMI);
30 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
31 " Board-ID %d Daughtercard ID %d\n",
32 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
33
34 /* SMBus/SPI on PSC0, Audio on PSC1 */
35 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
36 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
37 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
38 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
39 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
40 wmb();
41
42 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
43 * CPU clock; all other clock generators off/unused.
44 */
45 div = (get_au1x00_speed() + 25000000) / 50000000;
46 if (div & 1)
47 div++;
48 div = ((div >> 1) - 1) & 0xff;
49
50 freq0 = div << SYS_FC_FRDIV0_BIT;
51 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
52 wmb();
53 freq0 |= SYS_FC_FE0; /* enable F0 */
54 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
55 wmb();
56
57 /* psc0_intclk comes 1:1 from F0 */
58 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
59 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
60 wmb();
61}
62
63static int __init db1200_arch_init(void)
64{
65 /* GPIO7 is low-level triggered CPLD cascade */
66 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
68
69 /* insert/eject pairs: one of both is always screaming. To avoid
70 * issues they must not be automatically enabled when initially
71 * requested.
72 */
73 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
74 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
75 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
76 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
77 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
78 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
79 return 0;
80}
81arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
new file mode 100644
index 00000000000..613c0c0c8be
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
new file mode 100644
index 00000000000..5c956fe8760
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -0,0 +1,255 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/gpio.h>
31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/pm.h>
34
35#include <asm/mach-au1x00/au1000.h>
36#include <asm/mach-au1x00/au1xxx_eth.h>
37#include <asm/mach-db1x00/db1x00.h>
38#include <asm/mach-db1x00/bcsr.h>
39#include <asm/reboot.h>
40
41#include <prom.h>
42
43#ifdef CONFIG_MIPS_DB1500
44char irq_tab_alchemy[][5] __initdata = {
45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
47};
48
49#endif
50
51
52#ifdef CONFIG_MIPS_DB1550
53char irq_tab_alchemy[][5] __initdata = {
54 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
55 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
56 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
57};
58#endif
59
60
61#ifdef CONFIG_MIPS_BOSPORUS
62char irq_tab_alchemy[][5] __initdata = {
63 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
64 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
65 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
66};
67
68/*
69 * Micrel/Kendin 5 port switch attached to MAC0,
70 * MAC0 is associated with PHY address 5 (== WAN port)
71 * MAC1 is not associated with any PHY, since it's connected directly
72 * to the switch.
73 * no interrupts are used
74 */
75static struct au1000_eth_platform_data eth0_pdata = {
76 .phy_static_config = 1,
77 .phy_addr = 5,
78};
79
80static void bosporus_power_off(void)
81{
82 while (1)
83 asm volatile (".set mips3 ; wait ; .set mips0");
84}
85
86const char *get_system_type(void)
87{
88 return "Alchemy Bosporus Gateway Reference";
89}
90#endif
91
92
93#ifdef CONFIG_MIPS_MIRAGE
94char irq_tab_alchemy[][5] __initdata = {
95 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
96 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
97 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
98};
99
100static void mirage_power_off(void)
101{
102 alchemy_gpio_direction_output(210, 1);
103}
104
105const char *get_system_type(void)
106{
107 return "Alchemy Mirage";
108}
109#endif
110
111
112#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
113static void mips_softreset(void)
114{
115 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
116}
117
118#else
119
120const char *get_system_type(void)
121{
122 return "Alchemy Db1x00";
123}
124#endif
125
126
127void __init board_setup(void)
128{
129 unsigned long bcsr1, bcsr2;
130
131 bcsr1 = DB1000_BCSR_PHYS_ADDR;
132 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
133
134#ifdef CONFIG_MIPS_DB1000
135 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
136#endif
137#ifdef CONFIG_MIPS_DB1500
138 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
139#endif
140#ifdef CONFIG_MIPS_DB1100
141 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
142#endif
143#ifdef CONFIG_MIPS_BOSPORUS
144 au1xxx_override_eth_cfg(0, &eth0_pdata);
145
146 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
147#endif
148#ifdef CONFIG_MIPS_MIRAGE
149 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
150#endif
151#ifdef CONFIG_MIPS_DB1550
152 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
153
154 bcsr1 = DB1550_BCSR_PHYS_ADDR;
155 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
156#endif
157
158 /* initialize board register space */
159 bcsr_init(bcsr1, bcsr2);
160
161 /* Not valid for Au1550 */
162#if defined(CONFIG_IRDA) && \
163 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
164 {
165 u32 pin_func;
166
167 /* Set IRFIRSEL instead of GPIO15 */
168 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
169 au_writel(pin_func, SYS_PINFUNC);
170 /* Power off until the driver is in use */
171 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
172 BCSR_RESETS_IRDA_MODE_OFF);
173 }
174#endif
175 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
176
177 /* Enable GPIO[31:0] inputs */
178 alchemy_gpio1_input_enable();
179
180#ifdef CONFIG_MIPS_MIRAGE
181 {
182 u32 pin_func;
183
184 /* GPIO[20] is output */
185 alchemy_gpio_direction_output(20, 0);
186
187 /* Set GPIO[210:208] instead of SSI_0 */
188 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
189
190 /* Set GPIO[215:211] for LEDs */
191 pin_func |= 5 << 2;
192
193 /* Set GPIO[214:213] for more LEDs */
194 pin_func |= 5 << 12;
195
196 /* Set GPIO[207:200] instead of PCMCIA/LCD */
197 pin_func |= SYS_PF_LCD | SYS_PF_PC;
198 au_writel(pin_func, SYS_PINFUNC);
199
200 /*
201 * Enable speaker amplifier. This should
202 * be part of the audio driver.
203 */
204 alchemy_gpio_direction_output(209, 1);
205
206 pm_power_off = mirage_power_off;
207 _machine_halt = mirage_power_off;
208 _machine_restart = (void(*)(char *))mips_softreset;
209 }
210#endif
211
212#ifdef CONFIG_MIPS_BOSPORUS
213 pm_power_off = bosporus_power_off;
214 _machine_halt = bosporus_power_off;
215 _machine_restart = (void(*)(char *))mips_softreset;
216#endif
217 au_sync();
218}
219
220static int __init db1x00_init_irq(void)
221{
222#if defined(CONFIG_MIPS_MIRAGE)
223 irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
224#elif defined(CONFIG_MIPS_DB1550)
225 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
226 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
227 irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
228 irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
229 irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
230 irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
231#elif defined(CONFIG_MIPS_DB1500)
232 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
233 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
234 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
235 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
236 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
237 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
238#elif defined(CONFIG_MIPS_DB1100)
239 irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
240 irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
241 irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
242 irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
243 irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
244 irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
245#elif defined(CONFIG_MIPS_DB1000)
246 irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
247 irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
248 irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
249 irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
250 irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
251 irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
252#endif
253 return 0;
254}
255arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
new file mode 100644
index 00000000000..978d5ab3d67
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -0,0 +1,118 @@
1/*
2 * DBAu1xxx board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1xxx.h>
25#include <asm/mach-db1x00/bcsr.h>
26#include "../platform.h"
27
28/* DB1xxx PCMCIA interrupt sources:
29 * CD0/1 GPIO0/3
30 * STSCHG0/1 GPIO1/4
31 * CARD0/1 GPIO2/5
32 * Db1550: 0/1, 21/22, 3/5
33 */
34
35#define DB1XXX_HAS_PCMCIA
36#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
37
38#if defined(CONFIG_MIPS_DB1000)
39#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
40#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
41#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
42#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
43#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
44#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
45#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
46#define BOARD_FLASH_WIDTH 4 /* 32-bits */
47#elif defined(CONFIG_MIPS_DB1100)
48#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
49#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
50#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
51#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
52#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
53#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
54#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
55#define BOARD_FLASH_WIDTH 4 /* 32-bits */
56#elif defined(CONFIG_MIPS_DB1500)
57#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
58#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
59#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
60#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
61#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
62#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
63#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
64#define BOARD_FLASH_WIDTH 4 /* 32-bits */
65#elif defined(CONFIG_MIPS_DB1550)
66#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
67#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
68#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
69#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
70#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
71#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
72#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
73#define BOARD_FLASH_WIDTH 4 /* 32-bits */
74#else
75/* other board: no PCMCIA */
76#undef DB1XXX_HAS_PCMCIA
77#undef F_SWAPPED
78#define F_SWAPPED 0
79#if defined(CONFIG_MIPS_BOSPORUS)
80#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
81#define BOARD_FLASH_WIDTH 2 /* 16-bits */
82#elif defined(CONFIG_MIPS_MIRAGE)
83#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
84#define BOARD_FLASH_WIDTH 4 /* 32-bits */
85#endif
86#endif
87
88static int __init db1xxx_dev_init(void)
89{
90#ifdef DB1XXX_HAS_PCMCIA
91 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
92 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
93 PCMCIA_MEM_PHYS_ADDR,
94 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
95 PCMCIA_IO_PHYS_ADDR,
96 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
97 DB1XXX_PCMCIA_CARD0,
98 DB1XXX_PCMCIA_CD0,
99 /*DB1XXX_PCMCIA_STSCHG0*/0,
100 0,
101 0);
102
103 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
104 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
105 PCMCIA_MEM_PHYS_ADDR + 0x004000000,
106 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
107 PCMCIA_IO_PHYS_ADDR + 0x004000000,
108 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
109 DB1XXX_PCMCIA_CARD1,
110 DB1XXX_PCMCIA_CD1,
111 /*DB1XXX_PCMCIA_STSCHG1*/0,
112 0,
113 1);
114#endif
115 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
116 return 0;
117}
118device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
new file mode 100644
index 00000000000..97c6615ba2b
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1000/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1000 board.
6#
7
8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
new file mode 100644
index 00000000000..e64fdcbf75d
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -0,0 +1,209 @@
1/*
2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/pm.h>
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1000.h>
33#include <asm/reboot.h>
34#include <prom.h>
35
36#include "../platform.h"
37
38const char *get_system_type(void)
39{
40 return "Alchemy Pb1000";
41}
42
43static void board_reset(char *c)
44{
45 asm volatile ("jr %0" : : "r" (0xbfc00000));
46}
47
48static void board_power_off(void)
49{
50 while (1)
51 asm volatile (
52 " .set mips32 \n"
53 " wait \n"
54 " .set mips0 \n");
55}
56
57void __init board_setup(void)
58{
59 u32 pin_func, static_cfg0;
60 u32 sys_freqctrl, sys_clksrc;
61 u32 prid = read_c0_prid();
62
63 sys_freqctrl = 0;
64 sys_clksrc = 0;
65
66 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
67 au_writel(8, SYS_AUXPLL);
68 alchemy_gpio1_input_enable();
69 udelay(100);
70
71#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
72 /* Zero and disable FREQ2 */
73 sys_freqctrl = au_readl(SYS_FREQCTRL0);
74 sys_freqctrl &= ~0xFFF00000;
75 au_writel(sys_freqctrl, SYS_FREQCTRL0);
76
77 /* Zero and disable USBH/USBD clocks */
78 sys_clksrc = au_readl(SYS_CLKSRC);
79 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
80 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
81 au_writel(sys_clksrc, SYS_CLKSRC);
82
83 sys_freqctrl = au_readl(SYS_FREQCTRL0);
84 sys_freqctrl &= ~0xFFF00000;
85
86 sys_clksrc = au_readl(SYS_CLKSRC);
87 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
88 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
89
90 switch (prid & 0x000000FF) {
91 case 0x00: /* DA */
92 case 0x01: /* HA */
93 case 0x02: /* HB */
94 /* CPU core freq to 48 MHz to slow it way down... */
95 au_writel(4, SYS_CPUPLL);
96
97 /*
98 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
99 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
100 */
101 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
102 au_writel(sys_freqctrl, SYS_FREQCTRL0);
103
104 /* CPU core freq to 384 MHz */
105 au_writel(0x20, SYS_CPUPLL);
106
107 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
108 break;
109
110 default: /* HC and newer */
111 /* FREQ2 = aux / 2 = 48 MHz */
112 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
113 SYS_FC_FE2 | SYS_FC_FS2;
114 au_writel(sys_freqctrl, SYS_FREQCTRL0);
115 break;
116 }
117
118 /*
119 * Route 48 MHz FREQ2 into USB Host and/or Device
120 */
121 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
122 au_writel(sys_clksrc, SYS_CLKSRC);
123
124 /* Configure pins GPIO[14:9] as GPIO */
125 pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
126
127 /* 2nd USB port is USB host */
128 pin_func |= SYS_PF_USB;
129
130 au_writel(pin_func, SYS_PINFUNC);
131
132 alchemy_gpio_direction_input(11);
133 alchemy_gpio_direction_input(13);
134 alchemy_gpio_direction_output(4, 0);
135 alchemy_gpio_direction_output(5, 0);
136#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
137
138 /* Make GPIO 15 an input (for interrupt line) */
139 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
140 /* We don't need I2S, so make it available for GPIO[31:29] */
141 pin_func |= SYS_PF_I2S;
142 au_writel(pin_func, SYS_PINFUNC);
143
144 alchemy_gpio_direction_input(15);
145
146 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
147 au_writel(static_cfg0, MEM_STCFG0);
148
149 /* configure RCE2* for LCD */
150 au_writel(0x00000004, MEM_STCFG2);
151
152 /* MEM_STTIME2 */
153 au_writel(0x09000000, MEM_STTIME2);
154
155 /* Set 32-bit base address decoding for RCE2* */
156 au_writel(0x10003ff0, MEM_STADDR2);
157
158 /*
159 * PCI CPLD setup
160 * Expand CE0 to cover PCI
161 */
162 au_writel(0x11803e40, MEM_STADDR1);
163
164 /* Burst visibility on */
165 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
166
167 au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
168 au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
169
170 /* Setup the static bus controller */
171 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
172 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
173 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
174
175 /*
176 * Enable Au1000 BCLK switching - note: sed1356 must not use
177 * its BCLK (Au1000 LCLK) for any timings
178 */
179 switch (prid & 0x000000FF) {
180 case 0x00: /* DA */
181 case 0x01: /* HA */
182 case 0x02: /* HB */
183 break;
184 default: /* HC and newer */
185 /*
186 * Enable sys bus clock divider when IDLE state or no bus
187 * activity.
188 */
189 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
190 break;
191 }
192
193 pm_power_off = board_power_off;
194 _machine_halt = board_power_off;
195 _machine_restart = board_reset;
196}
197
198static int __init pb1000_init_irq(void)
199{
200 irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
201 return 0;
202}
203arch_initcall(pb1000_init_irq);
204
205static int __init pb1000_device_init(void)
206{
207 return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
208}
209device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
new file mode 100644
index 00000000000..7e3756c83fe
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1100 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
new file mode 100644
index 00000000000..d108fd573aa
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -0,0 +1,127 @@
1/*
2 * Copyright 2002, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/gpio.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h>
35
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1100";
40}
41
42void __init board_setup(void)
43{
44 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
45
46 bcsr_init(DB1000_BCSR_PHYS_ADDR,
47 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
48
49 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
50 au_writel(8, SYS_AUXPLL);
51 alchemy_gpio1_input_enable();
52 udelay(100);
53
54#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
55 {
56 u32 pin_func, sys_freqctrl, sys_clksrc;
57
58 /* Configure pins GPIO[14:9] as GPIO */
59 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
60
61 /* Zero and disable FREQ2 */
62 sys_freqctrl = au_readl(SYS_FREQCTRL0);
63 sys_freqctrl &= ~0xFFF00000;
64 au_writel(sys_freqctrl, SYS_FREQCTRL0);
65
66 /* Zero and disable USBH/USBD/IrDA clock */
67 sys_clksrc = au_readl(SYS_CLKSRC);
68 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
69 au_writel(sys_clksrc, SYS_CLKSRC);
70
71 sys_freqctrl = au_readl(SYS_FREQCTRL0);
72 sys_freqctrl &= ~0xFFF00000;
73
74 sys_clksrc = au_readl(SYS_CLKSRC);
75 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
76
77 /* FREQ2 = aux / 2 = 48 MHz */
78 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
79 SYS_FC_FE2 | SYS_FC_FS2;
80 au_writel(sys_freqctrl, SYS_FREQCTRL0);
81
82 /*
83 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
84 */
85 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
86 au_writel(sys_clksrc, SYS_CLKSRC);
87
88 /* Setup the static bus controller */
89 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
90 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
91 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
92
93 /*
94 * Get USB Functionality pin state (device vs host drive pins).
95 */
96 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
97 /* 2nd USB port is USB host. */
98 pin_func |= SYS_PF_USB;
99 au_writel(pin_func, SYS_PINFUNC);
100 }
101#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
102
103 /* Enable sys bus clock divider when IDLE state or no bus activity. */
104 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
105
106 /* Enable the RTC if not already enabled. */
107 if (!(readb(base + 0x28) & 0x20)) {
108 writeb(readb(base + 0x28) | 0x20, base + 0x28);
109 au_sync();
110 }
111 /* Put the clock in BCD mode. */
112 if (readb(base + 0x2C) & 0x4) { /* reg B */
113 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
114 au_sync();
115 }
116}
117
118static int __init pb1100_init_irq(void)
119{
120 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
121 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
122 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
123 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
124
125 return 0;
126}
127arch_initcall(pb1100_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
new file mode 100644
index 00000000000..2c8dc29759f
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -0,0 +1,50 @@
1/*
2 * Pb1100 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22
23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-db1x00/bcsr.h>
25
26#include "../platform.h"
27
28static int __init pb1100_dev_init(void)
29{
30 int swapped;
31
32 /* PCMCIA. single socket, identical to Pb1500 */
33 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
34 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
35 PCMCIA_MEM_PHYS_ADDR,
36 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
37 PCMCIA_IO_PHYS_ADDR,
38 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
39 AU1100_GPIO11_INT, /* card */
40 AU1100_GPIO9_INT, /* insert */
41 /*AU1100_GPIO10_INT*/0, /* stschg */
42 0, /* eject */
43 0); /* id */
44
45 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
46 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
47
48 return 0;
49}
50device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
new file mode 100644
index 00000000000..18c1bd53e4c
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3#
4
5obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
new file mode 100644
index 00000000000..6d06b07c238
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -0,0 +1,174 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/sched.h>
30
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h>
33
34#ifdef CONFIG_MIPS_PB1200
35#include <asm/mach-pb1x00/pb1200.h>
36#endif
37
38#ifdef CONFIG_MIPS_DB1200
39#include <asm/mach-db1x00/db1200.h>
40#define PB1200_INT_BEGIN DB1200_INT_BEGIN
41#define PB1200_INT_END DB1200_INT_END
42#endif
43
44#include <prom.h>
45
46const char *get_system_type(void)
47{
48 return "Alchemy Pb1200";
49}
50
51void __init board_setup(void)
52{
53 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
54 bcsr_init(PB1200_BCSR_PHYS_ADDR,
55 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
56
57#if 0
58 {
59 u32 pin_func;
60
61 /*
62 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
63 * but it is board specific code, so put it here.
64 */
65 pin_func = au_readl(SYS_PINFUNC);
66 au_sync();
67 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
68 au_writel(pin_func, SYS_PINFUNC);
69
70 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
71 au_sync();
72 }
73#endif
74
75#if defined(CONFIG_I2C_AU1550)
76 {
77 u32 freq0, clksrc;
78 u32 pin_func;
79
80 /* Select SMBus in CPLD */
81 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
82
83 pin_func = au_readl(SYS_PINFUNC);
84 au_sync();
85 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
86 /* Set GPIOs correctly */
87 pin_func |= 2 << 17;
88 au_writel(pin_func, SYS_PINFUNC);
89 au_sync();
90
91 /* The I2C driver depends on 50 MHz clock */
92 freq0 = au_readl(SYS_FREQCTRL0);
93 au_sync();
94 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
95 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
96 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
97 au_writel(freq0, SYS_FREQCTRL0);
98 au_sync();
99 freq0 |= SYS_FC_FE1;
100 au_writel(freq0, SYS_FREQCTRL0);
101 au_sync();
102
103 clksrc = au_readl(SYS_CLKSRC);
104 au_sync();
105 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
106 /* Bit 22 is EXTCLK0 for PSC0 */
107 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
108 au_writel(clksrc, SYS_CLKSRC);
109 au_sync();
110 }
111#endif
112
113 /*
114 * The Pb1200 development board uses external MUX for PSC0 to
115 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
116 */
117#ifdef CONFIG_I2C_AU1550
118 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
119#endif
120 au_sync();
121}
122
123static int __init pb1200_init_irq(void)
124{
125 /* We have a problem with CPLD rev 3. */
126 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
127 printk(KERN_ERR "WARNING!!!\n");
128 printk(KERN_ERR "WARNING!!!\n");
129 printk(KERN_ERR "WARNING!!!\n");
130 printk(KERN_ERR "WARNING!!!\n");
131 printk(KERN_ERR "WARNING!!!\n");
132 printk(KERN_ERR "WARNING!!!\n");
133 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
134 printk(KERN_ERR "updated to latest revision. This software will\n");
135 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
136 printk(KERN_ERR "WARNING!!!\n");
137 printk(KERN_ERR "WARNING!!!\n");
138 printk(KERN_ERR "WARNING!!!\n");
139 printk(KERN_ERR "WARNING!!!\n");
140 printk(KERN_ERR "WARNING!!!\n");
141 printk(KERN_ERR "WARNING!!!\n");
142 panic("Game over. Your score is 0.");
143 }
144
145 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
146 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
147
148 return 0;
149}
150arch_initcall(pb1200_init_irq);
151
152
153int board_au1200fb_panel(void)
154{
155 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
156}
157
158int board_au1200fb_panel_init(void)
159{
160 /* Apply power */
161 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
162 BCSR_BOARD_LCDBL);
163 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
164 return 0;
165}
166
167int board_au1200fb_panel_shutdown(void)
168{
169 /* Remove power */
170 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
171 BCSR_BOARD_LCDBL, 0);
172 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
173 return 0;
174}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
new file mode 100644
index 00000000000..3ef2dceeb79
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -0,0 +1,203 @@
1/*
2 * Pb1200/DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/leds.h>
24#include <linux/platform_device.h>
25#include <linux/smc91x.h>
26
27#include <asm/mach-au1x00/au1xxx.h>
28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-db1x00/bcsr.h>
30
31#include "../platform.h"
32
33static int mmc_activity;
34
35static void pb1200mmc0_set_power(void *mmc_host, int state)
36{
37 if (state)
38 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
39 else
40 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
41
42 msleep(1);
43}
44
45static int pb1200mmc0_card_readonly(void *mmc_host)
46{
47 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
48}
49
50static int pb1200mmc0_card_inserted(void *mmc_host)
51{
52 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
53}
54
55static void pb1200_mmcled_set(struct led_classdev *led,
56 enum led_brightness brightness)
57{
58 if (brightness != LED_OFF) {
59 if (++mmc_activity == 1)
60 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
61 } else {
62 if (--mmc_activity == 0)
63 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
64 }
65}
66
67static struct led_classdev pb1200mmc_led = {
68 .brightness_set = pb1200_mmcled_set,
69};
70
71static void pb1200mmc1_set_power(void *mmc_host, int state)
72{
73 if (state)
74 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
75 else
76 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
77
78 msleep(1);
79}
80
81static int pb1200mmc1_card_readonly(void *mmc_host)
82{
83 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
84}
85
86static int pb1200mmc1_card_inserted(void *mmc_host)
87{
88 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
89}
90
91const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
92 [0] = {
93 .set_power = pb1200mmc0_set_power,
94 .card_inserted = pb1200mmc0_card_inserted,
95 .card_readonly = pb1200mmc0_card_readonly,
96 .cd_setup = NULL, /* use poll-timer in driver */
97 .led = &pb1200mmc_led,
98 },
99 [1] = {
100 .set_power = pb1200mmc1_set_power,
101 .card_inserted = pb1200mmc1_card_inserted,
102 .card_readonly = pb1200mmc1_card_readonly,
103 .cd_setup = NULL, /* use poll-timer in driver */
104 .led = &pb1200mmc_led,
105 },
106};
107
108static struct resource ide_resources[] = {
109 [0] = {
110 .start = IDE_PHYS_ADDR,
111 .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
112 .flags = IORESOURCE_MEM
113 },
114 [1] = {
115 .start = IDE_INT,
116 .end = IDE_INT,
117 .flags = IORESOURCE_IRQ
118 }
119};
120
121static u64 ide_dmamask = DMA_BIT_MASK(32);
122
123static struct platform_device ide_device = {
124 .name = "au1200-ide",
125 .id = 0,
126 .dev = {
127 .dma_mask = &ide_dmamask,
128 .coherent_dma_mask = DMA_BIT_MASK(32),
129 },
130 .num_resources = ARRAY_SIZE(ide_resources),
131 .resource = ide_resources
132};
133
134static struct smc91x_platdata smc_data = {
135 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
136 .leda = RPC_LED_100_10,
137 .ledb = RPC_LED_TX_RX,
138};
139
140static struct resource smc91c111_resources[] = {
141 [0] = {
142 .name = "smc91x-regs",
143 .start = SMC91C111_PHYS_ADDR,
144 .end = SMC91C111_PHYS_ADDR + 0xf,
145 .flags = IORESOURCE_MEM
146 },
147 [1] = {
148 .start = SMC91C111_INT,
149 .end = SMC91C111_INT,
150 .flags = IORESOURCE_IRQ
151 },
152};
153
154static struct platform_device smc91c111_device = {
155 .dev = {
156 .platform_data = &smc_data,
157 },
158 .name = "smc91x",
159 .id = -1,
160 .num_resources = ARRAY_SIZE(smc91c111_resources),
161 .resource = smc91c111_resources
162};
163
164static struct platform_device *board_platform_devices[] __initdata = {
165 &ide_device,
166 &smc91c111_device
167};
168
169static int __init board_register_devices(void)
170{
171 int swapped;
172
173 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
174 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
175 PCMCIA_MEM_PHYS_ADDR,
176 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
177 PCMCIA_IO_PHYS_ADDR,
178 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
179 PB1200_PC0_INT,
180 PB1200_PC0_INSERT_INT,
181 /*PB1200_PC0_STSCHG_INT*/0,
182 PB1200_PC0_EJECT_INT,
183 0);
184
185 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
186 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
187 PCMCIA_MEM_PHYS_ADDR + 0x008000000,
188 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
189 PCMCIA_IO_PHYS_ADDR + 0x008000000,
190 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
191 PB1200_PC1_INT,
192 PB1200_PC1_INSERT_INT,
193 /*PB1200_PC1_STSCHG_INT*/0,
194 PB1200_PC1_EJECT_INT,
195 1);
196
197 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
198 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
199
200 return platform_add_devices(board_platform_devices,
201 ARRAY_SIZE(board_platform_devices));
202}
203device_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
new file mode 100644
index 00000000000..e83b151b5b6
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1500 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
new file mode 100644
index 00000000000..3b4fa320696
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -0,0 +1,148 @@
1/*
2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h>
35
36
37char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
40};
41
42
43const char *get_system_type(void)
44{
45 return "Alchemy Pb1500";
46}
47
48void __init board_setup(void)
49{
50 u32 pin_func;
51 u32 sys_freqctrl, sys_clksrc;
52
53 bcsr_init(DB1000_BCSR_PHYS_ADDR,
54 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
55
56 sys_clksrc = sys_freqctrl = pin_func = 0;
57 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
58 au_writel(8, SYS_AUXPLL);
59 alchemy_gpio1_input_enable();
60 udelay(100);
61
62 /* GPIO201 is input for PCMCIA card detect */
63 /* GPIO203 is input for PCMCIA interrupt request */
64 alchemy_gpio_direction_input(201);
65 alchemy_gpio_direction_input(203);
66
67#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
68
69 /* Zero and disable FREQ2 */
70 sys_freqctrl = au_readl(SYS_FREQCTRL0);
71 sys_freqctrl &= ~0xFFF00000;
72 au_writel(sys_freqctrl, SYS_FREQCTRL0);
73
74 /* zero and disable USBH/USBD clocks */
75 sys_clksrc = au_readl(SYS_CLKSRC);
76 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
77 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
78 au_writel(sys_clksrc, SYS_CLKSRC);
79
80 sys_freqctrl = au_readl(SYS_FREQCTRL0);
81 sys_freqctrl &= ~0xFFF00000;
82
83 sys_clksrc = au_readl(SYS_CLKSRC);
84 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
85 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
86
87 /* FREQ2 = aux/2 = 48 MHz */
88 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
89 au_writel(sys_freqctrl, SYS_FREQCTRL0);
90
91 /*
92 * Route 48MHz FREQ2 into USB Host and/or Device
93 */
94 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
95 au_writel(sys_clksrc, SYS_CLKSRC);
96
97 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
98 /* 2nd USB port is USB host */
99 pin_func |= SYS_PF_USB;
100 au_writel(pin_func, SYS_PINFUNC);
101#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
102
103#ifdef CONFIG_PCI
104 /* Setup PCI bus controller */
105 au_writel(0, Au1500_PCI_CMEM);
106 au_writel(0x00003fff, Au1500_CFG_BASE);
107#if defined(__MIPSEB__)
108 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
109#else
110 au_writel(0xf, Au1500_PCI_CFG);
111#endif
112 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
113 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
114 au_writel(0x02a00356, Au1500_PCI_STATCMD);
115 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
116 au_writel(0x00000008, Au1500_PCI_MBAR);
117 au_sync();
118#endif
119
120 /* Enable sys bus clock divider when IDLE state or no bus activity. */
121 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
122
123 /* Enable the RTC if not already enabled */
124 if (!(au_readl(0xac000028) & 0x20)) {
125 printk(KERN_INFO "enabling clock ...\n");
126 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
127 }
128 /* Put the clock in BCD mode */
129 if (au_readl(0xac00002c) & 0x4) { /* reg B */
130 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
131 au_sync();
132 }
133}
134
135static int __init pb1500_init_irq(void)
136{
137 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
138 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
139 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
140 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
141 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
142 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
143 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
144 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
145
146 return 0;
147}
148arch_initcall(pb1500_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
new file mode 100644
index 00000000000..d443bc7aa76
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -0,0 +1,49 @@
1/*
2 * Pb1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-db1x00/bcsr.h>
24
25#include "../platform.h"
26
27static int __init pb1500_dev_init(void)
28{
29 int swapped;
30
31 /* PCMCIA. single socket, identical to Pb1500 */
32 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
33 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
34 PCMCIA_MEM_PHYS_ADDR,
35 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
36 PCMCIA_IO_PHYS_ADDR,
37 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
38 AU1500_GPIO11_INT, /* card */
39 AU1500_GPIO9_INT, /* insert */
40 /*AU1500_GPIO10_INT*/0, /* stschg */
41 0, /* eject */
42 0); /* id */
43
44 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
45 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
46
47 return 0;
48}
49device_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
new file mode 100644
index 00000000000..9661b6ec5dd
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1550 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
new file mode 100644
index 00000000000..b790213848b
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -0,0 +1,86 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1550 board setup.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32
33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-pb1x00/pb1550.h>
35#include <asm/mach-db1x00/bcsr.h>
36#include <asm/mach-au1x00/gpio.h>
37
38#include <prom.h>
39
40
41char irq_tab_alchemy[][5] __initdata = {
42 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
43 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
44};
45
46const char *get_system_type(void)
47{
48 return "Alchemy Pb1550";
49}
50
51void __init board_setup(void)
52{
53 u32 pin_func;
54
55 bcsr_init(PB1550_BCSR_PHYS_ADDR,
56 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
57
58 alchemy_gpio2_enable();
59
60 /*
61 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
62 * but it is board specific code, so put it here.
63 */
64 pin_func = au_readl(SYS_PINFUNC);
65 au_sync();
66 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
67 au_writel(pin_func, SYS_PINFUNC);
68
69 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
70
71 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
72}
73
74static int __init pb1550_init_irq(void)
75{
76 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
77 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
78 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
79
80 /* enable both PCMCIA card irqs in the shared line */
81 alchemy_gpio2_enable_int(201);
82 alchemy_gpio2_enable_int(202);
83
84 return 0;
85}
86arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
new file mode 100644
index 00000000000..d7150d0f49c
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -0,0 +1,69 @@
1/*
2 * Pb1550 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22
23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-pb1x00/pb1550.h>
25#include <asm/mach-db1x00/bcsr.h>
26
27#include "../platform.h"
28
29static int __init pb1550_dev_init(void)
30{
31 int swapped;
32
33 /* Pb1550, like all others, also has statuschange irqs; however they're
34 * wired up on one of the Au1550's shared GPIO201_205 line, which also
35 * services the PCMCIA card interrupts. So we ignore statuschange and
36 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
37 * drivers are used to shared irqs and b) statuschange isn't really use-
38 * ful anyway.
39 */
40 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
41 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
42 PCMCIA_MEM_PHYS_ADDR,
43 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 PCMCIA_IO_PHYS_ADDR,
45 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
46 AU1550_GPIO201_205_INT,
47 AU1550_GPIO0_INT,
48 0,
49 0,
50 0);
51
52 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
53 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
54 PCMCIA_MEM_PHYS_ADDR + 0x008000000,
55 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
56 PCMCIA_IO_PHYS_ADDR + 0x008000000,
57 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
58 AU1550_GPIO201_205_INT,
59 AU1550_GPIO1_INT,
60 0,
61 0,
62 1);
63
64 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
65 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
66
67 return 0;
68}
69device_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
new file mode 100644
index 00000000000..e5306b56da6
--- /dev/null
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -0,0 +1,66 @@
1/*
2 * Common code used by all Alchemy develboards.
3 *
4 * Extracted from files which had this to say:
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <asm/bootinfo.h>
33#include <asm/mach-au1x00/au1000.h>
34#include <prom.h>
35
36#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \
37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \
38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \
39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
40#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000
41
42#else /* Au1550/Au1200-based develboards */
43#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000
44#endif
45
46void __init prom_init(void)
47{
48 unsigned char *memsize_str;
49 unsigned long memsize;
50
51 prom_argc = (int)fw_arg0;
52 prom_argv = (char **)fw_arg1;
53 prom_envp = (char **)fw_arg2;
54
55 prom_init_cmdline();
56 memsize_str = prom_getenv("memsize");
57 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
58 memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
59
60 add_memory_region(0, memsize, BOOT_MEM_RAM);
61}
62
63void prom_putchar(unsigned char c)
64{
65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
66}
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
new file mode 100644
index 00000000000..cb73fe256dc
--- /dev/null
+++ b/arch/mips/alchemy/gpr/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for Trapeze ITS GPR board.
6#
7
8obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
new file mode 100644
index 00000000000..5f8f0691ed2
--- /dev/null
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2000-2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/gpio.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/pm.h>
33
34#include <asm/reboot.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39char irq_tab_alchemy[][5] __initdata = {
40 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
41};
42
43static void gpr_reset(char *c)
44{
45 /* switch System-LED to orange (red# and green# on) */
46 alchemy_gpio_direction_output(4, 0);
47 alchemy_gpio_direction_output(5, 0);
48
49 /* trigger watchdog to reset board in 200ms */
50 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
51 raw_local_irq_disable();
52 alchemy_gpio_direction_output(1, 0);
53 udelay(1);
54 alchemy_gpio_set_value(1, 1);
55 while (1)
56 cpu_wait();
57}
58
59static void gpr_power_off(void)
60{
61 while (1)
62 cpu_wait();
63}
64
65void __init board_setup(void)
66{
67 printk(KERN_INFO "Trapeze ITS GPR board\n");
68
69 pm_power_off = gpr_power_off;
70 _machine_halt = gpr_power_off;
71 _machine_restart = gpr_reset;
72
73 /* Enable UART1/3 */
74 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
75 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
76
77 /* Take away Reset of UMTS-card */
78 alchemy_gpio_direction_output(215, 1);
79
80#ifdef CONFIG_PCI
81#if defined(__MIPSEB__)
82 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
83#else
84 au_writel(0xf, Au1500_PCI_CFG);
85#endif
86#endif
87}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
new file mode 100644
index 00000000000..229aafae680
--- /dev/null
+++ b/arch/mips/alchemy/gpr/init.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/kernel.h>
30
31#include <asm/bootinfo.h>
32#include <asm/mach-au1x00/au1000.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38 return "GPR";
39}
40
41void __init prom_init(void)
42{
43 unsigned char *memsize_str;
44 unsigned long memsize;
45
46 prom_argc = fw_arg0;
47 prom_argv = (char **)fw_arg1;
48 prom_envp = (char **)fw_arg2;
49
50 prom_init_cmdline();
51
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x04000000;
55 else
56 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
new file mode 100644
index 00000000000..14b46629cfc
--- /dev/null
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -0,0 +1,183 @@
1/*
2 * GPR board platform device registration
3 *
4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h>
25#include <linux/leds.h>
26#include <linux/gpio.h>
27#include <linux/i2c.h>
28#include <linux/i2c-gpio.h>
29
30#include <asm/mach-au1x00/au1000.h>
31
32/*
33 * Watchdog
34 */
35static struct resource gpr_wdt_resource[] = {
36 [0] = {
37 .start = 1,
38 .end = 1,
39 .name = "gpr-adm6320-wdt",
40 .flags = IORESOURCE_IRQ,
41 }
42};
43
44static struct platform_device gpr_wdt_device = {
45 .name = "adm6320-wdt",
46 .id = 0,
47 .num_resources = ARRAY_SIZE(gpr_wdt_resource),
48 .resource = gpr_wdt_resource,
49};
50
51/*
52 * FLASH
53 *
54 * 0x00000000-0x00200000 : "kernel"
55 * 0x00200000-0x00a00000 : "rootfs"
56 * 0x01d00000-0x01f00000 : "config"
57 * 0x01c00000-0x01d00000 : "yamon"
58 * 0x01d00000-0x01d40000 : "yamon env vars"
59 * 0x00000000-0x00a00000 : "kernel+rootfs"
60 */
61static struct mtd_partition gpr_mtd_partitions[] = {
62 {
63 .name = "kernel",
64 .size = 0x00200000,
65 .offset = 0,
66 },
67 {
68 .name = "rootfs",
69 .size = 0x00800000,
70 .offset = MTDPART_OFS_APPEND,
71 .mask_flags = MTD_WRITEABLE,
72 },
73 {
74 .name = "config",
75 .size = 0x00200000,
76 .offset = 0x01d00000,
77 },
78 {
79 .name = "yamon",
80 .size = 0x00100000,
81 .offset = 0x01c00000,
82 },
83 {
84 .name = "yamon env vars",
85 .size = 0x00040000,
86 .offset = MTDPART_OFS_APPEND,
87 },
88 {
89 .name = "kernel+rootfs",
90 .size = 0x00a00000,
91 .offset = 0,
92 },
93};
94
95static struct physmap_flash_data gpr_flash_data = {
96 .width = 4,
97 .nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
98 .parts = gpr_mtd_partitions,
99};
100
101static struct resource gpr_mtd_resource = {
102 .start = 0x1e000000,
103 .end = 0x1fffffff,
104 .flags = IORESOURCE_MEM,
105};
106
107static struct platform_device gpr_mtd_device = {
108 .name = "physmap-flash",
109 .dev = {
110 .platform_data = &gpr_flash_data,
111 },
112 .num_resources = 1,
113 .resource = &gpr_mtd_resource,
114};
115
116/*
117 * LEDs
118 */
119static struct gpio_led gpr_gpio_leds[] = {
120 { /* green */
121 .name = "gpr:green",
122 .gpio = 4,
123 .active_low = 1,
124 },
125 { /* red */
126 .name = "gpr:red",
127 .gpio = 5,
128 .active_low = 1,
129 }
130};
131
132static struct gpio_led_platform_data gpr_led_data = {
133 .num_leds = ARRAY_SIZE(gpr_gpio_leds),
134 .leds = gpr_gpio_leds,
135};
136
137static struct platform_device gpr_led_devices = {
138 .name = "leds-gpio",
139 .id = -1,
140 .dev = {
141 .platform_data = &gpr_led_data,
142 }
143};
144
145/*
146 * I2C
147 */
148static struct i2c_gpio_platform_data gpr_i2c_data = {
149 .sda_pin = 209,
150 .sda_is_open_drain = 1,
151 .scl_pin = 210,
152 .scl_is_open_drain = 1,
153 .udelay = 2, /* ~100 kHz */
154 .timeout = HZ,
155 };
156
157static struct platform_device gpr_i2c_device = {
158 .name = "i2c-gpio",
159 .id = -1,
160 .dev.platform_data = &gpr_i2c_data,
161};
162
163static struct i2c_board_info gpr_i2c_info[] __initdata = {
164 {
165 I2C_BOARD_INFO("lm83", 0x18),
166 .type = "lm83"
167 }
168};
169
170static struct platform_device *gpr_devices[] __initdata = {
171 &gpr_wdt_device,
172 &gpr_mtd_device,
173 &gpr_i2c_device,
174 &gpr_led_devices,
175};
176
177static int __init gpr_dev_init(void)
178{
179 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
180
181 return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
182}
183device_initcall(gpr_dev_init);
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
new file mode 100644
index 00000000000..81b540ceaf8
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -0,0 +1,9 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4# Bruno Randolf <bruno.randolf@4g-systems.biz>
5#
6# Makefile for 4G Systems MTX-1 board.
7#
8
9obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
new file mode 100644
index 00000000000..3ae984cf98c
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -0,0 +1,134 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * 4G Systems MTX-1 board setup.
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Bruno Randolf <bruno.randolf@4g-systems.biz>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/gpio.h>
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/pm.h>
35
36#include <asm/reboot.h>
37#include <asm/mach-au1x00/au1000.h>
38
39#include <prom.h>
40
41char irq_tab_alchemy[][5] __initdata = {
42 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
43 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
44 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
45 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
46 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
47 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
48 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
49 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
50};
51
52extern int (*board_pci_idsel)(unsigned int devsel, int assert);
53int mtx1_pci_idsel(unsigned int devsel, int assert);
54
55static void mtx1_reset(char *c)
56{
57 /* Jump to the reset vector */
58 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
59}
60
61static void mtx1_power_off(void)
62{
63 while (1)
64 asm volatile (
65 " .set mips32 \n"
66 " wait \n"
67 " .set mips0 \n");
68}
69
70void __init board_setup(void)
71{
72#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
73 /* Enable USB power switch */
74 alchemy_gpio_direction_output(204, 0);
75#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
76
77#ifdef CONFIG_PCI
78#if defined(__MIPSEB__)
79 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
80#else
81 au_writel(0xf, Au1500_PCI_CFG);
82#endif
83 board_pci_idsel = mtx1_pci_idsel;
84#endif
85
86 /* Initialize sys_pinfunc */
87 au_writel(SYS_PF_NI2, SYS_PINFUNC);
88
89 /* Initialize GPIO */
90 au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
91 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
92 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
93 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
94 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
95
96 /* Enable LED and set it to green */
97 alchemy_gpio_direction_output(211, 1); /* green on */
98 alchemy_gpio_direction_output(212, 0); /* red off */
99
100 pm_power_off = mtx1_power_off;
101 _machine_halt = mtx1_power_off;
102 _machine_restart = mtx1_reset;
103
104 printk(KERN_INFO "4G Systems MTX-1 Board\n");
105}
106
107int
108mtx1_pci_idsel(unsigned int devsel, int assert)
109{
110 /* This function is only necessary to support a proprietary Cardbus
111 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
112 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
113 */
114 if (assert && devsel != 0)
115 /* Suppress signal to Cardbus */
116 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
117 else
118 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
119
120 udelay(1);
121 return 1;
122}
123
124static int __init mtx1_init_irq(void)
125{
126 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
127 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
128 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
129 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
130 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
131
132 return 0;
133}
134arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
new file mode 100644
index 00000000000..2e81cc7f342
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -0,0 +1,66 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * 4G Systems MTX-1 board setup
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Bruno Randolf <bruno.randolf@4g-systems.biz>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/bootinfo.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39const char *get_system_type(void)
40{
41 return "MTX-1";
42}
43
44void __init prom_init(void)
45{
46 unsigned char *memsize_str;
47 unsigned long memsize;
48
49 prom_argc = fw_arg0;
50 prom_argv = (char **)fw_arg1;
51 prom_envp = (char **)fw_arg2;
52
53 prom_init_cmdline();
54
55 memsize_str = prom_getenv("memsize");
56 if (!memsize_str)
57 memsize = 0x04000000;
58 else
59 strict_strtoul(memsize_str, 0, &memsize);
60 add_memory_region(0, memsize, BOOT_MEM_RAM);
61}
62
63void prom_putchar(unsigned char c)
64{
65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
66}
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
new file mode 100644
index 00000000000..55628e390fd
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -0,0 +1,168 @@
1/*
2 * MTX-1 platform devices registration
3 *
4 * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/leds.h>
24#include <linux/gpio.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h>
27#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h>
29#include <mtd/mtd-abi.h>
30
31#include <asm/mach-au1x00/au1xxx_eth.h>
32
33static struct gpio_keys_button mtx1_gpio_button[] = {
34 {
35 .gpio = 207,
36 .code = BTN_0,
37 .desc = "System button",
38 }
39};
40
41static struct gpio_keys_platform_data mtx1_buttons_data = {
42 .buttons = mtx1_gpio_button,
43 .nbuttons = ARRAY_SIZE(mtx1_gpio_button),
44};
45
46static struct platform_device mtx1_button = {
47 .name = "gpio-keys",
48 .id = -1,
49 .dev = {
50 .platform_data = &mtx1_buttons_data,
51 }
52};
53
54static struct resource mtx1_wdt_res[] = {
55 [0] = {
56 .start = 215,
57 .end = 215,
58 .name = "mtx1-wdt-gpio",
59 .flags = IORESOURCE_IRQ,
60 }
61};
62
63static struct platform_device mtx1_wdt = {
64 .name = "mtx1-wdt",
65 .id = 0,
66 .num_resources = ARRAY_SIZE(mtx1_wdt_res),
67 .resource = mtx1_wdt_res,
68};
69
70static struct gpio_led default_leds[] = {
71 {
72 .name = "mtx1:green",
73 .gpio = 211,
74 }, {
75 .name = "mtx1:red",
76 .gpio = 212,
77 },
78};
79
80static struct gpio_led_platform_data mtx1_led_data = {
81 .num_leds = ARRAY_SIZE(default_leds),
82 .leds = default_leds,
83};
84
85static struct platform_device mtx1_gpio_leds = {
86 .name = "leds-gpio",
87 .id = -1,
88 .dev = {
89 .platform_data = &mtx1_led_data,
90 }
91};
92
93static struct mtd_partition mtx1_mtd_partitions[] = {
94 {
95 .name = "filesystem",
96 .size = 0x01C00000,
97 .offset = 0,
98 },
99 {
100 .name = "yamon",
101 .size = 0x00100000,
102 .offset = MTDPART_OFS_APPEND,
103 .mask_flags = MTD_WRITEABLE,
104 },
105 {
106 .name = "kernel",
107 .size = 0x002c0000,
108 .offset = MTDPART_OFS_APPEND,
109 },
110 {
111 .name = "yamon env",
112 .size = 0x00040000,
113 .offset = MTDPART_OFS_APPEND,
114 },
115};
116
117static struct physmap_flash_data mtx1_flash_data = {
118 .width = 4,
119 .nr_parts = 4,
120 .parts = mtx1_mtd_partitions,
121};
122
123static struct resource mtx1_mtd_resource = {
124 .start = 0x1e000000,
125 .end = 0x1fffffff,
126 .flags = IORESOURCE_MEM,
127};
128
129static struct platform_device mtx1_mtd = {
130 .name = "physmap-flash",
131 .dev = {
132 .platform_data = &mtx1_flash_data,
133 },
134 .num_resources = 1,
135 .resource = &mtx1_mtd_resource,
136};
137
138static struct __initdata platform_device * mtx1_devs[] = {
139 &mtx1_gpio_leds,
140 &mtx1_wdt,
141 &mtx1_button,
142 &mtx1_mtd,
143};
144
145static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
146 .phy_search_highest_addr = 1,
147 .phy1_search_mac0 = 1,
148};
149
150static int __init mtx1_register_devices(void)
151{
152 int rc;
153
154 au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
155
156 rc = gpio_request(mtx1_gpio_button[0].gpio,
157 mtx1_gpio_button[0].desc);
158 if (rc < 0) {
159 printk(KERN_INFO "mtx1: failed to request %d\n",
160 mtx1_gpio_button[0].gpio);
161 goto out;
162 }
163 gpio_direction_input(mtx1_gpio_button[0].gpio);
164out:
165 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
166}
167
168arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
new file mode 100644
index 00000000000..91defcf4f33
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for MyCable XXS1500 board.
6#
7
8obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
new file mode 100644
index 00000000000..81e57fad07a
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright 2000-2003, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/gpio.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31
32#include <asm/reboot.h>
33#include <asm/mach-au1x00/au1000.h>
34
35#include <prom.h>
36
37static void xxs1500_reset(char *c)
38{
39 /* Jump to the reset vector */
40 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
41}
42
43static void xxs1500_power_off(void)
44{
45 while (1)
46 asm volatile (
47 " .set mips32 \n"
48 " wait \n"
49 " .set mips0 \n");
50}
51
52void __init board_setup(void)
53{
54 u32 pin_func;
55
56 pm_power_off = xxs1500_power_off;
57 _machine_halt = xxs1500_power_off;
58 _machine_restart = xxs1500_reset;
59
60 alchemy_gpio1_input_enable();
61 alchemy_gpio2_enable();
62
63 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
64 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
65 pin_func |= SYS_PF_UR3;
66 au_writel(pin_func, SYS_PINFUNC);
67
68 /* Enable UART */
69 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
70 /* Enable DTR (MCR bit 0) = USB power up */
71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 wmb();
73
74#ifdef CONFIG_PCI
75#if defined(__MIPSEB__)
76 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
77#else
78 au_writel(0xf, Au1500_PCI_CFG);
79#endif
80#endif
81}
82
83static int __init xxs1500_init_irq(void)
84{
85 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
86 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
87 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
88 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
89 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
90 irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
91
92 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
93 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
94 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
95 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
96 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
97 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
98
99 return 0;
100}
101arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
new file mode 100644
index 00000000000..0ee02cfa989
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -0,0 +1,63 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * XXS1500 board setup
4 *
5 * Copyright 2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33#include <asm/mach-au1x00/au1000.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "XXS1500";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52
53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
55 memsize = 0x04000000;
56
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
new file mode 100644
index 00000000000..e87c45cde61
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -0,0 +1,63 @@
1/*
2 * XXS1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1000.h>
25
26static struct resource xxs1500_pcmcia_res[] = {
27 {
28 .name = "pcmcia-io",
29 .flags = IORESOURCE_MEM,
30 .start = PCMCIA_IO_PHYS_ADDR,
31 .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
32 },
33 {
34 .name = "pcmcia-attr",
35 .flags = IORESOURCE_MEM,
36 .start = PCMCIA_ATTR_PHYS_ADDR,
37 .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
38 },
39 {
40 .name = "pcmcia-mem",
41 .flags = IORESOURCE_MEM,
42 .start = PCMCIA_MEM_PHYS_ADDR,
43 .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 },
45};
46
47static struct platform_device xxs1500_pcmcia_dev = {
48 .name = "xxs1500_pcmcia",
49 .id = -1,
50 .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res),
51 .resource = xxs1500_pcmcia_res,
52};
53
54static struct platform_device *xxs1500_devs[] __initdata = {
55 &xxs1500_pcmcia_dev,
56};
57
58static int __init xxs1500_dev_init(void)
59{
60 return platform_add_devices(xxs1500_devs,
61 ARRAY_SIZE(xxs1500_devs));
62}
63device_initcall(xxs1500_dev_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 04:42:54 -0400