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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/m68k/platform/520x
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/m68k/platform/520x')
-rw-r--r--arch/m68k/platform/520x/Makefile17
-rw-r--r--arch/m68k/platform/520x/config.c311
-rw-r--r--arch/m68k/platform/520x/gpio.c211
3 files changed, 539 insertions, 0 deletions
diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
new file mode 100644
index 00000000000..ad3f4e5a57c
--- /dev/null
+++ b/arch/m68k/platform/520x/Makefile
@@ -0,0 +1,17 @@
1#
2# Makefile for the M5208 specific file.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
new file mode 100644
index 00000000000..621238f1a21
--- /dev/null
+++ b/arch/m68k/platform/520x/config.c
@@ -0,0 +1,311 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/520x/config.c
5 *
6 * Copyright (C) 2005, Freescale (www.freescale.com)
7 * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
8 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/spi/spi.h>
19#include <linux/gpio.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h>
24#include <asm/mcfqspi.h>
25
26/***************************************************************************/
27
28static struct mcf_platform_uart m520x_uart_platform[] = {
29 {
30 .mapbase = MCFUART_BASE1,
31 .irq = MCFINT_VECBASE + MCFINT_UART0,
32 },
33 {
34 .mapbase = MCFUART_BASE2,
35 .irq = MCFINT_VECBASE + MCFINT_UART1,
36 },
37 {
38 .mapbase = MCFUART_BASE3,
39 .irq = MCFINT_VECBASE + MCFINT_UART2,
40 },
41 { },
42};
43
44static struct platform_device m520x_uart = {
45 .name = "mcfuart",
46 .id = 0,
47 .dev.platform_data = m520x_uart_platform,
48};
49
50static struct resource m520x_fec_resources[] = {
51 {
52 .start = MCFFEC_BASE,
53 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .start = 64 + 36,
58 .end = 64 + 36,
59 .flags = IORESOURCE_IRQ,
60 },
61 {
62 .start = 64 + 40,
63 .end = 64 + 40,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = 64 + 42,
68 .end = 64 + 42,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73static struct platform_device m520x_fec = {
74 .name = "fec",
75 .id = 0,
76 .num_resources = ARRAY_SIZE(m520x_fec_resources),
77 .resource = m520x_fec_resources,
78};
79
80#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
81static struct resource m520x_qspi_resources[] = {
82 {
83 .start = MCFQSPI_IOBASE,
84 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 {
88 .start = MCFINT_VECBASE + MCFINT_QSPI,
89 .end = MCFINT_VECBASE + MCFINT_QSPI,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94#define MCFQSPI_CS0 62
95#define MCFQSPI_CS1 63
96#define MCFQSPI_CS2 44
97
98static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
99{
100 int status;
101
102 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
103 if (status) {
104 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
105 goto fail0;
106 }
107 status = gpio_direction_output(MCFQSPI_CS0, 1);
108 if (status) {
109 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
110 goto fail1;
111 }
112
113 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
114 if (status) {
115 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
116 goto fail1;
117 }
118 status = gpio_direction_output(MCFQSPI_CS1, 1);
119 if (status) {
120 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
121 goto fail2;
122 }
123
124 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
125 if (status) {
126 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
127 goto fail2;
128 }
129 status = gpio_direction_output(MCFQSPI_CS2, 1);
130 if (status) {
131 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
132 goto fail3;
133 }
134
135 return 0;
136
137fail3:
138 gpio_free(MCFQSPI_CS2);
139fail2:
140 gpio_free(MCFQSPI_CS1);
141fail1:
142 gpio_free(MCFQSPI_CS0);
143fail0:
144 return status;
145}
146
147static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
148{
149 gpio_free(MCFQSPI_CS2);
150 gpio_free(MCFQSPI_CS1);
151 gpio_free(MCFQSPI_CS0);
152}
153
154static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
155 u8 chip_select, bool cs_high)
156{
157 switch (chip_select) {
158 case 0:
159 gpio_set_value(MCFQSPI_CS0, cs_high);
160 break;
161 case 1:
162 gpio_set_value(MCFQSPI_CS1, cs_high);
163 break;
164 case 2:
165 gpio_set_value(MCFQSPI_CS2, cs_high);
166 break;
167 }
168}
169
170static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, !cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, !cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, !cs_high);
182 break;
183 }
184}
185
186static struct mcfqspi_cs_control m520x_cs_control = {
187 .setup = m520x_cs_setup,
188 .teardown = m520x_cs_teardown,
189 .select = m520x_cs_select,
190 .deselect = m520x_cs_deselect,
191};
192
193static struct mcfqspi_platform_data m520x_qspi_data = {
194 .bus_num = 0,
195 .num_chipselect = 3,
196 .cs_control = &m520x_cs_control,
197};
198
199static struct platform_device m520x_qspi = {
200 .name = "mcfqspi",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(m520x_qspi_resources),
203 .resource = m520x_qspi_resources,
204 .dev.platform_data = &m520x_qspi_data,
205};
206
207static void __init m520x_qspi_init(void)
208{
209 u16 par;
210 /* setup Port QS for QSPI with gpio CS control */
211 writeb(0x3f, MCF_GPIO_PAR_QSPI);
212 /* make U1CTS and U2RTS gpio for cs_control */
213 par = readw(MCF_GPIO_PAR_UART);
214 par &= 0x00ff;
215 writew(par, MCF_GPIO_PAR_UART);
216}
217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
218
219
220static struct platform_device *m520x_devices[] __initdata = {
221 &m520x_uart,
222 &m520x_fec,
223#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
224 &m520x_qspi,
225#endif
226};
227
228/***************************************************************************/
229
230static void __init m520x_uart_init_line(int line, int irq)
231{
232 u16 par;
233 u8 par2;
234
235 switch (line) {
236 case 0:
237 par = readw(MCF_GPIO_PAR_UART);
238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
239 MCF_GPIO_PAR_UART_PAR_URXD0;
240 writew(par, MCF_GPIO_PAR_UART);
241 break;
242 case 1:
243 par = readw(MCF_GPIO_PAR_UART);
244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
245 MCF_GPIO_PAR_UART_PAR_URXD1;
246 writew(par, MCF_GPIO_PAR_UART);
247 break;
248 case 2:
249 par2 = readb(MCF_GPIO_PAR_FECI2C);
250 par2 &= ~0x0F;
251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
253 writeb(par2, MCF_GPIO_PAR_FECI2C);
254 break;
255 }
256}
257
258static void __init m520x_uarts_init(void)
259{
260 const int nrlines = ARRAY_SIZE(m520x_uart_platform);
261 int line;
262
263 for (line = 0; (line < nrlines); line++)
264 m520x_uart_init_line(line, m520x_uart_platform[line].irq);
265}
266
267/***************************************************************************/
268
269static void __init m520x_fec_init(void)
270{
271 u8 v;
272
273 /* Set multi-function pins to ethernet mode */
274 v = readb(MCF_GPIO_PAR_FEC);
275 writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
276
277 v = readb(MCF_GPIO_PAR_FECI2C);
278 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
279}
280
281/***************************************************************************/
282
283static void m520x_cpu_reset(void)
284{
285 local_irq_disable();
286 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
287}
288
289/***************************************************************************/
290
291void __init config_BSP(char *commandp, int size)
292{
293 mach_reset = m520x_cpu_reset;
294 m520x_uarts_init();
295 m520x_fec_init();
296#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
297 m520x_qspi_init();
298#endif
299}
300
301/***************************************************************************/
302
303static int __init init_BSP(void)
304{
305 platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
306 return 0;
307}
308
309arch_initcall(init_BSP);
310
311/***************************************************************************/
diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c
new file mode 100644
index 00000000000..d757328563d
--- /dev/null
+++ b/arch/m68k/platform/520x/gpio.c
@@ -0,0 +1,211 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "BUSCTL",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 4,
50 },
51 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
52 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
54 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
55 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
56 },
57 {
58 .gpio_chip = {
59 .label = "BE",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 4,
68 },
69 .pddr = (void __iomem *) MCFGPIO_PDDR_BE,
70 .podr = (void __iomem *) MCFGPIO_PODR_BE,
71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
72 .setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
73 .clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
74 },
75 {
76 .gpio_chip = {
77 .label = "CS",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 25,
85 .ngpio = 3,
86 },
87 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
88 .podr = (void __iomem *) MCFGPIO_PODR_CS,
89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
90 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
91 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
92 },
93 {
94 .gpio_chip = {
95 .label = "FECI2C",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
106 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
108 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
109 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
110 },
111 {
112 .gpio_chip = {
113 .label = "QSPI",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
124 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
126 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
127 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
128 },
129 {
130 .gpio_chip = {
131 .label = "TIMER",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 48,
139 .ngpio = 4,
140 },
141 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
142 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
144 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
145 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
146 },
147 {
148 .gpio_chip = {
149 .label = "UART",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 8,
158 },
159 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
160 .podr = (void __iomem *) MCFGPIO_PODR_UART,
161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
162 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
163 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECH",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 8,
176 },
177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
178 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
179 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
180 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
181 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
182 },
183 {
184 .gpio_chip = {
185 .label = "FECL",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
196 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
197 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
198 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
199 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
200 },
201};
202
203static int __init mcf_gpio_init(void)
204{
205 unsigned i = 0;
206 while (i < ARRAY_SIZE(mcf_gpio_chips))
207 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
208 return 0;
209}
210
211core_initcall(mcf_gpio_init);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-17 20:01:01 -0500