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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/m68k/platform
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/m68k/platform')
-rw-r--r--arch/m68k/platform/5206/Makefile18
-rw-r--r--arch/m68k/platform/5206/config.c127
-rw-r--r--arch/m68k/platform/5206/gpio.c49
-rw-r--r--arch/m68k/platform/520x/Makefile17
-rw-r--r--arch/m68k/platform/520x/config.c311
-rw-r--r--arch/m68k/platform/520x/gpio.c211
-rw-r--r--arch/m68k/platform/523x/Makefile17
-rw-r--r--arch/m68k/platform/523x/config.c293
-rw-r--r--arch/m68k/platform/523x/gpio.c284
-rw-r--r--arch/m68k/platform/5249/Makefile18
-rw-r--r--arch/m68k/platform/5249/config.c330
-rw-r--r--arch/m68k/platform/5249/gpio.c65
-rw-r--r--arch/m68k/platform/5249/intc2.c61
-rw-r--r--arch/m68k/platform/5272/Makefile18
-rw-r--r--arch/m68k/platform/5272/config.c176
-rw-r--r--arch/m68k/platform/5272/gpio.c81
-rw-r--r--arch/m68k/platform/5272/intc.c185
-rw-r--r--arch/m68k/platform/527x/Makefile18
-rw-r--r--arch/m68k/platform/527x/config.c384
-rw-r--r--arch/m68k/platform/527x/gpio.c609
-rw-r--r--arch/m68k/platform/528x/Makefile18
-rw-r--r--arch/m68k/platform/528x/config.c320
-rw-r--r--arch/m68k/platform/528x/gpio.c438
-rw-r--r--arch/m68k/platform/5307/Makefile20
-rw-r--r--arch/m68k/platform/5307/config.c147
-rw-r--r--arch/m68k/platform/5307/gpio.c49
-rw-r--r--arch/m68k/platform/5307/nettel.c153
-rw-r--r--arch/m68k/platform/532x/Makefile18
-rw-r--r--arch/m68k/platform/532x/config.c648
-rw-r--r--arch/m68k/platform/532x/gpio.c337
-rw-r--r--arch/m68k/platform/5407/Makefile18
-rw-r--r--arch/m68k/platform/5407/config.c122
-rw-r--r--arch/m68k/platform/5407/gpio.c49
-rw-r--r--arch/m68k/platform/54xx/Makefile19
-rw-r--r--arch/m68k/platform/54xx/config.c115
-rw-r--r--arch/m68k/platform/54xx/firebee.c86
-rw-r--r--arch/m68k/platform/68328/Makefile22
-rw-r--r--arch/m68k/platform/68328/bootlogo.h270
-rw-r--r--arch/m68k/platform/68328/bootlogo.pl10
-rw-r--r--arch/m68k/platform/68328/config.c52
-rw-r--r--arch/m68k/platform/68328/entry.S261
-rw-r--r--arch/m68k/platform/68328/head-de2.S128
-rw-r--r--arch/m68k/platform/68328/head-pilot.S222
-rw-r--r--arch/m68k/platform/68328/head-ram.S141
-rw-r--r--arch/m68k/platform/68328/head-rom.S110
-rw-r--r--arch/m68k/platform/68328/ints.c188
-rw-r--r--arch/m68k/platform/68328/romvec.S35
-rw-r--r--arch/m68k/platform/68328/timers.c134
-rw-r--r--arch/m68k/platform/68EZ328/Makefile11
-rw-r--r--arch/m68k/platform/68EZ328/bootlogo.h3204
-rw-r--r--arch/m68k/platform/68EZ328/config.c76
-rw-r--r--arch/m68k/platform/68VZ328/Makefile16
-rw-r--r--arch/m68k/platform/68VZ328/config.c188
-rw-r--r--arch/m68k/platform/coldfire/pinmux.c28
54 files changed, 10925 insertions, 0 deletions
diff --git a/arch/m68k/platform/5206/Makefile b/arch/m68k/platform/5206/Makefile
new file mode 100644
index 00000000000..b5db05625cf
--- /dev/null
+++ b/arch/m68k/platform/5206/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/5206/config.c
new file mode 100644
index 00000000000..6fa3f800277
--- /dev/null
+++ b/arch/m68k/platform/5206/config.c
@@ -0,0 +1,127 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5206/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20
21/***************************************************************************/
22
23static struct mcf_platform_uart m5206_uart_platform[] = {
24 {
25 .mapbase = MCF_MBAR + MCFUART_BASE1,
26 .irq = 73,
27 },
28 {
29 .mapbase = MCF_MBAR + MCFUART_BASE2,
30 .irq = 74,
31 },
32 { },
33};
34
35static struct platform_device m5206_uart = {
36 .name = "mcfuart",
37 .id = 0,
38 .dev.platform_data = m5206_uart_platform,
39};
40
41static struct platform_device *m5206_devices[] __initdata = {
42 &m5206_uart,
43};
44
45/***************************************************************************/
46
47static void __init m5206_uart_init_line(int line, int irq)
48{
49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 }
58}
59
60static void __init m5206_uarts_init(void)
61{
62 const int nrlines = ARRAY_SIZE(m5206_uart_platform);
63 int line;
64
65 for (line = 0; (line < nrlines); line++)
66 m5206_uart_init_line(line, m5206_uart_platform[line].irq);
67}
68
69/***************************************************************************/
70
71static void __init m5206_timers_init(void)
72{
73 /* Timer1 is always used as system timer */
74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77
78#ifdef CONFIG_HIGHPROFILE
79 /* Timer2 is to be used as a high speed profile timer */
80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83#endif
84}
85
86/***************************************************************************/
87
88void m5206_cpu_reset(void)
89{
90 local_irq_disable();
91 /* Set watchdog to soft reset, and enabled */
92 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
93 for (;;)
94 /* wait for watchdog to timeout */;
95}
96
97/***************************************************************************/
98
99void __init config_BSP(char *commandp, int size)
100{
101#if defined(CONFIG_NETtel)
102 /* Copy command line from FLASH to local buffer... */
103 memcpy(commandp, (char *) 0xf0004000, size);
104 commandp[size-1] = 0;
105#endif /* CONFIG_NETtel */
106
107 mach_reset = m5206_cpu_reset;
108 m5206_timers_init();
109 m5206_uarts_init();
110
111 /* Only support the external interrupts on their primary level */
112 mcf_mapirq2imr(25, MCFINTC_EINT1);
113 mcf_mapirq2imr(28, MCFINTC_EINT4);
114 mcf_mapirq2imr(31, MCFINTC_EINT7);
115}
116
117/***************************************************************************/
118
119static int __init init_BSP(void)
120{
121 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
122 return 0;
123}
124
125arch_initcall(init_BSP);
126
127/***************************************************************************/
diff --git a/arch/m68k/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c
new file mode 100644
index 00000000000..b9ab4a120f2
--- /dev/null
+++ b/arch/m68k/platform/5206/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
new file mode 100644
index 00000000000..ad3f4e5a57c
--- /dev/null
+++ b/arch/m68k/platform/520x/Makefile
@@ -0,0 +1,17 @@
1#
2# Makefile for the M5208 specific file.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
new file mode 100644
index 00000000000..621238f1a21
--- /dev/null
+++ b/arch/m68k/platform/520x/config.c
@@ -0,0 +1,311 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/520x/config.c
5 *
6 * Copyright (C) 2005, Freescale (www.freescale.com)
7 * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
8 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/spi/spi.h>
19#include <linux/gpio.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h>
24#include <asm/mcfqspi.h>
25
26/***************************************************************************/
27
28static struct mcf_platform_uart m520x_uart_platform[] = {
29 {
30 .mapbase = MCFUART_BASE1,
31 .irq = MCFINT_VECBASE + MCFINT_UART0,
32 },
33 {
34 .mapbase = MCFUART_BASE2,
35 .irq = MCFINT_VECBASE + MCFINT_UART1,
36 },
37 {
38 .mapbase = MCFUART_BASE3,
39 .irq = MCFINT_VECBASE + MCFINT_UART2,
40 },
41 { },
42};
43
44static struct platform_device m520x_uart = {
45 .name = "mcfuart",
46 .id = 0,
47 .dev.platform_data = m520x_uart_platform,
48};
49
50static struct resource m520x_fec_resources[] = {
51 {
52 .start = MCFFEC_BASE,
53 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .start = 64 + 36,
58 .end = 64 + 36,
59 .flags = IORESOURCE_IRQ,
60 },
61 {
62 .start = 64 + 40,
63 .end = 64 + 40,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = 64 + 42,
68 .end = 64 + 42,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73static struct platform_device m520x_fec = {
74 .name = "fec",
75 .id = 0,
76 .num_resources = ARRAY_SIZE(m520x_fec_resources),
77 .resource = m520x_fec_resources,
78};
79
80#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
81static struct resource m520x_qspi_resources[] = {
82 {
83 .start = MCFQSPI_IOBASE,
84 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 {
88 .start = MCFINT_VECBASE + MCFINT_QSPI,
89 .end = MCFINT_VECBASE + MCFINT_QSPI,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94#define MCFQSPI_CS0 62
95#define MCFQSPI_CS1 63
96#define MCFQSPI_CS2 44
97
98static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
99{
100 int status;
101
102 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
103 if (status) {
104 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
105 goto fail0;
106 }
107 status = gpio_direction_output(MCFQSPI_CS0, 1);
108 if (status) {
109 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
110 goto fail1;
111 }
112
113 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
114 if (status) {
115 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
116 goto fail1;
117 }
118 status = gpio_direction_output(MCFQSPI_CS1, 1);
119 if (status) {
120 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
121 goto fail2;
122 }
123
124 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
125 if (status) {
126 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
127 goto fail2;
128 }
129 status = gpio_direction_output(MCFQSPI_CS2, 1);
130 if (status) {
131 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
132 goto fail3;
133 }
134
135 return 0;
136
137fail3:
138 gpio_free(MCFQSPI_CS2);
139fail2:
140 gpio_free(MCFQSPI_CS1);
141fail1:
142 gpio_free(MCFQSPI_CS0);
143fail0:
144 return status;
145}
146
147static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
148{
149 gpio_free(MCFQSPI_CS2);
150 gpio_free(MCFQSPI_CS1);
151 gpio_free(MCFQSPI_CS0);
152}
153
154static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
155 u8 chip_select, bool cs_high)
156{
157 switch (chip_select) {
158 case 0:
159 gpio_set_value(MCFQSPI_CS0, cs_high);
160 break;
161 case 1:
162 gpio_set_value(MCFQSPI_CS1, cs_high);
163 break;
164 case 2:
165 gpio_set_value(MCFQSPI_CS2, cs_high);
166 break;
167 }
168}
169
170static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, !cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, !cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, !cs_high);
182 break;
183 }
184}
185
186static struct mcfqspi_cs_control m520x_cs_control = {
187 .setup = m520x_cs_setup,
188 .teardown = m520x_cs_teardown,
189 .select = m520x_cs_select,
190 .deselect = m520x_cs_deselect,
191};
192
193static struct mcfqspi_platform_data m520x_qspi_data = {
194 .bus_num = 0,
195 .num_chipselect = 3,
196 .cs_control = &m520x_cs_control,
197};
198
199static struct platform_device m520x_qspi = {
200 .name = "mcfqspi",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(m520x_qspi_resources),
203 .resource = m520x_qspi_resources,
204 .dev.platform_data = &m520x_qspi_data,
205};
206
207static void __init m520x_qspi_init(void)
208{
209 u16 par;
210 /* setup Port QS for QSPI with gpio CS control */
211 writeb(0x3f, MCF_GPIO_PAR_QSPI);
212 /* make U1CTS and U2RTS gpio for cs_control */
213 par = readw(MCF_GPIO_PAR_UART);
214 par &= 0x00ff;
215 writew(par, MCF_GPIO_PAR_UART);
216}
217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
218
219
220static struct platform_device *m520x_devices[] __initdata = {
221 &m520x_uart,
222 &m520x_fec,
223#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
224 &m520x_qspi,
225#endif
226};
227
228/***************************************************************************/
229
230static void __init m520x_uart_init_line(int line, int irq)
231{
232 u16 par;
233 u8 par2;
234
235 switch (line) {
236 case 0:
237 par = readw(MCF_GPIO_PAR_UART);
238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
239 MCF_GPIO_PAR_UART_PAR_URXD0;
240 writew(par, MCF_GPIO_PAR_UART);
241 break;
242 case 1:
243 par = readw(MCF_GPIO_PAR_UART);
244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
245 MCF_GPIO_PAR_UART_PAR_URXD1;
246 writew(par, MCF_GPIO_PAR_UART);
247 break;
248 case 2:
249 par2 = readb(MCF_GPIO_PAR_FECI2C);
250 par2 &= ~0x0F;
251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
253 writeb(par2, MCF_GPIO_PAR_FECI2C);
254 break;
255 }
256}
257
258static void __init m520x_uarts_init(void)
259{
260 const int nrlines = ARRAY_SIZE(m520x_uart_platform);
261 int line;
262
263 for (line = 0; (line < nrlines); line++)
264 m520x_uart_init_line(line, m520x_uart_platform[line].irq);
265}
266
267/***************************************************************************/
268
269static void __init m520x_fec_init(void)
270{
271 u8 v;
272
273 /* Set multi-function pins to ethernet mode */
274 v = readb(MCF_GPIO_PAR_FEC);
275 writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
276
277 v = readb(MCF_GPIO_PAR_FECI2C);
278 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
279}
280
281/***************************************************************************/
282
283static void m520x_cpu_reset(void)
284{
285 local_irq_disable();
286 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
287}
288
289/***************************************************************************/
290
291void __init config_BSP(char *commandp, int size)
292{
293 mach_reset = m520x_cpu_reset;
294 m520x_uarts_init();
295 m520x_fec_init();
296#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
297 m520x_qspi_init();
298#endif
299}
300
301/***************************************************************************/
302
303static int __init init_BSP(void)
304{
305 platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
306 return 0;
307}
308
309arch_initcall(init_BSP);
310
311/***************************************************************************/
diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c
new file mode 100644
index 00000000000..d757328563d
--- /dev/null
+++ b/arch/m68k/platform/520x/gpio.c
@@ -0,0 +1,211 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "BUSCTL",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 4,
50 },
51 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
52 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
54 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
55 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
56 },
57 {
58 .gpio_chip = {
59 .label = "BE",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 4,
68 },
69 .pddr = (void __iomem *) MCFGPIO_PDDR_BE,
70 .podr = (void __iomem *) MCFGPIO_PODR_BE,
71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
72 .setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
73 .clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
74 },
75 {
76 .gpio_chip = {
77 .label = "CS",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 25,
85 .ngpio = 3,
86 },
87 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
88 .podr = (void __iomem *) MCFGPIO_PODR_CS,
89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
90 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
91 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
92 },
93 {
94 .gpio_chip = {
95 .label = "FECI2C",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
106 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
108 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
109 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
110 },
111 {
112 .gpio_chip = {
113 .label = "QSPI",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
124 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
126 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
127 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
128 },
129 {
130 .gpio_chip = {
131 .label = "TIMER",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 48,
139 .ngpio = 4,
140 },
141 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
142 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
144 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
145 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
146 },
147 {
148 .gpio_chip = {
149 .label = "UART",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 8,
158 },
159 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
160 .podr = (void __iomem *) MCFGPIO_PODR_UART,
161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
162 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
163 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECH",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 8,
176 },
177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
178 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
179 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
180 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
181 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
182 },
183 {
184 .gpio_chip = {
185 .label = "FECL",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
196 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
197 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
198 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
199 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
200 },
201};
202
203static int __init mcf_gpio_init(void)
204{
205 unsigned i = 0;
206 while (i < ARRAY_SIZE(mcf_gpio_chips))
207 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
208 return 0;
209}
210
211core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/523x/Makefile b/arch/m68k/platform/523x/Makefile
new file mode 100644
index 00000000000..c04b8f71c88
--- /dev/null
+++ b/arch/m68k/platform/523x/Makefile
@@ -0,0 +1,17 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c
new file mode 100644
index 00000000000..71f4436ec80
--- /dev/null
+++ b/arch/m68k/platform/523x/config.c
@@ -0,0 +1,293 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/523x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 523x CPUs.
8 *
9 * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
21#include <asm/machdep.h>
22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
24#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m523x_uart_platform[] = {
30 {
31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 },
34 {
35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
37 },
38 {
39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
41 },
42 { },
43};
44
45static struct platform_device m523x_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m523x_uart_platform,
49};
50
51static struct resource m523x_fec_resources[] = {
52 {
53 .start = MCFFEC_BASE,
54 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = 64 + 23,
59 .end = 64 + 23,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = 64 + 27,
64 .end = 64 + 27,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = 64 + 29,
69 .end = 64 + 29,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct platform_device m523x_fec = {
75 .name = "fec",
76 .id = 0,
77 .num_resources = ARRAY_SIZE(m523x_fec_resources),
78 .resource = m523x_fec_resources,
79};
80
81#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
82static struct resource m523x_qspi_resources[] = {
83 {
84 .start = MCFQSPI_IOBASE,
85 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
86 .flags = IORESOURCE_MEM,
87 },
88 {
89 .start = MCFINT_VECBASE + MCFINT_QSPI,
90 .end = MCFINT_VECBASE + MCFINT_QSPI,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95#define MCFQSPI_CS0 91
96#define MCFQSPI_CS1 92
97#define MCFQSPI_CS2 103
98#define MCFQSPI_CS3 99
99
100static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control)
101{
102 int status;
103
104 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
105 if (status) {
106 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
107 goto fail0;
108 }
109 status = gpio_direction_output(MCFQSPI_CS0, 1);
110 if (status) {
111 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
112 goto fail1;
113 }
114
115 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
116 if (status) {
117 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
118 goto fail1;
119 }
120 status = gpio_direction_output(MCFQSPI_CS1, 1);
121 if (status) {
122 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
123 goto fail2;
124 }
125
126 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
127 if (status) {
128 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
129 goto fail2;
130 }
131 status = gpio_direction_output(MCFQSPI_CS2, 1);
132 if (status) {
133 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
134 goto fail3;
135 }
136
137 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
138 if (status) {
139 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
140 goto fail3;
141 }
142 status = gpio_direction_output(MCFQSPI_CS3, 1);
143 if (status) {
144 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
145 goto fail4;
146 }
147
148 return 0;
149
150fail4:
151 gpio_free(MCFQSPI_CS3);
152fail3:
153 gpio_free(MCFQSPI_CS2);
154fail2:
155 gpio_free(MCFQSPI_CS1);
156fail1:
157 gpio_free(MCFQSPI_CS0);
158fail0:
159 return status;
160}
161
162static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control)
163{
164 gpio_free(MCFQSPI_CS3);
165 gpio_free(MCFQSPI_CS2);
166 gpio_free(MCFQSPI_CS1);
167 gpio_free(MCFQSPI_CS0);
168}
169
170static void m523x_cs_select(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, cs_high);
182 break;
183 case 3:
184 gpio_set_value(MCFQSPI_CS3, cs_high);
185 break;
186 }
187}
188
189static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control,
190 u8 chip_select, bool cs_high)
191{
192 switch (chip_select) {
193 case 0:
194 gpio_set_value(MCFQSPI_CS0, !cs_high);
195 break;
196 case 1:
197 gpio_set_value(MCFQSPI_CS1, !cs_high);
198 break;
199 case 2:
200 gpio_set_value(MCFQSPI_CS2, !cs_high);
201 break;
202 case 3:
203 gpio_set_value(MCFQSPI_CS3, !cs_high);
204 break;
205 }
206}
207
208static struct mcfqspi_cs_control m523x_cs_control = {
209 .setup = m523x_cs_setup,
210 .teardown = m523x_cs_teardown,
211 .select = m523x_cs_select,
212 .deselect = m523x_cs_deselect,
213};
214
215static struct mcfqspi_platform_data m523x_qspi_data = {
216 .bus_num = 0,
217 .num_chipselect = 4,
218 .cs_control = &m523x_cs_control,
219};
220
221static struct platform_device m523x_qspi = {
222 .name = "mcfqspi",
223 .id = 0,
224 .num_resources = ARRAY_SIZE(m523x_qspi_resources),
225 .resource = m523x_qspi_resources,
226 .dev.platform_data = &m523x_qspi_data,
227};
228
229static void __init m523x_qspi_init(void)
230{
231 u16 par;
232
233 /* setup QSPS pins for QSPI with gpio CS control */
234 writeb(0x1f, MCFGPIO_PAR_QSPI);
235 /* and CS2 & CS3 as gpio */
236 par = readw(MCFGPIO_PAR_TIMER);
237 par &= 0x3f3f;
238 writew(par, MCFGPIO_PAR_TIMER);
239}
240#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
241
242static struct platform_device *m523x_devices[] __initdata = {
243 &m523x_uart,
244 &m523x_fec,
245#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
246 &m523x_qspi,
247#endif
248};
249
250/***************************************************************************/
251
252static void __init m523x_fec_init(void)
253{
254 u16 par;
255 u8 v;
256
257 /* Set multi-function pins to ethernet use */
258 par = readw(MCF_IPSBAR + 0x100082);
259 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
260 v = readb(MCF_IPSBAR + 0x100078);
261 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
262}
263
264/***************************************************************************/
265
266static void m523x_cpu_reset(void)
267{
268 local_irq_disable();
269 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
270}
271
272/***************************************************************************/
273
274void __init config_BSP(char *commandp, int size)
275{
276 mach_reset = m523x_cpu_reset;
277}
278
279/***************************************************************************/
280
281static int __init init_BSP(void)
282{
283 m523x_fec_init();
284#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
285 m523x_qspi_init();
286#endif
287 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
288 return 0;
289}
290
291arch_initcall(init_BSP);
292
293/***************************************************************************/
diff --git a/arch/m68k/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c
new file mode 100644
index 00000000000..327ebf142c8
--- /dev/null
+++ b/arch/m68k/platform/523x/gpio.c
@@ -0,0 +1,284 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .base = 1,
34 .ngpio = 7,
35 },
36 .pddr = (void __iomem *) MCFEPORT_EPDDR,
37 .podr = (void __iomem *) MCFEPORT_EPDR,
38 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "ADDR",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 13,
50 .ngpio = 3,
51 },
52 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
53 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
54 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
55 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
57 },
58 {
59 .gpio_chip = {
60 .label = "DATAH",
61 .request = mcf_gpio_request,
62 .free = mcf_gpio_free,
63 .direction_input = mcf_gpio_direction_input,
64 .direction_output = mcf_gpio_direction_output,
65 .get = mcf_gpio_get_value,
66 .set = mcf_gpio_set_value_fast,
67 .base = 16,
68 .ngpio = 8,
69 },
70 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
71 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
72 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
73 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
75 },
76 {
77 .gpio_chip = {
78 .label = "DATAL",
79 .request = mcf_gpio_request,
80 .free = mcf_gpio_free,
81 .direction_input = mcf_gpio_direction_input,
82 .direction_output = mcf_gpio_direction_output,
83 .get = mcf_gpio_get_value,
84 .set = mcf_gpio_set_value_fast,
85 .base = 24,
86 .ngpio = 8,
87 },
88 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
89 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
90 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
91 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
93 },
94 {
95 .gpio_chip = {
96 .label = "BUSCTL",
97 .request = mcf_gpio_request,
98 .free = mcf_gpio_free,
99 .direction_input = mcf_gpio_direction_input,
100 .direction_output = mcf_gpio_direction_output,
101 .get = mcf_gpio_get_value,
102 .set = mcf_gpio_set_value_fast,
103 .base = 32,
104 .ngpio = 8,
105 },
106 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
107 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
108 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
109 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
111 },
112 {
113 .gpio_chip = {
114 .label = "BS",
115 .request = mcf_gpio_request,
116 .free = mcf_gpio_free,
117 .direction_input = mcf_gpio_direction_input,
118 .direction_output = mcf_gpio_direction_output,
119 .get = mcf_gpio_get_value,
120 .set = mcf_gpio_set_value_fast,
121 .base = 40,
122 .ngpio = 4,
123 },
124 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
125 .podr = (void __iomem *) MCFGPIO_PODR_BS,
126 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
127 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
129 },
130 {
131 .gpio_chip = {
132 .label = "CS",
133 .request = mcf_gpio_request,
134 .free = mcf_gpio_free,
135 .direction_input = mcf_gpio_direction_input,
136 .direction_output = mcf_gpio_direction_output,
137 .get = mcf_gpio_get_value,
138 .set = mcf_gpio_set_value_fast,
139 .base = 49,
140 .ngpio = 7,
141 },
142 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
143 .podr = (void __iomem *) MCFGPIO_PODR_CS,
144 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
145 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
147 },
148 {
149 .gpio_chip = {
150 .label = "SDRAM",
151 .request = mcf_gpio_request,
152 .free = mcf_gpio_free,
153 .direction_input = mcf_gpio_direction_input,
154 .direction_output = mcf_gpio_direction_output,
155 .get = mcf_gpio_get_value,
156 .set = mcf_gpio_set_value_fast,
157 .base = 56,
158 .ngpio = 6,
159 },
160 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
161 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
162 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
163 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
165 },
166 {
167 .gpio_chip = {
168 .label = "FECI2C",
169 .request = mcf_gpio_request,
170 .free = mcf_gpio_free,
171 .direction_input = mcf_gpio_direction_input,
172 .direction_output = mcf_gpio_direction_output,
173 .get = mcf_gpio_get_value,
174 .set = mcf_gpio_set_value_fast,
175 .base = 64,
176 .ngpio = 4,
177 },
178 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
179 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
180 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
181 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
183 },
184 {
185 .gpio_chip = {
186 .label = "UARTH",
187 .request = mcf_gpio_request,
188 .free = mcf_gpio_free,
189 .direction_input = mcf_gpio_direction_input,
190 .direction_output = mcf_gpio_direction_output,
191 .get = mcf_gpio_get_value,
192 .set = mcf_gpio_set_value_fast,
193 .base = 72,
194 .ngpio = 2,
195 },
196 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
197 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
198 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
199 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
201 },
202 {
203 .gpio_chip = {
204 .label = "UARTL",
205 .request = mcf_gpio_request,
206 .free = mcf_gpio_free,
207 .direction_input = mcf_gpio_direction_input,
208 .direction_output = mcf_gpio_direction_output,
209 .get = mcf_gpio_get_value,
210 .set = mcf_gpio_set_value_fast,
211 .base = 80,
212 .ngpio = 8,
213 },
214 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
215 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
216 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
217 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
219 },
220 {
221 .gpio_chip = {
222 .label = "QSPI",
223 .request = mcf_gpio_request,
224 .free = mcf_gpio_free,
225 .direction_input = mcf_gpio_direction_input,
226 .direction_output = mcf_gpio_direction_output,
227 .get = mcf_gpio_get_value,
228 .set = mcf_gpio_set_value_fast,
229 .base = 88,
230 .ngpio = 5,
231 },
232 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
233 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
234 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
235 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
237 },
238 {
239 .gpio_chip = {
240 .label = "TIMER",
241 .request = mcf_gpio_request,
242 .free = mcf_gpio_free,
243 .direction_input = mcf_gpio_direction_input,
244 .direction_output = mcf_gpio_direction_output,
245 .get = mcf_gpio_get_value,
246 .set = mcf_gpio_set_value_fast,
247 .base = 96,
248 .ngpio = 8,
249 },
250 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
251 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
252 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
253 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
255 },
256 {
257 .gpio_chip = {
258 .label = "ETPU",
259 .request = mcf_gpio_request,
260 .free = mcf_gpio_free,
261 .direction_input = mcf_gpio_direction_input,
262 .direction_output = mcf_gpio_direction_output,
263 .get = mcf_gpio_get_value,
264 .set = mcf_gpio_set_value_fast,
265 .base = 104,
266 .ngpio = 3,
267 },
268 .pddr = (void __iomem *) MCFGPIO_PDDR_ETPU,
269 .podr = (void __iomem *) MCFGPIO_PODR_ETPU,
270 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
271 .setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
272 .clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU,
273 },
274};
275
276static int __init mcf_gpio_init(void)
277{
278 unsigned i = 0;
279 while (i < ARRAY_SIZE(mcf_gpio_chips))
280 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
281 return 0;
282}
283
284core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile
new file mode 100644
index 00000000000..4bed30fd007
--- /dev/null
+++ b/arch/m68k/platform/5249/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o intc2.o
18
diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c
new file mode 100644
index 00000000000..ceb31e5744a
--- /dev/null
+++ b/arch/m68k/platform/5249/config.c
@@ -0,0 +1,330 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5249/config.c
5 *
6 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
17#include <asm/machdep.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/mcfuart.h>
21#include <asm/mcfqspi.h>
22
23/***************************************************************************/
24
25static struct mcf_platform_uart m5249_uart_platform[] = {
26 {
27 .mapbase = MCF_MBAR + MCFUART_BASE1,
28 .irq = 73,
29 },
30 {
31 .mapbase = MCF_MBAR + MCFUART_BASE2,
32 .irq = 74,
33 },
34 { },
35};
36
37static struct platform_device m5249_uart = {
38 .name = "mcfuart",
39 .id = 0,
40 .dev.platform_data = m5249_uart_platform,
41};
42
43#ifdef CONFIG_M5249C3
44
45static struct resource m5249_smc91x_resources[] = {
46 {
47 .start = 0xe0000300,
48 .end = 0xe0000300 + 0x100,
49 .flags = IORESOURCE_MEM,
50 },
51 {
52 .start = MCFINTC2_GPIOIRQ6,
53 .end = MCFINTC2_GPIOIRQ6,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct platform_device m5249_smc91x = {
59 .name = "smc91x",
60 .id = 0,
61 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
62 .resource = m5249_smc91x_resources,
63};
64
65#endif /* CONFIG_M5249C3 */
66
67#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
68static struct resource m5249_qspi_resources[] = {
69 {
70 .start = MCFQSPI_IOBASE,
71 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .start = MCF_IRQ_QSPI,
76 .end = MCF_IRQ_QSPI,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81#define MCFQSPI_CS0 29
82#define MCFQSPI_CS1 24
83#define MCFQSPI_CS2 21
84#define MCFQSPI_CS3 22
85
86static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
87{
88 int status;
89
90 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
91 if (status) {
92 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
93 goto fail0;
94 }
95 status = gpio_direction_output(MCFQSPI_CS0, 1);
96 if (status) {
97 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
98 goto fail1;
99 }
100
101 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
102 if (status) {
103 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
104 goto fail1;
105 }
106 status = gpio_direction_output(MCFQSPI_CS1, 1);
107 if (status) {
108 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
109 goto fail2;
110 }
111
112 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
113 if (status) {
114 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
115 goto fail2;
116 }
117 status = gpio_direction_output(MCFQSPI_CS2, 1);
118 if (status) {
119 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
120 goto fail3;
121 }
122
123 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
124 if (status) {
125 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
126 goto fail3;
127 }
128 status = gpio_direction_output(MCFQSPI_CS3, 1);
129 if (status) {
130 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
131 goto fail4;
132 }
133
134 return 0;
135
136fail4:
137 gpio_free(MCFQSPI_CS3);
138fail3:
139 gpio_free(MCFQSPI_CS2);
140fail2:
141 gpio_free(MCFQSPI_CS1);
142fail1:
143 gpio_free(MCFQSPI_CS0);
144fail0:
145 return status;
146}
147
148static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
149{
150 gpio_free(MCFQSPI_CS3);
151 gpio_free(MCFQSPI_CS2);
152 gpio_free(MCFQSPI_CS1);
153 gpio_free(MCFQSPI_CS0);
154}
155
156static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
157 u8 chip_select, bool cs_high)
158{
159 switch (chip_select) {
160 case 0:
161 gpio_set_value(MCFQSPI_CS0, cs_high);
162 break;
163 case 1:
164 gpio_set_value(MCFQSPI_CS1, cs_high);
165 break;
166 case 2:
167 gpio_set_value(MCFQSPI_CS2, cs_high);
168 break;
169 case 3:
170 gpio_set_value(MCFQSPI_CS3, cs_high);
171 break;
172 }
173}
174
175static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
176 u8 chip_select, bool cs_high)
177{
178 switch (chip_select) {
179 case 0:
180 gpio_set_value(MCFQSPI_CS0, !cs_high);
181 break;
182 case 1:
183 gpio_set_value(MCFQSPI_CS1, !cs_high);
184 break;
185 case 2:
186 gpio_set_value(MCFQSPI_CS2, !cs_high);
187 break;
188 case 3:
189 gpio_set_value(MCFQSPI_CS3, !cs_high);
190 break;
191 }
192}
193
194static struct mcfqspi_cs_control m5249_cs_control = {
195 .setup = m5249_cs_setup,
196 .teardown = m5249_cs_teardown,
197 .select = m5249_cs_select,
198 .deselect = m5249_cs_deselect,
199};
200
201static struct mcfqspi_platform_data m5249_qspi_data = {
202 .bus_num = 0,
203 .num_chipselect = 4,
204 .cs_control = &m5249_cs_control,
205};
206
207static struct platform_device m5249_qspi = {
208 .name = "mcfqspi",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(m5249_qspi_resources),
211 .resource = m5249_qspi_resources,
212 .dev.platform_data = &m5249_qspi_data,
213};
214
215static void __init m5249_qspi_init(void)
216{
217 /* QSPI irq setup */
218 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
219 MCF_MBAR + MCFSIM_QSPIICR);
220 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
221}
222#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
223
224
225static struct platform_device *m5249_devices[] __initdata = {
226 &m5249_uart,
227#ifdef CONFIG_M5249C3
228 &m5249_smc91x,
229#endif
230#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
231 &m5249_qspi,
232#endif
233};
234
235/***************************************************************************/
236
237static void __init m5249_uart_init_line(int line, int irq)
238{
239 if (line == 0) {
240 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
241 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
242 mcf_mapirq2imr(irq, MCFINTC_UART0);
243 } else if (line == 1) {
244 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
245 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
246 mcf_mapirq2imr(irq, MCFINTC_UART1);
247 }
248}
249
250static void __init m5249_uarts_init(void)
251{
252 const int nrlines = ARRAY_SIZE(m5249_uart_platform);
253 int line;
254
255 for (line = 0; (line < nrlines); line++)
256 m5249_uart_init_line(line, m5249_uart_platform[line].irq);
257}
258
259/***************************************************************************/
260
261#ifdef CONFIG_M5249C3
262
263static void __init m5249_smc91x_init(void)
264{
265 u32 gpio;
266
267 /* Set the GPIO line as interrupt source for smc91x device */
268 gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
269 writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
270
271 gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
272 writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
273}
274
275#endif /* CONFIG_M5249C3 */
276
277/***************************************************************************/
278
279static void __init m5249_timers_init(void)
280{
281 /* Timer1 is always used as system timer */
282 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
283 MCF_MBAR + MCFSIM_TIMER1ICR);
284 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
285
286#ifdef CONFIG_HIGHPROFILE
287 /* Timer2 is to be used as a high speed profile timer */
288 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
289 MCF_MBAR + MCFSIM_TIMER2ICR);
290 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
291#endif
292}
293
294/***************************************************************************/
295
296void m5249_cpu_reset(void)
297{
298 local_irq_disable();
299 /* Set watchdog to soft reset, and enabled */
300 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
301 for (;;)
302 /* wait for watchdog to timeout */;
303}
304
305/***************************************************************************/
306
307void __init config_BSP(char *commandp, int size)
308{
309 mach_reset = m5249_cpu_reset;
310 m5249_timers_init();
311 m5249_uarts_init();
312#ifdef CONFIG_M5249C3
313 m5249_smc91x_init();
314#endif
315#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
316 m5249_qspi_init();
317#endif
318}
319
320/***************************************************************************/
321
322static int __init init_BSP(void)
323{
324 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
325 return 0;
326}
327
328arch_initcall(init_BSP);
329
330/***************************************************************************/
diff --git a/arch/m68k/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c
new file mode 100644
index 00000000000..2b56c6ef65b
--- /dev/null
+++ b/arch/m68k/platform/5249/gpio.c
@@ -0,0 +1,65 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "GPIO0",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 32,
34 },
35 .pddr = (void __iomem *) MCFSIM2_GPIOENABLE,
36 .podr = (void __iomem *) MCFSIM2_GPIOWRITE,
37 .ppdr = (void __iomem *) MCFSIM2_GPIOREAD,
38 },
39 {
40 .gpio_chip = {
41 .label = "GPIO1",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 32,
49 .ngpio = 32,
50 },
51 .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE,
52 .podr = (void __iomem *) MCFSIM2_GPIO1WRITE,
53 .ppdr = (void __iomem *) MCFSIM2_GPIO1READ,
54 },
55};
56
57static int __init mcf_gpio_init(void)
58{
59 unsigned i = 0;
60 while (i < ARRAY_SIZE(mcf_gpio_chips))
61 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
62 return 0;
63}
64
65core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/5249/intc2.c
new file mode 100644
index 00000000000..f343bf7bf5b
--- /dev/null
+++ b/arch/m68k/platform/5249/intc2.c
@@ -0,0 +1,61 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 5249
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20static void intc2_irq_gpio_mask(struct irq_data *d)
21{
22 u32 imr;
23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
26}
27
28static void intc2_irq_gpio_unmask(struct irq_data *d)
29{
30 u32 imr;
31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
34}
35
36static void intc2_irq_gpio_ack(struct irq_data *d)
37{
38 writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
39}
40
41static struct irq_chip intc2_irq_gpio_chip = {
42 .name = "CF-INTC2",
43 .irq_mask = intc2_irq_gpio_mask,
44 .irq_unmask = intc2_irq_gpio_unmask,
45 .irq_ack = intc2_irq_gpio_ack,
46};
47
48static int __init mcf_intc2_init(void)
49{
50 int irq;
51
52 /* GPIO interrupt sources */
53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
54 irq_set_chip(irq, &intc2_irq_gpio_chip);
55 irq_set_handler(irq, handle_edge_irq);
56 }
57
58 return 0;
59}
60
61arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile
new file mode 100644
index 00000000000..34110fc1430
--- /dev/null
+++ b/arch/m68k/platform/5272/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o intc.o
18
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/5272/config.c
new file mode 100644
index 00000000000..65bb582734e
--- /dev/null
+++ b/arch/m68k/platform/5272/config.c
@@ -0,0 +1,176 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5272/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
18#include <asm/machdep.h>
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h>
22
23/***************************************************************************/
24
25/*
26 * Some platforms need software versions of the GPIO data registers.
27 */
28unsigned short ppdata;
29unsigned char ledbank = 0xff;
30
31/***************************************************************************/
32
33static struct mcf_platform_uart m5272_uart_platform[] = {
34 {
35 .mapbase = MCF_MBAR + MCFUART_BASE1,
36 .irq = MCF_IRQ_UART1,
37 },
38 {
39 .mapbase = MCF_MBAR + MCFUART_BASE2,
40 .irq = MCF_IRQ_UART2,
41 },
42 { },
43};
44
45static struct platform_device m5272_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m5272_uart_platform,
49};
50
51static struct resource m5272_fec_resources[] = {
52 {
53 .start = MCF_MBAR + 0x840,
54 .end = MCF_MBAR + 0x840 + 0x1cf,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = MCF_IRQ_ERX,
59 .end = MCF_IRQ_ERX,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = MCF_IRQ_ETX,
64 .end = MCF_IRQ_ETX,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = MCF_IRQ_ENTC,
69 .end = MCF_IRQ_ENTC,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct platform_device m5272_fec = {
75 .name = "fec",
76 .id = 0,
77 .num_resources = ARRAY_SIZE(m5272_fec_resources),
78 .resource = m5272_fec_resources,
79};
80
81static struct platform_device *m5272_devices[] __initdata = {
82 &m5272_uart,
83 &m5272_fec,
84};
85
86/***************************************************************************/
87
88static void __init m5272_uart_init_line(int line, int irq)
89{
90 u32 v;
91
92 if ((line >= 0) && (line < 2)) {
93 /* Enable the output lines for the serial ports */
94 v = readl(MCF_MBAR + MCFSIM_PBCNT);
95 v = (v & ~0x000000ff) | 0x00000055;
96 writel(v, MCF_MBAR + MCFSIM_PBCNT);
97
98 v = readl(MCF_MBAR + MCFSIM_PDCNT);
99 v = (v & ~0x000003fc) | 0x000002a8;
100 writel(v, MCF_MBAR + MCFSIM_PDCNT);
101 }
102}
103
104static void __init m5272_uarts_init(void)
105{
106 const int nrlines = ARRAY_SIZE(m5272_uart_platform);
107 int line;
108
109 for (line = 0; (line < nrlines); line++)
110 m5272_uart_init_line(line, m5272_uart_platform[line].irq);
111}
112
113/***************************************************************************/
114
115static void m5272_cpu_reset(void)
116{
117 local_irq_disable();
118 /* Set watchdog to reset, and enabled */
119 __raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
120 __raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
121 __raw_writew(0, MCF_MBAR + MCFSIM_WCR);
122 for (;;)
123 /* wait for watchdog to timeout */;
124}
125
126/***************************************************************************/
127
128void __init config_BSP(char *commandp, int size)
129{
130#if defined (CONFIG_MOD5272)
131 volatile unsigned char *pivrp;
132
133 /* Set base of device vectors to be 64 */
134 pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
135 *pivrp = 0x40;
136#endif
137
138#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
139 /* Copy command line from FLASH to local buffer... */
140 memcpy(commandp, (char *) 0xf0004000, size);
141 commandp[size-1] = 0;
142#elif defined(CONFIG_CANCam)
143 /* Copy command line from FLASH to local buffer... */
144 memcpy(commandp, (char *) 0xf0010000, size);
145 commandp[size-1] = 0;
146#endif
147
148 mach_reset = m5272_cpu_reset;
149}
150
151/***************************************************************************/
152
153/*
154 * Some 5272 based boards have the FEC ethernet diectly connected to
155 * an ethernet switch. In this case we need to use the fixed phy type,
156 * and we need to declare it early in boot.
157 */
158static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
159 .link = 1,
160 .speed = 100,
161 .duplex = 0,
162};
163
164/***************************************************************************/
165
166static int __init init_BSP(void)
167{
168 m5272_uarts_init();
169 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
170 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
171 return 0;
172}
173
174arch_initcall(init_BSP);
175
176/***************************************************************************/
diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c
new file mode 100644
index 00000000000..57ac10a5d7f
--- /dev/null
+++ b/arch/m68k/platform/5272/gpio.c
@@ -0,0 +1,81 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PA",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39 {
40 .gpio_chip = {
41 .label = "PB",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 16,
49 .ngpio = 16,
50 },
51 .pddr = (void __iomem *) MCFSIM_PBDDR,
52 .podr = (void __iomem *) MCFSIM_PBDAT,
53 .ppdr = (void __iomem *) MCFSIM_PBDAT,
54 },
55 {
56 .gpio_chip = {
57 .label = "PC",
58 .request = mcf_gpio_request,
59 .free = mcf_gpio_free,
60 .direction_input = mcf_gpio_direction_input,
61 .direction_output = mcf_gpio_direction_output,
62 .get = mcf_gpio_get_value,
63 .set = mcf_gpio_set_value,
64 .base = 32,
65 .ngpio = 16,
66 },
67 .pddr = (void __iomem *) MCFSIM_PCDDR,
68 .podr = (void __iomem *) MCFSIM_PCDAT,
69 .ppdr = (void __iomem *) MCFSIM_PCDAT,
70 },
71};
72
73static int __init mcf_gpio_init(void)
74{
75 unsigned i = 0;
76 while (i < ARRAY_SIZE(mcf_gpio_chips))
77 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
78 return 0;
79}
80
81core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c
new file mode 100644
index 00000000000..7160e618b0a
--- /dev/null
+++ b/arch/m68k/platform/5272/intc.c
@@ -0,0 +1,185 @@
1/*
2 * intc.c -- interrupt controller or ColdFire 5272 SoC
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/kernel_stat.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/traps.h>
21
22/*
23 * The 5272 ColdFire interrupt controller is nothing like any other
24 * ColdFire interrupt controller - it truly is completely different.
25 * Given its age it is unlikely to be used on any other ColdFire CPU.
26 */
27
28/*
29 * The masking and priproty setting of interrupts on the 5272 is done
30 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
31 * loose mapping of vector number to register and internal bits, but
32 * a table is the easiest and quickest way to map them.
33 *
34 * Note that the external interrupts are edge triggered (unlike the
35 * internal interrupt sources which are level triggered). Which means
36 * they also need acknowledging via acknowledge bits.
37 */
38struct irqmap {
39 unsigned char icr;
40 unsigned char index;
41 unsigned char ack;
42};
43
44static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
45 /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
54 /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
55 /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
56 /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
57 /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
58 /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
59 /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
60 /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
61 /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
62 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
63 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
64 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
65 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
66 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
67 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
68 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
69 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
70 /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
71 /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
72 /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
73 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
74};
75
76/*
77 * The act of masking the interrupt also has a side effect of 'ack'ing
78 * an interrupt on this irq (for the external irqs). So this mask function
79 * is also an ack_mask function.
80 */
81static void intc_irq_mask(struct irq_data *d)
82{
83 unsigned int irq = d->irq;
84
85 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
86 u32 v;
87 irq -= MCFINT_VECBASE;
88 v = 0x8 << intc_irqmap[irq].index;
89 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
90 }
91}
92
93static void intc_irq_unmask(struct irq_data *d)
94{
95 unsigned int irq = d->irq;
96
97 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
98 u32 v;
99 irq -= MCFINT_VECBASE;
100 v = 0xd << intc_irqmap[irq].index;
101 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
102 }
103}
104
105static void intc_irq_ack(struct irq_data *d)
106{
107 unsigned int irq = d->irq;
108
109 /* Only external interrupts are acked */
110 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
111 irq -= MCFINT_VECBASE;
112 if (intc_irqmap[irq].ack) {
113 u32 v;
114 v = readl(MCF_MBAR + intc_irqmap[irq].icr);
115 v &= (0x7 << intc_irqmap[irq].index);
116 v |= (0x8 << intc_irqmap[irq].index);
117 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
118 }
119 }
120}
121
122static int intc_irq_set_type(struct irq_data *d, unsigned int type)
123{
124 unsigned int irq = d->irq;
125
126 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
127 irq -= MCFINT_VECBASE;
128 if (intc_irqmap[irq].ack) {
129 u32 v;
130 v = readl(MCF_MBAR + MCFSIM_PITR);
131 if (type == IRQ_TYPE_EDGE_FALLING)
132 v &= ~(0x1 << (32 - irq));
133 else
134 v |= (0x1 << (32 - irq));
135 writel(v, MCF_MBAR + MCFSIM_PITR);
136 }
137 }
138 return 0;
139}
140
141/*
142 * Simple flow handler to deal with the external edge triggered interrupts.
143 * We need to be careful with the masking/acking due to the side effects
144 * of masking an interrupt.
145 */
146static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
147{
148 irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
149 handle_simple_irq(irq, desc);
150}
151
152static struct irq_chip intc_irq_chip = {
153 .name = "CF-INTC",
154 .irq_mask = intc_irq_mask,
155 .irq_unmask = intc_irq_unmask,
156 .irq_mask_ack = intc_irq_mask,
157 .irq_ack = intc_irq_ack,
158 .irq_set_type = intc_irq_set_type,
159};
160
161void __init init_IRQ(void)
162{
163 int irq, edge;
164
165 /* Mask all interrupt sources */
166 writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
167 writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
168 writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
169 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
170
171 for (irq = 0; (irq < NR_IRQS); irq++) {
172 irq_set_chip(irq, &intc_irq_chip);
173 edge = 0;
174 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
175 edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
176 if (edge) {
177 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
178 irq_set_handler(irq, intc_external_irq);
179 } else {
180 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
181 irq_set_handler(irq, handle_level_irq);
182 }
183 }
184}
185
diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile
new file mode 100644
index 00000000000..6ac4b57370e
--- /dev/null
+++ b/arch/m68k/platform/527x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
new file mode 100644
index 00000000000..3ebc769cefd
--- /dev/null
+++ b/arch/m68k/platform/527x/config.c
@@ -0,0 +1,384 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/527x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 5270/5271 CPUs.
8 *
9 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
21#include <asm/machdep.h>
22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
24#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m527x_uart_platform[] = {
30 {
31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 },
34 {
35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART1,
37 },
38 {
39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART2,
41 },
42 { },
43};
44
45static struct platform_device m527x_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m527x_uart_platform,
49};
50
51static struct resource m527x_fec0_resources[] = {
52 {
53 .start = MCFFEC_BASE0,
54 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = 64 + 23,
59 .end = 64 + 23,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = 64 + 27,
64 .end = 64 + 27,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = 64 + 29,
69 .end = 64 + 29,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct resource m527x_fec1_resources[] = {
75 {
76 .start = MCFFEC_BASE1,
77 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .start = 128 + 23,
82 .end = 128 + 23,
83 .flags = IORESOURCE_IRQ,
84 },
85 {
86 .start = 128 + 27,
87 .end = 128 + 27,
88 .flags = IORESOURCE_IRQ,
89 },
90 {
91 .start = 128 + 29,
92 .end = 128 + 29,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device m527x_fec[] = {
98 {
99 .name = "fec",
100 .id = 0,
101 .num_resources = ARRAY_SIZE(m527x_fec0_resources),
102 .resource = m527x_fec0_resources,
103 },
104 {
105 .name = "fec",
106 .id = 1,
107 .num_resources = ARRAY_SIZE(m527x_fec1_resources),
108 .resource = m527x_fec1_resources,
109 },
110};
111
112#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
113static struct resource m527x_qspi_resources[] = {
114 {
115 .start = MCFQSPI_IOBASE,
116 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = MCFINT_VECBASE + MCFINT_QSPI,
121 .end = MCFINT_VECBASE + MCFINT_QSPI,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126#if defined(CONFIG_M5271)
127#define MCFQSPI_CS0 91
128#define MCFQSPI_CS1 92
129#define MCFQSPI_CS2 99
130#define MCFQSPI_CS3 103
131#elif defined(CONFIG_M5275)
132#define MCFQSPI_CS0 59
133#define MCFQSPI_CS1 60
134#define MCFQSPI_CS2 61
135#define MCFQSPI_CS3 62
136#endif
137
138static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
139{
140 int status;
141
142 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
143 if (status) {
144 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
145 goto fail0;
146 }
147 status = gpio_direction_output(MCFQSPI_CS0, 1);
148 if (status) {
149 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
150 goto fail1;
151 }
152
153 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
154 if (status) {
155 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
156 goto fail1;
157 }
158 status = gpio_direction_output(MCFQSPI_CS1, 1);
159 if (status) {
160 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
161 goto fail2;
162 }
163
164 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
165 if (status) {
166 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
167 goto fail2;
168 }
169 status = gpio_direction_output(MCFQSPI_CS2, 1);
170 if (status) {
171 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
172 goto fail3;
173 }
174
175 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
176 if (status) {
177 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
178 goto fail3;
179 }
180 status = gpio_direction_output(MCFQSPI_CS3, 1);
181 if (status) {
182 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
183 goto fail4;
184 }
185
186 return 0;
187
188fail4:
189 gpio_free(MCFQSPI_CS3);
190fail3:
191 gpio_free(MCFQSPI_CS2);
192fail2:
193 gpio_free(MCFQSPI_CS1);
194fail1:
195 gpio_free(MCFQSPI_CS0);
196fail0:
197 return status;
198}
199
200static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
201{
202 gpio_free(MCFQSPI_CS3);
203 gpio_free(MCFQSPI_CS2);
204 gpio_free(MCFQSPI_CS1);
205 gpio_free(MCFQSPI_CS0);
206}
207
208static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
209 u8 chip_select, bool cs_high)
210{
211 switch (chip_select) {
212 case 0:
213 gpio_set_value(MCFQSPI_CS0, cs_high);
214 break;
215 case 1:
216 gpio_set_value(MCFQSPI_CS1, cs_high);
217 break;
218 case 2:
219 gpio_set_value(MCFQSPI_CS2, cs_high);
220 break;
221 case 3:
222 gpio_set_value(MCFQSPI_CS3, cs_high);
223 break;
224 }
225}
226
227static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
228 u8 chip_select, bool cs_high)
229{
230 switch (chip_select) {
231 case 0:
232 gpio_set_value(MCFQSPI_CS0, !cs_high);
233 break;
234 case 1:
235 gpio_set_value(MCFQSPI_CS1, !cs_high);
236 break;
237 case 2:
238 gpio_set_value(MCFQSPI_CS2, !cs_high);
239 break;
240 case 3:
241 gpio_set_value(MCFQSPI_CS3, !cs_high);
242 break;
243 }
244}
245
246static struct mcfqspi_cs_control m527x_cs_control = {
247 .setup = m527x_cs_setup,
248 .teardown = m527x_cs_teardown,
249 .select = m527x_cs_select,
250 .deselect = m527x_cs_deselect,
251};
252
253static struct mcfqspi_platform_data m527x_qspi_data = {
254 .bus_num = 0,
255 .num_chipselect = 4,
256 .cs_control = &m527x_cs_control,
257};
258
259static struct platform_device m527x_qspi = {
260 .name = "mcfqspi",
261 .id = 0,
262 .num_resources = ARRAY_SIZE(m527x_qspi_resources),
263 .resource = m527x_qspi_resources,
264 .dev.platform_data = &m527x_qspi_data,
265};
266
267static void __init m527x_qspi_init(void)
268{
269#if defined(CONFIG_M5271)
270 u16 par;
271
272 /* setup QSPS pins for QSPI with gpio CS control */
273 writeb(0x1f, MCFGPIO_PAR_QSPI);
274 /* and CS2 & CS3 as gpio */
275 par = readw(MCFGPIO_PAR_TIMER);
276 par &= 0x3f3f;
277 writew(par, MCFGPIO_PAR_TIMER);
278#elif defined(CONFIG_M5275)
279 /* setup QSPS pins for QSPI with gpio CS control */
280 writew(0x003e, MCFGPIO_PAR_QSPI);
281#endif
282}
283#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
284
285static struct platform_device *m527x_devices[] __initdata = {
286 &m527x_uart,
287 &m527x_fec[0],
288#ifdef CONFIG_FEC2
289 &m527x_fec[1],
290#endif
291#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
292 &m527x_qspi,
293#endif
294};
295
296/***************************************************************************/
297
298static void __init m527x_uart_init_line(int line, int irq)
299{
300 u16 sepmask;
301
302 if ((line < 0) || (line > 2))
303 return;
304
305 /*
306 * External Pin Mask Setting & Enable External Pin for Interface
307 */
308 sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
309 if (line == 0)
310 sepmask |= UART0_ENABLE_MASK;
311 else if (line == 1)
312 sepmask |= UART1_ENABLE_MASK;
313 else if (line == 2)
314 sepmask |= UART2_ENABLE_MASK;
315 writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
316}
317
318static void __init m527x_uarts_init(void)
319{
320 const int nrlines = ARRAY_SIZE(m527x_uart_platform);
321 int line;
322
323 for (line = 0; (line < nrlines); line++)
324 m527x_uart_init_line(line, m527x_uart_platform[line].irq);
325}
326
327/***************************************************************************/
328
329static void __init m527x_fec_init(void)
330{
331 u16 par;
332 u8 v;
333
334 /* Set multi-function pins to ethernet mode for fec0 */
335#if defined(CONFIG_M5271)
336 v = readb(MCF_IPSBAR + 0x100047);
337 writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
338#else
339 par = readw(MCF_IPSBAR + 0x100082);
340 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
341 v = readb(MCF_IPSBAR + 0x100078);
342 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
343#endif
344
345#ifdef CONFIG_FEC2
346 /* Set multi-function pins to ethernet mode for fec1 */
347 par = readw(MCF_IPSBAR + 0x100082);
348 writew(par | 0xa0, MCF_IPSBAR + 0x100082);
349 v = readb(MCF_IPSBAR + 0x100079);
350 writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
351#endif
352}
353
354/***************************************************************************/
355
356static void m527x_cpu_reset(void)
357{
358 local_irq_disable();
359 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
360}
361
362/***************************************************************************/
363
364void __init config_BSP(char *commandp, int size)
365{
366 mach_reset = m527x_cpu_reset;
367 m527x_uarts_init();
368 m527x_fec_init();
369#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
370 m527x_qspi_init();
371#endif
372}
373
374/***************************************************************************/
375
376static int __init init_BSP(void)
377{
378 platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
379 return 0;
380}
381
382arch_initcall(init_BSP);
383
384/***************************************************************************/
diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c
new file mode 100644
index 00000000000..205da0aa0f2
--- /dev/null
+++ b/arch/m68k/platform/527x/gpio.c
@@ -0,0 +1,609 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24#if defined(CONFIG_M5271)
25 {
26 .gpio_chip = {
27 .label = "PIRQ",
28 .request = mcf_gpio_request,
29 .free = mcf_gpio_free,
30 .direction_input = mcf_gpio_direction_input,
31 .direction_output = mcf_gpio_direction_output,
32 .get = mcf_gpio_get_value,
33 .set = mcf_gpio_set_value,
34 .base = 1,
35 .ngpio = 7,
36 },
37 .pddr = (void __iomem *) MCFEPORT_EPDDR,
38 .podr = (void __iomem *) MCFEPORT_EPDR,
39 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
40 },
41 {
42 .gpio_chip = {
43 .label = "ADDR",
44 .request = mcf_gpio_request,
45 .free = mcf_gpio_free,
46 .direction_input = mcf_gpio_direction_input,
47 .direction_output = mcf_gpio_direction_output,
48 .get = mcf_gpio_get_value,
49 .set = mcf_gpio_set_value_fast,
50 .base = 13,
51 .ngpio = 3,
52 },
53 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
54 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
55 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
56 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
57 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
58 },
59 {
60 .gpio_chip = {
61 .label = "DATAH",
62 .request = mcf_gpio_request,
63 .free = mcf_gpio_free,
64 .direction_input = mcf_gpio_direction_input,
65 .direction_output = mcf_gpio_direction_output,
66 .get = mcf_gpio_get_value,
67 .set = mcf_gpio_set_value_fast,
68 .base = 16,
69 .ngpio = 8,
70 },
71 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
72 .podr = (void __iomem *) MCFGPIO_PODR_DATAH,
73 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
74 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
75 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
76 },
77 {
78 .gpio_chip = {
79 .label = "DATAL",
80 .request = mcf_gpio_request,
81 .free = mcf_gpio_free,
82 .direction_input = mcf_gpio_direction_input,
83 .direction_output = mcf_gpio_direction_output,
84 .get = mcf_gpio_get_value,
85 .set = mcf_gpio_set_value_fast,
86 .base = 24,
87 .ngpio = 8,
88 },
89 .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
90 .podr = (void __iomem *) MCFGPIO_PODR_DATAL,
91 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
92 .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
93 .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
94 },
95 {
96 .gpio_chip = {
97 .label = "BUSCTL",
98 .request = mcf_gpio_request,
99 .free = mcf_gpio_free,
100 .direction_input = mcf_gpio_direction_input,
101 .direction_output = mcf_gpio_direction_output,
102 .get = mcf_gpio_get_value,
103 .set = mcf_gpio_set_value_fast,
104 .base = 32,
105 .ngpio = 8,
106 },
107 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
108 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
109 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
110 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
111 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
112 },
113 {
114 .gpio_chip = {
115 .label = "BS",
116 .request = mcf_gpio_request,
117 .free = mcf_gpio_free,
118 .direction_input = mcf_gpio_direction_input,
119 .direction_output = mcf_gpio_direction_output,
120 .get = mcf_gpio_get_value,
121 .set = mcf_gpio_set_value_fast,
122 .base = 40,
123 .ngpio = 4,
124 },
125 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
126 .podr = (void __iomem *) MCFGPIO_PODR_BS,
127 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
128 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
129 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
130 },
131 {
132 .gpio_chip = {
133 .label = "CS",
134 .request = mcf_gpio_request,
135 .free = mcf_gpio_free,
136 .direction_input = mcf_gpio_direction_input,
137 .direction_output = mcf_gpio_direction_output,
138 .get = mcf_gpio_get_value,
139 .set = mcf_gpio_set_value_fast,
140 .base = 49,
141 .ngpio = 7,
142 },
143 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
144 .podr = (void __iomem *) MCFGPIO_PODR_CS,
145 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
146 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
147 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
148 },
149 {
150 .gpio_chip = {
151 .label = "SDRAM",
152 .request = mcf_gpio_request,
153 .free = mcf_gpio_free,
154 .direction_input = mcf_gpio_direction_input,
155 .direction_output = mcf_gpio_direction_output,
156 .get = mcf_gpio_get_value,
157 .set = mcf_gpio_set_value_fast,
158 .base = 56,
159 .ngpio = 6,
160 },
161 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
162 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
163 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
164 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
165 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
166 },
167 {
168 .gpio_chip = {
169 .label = "FECI2C",
170 .request = mcf_gpio_request,
171 .free = mcf_gpio_free,
172 .direction_input = mcf_gpio_direction_input,
173 .direction_output = mcf_gpio_direction_output,
174 .get = mcf_gpio_get_value,
175 .set = mcf_gpio_set_value_fast,
176 .base = 64,
177 .ngpio = 4,
178 },
179 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
180 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
181 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
182 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
183 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
184 },
185 {
186 .gpio_chip = {
187 .label = "UARTH",
188 .request = mcf_gpio_request,
189 .free = mcf_gpio_free,
190 .direction_input = mcf_gpio_direction_input,
191 .direction_output = mcf_gpio_direction_output,
192 .get = mcf_gpio_get_value,
193 .set = mcf_gpio_set_value_fast,
194 .base = 72,
195 .ngpio = 2,
196 },
197 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
198 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
199 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
200 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
201 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
202 },
203 {
204 .gpio_chip = {
205 .label = "UARTL",
206 .request = mcf_gpio_request,
207 .free = mcf_gpio_free,
208 .direction_input = mcf_gpio_direction_input,
209 .direction_output = mcf_gpio_direction_output,
210 .get = mcf_gpio_get_value,
211 .set = mcf_gpio_set_value_fast,
212 .base = 80,
213 .ngpio = 8,
214 },
215 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
216 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
217 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
218 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
219 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
220 },
221 {
222 .gpio_chip = {
223 .label = "QSPI",
224 .request = mcf_gpio_request,
225 .free = mcf_gpio_free,
226 .direction_input = mcf_gpio_direction_input,
227 .direction_output = mcf_gpio_direction_output,
228 .get = mcf_gpio_get_value,
229 .set = mcf_gpio_set_value_fast,
230 .base = 88,
231 .ngpio = 5,
232 },
233 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
234 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
235 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
236 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
237 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
238 },
239 {
240 .gpio_chip = {
241 .label = "TIMER",
242 .request = mcf_gpio_request,
243 .free = mcf_gpio_free,
244 .direction_input = mcf_gpio_direction_input,
245 .direction_output = mcf_gpio_direction_output,
246 .get = mcf_gpio_get_value,
247 .set = mcf_gpio_set_value_fast,
248 .base = 96,
249 .ngpio = 8,
250 },
251 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
252 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
253 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
254 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
255 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
256 },
257#elif defined(CONFIG_M5275)
258 {
259 .gpio_chip = {
260 .label = "PIRQ",
261 .request = mcf_gpio_request,
262 .free = mcf_gpio_free,
263 .direction_input = mcf_gpio_direction_input,
264 .direction_output = mcf_gpio_direction_output,
265 .get = mcf_gpio_get_value,
266 .set = mcf_gpio_set_value,
267 .base = 1,
268 .ngpio = 7,
269 },
270 .pddr = (void __iomem *) MCFEPORT_EPDDR,
271 .podr = (void __iomem *) MCFEPORT_EPDR,
272 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
273 },
274 {
275 .gpio_chip = {
276 .label = "BUSCTL",
277 .request = mcf_gpio_request,
278 .free = mcf_gpio_free,
279 .direction_input = mcf_gpio_direction_input,
280 .direction_output = mcf_gpio_direction_output,
281 .get = mcf_gpio_get_value,
282 .set = mcf_gpio_set_value_fast,
283 .base = 8,
284 .ngpio = 8,
285 },
286 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
287 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
288 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
289 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
290 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
291 },
292 {
293 .gpio_chip = {
294 .label = "ADDR",
295 .request = mcf_gpio_request,
296 .free = mcf_gpio_free,
297 .direction_input = mcf_gpio_direction_input,
298 .direction_output = mcf_gpio_direction_output,
299 .get = mcf_gpio_get_value,
300 .set = mcf_gpio_set_value_fast,
301 .base = 21,
302 .ngpio = 3,
303 },
304 .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
305 .podr = (void __iomem *) MCFGPIO_PODR_ADDR,
306 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
307 .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
308 .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
309 },
310 {
311 .gpio_chip = {
312 .label = "CS",
313 .request = mcf_gpio_request,
314 .free = mcf_gpio_free,
315 .direction_input = mcf_gpio_direction_input,
316 .direction_output = mcf_gpio_direction_output,
317 .get = mcf_gpio_get_value,
318 .set = mcf_gpio_set_value_fast,
319 .base = 25,
320 .ngpio = 7,
321 },
322 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
323 .podr = (void __iomem *) MCFGPIO_PODR_CS,
324 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
325 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
326 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
327 },
328 {
329 .gpio_chip = {
330 .label = "FEC0H",
331 .request = mcf_gpio_request,
332 .free = mcf_gpio_free,
333 .direction_input = mcf_gpio_direction_input,
334 .direction_output = mcf_gpio_direction_output,
335 .get = mcf_gpio_get_value,
336 .set = mcf_gpio_set_value_fast,
337 .base = 32,
338 .ngpio = 8,
339 },
340 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H,
341 .podr = (void __iomem *) MCFGPIO_PODR_FEC0H,
342 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
343 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
344 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
345 },
346 {
347 .gpio_chip = {
348 .label = "FEC0L",
349 .request = mcf_gpio_request,
350 .free = mcf_gpio_free,
351 .direction_input = mcf_gpio_direction_input,
352 .direction_output = mcf_gpio_direction_output,
353 .get = mcf_gpio_get_value,
354 .set = mcf_gpio_set_value_fast,
355 .base = 40,
356 .ngpio = 8,
357 },
358 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L,
359 .podr = (void __iomem *) MCFGPIO_PODR_FEC0L,
360 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
361 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
362 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
363 },
364 {
365 .gpio_chip = {
366 .label = "FECI2C",
367 .request = mcf_gpio_request,
368 .free = mcf_gpio_free,
369 .direction_input = mcf_gpio_direction_input,
370 .direction_output = mcf_gpio_direction_output,
371 .get = mcf_gpio_get_value,
372 .set = mcf_gpio_set_value_fast,
373 .base = 48,
374 .ngpio = 6,
375 },
376 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
377 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
378 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
379 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
380 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
381 },
382 {
383 .gpio_chip = {
384 .label = "QSPI",
385 .request = mcf_gpio_request,
386 .free = mcf_gpio_free,
387 .direction_input = mcf_gpio_direction_input,
388 .direction_output = mcf_gpio_direction_output,
389 .get = mcf_gpio_get_value,
390 .set = mcf_gpio_set_value_fast,
391 .base = 56,
392 .ngpio = 7,
393 },
394 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
395 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
396 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
397 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
398 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
399 },
400 {
401 .gpio_chip = {
402 .label = "SDRAM",
403 .request = mcf_gpio_request,
404 .free = mcf_gpio_free,
405 .direction_input = mcf_gpio_direction_input,
406 .direction_output = mcf_gpio_direction_output,
407 .get = mcf_gpio_get_value,
408 .set = mcf_gpio_set_value_fast,
409 .base = 64,
410 .ngpio = 8,
411 },
412 .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
413 .podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
414 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
415 .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
416 .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
417 },
418 {
419 .gpio_chip = {
420 .label = "TIMERH",
421 .request = mcf_gpio_request,
422 .free = mcf_gpio_free,
423 .direction_input = mcf_gpio_direction_input,
424 .direction_output = mcf_gpio_direction_output,
425 .get = mcf_gpio_get_value,
426 .set = mcf_gpio_set_value_fast,
427 .base = 72,
428 .ngpio = 4,
429 },
430 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH,
431 .podr = (void __iomem *) MCFGPIO_PODR_TIMERH,
432 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
433 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
434 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
435 },
436 {
437 .gpio_chip = {
438 .label = "TIMERL",
439 .request = mcf_gpio_request,
440 .free = mcf_gpio_free,
441 .direction_input = mcf_gpio_direction_input,
442 .direction_output = mcf_gpio_direction_output,
443 .get = mcf_gpio_get_value,
444 .set = mcf_gpio_set_value_fast,
445 .base = 80,
446 .ngpio = 4,
447 },
448 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL,
449 .podr = (void __iomem *) MCFGPIO_PODR_TIMERL,
450 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
451 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
452 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
453 },
454 {
455 .gpio_chip = {
456 .label = "UARTL",
457 .request = mcf_gpio_request,
458 .free = mcf_gpio_free,
459 .direction_input = mcf_gpio_direction_input,
460 .direction_output = mcf_gpio_direction_output,
461 .get = mcf_gpio_get_value,
462 .set = mcf_gpio_set_value_fast,
463 .base = 88,
464 .ngpio = 8,
465 },
466 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
467 .podr = (void __iomem *) MCFGPIO_PODR_UARTL,
468 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
469 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
470 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
471 },
472 {
473 .gpio_chip = {
474 .label = "FEC1H",
475 .request = mcf_gpio_request,
476 .free = mcf_gpio_free,
477 .direction_input = mcf_gpio_direction_input,
478 .direction_output = mcf_gpio_direction_output,
479 .get = mcf_gpio_get_value,
480 .set = mcf_gpio_set_value_fast,
481 .base = 96,
482 .ngpio = 8,
483 },
484 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H,
485 .podr = (void __iomem *) MCFGPIO_PODR_FEC1H,
486 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
487 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
488 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
489 },
490 {
491 .gpio_chip = {
492 .label = "FEC1L",
493 .request = mcf_gpio_request,
494 .free = mcf_gpio_free,
495 .direction_input = mcf_gpio_direction_input,
496 .direction_output = mcf_gpio_direction_output,
497 .get = mcf_gpio_get_value,
498 .set = mcf_gpio_set_value_fast,
499 .base = 104,
500 .ngpio = 8,
501 },
502 .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L,
503 .podr = (void __iomem *) MCFGPIO_PODR_FEC1L,
504 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
505 .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
506 .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
507 },
508 {
509 .gpio_chip = {
510 .label = "BS",
511 .request = mcf_gpio_request,
512 .free = mcf_gpio_free,
513 .direction_input = mcf_gpio_direction_input,
514 .direction_output = mcf_gpio_direction_output,
515 .get = mcf_gpio_get_value,
516 .set = mcf_gpio_set_value_fast,
517 .base = 114,
518 .ngpio = 2,
519 },
520 .pddr = (void __iomem *) MCFGPIO_PDDR_BS,
521 .podr = (void __iomem *) MCFGPIO_PODR_BS,
522 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
523 .setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
524 .clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
525 },
526 {
527 .gpio_chip = {
528 .label = "IRQ",
529 .request = mcf_gpio_request,
530 .free = mcf_gpio_free,
531 .direction_input = mcf_gpio_direction_input,
532 .direction_output = mcf_gpio_direction_output,
533 .get = mcf_gpio_get_value,
534 .set = mcf_gpio_set_value_fast,
535 .base = 121,
536 .ngpio = 7,
537 },
538 .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ,
539 .podr = (void __iomem *) MCFGPIO_PODR_IRQ,
540 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
541 .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
542 .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ,
543 },
544 {
545 .gpio_chip = {
546 .label = "USBH",
547 .request = mcf_gpio_request,
548 .free = mcf_gpio_free,
549 .direction_input = mcf_gpio_direction_input,
550 .direction_output = mcf_gpio_direction_output,
551 .get = mcf_gpio_get_value,
552 .set = mcf_gpio_set_value_fast,
553 .base = 128,
554 .ngpio = 1,
555 },
556 .pddr = (void __iomem *) MCFGPIO_PDDR_USBH,
557 .podr = (void __iomem *) MCFGPIO_PODR_USBH,
558 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
559 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
560 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH,
561 },
562 {
563 .gpio_chip = {
564 .label = "USBL",
565 .request = mcf_gpio_request,
566 .free = mcf_gpio_free,
567 .direction_input = mcf_gpio_direction_input,
568 .direction_output = mcf_gpio_direction_output,
569 .get = mcf_gpio_get_value,
570 .set = mcf_gpio_set_value_fast,
571 .base = 136,
572 .ngpio = 8,
573 },
574 .pddr = (void __iomem *) MCFGPIO_PDDR_USBL,
575 .podr = (void __iomem *) MCFGPIO_PODR_USBL,
576 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
577 .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
578 .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL,
579 },
580 {
581 .gpio_chip = {
582 .label = "UARTH",
583 .request = mcf_gpio_request,
584 .free = mcf_gpio_free,
585 .direction_input = mcf_gpio_direction_input,
586 .direction_output = mcf_gpio_direction_output,
587 .get = mcf_gpio_get_value,
588 .set = mcf_gpio_set_value_fast,
589 .base = 144,
590 .ngpio = 4,
591 },
592 .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
593 .podr = (void __iomem *) MCFGPIO_PODR_UARTH,
594 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
595 .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
596 .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
597 },
598#endif
599};
600
601static int __init mcf_gpio_init(void)
602{
603 unsigned i = 0;
604 while (i < ARRAY_SIZE(mcf_gpio_chips))
605 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
606 return 0;
607}
608
609core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/528x/Makefile b/arch/m68k/platform/528x/Makefile
new file mode 100644
index 00000000000..6ac4b57370e
--- /dev/null
+++ b/arch/m68k/platform/528x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c
new file mode 100644
index 00000000000..7abe77a2f3e
--- /dev/null
+++ b/arch/m68k/platform/528x/config.c
@@ -0,0 +1,320 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/528x/config.c
5 *
6 * Sub-architcture dependent initialization code for the Freescale
7 * 5280, 5281 and 5282 CPUs.
8 *
9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/param.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <linux/spi/spi.h>
21#include <linux/gpio.h>
22#include <asm/machdep.h>
23#include <asm/coldfire.h>
24#include <asm/mcfsim.h>
25#include <asm/mcfuart.h>
26#include <asm/mcfqspi.h>
27
28/***************************************************************************/
29
30static struct mcf_platform_uart m528x_uart_platform[] = {
31 {
32 .mapbase = MCFUART_BASE1,
33 .irq = MCFINT_VECBASE + MCFINT_UART0,
34 },
35 {
36 .mapbase = MCFUART_BASE2,
37 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
38 },
39 {
40 .mapbase = MCFUART_BASE3,
41 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
42 },
43 { },
44};
45
46static struct platform_device m528x_uart = {
47 .name = "mcfuart",
48 .id = 0,
49 .dev.platform_data = m528x_uart_platform,
50};
51
52static struct resource m528x_fec_resources[] = {
53 {
54 .start = MCFFEC_BASE,
55 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
56 .flags = IORESOURCE_MEM,
57 },
58 {
59 .start = 64 + 23,
60 .end = 64 + 23,
61 .flags = IORESOURCE_IRQ,
62 },
63 {
64 .start = 64 + 27,
65 .end = 64 + 27,
66 .flags = IORESOURCE_IRQ,
67 },
68 {
69 .start = 64 + 29,
70 .end = 64 + 29,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75static struct platform_device m528x_fec = {
76 .name = "fec",
77 .id = 0,
78 .num_resources = ARRAY_SIZE(m528x_fec_resources),
79 .resource = m528x_fec_resources,
80};
81
82#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
83static struct resource m528x_qspi_resources[] = {
84 {
85 .start = MCFQSPI_IOBASE,
86 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = MCFINT_VECBASE + MCFINT_QSPI,
91 .end = MCFINT_VECBASE + MCFINT_QSPI,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96#define MCFQSPI_CS0 147
97#define MCFQSPI_CS1 148
98#define MCFQSPI_CS2 149
99#define MCFQSPI_CS3 150
100
101static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
102{
103 int status;
104
105 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
106 if (status) {
107 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
108 goto fail0;
109 }
110 status = gpio_direction_output(MCFQSPI_CS0, 1);
111 if (status) {
112 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
113 goto fail1;
114 }
115
116 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
117 if (status) {
118 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
119 goto fail1;
120 }
121 status = gpio_direction_output(MCFQSPI_CS1, 1);
122 if (status) {
123 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
124 goto fail2;
125 }
126
127 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
128 if (status) {
129 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
130 goto fail2;
131 }
132 status = gpio_direction_output(MCFQSPI_CS2, 1);
133 if (status) {
134 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
135 goto fail3;
136 }
137
138 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
139 if (status) {
140 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
141 goto fail3;
142 }
143 status = gpio_direction_output(MCFQSPI_CS3, 1);
144 if (status) {
145 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
146 goto fail4;
147 }
148
149 return 0;
150
151fail4:
152 gpio_free(MCFQSPI_CS3);
153fail3:
154 gpio_free(MCFQSPI_CS2);
155fail2:
156 gpio_free(MCFQSPI_CS1);
157fail1:
158 gpio_free(MCFQSPI_CS0);
159fail0:
160 return status;
161}
162
163static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
164{
165 gpio_free(MCFQSPI_CS3);
166 gpio_free(MCFQSPI_CS2);
167 gpio_free(MCFQSPI_CS1);
168 gpio_free(MCFQSPI_CS0);
169}
170
171static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
172 u8 chip_select, bool cs_high)
173{
174 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
175}
176
177static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
178 u8 chip_select, bool cs_high)
179{
180 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
181}
182
183static struct mcfqspi_cs_control m528x_cs_control = {
184 .setup = m528x_cs_setup,
185 .teardown = m528x_cs_teardown,
186 .select = m528x_cs_select,
187 .deselect = m528x_cs_deselect,
188};
189
190static struct mcfqspi_platform_data m528x_qspi_data = {
191 .bus_num = 0,
192 .num_chipselect = 4,
193 .cs_control = &m528x_cs_control,
194};
195
196static struct platform_device m528x_qspi = {
197 .name = "mcfqspi",
198 .id = 0,
199 .num_resources = ARRAY_SIZE(m528x_qspi_resources),
200 .resource = m528x_qspi_resources,
201 .dev.platform_data = &m528x_qspi_data,
202};
203
204static void __init m528x_qspi_init(void)
205{
206 /* setup Port QS for QSPI with gpio CS control */
207 __raw_writeb(0x07, MCFGPIO_PQSPAR);
208}
209#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
210
211static struct platform_device *m528x_devices[] __initdata = {
212 &m528x_uart,
213 &m528x_fec,
214#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
215 &m528x_qspi,
216#endif
217};
218
219/***************************************************************************/
220
221static void __init m528x_uart_init_line(int line, int irq)
222{
223 u8 port;
224
225 if ((line < 0) || (line > 2))
226 return;
227
228 /* make sure PUAPAR is set for UART0 and UART1 */
229 if (line < 2) {
230 port = readb(MCF5282_GPIO_PUAPAR);
231 port |= (0x03 << (line * 2));
232 writeb(port, MCF5282_GPIO_PUAPAR);
233 }
234}
235
236static void __init m528x_uarts_init(void)
237{
238 const int nrlines = ARRAY_SIZE(m528x_uart_platform);
239 int line;
240
241 for (line = 0; (line < nrlines); line++)
242 m528x_uart_init_line(line, m528x_uart_platform[line].irq);
243}
244
245/***************************************************************************/
246
247static void __init m528x_fec_init(void)
248{
249 u16 v16;
250
251 /* Set multi-function pins to ethernet mode for fec0 */
252 v16 = readw(MCF_IPSBAR + 0x100056);
253 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
254 writeb(0xc0, MCF_IPSBAR + 0x100058);
255}
256
257/***************************************************************************/
258
259static void m528x_cpu_reset(void)
260{
261 local_irq_disable();
262 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
263}
264
265/***************************************************************************/
266
267#ifdef CONFIG_WILDFIRE
268void wildfire_halt(void)
269{
270 writeb(0, 0x30000007);
271 writeb(0x2, 0x30000007);
272}
273#endif
274
275#ifdef CONFIG_WILDFIREMOD
276void wildfiremod_halt(void)
277{
278 printk(KERN_INFO "WildFireMod hibernating...\n");
279
280 /* Set portE.5 to Digital IO */
281 MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
282
283 /* Make portE.5 an output */
284 MCF5282_GPIO_DDRE |= (1 << 5);
285
286 /* Now toggle portE.5 from low to high */
287 MCF5282_GPIO_PORTE &= ~(1 << 5);
288 MCF5282_GPIO_PORTE |= (1 << 5);
289
290 printk(KERN_EMERG "Failed to hibernate. Halting!\n");
291}
292#endif
293
294void __init config_BSP(char *commandp, int size)
295{
296#ifdef CONFIG_WILDFIRE
297 mach_halt = wildfire_halt;
298#endif
299#ifdef CONFIG_WILDFIREMOD
300 mach_halt = wildfiremod_halt;
301#endif
302}
303
304/***************************************************************************/
305
306static int __init init_BSP(void)
307{
308 mach_reset = m528x_cpu_reset;
309 m528x_uarts_init();
310 m528x_fec_init();
311#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
312 m528x_qspi_init();
313#endif
314 platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
315 return 0;
316}
317
318arch_initcall(init_BSP);
319
320/***************************************************************************/
diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c
new file mode 100644
index 00000000000..526db665d87
--- /dev/null
+++ b/arch/m68k/platform/528x/gpio.c
@@ -0,0 +1,438 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "NQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .base = 1,
34 .ngpio = 7,
35 },
36 .pddr = (void __iomem *)MCFEPORT_EPDDR,
37 .podr = (void __iomem *)MCFEPORT_EPDR,
38 .ppdr = (void __iomem *)MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "TA",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 8,
50 .ngpio = 4,
51 },
52 .pddr = (void __iomem *)MCFGPTA_GPTDDR,
53 .podr = (void __iomem *)MCFGPTA_GPTPORT,
54 .ppdr = (void __iomem *)MCFGPTB_GPTPORT,
55 },
56 {
57 .gpio_chip = {
58 .label = "TB",
59 .request = mcf_gpio_request,
60 .free = mcf_gpio_free,
61 .direction_input = mcf_gpio_direction_input,
62 .direction_output = mcf_gpio_direction_output,
63 .get = mcf_gpio_get_value,
64 .set = mcf_gpio_set_value_fast,
65 .base = 16,
66 .ngpio = 4,
67 },
68 .pddr = (void __iomem *)MCFGPTB_GPTDDR,
69 .podr = (void __iomem *)MCFGPTB_GPTPORT,
70 .ppdr = (void __iomem *)MCFGPTB_GPTPORT,
71 },
72 {
73 .gpio_chip = {
74 .label = "QA",
75 .request = mcf_gpio_request,
76 .free = mcf_gpio_free,
77 .direction_input = mcf_gpio_direction_input,
78 .direction_output = mcf_gpio_direction_output,
79 .get = mcf_gpio_get_value,
80 .set = mcf_gpio_set_value_fast,
81 .base = 24,
82 .ngpio = 4,
83 },
84 .pddr = (void __iomem *)MCFQADC_DDRQA,
85 .podr = (void __iomem *)MCFQADC_PORTQA,
86 .ppdr = (void __iomem *)MCFQADC_PORTQA,
87 },
88 {
89 .gpio_chip = {
90 .label = "QB",
91 .request = mcf_gpio_request,
92 .free = mcf_gpio_free,
93 .direction_input = mcf_gpio_direction_input,
94 .direction_output = mcf_gpio_direction_output,
95 .get = mcf_gpio_get_value,
96 .set = mcf_gpio_set_value_fast,
97 .base = 32,
98 .ngpio = 4,
99 },
100 .pddr = (void __iomem *)MCFQADC_DDRQB,
101 .podr = (void __iomem *)MCFQADC_PORTQB,
102 .ppdr = (void __iomem *)MCFQADC_PORTQB,
103 },
104 {
105 .gpio_chip = {
106 .label = "A",
107 .request = mcf_gpio_request,
108 .free = mcf_gpio_free,
109 .direction_input = mcf_gpio_direction_input,
110 .direction_output = mcf_gpio_direction_output,
111 .get = mcf_gpio_get_value,
112 .set = mcf_gpio_set_value_fast,
113 .base = 40,
114 .ngpio = 8,
115 },
116 .pddr = (void __iomem *)MCFGPIO_DDRA,
117 .podr = (void __iomem *)MCFGPIO_PORTA,
118 .ppdr = (void __iomem *)MCFGPIO_PORTAP,
119 .setr = (void __iomem *)MCFGPIO_SETA,
120 .clrr = (void __iomem *)MCFGPIO_CLRA,
121 },
122 {
123 .gpio_chip = {
124 .label = "B",
125 .request = mcf_gpio_request,
126 .free = mcf_gpio_free,
127 .direction_input = mcf_gpio_direction_input,
128 .direction_output = mcf_gpio_direction_output,
129 .get = mcf_gpio_get_value,
130 .set = mcf_gpio_set_value_fast,
131 .base = 48,
132 .ngpio = 8,
133 },
134 .pddr = (void __iomem *)MCFGPIO_DDRB,
135 .podr = (void __iomem *)MCFGPIO_PORTB,
136 .ppdr = (void __iomem *)MCFGPIO_PORTBP,
137 .setr = (void __iomem *)MCFGPIO_SETB,
138 .clrr = (void __iomem *)MCFGPIO_CLRB,
139 },
140 {
141 .gpio_chip = {
142 .label = "C",
143 .request = mcf_gpio_request,
144 .free = mcf_gpio_free,
145 .direction_input = mcf_gpio_direction_input,
146 .direction_output = mcf_gpio_direction_output,
147 .get = mcf_gpio_get_value,
148 .set = mcf_gpio_set_value_fast,
149 .base = 56,
150 .ngpio = 8,
151 },
152 .pddr = (void __iomem *)MCFGPIO_DDRC,
153 .podr = (void __iomem *)MCFGPIO_PORTC,
154 .ppdr = (void __iomem *)MCFGPIO_PORTCP,
155 .setr = (void __iomem *)MCFGPIO_SETC,
156 .clrr = (void __iomem *)MCFGPIO_CLRC,
157 },
158 {
159 .gpio_chip = {
160 .label = "D",
161 .request = mcf_gpio_request,
162 .free = mcf_gpio_free,
163 .direction_input = mcf_gpio_direction_input,
164 .direction_output = mcf_gpio_direction_output,
165 .get = mcf_gpio_get_value,
166 .set = mcf_gpio_set_value_fast,
167 .base = 64,
168 .ngpio = 8,
169 },
170 .pddr = (void __iomem *)MCFGPIO_DDRD,
171 .podr = (void __iomem *)MCFGPIO_PORTD,
172 .ppdr = (void __iomem *)MCFGPIO_PORTDP,
173 .setr = (void __iomem *)MCFGPIO_SETD,
174 .clrr = (void __iomem *)MCFGPIO_CLRD,
175 },
176 {
177 .gpio_chip = {
178 .label = "E",
179 .request = mcf_gpio_request,
180 .free = mcf_gpio_free,
181 .direction_input = mcf_gpio_direction_input,
182 .direction_output = mcf_gpio_direction_output,
183 .get = mcf_gpio_get_value,
184 .set = mcf_gpio_set_value_fast,
185 .base = 72,
186 .ngpio = 8,
187 },
188 .pddr = (void __iomem *)MCFGPIO_DDRE,
189 .podr = (void __iomem *)MCFGPIO_PORTE,
190 .ppdr = (void __iomem *)MCFGPIO_PORTEP,
191 .setr = (void __iomem *)MCFGPIO_SETE,
192 .clrr = (void __iomem *)MCFGPIO_CLRE,
193 },
194 {
195 .gpio_chip = {
196 .label = "F",
197 .request = mcf_gpio_request,
198 .free = mcf_gpio_free,
199 .direction_input = mcf_gpio_direction_input,
200 .direction_output = mcf_gpio_direction_output,
201 .get = mcf_gpio_get_value,
202 .set = mcf_gpio_set_value_fast,
203 .base = 80,
204 .ngpio = 8,
205 },
206 .pddr = (void __iomem *)MCFGPIO_DDRF,
207 .podr = (void __iomem *)MCFGPIO_PORTF,
208 .ppdr = (void __iomem *)MCFGPIO_PORTFP,
209 .setr = (void __iomem *)MCFGPIO_SETF,
210 .clrr = (void __iomem *)MCFGPIO_CLRF,
211 },
212 {
213 .gpio_chip = {
214 .label = "G",
215 .request = mcf_gpio_request,
216 .free = mcf_gpio_free,
217 .direction_input = mcf_gpio_direction_input,
218 .direction_output = mcf_gpio_direction_output,
219 .get = mcf_gpio_get_value,
220 .set = mcf_gpio_set_value_fast,
221 .base = 88,
222 .ngpio = 8,
223 },
224 .pddr = (void __iomem *)MCFGPIO_DDRG,
225 .podr = (void __iomem *)MCFGPIO_PORTG,
226 .ppdr = (void __iomem *)MCFGPIO_PORTGP,
227 .setr = (void __iomem *)MCFGPIO_SETG,
228 .clrr = (void __iomem *)MCFGPIO_CLRG,
229 },
230 {
231 .gpio_chip = {
232 .label = "H",
233 .request = mcf_gpio_request,
234 .free = mcf_gpio_free,
235 .direction_input = mcf_gpio_direction_input,
236 .direction_output = mcf_gpio_direction_output,
237 .get = mcf_gpio_get_value,
238 .set = mcf_gpio_set_value_fast,
239 .base = 96,
240 .ngpio = 8,
241 },
242 .pddr = (void __iomem *)MCFGPIO_DDRH,
243 .podr = (void __iomem *)MCFGPIO_PORTH,
244 .ppdr = (void __iomem *)MCFGPIO_PORTHP,
245 .setr = (void __iomem *)MCFGPIO_SETH,
246 .clrr = (void __iomem *)MCFGPIO_CLRH,
247 },
248 {
249 .gpio_chip = {
250 .label = "J",
251 .request = mcf_gpio_request,
252 .free = mcf_gpio_free,
253 .direction_input = mcf_gpio_direction_input,
254 .direction_output = mcf_gpio_direction_output,
255 .get = mcf_gpio_get_value,
256 .set = mcf_gpio_set_value_fast,
257 .base = 104,
258 .ngpio = 8,
259 },
260 .pddr = (void __iomem *)MCFGPIO_DDRJ,
261 .podr = (void __iomem *)MCFGPIO_PORTJ,
262 .ppdr = (void __iomem *)MCFGPIO_PORTJP,
263 .setr = (void __iomem *)MCFGPIO_SETJ,
264 .clrr = (void __iomem *)MCFGPIO_CLRJ,
265 },
266 {
267 .gpio_chip = {
268 .label = "DD",
269 .request = mcf_gpio_request,
270 .free = mcf_gpio_free,
271 .direction_input = mcf_gpio_direction_input,
272 .direction_output = mcf_gpio_direction_output,
273 .get = mcf_gpio_get_value,
274 .set = mcf_gpio_set_value_fast,
275 .base = 112,
276 .ngpio = 8,
277 },
278 .pddr = (void __iomem *)MCFGPIO_DDRDD,
279 .podr = (void __iomem *)MCFGPIO_PORTDD,
280 .ppdr = (void __iomem *)MCFGPIO_PORTDDP,
281 .setr = (void __iomem *)MCFGPIO_SETDD,
282 .clrr = (void __iomem *)MCFGPIO_CLRDD,
283 },
284 {
285 .gpio_chip = {
286 .label = "EH",
287 .request = mcf_gpio_request,
288 .free = mcf_gpio_free,
289 .direction_input = mcf_gpio_direction_input,
290 .direction_output = mcf_gpio_direction_output,
291 .get = mcf_gpio_get_value,
292 .set = mcf_gpio_set_value_fast,
293 .base = 120,
294 .ngpio = 8,
295 },
296 .pddr = (void __iomem *)MCFGPIO_DDREH,
297 .podr = (void __iomem *)MCFGPIO_PORTEH,
298 .ppdr = (void __iomem *)MCFGPIO_PORTEHP,
299 .setr = (void __iomem *)MCFGPIO_SETEH,
300 .clrr = (void __iomem *)MCFGPIO_CLREH,
301 },
302 {
303 .gpio_chip = {
304 .label = "EL",
305 .request = mcf_gpio_request,
306 .free = mcf_gpio_free,
307 .direction_input = mcf_gpio_direction_input,
308 .direction_output = mcf_gpio_direction_output,
309 .get = mcf_gpio_get_value,
310 .set = mcf_gpio_set_value_fast,
311 .base = 128,
312 .ngpio = 8,
313 },
314 .pddr = (void __iomem *)MCFGPIO_DDREL,
315 .podr = (void __iomem *)MCFGPIO_PORTEL,
316 .ppdr = (void __iomem *)MCFGPIO_PORTELP,
317 .setr = (void __iomem *)MCFGPIO_SETEL,
318 .clrr = (void __iomem *)MCFGPIO_CLREL,
319 },
320 {
321 .gpio_chip = {
322 .label = "AS",
323 .request = mcf_gpio_request,
324 .free = mcf_gpio_free,
325 .direction_input = mcf_gpio_direction_input,
326 .direction_output = mcf_gpio_direction_output,
327 .get = mcf_gpio_get_value,
328 .set = mcf_gpio_set_value_fast,
329 .base = 136,
330 .ngpio = 6,
331 },
332 .pddr = (void __iomem *)MCFGPIO_DDRAS,
333 .podr = (void __iomem *)MCFGPIO_PORTAS,
334 .ppdr = (void __iomem *)MCFGPIO_PORTASP,
335 .setr = (void __iomem *)MCFGPIO_SETAS,
336 .clrr = (void __iomem *)MCFGPIO_CLRAS,
337 },
338 {
339 .gpio_chip = {
340 .label = "QS",
341 .request = mcf_gpio_request,
342 .free = mcf_gpio_free,
343 .direction_input = mcf_gpio_direction_input,
344 .direction_output = mcf_gpio_direction_output,
345 .get = mcf_gpio_get_value,
346 .set = mcf_gpio_set_value_fast,
347 .base = 144,
348 .ngpio = 7,
349 },
350 .pddr = (void __iomem *)MCFGPIO_DDRQS,
351 .podr = (void __iomem *)MCFGPIO_PORTQS,
352 .ppdr = (void __iomem *)MCFGPIO_PORTQSP,
353 .setr = (void __iomem *)MCFGPIO_SETQS,
354 .clrr = (void __iomem *)MCFGPIO_CLRQS,
355 },
356 {
357 .gpio_chip = {
358 .label = "SD",
359 .request = mcf_gpio_request,
360 .free = mcf_gpio_free,
361 .direction_input = mcf_gpio_direction_input,
362 .direction_output = mcf_gpio_direction_output,
363 .get = mcf_gpio_get_value,
364 .set = mcf_gpio_set_value_fast,
365 .base = 152,
366 .ngpio = 6,
367 },
368 .pddr = (void __iomem *)MCFGPIO_DDRSD,
369 .podr = (void __iomem *)MCFGPIO_PORTSD,
370 .ppdr = (void __iomem *)MCFGPIO_PORTSDP,
371 .setr = (void __iomem *)MCFGPIO_SETSD,
372 .clrr = (void __iomem *)MCFGPIO_CLRSD,
373 },
374 {
375 .gpio_chip = {
376 .label = "TC",
377 .request = mcf_gpio_request,
378 .free = mcf_gpio_free,
379 .direction_input = mcf_gpio_direction_input,
380 .direction_output = mcf_gpio_direction_output,
381 .get = mcf_gpio_get_value,
382 .set = mcf_gpio_set_value_fast,
383 .base = 160,
384 .ngpio = 4,
385 },
386 .pddr = (void __iomem *)MCFGPIO_DDRTC,
387 .podr = (void __iomem *)MCFGPIO_PORTTC,
388 .ppdr = (void __iomem *)MCFGPIO_PORTTCP,
389 .setr = (void __iomem *)MCFGPIO_SETTC,
390 .clrr = (void __iomem *)MCFGPIO_CLRTC,
391 },
392 {
393 .gpio_chip = {
394 .label = "TD",
395 .request = mcf_gpio_request,
396 .free = mcf_gpio_free,
397 .direction_input = mcf_gpio_direction_input,
398 .direction_output = mcf_gpio_direction_output,
399 .get = mcf_gpio_get_value,
400 .set = mcf_gpio_set_value_fast,
401 .base = 168,
402 .ngpio = 4,
403 },
404 .pddr = (void __iomem *)MCFGPIO_DDRTD,
405 .podr = (void __iomem *)MCFGPIO_PORTTD,
406 .ppdr = (void __iomem *)MCFGPIO_PORTTDP,
407 .setr = (void __iomem *)MCFGPIO_SETTD,
408 .clrr = (void __iomem *)MCFGPIO_CLRTD,
409 },
410 {
411 .gpio_chip = {
412 .label = "UA",
413 .request = mcf_gpio_request,
414 .free = mcf_gpio_free,
415 .direction_input = mcf_gpio_direction_input,
416 .direction_output = mcf_gpio_direction_output,
417 .get = mcf_gpio_get_value,
418 .set = mcf_gpio_set_value_fast,
419 .base = 176,
420 .ngpio = 4,
421 },
422 .pddr = (void __iomem *)MCFGPIO_DDRUA,
423 .podr = (void __iomem *)MCFGPIO_PORTUA,
424 .ppdr = (void __iomem *)MCFGPIO_PORTUAP,
425 .setr = (void __iomem *)MCFGPIO_SETUA,
426 .clrr = (void __iomem *)MCFGPIO_CLRUA,
427 },
428};
429
430static int __init mcf_gpio_init(void)
431{
432 unsigned i = 0;
433 while (i < ARRAY_SIZE(mcf_gpio_chips))
434 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
435 return 0;
436}
437
438core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile
new file mode 100644
index 00000000000..d4293b791f2
--- /dev/null
+++ b/arch/m68k/platform/5307/Makefile
@@ -0,0 +1,20 @@
1#
2# Makefile for the m68knommu kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y += config.o gpio.o
18obj-$(CONFIG_NETtel) += nettel.o
19obj-$(CONFIG_CLEOPATRA) += nettel.o
20
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/5307/config.c
new file mode 100644
index 00000000000..00900ac06a9
--- /dev/null
+++ b/arch/m68k/platform/5307/config.c
@@ -0,0 +1,147 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5307/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20#include <asm/mcfwdebug.h>
21
22/***************************************************************************/
23
24/*
25 * Some platforms need software versions of the GPIO data registers.
26 */
27unsigned short ppdata;
28unsigned char ledbank = 0xff;
29
30/***************************************************************************/
31
32static struct mcf_platform_uart m5307_uart_platform[] = {
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE1,
35 .irq = 73,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE2,
39 .irq = 74,
40 },
41 { },
42};
43
44static struct platform_device m5307_uart = {
45 .name = "mcfuart",
46 .id = 0,
47 .dev.platform_data = m5307_uart_platform,
48};
49
50static struct platform_device *m5307_devices[] __initdata = {
51 &m5307_uart,
52};
53
54/***************************************************************************/
55
56static void __init m5307_uart_init_line(int line, int irq)
57{
58 if (line == 0) {
59 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
60 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
61 mcf_mapirq2imr(irq, MCFINTC_UART0);
62 } else if (line == 1) {
63 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
64 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
65 mcf_mapirq2imr(irq, MCFINTC_UART1);
66 }
67}
68
69static void __init m5307_uarts_init(void)
70{
71 const int nrlines = ARRAY_SIZE(m5307_uart_platform);
72 int line;
73
74 for (line = 0; (line < nrlines); line++)
75 m5307_uart_init_line(line, m5307_uart_platform[line].irq);
76}
77
78/***************************************************************************/
79
80static void __init m5307_timers_init(void)
81{
82 /* Timer1 is always used as system timer */
83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
84 MCF_MBAR + MCFSIM_TIMER1ICR);
85 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
86
87#ifdef CONFIG_HIGHPROFILE
88 /* Timer2 is to be used as a high speed profile timer */
89 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
90 MCF_MBAR + MCFSIM_TIMER2ICR);
91 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
92#endif
93}
94
95/***************************************************************************/
96
97void m5307_cpu_reset(void)
98{
99 local_irq_disable();
100 /* Set watchdog to soft reset, and enabled */
101 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
102 for (;;)
103 /* wait for watchdog to timeout */;
104}
105
106/***************************************************************************/
107
108void __init config_BSP(char *commandp, int size)
109{
110#if defined(CONFIG_NETtel) || \
111 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
112 /* Copy command line from FLASH to local buffer... */
113 memcpy(commandp, (char *) 0xf0004000, size);
114 commandp[size-1] = 0;
115#endif
116
117 mach_reset = m5307_cpu_reset;
118 m5307_timers_init();
119 m5307_uarts_init();
120
121 /* Only support the external interrupts on their primary level */
122 mcf_mapirq2imr(25, MCFINTC_EINT1);
123 mcf_mapirq2imr(27, MCFINTC_EINT3);
124 mcf_mapirq2imr(29, MCFINTC_EINT5);
125 mcf_mapirq2imr(31, MCFINTC_EINT7);
126
127#ifdef CONFIG_BDM_DISABLE
128 /*
129 * Disable the BDM clocking. This also turns off most of the rest of
130 * the BDM device. This is good for EMC reasons. This option is not
131 * incompatible with the memory protection option.
132 */
133 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
134#endif
135}
136
137/***************************************************************************/
138
139static int __init init_BSP(void)
140{
141 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
142 return 0;
143}
144
145arch_initcall(init_BSP);
146
147/***************************************************************************/
diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c
new file mode 100644
index 00000000000..5850612b4a3
--- /dev/null
+++ b/arch/m68k/platform/5307/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/nettel.c b/arch/m68k/platform/5307/nettel.c
new file mode 100644
index 00000000000..e925ea4602f
--- /dev/null
+++ b/arch/m68k/platform/5307/nettel.c
@@ -0,0 +1,153 @@
1/***************************************************************************/
2
3/*
4 * nettel.c -- startup code support for the NETtel boards
5 *
6 * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/coldfire.h>
17#include <asm/mcfsim.h>
18#include <asm/nettel.h>
19
20/***************************************************************************/
21
22/*
23 * Define the IO and interrupt resources of the 2 SMC9196 interfaces.
24 */
25#define NETTEL_SMC0_ADDR 0x30600300
26#define NETTEL_SMC0_IRQ 29
27
28#define NETTEL_SMC1_ADDR 0x30600000
29#define NETTEL_SMC1_IRQ 27
30
31/*
32 * We need some access into the SMC9196 registers. Define those registers
33 * we will need here (including the smc91x.h doesn't seem to give us these
34 * in a simple form).
35 */
36#define SMC91xx_BANKSELECT 14
37#define SMC91xx_BASEADDR 2
38#define SMC91xx_BASEMAC 4
39
40/***************************************************************************/
41
42static struct resource nettel_smc91x_0_resources[] = {
43 {
44 .start = NETTEL_SMC0_ADDR,
45 .end = NETTEL_SMC0_ADDR + 0x20,
46 .flags = IORESOURCE_MEM,
47 },
48 {
49 .start = NETTEL_SMC0_IRQ,
50 .end = NETTEL_SMC0_IRQ,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct resource nettel_smc91x_1_resources[] = {
56 {
57 .start = NETTEL_SMC1_ADDR,
58 .end = NETTEL_SMC1_ADDR + 0x20,
59 .flags = IORESOURCE_MEM,
60 },
61 {
62 .start = NETTEL_SMC1_IRQ,
63 .end = NETTEL_SMC1_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct platform_device nettel_smc91x[] = {
69 {
70 .name = "smc91x",
71 .id = 0,
72 .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources),
73 .resource = nettel_smc91x_0_resources,
74 },
75 {
76 .name = "smc91x",
77 .id = 1,
78 .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources),
79 .resource = nettel_smc91x_1_resources,
80 },
81};
82
83static struct platform_device *nettel_devices[] __initdata = {
84 &nettel_smc91x[0],
85 &nettel_smc91x[1],
86};
87
88/***************************************************************************/
89
90static u8 nettel_macdefault[] __initdata = {
91 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01,
92};
93
94/*
95 * Set flash contained MAC address into SMC9196 core. Make sure the flash
96 * MAC address is sane, and not an empty flash. If no good use the Moreton
97 * Bay default MAC address instead.
98 */
99
100static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr)
101{
102 u16 *macp;
103
104 macp = (u16 *) flashaddr;
105 if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
106 macp = (u16 *) &nettel_macdefault[0];
107
108 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
109 writew(macp[0], ioaddr + SMC91xx_BASEMAC);
110 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
111 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
112}
113
114/***************************************************************************/
115
116/*
117 * Re-map the address space of at least one of the SMC ethernet
118 * parts. Both parts power up decoding the same address, so we
119 * need to move one of them first, before doing anything else.
120 */
121
122static void __init nettel_smc91x_init(void)
123{
124 writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
125 mcf_setppdata(0, 0x0080);
126 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
127 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
128 mcf_setppdata(0x0080, 0);
129
130 /* Set correct chip select timing for SMC9196 accesses */
131 writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
132
133 /* Set the SMC interrupts to be auto-vectored */
134 mcf_autovector(NETTEL_SMC0_IRQ);
135 mcf_autovector(NETTEL_SMC1_IRQ);
136
137 /* Set MAC addresses from flash for both interfaces */
138 nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000);
139 nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006);
140}
141
142/***************************************************************************/
143
144static int __init init_nettel(void)
145{
146 nettel_smc91x_init();
147 platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices));
148 return 0;
149}
150
151arch_initcall(init_nettel);
152
153/***************************************************************************/
diff --git a/arch/m68k/platform/532x/Makefile b/arch/m68k/platform/532x/Makefile
new file mode 100644
index 00000000000..ce01669399c
--- /dev/null
+++ b/arch/m68k/platform/532x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
18obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/532x/config.c
new file mode 100644
index 00000000000..ca51323f957
--- /dev/null
+++ b/arch/m68k/platform/532x/config.c
@@ -0,0 +1,648 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/532x/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
9 * Copyright Freescale Semiconductor, Inc 2006
10 * Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/***************************************************************************/
19
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/spi/spi.h>
25#include <linux/gpio.h>
26#include <asm/machdep.h>
27#include <asm/coldfire.h>
28#include <asm/mcfsim.h>
29#include <asm/mcfuart.h>
30#include <asm/mcfdma.h>
31#include <asm/mcfwdebug.h>
32#include <asm/mcfqspi.h>
33
34/***************************************************************************/
35
36static struct mcf_platform_uart m532x_uart_platform[] = {
37 {
38 .mapbase = MCFUART_BASE1,
39 .irq = MCFINT_VECBASE + MCFINT_UART0,
40 },
41 {
42 .mapbase = MCFUART_BASE2,
43 .irq = MCFINT_VECBASE + MCFINT_UART1,
44 },
45 {
46 .mapbase = MCFUART_BASE3,
47 .irq = MCFINT_VECBASE + MCFINT_UART2,
48 },
49 { },
50};
51
52static struct platform_device m532x_uart = {
53 .name = "mcfuart",
54 .id = 0,
55 .dev.platform_data = m532x_uart_platform,
56};
57
58static struct resource m532x_fec_resources[] = {
59 {
60 .start = 0xfc030000,
61 .end = 0xfc0307ff,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = 64 + 36,
66 .end = 64 + 36,
67 .flags = IORESOURCE_IRQ,
68 },
69 {
70 .start = 64 + 40,
71 .end = 64 + 40,
72 .flags = IORESOURCE_IRQ,
73 },
74 {
75 .start = 64 + 42,
76 .end = 64 + 42,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct platform_device m532x_fec = {
82 .name = "fec",
83 .id = 0,
84 .num_resources = ARRAY_SIZE(m532x_fec_resources),
85 .resource = m532x_fec_resources,
86};
87
88#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
89static struct resource m532x_qspi_resources[] = {
90 {
91 .start = MCFQSPI_IOBASE,
92 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .start = MCFINT_VECBASE + MCFINT_QSPI,
97 .end = MCFINT_VECBASE + MCFINT_QSPI,
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102#define MCFQSPI_CS0 84
103#define MCFQSPI_CS1 85
104#define MCFQSPI_CS2 86
105
106static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
107{
108 int status;
109
110 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
111 if (status) {
112 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
113 goto fail0;
114 }
115 status = gpio_direction_output(MCFQSPI_CS0, 1);
116 if (status) {
117 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
118 goto fail1;
119 }
120
121 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
122 if (status) {
123 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
124 goto fail1;
125 }
126 status = gpio_direction_output(MCFQSPI_CS1, 1);
127 if (status) {
128 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
129 goto fail2;
130 }
131
132 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
133 if (status) {
134 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
135 goto fail2;
136 }
137 status = gpio_direction_output(MCFQSPI_CS2, 1);
138 if (status) {
139 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
140 goto fail3;
141 }
142
143 return 0;
144
145fail3:
146 gpio_free(MCFQSPI_CS2);
147fail2:
148 gpio_free(MCFQSPI_CS1);
149fail1:
150 gpio_free(MCFQSPI_CS0);
151fail0:
152 return status;
153}
154
155static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control)
156{
157 gpio_free(MCFQSPI_CS2);
158 gpio_free(MCFQSPI_CS1);
159 gpio_free(MCFQSPI_CS0);
160}
161
162static void m532x_cs_select(struct mcfqspi_cs_control *cs_control,
163 u8 chip_select, bool cs_high)
164{
165 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
166}
167
168static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control,
169 u8 chip_select, bool cs_high)
170{
171 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
172}
173
174static struct mcfqspi_cs_control m532x_cs_control = {
175 .setup = m532x_cs_setup,
176 .teardown = m532x_cs_teardown,
177 .select = m532x_cs_select,
178 .deselect = m532x_cs_deselect,
179};
180
181static struct mcfqspi_platform_data m532x_qspi_data = {
182 .bus_num = 0,
183 .num_chipselect = 3,
184 .cs_control = &m532x_cs_control,
185};
186
187static struct platform_device m532x_qspi = {
188 .name = "mcfqspi",
189 .id = 0,
190 .num_resources = ARRAY_SIZE(m532x_qspi_resources),
191 .resource = m532x_qspi_resources,
192 .dev.platform_data = &m532x_qspi_data,
193};
194
195static void __init m532x_qspi_init(void)
196{
197 /* setup QSPS pins for QSPI with gpio CS control */
198 writew(0x01f0, MCF_GPIO_PAR_QSPI);
199}
200#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
201
202
203static struct platform_device *m532x_devices[] __initdata = {
204 &m532x_uart,
205 &m532x_fec,
206#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
207 &m532x_qspi,
208#endif
209};
210
211/***************************************************************************/
212
213static void __init m532x_uart_init_line(int line, int irq)
214{
215 if (line == 0) {
216 /* GPIO initialization */
217 MCF_GPIO_PAR_UART |= 0x000F;
218 } else if (line == 1) {
219 /* GPIO initialization */
220 MCF_GPIO_PAR_UART |= 0x0FF0;
221 }
222}
223
224static void __init m532x_uarts_init(void)
225{
226 const int nrlines = ARRAY_SIZE(m532x_uart_platform);
227 int line;
228
229 for (line = 0; (line < nrlines); line++)
230 m532x_uart_init_line(line, m532x_uart_platform[line].irq);
231}
232/***************************************************************************/
233
234static void __init m532x_fec_init(void)
235{
236 /* Set multi-function pins to ethernet mode for fec0 */
237 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
238 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
239 MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
240 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
241}
242
243/***************************************************************************/
244
245static void m532x_cpu_reset(void)
246{
247 local_irq_disable();
248 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
249}
250
251/***************************************************************************/
252
253void __init config_BSP(char *commandp, int size)
254{
255#if !defined(CONFIG_BOOTPARAM)
256 /* Copy command line from FLASH to local buffer... */
257 memcpy(commandp, (char *) 0x4000, 4);
258 if(strncmp(commandp, "kcl ", 4) == 0){
259 memcpy(commandp, (char *) 0x4004, size);
260 commandp[size-1] = 0;
261 } else {
262 memset(commandp, 0, size);
263 }
264#endif
265
266#ifdef CONFIG_BDM_DISABLE
267 /*
268 * Disable the BDM clocking. This also turns off most of the rest of
269 * the BDM device. This is good for EMC reasons. This option is not
270 * incompatible with the memory protection option.
271 */
272 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
273#endif
274}
275
276/***************************************************************************/
277
278static int __init init_BSP(void)
279{
280 m532x_uarts_init();
281 m532x_fec_init();
282#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
283 m532x_qspi_init();
284#endif
285 platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
286 return 0;
287}
288
289arch_initcall(init_BSP);
290
291/***************************************************************************/
292/* Board initialization */
293/***************************************************************************/
294/*
295 * PLL min/max specifications
296 */
297#define MAX_FVCO 500000 /* KHz */
298#define MAX_FSYS 80000 /* KHz */
299#define MIN_FSYS 58333 /* KHz */
300#define FREF 16000 /* KHz */
301
302
303#define MAX_MFD 135 /* Multiplier */
304#define MIN_MFD 88 /* Multiplier */
305#define BUSDIV 6 /* Divider */
306
307/*
308 * Low Power Divider specifications
309 */
310#define MIN_LPD (1 << 0) /* Divider (not encoded) */
311#define MAX_LPD (1 << 15) /* Divider (not encoded) */
312#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
313
314#define SYS_CLK_KHZ 80000
315#define SYSTEM_PERIOD 12.5
316/*
317 * SDRAM Timing Parameters
318 */
319#define SDRAM_BL 8 /* # of beats in a burst */
320#define SDRAM_TWR 2 /* in clocks */
321#define SDRAM_CASL 2.5 /* CASL in clocks */
322#define SDRAM_TRCD 2 /* in clocks */
323#define SDRAM_TRP 2 /* in clocks */
324#define SDRAM_TRFC 7 /* in clocks */
325#define SDRAM_TREFI 7800 /* in ns */
326
327#define EXT_SRAM_ADDRESS (0xC0000000)
328#define FLASH_ADDRESS (0x00000000)
329#define SDRAM_ADDRESS (0x40000000)
330
331#define NAND_FLASH_ADDRESS (0xD0000000)
332
333int sys_clk_khz = 0;
334int sys_clk_mhz = 0;
335
336void wtm_init(void);
337void scm_init(void);
338void gpio_init(void);
339void fbcs_init(void);
340void sdramc_init(void);
341int clock_pll (int fsys, int flags);
342int clock_limp (int);
343int clock_exit_limp (void);
344int get_sys_clock (void);
345
346asmlinkage void __init sysinit(void)
347{
348 sys_clk_khz = clock_pll(0, 0);
349 sys_clk_mhz = sys_clk_khz/1000;
350
351 wtm_init();
352 scm_init();
353 gpio_init();
354 fbcs_init();
355 sdramc_init();
356}
357
358void wtm_init(void)
359{
360 /* Disable watchdog timer */
361 MCF_WTM_WCR = 0;
362}
363
364#define MCF_SCM_BCR_GBW (0x00000100)
365#define MCF_SCM_BCR_GBR (0x00000200)
366
367void scm_init(void)
368{
369 /* All masters are trusted */
370 MCF_SCM_MPR = 0x77777777;
371
372 /* Allow supervisor/user, read/write, and trusted/untrusted
373 access to all slaves */
374 MCF_SCM_PACRA = 0;
375 MCF_SCM_PACRB = 0;
376 MCF_SCM_PACRC = 0;
377 MCF_SCM_PACRD = 0;
378 MCF_SCM_PACRE = 0;
379 MCF_SCM_PACRF = 0;
380
381 /* Enable bursts */
382 MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
383}
384
385
386void fbcs_init(void)
387{
388 MCF_GPIO_PAR_CS = 0x0000003E;
389
390 /* Latch chip select */
391 MCF_FBCS1_CSAR = 0x10080000;
392
393 MCF_FBCS1_CSCR = 0x002A3780;
394 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
395
396 /* Initialize latch to drive signals to inactive states */
397 *((u16 *)(0x10080000)) = 0xFFFF;
398
399 /* External SRAM */
400 MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
401 MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
402 | MCF_FBCS_CSCR_AA
403 | MCF_FBCS_CSCR_SBM
404 | MCF_FBCS_CSCR_WS(1));
405 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
406 | MCF_FBCS_CSMR_V);
407
408 /* Boot Flash connected to FBCS0 */
409 MCF_FBCS0_CSAR = FLASH_ADDRESS;
410 MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
411 | MCF_FBCS_CSCR_BEM
412 | MCF_FBCS_CSCR_AA
413 | MCF_FBCS_CSCR_SBM
414 | MCF_FBCS_CSCR_WS(7));
415 MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
416 | MCF_FBCS_CSMR_V);
417}
418
419void sdramc_init(void)
420{
421 /*
422 * Check to see if the SDRAM has already been initialized
423 * by a run control tool
424 */
425 if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
426 /* SDRAM chip select initialization */
427
428 /* Initialize SDRAM chip select */
429 MCF_SDRAMC_SDCS0 = (0
430 | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
431 | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
432
433 /*
434 * Basic configuration and initialization
435 */
436 MCF_SDRAMC_SDCFG1 = (0
437 | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
438 | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
439 | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
440 | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
441 | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
442 | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
443 | MCF_SDRAMC_SDCFG1_WTLAT(3));
444 MCF_SDRAMC_SDCFG2 = (0
445 | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
446 | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
447 | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
448 | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
449
450
451 /*
452 * Precharge and enable write to SDMR
453 */
454 MCF_SDRAMC_SDCR = (0
455 | MCF_SDRAMC_SDCR_MODE_EN
456 | MCF_SDRAMC_SDCR_CKE
457 | MCF_SDRAMC_SDCR_DDR
458 | MCF_SDRAMC_SDCR_MUX(1)
459 | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
460 | MCF_SDRAMC_SDCR_PS_16
461 | MCF_SDRAMC_SDCR_IPALL);
462
463 /*
464 * Write extended mode register
465 */
466 MCF_SDRAMC_SDMR = (0
467 | MCF_SDRAMC_SDMR_BNKAD_LEMR
468 | MCF_SDRAMC_SDMR_AD(0x0)
469 | MCF_SDRAMC_SDMR_CMD);
470
471 /*
472 * Write mode register and reset DLL
473 */
474 MCF_SDRAMC_SDMR = (0
475 | MCF_SDRAMC_SDMR_BNKAD_LMR
476 | MCF_SDRAMC_SDMR_AD(0x163)
477 | MCF_SDRAMC_SDMR_CMD);
478
479 /*
480 * Execute a PALL command
481 */
482 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
483
484 /*
485 * Perform two REF cycles
486 */
487 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
488 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
489
490 /*
491 * Write mode register and clear reset DLL
492 */
493 MCF_SDRAMC_SDMR = (0
494 | MCF_SDRAMC_SDMR_BNKAD_LMR
495 | MCF_SDRAMC_SDMR_AD(0x063)
496 | MCF_SDRAMC_SDMR_CMD);
497
498 /*
499 * Enable auto refresh and lock SDMR
500 */
501 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
502 MCF_SDRAMC_SDCR |= (0
503 | MCF_SDRAMC_SDCR_REF
504 | MCF_SDRAMC_SDCR_DQS_OE(0xC));
505 }
506}
507
508void gpio_init(void)
509{
510 /* Enable UART0 pins */
511 MCF_GPIO_PAR_UART = ( 0
512 | MCF_GPIO_PAR_UART_PAR_URXD0
513 | MCF_GPIO_PAR_UART_PAR_UTXD0);
514
515 /* Initialize TIN3 as a GPIO output to enable the write
516 half of the latch */
517 MCF_GPIO_PAR_TIMER = 0x00;
518 __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
519 __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
520
521}
522
523int clock_pll(int fsys, int flags)
524{
525 int fref, temp, fout, mfd;
526 u32 i;
527
528 fref = FREF;
529
530 if (fsys == 0) {
531 /* Return current PLL output */
532 mfd = MCF_PLL_PFDR;
533
534 return (fref * mfd / (BUSDIV * 4));
535 }
536
537 /* Check bounds of requested system clock */
538 if (fsys > MAX_FSYS)
539 fsys = MAX_FSYS;
540 if (fsys < MIN_FSYS)
541 fsys = MIN_FSYS;
542
543 /* Multiplying by 100 when calculating the temp value,
544 and then dividing by 100 to calculate the mfd allows
545 for exact values without needing to include floating
546 point libraries. */
547 temp = 100 * fsys / fref;
548 mfd = 4 * BUSDIV * temp / 100;
549
550 /* Determine the output frequency for selected values */
551 fout = (fref * mfd / (BUSDIV * 4));
552
553 /*
554 * Check to see if the SDRAM has already been initialized.
555 * If it has then the SDRAM needs to be put into self refresh
556 * mode before reprogramming the PLL.
557 */
558 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
559 /* Put SDRAM into self refresh mode */
560 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
561
562 /*
563 * Initialize the PLL to generate the new system clock frequency.
564 * The device must be put into LIMP mode to reprogram the PLL.
565 */
566
567 /* Enter LIMP mode */
568 clock_limp(DEFAULT_LPD);
569
570 /* Reprogram PLL for desired fsys */
571 MCF_PLL_PODR = (0
572 | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
573 | MCF_PLL_PODR_BUSDIV(BUSDIV));
574
575 MCF_PLL_PFDR = mfd;
576
577 /* Exit LIMP mode */
578 clock_exit_limp();
579
580 /*
581 * Return the SDRAM to normal operation if it is in use.
582 */
583 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
584 /* Exit self refresh mode */
585 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
586
587 /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
588 MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
589
590 /* wait for DQS logic to relock */
591 for (i = 0; i < 0x200; i++)
592 ;
593
594 return fout;
595}
596
597int clock_limp(int div)
598{
599 u32 temp;
600
601 /* Check bounds of divider */
602 if (div < MIN_LPD)
603 div = MIN_LPD;
604 if (div > MAX_LPD)
605 div = MAX_LPD;
606
607 /* Save of the current value of the SSIDIV so we don't
608 overwrite the value*/
609 temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
610
611 /* Apply the divider to the system clock */
612 MCF_CCM_CDR = ( 0
613 | MCF_CCM_CDR_LPDIV(div)
614 | MCF_CCM_CDR_SSIDIV(temp));
615
616 MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
617
618 return (FREF/(3*(1 << div)));
619}
620
621int clock_exit_limp(void)
622{
623 int fout;
624
625 /* Exit LIMP mode */
626 MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
627
628 /* Wait for PLL to lock */
629 while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
630 ;
631
632 fout = get_sys_clock();
633
634 return fout;
635}
636
637int get_sys_clock(void)
638{
639 int divider;
640
641 /* Test to see if device is in LIMP mode */
642 if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
643 divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
644 return (FREF/(2 << divider));
645 }
646 else
647 return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
648}
diff --git a/arch/m68k/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c
new file mode 100644
index 00000000000..212a85deac9
--- /dev/null
+++ b/arch/m68k/platform/532x/gpio.c
@@ -0,0 +1,337 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = (void __iomem *) MCFEPORT_EPDDR,
36 .podr = (void __iomem *) MCFEPORT_EPDR,
37 .ppdr = (void __iomem *) MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "FECH",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 8,
50 },
51 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
52 .podr = (void __iomem *) MCFGPIO_PODR_FECH,
53 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
54 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
55 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
56 },
57 {
58 .gpio_chip = {
59 .label = "FECL",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
70 .podr = (void __iomem *) MCFGPIO_PODR_FECL,
71 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
72 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
73 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
74 },
75 {
76 .gpio_chip = {
77 .label = "SSI",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 5,
86 },
87 .pddr = (void __iomem *) MCFGPIO_PDDR_SSI,
88 .podr = (void __iomem *) MCFGPIO_PODR_SSI,
89 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
90 .setr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
91 .clrr = (void __iomem *) MCFGPIO_PCLRR_SSI,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
106 .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
107 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
108 .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BE",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = (void __iomem *) MCFGPIO_PDDR_BE,
124 .podr = (void __iomem *) MCFGPIO_PODR_BE,
125 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
126 .setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
127 .clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 5,
140 },
141 .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
142 .podr = (void __iomem *) MCFGPIO_PODR_CS,
143 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
144 .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
145 .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "PWM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 58,
157 .ngpio = 4,
158 },
159 .pddr = (void __iomem *) MCFGPIO_PDDR_PWM,
160 .podr = (void __iomem *) MCFGPIO_PODR_PWM,
161 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
162 .setr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
163 .clrr = (void __iomem *) MCFGPIO_PCLRR_PWM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
178 .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
179 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
180 .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
181 .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UART",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
196 .podr = (void __iomem *) MCFGPIO_PODR_UART,
197 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
198 .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
199 .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
200 },
201 {
202 .gpio_chip = {
203 .label = "QSPI",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 6,
212 },
213 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
214 .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
215 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
216 .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
217 .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
218 },
219 {
220 .gpio_chip = {
221 .label = "TIMER",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 4,
230 },
231 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
232 .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
233 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
234 .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
235 .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
236 },
237 {
238 .gpio_chip = {
239 .label = "LCDDATAH",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 2,
248 },
249 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
250 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH,
251 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
252 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
253 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
254 },
255 {
256 .gpio_chip = {
257 .label = "LCDDATAM",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 8,
266 },
267 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
268 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM,
269 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
270 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
271 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
272 },
273 {
274 .gpio_chip = {
275 .label = "LCDDATAL",
276 .request = mcf_gpio_request,
277 .free = mcf_gpio_free,
278 .direction_input = mcf_gpio_direction_input,
279 .direction_output = mcf_gpio_direction_output,
280 .get = mcf_gpio_get_value,
281 .set = mcf_gpio_set_value_fast,
282 .base = 112,
283 .ngpio = 8,
284 },
285 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
286 .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL,
287 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
288 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
289 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
290 },
291 {
292 .gpio_chip = {
293 .label = "LCDCTLH",
294 .request = mcf_gpio_request,
295 .free = mcf_gpio_free,
296 .direction_input = mcf_gpio_direction_input,
297 .direction_output = mcf_gpio_direction_output,
298 .get = mcf_gpio_get_value,
299 .set = mcf_gpio_set_value_fast,
300 .base = 120,
301 .ngpio = 1,
302 },
303 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
304 .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH,
305 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
306 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
307 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
308 },
309 {
310 .gpio_chip = {
311 .label = "LCDCTLL",
312 .request = mcf_gpio_request,
313 .free = mcf_gpio_free,
314 .direction_input = mcf_gpio_direction_input,
315 .direction_output = mcf_gpio_direction_output,
316 .get = mcf_gpio_get_value,
317 .set = mcf_gpio_set_value_fast,
318 .base = 128,
319 .ngpio = 8,
320 },
321 .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
322 .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL,
323 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
324 .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
325 .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
326 },
327};
328
329static int __init mcf_gpio_init(void)
330{
331 unsigned i = 0;
332 while (i < ARRAY_SIZE(mcf_gpio_chips))
333 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
334 return 0;
335}
336
337core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile
new file mode 100644
index 00000000000..e83fe148edd
--- /dev/null
+++ b/arch/m68k/platform/5407/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# asflags-y := -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o gpio.o
18
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/5407/config.c
new file mode 100644
index 00000000000..70ea789a400
--- /dev/null
+++ b/arch/m68k/platform/5407/config.c
@@ -0,0 +1,122 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/5407/config.c
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/kernel.h>
13#include <linux/param.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20
21/***************************************************************************/
22
23static struct mcf_platform_uart m5407_uart_platform[] = {
24 {
25 .mapbase = MCF_MBAR + MCFUART_BASE1,
26 .irq = 73,
27 },
28 {
29 .mapbase = MCF_MBAR + MCFUART_BASE2,
30 .irq = 74,
31 },
32 { },
33};
34
35static struct platform_device m5407_uart = {
36 .name = "mcfuart",
37 .id = 0,
38 .dev.platform_data = m5407_uart_platform,
39};
40
41static struct platform_device *m5407_devices[] __initdata = {
42 &m5407_uart,
43};
44
45/***************************************************************************/
46
47static void __init m5407_uart_init_line(int line, int irq)
48{
49 if (line == 0) {
50 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) {
54 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 }
58}
59
60static void __init m5407_uarts_init(void)
61{
62 const int nrlines = ARRAY_SIZE(m5407_uart_platform);
63 int line;
64
65 for (line = 0; (line < nrlines); line++)
66 m5407_uart_init_line(line, m5407_uart_platform[line].irq);
67}
68
69/***************************************************************************/
70
71static void __init m5407_timers_init(void)
72{
73 /* Timer1 is always used as system timer */
74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77
78#ifdef CONFIG_HIGHPROFILE
79 /* Timer2 is to be used as a high speed profile timer */
80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83#endif
84}
85
86/***************************************************************************/
87
88void m5407_cpu_reset(void)
89{
90 local_irq_disable();
91 /* set watchdog to soft reset, and enabled */
92 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
93 for (;;)
94 /* wait for watchdog to timeout */;
95}
96
97/***************************************************************************/
98
99void __init config_BSP(char *commandp, int size)
100{
101 mach_reset = m5407_cpu_reset;
102 m5407_timers_init();
103 m5407_uarts_init();
104
105 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1);
107 mcf_mapirq2imr(27, MCFINTC_EINT3);
108 mcf_mapirq2imr(29, MCFINTC_EINT5);
109 mcf_mapirq2imr(31, MCFINTC_EINT7);
110}
111
112/***************************************************************************/
113
114static int __init init_BSP(void)
115{
116 platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
117 return 0;
118}
119
120arch_initcall(init_BSP);
121
122/***************************************************************************/
diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c
new file mode 100644
index 00000000000..5850612b4a3
--- /dev/null
+++ b/arch/m68k/platform/5407/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = (void __iomem *) MCFSIM_PADDR,
36 .podr = (void __iomem *) MCFSIM_PADAT,
37 .ppdr = (void __iomem *) MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/54xx/Makefile b/arch/m68k/platform/54xx/Makefile
new file mode 100644
index 00000000000..6cfd090ec3c
--- /dev/null
+++ b/arch/m68k/platform/54xx/Makefile
@@ -0,0 +1,19 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o
18obj-$(CONFIG_FIREBEE) += firebee.o
19
diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/54xx/config.c
new file mode 100644
index 00000000000..78130984db9
--- /dev/null
+++ b/arch/m68k/platform/54xx/config.c
@@ -0,0 +1,115 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/54xx/config.c
5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/m54xxsim.h>
19#include <asm/mcfuart.h>
20#include <asm/m54xxgpt.h>
21
22/***************************************************************************/
23
24static struct mcf_platform_uart m54xx_uart_platform[] = {
25 {
26 .mapbase = MCF_MBAR + MCFUART_BASE1,
27 .irq = 64 + 35,
28 },
29 {
30 .mapbase = MCF_MBAR + MCFUART_BASE2,
31 .irq = 64 + 34,
32 },
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE3,
35 .irq = 64 + 33,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE4,
39 .irq = 64 + 32,
40 },
41};
42
43static struct platform_device m54xx_uart = {
44 .name = "mcfuart",
45 .id = 0,
46 .dev.platform_data = m54xx_uart_platform,
47};
48
49static struct platform_device *m54xx_devices[] __initdata = {
50 &m54xx_uart,
51};
52
53
54/***************************************************************************/
55
56static void __init m54xx_uart_init_line(int line, int irq)
57{
58 int rts_cts;
59
60 /* enable io pins */
61 switch (line) {
62 case 0:
63 rts_cts = 0; break;
64 case 1:
65 rts_cts = MCF_PAR_PSC_RTS_RTS; break;
66 case 2:
67 rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
68 case 3:
69 rts_cts = 0; break;
70 }
71 __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
72 MCF_MBAR + MCF_PAR_PSC(line));
73}
74
75static void __init m54xx_uarts_init(void)
76{
77 const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
78 int line;
79
80 for (line = 0; (line < nrlines); line++)
81 m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
82}
83
84/***************************************************************************/
85
86static void mcf54xx_reset(void)
87{
88 /* disable interrupts and enable the watchdog */
89 asm("movew #0x2700, %sr\n");
90 __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
91 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
92 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
93 MCF_MBAR + MCF_GPT_GMS0);
94}
95
96/***************************************************************************/
97
98void __init config_BSP(char *commandp, int size)
99{
100 mach_reset = mcf54xx_reset;
101 m54xx_uarts_init();
102}
103
104/***************************************************************************/
105
106static int __init init_BSP(void)
107{
108
109 platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
110 return 0;
111}
112
113arch_initcall(init_BSP);
114
115/***************************************************************************/
diff --git a/arch/m68k/platform/54xx/firebee.c b/arch/m68k/platform/54xx/firebee.c
new file mode 100644
index 00000000000..46d50534f98
--- /dev/null
+++ b/arch/m68k/platform/54xx/firebee.c
@@ -0,0 +1,86 @@
1/***************************************************************************/
2
3/*
4 * firebee.c -- extra startup code support for the FireBee boards
5 *
6 * Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h>
17#include <linux/mtd/physmap.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21/***************************************************************************/
22
23/*
24 * 8MB of NOR flash fitted to the FireBee board.
25 */
26#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */
27#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */
28
29#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */
30#define PART_BOOT_SIZE 0x00040000 /* 256k in size */
31#define PART_IMAGE_START 0x00040000 /* Start after boot loader */
32#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */
33#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */
34#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */
35
36static struct mtd_partition firebee_flash_parts[] = {
37 {
38 .name = "dBUG",
39 .offset = PART_BOOT_START,
40 .size = PART_BOOT_SIZE,
41 },
42 {
43 .name = "FPGA",
44 .offset = PART_FPGA_START,
45 .size = PART_FPGA_SIZE,
46 },
47 {
48 .name = "image",
49 .offset = PART_IMAGE_START,
50 .size = PART_IMAGE_SIZE,
51 },
52};
53
54static struct physmap_flash_data firebee_flash_data = {
55 .width = 2,
56 .nr_parts = ARRAY_SIZE(firebee_flash_parts),
57 .parts = firebee_flash_parts,
58};
59
60static struct resource firebee_flash_resource = {
61 .start = FLASH_PHYS_ADDR,
62 .end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
63 .flags = IORESOURCE_MEM,
64};
65
66static struct platform_device firebee_flash = {
67 .name = "physmap-flash",
68 .id = 0,
69 .dev = {
70 .platform_data = &firebee_flash_data,
71 },
72 .num_resources = 1,
73 .resource = &firebee_flash_resource,
74};
75
76/***************************************************************************/
77
78static int __init init_firebee(void)
79{
80 platform_device_register(&firebee_flash);
81 return 0;
82}
83
84arch_initcall(init_firebee);
85
86/***************************************************************************/
diff --git a/arch/m68k/platform/68328/Makefile b/arch/m68k/platform/68328/Makefile
new file mode 100644
index 00000000000..5e5435552d5
--- /dev/null
+++ b/arch/m68k/platform/68328/Makefile
@@ -0,0 +1,22 @@
1#
2# Makefile for arch/m68knommu/platform/68328.
3#
4
5head-y = head-$(MODEL).o
6head-$(CONFIG_PILOT) = head-pilot.o
7head-$(CONFIG_DRAGEN2) = head-de2.o
8
9obj-y += entry.o ints.o timers.o
10obj-$(CONFIG_M68328) += config.o
11obj-$(CONFIG_ROM) += romvec.o
12
13extra-y := head.o
14extra-$(CONFIG_M68328) += bootlogo.rh head.o
15
16$(obj)/bootlogo.rh: $(src)/bootlogo.h
17 perl $(src)/bootlogo.pl < $(src)/bootlogo.h > $(obj)/bootlogo.rh
18
19$(obj)/head.o: $(obj)/$(head-y)
20 ln -sf $(head-y) $(obj)/head.o
21
22clean-files := $(obj)/bootlogo.rh $(obj)/head.o $(head-y)
diff --git a/arch/m68k/platform/68328/bootlogo.h b/arch/m68k/platform/68328/bootlogo.h
new file mode 100644
index 00000000000..67bc2c17386
--- /dev/null
+++ b/arch/m68k/platform/68328/bootlogo.h
@@ -0,0 +1,270 @@
1#define bootlogo_width 160
2#define bootlogo_height 160
3static unsigned char bootlogo_bits[] = {
4 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x01, 0x00, 0x00, 0x00,
5 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
6 0x00, 0x00, 0x40, 0x55, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55,
8 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
11 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
12 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
13 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
14 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
15 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x10, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x00,
18 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
21 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
22 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x20, 0x00, 0x00,
23 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
24 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
26 0x80, 0x08, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00,
27 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x08, 0x00, 0x00,
28 0x00, 0xff, 0x80, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
29 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0xf8, 0x80, 0x0f,
30 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
31 0x50, 0x04, 0x00, 0x00, 0x00, 0x78, 0x80, 0x0f, 0x00, 0x00, 0x00, 0x00,
32 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x03, 0x00, 0x00,
33 0x00, 0x78, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
34 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00,
35 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40,
36 0xa8, 0x02, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
37 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x70, 0x28, 0x01, 0x00, 0x00,
38 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
39 0x00, 0x20, 0x00, 0x00, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00,
40 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x70,
41 0x54, 0x01, 0x00, 0x00, 0x00, 0x3e, 0x80, 0x01, 0x3a, 0x78, 0x80, 0x0e,
42 0x50, 0xc0, 0x03, 0x0e, 0x00, 0x20, 0x00, 0x00, 0xaa, 0x00, 0x00, 0x00,
43 0x00, 0x3e, 0xf0, 0x83, 0x1f, 0xfc, 0xe0, 0x0f, 0x78, 0xf8, 0x87, 0x1f,
44 0x00, 0x18, 0x00, 0x30, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x1e, 0xf8, 0xc3,
45 0x1f, 0xfc, 0xe0, 0x0f, 0x78, 0xf8, 0x87, 0x0f, 0x00, 0x20, 0x00, 0x10,
46 0x55, 0x00, 0x00, 0x00, 0x00, 0x1e, 0xc0, 0x03, 0x9f, 0xf3, 0x80, 0x0f,
47 0x78, 0x80, 0xc7, 0x0e, 0x00, 0x18, 0x00, 0x20, 0xaa, 0x00, 0x00, 0x00,
48 0x00, 0x1e, 0xe0, 0x03, 0x9f, 0xf1, 0x80, 0x07, 0x78, 0x80, 0x67, 0x00,
49 0x00, 0x24, 0x00, 0x18, 0x55, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe0, 0x01,
50 0x5e, 0xf0, 0x80, 0x07, 0x3c, 0x00, 0x2f, 0x00, 0x00, 0x14, 0x00, 0x20,
51 0xaa, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe0, 0x01, 0x7f, 0xf0, 0x80, 0x07,
52 0x3c, 0x00, 0x3f, 0x00, 0x00, 0x08, 0x00, 0x18, 0x55, 0x00, 0x00, 0x00,
53 0x00, 0x0f, 0xe0, 0x00, 0x3f, 0xf0, 0xc0, 0x03, 0x1e, 0x00, 0x1f, 0x00,
54 0x00, 0x14, 0x00, 0x28, 0xaa, 0x00, 0x00, 0x00, 0x80, 0x0f, 0xf0, 0x00,
55 0x1f, 0xf0, 0xc0, 0x03, 0x1f, 0x00, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x0c,
56 0x54, 0x00, 0x00, 0x00, 0x80, 0x07, 0x78, 0x00, 0x1f, 0x78, 0xc0, 0x03,
57 0x1f, 0x00, 0x1e, 0x00, 0x00, 0x0a, 0x00, 0x12, 0xa8, 0x00, 0x00, 0x00,
58 0x80, 0x07, 0x78, 0x00, 0x1f, 0x78, 0xe0, 0x03, 0x1f, 0x00, 0x1f, 0x00,
59 0x00, 0x04, 0x00, 0x0a, 0x54, 0x00, 0x00, 0x00, 0x80, 0x07, 0x78, 0x80,
60 0x0f, 0x78, 0xe0, 0x03, 0x1f, 0x00, 0x1e, 0x00, 0x00, 0x0a, 0x00, 0x08,
61 0x50, 0x01, 0x00, 0x00, 0x84, 0x03, 0x78, 0x80, 0x07, 0x3c, 0xe0, 0xc1,
62 0x0f, 0x00, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x06, 0xa8, 0x00, 0x00, 0x00,
63 0xc0, 0x03, 0x78, 0xc0, 0x07, 0x3c, 0xe0, 0xc1, 0x0f, 0x00, 0x1f, 0x00,
64 0x00, 0x0a, 0x00, 0x08, 0x50, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x38, 0xc0,
65 0x07, 0x3c, 0xe0, 0x60, 0x0f, 0x80, 0x1e, 0x00, 0x00, 0x05, 0x00, 0x07,
66 0xa0, 0x00, 0x00, 0x80, 0xe0, 0x01, 0x3c, 0xc0, 0x07, 0x3c, 0xf0, 0xa0,
67 0x07, 0xc0, 0x1c, 0x00, 0x00, 0x0a, 0x80, 0x08, 0xa0, 0x02, 0x00, 0xa0,
68 0xe0, 0x21, 0x1c, 0xc0, 0x03, 0x1c, 0x71, 0x90, 0x47, 0x40, 0x3c, 0x04,
69 0x00, 0x05, 0x80, 0x06, 0xa0, 0x02, 0x00, 0x20, 0xe0, 0x31, 0x1e, 0xc3,
70 0x03, 0x1e, 0x79, 0x98, 0x47, 0x60, 0x38, 0x04, 0x00, 0x15, 0x40, 0x0a,
71 0xa0, 0x0a, 0x00, 0x1a, 0xe0, 0x19, 0x9e, 0xe1, 0x01, 0x9e, 0x78, 0xcc,
72 0xa7, 0x32, 0x78, 0x02, 0x80, 0x2a, 0x40, 0x05, 0x80, 0x2a, 0x00, 0x05,
73 0xe0, 0x0d, 0x9e, 0xe0, 0x01, 0xde, 0x78, 0xc6, 0x97, 0x1b, 0x78, 0x03,
74 0x80, 0x52, 0x30, 0x0a, 0x00, 0x95, 0xd2, 0x0a, 0xe0, 0x0f, 0xfe, 0xe0,
75 0x00, 0x7e, 0xf8, 0x87, 0x9f, 0x0f, 0xf8, 0x01, 0x00, 0xa1, 0x0e, 0x15,
76 0x80, 0x55, 0x55, 0x01, 0xe0, 0x01, 0x3c, 0xf0, 0x00, 0x3c, 0xf0, 0x80,
77 0x8f, 0x0f, 0x70, 0x00, 0x00, 0x81, 0x02, 0x14, 0x00, 0x54, 0x55, 0x00,
78 0xc0, 0x01, 0x3c, 0x00, 0x00, 0x0c, 0x60, 0x00, 0x07, 0x03, 0x70, 0x00,
79 0x80, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
80 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
81 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
83 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
84 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
86 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
91 0x00, 0x00, 0x40, 0x01, 0x00, 0x11, 0x09, 0x00, 0x04, 0x00, 0x01, 0x00,
92 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00,
93 0x00, 0x20, 0x01, 0x00, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x49, 0x32, 0x49, 0x49, 0x91,
95 0x24, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
96 0x00, 0x00, 0x20, 0x49, 0x0a, 0x09, 0xc9, 0x92, 0x14, 0x81, 0x00, 0x00,
97 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x49,
98 0x18, 0x01, 0x49, 0x92, 0x0c, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x49, 0x30, 0x01, 0x49, 0x92,
100 0x14, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
101 0x00, 0x00, 0x08, 0x69, 0x22, 0x09, 0x49, 0xd2, 0x24, 0x24, 0x00, 0x00,
102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x51,
103 0x1a, 0x09, 0x49, 0xa2, 0x44, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
105 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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261 0xff, 0xbf, 0x24, 0x00, 0x00, 0x90, 0x24, 0x49, 0x12, 0x92, 0x40, 0x92,
262 0x24, 0x06, 0x49, 0x48, 0x50, 0x0a, 0x02, 0xfe, 0xff, 0x3f, 0x00, 0x05,
263 0x00, 0x50, 0xa5, 0x4a, 0x15, 0x92, 0x40, 0x92, 0x24, 0x06, 0x49, 0x48,
264 0x80, 0x40, 0x48, 0xfe, 0xff, 0x3f, 0x49, 0x00, 0x00, 0x20, 0x42, 0x84,
265 0x88, 0x1a, 0x41, 0x92, 0x34, 0x49, 0x49, 0x68, 0x00, 0x38, 0x10, 0x07,
266 0x00, 0x60, 0x80, 0x00, 0x00, 0x20, 0x42, 0x84, 0x88, 0x14, 0x4e, 0x92,
267 0x28, 0x49, 0x46, 0x50, 0x00, 0x80, 0x83, 0x01, 0x00, 0xa0, 0x6a, 0x00,
268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
269 0x00, 0x00, 0xfc, 0x00, 0x00, 0xc0, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x00,
270 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, };
diff --git a/arch/m68k/platform/68328/bootlogo.pl b/arch/m68k/platform/68328/bootlogo.pl
new file mode 100644
index 00000000000..b04ae3f50da
--- /dev/null
+++ b/arch/m68k/platform/68328/bootlogo.pl
@@ -0,0 +1,10 @@
1
2$_ = join("", <>);
3
4s/(0x[0-9a-f]{2})/sprintf("0x%.2x",ord(pack("b8",unpack("B8",chr(hex($1))))))/gei;
5
6s/^ / .byte /gm;
7s/[,};]+$//gm;
8s/^static.*//gm;
9
10print $_;
diff --git a/arch/m68k/platform/68328/config.c b/arch/m68k/platform/68328/config.c
new file mode 100644
index 00000000000..a7bd21deb00
--- /dev/null
+++ b/arch/m68k/platform/68328/config.c
@@ -0,0 +1,52 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/68328/config.c
5 *
6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive
11 * for more details.
12 *
13 * VZ Support/Fixes Evan Stawnyczy <e@lineo.ca>
14 */
15
16/***************************************************************************/
17
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <asm/system.h>
21#include <asm/machdep.h>
22#include <asm/MC68328.h>
23
24/***************************************************************************/
25
26void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
27
28/***************************************************************************/
29
30void m68328_reset (void)
31{
32 local_irq_disable();
33 asm volatile ("moveal #0x10c00000, %a0;\n\t"
34 "moveb #0, 0xFFFFF300;\n\t"
35 "moveal 0(%a0), %sp;\n\t"
36 "moveal 4(%a0), %a0;\n\t"
37 "jmp (%a0);");
38}
39
40/***************************************************************************/
41
42void config_BSP(char *command, int len)
43{
44 printk(KERN_INFO "\n68328 support D. Jeff Dionne <jeff@uclinux.org>\n");
45 printk(KERN_INFO "68328 support Kenneth Albanowski <kjahds@kjshds.com>\n");
46 printk(KERN_INFO "68328/Pilot support Bernhard Kuhn <kuhn@lpr.e-technik.tu-muenchen.de>\n");
47
48 mach_gettod = m68328_timer_gettod;
49 mach_reset = m68328_reset;
50}
51
52/***************************************************************************/
diff --git a/arch/m68k/platform/68328/entry.S b/arch/m68k/platform/68328/entry.S
new file mode 100644
index 00000000000..293e1eba9ac
--- /dev/null
+++ b/arch/m68k/platform/68328/entry.S
@@ -0,0 +1,261 @@
1/*
2 * linux/arch/m68knommu/platform/68328/entry.S
3 *
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file README.legal in the main directory of this archive
8 * for more details.
9 *
10 * Linux/m68k support by Hamish Macdonald
11 */
12
13#include <linux/linkage.h>
14#include <asm/thread_info.h>
15#include <asm/unistd.h>
16#include <asm/errno.h>
17#include <asm/setup.h>
18#include <asm/segment.h>
19#include <asm/traps.h>
20#include <asm/asm-offsets.h>
21#include <asm/entry.h>
22
23.text
24
25.globl system_call
26.globl resume
27.globl ret_from_exception
28.globl ret_from_signal
29.globl sys_call_table
30.globl ret_from_interrupt
31.globl bad_interrupt
32.globl inthandler1
33.globl inthandler2
34.globl inthandler3
35.globl inthandler4
36.globl inthandler5
37.globl inthandler6
38.globl inthandler7
39
40badsys:
41 movel #-ENOSYS,%sp@(PT_OFF_D0)
42 jra ret_from_exception
43
44do_trace:
45 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
46 subql #4,%sp
47 SAVE_SWITCH_STACK
48 jbsr syscall_trace_enter
49 RESTORE_SWITCH_STACK
50 addql #4,%sp
51 movel %sp@(PT_OFF_ORIG_D0),%d1
52 movel #-ENOSYS,%d0
53 cmpl #NR_syscalls,%d1
54 jcc 1f
55 lsl #2,%d1
56 lea sys_call_table, %a0
57 jbsr %a0@(%d1)
58
591: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
60 subql #4,%sp /* dummy return address */
61 SAVE_SWITCH_STACK
62 jbsr syscall_trace_leave
63
64ret_from_signal:
65 RESTORE_SWITCH_STACK
66 addql #4,%sp
67 jra ret_from_exception
68
69ENTRY(system_call)
70 SAVE_ALL
71
72 /* save top of frame*/
73 pea %sp@
74 jbsr set_esp0
75 addql #4,%sp
76
77 movel %sp@(PT_OFF_ORIG_D0),%d0
78
79 movel %sp,%d1 /* get thread_info pointer */
80 andl #-THREAD_SIZE,%d1
81 movel %d1,%a2
82 btst #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
83 jne do_trace
84 cmpl #NR_syscalls,%d0
85 jcc badsys
86 lsl #2,%d0
87 lea sys_call_table,%a0
88 movel %a0@(%d0), %a0
89 jbsr %a0@
90 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/
91
92ret_from_exception:
93 btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/
94 jeq Luser_return /* if so, skip resched, signals*/
95
96Lkernel_return:
97 RESTORE_ALL
98
99Luser_return:
100 /* only allow interrupts when we are really the last one on the*/
101 /* kernel stack, otherwise stack overflow can occur during*/
102 /* heavy interrupt load*/
103 andw #ALLOWINT,%sr
104
105 movel %sp,%d1 /* get thread_info pointer */
106 andl #-THREAD_SIZE,%d1
107 movel %d1,%a2
1081:
109 move %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
110 jne Lwork_to_do
111 RESTORE_ALL
112
113Lwork_to_do:
114 movel %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
115 btst #TIF_NEED_RESCHED,%d1
116 jne reschedule
117
118Lsignal_return:
119 subql #4,%sp /* dummy return address*/
120 SAVE_SWITCH_STACK
121 pea %sp@(SWITCH_STACK_SIZE)
122 bsrw do_signal
123 addql #4,%sp
124 RESTORE_SWITCH_STACK
125 addql #4,%sp
126 jra 1b
127
128/*
129 * This is the main interrupt handler, responsible for calling process_int()
130 */
131inthandler1:
132 SAVE_ALL
133 movew %sp@(PT_OFF_FORMATVEC), %d0
134 and #0x3ff, %d0
135
136 movel %sp,%sp@-
137 movel #65,%sp@- /* put vector # on stack*/
138 jbsr process_int /* process the IRQ*/
1393: addql #8,%sp /* pop parameters off stack*/
140 bra ret_from_interrupt
141
142inthandler2:
143 SAVE_ALL
144 movew %sp@(PT_OFF_FORMATVEC), %d0
145 and #0x3ff, %d0
146
147 movel %sp,%sp@-
148 movel #66,%sp@- /* put vector # on stack*/
149 jbsr process_int /* process the IRQ*/
1503: addql #8,%sp /* pop parameters off stack*/
151 bra ret_from_interrupt
152
153inthandler3:
154 SAVE_ALL
155 movew %sp@(PT_OFF_FORMATVEC), %d0
156 and #0x3ff, %d0
157
158 movel %sp,%sp@-
159 movel #67,%sp@- /* put vector # on stack*/
160 jbsr process_int /* process the IRQ*/
1613: addql #8,%sp /* pop parameters off stack*/
162 bra ret_from_interrupt
163
164inthandler4:
165 SAVE_ALL
166 movew %sp@(PT_OFF_FORMATVEC), %d0
167 and #0x3ff, %d0
168
169 movel %sp,%sp@-
170 movel #68,%sp@- /* put vector # on stack*/
171 jbsr process_int /* process the IRQ*/
1723: addql #8,%sp /* pop parameters off stack*/
173 bra ret_from_interrupt
174
175inthandler5:
176 SAVE_ALL
177 movew %sp@(PT_OFF_FORMATVEC), %d0
178 and #0x3ff, %d0
179
180 movel %sp,%sp@-
181 movel #69,%sp@- /* put vector # on stack*/
182 jbsr process_int /* process the IRQ*/
1833: addql #8,%sp /* pop parameters off stack*/
184 bra ret_from_interrupt
185
186inthandler6:
187 SAVE_ALL
188 movew %sp@(PT_OFF_FORMATVEC), %d0
189 and #0x3ff, %d0
190
191 movel %sp,%sp@-
192 movel #70,%sp@- /* put vector # on stack*/
193 jbsr process_int /* process the IRQ*/
1943: addql #8,%sp /* pop parameters off stack*/
195 bra ret_from_interrupt
196
197inthandler7:
198 SAVE_ALL
199 movew %sp@(PT_OFF_FORMATVEC), %d0
200 and #0x3ff, %d0
201
202 movel %sp,%sp@-
203 movel #71,%sp@- /* put vector # on stack*/
204 jbsr process_int /* process the IRQ*/
2053: addql #8,%sp /* pop parameters off stack*/
206 bra ret_from_interrupt
207
208inthandler:
209 SAVE_ALL
210 movew %sp@(PT_OFF_FORMATVEC), %d0
211 and #0x3ff, %d0
212
213 movel %sp,%sp@-
214 movel %d0,%sp@- /* put vector # on stack*/
215 jbsr process_int /* process the IRQ*/
2163: addql #8,%sp /* pop parameters off stack*/
217 bra ret_from_interrupt
218
219ret_from_interrupt:
220 jeq 1f
2212:
222 RESTORE_ALL
2231:
224 moveb %sp@(PT_OFF_SR), %d0
225 and #7, %d0
226 jhi 2b
227
228 /* check if we need to do software interrupts */
229 jeq ret_from_exception
230
231 pea ret_from_exception
232 jra do_softirq
233
234
235/*
236 * Handler for uninitialized and spurious interrupts.
237 */
238ENTRY(bad_interrupt)
239 addql #1,irq_err_count
240 rte
241
242/*
243 * Beware - when entering resume, prev (the current task) is
244 * in a0, next (the new task) is in a1, so don't change these
245 * registers until their contents are no longer needed.
246 */
247ENTRY(resume)
248 movel %a0,%d1 /* save prev thread in d1 */
249 movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */
250 SAVE_SWITCH_STACK
251 movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */
252 movel %usp,%a3 /* save usp */
253 movel %a3,%a0@(TASK_THREAD+THREAD_USP)
254
255 movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore user stack */
256 movel %a3,%usp
257 movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */
258 RESTORE_SWITCH_STACK
259 movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */
260 rts
261
diff --git a/arch/m68k/platform/68328/head-de2.S b/arch/m68k/platform/68328/head-de2.S
new file mode 100644
index 00000000000..f632fdcb93e
--- /dev/null
+++ b/arch/m68k/platform/68328/head-de2.S
@@ -0,0 +1,128 @@
1
2#define MEM_END 0x00800000 /* Memory size 8Mb */
3
4#undef CRT_DEBUG
5
6.macro PUTC CHAR
7#ifdef CRT_DEBUG
8 moveq #\CHAR, %d7
9 jsr putc
10#endif
11.endm
12
13 .global _start
14 .global _rambase
15 .global _ramvec
16 .global _ramstart
17 .global _ramend
18
19 .data
20
21/*
22 * Set up the usable of RAM stuff
23 */
24_rambase:
25 .long 0
26_ramvec:
27 .long 0
28_ramstart:
29 .long 0
30_ramend:
31 .long 0
32
33 .text
34
35_start:
36
37/*
38 * Setup initial stack
39 */
40 /* disable all interrupts */
41 movew #0x2700, %sr
42 movel #-1, 0xfffff304
43 movel #MEM_END-4, %sp
44
45 PUTC '\r'
46 PUTC '\n'
47 PUTC 'A'
48 PUTC 'B'
49
50/*
51 * Determine end of RAM
52 */
53
54 movel #MEM_END, %a0
55 movel %a0, _ramend
56
57 PUTC 'C'
58
59/*
60 * Move ROM filesystem above bss :-)
61 */
62
63 moveal #_sbss, %a0 /* romfs at the start of bss */
64 moveal #_ebss, %a1 /* Set up destination */
65 movel %a0, %a2 /* Copy of bss start */
66
67 movel 8(%a0), %d1 /* Get size of ROMFS */
68 addql #8, %d1 /* Allow for rounding */
69 andl #0xfffffffc, %d1 /* Whole words */
70
71 addl %d1, %a0 /* Copy from end */
72 addl %d1, %a1 /* Copy from end */
73 movel %a1, _ramstart /* Set start of ram */
74
751:
76 movel -(%a0), %d0 /* Copy dword */
77 movel %d0, -(%a1)
78 cmpl %a0, %a2 /* Check if at end */
79 bne 1b
80
81 PUTC 'D'
82
83/*
84 * Initialize BSS segment to 0
85 */
86
87 lea _sbss, %a0
88 lea _ebss, %a1
89
90 /* Copy 0 to %a0 until %a0 == %a1 */
912: cmpal %a0, %a1
92 beq 1f
93 clrl (%a0)+
94 bra 2b
951:
96
97 PUTC 'E'
98
99/*
100 * Load the current task pointer and stack
101 */
102
103 lea init_thread_union, %a0
104 lea 0x2000(%a0), %sp
105
106 PUTC 'F'
107 PUTC '\r'
108 PUTC '\n'
109
110/*
111 * Go
112 */
113
114 jmp start_kernel
115
116/*
117 * Local functions
118 */
119
120#ifdef CRT_DEBUG
121putc:
122 moveb %d7, 0xfffff907
1231:
124 movew 0xfffff906, %d7
125 andw #0x2000, %d7
126 beq 1b
127 rts
128#endif
diff --git a/arch/m68k/platform/68328/head-pilot.S b/arch/m68k/platform/68328/head-pilot.S
new file mode 100644
index 00000000000..aecff532b34
--- /dev/null
+++ b/arch/m68k/platform/68328/head-pilot.S
@@ -0,0 +1,222 @@
1/*
2 * linux/arch/m68knommu/platform/68328/head-pilot.S
3 * - A startup file for the MC68328
4 *
5 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
6 * Kenneth Albanowski <kjahds@kjahds.com>,
7 * The Silver Hammer Group, Ltd.
8 *
9 * (c) 1995, Dionne & Associates
10 * (c) 1995, DKG Display Tech.
11 */
12
13#define ASSEMBLY
14
15#define IMMED #
16#define DBG_PUTC(x) moveb IMMED x, 0xfffff907
17
18
19.global _stext
20.global _start
21
22.global _rambase
23.global _ramvec
24.global _ramstart
25.global _ramend
26
27.global penguin_bits
28
29#ifdef CONFIG_PILOT
30
31#define IMR 0xFFFFF304
32
33 .data
34 .align 16
35
36penguin_bits:
37#include "bootlogo.rh"
38
39#endif
40
41/*****************************************************************************/
42
43.data
44
45/*
46 * Set up the usable of RAM stuff. Size of RAM is determined then
47 * an initial stack set up at the end.
48 */
49.align 4
50_ramvec:
51.long 0
52_rambase:
53.long 0
54_ramstart:
55.long 0
56_ramend:
57.long 0
58
59.text
60
61_start:
62_stext:
63
64
65#ifdef CONFIG_M68328
66
67#ifdef CONFIG_PILOT
68 .byte 0x4e, 0xfa, 0x00, 0x0a /* Jmp +X bytes */
69 .byte 'b', 'o', 'o', 't'
70 .word 10000
71
72 nop
73#endif
74
75 moveq #0, %d0
76 movew %d0, 0xfffff618 /* Watchdog off */
77 movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
78
79 movew #0x0800, 0xfffff906 /* Ignore CTS */
80 movew #0x010b, 0xfffff902 /* BAUD to 9600 */
81
82 movew #0x2410, 0xfffff200 /* PLLCR */
83 movew #0x123, 0xfffff202 /* PLLFSR */
84
85#ifdef CONFIG_PILOT
86 moveb #0, 0xfffffA27 /* LCKCON */
87 movel #_start, 0xfffffA00 /* LSSA */
88 moveb #0xa, 0xfffffA05 /* LVPW */
89 movew #0x9f, 0xFFFFFa08 /* LXMAX */
90 movew #0x9f, 0xFFFFFa0a /* LYMAX */
91 moveb #9, 0xfffffa29 /* LBAR */
92 moveb #0, 0xfffffa25 /* LPXCD */
93 moveb #0x04, 0xFFFFFa20 /* LPICF */
94 moveb #0x58, 0xfffffA27 /* LCKCON */
95 moveb #0x85, 0xfffff429 /* PFDATA */
96 moveb #0xd8, 0xfffffA27 /* LCKCON */
97 moveb #0xc5, 0xfffff429 /* PFDATA */
98 moveb #0xd5, 0xfffff429 /* PFDATA */
99
100 moveal #0x00100000, %a3
101 moveal #0x100ffc00, %a4
102#endif /* CONFIG_PILOT */
103
104#endif /* CONFIG_M68328 */
105
106 movew #0x2700, %sr
107 lea %a4@(-4), %sp
108
109 DBG_PUTC('\r')
110 DBG_PUTC('\n')
111 DBG_PUTC('A')
112
113 moveq #0,%d0
114 movew #16384, %d0 /* PLL settle wait loop */
115L0:
116 subw #1, %d0
117 bne L0
118
119 DBG_PUTC('B')
120
121 /* Copy command line from beginning of RAM (+16) to end of bss */
122 movel #CONFIG_VECTORBASE, %d7
123 addl #16, %d7
124 moveal %d7, %a0
125 moveal #_ebss, %a1
126 lea %a1@(512), %a2
127
128 DBG_PUTC('C')
129
130 /* Copy %a0 to %a1 until %a1 == %a2 */
131L2:
132 movel %a0@+, %d0
133 movel %d0, %a1@+
134 cmpal %a1, %a2
135 bhi L2
136
137 /* Copy data+init segment from ROM to RAM */
138 moveal #_etext, %a0
139 moveal #_sdata, %a1
140 moveal #__init_end, %a2
141
142 DBG_PUTC('D')
143
144 /* Copy %a0 to %a1 until %a1 == %a2 */
145LD1:
146 movel %a0@+, %d0
147 movel %d0, %a1@+
148 cmpal %a1, %a2
149 bhi LD1
150
151 DBG_PUTC('E')
152
153 moveal #_sbss, %a0
154 moveal #_ebss, %a1
155
156 /* Copy 0 to %a0 until %a0 == %a1 */
157L1:
158 movel #0, %a0@+
159 cmpal %a0, %a1
160 bhi L1
161
162 DBG_PUTC('F')
163
164 /* Copy command line from end of bss to command line */
165 moveal #_ebss, %a0
166 moveal #command_line, %a1
167 lea %a1@(512), %a2
168
169 DBG_PUTC('G')
170
171 /* Copy %a0 to %a1 until %a1 == %a2 */
172L3:
173 movel %a0@+, %d0
174 movel %d0, %a1@+
175 cmpal %a1, %a2
176 bhi L3
177
178 movel #_sdata, %d0
179 movel %d0, _rambase
180 movel #_ebss, %d0
181 movel %d0, _ramstart
182
183 movel %a4, %d0
184 subl #4096, %d0 /* Reserve 4K of stack */
185 moveq #79, %d7
186 movel %d0, _ramend
187
188 movel %a3, %d0
189 movel %d0, rom_length
190
191 pea 0
192 pea env
193 pea %sp@(4)
194 pea 0
195
196 DBG_PUTC('H')
197
198#ifdef CONFIG_PILOT
199 movel #penguin_bits, 0xFFFFFA00
200 moveb #10, 0xFFFFFA05
201 movew #160, 0xFFFFFA08
202 movew #160, 0xFFFFFA0A
203#endif /* CONFIG_PILOT */
204
205 DBG_PUTC('I')
206
207 lea init_thread_union, %a0
208 lea 0x2000(%a0), %sp
209
210 DBG_PUTC('J')
211 DBG_PUTC('\r')
212 DBG_PUTC('\n')
213
214 jsr start_kernel
215_exit:
216
217 jmp _exit
218
219
220 .data
221env:
222 .long 0
diff --git a/arch/m68k/platform/68328/head-ram.S b/arch/m68k/platform/68328/head-ram.S
new file mode 100644
index 00000000000..7f1aeeacb21
--- /dev/null
+++ b/arch/m68k/platform/68328/head-ram.S
@@ -0,0 +1,141 @@
1
2 .global __main
3 .global __rom_start
4
5 .global _rambase
6 .global _ramstart
7
8 .global splash_bits
9 .global _start
10 .global _stext
11 .global _edata
12
13#define DEBUG
14#define ROM_OFFSET 0x10C00000
15#define STACK_GAURD 0x10
16
17 .text
18
19_start:
20_stext:
21 movew #0x2700, %sr /* Exceptions off! */
22
23#if 0
24 /* Init chip registers. uCsimm specific */
25 moveb #0x00, 0xfffffb0b /* Watchdog off */
26 moveb #0x10, 0xfffff000 /* SCR */
27
28 movew #0x2400, 0xfffff200 /* PLLCR */
29 movew #0x0123, 0xfffff202 /* PLLFSR */
30
31 moveb #0x00, 0xfffff40b /* enable chip select */
32 moveb #0x00, 0xfffff423 /* enable /DWE */
33 moveb #0x08, 0xfffffd0d /* disable hardmap */
34 moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
35
36 movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
37 movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
38
39 movew #0x8f00, 0xfffffc00 /* DRAM configuration */
40 movew #0x9667, 0xfffffc02 /* DRAM control */
41 movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
42 movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
43
44 moveb #0x40, 0xfffff300 /* IVR */
45 movel #0x007FFFFF, %d0 /* IMR */
46 movel %d0, 0xfffff304
47
48 moveb 0xfffff42b, %d0
49 andb #0xe0, %d0
50 moveb %d0, 0xfffff42b
51
52 moveb #0x08, 0xfffff907 /* Ignore CTS */
53 movew #0x010b, 0xfffff902 /* BAUD to 9600 */
54 movew #0xe100, 0xfffff900 /* enable */
55#endif
56
57 movew #16384, %d0 /* PLL settle wait loop */
58L0:
59 subw #1, %d0
60 bne L0
61#ifdef DEBUG
62 moveq #70, %d7 /* 'F' */
63 moveb %d7,0xfffff907 /* No absolute addresses */
64pclp1:
65 movew 0xfffff906, %d7
66 andw #0x2000, %d7
67 beq pclp1
68#endif /* DEBUG */
69
70#ifdef DEBUG
71 moveq #82, %d7 /* 'R' */
72 moveb %d7,0xfffff907 /* No absolute addresses */
73pclp3:
74 movew 0xfffff906, %d7
75 andw #0x2000, %d7
76 beq pclp3
77#endif /* DEBUG */
78 moveal #0x007ffff0, %ssp
79 moveal #_sbss, %a0
80 moveal #_ebss, %a1
81
82 /* Copy 0 to %a0 until %a0 >= %a1 */
83L1:
84 movel #0, %a0@+
85 cmpal %a0, %a1
86 bhi L1
87
88#ifdef DEBUG
89 moveq #67, %d7 /* 'C' */
90 jsr putc
91#endif /* DEBUG */
92
93 pea 0
94 pea env
95 pea %sp@(4)
96 pea 0
97
98#ifdef DEBUG
99 moveq #70, %d7 /* 'F' */
100 jsr putc
101#endif /* DEBUG */
102
103lp:
104 jsr start_kernel
105 jmp lp
106_exit:
107
108 jmp _exit
109
110__main:
111 /* nothing */
112 rts
113
114#ifdef DEBUG
115putc:
116 moveb %d7,0xfffff907
117pclp:
118 movew 0xfffff906, %d7
119 andw #0x2000, %d7
120 beq pclp
121 rts
122#endif /* DEBUG */
123
124 .data
125
126/*
127 * Set up the usable of RAM stuff. Size of RAM is determined then
128 * an initial stack set up at the end.
129 */
130.align 4
131_ramvec:
132.long 0
133_rambase:
134.long 0
135_ramstart:
136.long 0
137_ramend:
138.long 0
139
140env:
141 .long 0
diff --git a/arch/m68k/platform/68328/head-rom.S b/arch/m68k/platform/68328/head-rom.S
new file mode 100644
index 00000000000..6ec77d3ea0b
--- /dev/null
+++ b/arch/m68k/platform/68328/head-rom.S
@@ -0,0 +1,110 @@
1
2 .global _start
3 .global _stext
4
5 .global _rambase
6 .global _ramvec
7 .global _ramstart
8 .global _ramend
9
10#ifdef CONFIG_INIT_LCD
11 .global splash_bits
12#endif
13
14 .data
15
16/*
17 * Set up the usable of RAM stuff. Size of RAM is determined then
18 * an initial stack set up at the end.
19 */
20.align 4
21_ramvec:
22.long 0
23_rambase:
24.long 0
25_ramstart:
26.long 0
27_ramend:
28.long 0
29
30#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
31
32#ifdef CONFIG_INIT_LCD
33splash_bits:
34#include "bootlogo.rh"
35#endif
36
37 .text
38_start:
39_stext: movew #0x2700,%sr
40#ifdef CONFIG_INIT_LCD
41 movel #splash_bits, 0xfffffA00 /* LSSA */
42 moveb #0x28, 0xfffffA05 /* LVPW */
43 movew #0x280, 0xFFFFFa08 /* LXMAX */
44 movew #0x1df, 0xFFFFFa0a /* LYMAX */
45 moveb #0, 0xfffffa29 /* LBAR */
46 moveb #0, 0xfffffa25 /* LPXCD */
47 moveb #0x08, 0xFFFFFa20 /* LPICF */
48 moveb #0x01, 0xFFFFFA21 /* -ve pol */
49 moveb #0x81, 0xfffffA27 /* LCKCON */
50 movew #0xff00, 0xfffff412 /* LCD pins */
51#endif
52 moveal #RAMEND-CONFIG_MEMORY_RESERVE*0x100000 - 0x10, %sp
53 movew #32767, %d0 /* PLL settle wait loop */
541: subq #1, %d0
55 bne 1b
56
57 /* Copy data segment from ROM to RAM */
58 moveal #_etext, %a0
59 moveal #_sdata, %a1
60 moveal #_edata, %a2
61
62 /* Copy %a0 to %a1 until %a1 == %a2 */
631: movel %a0@+, %a1@+
64 cmpal %a1, %a2
65 bhi 1b
66
67 moveal #_sbss, %a0
68 moveal #_ebss, %a1
69 /* Copy 0 to %a0 until %a0 == %a1 */
70
711:
72 clrl %a0@+
73 cmpal %a0, %a1
74 bhi 1b
75
76 movel #_sdata, %d0
77 movel %d0, _rambase
78 movel #_ebss, %d0
79 movel %d0, _ramstart
80 movel #RAMEND-CONFIG_MEMORY_RESERVE*0x100000, %d0
81 movel %d0, _ramend
82 movel #CONFIG_VECTORBASE, %d0
83 movel %d0, _ramvec
84
85/*
86 * load the current task pointer and stack
87 */
88 lea init_thread_union, %a0
89 lea 0x2000(%a0), %sp
90
911: jsr start_kernel
92 bra 1b
93_exit:
94
95 jmp _exit
96
97
98putc:
99 moveb %d7,0xfffff907
1001:
101 movew 0xfffff906, %d7
102 andw #0x2000, %d7
103 beq 1b
104 rts
105
106 .data
107env:
108 .long 0
109 .text
110
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c
new file mode 100644
index 00000000000..4bd456531f9
--- /dev/null
+++ b/arch/m68k/platform/68328/ints.c
@@ -0,0 +1,188 @@
1/*
2 * linux/arch/m68knommu/platform/68328/ints.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive
6 * for more details.
7 *
8 * Copyright 1996 Roman Zippel
9 * Copyright 1999 D. Jeff Dionne <jeff@rt-control.com>
10 */
11
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <asm/traps.h>
18#include <asm/io.h>
19#include <asm/machdep.h>
20
21#if defined(CONFIG_M68328)
22#include <asm/MC68328.h>
23#elif defined(CONFIG_M68EZ328)
24#include <asm/MC68EZ328.h>
25#elif defined(CONFIG_M68VZ328)
26#include <asm/MC68VZ328.h>
27#endif
28
29/* assembler routines */
30asmlinkage void system_call(void);
31asmlinkage void buserr(void);
32asmlinkage void trap(void);
33asmlinkage void trap3(void);
34asmlinkage void trap4(void);
35asmlinkage void trap5(void);
36asmlinkage void trap6(void);
37asmlinkage void trap7(void);
38asmlinkage void trap8(void);
39asmlinkage void trap9(void);
40asmlinkage void trap10(void);
41asmlinkage void trap11(void);
42asmlinkage void trap12(void);
43asmlinkage void trap13(void);
44asmlinkage void trap14(void);
45asmlinkage void trap15(void);
46asmlinkage void trap33(void);
47asmlinkage void trap34(void);
48asmlinkage void trap35(void);
49asmlinkage void trap36(void);
50asmlinkage void trap37(void);
51asmlinkage void trap38(void);
52asmlinkage void trap39(void);
53asmlinkage void trap40(void);
54asmlinkage void trap41(void);
55asmlinkage void trap42(void);
56asmlinkage void trap43(void);
57asmlinkage void trap44(void);
58asmlinkage void trap45(void);
59asmlinkage void trap46(void);
60asmlinkage void trap47(void);
61asmlinkage irqreturn_t bad_interrupt(int, void *);
62asmlinkage irqreturn_t inthandler(void);
63asmlinkage irqreturn_t inthandler1(void);
64asmlinkage irqreturn_t inthandler2(void);
65asmlinkage irqreturn_t inthandler3(void);
66asmlinkage irqreturn_t inthandler4(void);
67asmlinkage irqreturn_t inthandler5(void);
68asmlinkage irqreturn_t inthandler6(void);
69asmlinkage irqreturn_t inthandler7(void);
70
71extern e_vector *_ramvec;
72
73/* The 68k family did not have a good way to determine the source
74 * of interrupts until later in the family. The EC000 core does
75 * not provide the vector number on the stack, we vector everything
76 * into one vector and look in the blasted mask register...
77 * This code is designed to be fast, almost constant time, not clean!
78 */
79void process_int(int vec, struct pt_regs *fp)
80{
81 int irq;
82 int mask;
83
84 unsigned long pend = ISR;
85
86 while (pend) {
87 if (pend & 0x0000ffff) {
88 if (pend & 0x000000ff) {
89 if (pend & 0x0000000f) {
90 mask = 0x00000001;
91 irq = 0;
92 } else {
93 mask = 0x00000010;
94 irq = 4;
95 }
96 } else {
97 if (pend & 0x00000f00) {
98 mask = 0x00000100;
99 irq = 8;
100 } else {
101 mask = 0x00001000;
102 irq = 12;
103 }
104 }
105 } else {
106 if (pend & 0x00ff0000) {
107 if (pend & 0x000f0000) {
108 mask = 0x00010000;
109 irq = 16;
110 } else {
111 mask = 0x00100000;
112 irq = 20;
113 }
114 } else {
115 if (pend & 0x0f000000) {
116 mask = 0x01000000;
117 irq = 24;
118 } else {
119 mask = 0x10000000;
120 irq = 28;
121 }
122 }
123 }
124
125 while (! (mask & pend)) {
126 mask <<=1;
127 irq++;
128 }
129
130 do_IRQ(irq, fp);
131 pend &= ~mask;
132 }
133}
134
135static void intc_irq_unmask(struct irq_data *d)
136{
137 IMR &= ~(1 << d->irq);
138}
139
140static void intc_irq_mask(struct irq_data *d)
141{
142 IMR |= (1 << d->irq);
143}
144
145static struct irq_chip intc_irq_chip = {
146 .name = "M68K-INTC",
147 .irq_mask = intc_irq_mask,
148 .irq_unmask = intc_irq_unmask,
149};
150
151/*
152 * This function should be called during kernel startup to initialize
153 * the machine vector table.
154 */
155void __init trap_init(void)
156{
157 int i;
158
159 /* set up the vectors */
160 for (i = 72; i < 256; ++i)
161 _ramvec[i] = (e_vector) bad_interrupt;
162
163 _ramvec[32] = system_call;
164
165 _ramvec[65] = (e_vector) inthandler1;
166 _ramvec[66] = (e_vector) inthandler2;
167 _ramvec[67] = (e_vector) inthandler3;
168 _ramvec[68] = (e_vector) inthandler4;
169 _ramvec[69] = (e_vector) inthandler5;
170 _ramvec[70] = (e_vector) inthandler6;
171 _ramvec[71] = (e_vector) inthandler7;
172}
173
174void __init init_IRQ(void)
175{
176 int i;
177
178 IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
179
180 /* turn off all interrupts */
181 IMR = ~0;
182
183 for (i = 0; (i < NR_IRQS); i++) {
184 irq_set_chip(i, &intc_irq_chip);
185 irq_set_handler(i, handle_level_irq);
186 }
187}
188
diff --git a/arch/m68k/platform/68328/romvec.S b/arch/m68k/platform/68328/romvec.S
new file mode 100644
index 00000000000..31084466eae
--- /dev/null
+++ b/arch/m68k/platform/68328/romvec.S
@@ -0,0 +1,35 @@
1/*
2 * linux/arch/m68knommu/platform/68328/romvec.S
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive
6 * for more details.
7 *
8 * Copyright 1996 Roman Zippel
9 * Copyright 1999 D. Jeff Dionne <jeff@rt-control.com>
10 * Copyright 2006 Greg Ungerer <gerg@snapgear.com>
11 */
12
13.global _start
14.global _buserr
15.global trap
16.global system_call
17
18.section .romvec
19
20e_vectors:
21.long CONFIG_RAMBASE+CONFIG_RAMSIZE-4, _start, buserr, trap
22.long trap, trap, trap, trap
23.long trap, trap, trap, trap
24.long trap, trap, trap, trap
25.long trap, trap, trap, trap
26.long trap, trap, trap, trap
27.long trap, trap, trap, trap
28.long trap, trap, trap, trap
29/* TRAP #0-15 */
30.long system_call, trap, trap, trap
31.long trap, trap, trap, trap
32.long trap, trap, trap, trap
33.long trap, trap, trap, trap
34.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
35
diff --git a/arch/m68k/platform/68328/timers.c b/arch/m68k/platform/68328/timers.c
new file mode 100644
index 00000000000..309f725995b
--- /dev/null
+++ b/arch/m68k/platform/68328/timers.c
@@ -0,0 +1,134 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/68328/timers.c
5 *
6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne
8 * Copyright (C) 2001 Georges Menie, Ken Desmet
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15/***************************************************************************/
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/clocksource.h>
23#include <asm/setup.h>
24#include <asm/system.h>
25#include <asm/pgtable.h>
26#include <asm/machdep.h>
27#include <asm/MC68VZ328.h>
28
29/***************************************************************************/
30
31#if defined(CONFIG_DRAGEN2)
32/* with a 33.16 MHz clock, this will give usec resolution to the time functions */
33#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK
34#define CLOCK_PRE 7
35#define TICKS_PER_JIFFY 41450
36
37#elif defined(CONFIG_XCOPILOT_BUGS)
38/*
39 * The only thing I know is that CLK32 is not available on Xcopilot
40 * I have little idea about what frequency SYSCLK has on Xcopilot.
41 * The values for prescaler and compare registers were simply
42 * taken from the original source
43 */
44#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK
45#define CLOCK_PRE 2
46#define TICKS_PER_JIFFY 0xd7e4
47
48#else
49/* default to using the 32Khz clock */
50#define CLOCK_SOURCE TCTL_CLKSOURCE_32KHZ
51#define CLOCK_PRE 31
52#define TICKS_PER_JIFFY 10
53#endif
54
55static u32 m68328_tick_cnt;
56
57/***************************************************************************/
58
59static irqreturn_t hw_tick(int irq, void *dummy)
60{
61 /* Reset Timer1 */
62 TSTAT &= 0;
63
64 m68328_tick_cnt += TICKS_PER_JIFFY;
65 return arch_timer_interrupt(irq, dummy);
66}
67
68/***************************************************************************/
69
70static struct irqaction m68328_timer_irq = {
71 .name = "timer",
72 .flags = IRQF_DISABLED | IRQF_TIMER,
73 .handler = hw_tick,
74};
75
76/***************************************************************************/
77
78static cycle_t m68328_read_clk(struct clocksource *cs)
79{
80 unsigned long flags;
81 u32 cycles;
82
83 local_irq_save(flags);
84 cycles = m68328_tick_cnt + TCN;
85 local_irq_restore(flags);
86
87 return cycles;
88}
89
90/***************************************************************************/
91
92static struct clocksource m68328_clk = {
93 .name = "timer",
94 .rating = 250,
95 .read = m68328_read_clk,
96 .shift = 20,
97 .mask = CLOCKSOURCE_MASK(32),
98 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
99};
100
101/***************************************************************************/
102
103void hw_timer_init(void)
104{
105 /* disable timer 1 */
106 TCTL = 0;
107
108 /* set ISR */
109 setup_irq(TMR_IRQ_NUM, &m68328_timer_irq);
110
111 /* Restart mode, Enable int, Set clock source */
112 TCTL = TCTL_OM | TCTL_IRQEN | CLOCK_SOURCE;
113 TPRER = CLOCK_PRE;
114 TCMP = TICKS_PER_JIFFY;
115
116 /* Enable timer 1 */
117 TCTL |= TCTL_TEN;
118 m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift);
119 clocksource_register(&m68328_clk);
120}
121
122/***************************************************************************/
123
124void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec)
125{
126 long now = RTCTIME;
127
128 *year = *mon = *day = 1;
129 *hour = (now >> 24) % 24;
130 *min = (now >> 16) % 60;
131 *sec = now % 60;
132}
133
134/***************************************************************************/
diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile
new file mode 100644
index 00000000000..ee97735a242
--- /dev/null
+++ b/arch/m68k/platform/68EZ328/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for arch/m68knommu/platform/68EZ328.
3#
4
5obj-y := config.o
6
7extra-y := bootlogo.rh
8
9$(obj)/bootlogo.rh: $(src)/bootlogo.h
10 perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \
11 > $(obj)/bootlogo.rh
diff --git a/arch/m68k/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68EZ328/bootlogo.h
new file mode 100644
index 00000000000..e842bdae583
--- /dev/null
+++ b/arch/m68k/platform/68EZ328/bootlogo.h
@@ -0,0 +1,3204 @@
1#define splash_width 640
2#define splash_height 480
3static unsigned char splash_bits[] = {
4 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
5 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
6 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
11 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
12 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
13 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
14 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
15 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
18 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
21 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
22 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
23 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
24 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
26 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
27 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
28 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
29 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
30 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
31 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
32 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
33 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
34 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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204 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
205 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00,
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224 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
225 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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229 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
230 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff,
231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00,
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244 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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251 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00,
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257 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
258 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00,
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264 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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271 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00,
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278 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00,
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284 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
285 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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304 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
305 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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311 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
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318 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
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325 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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998 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
999 0x00, 0x00, 0x00, 0xff, 0x09, 0x00, 0x00, 0x9b, 0x01, 0xc0, 0x00, 0x00,
1000 0xc6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1001 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1002 0x00, 0x00, 0x00, 0xc0, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1003 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xf8, 0x01, 0x00, 0x00, 0x00, 0x00,
1004 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00,
1005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
1006 0x00, 0x00, 0x00, 0x07, 0x32, 0x06, 0x18, 0x43, 0x00, 0x06, 0x00, 0x00,
1007 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1008 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
1009 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1010 0x00, 0xf0, 0xc1, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1011 0x02, 0x02, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x07,
1013 0x32, 0x06, 0x18, 0x43, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1014 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x00, 0x00, 0x00,
1016 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00,
1017 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x02, 0x10, 0xe0,
1018 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1019 0x00, 0x00, 0x00, 0x70, 0x08, 0x00, 0x00, 0x7b, 0x00, 0x30, 0x03, 0x0c,
1020 0x08, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1021 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1022 0x00, 0x00, 0x00, 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1023 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
1024 0x00, 0x00, 0x00, 0xe0, 0x07, 0x03, 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00,
1025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1026 0x09, 0x00, 0xc0, 0x84, 0x8d, 0x01, 0x80, 0x00, 0xc0, 0x06, 0x00, 0x00,
1027 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1029 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1030 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
1031 0xfd, 0x03, 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1032 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0xc0, 0x84,
1033 0x8d, 0x01, 0x80, 0x00, 0xc0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1034 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00,
1036 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00,
1037 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xfd, 0x03, 0xf0, 0x7f,
1038 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1039 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0xc0, 0x1b, 0x00, 0x30, 0x00, 0x40,
1040 0x08, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1041 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1042 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1043 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
1044 0x00, 0x00, 0x00, 0xff, 0xfc, 0x01, 0xf0, 0x3f, 0x00, 0x00, 0x00, 0x00,
1045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1046 0x08, 0x00, 0xc0, 0x1b, 0x00, 0x30, 0x00, 0x40, 0x08, 0x18, 0x00, 0x00,
1047 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1048 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1049 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
1050 0x07, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
1051 0xf8, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0xc0, 0x64,
1053 0x42, 0x06, 0x1b, 0x03, 0x00, 0x61, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
1054 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x80, 0x00, 0x00, 0x00,
1056 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0xc0, 0x00,
1057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x10, 0x00,
1058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1059 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0xc0, 0x64, 0x42, 0x06, 0x1b, 0x03,
1060 0x00, 0x61, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1061 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1062 0x00, 0x00, 0x00, 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1063 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00,
1064 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
1066 0x0f, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x80, 0x30, 0x08, 0x86, 0x00, 0x00,
1067 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1069 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1070 0xff, 0x3f, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
1071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x1b,
1073 0x00, 0x00, 0x80, 0x30, 0x08, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1074 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x00, 0x00, 0x00,
1076 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xc3, 0x03,
1077 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00,
1078 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1079 0x00, 0x00, 0x00, 0xfc, 0x0f, 0x00, 0xe0, 0x84, 0x31, 0x30, 0x04, 0x80,
1080 0xc1, 0x18, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1081 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1082 0x00, 0x00, 0x00, 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1083 0x00, 0x00, 0x00, 0x1c, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
1084 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1086 0x09, 0x00, 0xc0, 0x63, 0x02, 0x06, 0x00, 0x00, 0x00, 0x60, 0x6c, 0xfc,
1087 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1089 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
1090 0xe0, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1091 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x08, 0x00, 0xc0, 0x63,
1093 0x02, 0x06, 0x00, 0x00, 0x00, 0x60, 0x6c, 0xfc, 0xff, 0x03, 0x00, 0x00,
1094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
1096 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0xff, 0xff, 0x03,
1097 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1099 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0xe0, 0x1c, 0x40, 0x00, 0x1b, 0x4c,
1100 0x06, 0x81, 0x80, 0xfd, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1103 0x00, 0x00, 0x00, 0x70, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00,
1104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1106 0x00, 0x00, 0xe0, 0x1c, 0x40, 0x00, 0x1b, 0x4c, 0x06, 0x81, 0x80, 0xfd,
1107 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1109 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
1110 0x00, 0x80, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x09, 0x00, 0x20, 0x63,
1113 0x0c, 0x08, 0x80, 0x00, 0x30, 0x06, 0x0c, 0xfc, 0xff, 0x7f, 0x00, 0x00,
1114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00,
1116 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x30, 0x00,
1117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
1118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1119 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x20, 0x63, 0x0c, 0x08, 0x80, 0x00,
1120 0x30, 0x06, 0x0c, 0xfc, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1122 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1123 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0x00, 0x00, 0x00, 0x00,
1125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
1126 0x0f, 0x00, 0xd8, 0x84, 0x01, 0xc0, 0x00, 0x00, 0x06, 0x00, 0x80, 0xf1,
1127 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1129 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1131 0x00, 0x00, 0xe0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0xf8, 0x1b,
1133 0x40, 0x08, 0x84, 0x0c, 0xc0, 0x18, 0x13, 0xcc, 0xff, 0xff, 0x0f, 0x00,
1134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x00,
1136 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xe0, 0x7f,
1138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1139 0x00, 0x00, 0x00, 0xfc, 0x0f, 0x00, 0xf8, 0x1b, 0x40, 0x08, 0x84, 0x0c,
1140 0xc0, 0x18, 0x13, 0xcc, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
1141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1142 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1144 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0xf0, 0xe4, 0x00, 0x00, 0x00, 0x00,
1145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1146 0x09, 0x00, 0x38, 0x80, 0x01, 0x00, 0x18, 0x30, 0x06, 0x01, 0x00, 0xc0,
1147 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
1149 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1150 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1151 0x07, 0x00, 0x30, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x38, 0x80,
1153 0x01, 0x00, 0x18, 0x30, 0x06, 0x01, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x01,
1154 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1311 0x04, 0x00, 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x08, 0x00, 0xd9, 0x04,
1313 0x00, 0x08, 0x00, 0x80, 0xf9, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1314 0x00, 0xf0, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x1e, 0x00, 0x00,
1316 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0xfe, 0xff, 0x01,
1317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x20, 0x04, 0x00, 0x60, 0x00,
1318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1319 0x00, 0x00, 0x00, 0xc0, 0x09, 0x00, 0xd9, 0x04, 0x00, 0x08, 0x00, 0x80,
1320 0xf9, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff,
1321 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1322 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1323 0x00, 0x00, 0x00, 0x78, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00,
1324 0x00, 0x00, 0x80, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1326 0x0f, 0xc0, 0x27, 0x00, 0x30, 0xc0, 0x60, 0xb0, 0xff, 0x7f, 0x00, 0x00,
1327 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00,
1328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
1329 0x60, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1330 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41,
1331 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1332 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xc0, 0xde, 0x9b,
1333 0x8d, 0x01, 0x04, 0xc3, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1334 0x00, 0x80, 0xf1, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
1336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbc, 0x03, 0x00, 0xf0, 0x01,
1337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x07, 0x00, 0x00, 0x00,
1338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1339 0x00, 0x00, 0x00, 0x00, 0x08, 0xc0, 0xde, 0x9b, 0x8d, 0x01, 0x04, 0xc3,
1340 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xf1, 0xff,
1341 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1343 0x00, 0x00, 0x00, 0x3e, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
1344 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1346 0x00, 0xc0, 0x39, 0x04, 0x00, 0xc8, 0x00, 0xfc, 0xff, 0x07, 0x00, 0x00,
1347 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xf8, 0xff, 0x3f, 0x00, 0x00,
1348 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
1349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
1350 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff,
1351 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1352 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0xc0, 0x39, 0x04,
1353 0x00, 0xc8, 0x00, 0xfc, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1354 0x00, 0x00, 0xc6, 0xf8, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x40, 0x00, 0x00, 0x00,
1356 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00,
1357 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0x00, 0x00,
1358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1359 0x00, 0x00, 0x00, 0x1f, 0x00, 0xc0, 0xc7, 0x60, 0x42, 0x00, 0x60, 0xff,
1360 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1361 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1362 0x00, 0x00, 0x00, 0xf8, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1363 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1364 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f,
1366 0x00, 0xc0, 0xc7, 0x60, 0x42, 0x00, 0x60, 0xff, 0xff, 0x01, 0x00, 0x00,
1367 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0x00, 0x00,
1368 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
1369 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1370 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1372 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0xc0, 0xff, 0x07,
1373 0xb0, 0x09, 0xe4, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1374 0x00, 0x00, 0x30, 0x00, 0xfc, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
1375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00,
1376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00,
1377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1378 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1379 0x00, 0x00, 0x00, 0x0e, 0x00, 0xc0, 0xde, 0x78, 0x02, 0x00, 0xfb, 0xff,
1380 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1381 0x80, 0xff, 0x1f, 0xf8, 0xff, 0xff, 0x1f, 0xf0, 0xff, 0xff, 0x00, 0x00,
1382 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1383 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00,
1384 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1386 0x00, 0xc0, 0xde, 0x78, 0x02, 0x00, 0xfb, 0xff, 0xff, 0x00, 0x00, 0x00,
1387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 0xf8,
1388 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x08,
1389 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1390 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1392 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xc0, 0x3f, 0x07,
1393 0xb0, 0xc9, 0xf8, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1394 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1395 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1396 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x01,
1397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1399 0x00, 0x00, 0x00, 0x00, 0x08, 0xc0, 0x3f, 0x07, 0xb0, 0xc9, 0xf8, 0xff,
1400 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1401 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
1402 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1403 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00,
1404 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
1406 0x0f, 0x00, 0xe7, 0xfb, 0x43, 0x30, 0xf8, 0xff, 0x0f, 0x00, 0x00, 0x00,
1407 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff,
1408 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00,
1409 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1410 0x07, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1412 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x0f, 0x00, 0xe7, 0xfb,
1413 0x43, 0x30, 0xf8, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1414 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1415 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x08, 0x70, 0x00, 0x00, 0x00,
1416 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0xe0, 0x01,
1417 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1418 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1419 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0xfe, 0x1c, 0xb2, 0x0f, 0xe0, 0xff,
1420 0x07, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
1421 0x00, 0xc0, 0xff, 0xff, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1422 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1423 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00,
1424 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1426 0x0f, 0x00, 0xf8, 0xe7, 0xfd, 0x01, 0xe0, 0xff, 0x07, 0x00, 0xe0, 0xff,
1427 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0xe0,
1428 0xb1, 0x3f, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0xf8,
1429 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1430 0xf0, 0xc0, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
1431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0xf8, 0xe7,
1433 0xfd, 0x01, 0xe0, 0xff, 0x07, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, 0x00,
1434 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0xe0, 0xb1, 0x3f, 0x00, 0x00,
1435 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00,
1436 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x03,
1437 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00,
1438 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1439 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x80, 0xff,
1440 0x01, 0x00, 0xe0, 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1441 0x00, 0x00, 0x00, 0x98, 0x4f, 0x0e, 0x18, 0x00, 0xf8, 0xff, 0xff, 0xff,
1442 0x07, 0x00, 0x00, 0xf8, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1443 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00,
1444 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
1446 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0x03,
1447 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98,
1448 0x4f, 0x0e, 0xf8, 0x1f, 0xf6, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x08,
1449 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
1450 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1451 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0xf8, 0xff,
1453 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00,
1454 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xb1, 0x01, 0xff, 0x1f,
1455 0xf6, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
1456 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x1f, 0x00,
1457 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x07, 0x00, 0x00, 0x00,
1458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1459 0x00, 0x00, 0x00, 0x04, 0x08, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00,
1460 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1461 0x00, 0x00, 0x00, 0xf8, 0xb1, 0x01, 0xff, 0x7f, 0xc0, 0xff, 0xff, 0xff,
1462 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1463 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1464 0x00, 0x00, 0x80, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1466 0x0f, 0x00, 0xe0, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1467 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
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1470 0xff, 0xe3, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
1471 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1473 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00,
1474 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0xce, 0xff, 0x7f,
1475 0x00, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
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1482 0x3f, 0x00, 0x00, 0xe0, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1486 0x0f, 0x00, 0xc0, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1487 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0x1c,
1488 0x00, 0xc0, 0xff, 0x73, 0xc0, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0xf0,
1489 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
1490 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
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1492 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc0, 0xff,
1493 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x00, 0x00,
1494 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0x1c, 0x00, 0xc0, 0x7f, 0x1c,
1495 0x30, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00,
1496 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x78, 0x00,
1497 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x01, 0x00, 0x00,
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1499 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x00, 0x00,
1500 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
1501 0x00, 0x00, 0x38, 0x87, 0x31, 0x06, 0x7c, 0x1c, 0x30, 0xff, 0xff, 0xff,
1502 0xff, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1503 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00,
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1506 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1507 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x87,
1508 0x31, 0x06, 0xfc, 0x0f, 0xc8, 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x38,
1509 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
1510 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff,
1511 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1513 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x0f, 0x00,
1514 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xe6, 0x04, 0x00, 0x30, 0xe3, 0x0f,
1515 0xc8, 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
1516 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0xe0, 0x01,
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1520 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
1521 0x00, 0x30, 0xe6, 0x04, 0x00, 0x30, 0x03, 0x00, 0xf0, 0xff, 0xff, 0xff,
1522 0xff, 0x03, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1523 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00,
1524 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1526 0x07, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1527 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x1b,
1528 0x4c, 0x00, 0x04, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x10,
1529 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1530 0x01, 0x00, 0xf0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
1531 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1533 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00,
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1535 0xff, 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
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1541 0x00, 0x02, 0x07, 0x04, 0x00, 0x06, 0x78, 0xf3, 0xff, 0xff, 0xff, 0xff,
1542 0xff, 0x07, 0x00, 0xf8, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1546 0x08, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1547 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x3e, 0x04,
1548 0x02, 0x30, 0x60, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0xf8,
1549 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1552 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x00, 0xc0, 0xff,
1553 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00,
1554 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x3e, 0x04, 0x02, 0x30, 0xe0, 0xff,
1555 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00,
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1562 0xff, 0x07, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1566 0x08, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1567 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x04,
1568 0x40, 0x00, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x08,
1569 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1572 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0e, 0x00, 0x00, 0xff,
1573 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00,
1574 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x39, 0x67, 0x00, 0x06, 0xe0, 0xff,
1575 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
1576 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1582 0xff, 0x3f, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1584 0x00, 0x00, 0x18, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1586 0x0f, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1587 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x04,
1588 0x30, 0x00, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x08,
1589 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1590 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00,
1591 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1592 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x06, 0x00, 0x00, 0xff,
1593 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 0x00, 0x7e, 0x00,
1594 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x3e, 0x9b, 0x01, 0x30, 0xe0, 0xff,
1595 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x08, 0x60, 0x00, 0x00, 0x00,
1596 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1597 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x06, 0x00, 0x00, 0x00,
1598 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1599 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0x00,
1600 0x00, 0x00, 0x00, 0xc0, 0x1f, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00,
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1602 0xff, 0x3f, 0x00, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1603 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1604 0x00, 0x00, 0x1c, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1606 0x00, 0x02, 0x00, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1607 0x01, 0x00, 0xf0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x1c,
1608 0x0c, 0x06, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x38,
1609 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xe0,
1611 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1612 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0xff,
1613 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x00, 0xf0, 0x01,
1614 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x1c, 0x0c, 0x06, 0xfb, 0xff,
1615 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x68, 0x7c, 0x00, 0x00, 0x00,
1616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1618 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1619 0x00, 0x00, 0x00, 0xff, 0xff, 0x03, 0x00, 0xff, 0x3f, 0x00, 0x00, 0x00,
1620 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00,
1621 0x00, 0x00, 0x38, 0x18, 0x00, 0x00, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff,
1622 0xff, 0x3f, 0x00, 0xc0, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1781 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x03, 0x80, 0xff, 0xff, 0xff, 0xff,
1782 0x3f, 0x00, 0x00, 0x38, 0x06, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1783 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1784 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1785 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1786 0x0c, 0x00, 0x00, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1787 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
1788 0xff, 0xff, 0x03, 0xfc, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x38,
1789 0x1e, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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1792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0e, 0x00, 0x00, 0xff,
1793 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x03, 0xfc,
1795 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x38, 0xfc, 0x1f, 0x00, 0x00,
1796 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1797 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1798 0x00, 0x00, 0x00, 0x70, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1799 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff, 0x3f, 0x00, 0x00,
1800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1801 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1802 0x1f, 0x00, 0x00, 0x38, 0xf8, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1803 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1804 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
1805 0x80, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1806 0x0f, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1808 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x78,
1809 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1811 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xe0, 0x1f, 0x00, 0x00,
1812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x07, 0x00, 0x00, 0xff,
1813 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1814 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
1815 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0xf8, 0xc1, 0x07, 0x00, 0x00,
1816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1817 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1818 0x00, 0x00, 0x00, 0x60, 0xf8, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1819 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 0x00,
1820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00,
1821 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1822 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1823 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1824 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1825 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1826 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
1827 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xff, 0xff,
1828 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00,
1829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1831 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00,
1832 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc0, 0xff,
1833 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1834 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1835 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1837 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1838 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1839 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 0x00,
1840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1841 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1842 0x01, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1845 0xe0, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1846 0x08, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00,
1847 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x67,
1848 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0xf8,
1849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1851 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x13, 0x00, 0x00,
1852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0xc0, 0xff,
1853 0xff, 0xff, 0x1f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1854 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x67, 0xfe, 0xff, 0xff, 0xff,
1855 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00,
1856 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1857 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1858 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1859 0x00, 0x00, 0x00, 0xfc, 0x0f, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 0x03,
1860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1861 0xf0, 0xff, 0xff, 0x98, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
1862 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1865 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1866 0x0f, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x08, 0x00, 0x00, 0x00,
1867 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x98,
1868 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x70,
1869 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1871 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
1872 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0xf8, 0xff,
1873 0xff, 0xff, 0x7f, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1874 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x3f, 0xe7, 0xff, 0xff, 0xff, 0xff,
1875 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1876 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1877 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1878 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1879 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0xff, 0xfc, 0xff, 0xff, 0xff, 0x00,
1880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1881 0xff, 0xff, 0x3f, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
1882 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1883 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1884 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
1886 0x00, 0xc0, 0xff, 0x67, 0x8c, 0xf9, 0xfb, 0x73, 0x00, 0x67, 0x10, 0x00,
1887 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xf8,
1888 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x80,
1889 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1890 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1891 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1892 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0xc0, 0xff, 0x67,
1893 0x8c, 0xf9, 0xfb, 0x73, 0x00, 0x67, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
1894 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 0xe7, 0xff, 0xff, 0xff, 0xff,
1895 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x00,
1896 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1897 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1898 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1899 0x00, 0x00, 0x00, 0x03, 0x00, 0xc0, 0x27, 0xfc, 0x73, 0xc6, 0x1c, 0x8c,
1900 0x37, 0x80, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff,
1901 0xff, 0xff, 0x1f, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00,
1902 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1903 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1904 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
1906 0x00, 0xc0, 0x27, 0xfc, 0x73, 0xc6, 0x1c, 0x8c, 0x37, 0x80, 0x0c, 0x00,
1907 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xfc,
1908 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1909 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1912 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0xc0, 0xfe, 0x03,
1913 0x8c, 0x09, 0xe3, 0x73, 0xc8, 0x06, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
1914 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
1915 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00,
1916 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1917 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1918 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1919 0x00, 0x00, 0x00, 0xff, 0x0f, 0xc0, 0xfe, 0x03, 0x8c, 0x09, 0xe3, 0x73,
1920 0xc8, 0x06, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff,
1921 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00,
1922 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1923 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1924 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1926 0x0f, 0xc0, 0x27, 0xe7, 0x31, 0x36, 0x04, 0x8c, 0x01, 0x60, 0x03, 0x00,
1927 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1928 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
1929 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1930 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1932 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, 0xc0, 0xde, 0x18,
1933 0x42, 0xc0, 0x98, 0x30, 0x08, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
1934 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00,
1935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00,
1936 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1937 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1938 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
1939 0x00, 0x00, 0x00, 0xff, 0x0f, 0xc0, 0xde, 0x18, 0x42, 0xc0, 0x98, 0x30,
1940 0x08, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff,
1941 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1942 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1943 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1944 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1945 0x02, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1946 0x00, 0xc0, 0x27, 0x63, 0x00, 0x08, 0x63, 0x03, 0x06, 0x60, 0x10, 0x00,
1947 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1948 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1949 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1950 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1951 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 0x00,
1952 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xc0, 0x27, 0x63,
1953 0x00, 0x08, 0x63, 0x03, 0x06, 0x60, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
1954 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00,
1955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x00,
1956 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1958 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
1959 0x00, 0x00, 0x00, 0x00, 0x08, 0xc0, 0xd9, 0x04, 0xb2, 0x01, 0x00, 0xb0,
1960 0x31, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf9, 0xff,
1961 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1962 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1963 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1964 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1965 0xfe, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1966 0x08, 0xc0, 0xd9, 0x04, 0xb2, 0x01, 0x00, 0xb0, 0x31, 0x19, 0x03, 0x00,
1967 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x07,
1968 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1969 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1970 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1971 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, 0x00,
1972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0c, 0xc0, 0x1e, 0x63,
1973 0x00, 0x30, 0x04, 0x03, 0xc8, 0x60, 0x00, 0x0e, 0x00, 0x00, 0xfc, 0xff,
1974 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00,
1975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1976 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1978 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
1979 0x00, 0x00, 0x00, 0x03, 0x0e, 0xc0, 0xe1, 0x18, 0x80, 0x01, 0x60, 0xb0,
1980 0x01, 0xe7, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1981 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1982 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1985 0x02, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
1986 0x0f, 0xc0, 0xe1, 0x18, 0x80, 0x01, 0x60, 0xb0, 0x01, 0xe7, 0xf3, 0xff,
1987 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00,
1988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
1989 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x04, 0x00,
1992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8d, 0x0f, 0xc0, 0x1e, 0x03,
1993 0x02, 0x08, 0x04, 0x00, 0xc8, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1994 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
1995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00,
1996 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1997 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1998 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
1999 0x00, 0x00, 0x00, 0xd8, 0x0f, 0xc0, 0x1e, 0x03, 0x02, 0x08, 0x04, 0x00,
2000 0xc8, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2001 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2002 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2003 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2004 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2005 0xc0, 0x0f, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2006 0x0b, 0x00, 0x21, 0x64, 0x40, 0xc0, 0x00, 0xb3, 0xf1, 0xfe, 0xff, 0xff,
2007 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00,
2008 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2009 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2011 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xfb, 0x07, 0x00,
2012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x21, 0x64,
2013 0x40, 0xc0, 0x00, 0xb3, 0xf1, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2014 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2016 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2017 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2018 0x00, 0x00, 0x00, 0x00, 0xfc, 0xfb, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
2019 0x00, 0x00, 0x00, 0xfd, 0x00, 0xc0, 0xdf, 0x00, 0x00, 0x06, 0x60, 0x00,
2020 0x0e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2021 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2023 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2024 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2025 0xfe, 0xf9, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbf,
2026 0x01, 0xc0, 0xdf, 0x00, 0x00, 0x06, 0x60, 0x00, 0x0e, 0xff, 0xff, 0xff,
2027 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00,
2028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2029 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2031 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0xf0, 0x03, 0x00,
2032 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x0b, 0xc0, 0xc0, 0x84,
2033 0x31, 0xc0, 0x00, 0x4c, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2034 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x83, 0x07, 0x00, 0x00,
2036 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2037 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2038 0x00, 0x00, 0x00, 0x00, 0x1e, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
2039 0x00, 0x00, 0x00, 0x0f, 0x0e, 0xc0, 0x3f, 0x18, 0x00, 0x06, 0x84, 0x80,
2040 0x09, 0xff, 0xff, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2041 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2042 0x00, 0x00, 0x00, 0xf0, 0xc3, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2043 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2044 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2045 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
2046 0x0c, 0xc0, 0x3f, 0x18, 0x00, 0x06, 0x84, 0x80, 0x09, 0xff, 0xff, 0x3f,
2047 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00,
2048 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
2049 0xc1, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
2052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xc0, 0xc1, 0x03,
2053 0x4c, 0x00, 0x00, 0x30, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2054 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x90, 0x13, 0x00, 0x00,
2056 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2058 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2059 0x00, 0x00, 0x00, 0x01, 0x08, 0xc0, 0xc1, 0x03, 0x4c, 0x00, 0x00, 0x30,
2060 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2061 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2062 0x00, 0x00, 0x00, 0x08, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2066 0x00, 0xc0, 0x3f, 0x98, 0x01, 0x08, 0x1b, 0x43, 0xc8, 0xff, 0xff, 0xff,
2067 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00,
2068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2069 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0x98,
2073 0x01, 0x08, 0x1b, 0x43, 0xc8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2074 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x38, 0x18, 0x00, 0x00,
2076 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2077 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2078 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
2079 0x00, 0x00, 0x00, 0x0e, 0x00, 0xc0, 0xc6, 0x03, 0x40, 0x00, 0x00, 0x80,
2080 0x31, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
2081 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2082 0x00, 0x00, 0x00, 0xf8, 0xef, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2083 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2084 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2085 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f,
2086 0x00, 0x00, 0x3f, 0x18, 0x0c, 0x30, 0x60, 0x0c, 0xce, 0xff, 0xff, 0xff,
2087 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
2088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2089 0xef, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2090 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2091 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00,
2092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x3f, 0x18,
2093 0x0c, 0x30, 0x60, 0x0c, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2094 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xc7, 0x0f, 0x00, 0x00,
2096 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2097 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
2099 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0xde, 0x63, 0x40, 0x06, 0x03, 0x30,
2100 0x30, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
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2126 0x03, 0x00, 0xe0, 0x1b, 0x0c, 0x08, 0x18, 0x40, 0x30, 0xfe, 0xff, 0xff,
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2128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2129 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0xc0, 0x84,
2133 0x81, 0x01, 0x03, 0x0c, 0xc6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2134 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2139 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0xc0, 0x84, 0x81, 0x01, 0x03, 0x0c,
2140 0xc6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00,
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2146 0x0e, 0x00, 0x00, 0x1b, 0x0c, 0x30, 0x80, 0x00, 0x30, 0xf8, 0xff, 0xff,
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2154 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2167 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2173 0x01, 0x08, 0x60, 0x0c, 0x06, 0x86, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff,
2174 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2186 0x07, 0x00, 0x00, 0x18, 0x0c, 0xc0, 0x00, 0x00, 0xc0, 0x00, 0xfc, 0xff,
2187 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2189 0x1f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2193 0x01, 0x06, 0x00, 0x30, 0x06, 0x86, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
2194 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2198 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2199 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0xe0, 0x01, 0x06, 0x00, 0x30,
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2205 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2206 0x00, 0x00, 0x00, 0x60, 0x30, 0x00, 0x63, 0x03, 0x30, 0x00, 0xe0, 0xff,
2207 0xff, 0xff, 0xff, 0x8f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2213 0x30, 0x00, 0x63, 0x03, 0x30, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0x0f,
2214 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2220 0x00, 0x06, 0x83, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00,
2221 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2222 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2223 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2224 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2225 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2226 0x08, 0x00, 0x00, 0x80, 0x83, 0x09, 0x18, 0x00, 0x00, 0x06, 0x83, 0xff,
2227 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2228 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2229 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2230 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2231 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00,
2232 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0x00,
2233 0x00, 0xc0, 0x00, 0x8c, 0xc9, 0x60, 0x00, 0xfe, 0xff, 0xff, 0x01, 0x00,
2234 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2237 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2238 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2239 0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x8e, 0x01, 0x84, 0x40,
2240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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2245 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2246 0x0f, 0x00, 0x00, 0x00, 0x8e, 0x01, 0x84, 0x40, 0x00, 0x00, 0x00, 0x00,
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2251 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00,
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3187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3204 };
diff --git a/arch/m68k/platform/68EZ328/config.c b/arch/m68k/platform/68EZ328/config.c
new file mode 100644
index 00000000000..1be1a16f689
--- /dev/null
+++ b/arch/m68k/platform/68EZ328/config.c
@@ -0,0 +1,76 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/68EZ328/config.c
5 *
6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive
11 * for more details.
12 */
13
14/***************************************************************************/
15
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <asm/system.h>
19#include <asm/pgtable.h>
20#include <asm/machdep.h>
21#include <asm/MC68EZ328.h>
22#ifdef CONFIG_UCSIMM
23#include <asm/bootstd.h>
24#endif
25
26/***************************************************************************/
27
28void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
29
30/***************************************************************************/
31
32void m68ez328_reset(void)
33{
34 local_irq_disable();
35 asm volatile (
36 "moveal #0x10c00000, %a0;\n"
37 "moveb #0, 0xFFFFF300;\n"
38 "moveal 0(%a0), %sp;\n"
39 "moveal 4(%a0), %a0;\n"
40 "jmp (%a0);\n"
41 );
42}
43
44/***************************************************************************/
45
46unsigned char *cs8900a_hwaddr;
47static int errno;
48
49#ifdef CONFIG_UCSIMM
50_bsc0(char *, getserialnum)
51_bsc1(unsigned char *, gethwaddr, int, a)
52_bsc1(char *, getbenv, char *, a)
53#endif
54
55void config_BSP(char *command, int len)
56{
57 unsigned char *p;
58
59 printk(KERN_INFO "\n68EZ328 DragonBallEZ support (C) 1999 Rt-Control, Inc\n");
60
61#ifdef CONFIG_UCSIMM
62 printk(KERN_INFO "uCsimm serial string [%s]\n",getserialnum());
63 p = cs8900a_hwaddr = gethwaddr(0);
64 printk(KERN_INFO "uCsimm hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
65 p[0], p[1], p[2], p[3], p[4], p[5]);
66
67 p = getbenv("APPEND");
68 if (p) strcpy(p,command);
69 else command[0] = 0;
70#endif
71
72 mach_gettod = m68328_timer_gettod;
73 mach_reset = m68ez328_reset;
74}
75
76/***************************************************************************/
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
new file mode 100644
index 00000000000..447ffa0fd7c
--- /dev/null
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -0,0 +1,16 @@
1#
2# Makefile for arch/m68knommu/platform/68VZ328.
3#
4
5obj-y := config.o
6logo-$(UCDIMM) := bootlogo.rh
7logo-$(DRAGEN2) := screen.h
8extra-y := $(logo-y)
9
10$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h
11 perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh
12
13$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
14 perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
15
16clean-files := $(obj)/screen.h $(obj)/bootlogo.rh
diff --git a/arch/m68k/platform/68VZ328/config.c b/arch/m68k/platform/68VZ328/config.c
new file mode 100644
index 00000000000..eabaabe8af3
--- /dev/null
+++ b/arch/m68k/platform/68VZ328/config.c
@@ -0,0 +1,188 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/68VZ328/config.c
5 *
6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne
8 * Copyright (C) 2001 Georges Menie, Ken Desmet
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15/***************************************************************************/
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/kd.h>
20#include <linux/netdevice.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23
24#include <asm/system.h>
25#include <asm/pgtable.h>
26#include <asm/machdep.h>
27#include <asm/MC68VZ328.h>
28#include <asm/bootstd.h>
29
30#ifdef CONFIG_INIT_LCD
31#include "bootlogo.h"
32#endif
33
34/***************************************************************************/
35
36void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
37
38/***************************************************************************/
39/* Init Drangon Engine hardware */
40/***************************************************************************/
41#if defined(CONFIG_DRAGEN2)
42
43static void m68vz328_reset(void)
44{
45 local_irq_disable();
46
47#ifdef CONFIG_INIT_LCD
48 PBDATA |= 0x20; /* disable CCFL light */
49 PKDATA |= 0x4; /* disable LCD controller */
50 LCKCON = 0;
51#endif
52
53 __asm__ __volatile__(
54 "reset\n\t"
55 "moveal #0x04000000, %a0\n\t"
56 "moveal 0(%a0), %sp\n\t"
57 "moveal 4(%a0), %a0\n\t"
58 "jmp (%a0)"
59 );
60}
61
62static void init_hardware(char *command, int size)
63{
64#ifdef CONFIG_DIRECT_IO_ACCESS
65 SCR = 0x10; /* allow user access to internal registers */
66#endif
67
68 /* CSGB Init */
69 CSGBB = 0x4000;
70 CSB = 0x1a1;
71
72 /* CS8900 init */
73 /* PK3: hardware sleep function pin, active low */
74 PKSEL |= PK(3); /* select pin as I/O */
75 PKDIR |= PK(3); /* select pin as output */
76 PKDATA |= PK(3); /* set pin high */
77
78 /* PF5: hardware reset function pin, active high */
79 PFSEL |= PF(5); /* select pin as I/O */
80 PFDIR |= PF(5); /* select pin as output */
81 PFDATA &= ~PF(5); /* set pin low */
82
83 /* cs8900 hardware reset */
84 PFDATA |= PF(5);
85 { int i; for (i = 0; i < 32000; ++i); }
86 PFDATA &= ~PF(5);
87
88 /* INT1 enable (cs8900 IRQ) */
89 PDPOL &= ~PD(1); /* active high signal */
90 PDIQEG &= ~PD(1);
91 PDIRQEN |= PD(1); /* IRQ enabled */
92
93#ifdef CONFIG_INIT_LCD
94 /* initialize LCD controller */
95 LSSA = (long) screen_bits;
96 LVPW = 0x14;
97 LXMAX = 0x140;
98 LYMAX = 0xef;
99 LRRA = 0;
100 LPXCD = 3;
101 LPICF = 0x08;
102 LPOLCF = 0;
103 LCKCON = 0x80;
104 PCPDEN = 0xff;
105 PCSEL = 0;
106
107 /* Enable LCD controller */
108 PKDIR |= 0x4;
109 PKSEL |= 0x4;
110 PKDATA &= ~0x4;
111
112 /* Enable CCFL backlighting circuit */
113 PBDIR |= 0x20;
114 PBSEL |= 0x20;
115 PBDATA &= ~0x20;
116
117 /* contrast control register */
118 PFDIR |= 0x1;
119 PFSEL &= ~0x1;
120 PWMR = 0x037F;
121#endif
122}
123
124/***************************************************************************/
125/* Init RT-Control uCdimm hardware */
126/***************************************************************************/
127#elif defined(CONFIG_UCDIMM)
128
129static void m68vz328_reset(void)
130{
131 local_irq_disable();
132 asm volatile (
133 "moveal #0x10c00000, %a0;\n\t"
134 "moveb #0, 0xFFFFF300;\n\t"
135 "moveal 0(%a0), %sp;\n\t"
136 "moveal 4(%a0), %a0;\n\t"
137 "jmp (%a0);\n"
138 );
139}
140
141unsigned char *cs8900a_hwaddr;
142static int errno;
143
144_bsc0(char *, getserialnum)
145_bsc1(unsigned char *, gethwaddr, int, a)
146_bsc1(char *, getbenv, char *, a)
147
148static void init_hardware(char *command, int size)
149{
150 char *p;
151
152 printk(KERN_INFO "uCdimm serial string [%s]\n", getserialnum());
153 p = cs8900a_hwaddr = gethwaddr(0);
154 printk(KERN_INFO "uCdimm hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
155 p[0], p[1], p[2], p[3], p[4], p[5]);
156 p = getbenv("APPEND");
157 if (p)
158 strcpy(p, command);
159 else
160 command[0] = 0;
161}
162
163/***************************************************************************/
164#else
165
166static void m68vz328_reset(void)
167{
168}
169
170static void init_hardware(char *command, int size)
171{
172}
173
174/***************************************************************************/
175#endif
176/***************************************************************************/
177
178void config_BSP(char *command, int size)
179{
180 printk(KERN_INFO "68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n");
181
182 init_hardware(command, size);
183
184 mach_gettod = m68328_timer_gettod;
185 mach_reset = m68vz328_reset;
186}
187
188/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c
new file mode 100644
index 00000000000..8c62b825939
--- /dev/null
+++ b/arch/m68k/platform/coldfire/pinmux.c
@@ -0,0 +1,28 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/pinmux.h>
20
21int mcf_pinmux_request(unsigned pinmux, unsigned func)
22{
23 return 0;
24}
25
26void mcf_pinmux_release(unsigned pinmux, unsigned func)
27{
28}
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-12 02:27:20 -0500