blackfin: twi: move twi bit mask macro to twi head file

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>

1 files changed, 0 insertions, 76 deletions

diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
index d27f81d6c4b..f5aaf0573c0 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -1746,80 +1746,4 @@
 #define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
 #define BGSTAT                  0x00000020 /* Bus granted */
 
-
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
-#else
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
-#endif /* _MISRA_RULES */
-
-/* TWIx_PRESCALE Masks                                                           */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA         0x0080          /* TWI Enable            */
-#define SCCB            0x0200          /* SCCB Compatibility Enable */
-
-/* TWIx_SLAVE_CTRL Masks                                                                 */
-#define SEN                     0x0001          /* Slave Enable          */
-#define SADD_LEN        0x0002          /* Slave Address Length */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
-
-/* TWIx_SLAVE_STAT Masks                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator */
-
-/* TWIx_MASTER_CTRL Masks                                                */
-#define MEN                     0x0001          /* Master Mode Enable */
-#define MADD_LEN        0x0002          /* Master Address Length */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs */
-#define STOP            0x0010          /* Issue Stop Condition */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer */
-#define SDAOVR          0x4000          /* Serial Data Override */
-#define SCLOVR          0x8000          /* Serial Clock Override */
-
-/* TWIx_MASTER_STAT Masks                                                        */
-#define MPROG           0x0001          /* Master Transfer In Progress */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK            0x0004          /* Address Not Acknowledged */
-#define DNAK            0x0008          /* Data Not Acknowledged */
-#define BUFRDERR        0x0010          /* Buffer Read Error */
-#define BUFWRERR        0x0020          /* Buffer Write Error */
-#define SDASEN          0x0040          /* Serial Data Sense */
-#define SCLSEN          0x0080          /* Serial Clock Sense */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator */
-
-/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
-#define SINIT           0x0001          /* Slave Transfer Initiated */
-#define SCOMP           0x0002          /* Slave Transfer Complete */
-#define SERR            0x0004          /* Slave Transfer Error */
-#define SOVF            0x0008          /* Slave Overflow */
-#define MCOMP           0x0010          /* Master Transfer Complete */
-#define MERR            0x0020          /* Master Transfer Error */
-#define XMTSERV         0x0040          /* Transmit FIFO Service */
-#define RCVSERV         0x0080          /* Receive FIFO Service */
-
-/* TWIx_FIFO_CTL Masks                                   */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
-
-/* TWIx_FIFO_STAT Masks                                                          */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
-
 #endif