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authorSonic Zhang <sonic.zhang@analog.com>2011-11-24 04:40:07 -0500
committerBob Liu <lliubbo@gmail.com>2012-05-21 02:54:21 -0400
commitc55c89e939f2a0a83d5c61462be554d5d2408178 (patch)
treef3fe0781b6bf66acb3fb1a321ff446c240afeb73
parent2879bb30d788bb3841e2f1675ea7af5204eb171c (diff)
blackfin: twi: move twi bit mask macro to twi head file
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h70
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h71
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h71
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h69
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF538.h76
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h109
6 files changed, 70 insertions, 396 deletions
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index e767d649dfc..74d10237f70 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -42,4 +42,74 @@ struct bfin_twi_regs {
42 42
43#undef __BFP 43#undef __BFP
44 44
45/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
46/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
47#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
48#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
49
50/* TWI_PRESCALE Masks */
51#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
52#define TWI_ENA 0x0080 /* TWI Enable */
53#define SCCB 0x0200 /* SCCB Compatibility Enable */
54
55/* TWI_SLAVE_CTL Masks */
56#define SEN 0x0001 /* Slave Enable */
57#define SADD_LEN 0x0002 /* Slave Address Length */
58#define STDVAL 0x0004 /* Slave Transmit Data Valid */
59#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
60#define GEN 0x0010 /* General Call Address Matching Enabled */
61
62/* TWI_SLAVE_STAT Masks */
63#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
64#define GCALL 0x0002 /* General Call Indicator */
65
66/* TWI_MASTER_CTL Masks */
67#define MEN 0x0001 /* Master Mode Enable */
68#define MADD_LEN 0x0002 /* Master Address Length */
69#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
70#define FAST 0x0008 /* Use Fast Mode Timing Specs */
71#define STOP 0x0010 /* Issue Stop Condition */
72#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
73#define DCNT 0x3FC0 /* Data Bytes To Transfer */
74#define SDAOVR 0x4000 /* Serial Data Override */
75#define SCLOVR 0x8000 /* Serial Clock Override */
76
77/* TWI_MASTER_STAT Masks */
78#define MPROG 0x0001 /* Master Transfer In Progress */
79#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
80#define ANAK 0x0004 /* Address Not Acknowledged */
81#define DNAK 0x0008 /* Data Not Acknowledged */
82#define BUFRDERR 0x0010 /* Buffer Read Error */
83#define BUFWRERR 0x0020 /* Buffer Write Error */
84#define SDASEN 0x0040 /* Serial Data Sense */
85#define SCLSEN 0x0080 /* Serial Clock Sense */
86#define BUSBUSY 0x0100 /* Bus Busy Indicator */
87
88/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
89#define SINIT 0x0001 /* Slave Transfer Initiated */
90#define SCOMP 0x0002 /* Slave Transfer Complete */
91#define SERR 0x0004 /* Slave Transfer Error */
92#define SOVF 0x0008 /* Slave Overflow */
93#define MCOMP 0x0010 /* Master Transfer Complete */
94#define MERR 0x0020 /* Master Transfer Error */
95#define XMTSERV 0x0040 /* Transmit FIFO Service */
96#define RCVSERV 0x0080 /* Receive FIFO Service */
97
98/* TWI_FIFO_CTRL Masks */
99#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
100#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
101#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
102#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
103
104/* TWI_FIFO_STAT Masks */
105#define XMTSTAT 0x0003 /* Transmit FIFO Status */
106#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
107#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
108#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
109
110#define RCVSTAT 0x000C /* Receive FIFO Status */
111#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
112#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
113#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
114
45#endif 115#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 729704078cd..a818bb15cf0 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1083,77 +1083,6 @@
1083#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1083#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1084 1084
1085 1085
1086/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1087/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1088#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1089#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1090
1091/* TWI_PRESCALE Masks */
1092#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1093#define TWI_ENA 0x0080 /* TWI Enable */
1094#define SCCB 0x0200 /* SCCB Compatibility Enable */
1095
1096/* TWI_SLAVE_CTL Masks */
1097#define SEN 0x0001 /* Slave Enable */
1098#define SADD_LEN 0x0002 /* Slave Address Length */
1099#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1100#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1101#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1102
1103/* TWI_SLAVE_STAT Masks */
1104#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1105#define GCALL 0x0002 /* General Call Indicator */
1106
1107/* TWI_MASTER_CTL Masks */
1108#define MEN 0x0001 /* Master Mode Enable */
1109#define MADD_LEN 0x0002 /* Master Address Length */
1110#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1111#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1112#define STOP 0x0010 /* Issue Stop Condition */
1113#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1114#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1115#define SDAOVR 0x4000 /* Serial Data Override */
1116#define SCLOVR 0x8000 /* Serial Clock Override */
1117
1118/* TWI_MASTER_STAT Masks */
1119#define MPROG 0x0001 /* Master Transfer In Progress */
1120#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1121#define ANAK 0x0004 /* Address Not Acknowledged */
1122#define DNAK 0x0008 /* Data Not Acknowledged */
1123#define BUFRDERR 0x0010 /* Buffer Read Error */
1124#define BUFWRERR 0x0020 /* Buffer Write Error */
1125#define SDASEN 0x0040 /* Serial Data Sense */
1126#define SCLSEN 0x0080 /* Serial Clock Sense */
1127#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1128
1129/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1130#define SINIT 0x0001 /* Slave Transfer Initiated */
1131#define SCOMP 0x0002 /* Slave Transfer Complete */
1132#define SERR 0x0004 /* Slave Transfer Error */
1133#define SOVF 0x0008 /* Slave Overflow */
1134#define MCOMP 0x0010 /* Master Transfer Complete */
1135#define MERR 0x0020 /* Master Transfer Error */
1136#define XMTSERV 0x0040 /* Transmit FIFO Service */
1137#define RCVSERV 0x0080 /* Receive FIFO Service */
1138
1139/* TWI_FIFO_CTRL Masks */
1140#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1141#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1142#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1143#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1144
1145/* TWI_FIFO_STAT Masks */
1146#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1147#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1148#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1149#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1150
1151#define RCVSTAT 0x000C /* Receive FIFO Status */
1152#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1153#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1154#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1155
1156
1157/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1086/* ******************* PIN CONTROL REGISTER MASKS ************************/
1158/* PORT_MUX Masks */ 1087/* PORT_MUX Masks */
1159#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ 1088#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 37d353a1972..e8fdacb8c64 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1084,77 +1084,6 @@
1084#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1084#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1085 1085
1086 1086
1087/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1088/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1089#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1090#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1091
1092/* TWI_PRESCALE Masks */
1093#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1094#define TWI_ENA 0x0080 /* TWI Enable */
1095#define SCCB 0x0200 /* SCCB Compatibility Enable */
1096
1097/* TWI_SLAVE_CTL Masks */
1098#define SEN 0x0001 /* Slave Enable */
1099#define SADD_LEN 0x0002 /* Slave Address Length */
1100#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1101#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1102#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1103
1104/* TWI_SLAVE_STAT Masks */
1105#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1106#define GCALL 0x0002 /* General Call Indicator */
1107
1108/* TWI_MASTER_CTL Masks */
1109#define MEN 0x0001 /* Master Mode Enable */
1110#define MADD_LEN 0x0002 /* Master Address Length */
1111#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1112#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1113#define STOP 0x0010 /* Issue Stop Condition */
1114#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1115#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1116#define SDAOVR 0x4000 /* Serial Data Override */
1117#define SCLOVR 0x8000 /* Serial Clock Override */
1118
1119/* TWI_MASTER_STAT Masks */
1120#define MPROG 0x0001 /* Master Transfer In Progress */
1121#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1122#define ANAK 0x0004 /* Address Not Acknowledged */
1123#define DNAK 0x0008 /* Data Not Acknowledged */
1124#define BUFRDERR 0x0010 /* Buffer Read Error */
1125#define BUFWRERR 0x0020 /* Buffer Write Error */
1126#define SDASEN 0x0040 /* Serial Data Sense */
1127#define SCLSEN 0x0080 /* Serial Clock Sense */
1128#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1129
1130/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1131#define SINIT 0x0001 /* Slave Transfer Initiated */
1132#define SCOMP 0x0002 /* Slave Transfer Complete */
1133#define SERR 0x0004 /* Slave Transfer Error */
1134#define SOVF 0x0008 /* Slave Overflow */
1135#define MCOMP 0x0010 /* Master Transfer Complete */
1136#define MERR 0x0020 /* Master Transfer Error */
1137#define XMTSERV 0x0040 /* Transmit FIFO Service */
1138#define RCVSERV 0x0080 /* Receive FIFO Service */
1139
1140/* TWI_FIFO_CTRL Masks */
1141#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1142#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1143#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1144#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1145
1146/* TWI_FIFO_STAT Masks */
1147#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1148#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1149#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1150#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1151
1152#define RCVSTAT 0x000C /* Receive FIFO Status */
1153#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1154#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1155#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1156
1157
1158/* Omit CAN masks from defBF534.h */ 1087/* Omit CAN masks from defBF534.h */
1159 1088
1160/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1089/* ******************* PIN CONTROL REGISTER MASKS ************************/
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 4a031dde173..d0deb66e6e8 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1403,75 +1403,6 @@
1403#define ERR_DET 0x4000 /* Error Detected Indicator */ 1403#define ERR_DET 0x4000 /* Error Detected Indicator */
1404#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1404#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1405 1405
1406/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1407/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1408#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1409#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1410
1411/* TWI_PRESCALE Masks */
1412#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1413#define TWI_ENA 0x0080 /* TWI Enable */
1414#define SCCB 0x0200 /* SCCB Compatibility Enable */
1415
1416/* TWI_SLAVE_CTL Masks */
1417#define SEN 0x0001 /* Slave Enable */
1418#define SADD_LEN 0x0002 /* Slave Address Length */
1419#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1420#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1421#define GEN 0x0010 /* General Call Address Matching Enabled */
1422
1423/* TWI_SLAVE_STAT Masks */
1424#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1425#define GCALL 0x0002 /* General Call Indicator */
1426
1427/* TWI_MASTER_CTL Masks */
1428#define MEN 0x0001 /* Master Mode Enable */
1429#define MADD_LEN 0x0002 /* Master Address Length */
1430#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1431#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1432#define STOP 0x0010 /* Issue Stop Condition */
1433#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1434#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1435#define SDAOVR 0x4000 /* Serial Data Override */
1436#define SCLOVR 0x8000 /* Serial Clock Override */
1437
1438/* TWI_MASTER_STAT Masks */
1439#define MPROG 0x0001 /* Master Transfer In Progress */
1440#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1441#define ANAK 0x0004 /* Address Not Acknowledged */
1442#define DNAK 0x0008 /* Data Not Acknowledged */
1443#define BUFRDERR 0x0010 /* Buffer Read Error */
1444#define BUFWRERR 0x0020 /* Buffer Write Error */
1445#define SDASEN 0x0040 /* Serial Data Sense */
1446#define SCLSEN 0x0080 /* Serial Clock Sense */
1447#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1448
1449/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1450#define SINIT 0x0001 /* Slave Transfer Initiated */
1451#define SCOMP 0x0002 /* Slave Transfer Complete */
1452#define SERR 0x0004 /* Slave Transfer Error */
1453#define SOVF 0x0008 /* Slave Overflow */
1454#define MCOMP 0x0010 /* Master Transfer Complete */
1455#define MERR 0x0020 /* Master Transfer Error */
1456#define XMTSERV 0x0040 /* Transmit FIFO Service */
1457#define RCVSERV 0x0080 /* Receive FIFO Service */
1458
1459/* TWI_FIFO_CTRL Masks */
1460#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1461#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1462#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1463#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1464
1465/* TWI_FIFO_STAT Masks */
1466#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1467#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1468#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1469#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1470
1471#define RCVSTAT 0x000C /* Receive FIFO Status */
1472#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1473#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1474#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1475 1406
1476/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1407/* ******************* PIN CONTROL REGISTER MASKS ************************/
1477/* PORT_MUX Masks */ 1408/* PORT_MUX Masks */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
index d27f81d6c4b..f5aaf0573c0 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -1746,80 +1746,4 @@
1746#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1746#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1747#define BGSTAT 0x00000020 /* Bus granted */ 1747#define BGSTAT 0x00000020 /* Bus granted */
1748 1748
1749
1750/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
1751/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1752#ifdef _MISRA_RULES
1753#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
1754#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
1755#else
1756#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1757#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1758#endif /* _MISRA_RULES */
1759
1760/* TWIx_PRESCALE Masks */
1761#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1762#define TWI_ENA 0x0080 /* TWI Enable */
1763#define SCCB 0x0200 /* SCCB Compatibility Enable */
1764
1765/* TWIx_SLAVE_CTRL Masks */
1766#define SEN 0x0001 /* Slave Enable */
1767#define SADD_LEN 0x0002 /* Slave Address Length */
1768#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1769#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1770#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1771
1772/* TWIx_SLAVE_STAT Masks */
1773#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1774#define GCALL 0x0002 /* General Call Indicator */
1775
1776/* TWIx_MASTER_CTRL Masks */
1777#define MEN 0x0001 /* Master Mode Enable */
1778#define MADD_LEN 0x0002 /* Master Address Length */
1779#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1780#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1781#define STOP 0x0010 /* Issue Stop Condition */
1782#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1783#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1784#define SDAOVR 0x4000 /* Serial Data Override */
1785#define SCLOVR 0x8000 /* Serial Clock Override */
1786
1787/* TWIx_MASTER_STAT Masks */
1788#define MPROG 0x0001 /* Master Transfer In Progress */
1789#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1790#define ANAK 0x0004 /* Address Not Acknowledged */
1791#define DNAK 0x0008 /* Data Not Acknowledged */
1792#define BUFRDERR 0x0010 /* Buffer Read Error */
1793#define BUFWRERR 0x0020 /* Buffer Write Error */
1794#define SDASEN 0x0040 /* Serial Data Sense */
1795#define SCLSEN 0x0080 /* Serial Clock Sense */
1796#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1797
1798/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
1799#define SINIT 0x0001 /* Slave Transfer Initiated */
1800#define SCOMP 0x0002 /* Slave Transfer Complete */
1801#define SERR 0x0004 /* Slave Transfer Error */
1802#define SOVF 0x0008 /* Slave Overflow */
1803#define MCOMP 0x0010 /* Master Transfer Complete */
1804#define MERR 0x0020 /* Master Transfer Error */
1805#define XMTSERV 0x0040 /* Transmit FIFO Service */
1806#define RCVSERV 0x0080 /* Receive FIFO Service */
1807
1808/* TWIx_FIFO_CTL Masks */
1809#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1810#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1811#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1812#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1813
1814/* TWIx_FIFO_STAT Masks */
1815#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1816#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1817#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1818#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1819
1820#define RCVSTAT 0x000C /* Receive FIFO Status */
1821#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1822#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1823#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1824
1825#endif 1749#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 0867c2bedb4..b0102306035 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2062,115 +2062,6 @@
2062#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ 2062#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
2063#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ 2063#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
2064 2064
2065/* ************************************************ */
2066/* The TWI bit masks fields are from the ADSP-BF538 */
2067/* and they have not been verified as the final */
2068/* ones for the Moab processors ... bz 1/19/2007 */
2069/* ************************************************ */
2070
2071/* Bit masks for TWIx_CONTROL */
2072
2073#define PRESCALE 0x7f /* Prescale Value */
2074#define TWI_ENA 0x80 /* TWI Enable */
2075#define SCCB 0x200 /* Serial Camera Control Bus */
2076
2077/* Bit maskes for TWIx_CLKDIV */
2078
2079#define CLKLOW 0xff /* Clock Low */
2080#define CLKHI 0xff00 /* Clock High */
2081
2082/* Bit maskes for TWIx_SLAVE_CTL */
2083
2084#define SEN 0x1 /* Slave Enable */
2085#define STDVAL 0x4 /* Slave Transmit Data Valid */
2086#define NAK 0x8 /* Not Acknowledge */
2087#define GEN 0x10 /* General Call Enable */
2088
2089/* Bit maskes for TWIx_SLAVE_ADDR */
2090
2091#define SADDR 0x7f /* Slave Mode Address */
2092
2093/* Bit maskes for TWIx_SLAVE_STAT */
2094
2095#define SDIR 0x1 /* Slave Transfer Direction */
2096#define GCALL 0x2 /* General Call */
2097
2098/* Bit maskes for TWIx_MASTER_CTL */
2099
2100#define MEN 0x1 /* Master Mode Enable */
2101#define MDIR 0x4 /* Master Transfer Direction */
2102#define FAST 0x8 /* Fast Mode */
2103#define STOP 0x10 /* Issue Stop Condition */
2104#define RSTART 0x20 /* Repeat Start */
2105#define DCNT 0x3fc0 /* Data Transfer Count */
2106#define SDAOVR 0x4000 /* Serial Data Override */
2107#define SCLOVR 0x8000 /* Serial Clock Override */
2108
2109/* Bit maskes for TWIx_MASTER_ADDR */
2110
2111#define MADDR 0x7f /* Master Mode Address */
2112
2113/* Bit maskes for TWIx_MASTER_STAT */
2114
2115#define MPROG 0x1 /* Master Transfer in Progress */
2116#define LOSTARB 0x2 /* Lost Arbitration */
2117#define ANAK 0x4 /* Address Not Acknowledged */
2118#define DNAK 0x8 /* Data Not Acknowledged */
2119#define BUFRDERR 0x10 /* Buffer Read Error */
2120#define BUFWRERR 0x20 /* Buffer Write Error */
2121#define SDASEN 0x40 /* Serial Data Sense */
2122#define SCLSEN 0x80 /* Serial Clock Sense */
2123#define BUSBUSY 0x100 /* Bus Busy */
2124
2125/* Bit maskes for TWIx_FIFO_CTL */
2126
2127#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
2128#define RCVFLUSH 0x2 /* Receive Buffer Flush */
2129#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
2130#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
2131
2132/* Bit maskes for TWIx_FIFO_STAT */
2133
2134#define XMTSTAT 0x3 /* Transmit FIFO Status */
2135#define RCVSTAT 0xc /* Receive FIFO Status */
2136
2137/* Bit maskes for TWIx_INT_MASK */
2138
2139#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
2140#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
2141#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
2142#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
2143#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
2144#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
2145#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
2146#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
2147
2148/* Bit maskes for TWIx_INT_STAT */
2149
2150#define SINIT 0x1 /* Slave Transfer Initiated */
2151#define SCOMP 0x2 /* Slave Transfer Complete */
2152#define SERR 0x4 /* Slave Transfer Error */
2153#define SOVF 0x8 /* Slave Overflow */
2154#define MCOMP 0x10 /* Master Transfer Complete */
2155#define MERR 0x20 /* Master Transfer Error */
2156#define XMTSERV 0x40 /* Transmit FIFO Service */
2157#define RCVSERV 0x80 /* Receive FIFO Service */
2158
2159/* Bit maskes for TWIx_XMT_DATA8 */
2160
2161#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
2162
2163/* Bit maskes for TWIx_XMT_DATA16 */
2164
2165#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
2166
2167/* Bit maskes for TWIx_RCV_DATA8 */
2168
2169#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
2170
2171/* Bit maskes for TWIx_RCV_DATA16 */
2172
2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2174 2065
2175/* ******************************************* */ 2066/* ******************************************* */
2176/* MULTI BIT MACRO ENUMERATIONS */ 2067/* MULTI BIT MACRO ENUMERATIONS */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 19:28:27 -0400