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authorJiri Kosina <jkosina@suse.cz>2010-08-10 07:22:08 -0400
committerJiri Kosina <jkosina@suse.cz>2010-08-10 07:22:08 -0400
commitfb8231a8b139035476f2a8aaac837d0099b66dad (patch)
tree2875806beb96ea0cdab292146767a5085721dc6a /arch/blackfin/mach-bf537/include/mach/portmux.h
parent426d31071ac476ea62c62656b242930c17b58c00 (diff)
parentf6cec0ae58c17522a7bc4e2f39dae19f199ab534 (diff)
Merge branch 'master' into for-next
Conflicts: arch/arm/mach-omap1/board-nokia770.c
Diffstat (limited to 'arch/blackfin/mach-bf537/include/mach/portmux.h')
-rw-r--r--arch/blackfin/mach-bf537/include/mach/portmux.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
index da9760329e4..71d9eaeb579 100644
--- a/arch/blackfin/mach-bf537/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf537/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ 10#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
11 11
12#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 12#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
13#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 13#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
@@ -37,6 +37,7 @@
37#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) 37#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
38#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) 38#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
39#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) 39#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
40#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
40#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 41#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
41 42
42#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) 43#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
@@ -135,7 +136,6 @@
135 P_MDC, \ 136 P_MDC, \
136 P_MDIO, 0} 137 P_MDIO, 0}
137 138
138
139#define P_RMII0 {\ 139#define P_RMII0 {\
140 P_MII0_ETxD0, \ 140 P_MII0_ETxD0, \
141 P_MII0_ETxD1, \ 141 P_MII0_ETxD1, \
@@ -148,4 +148,5 @@
148 P_RMII0_CRS_DV, \ 148 P_RMII0_CRS_DV, \
149 P_MDC, \ 149 P_MDC, \
150 P_MDIO, 0} 150 P_MDIO, 0}
151#endif /* _MACH_PORTMUX_H_ */ 151
152#endif /* _MACH_PORTMUX_H_ */