diff options
author | Jiri Kosina <jkosina@suse.cz> | 2010-08-10 07:22:08 -0400 |
---|---|---|
committer | Jiri Kosina <jkosina@suse.cz> | 2010-08-10 07:22:08 -0400 |
commit | fb8231a8b139035476f2a8aaac837d0099b66dad (patch) | |
tree | 2875806beb96ea0cdab292146767a5085721dc6a /arch/blackfin/mach-bf537 | |
parent | 426d31071ac476ea62c62656b242930c17b58c00 (diff) | |
parent | f6cec0ae58c17522a7bc4e2f39dae19f199ab534 (diff) |
Merge branch 'master' into for-next
Conflicts:
arch/arm/mach-omap1/board-nokia770.c
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/anomaly.h | 11 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 36 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/gpio.h | 96 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/portmux.h | 7 |
4 files changed, 79 insertions, 71 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index d2c427bc665..43df6afd22a 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h | |||
@@ -5,7 +5,7 @@ | |||
5 | * and can be replaced with that version at any time | 5 | * and can be replaced with that version at any time |
6 | * DO NOT EDIT THIS FILE | 6 | * DO NOT EDIT THIS FILE |
7 | * | 7 | * |
8 | * Copyright 2004-2009 Analog Devices Inc. | 8 | * Copyright 2004-2010 Analog Devices Inc. |
9 | * Licensed under the ADI BSD license. | 9 | * Licensed under the ADI BSD license. |
10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd | 10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd |
11 | */ | 11 | */ |
@@ -162,8 +162,14 @@ | |||
162 | #define ANOMALY_05000461 (1) | 162 | #define ANOMALY_05000461 (1) |
163 | /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ | 163 | /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ |
164 | #define ANOMALY_05000473 (1) | 164 | #define ANOMALY_05000473 (1) |
165 | /* Possible Lockup Condition whem Modifying PLL from External Memory */ | ||
166 | #define ANOMALY_05000475 (1) | ||
165 | /* TESTSET Instruction Cannot Be Interrupted */ | 167 | /* TESTSET Instruction Cannot Be Interrupted */ |
166 | #define ANOMALY_05000477 (1) | 168 | #define ANOMALY_05000477 (1) |
169 | /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ | ||
170 | #define ANOMALY_05000481 (1) | ||
171 | /* IFLUSH sucks at life */ | ||
172 | #define ANOMALY_05000491 (1) | ||
167 | 173 | ||
168 | /* Anomalies that don't exist on this proc */ | 174 | /* Anomalies that don't exist on this proc */ |
169 | #define ANOMALY_05000099 (0) | 175 | #define ANOMALY_05000099 (0) |
@@ -179,6 +185,7 @@ | |||
179 | #define ANOMALY_05000198 (0) | 185 | #define ANOMALY_05000198 (0) |
180 | #define ANOMALY_05000202 (0) | 186 | #define ANOMALY_05000202 (0) |
181 | #define ANOMALY_05000215 (0) | 187 | #define ANOMALY_05000215 (0) |
188 | #define ANOMALY_05000219 (0) | ||
182 | #define ANOMALY_05000220 (0) | 189 | #define ANOMALY_05000220 (0) |
183 | #define ANOMALY_05000227 (0) | 190 | #define ANOMALY_05000227 (0) |
184 | #define ANOMALY_05000230 (0) | 191 | #define ANOMALY_05000230 (0) |
@@ -211,6 +218,6 @@ | |||
211 | #define ANOMALY_05000465 (0) | 218 | #define ANOMALY_05000465 (0) |
212 | #define ANOMALY_05000467 (0) | 219 | #define ANOMALY_05000467 (0) |
213 | #define ANOMALY_05000474 (0) | 220 | #define ANOMALY_05000474 (0) |
214 | #define ANOMALY_05000475 (0) | 221 | #define ANOMALY_05000485 (0) |
215 | 222 | ||
216 | #endif | 223 | #endif |
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index cf396ea4009..aad61b88737 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
@@ -434,22 +434,22 @@ | |||
434 | 434 | ||
435 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | 435 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ |
436 | #define TWI0_REGBASE 0xFFC01400 | 436 | #define TWI0_REGBASE 0xFFC01400 |
437 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 437 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
438 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ | 438 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ |
439 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | 439 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
440 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 440 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
441 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 441 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
442 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | 442 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
443 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 443 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
444 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 444 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
445 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | 445 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
446 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | 446 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
447 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | 447 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
448 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 448 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
449 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 449 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
450 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 450 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
451 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | 451 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
452 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | 452 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
453 | 453 | ||
454 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | 454 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ |
455 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | 455 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
@@ -1642,7 +1642,7 @@ | |||
1642 | #define TWI_ENA 0x0080 /* TWI Enable */ | 1642 | #define TWI_ENA 0x0080 /* TWI Enable */ |
1643 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | 1643 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
1644 | 1644 | ||
1645 | /* TWI_SLAVE_CTRL Masks */ | 1645 | /* TWI_SLAVE_CTL Masks */ |
1646 | #define SEN 0x0001 /* Slave Enable */ | 1646 | #define SEN 0x0001 /* Slave Enable */ |
1647 | #define SADD_LEN 0x0002 /* Slave Address Length */ | 1647 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
1648 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | 1648 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
@@ -1653,7 +1653,7 @@ | |||
1653 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | 1653 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
1654 | #define GCALL 0x0002 /* General Call Indicator */ | 1654 | #define GCALL 0x0002 /* General Call Indicator */ |
1655 | 1655 | ||
1656 | /* TWI_MASTER_CTRL Masks */ | 1656 | /* TWI_MASTER_CTL Masks */ |
1657 | #define MEN 0x0001 /* Master Mode Enable */ | 1657 | #define MEN 0x0001 /* Master Mode Enable */ |
1658 | #define MADD_LEN 0x0002 /* Master Address Length */ | 1658 | #define MADD_LEN 0x0002 /* Master Address Length */ |
1659 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | 1659 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h index 104bff85290..f80c2995efd 100644 --- a/arch/blackfin/mach-bf537/include/mach/gpio.h +++ b/arch/blackfin/mach-bf537/include/mach/gpio.h | |||
@@ -9,54 +9,54 @@ | |||
9 | 9 | ||
10 | #define MAX_BLACKFIN_GPIOS 48 | 10 | #define MAX_BLACKFIN_GPIOS 48 |
11 | 11 | ||
12 | #define GPIO_PF0 0 | 12 | #define GPIO_PF0 0 |
13 | #define GPIO_PF1 1 | 13 | #define GPIO_PF1 1 |
14 | #define GPIO_PF2 2 | 14 | #define GPIO_PF2 2 |
15 | #define GPIO_PF3 3 | 15 | #define GPIO_PF3 3 |
16 | #define GPIO_PF4 4 | 16 | #define GPIO_PF4 4 |
17 | #define GPIO_PF5 5 | 17 | #define GPIO_PF5 5 |
18 | #define GPIO_PF6 6 | 18 | #define GPIO_PF6 6 |
19 | #define GPIO_PF7 7 | 19 | #define GPIO_PF7 7 |
20 | #define GPIO_PF8 8 | 20 | #define GPIO_PF8 8 |
21 | #define GPIO_PF9 9 | 21 | #define GPIO_PF9 9 |
22 | #define GPIO_PF10 10 | 22 | #define GPIO_PF10 10 |
23 | #define GPIO_PF11 11 | 23 | #define GPIO_PF11 11 |
24 | #define GPIO_PF12 12 | 24 | #define GPIO_PF12 12 |
25 | #define GPIO_PF13 13 | 25 | #define GPIO_PF13 13 |
26 | #define GPIO_PF14 14 | 26 | #define GPIO_PF14 14 |
27 | #define GPIO_PF15 15 | 27 | #define GPIO_PF15 15 |
28 | #define GPIO_PG0 16 | 28 | #define GPIO_PG0 16 |
29 | #define GPIO_PG1 17 | 29 | #define GPIO_PG1 17 |
30 | #define GPIO_PG2 18 | 30 | #define GPIO_PG2 18 |
31 | #define GPIO_PG3 19 | 31 | #define GPIO_PG3 19 |
32 | #define GPIO_PG4 20 | 32 | #define GPIO_PG4 20 |
33 | #define GPIO_PG5 21 | 33 | #define GPIO_PG5 21 |
34 | #define GPIO_PG6 22 | 34 | #define GPIO_PG6 22 |
35 | #define GPIO_PG7 23 | 35 | #define GPIO_PG7 23 |
36 | #define GPIO_PG8 24 | 36 | #define GPIO_PG8 24 |
37 | #define GPIO_PG9 25 | 37 | #define GPIO_PG9 25 |
38 | #define GPIO_PG10 26 | 38 | #define GPIO_PG10 26 |
39 | #define GPIO_PG11 27 | 39 | #define GPIO_PG11 27 |
40 | #define GPIO_PG12 28 | 40 | #define GPIO_PG12 28 |
41 | #define GPIO_PG13 29 | 41 | #define GPIO_PG13 29 |
42 | #define GPIO_PG14 30 | 42 | #define GPIO_PG14 30 |
43 | #define GPIO_PG15 31 | 43 | #define GPIO_PG15 31 |
44 | #define GPIO_PH0 32 | 44 | #define GPIO_PH0 32 |
45 | #define GPIO_PH1 33 | 45 | #define GPIO_PH1 33 |
46 | #define GPIO_PH2 34 | 46 | #define GPIO_PH2 34 |
47 | #define GPIO_PH3 35 | 47 | #define GPIO_PH3 35 |
48 | #define GPIO_PH4 36 | 48 | #define GPIO_PH4 36 |
49 | #define GPIO_PH5 37 | 49 | #define GPIO_PH5 37 |
50 | #define GPIO_PH6 38 | 50 | #define GPIO_PH6 38 |
51 | #define GPIO_PH7 39 | 51 | #define GPIO_PH7 39 |
52 | #define GPIO_PH8 40 | 52 | #define GPIO_PH8 40 |
53 | #define GPIO_PH9 41 | 53 | #define GPIO_PH9 41 |
54 | #define GPIO_PH10 42 | 54 | #define GPIO_PH10 42 |
55 | #define GPIO_PH11 43 | 55 | #define GPIO_PH11 43 |
56 | #define GPIO_PH12 44 | 56 | #define GPIO_PH12 44 |
57 | #define GPIO_PH13 45 | 57 | #define GPIO_PH13 45 |
58 | #define GPIO_PH14 46 | 58 | #define GPIO_PH14 46 |
59 | #define GPIO_PH15 47 | 59 | #define GPIO_PH15 47 |
60 | 60 | ||
61 | #define PORT_F GPIO_PF0 | 61 | #define PORT_F GPIO_PF0 |
62 | #define PORT_G GPIO_PG0 | 62 | #define PORT_G GPIO_PG0 |
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h index da9760329e4..71d9eaeb579 100644 --- a/arch/blackfin/mach-bf537/include/mach/portmux.h +++ b/arch/blackfin/mach-bf537/include/mach/portmux.h | |||
@@ -7,7 +7,7 @@ | |||
7 | #ifndef _MACH_PORTMUX_H_ | 7 | #ifndef _MACH_PORTMUX_H_ |
8 | #define _MACH_PORTMUX_H_ | 8 | #define _MACH_PORTMUX_H_ |
9 | 9 | ||
10 | #define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ | 10 | #define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ |
11 | 11 | ||
12 | #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) | 12 | #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) |
13 | #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) | 13 | #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) |
@@ -37,6 +37,7 @@ | |||
37 | #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) | 37 | #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) |
38 | #define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) | 38 | #define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) |
39 | #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) | 39 | #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) |
40 | #define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10 | ||
40 | #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 | 41 | #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 |
41 | 42 | ||
42 | #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) | 43 | #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) |
@@ -135,7 +136,6 @@ | |||
135 | P_MDC, \ | 136 | P_MDC, \ |
136 | P_MDIO, 0} | 137 | P_MDIO, 0} |
137 | 138 | ||
138 | |||
139 | #define P_RMII0 {\ | 139 | #define P_RMII0 {\ |
140 | P_MII0_ETxD0, \ | 140 | P_MII0_ETxD0, \ |
141 | P_MII0_ETxD1, \ | 141 | P_MII0_ETxD1, \ |
@@ -148,4 +148,5 @@ | |||
148 | P_RMII0_CRS_DV, \ | 148 | P_RMII0_CRS_DV, \ |
149 | P_MDC, \ | 149 | P_MDC, \ |
150 | P_MDIO, 0} | 150 | P_MDIO, 0} |
151 | #endif /* _MACH_PORTMUX_H_ */ | 151 | |
152 | #endif /* _MACH_PORTMUX_H_ */ | ||