diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-ux500/include/mach | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'arch/arm/mach-ux500/include/mach')
-rw-r--r-- | arch/arm/mach-ux500/include/mach/db5500-regs.h | 137 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/entry-macro.S | 20 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/gpio.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/io.h | 22 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/irqs-board-u5500.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/irqs-db5500.h | 113 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/mbox-db5500.h | 88 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/memory.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/system.h | 25 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/usb.h | 25 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/vmalloc.h | 18 |
11 files changed, 499 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h new file mode 100644 index 00000000000..6ad98329410 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2010 | ||
3 | * | ||
4 | * License terms: GNU General Public License (GPL) version 2 | ||
5 | */ | ||
6 | |||
7 | #ifndef __MACH_DB5500_REGS_H | ||
8 | #define __MACH_DB5500_REGS_H | ||
9 | |||
10 | #define U5500_PER1_BASE 0xA0020000 | ||
11 | #define U5500_PER2_BASE 0xA0010000 | ||
12 | #define U5500_PER3_BASE 0x80140000 | ||
13 | #define U5500_PER4_BASE 0x80150000 | ||
14 | #define U5500_PER5_BASE 0x80100000 | ||
15 | #define U5500_PER6_BASE 0x80120000 | ||
16 | |||
17 | #define U5500_GIC_DIST_BASE 0xA0411000 | ||
18 | #define U5500_GIC_CPU_BASE 0xA0410100 | ||
19 | #define U5500_DMA_BASE 0x90030000 | ||
20 | #define U5500_STM_BASE 0x90020000 | ||
21 | #define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000) | ||
22 | #define U5500_MCDE_BASE 0xA0400000 | ||
23 | #define U5500_MODEM_BASE 0xB0000000 | ||
24 | #define U5500_L2CC_BASE 0xA0412000 | ||
25 | #define U5500_SCU_BASE 0xA0410000 | ||
26 | #define U5500_DSI1_BASE 0xA0401000 | ||
27 | #define U5500_DSI2_BASE 0xA0402000 | ||
28 | #define U5500_SIA_BASE 0xA0100000 | ||
29 | #define U5500_SVA_BASE 0x80200000 | ||
30 | #define U5500_HSEM_BASE 0xA0000000 | ||
31 | #define U5500_NAND0_BASE 0x60000000 | ||
32 | #define U5500_NAND1_BASE 0x70000000 | ||
33 | #define U5500_TWD_BASE 0xa0410600 | ||
34 | #define U5500_ICN_BASE 0xA0040000 | ||
35 | #define U5500_B2R2_BASE 0xa0200000 | ||
36 | #define U5500_BOOT_ROM_BASE 0x90000000 | ||
37 | |||
38 | #define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) | ||
39 | #define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) | ||
40 | #define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) | ||
41 | #define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) | ||
42 | #define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) | ||
43 | #define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) | ||
44 | #define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) | ||
45 | #define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) | ||
46 | |||
47 | #define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) | ||
48 | #define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) | ||
49 | #define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) | ||
50 | |||
51 | #define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) | ||
52 | #define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) | ||
53 | #define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) | ||
54 | #define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) | ||
55 | |||
56 | #define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) | ||
57 | #define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) | ||
58 | #define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) | ||
59 | #define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) | ||
60 | #define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) | ||
61 | #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) | ||
62 | #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) | ||
63 | #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) | ||
64 | #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) | ||
65 | #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) | ||
66 | #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) | ||
67 | #define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) | ||
68 | |||
69 | #define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) | ||
70 | #define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) | ||
71 | #define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) | ||
72 | #define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) | ||
73 | #define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) | ||
74 | #define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) | ||
75 | #define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) | ||
76 | #define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) | ||
77 | #define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) | ||
78 | #define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) | ||
79 | #define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) | ||
80 | #define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) | ||
81 | #define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) | ||
82 | #define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) | ||
83 | #define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) | ||
84 | #define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) | ||
85 | #define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) | ||
86 | |||
87 | #define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) | ||
88 | #define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) | ||
89 | #define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) | ||
90 | #define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) | ||
91 | #define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100) | ||
92 | #define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) | ||
93 | #define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) | ||
94 | #define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) | ||
95 | #define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) | ||
96 | #define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) | ||
97 | #define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) | ||
98 | |||
99 | #define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE | ||
100 | #define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) | ||
101 | #define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE | ||
102 | #define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE | ||
103 | #define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE | ||
104 | #define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE | ||
105 | #define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) | ||
106 | #define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) | ||
107 | |||
108 | #define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000) | ||
109 | #define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40) | ||
110 | #define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F) | ||
111 | #define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60) | ||
112 | #define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F) | ||
113 | #define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80) | ||
114 | #define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F) | ||
115 | #define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0) | ||
116 | #define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF) | ||
117 | #define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00) | ||
118 | #define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F) | ||
119 | #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) | ||
120 | #define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) | ||
121 | |||
122 | #define U5500_ACCCON_BASE_SEC (0xBFFF0000) | ||
123 | #define U5500_ACCCON_BASE (0xBFFF1000) | ||
124 | #define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) | ||
125 | #define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) | ||
126 | |||
127 | #define U5500_ESRAM_BASE 0x40000000 | ||
128 | #define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 | ||
129 | #define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) | ||
130 | |||
131 | #define U5500_MCDE_SIZE 0x1000 | ||
132 | #define U5500_DSI_LINK_SIZE 0x1000 | ||
133 | #define U5500_DSI_LINK_COUNT 0x2 | ||
134 | #define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE) | ||
135 | #define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE) | ||
136 | |||
137 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S new file mode 100644 index 00000000000..071bba94f72 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * Low-level IRQ helper macros for U8500 platforms | ||
3 | * | ||
4 | * Copyright (C) 2009 ST-Ericsson. | ||
5 | * | ||
6 | * This file is a copy of ARM Realview platform. | ||
7 | * -just satisfied checkpatch script. | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | #include <mach/hardware.h> | ||
14 | #include <asm/hardware/entry-macro-gic.S> | ||
15 | |||
16 | .macro disable_fiq | ||
17 | .endm | ||
18 | |||
19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
20 | .endm | ||
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h new file mode 100644 index 00000000000..3c4cd31ad9f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/gpio.h | |||
@@ -0,0 +1,12 @@ | |||
1 | #ifndef __ASM_ARCH_GPIO_H | ||
2 | #define __ASM_ARCH_GPIO_H | ||
3 | |||
4 | /* | ||
5 | * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough | ||
6 | * room for a couple of GPIO expanders. | ||
7 | */ | ||
8 | #define ARCH_NR_GPIOS 350 | ||
9 | |||
10 | #include <plat/gpio.h> | ||
11 | |||
12 | #endif /* __ASM_ARCH_GPIO_H */ | ||
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h new file mode 100644 index 00000000000..1cf3f44ce5b --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/io.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-u8500/include/mach/io.h | ||
3 | * | ||
4 | * Copyright (C) 1997-1999 Russell King | ||
5 | * | ||
6 | * Modifications: | ||
7 | * 06-12-1997 RMK Created. | ||
8 | * 07-04-1999 RMK Major cleanup | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_ARCH_IO_H | ||
11 | #define __ASM_ARM_ARCH_IO_H | ||
12 | |||
13 | #define IO_SPACE_LIMIT 0xffffffff | ||
14 | |||
15 | /* | ||
16 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
17 | * drivers out there that might just work if we fake them... | ||
18 | */ | ||
19 | #define __io(a) __typesafe_io(a) | ||
20 | #define __mem_pci(a) (a) | ||
21 | |||
22 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h new file mode 100644 index 00000000000..29d972c7717 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2010 | ||
3 | * | ||
4 | * License terms: GNU General Public License (GPL) version 2 | ||
5 | */ | ||
6 | |||
7 | #ifndef __MACH_IRQS_BOARD_U5500_H | ||
8 | #define __MACH_IRQS_BOARD_U5500_H | ||
9 | |||
10 | #define AB5500_NR_IRQS 5 | ||
11 | #define IRQ_AB5500_BASE IRQ_BOARD_START | ||
12 | #define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS) | ||
13 | |||
14 | #define U5500_IRQ_END IRQ_AB5500_END | ||
15 | |||
16 | #if IRQ_BOARD_END < U5500_IRQ_END | ||
17 | #undef IRQ_BOARD_END | ||
18 | #define IRQ_BOARD_END U5500_IRQ_END | ||
19 | #endif | ||
20 | |||
21 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h new file mode 100644 index 00000000000..77239776a6f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h | |||
@@ -0,0 +1,113 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2010 | ||
3 | * | ||
4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> | ||
5 | * License terms: GNU General Public License (GPL) version 2 | ||
6 | */ | ||
7 | |||
8 | #ifndef __MACH_IRQS_DB5500_H | ||
9 | #define __MACH_IRQS_DB5500_H | ||
10 | |||
11 | #define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4) | ||
12 | #define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6) | ||
13 | #define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7) | ||
14 | #define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8) | ||
15 | #define IRQ_DB5500_RTT (IRQ_SHPI_START + 9) | ||
16 | #define IRQ_DB5500_PKA (IRQ_SHPI_START + 10) | ||
17 | #define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11) | ||
18 | #define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12) | ||
19 | #define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13) | ||
20 | #define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14) | ||
21 | #define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15) | ||
22 | #define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16) | ||
23 | #define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17) | ||
24 | #define IRQ_DB5500_RTC (IRQ_SHPI_START + 18) | ||
25 | #define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19) | ||
26 | #define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20) | ||
27 | #define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21) | ||
28 | #define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22) | ||
29 | #define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23) | ||
30 | #define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24) | ||
31 | #define IRQ_DB5500_DMA (IRQ_SHPI_START + 25) | ||
32 | #define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26) | ||
33 | #define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27) | ||
34 | #define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28) | ||
35 | #define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29) | ||
36 | #define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30) | ||
37 | #define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31) | ||
38 | #define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33) | ||
39 | #define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34) | ||
40 | #define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35) | ||
41 | #define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36) | ||
42 | #define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37) | ||
43 | #define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38) | ||
44 | #define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39) | ||
45 | #define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40) | ||
46 | #define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41) | ||
47 | #define IRQ_DB5500_SIA (IRQ_SHPI_START + 42) | ||
48 | #define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43) | ||
49 | #define IRQ_DB5500_HVA (IRQ_SHPI_START + 44) | ||
50 | #define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45) | ||
51 | #define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46) | ||
52 | #define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47) | ||
53 | #define IRQ_DB5500_DISP (IRQ_SHPI_START + 48) | ||
54 | #define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50) | ||
55 | #define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52) | ||
56 | #define IRQ_DB5500_KBD (IRQ_SHPI_START + 53) | ||
57 | #define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55) | ||
58 | #define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56) | ||
59 | #define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57) | ||
60 | #define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59) | ||
61 | #define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) | ||
62 | #define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) | ||
63 | #define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) | ||
64 | #define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65) | ||
65 | #define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) | ||
66 | #define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) | ||
67 | #define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) | ||
68 | #define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108) | ||
69 | #define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109) | ||
70 | #define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110) | ||
71 | #define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112) | ||
72 | #define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113) | ||
73 | #define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114) | ||
74 | #define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115) | ||
75 | #define IRQ_DB5500_MALI (IRQ_SHPI_START + 116) | ||
76 | #define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118) | ||
77 | #define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119) | ||
78 | #define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120) | ||
79 | #define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121) | ||
80 | #define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122) | ||
81 | #define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123) | ||
82 | #define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124) | ||
83 | #define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) | ||
84 | #define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) | ||
85 | |||
86 | #ifdef CONFIG_UX500_SOC_DB5500 | ||
87 | |||
88 | /* | ||
89 | * After the GPIO ones we reserve a range of IRQ:s in which virtual | ||
90 | * IRQ:s representing modem IRQ:s can be allocated | ||
91 | */ | ||
92 | #define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START | ||
93 | #define IRQ_MODEM_EVENTS_NBR 72 | ||
94 | #define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR) | ||
95 | |||
96 | /* List of virtual IRQ:s that are allocated from the range above */ | ||
97 | #define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43) | ||
98 | #define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45) | ||
99 | #define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41) | ||
100 | |||
101 | /* | ||
102 | * We may have several SoCs, but only one will run at a | ||
103 | * time, so the one with most IRQs will bump this ahead, | ||
104 | * but the IRQ_SOC_START remains the same for either SoC. | ||
105 | */ | ||
106 | #if IRQ_SOC_END < IRQ_MODEM_EVENTS_END | ||
107 | #undef IRQ_SOC_END | ||
108 | #define IRQ_SOC_END IRQ_MODEM_EVENTS_END | ||
109 | #endif | ||
110 | |||
111 | #endif /* CONFIG_UX500_SOC_DB5500 */ | ||
112 | |||
113 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h new file mode 100644 index 00000000000..7f9da4d2fbd --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2010 | ||
3 | * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. | ||
4 | * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. | ||
5 | * License terms: GNU General Public License (GPL), version 2. | ||
6 | */ | ||
7 | |||
8 | #ifndef __INC_STE_MBOX_H | ||
9 | #define __INC_STE_MBOX_H | ||
10 | |||
11 | #define MBOX_BUF_SIZE 16 | ||
12 | #define MBOX_NAME_SIZE 8 | ||
13 | |||
14 | /** | ||
15 | * mbox_recv_cb_t - Definition of the mailbox callback. | ||
16 | * @mbox_msg: The mailbox message. | ||
17 | * @priv: The clients private data as specified in the call to mbox_setup. | ||
18 | * | ||
19 | * This function will be called upon reception of new mailbox messages. | ||
20 | */ | ||
21 | typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv); | ||
22 | |||
23 | /** | ||
24 | * struct mbox - Mailbox instance struct | ||
25 | * @list: Linked list head. | ||
26 | * @pdev: Pointer to device struct. | ||
27 | * @cb: Callback function. Will be called | ||
28 | * when new data is received. | ||
29 | * @client_data: Clients private data. Will be sent back | ||
30 | * in the callback function. | ||
31 | * @virtbase_peer: Virtual address for outgoing mailbox. | ||
32 | * @virtbase_local: Virtual address for incoming mailbox. | ||
33 | * @buffer: Then internal queue for outgoing messages. | ||
34 | * @name: Name of this mailbox. | ||
35 | * @buffer_available: Completion variable to achieve "blocking send". | ||
36 | * This variable will be signaled when there is | ||
37 | * internal buffer space available. | ||
38 | * @client_blocked: To keep track if any client is currently | ||
39 | * blocked. | ||
40 | * @lock: Spinlock to protect this mailbox instance. | ||
41 | * @write_index: Index in internal buffer to write to. | ||
42 | * @read_index: Index in internal buffer to read from. | ||
43 | * @allocated: Indicates whether this particular mailbox | ||
44 | * id has been allocated by someone. | ||
45 | */ | ||
46 | struct mbox { | ||
47 | struct list_head list; | ||
48 | struct platform_device *pdev; | ||
49 | mbox_recv_cb_t *cb; | ||
50 | void *client_data; | ||
51 | void __iomem *virtbase_peer; | ||
52 | void __iomem *virtbase_local; | ||
53 | u32 buffer[MBOX_BUF_SIZE]; | ||
54 | char name[MBOX_NAME_SIZE]; | ||
55 | struct completion buffer_available; | ||
56 | u8 client_blocked; | ||
57 | spinlock_t lock; | ||
58 | u8 write_index; | ||
59 | u8 read_index; | ||
60 | bool allocated; | ||
61 | }; | ||
62 | |||
63 | /** | ||
64 | * mbox_setup - Set up a mailbox and return its instance. | ||
65 | * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU, | ||
66 | * 2 for modem DSP. | ||
67 | * @mbox_cb: Pointer to the callback function to be called when a new message | ||
68 | * is received. | ||
69 | * @priv: Client user data which will be returned in the callback. | ||
70 | * | ||
71 | * Returns a mailbox instance to be specified in subsequent calls to mbox_send. | ||
72 | */ | ||
73 | struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv); | ||
74 | |||
75 | /** | ||
76 | * mbox_send - Send a mailbox message. | ||
77 | * @mbox: Mailbox instance (returned by mbox_setup) | ||
78 | * @mbox_msg: The mailbox message to send. | ||
79 | * @block: Specifies whether this call will block until send is possible, | ||
80 | * or return an error if the mailbox buffer is full. | ||
81 | * | ||
82 | * Returns 0 on success or a negative error code on error. -ENOMEM indicates | ||
83 | * that the internal buffer is full and you have to try again later (or | ||
84 | * specify "block" in order to block until send is possible). | ||
85 | */ | ||
86 | int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block); | ||
87 | |||
88 | #endif /*INC_STE_MBOX_H*/ | ||
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h new file mode 100644 index 00000000000..2ef697a6700 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/memory.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 ST-Ericsson | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | */ | ||
9 | #ifndef __ASM_ARCH_MEMORY_H | ||
10 | #define __ASM_ARCH_MEMORY_H | ||
11 | |||
12 | /* | ||
13 | * Physical DRAM offset. | ||
14 | */ | ||
15 | #define PLAT_PHYS_OFFSET UL(0x00000000) | ||
16 | #define BUS_OFFSET UL(0x00000000) | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h new file mode 100644 index 00000000000..c0cd8006f1a --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/system.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 ST-Ericsson. | ||
3 | * | ||
4 | * This file is licensed under the terms of the GNU General Public | ||
5 | * License version 2. This program is licensed "as is" without any | ||
6 | * warranty of any kind, whether express or implied. | ||
7 | */ | ||
8 | #ifndef __ASM_ARCH_SYSTEM_H | ||
9 | #define __ASM_ARCH_SYSTEM_H | ||
10 | |||
11 | static inline void arch_idle(void) | ||
12 | { | ||
13 | /* | ||
14 | * This should do all the clock switching | ||
15 | * and wait for interrupt tricks | ||
16 | */ | ||
17 | cpu_do_idle(); | ||
18 | } | ||
19 | |||
20 | static inline void arch_reset(char mode, const char *cmd) | ||
21 | { | ||
22 | /* yet to be implemented - TODO */ | ||
23 | } | ||
24 | |||
25 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h new file mode 100644 index 00000000000..d3739d41881 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/usb.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2011 | ||
3 | * | ||
4 | * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> | ||
5 | * License terms: GNU General Public License (GPL) version 2 | ||
6 | */ | ||
7 | #ifndef __ASM_ARCH_USB_H | ||
8 | #define __ASM_ARCH_USB_H | ||
9 | |||
10 | #include <linux/dmaengine.h> | ||
11 | |||
12 | #define UX500_MUSB_DMA_NUM_RX_CHANNELS 8 | ||
13 | #define UX500_MUSB_DMA_NUM_TX_CHANNELS 8 | ||
14 | |||
15 | struct ux500_musb_board_data { | ||
16 | void **dma_rx_param_array; | ||
17 | void **dma_tx_param_array; | ||
18 | u32 num_rx_channels; | ||
19 | u32 num_tx_channels; | ||
20 | bool (*dma_filter)(struct dma_chan *chan, void *filter_param); | ||
21 | }; | ||
22 | |||
23 | void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg, | ||
24 | int *dma_tx_cfg); | ||
25 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h new file mode 100644 index 00000000000..a4945cb4117 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/vmalloc.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 ST-Ericsson | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
18 | #define VMALLOC_END 0xf0000000UL | ||