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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-ux500
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r--arch/arm/mach-ux500/board-u5500-sdi.c74
-rw-r--r--arch/arm/mach-ux500/board-u5500.c126
-rw-r--r--arch/arm/mach-ux500/clock.c821
-rw-r--r--arch/arm/mach-ux500/clock.h151
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c227
-rw-r--r--arch/arm/mach-ux500/devices-db5500.h79
-rw-r--r--arch/arm/mach-ux500/dma-db5500.c136
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h137
-rw-r--r--arch/arm/mach-ux500/include/mach/entry-macro.S20
-rw-r--r--arch/arm/mach-ux500/include/mach/gpio.h12
-rw-r--r--arch/arm/mach-ux500/include/mach/io.h22
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-u5500.h21
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h113
-rw-r--r--arch/arm/mach-ux500/include/mach/mbox-db5500.h88
-rw-r--r--arch/arm/mach-ux500/include/mach/memory.h18
-rw-r--r--arch/arm/mach-ux500/include/mach/system.h25
-rw-r--r--arch/arm/mach-ux500/include/mach/usb.h25
-rw-r--r--arch/arm/mach-ux500/include/mach/vmalloc.h18
-rw-r--r--arch/arm/mach-ux500/localtimer.c29
-rw-r--r--arch/arm/mach-ux500/mbox-db5500.c565
-rw-r--r--arch/arm/mach-ux500/modem-irq-db5500.c143
-rw-r--r--arch/arm/mach-ux500/pins-db5500.h620
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db5500.h135
23 files changed, 3605 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
new file mode 100644
index 00000000000..739fb4c5b16
--- /dev/null
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -0,0 +1,74 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Hanumath Prasad <ulf.hansson@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/amba/mmci.h>
9#include <linux/mmc/host.h>
10#include <linux/gpio.h>
11
12#include <plat/pincfg.h>
13#include <mach/db5500-regs.h>
14#include <plat/ste_dma40.h>
15
16#include "pins-db5500.h"
17#include "devices-db5500.h"
18#include "ste-dma40-db5500.h"
19
20static pin_cfg_t u5500_sdi_pins[] = {
21 /* SDI0 (POP eMMC) */
22 GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP,
23 GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP,
24 GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP,
25 GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP,
26 GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP,
27 GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP,
28 GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP,
29 GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP,
30 GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP,
31 GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW,
32};
33
34#ifdef CONFIG_STE_DMA40
35struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
36 .mode = STEDMA40_MODE_LOGICAL,
37 .dir = STEDMA40_PERIPH_TO_MEM,
38 .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
39 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .src_info.data_width = STEDMA40_WORD_WIDTH,
41 .dst_info.data_width = STEDMA40_WORD_WIDTH,
42};
43
44static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
45 .mode = STEDMA40_MODE_LOGICAL,
46 .dir = STEDMA40_MEM_TO_PERIPH,
47 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
48 .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
49 .src_info.data_width = STEDMA40_WORD_WIDTH,
50 .dst_info.data_width = STEDMA40_WORD_WIDTH,
51};
52#endif
53
54static struct mmci_platform_data u5500_sdi0_data = {
55 .ocr_mask = MMC_VDD_165_195,
56 .f_max = 50000000,
57 .capabilities = MMC_CAP_4_BIT_DATA |
58 MMC_CAP_8_BIT_DATA |
59 MMC_CAP_MMC_HIGHSPEED,
60 .gpio_cd = -1,
61 .gpio_wp = -1,
62#ifdef CONFIG_STE_DMA40
63 .dma_filter = stedma40_filter,
64 .dma_rx_param = &u5500_sdi0_dma_cfg_rx,
65 .dma_tx_param = &u5500_sdi0_dma_cfg_tx,
66#endif
67};
68
69void __init u5500_sdi_init(void)
70{
71 nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
72
73 db5500_add_sdi0(&u5500_sdi0_data);
74}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
new file mode 100644
index 00000000000..e58f0f56242
--- /dev/null
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/amba/bus.h>
11#include <linux/gpio.h>
12#include <linux/irq.h>
13#include <linux/i2c.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17
18#include <plat/pincfg.h>
19#include <plat/i2c.h>
20
21#include <mach/hardware.h>
22#include <mach/devices.h>
23#include <mach/setup.h>
24
25#include "pins-db5500.h"
26#include "devices-db5500.h"
27#include <linux/led-lm3530.h>
28
29/*
30 * GPIO
31 */
32
33static pin_cfg_t u5500_pins[] = {
34 /* I2C */
35 GPIO218_I2C2_SCL | PIN_INPUT_PULLUP,
36 GPIO219_I2C2_SDA | PIN_INPUT_PULLUP,
37
38 /* DISPLAY_ENABLE */
39 GPIO226_GPIO | PIN_OUTPUT_LOW,
40
41 /* Backlight Enbale */
42 GPIO224_GPIO | PIN_OUTPUT_HIGH,
43};
44/*
45 * I2C
46 */
47
48#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
49static struct nmk_i2c_controller u5500_i2c##id##_data = { \
50 /* \
51 * slave data setup time, which is \
52 * 250 ns,100ns,10ns which is 14,6,2 \
53 * respectively for a 48 Mhz \
54 * i2c clock \
55 */ \
56 .slsu = _slsu, \
57 /* Tx FIFO threshold */ \
58 .tft = _tft, \
59 /* Rx FIFO threshold */ \
60 .rft = _rft, \
61 /* std. mode operation */ \
62 .clk_freq = clk, \
63 .sm = _sm, \
64}
65/*
66 * The board uses TODO <3> i2c controllers, initialize all of
67 * them with slave data setup time of 250 ns,
68 * Tx & Rx FIFO threshold values as 1 and standard
69 * mode of operation
70 */
71
72U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST);
73
74static struct lm3530_platform_data u5500_als_platform_data = {
75 .mode = LM3530_BL_MODE_MANUAL,
76 .als_input_mode = LM3530_INPUT_ALS1,
77 .max_current = LM3530_FS_CURR_26mA,
78 .pwm_pol_hi = true,
79 .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms,
80 .brt_ramp_law = 1, /* Linear */
81 .brt_ramp_fall = LM3530_RAMP_TIME_8s,
82 .brt_ramp_rise = LM3530_RAMP_TIME_8s,
83 .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm,
84 .als2_resistor_sel = LM3530_ALS_IMPD_Z,
85 .als_vmin = 730, /* mV */
86 .als_vmax = 1020, /* mV */
87 .brt_val = 0x7F, /* Max brightness */
88};
89
90
91static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
92 {
93 /* Backlight */
94 I2C_BOARD_INFO("lm3530-led", 0x36),
95 .platform_data = &u5500_als_platform_data,
96 },
97};
98
99static void __init u5500_i2c_init(void)
100{
101 db5500_add_i2c2(&u5500_i2c2_data);
102 i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
103}
104static void __init u5500_uart_init(void)
105{
106 db5500_add_uart0(NULL);
107 db5500_add_uart1(NULL);
108 db5500_add_uart2(NULL);
109}
110
111static void __init u5500_init_machine(void)
112{
113 u5500_init_devices();
114 nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
115 u5500_i2c_init();
116 u5500_sdi_init();
117 u5500_uart_init();
118}
119
120MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
121 .boot_params = 0x00000100,
122 .map_io = u5500_map_io,
123 .init_irq = ux500_init_irq,
124 .timer = &ux500_timer,
125 .init_machine = u5500_init_machine,
126MACHINE_END
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
new file mode 100644
index 00000000000..e832664d1bd
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.c
@@ -0,0 +1,821 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/list.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/clkdev.h>
17#include <linux/cpufreq.h>
18
19#include <plat/mtu.h>
20#include <mach/hardware.h>
21#include "clock.h"
22
23#ifdef CONFIG_DEBUG_FS
24#include <linux/debugfs.h>
25#include <linux/uaccess.h> /* for copy_from_user */
26static LIST_HEAD(clk_list);
27#endif
28
29#define PRCC_PCKEN 0x00
30#define PRCC_PCKDIS 0x04
31#define PRCC_KCKEN 0x08
32#define PRCC_KCKDIS 0x0C
33
34#define PRCM_YYCLKEN0_MGT_SET 0x510
35#define PRCM_YYCLKEN1_MGT_SET 0x514
36#define PRCM_YYCLKEN0_MGT_CLR 0x518
37#define PRCM_YYCLKEN1_MGT_CLR 0x51C
38#define PRCM_YYCLKEN0_MGT_VAL 0x520
39#define PRCM_YYCLKEN1_MGT_VAL 0x524
40
41#define PRCM_SVAMMDSPCLK_MGT 0x008
42#define PRCM_SIAMMDSPCLK_MGT 0x00C
43#define PRCM_SGACLK_MGT 0x014
44#define PRCM_UARTCLK_MGT 0x018
45#define PRCM_MSP02CLK_MGT 0x01C
46#define PRCM_MSP1CLK_MGT 0x288
47#define PRCM_I2CCLK_MGT 0x020
48#define PRCM_SDMMCCLK_MGT 0x024
49#define PRCM_SLIMCLK_MGT 0x028
50#define PRCM_PER1CLK_MGT 0x02C
51#define PRCM_PER2CLK_MGT 0x030
52#define PRCM_PER3CLK_MGT 0x034
53#define PRCM_PER5CLK_MGT 0x038
54#define PRCM_PER6CLK_MGT 0x03C
55#define PRCM_PER7CLK_MGT 0x040
56#define PRCM_LCDCLK_MGT 0x044
57#define PRCM_BMLCLK_MGT 0x04C
58#define PRCM_HSITXCLK_MGT 0x050
59#define PRCM_HSIRXCLK_MGT 0x054
60#define PRCM_HDMICLK_MGT 0x058
61#define PRCM_APEATCLK_MGT 0x05C
62#define PRCM_APETRACECLK_MGT 0x060
63#define PRCM_MCDECLK_MGT 0x064
64#define PRCM_IPI2CCLK_MGT 0x068
65#define PRCM_DSIALTCLK_MGT 0x06C
66#define PRCM_DMACLK_MGT 0x074
67#define PRCM_B2R2CLK_MGT 0x078
68#define PRCM_TVCLK_MGT 0x07C
69#define PRCM_TCR 0x1C8
70#define PRCM_TCR_STOPPED (1 << 16)
71#define PRCM_TCR_DOZE_MODE (1 << 17)
72#define PRCM_UNIPROCLK_MGT 0x278
73#define PRCM_SSPCLK_MGT 0x280
74#define PRCM_RNGCLK_MGT 0x284
75#define PRCM_UICCCLK_MGT 0x27C
76
77#define PRCM_MGT_ENABLE (1 << 8)
78
79static DEFINE_SPINLOCK(clocks_lock);
80
81static void __clk_enable(struct clk *clk)
82{
83 if (clk->enabled++ == 0) {
84 if (clk->parent_cluster)
85 __clk_enable(clk->parent_cluster);
86
87 if (clk->parent_periph)
88 __clk_enable(clk->parent_periph);
89
90 if (clk->ops && clk->ops->enable)
91 clk->ops->enable(clk);
92 }
93}
94
95int clk_enable(struct clk *clk)
96{
97 unsigned long flags;
98
99 spin_lock_irqsave(&clocks_lock, flags);
100 __clk_enable(clk);
101 spin_unlock_irqrestore(&clocks_lock, flags);
102
103 return 0;
104}
105EXPORT_SYMBOL(clk_enable);
106
107static void __clk_disable(struct clk *clk)
108{
109 if (--clk->enabled == 0) {
110 if (clk->ops && clk->ops->disable)
111 clk->ops->disable(clk);
112
113 if (clk->parent_periph)
114 __clk_disable(clk->parent_periph);
115
116 if (clk->parent_cluster)
117 __clk_disable(clk->parent_cluster);
118 }
119}
120
121void clk_disable(struct clk *clk)
122{
123 unsigned long flags;
124
125 WARN_ON(!clk->enabled);
126
127 spin_lock_irqsave(&clocks_lock, flags);
128 __clk_disable(clk);
129 spin_unlock_irqrestore(&clocks_lock, flags);
130}
131EXPORT_SYMBOL(clk_disable);
132
133/*
134 * The MTU has a separate, rather complex muxing setup
135 * with alternative parents (peripheral cluster or
136 * ULP or fixed 32768 Hz) depending on settings
137 */
138static unsigned long clk_mtu_get_rate(struct clk *clk)
139{
140 void __iomem *addr;
141 u32 tcr;
142 int mtu = (int) clk->data;
143 /*
144 * One of these is selected eventually
145 * TODO: Replace the constant with a reference
146 * to the ULP source once this is modeled.
147 */
148 unsigned long clk32k = 32768;
149 unsigned long mturate;
150 unsigned long retclk;
151
152 if (cpu_is_u5500())
153 addr = __io_address(U5500_PRCMU_BASE);
154 else if (cpu_is_u8500())
155 addr = __io_address(U8500_PRCMU_BASE);
156 else
157 ux500_unknown_soc();
158
159 /*
160 * On a startup, always conifgure the TCR to the doze mode;
161 * bootloaders do it for us. Do this in the kernel too.
162 */
163 writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
164
165 tcr = readl(addr + PRCM_TCR);
166
167 /* Get the rate from the parent as a default */
168 if (clk->parent_periph)
169 mturate = clk_get_rate(clk->parent_periph);
170 else if (clk->parent_cluster)
171 mturate = clk_get_rate(clk->parent_cluster);
172 else
173 /* We need to be connected SOMEWHERE */
174 BUG();
175
176 /* Return the clock selected for this MTU */
177 if (tcr & (1 << mtu))
178 retclk = clk32k;
179 else
180 retclk = mturate;
181
182 pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
183 return retclk;
184}
185
186unsigned long clk_get_rate(struct clk *clk)
187{
188 unsigned long rate;
189
190 /*
191 * If there is a custom getrate callback for this clock,
192 * it will take precedence.
193 */
194 if (clk->get_rate)
195 return clk->get_rate(clk);
196
197 if (clk->ops && clk->ops->get_rate)
198 return clk->ops->get_rate(clk);
199
200 rate = clk->rate;
201 if (!rate) {
202 if (clk->parent_periph)
203 rate = clk_get_rate(clk->parent_periph);
204 else if (clk->parent_cluster)
205 rate = clk_get_rate(clk->parent_cluster);
206 }
207
208 return rate;
209}
210EXPORT_SYMBOL(clk_get_rate);
211
212long clk_round_rate(struct clk *clk, unsigned long rate)
213{
214 /*TODO*/
215 return rate;
216}
217EXPORT_SYMBOL(clk_round_rate);
218
219int clk_set_rate(struct clk *clk, unsigned long rate)
220{
221 clk->rate = rate;
222 return 0;
223}
224EXPORT_SYMBOL(clk_set_rate);
225
226static void clk_prcmu_enable(struct clk *clk)
227{
228 void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
229 + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
230
231 writel(1 << clk->prcmu_cg_bit, cg_set_reg);
232}
233
234static void clk_prcmu_disable(struct clk *clk)
235{
236 void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
237 + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
238
239 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
240}
241
242/* ED doesn't have the combined set/clr registers */
243static void clk_prcmu_ed_enable(struct clk *clk)
244{
245 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
246 + clk->prcmu_cg_mgt;
247
248 writel(readl(addr) | PRCM_MGT_ENABLE, addr);
249}
250
251static void clk_prcmu_ed_disable(struct clk *clk)
252{
253 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
254 + clk->prcmu_cg_mgt;
255
256 writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
257}
258
259static struct clkops clk_prcmu_ops = {
260 .enable = clk_prcmu_enable,
261 .disable = clk_prcmu_disable,
262};
263
264static unsigned int clkrst_base[] = {
265 [1] = U8500_CLKRST1_BASE,
266 [2] = U8500_CLKRST2_BASE,
267 [3] = U8500_CLKRST3_BASE,
268 [5] = U8500_CLKRST5_BASE,
269 [6] = U8500_CLKRST6_BASE,
270 [7] = U8500_CLKRST7_BASE_ED,
271};
272
273static void clk_prcc_enable(struct clk *clk)
274{
275 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
276
277 if (clk->prcc_kernel != -1)
278 writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
279
280 if (clk->prcc_bus != -1)
281 writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
282}
283
284static void clk_prcc_disable(struct clk *clk)
285{
286 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
287
288 if (clk->prcc_bus != -1)
289 writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
290
291 if (clk->prcc_kernel != -1)
292 writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
293}
294
295static struct clkops clk_prcc_ops = {
296 .enable = clk_prcc_enable,
297 .disable = clk_prcc_disable,
298};
299
300static struct clk clk_32khz = {
301 .name = "clk_32khz",
302 .rate = 32000,
303};
304
305/*
306 * PRCMU level clock gating
307 */
308
309/* Bank 0 */
310static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
311static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
312static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
313static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
314static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
315static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
316static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
317static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000);
318static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
319static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
320static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
321static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
322static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
323static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
324static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
325static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
326static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
327static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
328static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
329static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
330static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
331static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
332static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
333static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
334static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
335static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
336static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
337static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
338static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
339static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
340
341/* Bank 1 */
342static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
343static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
344
345/*
346 * PRCC level clock gating
347 * Format: per#, clk, PCKEN bit, KCKEN bit, parent
348 */
349
350/* Peripheral Cluster #1 */
351static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
352static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
353static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
354static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
355static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
356static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
357static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
358static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
359static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
360static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
361static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
362static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
363static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
364
365/* Peripheral Cluster #2 */
366
367static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
368static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
369static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
370static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
371static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
372static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
373static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
374static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
375static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
376static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
377static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
378static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
379
380static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
381static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
382static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
383static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
384static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
385static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
386static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
387static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
388static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
389static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
390static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
391static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
392
393/* Peripheral Cluster #3 */
394static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
395static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
396static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
397static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
398static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
399static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
400static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
401static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
402static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
403static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
404static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
405
406/* Peripheral Cluster #4 is in the always on domain */
407
408/* Peripheral Cluster #5 */
409static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
410static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
411static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
412
413/* Peripheral Cluster #6 */
414
415/* MTU ID in data */
416static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
417static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
418static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
419static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
420static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
421static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
422static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
423static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
424static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
425static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
426static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
427static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
428
429/* Peripheral Cluster #7 */
430
431static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
432/* MTU ID in data */
433static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
434static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
435static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
436static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
437
438static struct clk clk_dummy_apb_pclk = {
439 .name = "apb_pclk",
440};
441
442static struct clk_lookup u8500_common_clks[] = {
443 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
444
445 /* Peripheral Cluster #1 */
446 CLK(gpio0, "gpio.0", NULL),
447 CLK(gpio0, "gpio.1", NULL),
448 CLK(slimbus0, "slimbus0", NULL),
449 CLK(i2c2, "nmk-i2c.2", NULL),
450 CLK(sdi0, "sdi0", NULL),
451 CLK(msp0, "msp0", NULL),
452 CLK(i2c1, "nmk-i2c.1", NULL),
453 CLK(uart1, "uart1", NULL),
454 CLK(uart0, "uart0", NULL),
455
456 /* Peripheral Cluster #3 */
457 CLK(gpio2, "gpio.2", NULL),
458 CLK(gpio2, "gpio.3", NULL),
459 CLK(gpio2, "gpio.4", NULL),
460 CLK(gpio2, "gpio.5", NULL),
461 CLK(sdi5, "sdi5", NULL),
462 CLK(uart2, "uart2", NULL),
463 CLK(ske, "ske", NULL),
464 CLK(ske, "nmk-ske-keypad", NULL),
465 CLK(sdi2, "sdi2", NULL),
466 CLK(i2c0, "nmk-i2c.0", NULL),
467 CLK(fsmc, "fsmc", NULL),
468
469 /* Peripheral Cluster #5 */
470 CLK(gpio3, "gpio.8", NULL),
471
472 /* Peripheral Cluster #6 */
473 CLK(hash1, "hash1", NULL),
474 CLK(pka, "pka", NULL),
475 CLK(hash0, "hash0", NULL),
476 CLK(cryp0, "cryp0", NULL),
477
478 /* PRCMU level clock gating */
479
480 /* Bank 0 */
481 CLK(svaclk, "sva", NULL),
482 CLK(siaclk, "sia", NULL),
483 CLK(sgaclk, "sga", NULL),
484 CLK(slimclk, "slim", NULL),
485 CLK(lcdclk, "lcd", NULL),
486 CLK(bmlclk, "bml", NULL),
487 CLK(hsitxclk, "stm-hsi.0", NULL),
488 CLK(hsirxclk, "stm-hsi.1", NULL),
489 CLK(hdmiclk, "hdmi", NULL),
490 CLK(apeatclk, "apeat", NULL),
491 CLK(apetraceclk, "apetrace", NULL),
492 CLK(mcdeclk, "mcde", NULL),
493 CLK(ipi2clk, "ipi2", NULL),
494 CLK(dmaclk, "dma40.0", NULL),
495 CLK(b2r2clk, "b2r2", NULL),
496 CLK(tvclk, "tv", NULL),
497};
498
499static struct clk_lookup u8500_ed_clks[] = {
500 /* Peripheral Cluster #1 */
501 CLK(spi3_ed, "spi3", NULL),
502 CLK(msp1_ed, "msp1", NULL),
503
504 /* Peripheral Cluster #2 */
505 CLK(gpio1_ed, "gpio.6", NULL),
506 CLK(gpio1_ed, "gpio.7", NULL),
507 CLK(ssitx_ed, "ssitx", NULL),
508 CLK(ssirx_ed, "ssirx", NULL),
509 CLK(spi0_ed, "spi0", NULL),
510 CLK(sdi3_ed, "sdi3", NULL),
511 CLK(sdi1_ed, "sdi1", NULL),
512 CLK(msp2_ed, "msp2", NULL),
513 CLK(sdi4_ed, "sdi4", NULL),
514 CLK(pwl_ed, "pwl", NULL),
515 CLK(spi1_ed, "spi1", NULL),
516 CLK(spi2_ed, "spi2", NULL),
517 CLK(i2c3_ed, "nmk-i2c.3", NULL),
518
519 /* Peripheral Cluster #3 */
520 CLK(ssp1_ed, "ssp1", NULL),
521 CLK(ssp0_ed, "ssp0", NULL),
522
523 /* Peripheral Cluster #5 */
524 CLK(usb_ed, "musb-ux500.0", "usb"),
525
526 /* Peripheral Cluster #6 */
527 CLK(dmc_ed, "dmc", NULL),
528 CLK(cryp1_ed, "cryp1", NULL),
529 CLK(rng_ed, "rng", NULL),
530
531 /* Peripheral Cluster #7 */
532 CLK(tzpc0_ed, "tzpc0", NULL),
533 CLK(mtu1_ed, "mtu1", NULL),
534 CLK(mtu0_ed, "mtu0", NULL),
535 CLK(wdg_ed, "wdg", NULL),
536 CLK(cfgreg_ed, "cfgreg", NULL),
537};
538
539static struct clk_lookup u8500_v1_clks[] = {
540 /* Peripheral Cluster #1 */
541 CLK(i2c4, "nmk-i2c.4", NULL),
542 CLK(spi3_v1, "spi3", NULL),
543 CLK(msp1_v1, "msp1", NULL),
544
545 /* Peripheral Cluster #2 */
546 CLK(gpio1_v1, "gpio.6", NULL),
547 CLK(gpio1_v1, "gpio.7", NULL),
548 CLK(ssitx_v1, "ssitx", NULL),
549 CLK(ssirx_v1, "ssirx", NULL),
550 CLK(spi0_v1, "spi0", NULL),
551 CLK(sdi3_v1, "sdi3", NULL),
552 CLK(sdi1_v1, "sdi1", NULL),
553 CLK(msp2_v1, "msp2", NULL),
554 CLK(sdi4_v1, "sdi4", NULL),
555 CLK(pwl_v1, "pwl", NULL),
556 CLK(spi1_v1, "spi1", NULL),
557 CLK(spi2_v1, "spi2", NULL),
558 CLK(i2c3_v1, "nmk-i2c.3", NULL),
559
560 /* Peripheral Cluster #3 */
561 CLK(ssp1_v1, "ssp1", NULL),
562 CLK(ssp0_v1, "ssp0", NULL),
563
564 /* Peripheral Cluster #5 */
565 CLK(usb_v1, "musb-ux500.0", "usb"),
566
567 /* Peripheral Cluster #6 */
568 CLK(mtu1_v1, "mtu1", NULL),
569 CLK(mtu0_v1, "mtu0", NULL),
570 CLK(cfgreg_v1, "cfgreg", NULL),
571 CLK(hash1, "hash1", NULL),
572 CLK(unipro_v1, "unipro", NULL),
573 CLK(rng_v1, "rng", NULL),
574
575 /* PRCMU level clock gating */
576
577 /* Bank 0 */
578 CLK(uniproclk, "uniproclk", NULL),
579 CLK(dsialtclk, "dsialt", NULL),
580
581 /* Bank 1 */
582 CLK(rngclk, "rng", NULL),
583 CLK(uiccclk, "uicc", NULL),
584};
585
586#ifdef CONFIG_DEBUG_FS
587/*
588 * debugfs support to trace clock tree hierarchy and attributes with
589 * powerdebug
590 */
591static struct dentry *clk_debugfs_root;
592
593void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
594{
595 while (num--) {
596 /* Check that the clock has not been already registered */
597 if (!(cl->clk->list.prev != cl->clk->list.next))
598 list_add_tail(&cl->clk->list, &clk_list);
599
600 cl++;
601 }
602}
603
604static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
605 size_t size, loff_t *off)
606{
607 struct clk *clk = file->f_dentry->d_inode->i_private;
608 char cusecount[128];
609 unsigned int len;
610
611 len = sprintf(cusecount, "%u\n", clk->enabled);
612 return simple_read_from_buffer(buf, size, off, cusecount, len);
613}
614
615static ssize_t rate_dbg_read(struct file *file, char __user *buf,
616 size_t size, loff_t *off)
617{
618 struct clk *clk = file->f_dentry->d_inode->i_private;
619 char crate[128];
620 unsigned int rate;
621 unsigned int len;
622
623 rate = clk_get_rate(clk);
624 len = sprintf(crate, "%u\n", rate);
625 return simple_read_from_buffer(buf, size, off, crate, len);
626}
627
628static const struct file_operations usecount_fops = {
629 .read = usecount_dbg_read,
630};
631
632static const struct file_operations set_rate_fops = {
633 .read = rate_dbg_read,
634};
635
636static struct dentry *clk_debugfs_register_dir(struct clk *c,
637 struct dentry *p_dentry)
638{
639 struct dentry *d, *clk_d;
640 const char *p = c->name;
641
642 if (!p)
643 p = "BUG";
644
645 clk_d = debugfs_create_dir(p, p_dentry);
646 if (!clk_d)
647 return NULL;
648
649 d = debugfs_create_file("usecount", S_IRUGO,
650 clk_d, c, &usecount_fops);
651 if (!d)
652 goto err_out;
653 d = debugfs_create_file("rate", S_IRUGO,
654 clk_d, c, &set_rate_fops);
655 if (!d)
656 goto err_out;
657 /*
658 * TODO : not currently available in ux500
659 * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
660 * if (!d)
661 * goto err_out;
662 */
663
664 return clk_d;
665
666err_out:
667 debugfs_remove_recursive(clk_d);
668 return NULL;
669}
670
671static int clk_debugfs_register_one(struct clk *c)
672{
673 struct clk *pa = c->parent_periph;
674 struct clk *bpa = c->parent_cluster;
675
676 if (!(bpa && !pa)) {
677 c->dent = clk_debugfs_register_dir(c,
678 pa ? pa->dent : clk_debugfs_root);
679 if (!c->dent)
680 return -ENOMEM;
681 }
682
683 if (bpa) {
684 c->dent_bus = clk_debugfs_register_dir(c,
685 bpa->dent_bus ? bpa->dent_bus : bpa->dent);
686 if ((!c->dent_bus) && (c->dent)) {
687 debugfs_remove_recursive(c->dent);
688 c->dent = NULL;
689 return -ENOMEM;
690 }
691 }
692 return 0;
693}
694
695static int clk_debugfs_register(struct clk *c)
696{
697 int err;
698 struct clk *pa = c->parent_periph;
699 struct clk *bpa = c->parent_cluster;
700
701 if (pa && (!pa->dent && !pa->dent_bus)) {
702 err = clk_debugfs_register(pa);
703 if (err)
704 return err;
705 }
706
707 if (bpa && (!bpa->dent && !bpa->dent_bus)) {
708 err = clk_debugfs_register(bpa);
709 if (err)
710 return err;
711 }
712
713 if ((!c->dent) && (!c->dent_bus)) {
714 err = clk_debugfs_register_one(c);
715 if (err)
716 return err;
717 }
718 return 0;
719}
720
721static int __init clk_debugfs_init(void)
722{
723 struct clk *c;
724 struct dentry *d;
725 int err;
726
727 d = debugfs_create_dir("clock", NULL);
728 if (!d)
729 return -ENOMEM;
730 clk_debugfs_root = d;
731
732 list_for_each_entry(c, &clk_list, list) {
733 err = clk_debugfs_register(c);
734 if (err)
735 goto err_out;
736 }
737 return 0;
738err_out:
739 debugfs_remove_recursive(clk_debugfs_root);
740 return err;
741}
742
743late_initcall(clk_debugfs_init);
744#endif /* defined(CONFIG_DEBUG_FS) */
745
746unsigned long clk_smp_twd_rate = 400000000;
747
748unsigned long clk_smp_twd_get_rate(struct clk *clk)
749{
750 return clk_smp_twd_rate;
751}
752
753static struct clk clk_smp_twd = {
754 .get_rate = clk_smp_twd_get_rate,
755 .name = "smp_twd",
756};
757
758static struct clk_lookup clk_smp_twd_lookup = {
759 .dev_id = "smp_twd",
760 .clk = &clk_smp_twd,
761};
762
763#ifdef CONFIG_CPU_FREQ
764
765static int clk_twd_cpufreq_transition(struct notifier_block *nb,
766 unsigned long state, void *data)
767{
768 struct cpufreq_freqs *f = data;
769
770 if (state == CPUFREQ_PRECHANGE) {
771 /* Save frequency in simple Hz */
772 clk_smp_twd_rate = f->new * 1000;
773 }
774
775 return NOTIFY_OK;
776}
777
778static struct notifier_block clk_twd_cpufreq_nb = {
779 .notifier_call = clk_twd_cpufreq_transition,
780};
781
782static int clk_init_smp_twd_cpufreq(void)
783{
784 return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
785 CPUFREQ_TRANSITION_NOTIFIER);
786}
787late_initcall(clk_init_smp_twd_cpufreq);
788
789#endif
790
791int __init clk_init(void)
792{
793 if (cpu_is_u8500ed()) {
794 clk_prcmu_ops.enable = clk_prcmu_ed_enable;
795 clk_prcmu_ops.disable = clk_prcmu_ed_disable;
796 clk_per6clk.rate = 100000000;
797 } else if (cpu_is_u5500()) {
798 /* Clock tree for U5500 not implemented yet */
799 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
800 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
801 clk_uartclk.rate = 36360000;
802 clk_sdmmcclk.rate = 99900000;
803 }
804
805 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
806 if (cpu_is_u8500ed())
807 clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
808 else
809 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
810
811 clkdev_add(&clk_smp_twd_lookup);
812
813#ifdef CONFIG_DEBUG_FS
814 clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
815 if (cpu_is_u8500ed())
816 clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
817 else
818 clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
819#endif
820 return 0;
821}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
new file mode 100644
index 00000000000..07449070522
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.h
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2010 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10/**
11 * struct clkops - ux500 clock operations
12 * @enable: function to enable the clock
13 * @disable: function to disable the clock
14 * @get_rate: function to get the current clock rate
15 *
16 * This structure contains function pointers to functions that will be used to
17 * control the clock. All of these functions are optional. If get_rate is
18 * NULL, the rate in the struct clk will be used.
19 */
20struct clkops {
21 void (*enable) (struct clk *);
22 void (*disable) (struct clk *);
23 unsigned long (*get_rate) (struct clk *);
24};
25
26/**
27 * struct clk - ux500 clock structure
28 * @ops: pointer to clkops struct used to control this clock
29 * @name: name, for debugging
30 * @enabled: refcount. positive if enabled, zero if disabled
31 * @get_rate: custom callback for getting the clock rate
32 * @data: custom per-clock data for example for the get_rate
33 * callback
34 * @rate: fixed rate for clocks which don't implement
35 * ops->getrate
36 * @prcmu_cg_off: address offset of the combined enable/disable register
37 * (used on u8500v1)
38 * @prcmu_cg_bit: bit in the combined enable/disable register (used on
39 * u8500v1)
40 * @prcmu_cg_mgt: address of the enable/disable register (used on
41 * u8500ed)
42 * @cluster: peripheral cluster number
43 * @prcc_bus: bit for the bus clock in the peripheral's CLKRST
44 * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST.
45 * -1 if no kernel clock exists.
46 * @parent_cluster: pointer to parent's cluster clk struct
47 * @parent_periph: pointer to parent's peripheral clk struct
48 *
49 * Peripherals are organised into clusters, and each cluster has an associated
50 * bus clock. Some peripherals also have a parent peripheral clock.
51 *
52 * In order to enable a clock for a peripheral, we need to enable:
53 * (1) the parent cluster (bus) clock at the PRCMU level
54 * (2) the parent peripheral clock (if any) at the PRCMU level
55 * (3) the peripheral's bus & kernel clock at the PRCC level
56 *
57 * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
58 * of the cluster and peripheral clocks, and hooking these as the parents of
59 * the individual peripheral clocks.
60 *
61 * (3) is handled by specifying the bits in the PRCC control registers required
62 * to enable these clocks and modifying them in the ->enable and
63 * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
64 *
65 * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
66 * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
67 * prcc, and parent pointers are only used for the PRCC-level clocks.
68 */
69struct clk {
70 const struct clkops *ops;
71 const char *name;
72 unsigned int enabled;
73 unsigned long (*get_rate)(struct clk *);
74 void *data;
75
76 unsigned long rate;
77 struct list_head list;
78
79 /* These three are only for PRCMU clks */
80
81 unsigned int prcmu_cg_off;
82 unsigned int prcmu_cg_bit;
83 unsigned int prcmu_cg_mgt;
84
85 /* The rest are only for PRCC clks */
86
87 int cluster;
88 unsigned int prcc_bus;
89 unsigned int prcc_kernel;
90
91 struct clk *parent_cluster;
92 struct clk *parent_periph;
93#if defined(CONFIG_DEBUG_FS)
94 struct dentry *dent; /* For visible tree hierarchy */
95 struct dentry *dent_bus; /* For visible tree hierarchy */
96#endif
97};
98
99#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
100struct clk clk_##_name = { \
101 .name = #_name, \
102 .ops = &clk_prcmu_ops, \
103 .prcmu_cg_off = _cg_off, \
104 .prcmu_cg_bit = _cg_bit, \
105 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
106 }
107
108#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
109struct clk clk_##_name = { \
110 .name = #_name, \
111 .ops = &clk_prcmu_ops, \
112 .prcmu_cg_off = _cg_off, \
113 .prcmu_cg_bit = _cg_bit, \
114 .rate = _rate, \
115 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
116 }
117
118#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
119struct clk clk_##_name = { \
120 .name = #_name, \
121 .ops = &clk_prcc_ops, \
122 .cluster = _pclust, \
123 .prcc_bus = _bus_en, \
124 .prcc_kernel = _kernel_en, \
125 .parent_cluster = &clk_per##_pclust##clk, \
126 .parent_periph = _kernclk \
127 }
128
129#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
130struct clk clk_##_name = { \
131 .name = #_name, \
132 .ops = &clk_prcc_ops, \
133 .cluster = _pclust, \
134 .prcc_bus = _bus_en, \
135 .prcc_kernel = _kernel_en, \
136 .parent_cluster = &clk_per##_pclust##clk, \
137 .parent_periph = _kernclk, \
138 .get_rate = _callback, \
139 .data = (void *) _data \
140 }
141
142
143#define CLK(_clk, _devname, _conname) \
144 { \
145 .clk = &clk_##_clk, \
146 .dev_id = _devname, \
147 .con_id = _conname, \
148 }
149
150int __init clk_db8500_ed_fixup(void);
151int __init clk_init(void);
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
new file mode 100644
index 00000000000..22705d246fc
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -0,0 +1,227 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/platform_device.h>
9#include <linux/amba/bus.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12
13#include <asm/mach/map.h>
14#include <asm/pmu.h>
15
16#include <plat/gpio.h>
17
18#include <mach/hardware.h>
19#include <mach/devices.h>
20#include <mach/setup.h>
21#include <mach/irqs.h>
22#include <mach/usb.h>
23
24#include "devices-db5500.h"
25#include "ste-dma40-db5500.h"
26
27static struct map_desc u5500_uart_io_desc[] __initdata = {
28 __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
29 __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K),
30};
31
32static struct map_desc u5500_io_desc[] __initdata = {
33 __IO_DEV_DESC(U5500_GIC_CPU_BASE, SZ_4K),
34 __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K),
35 __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K),
36 __IO_DEV_DESC(U5500_TWD_BASE, SZ_4K),
37 __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K),
38 __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K),
39 __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K),
40
41 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
42 __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
43 __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
44 __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
45 __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
46 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
47 __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
48};
49
50static struct resource db5500_pmu_resources[] = {
51 [0] = {
52 .start = IRQ_DB5500_PMU0,
53 .end = IRQ_DB5500_PMU0,
54 .flags = IORESOURCE_IRQ,
55 },
56 [1] = {
57 .start = IRQ_DB5500_PMU1,
58 .end = IRQ_DB5500_PMU1,
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static struct platform_device db5500_pmu_device = {
64 .name = "arm-pmu",
65 .id = ARM_PMU_DEVICE_CPU,
66 .num_resources = ARRAY_SIZE(db5500_pmu_resources),
67 .resource = db5500_pmu_resources,
68};
69
70static struct resource mbox0_resources[] = {
71 {
72 .name = "mbox_peer",
73 .start = U5500_MBOX0_PEER_START,
74 .end = U5500_MBOX0_PEER_END,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .name = "mbox_local",
79 .start = U5500_MBOX0_LOCAL_START,
80 .end = U5500_MBOX0_LOCAL_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .name = "mbox_irq",
85 .start = MBOX_PAIR0_VIRT_IRQ,
86 .end = MBOX_PAIR0_VIRT_IRQ,
87 .flags = IORESOURCE_IRQ,
88 }
89};
90
91static struct resource mbox1_resources[] = {
92 {
93 .name = "mbox_peer",
94 .start = U5500_MBOX1_PEER_START,
95 .end = U5500_MBOX1_PEER_END,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .name = "mbox_local",
100 .start = U5500_MBOX1_LOCAL_START,
101 .end = U5500_MBOX1_LOCAL_END,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .name = "mbox_irq",
106 .start = MBOX_PAIR1_VIRT_IRQ,
107 .end = MBOX_PAIR1_VIRT_IRQ,
108 .flags = IORESOURCE_IRQ,
109 }
110};
111
112static struct resource mbox2_resources[] = {
113 {
114 .name = "mbox_peer",
115 .start = U5500_MBOX2_PEER_START,
116 .end = U5500_MBOX2_PEER_END,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .name = "mbox_local",
121 .start = U5500_MBOX2_LOCAL_START,
122 .end = U5500_MBOX2_LOCAL_END,
123 .flags = IORESOURCE_MEM,
124 },
125 {
126 .name = "mbox_irq",
127 .start = MBOX_PAIR2_VIRT_IRQ,
128 .end = MBOX_PAIR2_VIRT_IRQ,
129 .flags = IORESOURCE_IRQ,
130 }
131};
132
133static struct platform_device mbox0_device = {
134 .id = 0,
135 .name = "mbox",
136 .resource = mbox0_resources,
137 .num_resources = ARRAY_SIZE(mbox0_resources),
138};
139
140static struct platform_device mbox1_device = {
141 .id = 1,
142 .name = "mbox",
143 .resource = mbox1_resources,
144 .num_resources = ARRAY_SIZE(mbox1_resources),
145};
146
147static struct platform_device mbox2_device = {
148 .id = 2,
149 .name = "mbox",
150 .resource = mbox2_resources,
151 .num_resources = ARRAY_SIZE(mbox2_resources),
152};
153
154static struct platform_device *db5500_platform_devs[] __initdata = {
155 &db5500_pmu_device,
156 &mbox0_device,
157 &mbox1_device,
158 &mbox2_device,
159};
160
161static resource_size_t __initdata db5500_gpio_base[] = {
162 U5500_GPIOBANK0_BASE,
163 U5500_GPIOBANK1_BASE,
164 U5500_GPIOBANK2_BASE,
165 U5500_GPIOBANK3_BASE,
166 U5500_GPIOBANK4_BASE,
167 U5500_GPIOBANK5_BASE,
168 U5500_GPIOBANK6_BASE,
169 U5500_GPIOBANK7_BASE,
170};
171
172static void __init db5500_add_gpios(void)
173{
174 struct nmk_gpio_platform_data pdata = {
175 /* No custom data yet */
176 };
177
178 dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base),
179 IRQ_DB5500_GPIO0, &pdata);
180}
181
182void __init u5500_map_io(void)
183{
184 /*
185 * Map the UARTs early so that the DEBUG_LL stuff continues to work.
186 */
187 iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc));
188
189 ux500_map_io();
190
191 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
192
193 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
194}
195
196static int usb_db5500_rx_dma_cfg[] = {
197 DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
198 DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
199 DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
200 DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
201 DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
202 DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
203 DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
204 DB5500_DMA_DEV38_USB_OTG_IEP_8
205};
206
207static int usb_db5500_tx_dma_cfg[] = {
208 DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
209 DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
210 DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
211 DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
212 DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
213 DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
214 DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
215 DB5500_DMA_DEV38_USB_OTG_OEP_8
216};
217
218void __init u5500_init_devices(void)
219{
220 db5500_add_gpios();
221 db5500_dma_init();
222 db5500_add_rtc();
223 db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
224
225 platform_add_devices(db5500_platform_devs,
226 ARRAY_SIZE(db5500_platform_devs));
227}
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
new file mode 100644
index 00000000000..0c4bccd02b9
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -0,0 +1,79 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __DEVICES_DB5500_H
9#define __DEVICES_DB5500_H
10
11#include "devices-common.h"
12
13#define db5500_add_i2c1(pdata) \
14 dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
15#define db5500_add_i2c2(pdata) \
16 dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
17#define db5500_add_i2c3(pdata) \
18 dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
19
20#define db5500_add_msp0_i2s(pdata) \
21 dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
22#define db5500_add_msp1_i2s(pdata) \
23 dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
24#define db5500_add_msp2_i2s(pdata) \
25 dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
26
27#define db5500_add_msp0_spi(pdata) \
28 dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
29#define db5500_add_msp1_spi(pdata) \
30 dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
31#define db5500_add_msp2_spi(pdata) \
32 dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
33
34#define db5500_add_rtc() \
35 dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
36
37#define db5500_add_usb(rx_cfg, tx_cfg) \
38 ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
39
40#define db5500_add_sdi0(pdata) \
41 dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata, \
42 0x10480180)
43#define db5500_add_sdi1(pdata) \
44 dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata, \
45 0x10480180)
46#define db5500_add_sdi2(pdata) \
47 dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata \
48 0x10480180)
49#define db5500_add_sdi3(pdata) \
50 dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata \
51 0x10480180)
52#define db5500_add_sdi4(pdata) \
53 dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata \
54 0x10480180)
55
56/* This one has a bad peripheral ID in the U5500 silicon */
57#define db5500_add_spi0(pdata) \
58 dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata, \
59 0x10080023)
60#define db5500_add_spi1(pdata) \
61 dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata, \
62 0x10080023)
63#define db5500_add_spi2(pdata) \
64 dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata \
65 0x10080023)
66#define db5500_add_spi3(pdata) \
67 dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata \
68 0x10080023)
69
70#define db5500_add_uart0(plat) \
71 dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
72#define db5500_add_uart1(plat) \
73 dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1, plat)
74#define db5500_add_uart2(plat) \
75 dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2, plat)
76#define db5500_add_uart3(plat) \
77 dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat)
78
79#endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
new file mode 100644
index 00000000000..1cfab68ae41
--- /dev/null
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson
7 *
8 * License terms: GNU General Public License (GPL), version 2
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13
14#include <plat/ste_dma40.h>
15#include <mach/setup.h>
16#include <mach/hardware.h>
17
18#include "ste-dma40-db5500.h"
19
20static struct resource dma40_resources[] = {
21 [0] = {
22 .start = U5500_DMA_BASE,
23 .end = U5500_DMA_BASE + SZ_4K - 1,
24 .flags = IORESOURCE_MEM,
25 .name = "base",
26 },
27 [1] = {
28 .start = U5500_DMA_LCPA_BASE,
29 .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
30 .flags = IORESOURCE_MEM,
31 .name = "lcpa",
32 },
33 [2] = {
34 .start = IRQ_DB5500_DMA,
35 .end = IRQ_DB5500_DMA,
36 .flags = IORESOURCE_IRQ
37 }
38};
39
40/* Default configuration for physical memcpy */
41static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
42 .mode = STEDMA40_MODE_PHYSICAL,
43 .dir = STEDMA40_MEM_TO_MEM,
44
45 .src_info.data_width = STEDMA40_BYTE_WIDTH,
46 .src_info.psize = STEDMA40_PSIZE_PHY_1,
47 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
48
49 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
50 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
51 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
52};
53
54/* Default configuration for logical memcpy */
55static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
56 .dir = STEDMA40_MEM_TO_MEM,
57
58 .src_info.data_width = STEDMA40_BYTE_WIDTH,
59 .src_info.psize = STEDMA40_PSIZE_LOG_1,
60 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
61
62 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
63 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
64 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
65};
66
67/*
68 * Mapping between soruce event lines and physical device address This was
69 * created assuming that the event line is tied to a device and therefore the
70 * address is constant, however this is not true for at least USB, and the
71 * values are just placeholders for USB. This table is preserved and used for
72 * now.
73 */
74static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
75 [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
76 [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
77 [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
78 [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
79 [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
80 [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
81 [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
82 [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
83 [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
84};
85
86/* Mapping between destination event lines and physical device address */
87static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
88 [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
89 [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
90 [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
91 [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
92 [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
93 [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
94 [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
95 [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
96 [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
97};
98
99static int dma40_memcpy_event[] = {
100 DB5500_DMA_MEMCPY_TX_1,
101 DB5500_DMA_MEMCPY_TX_2,
102 DB5500_DMA_MEMCPY_TX_3,
103 DB5500_DMA_MEMCPY_TX_4,
104 DB5500_DMA_MEMCPY_TX_5,
105};
106
107static struct stedma40_platform_data dma40_plat_data = {
108 .dev_len = ARRAY_SIZE(dma40_rx_map),
109 .dev_rx = dma40_rx_map,
110 .dev_tx = dma40_tx_map,
111 .memcpy = dma40_memcpy_event,
112 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
113 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
114 .memcpy_conf_log = &dma40_memcpy_conf_log,
115 .disabled_channels = {-1},
116};
117
118static struct platform_device dma40_device = {
119 .dev = {
120 .platform_data = &dma40_plat_data,
121 },
122 .name = "dma40",
123 .id = 0,
124 .num_resources = ARRAY_SIZE(dma40_resources),
125 .resource = dma40_resources
126};
127
128void __init db5500_dma_init(void)
129{
130 int ret;
131
132 ret = platform_device_register(&dma40_device);
133 if (ret)
134 dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
135
136}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
new file mode 100644
index 00000000000..6ad98329410
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -0,0 +1,137 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB5500_REGS_H
8#define __MACH_DB5500_REGS_H
9
10#define U5500_PER1_BASE 0xA0020000
11#define U5500_PER2_BASE 0xA0010000
12#define U5500_PER3_BASE 0x80140000
13#define U5500_PER4_BASE 0x80150000
14#define U5500_PER5_BASE 0x80100000
15#define U5500_PER6_BASE 0x80120000
16
17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000
20#define U5500_STM_BASE 0x90020000
21#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
22#define U5500_MCDE_BASE 0xA0400000
23#define U5500_MODEM_BASE 0xB0000000
24#define U5500_L2CC_BASE 0xA0412000
25#define U5500_SCU_BASE 0xA0410000
26#define U5500_DSI1_BASE 0xA0401000
27#define U5500_DSI2_BASE 0xA0402000
28#define U5500_SIA_BASE 0xA0100000
29#define U5500_SVA_BASE 0x80200000
30#define U5500_HSEM_BASE 0xA0000000
31#define U5500_NAND0_BASE 0x60000000
32#define U5500_NAND1_BASE 0x70000000
33#define U5500_TWD_BASE 0xa0410600
34#define U5500_ICN_BASE 0xA0040000
35#define U5500_B2R2_BASE 0xa0200000
36#define U5500_BOOT_ROM_BASE 0x90000000
37
38#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
39#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
40#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
41#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
42#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
43#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
44#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
45#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
46
47#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
48#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
49#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
50
51#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
52#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
53#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
54#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
55
56#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
57#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
58#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
59#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
60#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
61#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
62#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
63#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
64#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
65#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
66#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
67#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
68
69#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
70#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
71#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
72#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
73#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
74#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
75#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
76#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
77#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
78#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
79#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
80#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
81#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
82#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
83#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
84#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
85#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
86
87#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
88#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
89#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
90#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
91#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
92#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
93#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
94#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
95#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
96#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
97#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
98
99#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
100#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
101#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
102#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
103#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
104#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
105#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
106#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
107
108#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000)
109#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40)
110#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F)
111#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
112#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F)
113#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80)
114#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F)
115#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
116#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF)
117#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00)
118#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F)
119#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
120#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
121
122#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
123#define U5500_ACCCON_BASE (0xBFFF1000)
124#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
125#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
126
127#define U5500_ESRAM_BASE 0x40000000
128#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
129#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
130
131#define U5500_MCDE_SIZE 0x1000
132#define U5500_DSI_LINK_SIZE 0x1000
133#define U5500_DSI_LINK_COUNT 0x2
134#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
135#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
136
137#endif
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
new file mode 100644
index 00000000000..071bba94f72
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -0,0 +1,20 @@
1/*
2 * Low-level IRQ helper macros for U8500 platforms
3 *
4 * Copyright (C) 2009 ST-Ericsson.
5 *
6 * This file is a copy of ARM Realview platform.
7 * -just satisfied checkpatch script.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13#include <mach/hardware.h>
14#include <asm/hardware/entry-macro-gic.S>
15
16 .macro disable_fiq
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
new file mode 100644
index 00000000000..3c4cd31ad9f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_ARCH_GPIO_H
2#define __ASM_ARCH_GPIO_H
3
4/*
5 * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough
6 * room for a couple of GPIO expanders.
7 */
8#define ARCH_NR_GPIOS 350
9
10#include <plat/gpio.h>
11
12#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100644
index 00000000000..1cf3f44ce5b
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-u8500/include/mach/io.h
3 *
4 * Copyright (C) 1997-1999 Russell King
5 *
6 * Modifications:
7 * 06-12-1997 RMK Created.
8 * 07-04-1999 RMK Major cleanup
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#define IO_SPACE_LIMIT 0xffffffff
14
15/*
16 * We don't actually have real ISA nor PCI buses, but there is so many
17 * drivers out there that might just work if we fake them...
18 */
19#define __io(a) __typesafe_io(a)
20#define __mem_pci(a) (a)
21
22#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
new file mode 100644
index 00000000000..29d972c7717
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_IRQS_BOARD_U5500_H
8#define __MACH_IRQS_BOARD_U5500_H
9
10#define AB5500_NR_IRQS 5
11#define IRQ_AB5500_BASE IRQ_BOARD_START
12#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
13
14#define U5500_IRQ_END IRQ_AB5500_END
15
16#if IRQ_BOARD_END < U5500_IRQ_END
17#undef IRQ_BOARD_END
18#define IRQ_BOARD_END U5500_IRQ_END
19#endif
20
21#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644
index 00000000000..77239776a6f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,113 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB5500_H
9#define __MACH_IRQS_DB5500_H
10
11#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
14#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
23#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
36#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
37#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
38#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
39#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
40#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
41#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
42#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
43#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
44#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
45#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
46#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
50#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
55#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
56#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
57#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
58#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
59#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
60#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
65#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
66#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
67#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
68#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
69#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
70#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
71#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
72#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
73#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
74#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
75#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
76#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
77#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
78#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
79#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
80#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
81#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
82#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
85
86#ifdef CONFIG_UX500_SOC_DB5500
87
88/*
89 * After the GPIO ones we reserve a range of IRQ:s in which virtual
90 * IRQ:s representing modem IRQ:s can be allocated
91 */
92#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
93#define IRQ_MODEM_EVENTS_NBR 72
94#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
95
96/* List of virtual IRQ:s that are allocated from the range above */
97#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
98#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
99#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
100
101/*
102 * We may have several SoCs, but only one will run at a
103 * time, so the one with most IRQs will bump this ahead,
104 * but the IRQ_SOC_START remains the same for either SoC.
105 */
106#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
107#undef IRQ_SOC_END
108#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
109#endif
110
111#endif /* CONFIG_UX500_SOC_DB5500 */
112
113#endif
diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
new file mode 100644
index 00000000000..7f9da4d2fbd
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __INC_STE_MBOX_H
9#define __INC_STE_MBOX_H
10
11#define MBOX_BUF_SIZE 16
12#define MBOX_NAME_SIZE 8
13
14/**
15 * mbox_recv_cb_t - Definition of the mailbox callback.
16 * @mbox_msg: The mailbox message.
17 * @priv: The clients private data as specified in the call to mbox_setup.
18 *
19 * This function will be called upon reception of new mailbox messages.
20 */
21typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
22
23/**
24 * struct mbox - Mailbox instance struct
25 * @list: Linked list head.
26 * @pdev: Pointer to device struct.
27 * @cb: Callback function. Will be called
28 * when new data is received.
29 * @client_data: Clients private data. Will be sent back
30 * in the callback function.
31 * @virtbase_peer: Virtual address for outgoing mailbox.
32 * @virtbase_local: Virtual address for incoming mailbox.
33 * @buffer: Then internal queue for outgoing messages.
34 * @name: Name of this mailbox.
35 * @buffer_available: Completion variable to achieve "blocking send".
36 * This variable will be signaled when there is
37 * internal buffer space available.
38 * @client_blocked: To keep track if any client is currently
39 * blocked.
40 * @lock: Spinlock to protect this mailbox instance.
41 * @write_index: Index in internal buffer to write to.
42 * @read_index: Index in internal buffer to read from.
43 * @allocated: Indicates whether this particular mailbox
44 * id has been allocated by someone.
45 */
46struct mbox {
47 struct list_head list;
48 struct platform_device *pdev;
49 mbox_recv_cb_t *cb;
50 void *client_data;
51 void __iomem *virtbase_peer;
52 void __iomem *virtbase_local;
53 u32 buffer[MBOX_BUF_SIZE];
54 char name[MBOX_NAME_SIZE];
55 struct completion buffer_available;
56 u8 client_blocked;
57 spinlock_t lock;
58 u8 write_index;
59 u8 read_index;
60 bool allocated;
61};
62
63/**
64 * mbox_setup - Set up a mailbox and return its instance.
65 * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU,
66 * 2 for modem DSP.
67 * @mbox_cb: Pointer to the callback function to be called when a new message
68 * is received.
69 * @priv: Client user data which will be returned in the callback.
70 *
71 * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
72 */
73struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
74
75/**
76 * mbox_send - Send a mailbox message.
77 * @mbox: Mailbox instance (returned by mbox_setup)
78 * @mbox_msg: The mailbox message to send.
79 * @block: Specifies whether this call will block until send is possible,
80 * or return an error if the mailbox buffer is full.
81 *
82 * Returns 0 on success or a negative error code on error. -ENOMEM indicates
83 * that the internal buffer is full and you have to try again later (or
84 * specify "block" in order to block until send is possible).
85 */
86int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
87
88#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
new file mode 100644
index 00000000000..2ef697a6700
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/memory.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9#ifndef __ASM_ARCH_MEMORY_H
10#define __ASM_ARCH_MEMORY_H
11
12/*
13 * Physical DRAM offset.
14 */
15#define PLAT_PHYS_OFFSET UL(0x00000000)
16#define BUS_OFFSET UL(0x00000000)
17
18#endif
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
new file mode 100644
index 00000000000..c0cd8006f1a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/system.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson.
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8#ifndef __ASM_ARCH_SYSTEM_H
9#define __ASM_ARCH_SYSTEM_H
10
11static inline void arch_idle(void)
12{
13 /*
14 * This should do all the clock switching
15 * and wait for interrupt tricks
16 */
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode, const char *cmd)
21{
22 /* yet to be implemented - TODO */
23}
24
25#endif
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
new file mode 100644
index 00000000000..d3739d41881
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/usb.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#ifndef __ASM_ARCH_USB_H
8#define __ASM_ARCH_USB_H
9
10#include <linux/dmaengine.h>
11
12#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
13#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
14
15struct ux500_musb_board_data {
16 void **dma_rx_param_array;
17 void **dma_tx_param_array;
18 u32 num_rx_channels;
19 u32 num_tx_channels;
20 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
21};
22
23void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
24 int *dma_tx_cfg);
25#endif
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
new file mode 100644
index 00000000000..a4945cb4117
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
new file mode 100644
index 00000000000..5ba113309a0
--- /dev/null
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2008-2009 ST-Ericsson
3 * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
4 *
5 * This file is heavily based on relaview platform, almost a copy.
6 *
7 * Copyright (C) 2002 ARM Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/clockchips.h>
16
17#include <asm/irq.h>
18#include <asm/smp_twd.h>
19#include <asm/localtimer.h>
20
21/*
22 * Setup the local clock events for a CPU.
23 */
24int __cpuinit local_timer_setup(struct clock_event_device *evt)
25{
26 evt->irq = IRQ_LOCALTIMER;
27 twd_timer_setup(evt);
28 return 0;
29}
diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
new file mode 100644
index 00000000000..2b2d51caf9d
--- /dev/null
+++ b/arch/arm/mach-ux500/mbox-db5500.c
@@ -0,0 +1,565 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8/*
9 * Mailbox nomenclature:
10 *
11 * APE MODEM
12 * mbox pairX
13 * ..........................
14 * . .
15 * . peer .
16 * . send ---- .
17 * . --> | | .
18 * . | | .
19 * . ---- .
20 * . .
21 * . local .
22 * . rec ---- .
23 * . | | <-- .
24 * . | | .
25 * . ---- .
26 * .........................
27 */
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/platform_device.h>
38#include <linux/debugfs.h>
39#include <linux/seq_file.h>
40#include <linux/completion.h>
41#include <mach/mbox-db5500.h>
42
43#define MBOX_NAME "mbox"
44
45#define MBOX_FIFO_DATA 0x000
46#define MBOX_FIFO_ADD 0x004
47#define MBOX_FIFO_REMOVE 0x008
48#define MBOX_FIFO_THRES_FREE 0x00C
49#define MBOX_FIFO_THRES_OCCUP 0x010
50#define MBOX_FIFO_STATUS 0x014
51
52#define MBOX_DISABLE_IRQ 0x4
53#define MBOX_ENABLE_IRQ 0x0
54#define MBOX_LATCH 1
55
56/* Global list of all mailboxes */
57static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
58
59static struct mbox *get_mbox_with_id(u8 id)
60{
61 u8 i;
62 struct list_head *pos = &mboxs;
63 for (i = 0; i <= id; i++)
64 pos = pos->next;
65
66 return (struct mbox *) list_entry(pos, struct mbox, list);
67}
68
69int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
70{
71 int res = 0;
72
73 spin_lock(&mbox->lock);
74
75 dev_dbg(&(mbox->pdev->dev),
76 "About to buffer 0x%X to mailbox 0x%X."
77 " ri = %d, wi = %d\n",
78 mbox_msg, (u32)mbox, mbox->read_index,
79 mbox->write_index);
80
81 /* Check if write buffer is full */
82 while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
83 if (!block) {
84 dev_dbg(&(mbox->pdev->dev),
85 "Buffer full in non-blocking call! "
86 "Returning -ENOMEM!\n");
87 res = -ENOMEM;
88 goto exit;
89 }
90 spin_unlock(&mbox->lock);
91 dev_dbg(&(mbox->pdev->dev),
92 "Buffer full in blocking call! Sleeping...\n");
93 mbox->client_blocked = 1;
94 wait_for_completion(&mbox->buffer_available);
95 dev_dbg(&(mbox->pdev->dev),
96 "Blocking send was woken up! Trying again...\n");
97 spin_lock(&mbox->lock);
98 }
99
100 mbox->buffer[mbox->write_index] = mbox_msg;
101 mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
102
103 /*
104 * Indicate that we want an IRQ as soon as there is a slot
105 * in the FIFO
106 */
107 writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
108
109exit:
110 spin_unlock(&mbox->lock);
111 return res;
112}
113EXPORT_SYMBOL(mbox_send);
114
115#if defined(CONFIG_DEBUG_FS)
116/*
117 * Expected input: <value> <nbr sends>
118 * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
119 */
120static ssize_t mbox_write_fifo(struct device *dev,
121 struct device_attribute *attr,
122 const char *buf,
123 size_t count)
124{
125 unsigned long mbox_mess;
126 unsigned long nbr_sends;
127 unsigned long i;
128 char int_buf[16];
129 char *token;
130 char *val;
131
132 struct mbox *mbox = (struct mbox *) dev->platform_data;
133
134 strncpy((char *) &int_buf, buf, sizeof(int_buf));
135 token = (char *) &int_buf;
136
137 /* Parse message */
138 val = strsep(&token, " ");
139 if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
140 mbox_mess = 0xDEADBEEF;
141
142 val = strsep(&token, " ");
143 if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
144 nbr_sends = 1;
145
146 dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
147 mbox_mess, nbr_sends, (u32) mbox);
148
149 for (i = 0; i < nbr_sends; i++)
150 mbox_send(mbox, mbox_mess, true);
151
152 return count;
153}
154
155static ssize_t mbox_read_fifo(struct device *dev,
156 struct device_attribute *attr,
157 char *buf)
158{
159 int mbox_value;
160 struct mbox *mbox = (struct mbox *) dev->platform_data;
161
162 if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
163 return sprintf(buf, "Mailbox is empty\n");
164
165 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
166 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
167
168 return sprintf(buf, "0x%X\n", mbox_value);
169}
170
171static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
172
173static int mbox_show(struct seq_file *s, void *data)
174{
175 struct list_head *pos;
176 u8 mbox_index = 0;
177
178 list_for_each(pos, &mboxs) {
179 struct mbox *m =
180 (struct mbox *) list_entry(pos, struct mbox, list);
181 if (m == NULL) {
182 seq_printf(s,
183 "Unable to retrieve mailbox %d\n",
184 mbox_index);
185 continue;
186 }
187
188 spin_lock(&m->lock);
189 if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
190 seq_printf(s, "MAILBOX %d not setup or corrupt\n",
191 mbox_index);
192 spin_unlock(&m->lock);
193 continue;
194 }
195
196 seq_printf(s,
197 "===========================\n"
198 " MAILBOX %d\n"
199 " PEER MAILBOX DUMP\n"
200 "---------------------------\n"
201 "FIFO: 0x%X (%d)\n"
202 "Free Threshold: 0x%.2X (%d)\n"
203 "Occupied Threshold: 0x%.2X (%d)\n"
204 "Status: 0x%.2X (%d)\n"
205 " Free spaces (ot): %d (%d)\n"
206 " Occup spaces (ot): %d (%d)\n"
207 "===========================\n"
208 " LOCAL MAILBOX DUMP\n"
209 "---------------------------\n"
210 "FIFO: 0x%.X (%d)\n"
211 "Free Threshold: 0x%.2X (%d)\n"
212 "Occupied Threshold: 0x%.2X (%d)\n"
213 "Status: 0x%.2X (%d)\n"
214 " Free spaces (ot): %d (%d)\n"
215 " Occup spaces (ot): %d (%d)\n"
216 "===========================\n"
217 "write_index: %d\n"
218 "read_index : %d\n"
219 "===========================\n"
220 "\n",
221 mbox_index,
222 readl(m->virtbase_peer + MBOX_FIFO_DATA),
223 readl(m->virtbase_peer + MBOX_FIFO_DATA),
224 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
225 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
226 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
227 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
228 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
229 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
230 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
231 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
232 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
233 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
234 readl(m->virtbase_local + MBOX_FIFO_DATA),
235 readl(m->virtbase_local + MBOX_FIFO_DATA),
236 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
237 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
238 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
239 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
240 readl(m->virtbase_local + MBOX_FIFO_STATUS),
241 readl(m->virtbase_local + MBOX_FIFO_STATUS),
242 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
243 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
244 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
245 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
246 m->write_index, m->read_index);
247 mbox_index++;
248 spin_unlock(&m->lock);
249 }
250
251 return 0;
252}
253
254static int mbox_open(struct inode *inode, struct file *file)
255{
256 return single_open(file, mbox_show, NULL);
257}
258
259static const struct file_operations mbox_operations = {
260 .owner = THIS_MODULE,
261 .open = mbox_open,
262 .read = seq_read,
263 .llseek = seq_lseek,
264 .release = single_release,
265};
266#endif
267
268static irqreturn_t mbox_irq(int irq, void *arg)
269{
270 u32 mbox_value;
271 int nbr_occup;
272 int nbr_free;
273 struct mbox *mbox = (struct mbox *) arg;
274
275 spin_lock(&mbox->lock);
276
277 dev_dbg(&(mbox->pdev->dev),
278 "mbox IRQ [%d] received. ri = %d, wi = %d\n",
279 irq, mbox->read_index, mbox->write_index);
280
281 /*
282 * Check if we have any outgoing messages, and if there is space for
283 * them in the FIFO.
284 */
285 if (mbox->read_index != mbox->write_index) {
286 /*
287 * Check by reading FREE for LOCAL since that indicates
288 * OCCUP for PEER
289 */
290 nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
291 >> 4) & 0x7;
292 dev_dbg(&(mbox->pdev->dev),
293 "Status indicates %d empty spaces in the FIFO!\n",
294 nbr_free);
295
296 while ((nbr_free > 0) &&
297 (mbox->read_index != mbox->write_index)) {
298 /* Write the message and latch it into the FIFO */
299 writel(mbox->buffer[mbox->read_index],
300 (mbox->virtbase_peer + MBOX_FIFO_DATA));
301 writel(MBOX_LATCH,
302 (mbox->virtbase_peer + MBOX_FIFO_ADD));
303 dev_dbg(&(mbox->pdev->dev),
304 "Wrote message 0x%X to addr 0x%X\n",
305 mbox->buffer[mbox->read_index],
306 (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
307
308 nbr_free--;
309 mbox->read_index =
310 (mbox->read_index + 1) % MBOX_BUF_SIZE;
311 }
312
313 /*
314 * Check if we still want IRQ:s when there is free
315 * space to send
316 */
317 if (mbox->read_index != mbox->write_index) {
318 dev_dbg(&(mbox->pdev->dev),
319 "Still have messages to send, but FIFO full. "
320 "Request IRQ again!\n");
321 writel(MBOX_ENABLE_IRQ,
322 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
323 } else {
324 dev_dbg(&(mbox->pdev->dev),
325 "No more messages to send. "
326 "Do not request IRQ again!\n");
327 writel(MBOX_DISABLE_IRQ,
328 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
329 }
330
331 /*
332 * Check if we can signal any blocked clients that it is OK to
333 * start buffering again
334 */
335 if (mbox->client_blocked &&
336 (((mbox->write_index + 1) % MBOX_BUF_SIZE)
337 != mbox->read_index)) {
338 dev_dbg(&(mbox->pdev->dev),
339 "Waking up blocked client\n");
340 complete(&mbox->buffer_available);
341 mbox->client_blocked = 0;
342 }
343 }
344
345 /* Check if we have any incoming messages */
346 nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
347 if (nbr_occup == 0)
348 goto exit;
349
350 if (mbox->cb == NULL) {
351 dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
352 "leaving %d incoming messages in fifo!\n", nbr_occup);
353 goto exit;
354 }
355
356 /* Read and acknowledge the message */
357 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
358 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
359
360 /* Notify consumer of new mailbox message */
361 dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
362 mbox_value);
363 mbox->cb(mbox_value, mbox->client_data);
364
365exit:
366 dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
367 mbox->read_index, mbox->write_index);
368 spin_unlock(&mbox->lock);
369
370 return IRQ_HANDLED;
371}
372
373/* Setup is executed once for each mbox pair */
374struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
375{
376 struct resource *resource;
377 int irq;
378 int res;
379 struct mbox *mbox;
380
381 mbox = get_mbox_with_id(mbox_id);
382 if (mbox == NULL) {
383 dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
384 mbox_id);
385 goto exit;
386 }
387
388 /*
389 * Check if mailbox has been allocated to someone else,
390 * otherwise allocate it
391 */
392 if (mbox->allocated) {
393 dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
394 mbox_id);
395 mbox = NULL;
396 goto exit;
397 }
398 mbox->allocated = true;
399
400 dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
401 mbox_id, (u32)mbox);
402
403 mbox->client_data = priv;
404 mbox->cb = mbox_cb;
405
406 /* Get addr for peer mailbox and ioremap it */
407 resource = platform_get_resource_byname(mbox->pdev,
408 IORESOURCE_MEM,
409 "mbox_peer");
410 if (resource == NULL) {
411 dev_err(&(mbox->pdev->dev),
412 "Unable to retrieve mbox peer resource\n");
413 mbox = NULL;
414 goto exit;
415 }
416 dev_dbg(&(mbox->pdev->dev),
417 "Resource name: %s start: 0x%X, end: 0x%X\n",
418 resource->name, resource->start, resource->end);
419 mbox->virtbase_peer = ioremap(resource->start, resource_size(resource));
420 if (!mbox->virtbase_peer) {
421 dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
422 mbox = NULL;
423 goto exit;
424 }
425 dev_dbg(&(mbox->pdev->dev),
426 "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
427 resource->start, resource->end, (u32) mbox->virtbase_peer);
428
429 /* Get addr for local mailbox and ioremap it */
430 resource = platform_get_resource_byname(mbox->pdev,
431 IORESOURCE_MEM,
432 "mbox_local");
433 if (resource == NULL) {
434 dev_err(&(mbox->pdev->dev),
435 "Unable to retrieve mbox local resource\n");
436 mbox = NULL;
437 goto exit;
438 }
439 dev_dbg(&(mbox->pdev->dev),
440 "Resource name: %s start: 0x%X, end: 0x%X\n",
441 resource->name, resource->start, resource->end);
442 mbox->virtbase_local = ioremap(resource->start, resource_size(resource));
443 if (!mbox->virtbase_local) {
444 dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
445 mbox = NULL;
446 goto exit;
447 }
448 dev_dbg(&(mbox->pdev->dev),
449 "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
450 resource->start, resource->end, (u32) mbox->virtbase_peer);
451
452 init_completion(&mbox->buffer_available);
453 mbox->client_blocked = 0;
454
455 /* Get IRQ for mailbox and allocate it */
456 irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
457 if (irq < 0) {
458 dev_err(&(mbox->pdev->dev),
459 "Unable to retrieve mbox irq resource\n");
460 mbox = NULL;
461 goto exit;
462 }
463
464 dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
465 res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
466 if (res < 0) {
467 dev_err(&(mbox->pdev->dev),
468 "Unable to allocate mbox irq %d\n", irq);
469 mbox = NULL;
470 goto exit;
471 }
472
473 /* Set up mailbox to not launch IRQ on free space in mailbox */
474 writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
475
476 /*
477 * Set up mailbox to launch IRQ on new message if we have
478 * a callback set. If not, do not raise IRQ, but keep message
479 * in FIFO for manual retrieval
480 */
481 if (mbox_cb != NULL)
482 writel(MBOX_ENABLE_IRQ,
483 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
484 else
485 writel(MBOX_DISABLE_IRQ,
486 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
487
488#if defined(CONFIG_DEBUG_FS)
489 res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
490 if (res != 0)
491 dev_warn(&(mbox->pdev->dev),
492 "Unable to create mbox sysfs entry");
493
494 (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
495 NULL, &mbox_operations);
496#endif
497
498 dev_info(&(mbox->pdev->dev),
499 "Mailbox driver with index %d initiated!\n", mbox_id);
500
501exit:
502 return mbox;
503}
504EXPORT_SYMBOL(mbox_setup);
505
506
507int __init mbox_probe(struct platform_device *pdev)
508{
509 struct mbox local_mbox;
510 struct mbox *mbox;
511 int res = 0;
512 dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
513
514 memset(&local_mbox, 0x0, sizeof(struct mbox));
515
516 /* Associate our mbox data with the platform device */
517 res = platform_device_add_data(pdev,
518 (void *) &local_mbox,
519 sizeof(struct mbox));
520 if (res != 0) {
521 dev_err(&(pdev->dev),
522 "Unable to allocate driver platform data!\n");
523 goto exit;
524 }
525
526 mbox = (struct mbox *) pdev->dev.platform_data;
527 mbox->pdev = pdev;
528 mbox->write_index = 0;
529 mbox->read_index = 0;
530
531 INIT_LIST_HEAD(&(mbox->list));
532 list_add_tail(&(mbox->list), &mboxs);
533
534 sprintf(mbox->name, "%s", MBOX_NAME);
535 spin_lock_init(&mbox->lock);
536
537 dev_info(&(pdev->dev), "Mailbox driver loaded\n");
538
539exit:
540 return res;
541}
542
543static struct platform_driver mbox_driver = {
544 .driver = {
545 .name = MBOX_NAME,
546 .owner = THIS_MODULE,
547 },
548};
549
550static int __init mbox_init(void)
551{
552 return platform_driver_probe(&mbox_driver, mbox_probe);
553}
554
555module_init(mbox_init);
556
557void __exit mbox_exit(void)
558{
559 platform_driver_unregister(&mbox_driver);
560}
561
562module_exit(mbox_exit);
563
564MODULE_LICENSE("GPL");
565MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
new file mode 100644
index 00000000000..6b86416c94c
--- /dev/null
+++ b/arch/arm/mach-ux500/modem-irq-db5500.c
@@ -0,0 +1,143 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14
15#include <mach/id.h>
16
17#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
18#define MODEM_INTCON_SIZE 0xFFF
19
20#define DEST_IRQ41_OFFSET 0x2A4
21#define DEST_IRQ43_OFFSET 0x2AC
22#define DEST_IRQ45_OFFSET 0x2B4
23
24#define PRIO_IRQ41_OFFSET 0x6A4
25#define PRIO_IRQ43_OFFSET 0x6AC
26#define PRIO_IRQ45_OFFSET 0x6B4
27
28#define ALLOW_IRQ_OFFSET 0x104
29
30#define MODEM_INTCON_CPU_NBR 0x1
31#define MODEM_INTCON_PRIO_HIGH 0x0
32
33#define MODEM_INTCON_ALLOW_IRQ41 0x0200
34#define MODEM_INTCON_ALLOW_IRQ43 0x0800
35#define MODEM_INTCON_ALLOW_IRQ45 0x2000
36
37#define MODEM_IRQ_REG_OFFSET 0x4
38
39struct modem_irq {
40 void __iomem *modem_intcon_base;
41};
42
43
44static void setup_modem_intcon(void __iomem *modem_intcon_base)
45{
46 /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
47 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
48 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
49 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
50
51 /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
52 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
53 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
54 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
55
56 /* IC_ALLOW_ARRAY - IRQ enable */
57 writel(MODEM_INTCON_ALLOW_IRQ41 |
58 MODEM_INTCON_ALLOW_IRQ43 |
59 MODEM_INTCON_ALLOW_IRQ45,
60 modem_intcon_base + ALLOW_IRQ_OFFSET);
61}
62
63static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
64{
65 int real_irq;
66 int virt_irq;
67 struct modem_irq *mi = (struct modem_irq *)data;
68
69 /* Read modem side IRQ number from modem IRQ controller */
70 real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
71 virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
72
73 pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
74 "which will be 0x%X (%d) which translates to "
75 "virtual IRQ 0x%X (%d)!\n",
76 (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
77 real_irq,
78 real_irq & 0xFF,
79 real_irq & 0xFF,
80 virt_irq,
81 virt_irq);
82
83 if (virt_irq != 0)
84 generic_handle_irq(virt_irq);
85
86 pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
87
88 return IRQ_HANDLED;
89}
90
91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
92{
93 irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
94 set_irq_flags(irq, IRQF_VALID);
95
96 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
97}
98
99static int modem_irq_init(void)
100{
101 int err;
102 static struct irq_chip modem_irq_chip;
103 struct modem_irq *mi;
104
105 if (!cpu_is_u5500())
106 return -ENODEV;
107
108 pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
109 IRQ_DB5500_MODEM);
110
111 mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
112 if (!mi) {
113 pr_err("modem_irq: Could not allocate device\n");
114 return -ENOMEM;
115 }
116
117 mi->modem_intcon_base =
118 ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
119 pr_debug("modem_irq: ioremapped modem_intcon_base from "
120 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
121 (u32)mi->modem_intcon_base);
122
123 setup_modem_intcon(mi->modem_intcon_base);
124
125 modem_irq_chip = dummy_irq_chip;
126 modem_irq_chip.name = "modem_irq";
127
128 /* Create the virtual IRQ:s needed */
129 create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
130 create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
131 create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
132
133 err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
134 modem_cpu_irq_handler, IRQF_ONESHOT,
135 "modem_irq", mi);
136 if (err)
137 pr_err("modem_irq: Could not register IRQ %d\n",
138 IRQ_DB5500_MODEM);
139
140 return 0;
141}
142
143arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
new file mode 100644
index 00000000000..bf50c21fe69
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db5500.h
@@ -0,0 +1,620 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_DB5500_PINS_H
9#define __MACH_DB5500_PINS_H
10
11#define GPIO0_GPIO PIN_CFG(0, GPIO)
12#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A)
13
14#define GPIO1_GPIO PIN_CFG(1, GPIO)
15#define GPIO1_SM_A3 PIN_CFG(1, ALT_A)
16
17#define GPIO2_GPIO PIN_CFG(2, GPIO)
18#define GPIO2_SM_A4 PIN_CFG(2, ALT_A)
19#define GPIO2_SM_AVD PIN_CFG(2, ALT_B)
20
21#define GPIO3_GPIO PIN_CFG(3, GPIO)
22#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A)
23
24#define GPIO4_GPIO PIN_CFG(4, GPIO)
25#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A)
26
27#define GPIO5_GPIO PIN_CFG(5, GPIO)
28#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A)
29#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B)
30
31#define GPIO6_GPIO PIN_CFG(6, GPIO)
32#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A)
33#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B)
34
35#define GPIO7_GPIO PIN_CFG(7, GPIO)
36#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A)
37#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B)
38
39#define GPIO8_GPIO PIN_CFG(8, GPIO)
40#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A)
41#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B)
42
43#define GPIO9_GPIO PIN_CFG(9, GPIO)
44#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A)
45#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B)
46
47#define GPIO10_GPIO PIN_CFG(10, GPIO)
48#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A)
49#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B)
50
51#define GPIO11_GPIO PIN_CFG(11, GPIO)
52#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A)
53#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B)
54
55#define GPIO12_GPIO PIN_CFG(12, GPIO)
56#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A)
57#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B)
58
59#define GPIO13_GPIO PIN_CFG(13, GPIO)
60#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A)
61#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B)
62#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C)
63
64#define GPIO14_GPIO PIN_CFG(14, GPIO)
65#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A)
66#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B)
67#define GPIO14_SM_CKO PIN_CFG(14, ALT_C)
68
69#define GPIO15_GPIO PIN_CFG(15, GPIO)
70#define GPIO15_SM_A5 PIN_CFG(15, ALT_A)
71#define GPIO15_SM_CLE PIN_CFG(15, ALT_B)
72
73#define GPIO16_GPIO PIN_CFG(16, GPIO)
74#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A)
75#define GPIO16_SM_OEn PIN_CFG(16, ALT_B)
76
77#define GPIO17_GPIO PIN_CFG(17, GPIO)
78#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A)
79#define GPIO17_SM_WEn PIN_CFG(17, ALT_B)
80
81#define GPIO18_GPIO PIN_CFG(18, GPIO)
82#define GPIO18_SM_A6 PIN_CFG(18, ALT_A)
83#define GPIO18_SM_ALE PIN_CFG(18, ALT_B)
84#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C)
85
86#define GPIO19_GPIO PIN_CFG(19, GPIO)
87#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A)
88#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B)
89
90#define GPIO20_GPIO PIN_CFG(20, GPIO)
91#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A)
92#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B)
93
94#define GPIO21_GPIO PIN_CFG(21, GPIO)
95#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A)
96#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B)
97
98#define GPIO22_GPIO PIN_CFG(22, GPIO)
99#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A)
100#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B)
101
102#define GPIO23_GPIO PIN_CFG(23, GPIO)
103#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A)
104#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B)
105#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C)
106
107#define GPIO24_GPIO PIN_CFG(24, GPIO)
108#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A)
109#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B)
110#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C)
111
112#define GPIO25_GPIO PIN_CFG(25, GPIO)
113#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A)
114#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B)
115#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C)
116
117#define GPIO26_GPIO PIN_CFG(26, GPIO)
118#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A)
119#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B)
120
121#define GPIO27_GPIO PIN_CFG(27, GPIO)
122#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A)
123#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B)
124
125#define GPIO28_GPIO PIN_CFG(28, GPIO)
126#define GPIO28_U0_TXD PIN_CFG(28, ALT_A)
127#define GPIO28_SM_A0 PIN_CFG(28, ALT_B)
128
129#define GPIO29_GPIO PIN_CFG(29, GPIO)
130#define GPIO29_U0_RXD PIN_CFG(29, ALT_A)
131#define GPIO29_SM_A1 PIN_CFG(29, ALT_B)
132#define GPIO29_PWM_0 PIN_CFG(29, ALT_C)
133
134#define GPIO30_GPIO PIN_CFG(30, GPIO)
135#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
136#define GPIO30_SM_A2 PIN_CFG(30, ALT_B)
137#define GPIO30_PWM_1 PIN_CFG(30, ALT_C)
138
139#define GPIO31_GPIO PIN_CFG(31, GPIO)
140#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A)
141#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B)
142#define GPIO31_PWM_2 PIN_CFG(31, ALT_C)
143
144#define GPIO32_GPIO PIN_CFG(32, GPIO)
145#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A)
146#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B)
147
148#define GPIO33_GPIO PIN_CFG(33, GPIO)
149#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A)
150#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B)
151
152#define GPIO34_GPIO PIN_CFG(34, GPIO)
153#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A)
154#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B)
155
156#define GPIO35_GPIO PIN_CFG(35, GPIO)
157#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A)
158#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B)
159
160#define GPIO64_GPIO PIN_CFG(64, GPIO)
161#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A)
162#define GPIO64_U0_TXD PIN_CFG(64, ALT_B)
163
164#define GPIO65_GPIO PIN_CFG(65, GPIO)
165#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A)
166#define GPIO65_U0_RXD PIN_CFG(65, ALT_B)
167
168#define GPIO66_GPIO PIN_CFG(66, GPIO)
169#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A)
170
171#define GPIO67_GPIO PIN_CFG(67, GPIO)
172#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A)
173
174#define GPIO68_GPIO PIN_CFG(68, GPIO)
175#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A)
176
177#define GPIO69_GPIO PIN_CFG(69, GPIO)
178#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A)
179
180#define GPIO70_GPIO PIN_CFG(70, GPIO)
181#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A)
182
183#define GPIO71_GPIO PIN_CFG(71, GPIO)
184#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A)
185
186#define GPIO72_GPIO PIN_CFG(72, GPIO)
187#define GPIO72_USB_STP PIN_CFG(72, ALT_A)
188
189#define GPIO73_GPIO PIN_CFG(73, GPIO)
190#define GPIO73_USB_DIR PIN_CFG(73, ALT_A)
191
192#define GPIO74_GPIO PIN_CFG(74, GPIO)
193#define GPIO74_USB_NXT PIN_CFG(74, ALT_A)
194
195#define GPIO75_GPIO PIN_CFG(75, GPIO)
196#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A)
197
198#define GPIO76_GPIO PIN_CFG(76, GPIO)
199
200#define GPIO77_GPIO PIN_CFG(77, GPIO)
201#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A)
202
203#define GPIO78_GPIO PIN_CFG(78, GPIO)
204#define GPIO78_IRQn PIN_CFG(78, ALT_A)
205
206#define GPIO79_GPIO PIN_CFG(79, GPIO)
207#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A)
208
209#define GPIO80_GPIO PIN_CFG(80, GPIO)
210#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A)
211
212#define GPIO81_GPIO PIN_CFG(81, GPIO)
213#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A)
214
215#define GPIO82_GPIO PIN_CFG(82, GPIO)
216#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A)
217
218#define GPIO96_GPIO PIN_CFG(96, GPIO)
219#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A)
220#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B)
221#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C)
222
223#define GPIO97_GPIO PIN_CFG(97, GPIO)
224#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A)
225#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B)
226#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C)
227
228#define GPIO98_GPIO PIN_CFG(98, GPIO)
229#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A)
230#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B)
231#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C)
232
233#define GPIO99_GPIO PIN_CFG(99, GPIO)
234#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A)
235#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B)
236#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C)
237
238#define GPIO100_GPIO PIN_CFG(100, GPIO)
239#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A)
240
241#define GPIO101_GPIO PIN_CFG(101, GPIO)
242#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A)
243
244#define GPIO128_GPIO PIN_CFG(128, GPIO)
245#define GPIO128_KP_I0 PIN_CFG(128, ALT_A)
246#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B)
247
248#define GPIO129_GPIO PIN_CFG(129, GPIO)
249#define GPIO129_KP_O0 PIN_CFG(129, ALT_A)
250#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B)
251
252#define GPIO130_GPIO PIN_CFG(130, GPIO)
253#define GPIO130_KP_I1 PIN_CFG(130, ALT_A)
254#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B)
255
256#define GPIO131_GPIO PIN_CFG(131, GPIO)
257#define GPIO131_KP_O1 PIN_CFG(131, ALT_A)
258#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B)
259
260#define GPIO132_GPIO PIN_CFG(132, GPIO)
261#define GPIO132_KP_I2 PIN_CFG(132, ALT_A)
262#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B)
263#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C)
264
265#define GPIO133_GPIO PIN_CFG(133, GPIO)
266#define GPIO133_KP_O2 PIN_CFG(133, ALT_A)
267#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B)
268#define GPIO133_U0_RXD PIN_CFG(133, ALT_C)
269
270#define GPIO134_GPIO PIN_CFG(134, GPIO)
271#define GPIO134_KP_I3 PIN_CFG(134, ALT_A)
272#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B)
273#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C)
274
275#define GPIO135_GPIO PIN_CFG(135, GPIO)
276#define GPIO135_KP_O3 PIN_CFG(135, ALT_A)
277#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B)
278#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C)
279
280#define GPIO136_GPIO PIN_CFG(136, GPIO)
281#define GPIO136_KP_I4 PIN_CFG(136, ALT_A)
282#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B)
283#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C)
284
285#define GPIO137_GPIO PIN_CFG(137, GPIO)
286#define GPIO137_KP_O4 PIN_CFG(137, ALT_A)
287#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B)
288#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C)
289
290#define GPIO138_GPIO PIN_CFG(138, GPIO)
291#define GPIO138_KP_I5 PIN_CFG(138, ALT_A)
292#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B)
293#define GPIO138_U0_TXD PIN_CFG(138, ALT_C)
294
295#define GPIO139_GPIO PIN_CFG(139, GPIO)
296#define GPIO139_KP_O5 PIN_CFG(139, ALT_A)
297#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B)
298#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C)
299
300#define GPIO140_GPIO PIN_CFG(140, GPIO)
301#define GPIO140_KP_I6 PIN_CFG(140, ALT_A)
302#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B)
303#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C)
304
305#define GPIO141_GPIO PIN_CFG(141, GPIO)
306#define GPIO141_KP_O6 PIN_CFG(141, ALT_A)
307#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B)
308#define GPIO141_U0_RXD PIN_CFG(141, ALT_C)
309
310#define GPIO142_GPIO PIN_CFG(142, GPIO)
311#define GPIO142_KP_I7 PIN_CFG(142, ALT_A)
312#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B)
313#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C)
314
315#define GPIO143_GPIO PIN_CFG(143, GPIO)
316#define GPIO143_KP_O7 PIN_CFG(143, ALT_A)
317#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B)
318#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C)
319
320#define GPIO144_GPIO PIN_CFG(144, GPIO)
321#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A)
322#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B)
323#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C)
324
325#define GPIO145_GPIO PIN_CFG(145, GPIO)
326#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A)
327#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B)
328#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C)
329
330#define GPIO146_GPIO PIN_CFG(146, GPIO)
331#define GPIO146_PWM_0 PIN_CFG(146, ALT_A)
332#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B)
333
334#define GPIO147_GPIO PIN_CFG(147, GPIO)
335#define GPIO147_PWM_1 PIN_CFG(147, ALT_A)
336#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B)
337
338#define GPIO148_GPIO PIN_CFG(148, GPIO)
339#define GPIO148_PWM_2 PIN_CFG(148, ALT_A)
340#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B)
341
342#define GPIO160_GPIO PIN_CFG(160, GPIO)
343#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A)
344
345#define GPIO161_GPIO PIN_CFG(161, GPIO)
346#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A)
347
348#define GPIO162_GPIO PIN_CFG(162, GPIO)
349#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A)
350
351#define GPIO163_GPIO PIN_CFG(163, GPIO)
352
353#define GPIO164_GPIO PIN_CFG(164, GPIO)
354#define GPIO164_GPS_START PIN_CFG(164, ALT_A)
355
356#define GPIO165_GPIO PIN_CFG(165, GPIO)
357#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A)
358#define GPIO165_U3_RXD PIN_CFG(165, ALT_B)
359#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C)
360
361#define GPIO166_GPIO PIN_CFG(166, GPIO)
362#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A)
363#define GPIO166_U3_TXD PIN_CFG(166, ALT_B)
364#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C)
365
366#define GPIO167_GPIO PIN_CFG(167, GPIO)
367#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A)
368#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B)
369#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C)
370
371#define GPIO168_GPIO PIN_CFG(168, GPIO)
372#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A)
373#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B)
374#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C)
375
376#define GPIO169_GPIO PIN_CFG(169, GPIO)
377#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A)
378#define GPIO169_DDR_RC PIN_CFG(169, ALT_B)
379#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C)
380
381#define GPIO170_GPIO PIN_CFG(170, GPIO)
382#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A)
383
384#define GPIO171_GPIO PIN_CFG(171, GPIO)
385#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A)
386#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B)
387#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C)
388
389#define GPIO172_GPIO PIN_CFG(172, GPIO)
390#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A)
391#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B)
392#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C)
393
394#define GPIO173_GPIO PIN_CFG(173, GPIO)
395#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A)
396#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B)
397#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C)
398
399#define GPIO174_GPIO PIN_CFG(174, GPIO)
400#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A)
401#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B)
402#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C)
403
404#define GPIO175_GPIO PIN_CFG(175, GPIO)
405#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A)
406#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B)
407#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C)
408
409#define GPIO176_GPIO PIN_CFG(176, GPIO)
410#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A)
411#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B)
412
413#define GPIO177_GPIO PIN_CFG(177, GPIO)
414#define GPIO177_U2_RXD PIN_CFG(177, ALT_A)
415#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B)
416#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C)
417
418#define GPIO178_GPIO PIN_CFG(178, GPIO)
419#define GPIO178_U2_TXD PIN_CFG(178, ALT_A)
420#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B)
421#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C)
422
423#define GPIO179_GPIO PIN_CFG(179, GPIO)
424#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A)
425#define GPIO179_U3_RXD PIN_CFG(179, ALT_B)
426#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C)
427
428#define GPIO180_GPIO PIN_CFG(180, GPIO)
429#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A)
430#define GPIO180_U3_TXD PIN_CFG(180, ALT_B)
431#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C)
432
433#define GPIO185_GPIO PIN_CFG(185, GPIO)
434#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A)
435#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B)
436
437#define GPIO186_GPIO PIN_CFG(186, GPIO)
438#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A)
439#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B)
440
441#define GPIO187_GPIO PIN_CFG(187, GPIO)
442#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A)
443#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B)
444
445#define GPIO188_GPIO PIN_CFG(188, GPIO)
446#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A)
447#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B)
448
449#define GPIO189_GPIO PIN_CFG(189, GPIO)
450#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A)
451#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B)
452
453#define GPIO190_GPIO PIN_CFG(190, GPIO)
454#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A)
455#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B)
456
457#define GPIO191_GPIO PIN_CFG(191, GPIO)
458#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A)
459#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B)
460#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C)
461
462#define GPIO192_GPIO PIN_CFG(192, GPIO)
463#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A)
464#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B)
465#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C)
466
467#define GPIO193_GPIO PIN_CFG(193, GPIO)
468#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A)
469#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B)
470#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C)
471
472#define GPIO194_GPIO PIN_CFG(194, GPIO)
473#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A)
474#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B)
475#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C)
476
477#define GPIO195_GPIO PIN_CFG(195, GPIO)
478#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A)
479#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B)
480#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C)
481
482#define GPIO196_GPIO PIN_CFG(196, GPIO)
483#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A)
484#define GPIO196_U0_RXD PIN_CFG(196, ALT_B)
485#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C)
486
487#define GPIO197_GPIO PIN_CFG(197, GPIO)
488#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A)
489#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B)
490
491#define GPIO198_GPIO PIN_CFG(198, GPIO)
492#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A)
493
494#define GPIO199_GPIO PIN_CFG(199, GPIO)
495#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A)
496#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B)
497
498#define GPIO200_GPIO PIN_CFG(200, GPIO)
499#define GPIO200_U1_TXD PIN_CFG(200, ALT_A)
500#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B)
501
502#define GPIO201_GPIO PIN_CFG(201, GPIO)
503#define GPIO201_U1_RXD PIN_CFG(201, ALT_A)
504#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B)
505
506#define GPIO202_GPIO PIN_CFG(202, GPIO)
507#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A)
508#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B)
509
510#define GPIO203_GPIO PIN_CFG(203, GPIO)
511#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A)
512#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B)
513
514#define GPIO204_GPIO PIN_CFG(204, GPIO)
515#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A)
516#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B)
517#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C)
518
519#define GPIO205_GPIO PIN_CFG(205, GPIO)
520#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A)
521#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B)
522#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C)
523
524#define GPIO206_GPIO PIN_CFG(206, GPIO)
525#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A)
526#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B)
527#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C)
528
529#define GPIO207_GPIO PIN_CFG(207, GPIO)
530#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A)
531#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B)
532#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C)
533
534#define GPIO208_GPIO PIN_CFG(208, GPIO)
535#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A)
536#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B)
537#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C)
538
539#define GPIO209_GPIO PIN_CFG(209, GPIO)
540#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A)
541#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B)
542#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C)
543
544#define GPIO210_GPIO PIN_CFG(210, GPIO)
545#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A)
546#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B)
547
548#define GPIO211_GPIO PIN_CFG(211, GPIO)
549#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A)
550#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B)
551
552#define GPIO212_GPIO PIN_CFG(212, GPIO)
553#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A)
554#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B)
555
556#define GPIO213_GPIO PIN_CFG(213, GPIO)
557#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A)
558#define GPIO213_LCD_DE PIN_CFG(213, ALT_B)
559#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C)
560
561#define GPIO214_GPIO PIN_CFG(214, GPIO)
562#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A)
563#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B)
564#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C)
565
566#define GPIO215_GPIO PIN_CFG(215, GPIO)
567#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A)
568#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B)
569#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C)
570
571#define GPIO216_GPIO PIN_CFG(216, GPIO)
572#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A)
573#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B)
574
575#define GPIO217_GPIO PIN_CFG(217, GPIO)
576#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A)
577#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B)
578#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C)
579
580#define GPIO218_GPIO PIN_CFG(218, GPIO)
581#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A)
582#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B)
583
584#define GPIO219_GPIO PIN_CFG(219, GPIO)
585#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A)
586#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B)
587
588#define GPIO220_GPIO PIN_CFG(220, GPIO)
589#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A)
590#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B)
591
592#define GPIO221_GPIO PIN_CFG(221, GPIO)
593#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A)
594#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B)
595
596#define GPIO222_GPIO PIN_CFG(222, GPIO)
597#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A)
598#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B)
599
600#define GPIO223_GPIO PIN_CFG(223, GPIO)
601#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A)
602#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B)
603
604#define GPIO224_GPIO PIN_CFG(224, GPIO)
605#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A)
606#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B)
607
608#define GPIO225_GPIO PIN_CFG(225, GPIO)
609#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A)
610#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B)
611
612#define GPIO226_GPIO PIN_CFG(226, GPIO)
613#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A)
614#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B)
615
616#define GPIO227_GPIO PIN_CFG(227, GPIO)
617#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A)
618#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B)
619
620#endif
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
new file mode 100644
index 00000000000..cb2110c3285
--- /dev/null
+++ b/arch/arm/mach-ux500/ste-dma40-db5500.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * DB5500-SoC-specific configuration for DMA40
8 */
9
10#ifndef STE_DMA40_DB5500_H
11#define STE_DMA40_DB5500_H
12
13#define DB5500_DMA_NR_DEV 64
14
15enum dma_src_dev_type {
16 DB5500_DMA_DEV0_SPI0_RX = 0,
17 DB5500_DMA_DEV1_SPI1_RX = 1,
18 DB5500_DMA_DEV2_SPI2_RX = 2,
19 DB5500_DMA_DEV3_SPI3_RX = 3,
20 DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
21 DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
22 DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
23 DB5500_DMA_DEV7_IRDA_RFS = 7,
24 DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
25 DB5500_DMA_DEV9_MSP0_RX = 9,
26 DB5500_DMA_DEV10_MSP1_RX = 10,
27 DB5500_DMA_DEV11_MSP2_RX = 11,
28 DB5500_DMA_DEV12_UART0_RX = 12,
29 DB5500_DMA_DEV13_UART1_RX = 13,
30 DB5500_DMA_DEV14_UART2_RX = 14,
31 DB5500_DMA_DEV15_UART3_RX = 15,
32 DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
33 DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
34 DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
35 DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
36 DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
37 DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
38 DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
39 DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
40 DB5500_DMA_DEV24_SDMMC0_RX = 24,
41 DB5500_DMA_DEV25_SDMMC1_RX = 25,
42 DB5500_DMA_DEV26_SDMMC2_RX = 26,
43 DB5500_DMA_DEV27_SDMMC3_RX = 27,
44 DB5500_DMA_DEV28_SDMMC4_RX = 28,
45 /* 29 - 32 not used */
46 DB5500_DMA_DEV33_SDMMC0_RX = 33,
47 DB5500_DMA_DEV34_SDMMC1_RX = 34,
48 DB5500_DMA_DEV35_SDMMC2_RX = 35,
49 DB5500_DMA_DEV36_SDMMC3_RX = 36,
50 DB5500_DMA_DEV37_SDMMC4_RX = 37,
51 DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
52 DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
53 DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
54 DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
55 DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
56 DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
57 DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
58 DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
59 /* 46 not used */
60 DB5500_DMA_DEV47_MCDE_RX = 47,
61 DB5500_DMA_DEV48_CRYPTO1_RX = 48,
62 /* 49, 50 not used */
63 DB5500_DMA_DEV49_I2C1_RX = 51,
64 DB5500_DMA_DEV50_I2C3_RX = 52,
65 DB5500_DMA_DEV51_I2C2_RX = 53,
66 /* 54 - 60 not used */
67 DB5500_DMA_DEV61_CRYPTO0_RX = 61,
68 /* 62, 63 not used */
69};
70
71enum dma_dest_dev_type {
72 DB5500_DMA_DEV0_SPI0_TX = 0,
73 DB5500_DMA_DEV1_SPI1_TX = 1,
74 DB5500_DMA_DEV2_SPI2_TX = 2,
75 DB5500_DMA_DEV3_SPI3_TX = 3,
76 DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
77 DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
78 DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
79 DB5500_DMA_DEV7_IRRC_TX = 7,
80 DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
81 DB5500_DMA_DEV9_MSP0_TX = 9,
82 DB5500_DMA_DEV10_MSP1_TX = 10,
83 DB5500_DMA_DEV11_MSP2_TX = 11,
84 DB5500_DMA_DEV12_UART0_TX = 12,
85 DB5500_DMA_DEV13_UART1_TX = 13,
86 DB5500_DMA_DEV14_UART2_TX = 14,
87 DB5500_DMA_DEV15_UART3_TX = 15,
88 DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
89 DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
90 DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
91 DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
92 DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
93 DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
94 DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
95 DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
96 DB5500_DMA_DEV24_SDMMC0_TX = 24,
97 DB5500_DMA_DEV25_SDMMC1_TX = 25,
98 DB5500_DMA_DEV26_SDMMC2_TX = 26,
99 DB5500_DMA_DEV27_SDMMC3_TX = 27,
100 DB5500_DMA_DEV28_SDMMC4_TX = 28,
101 /* 29 - 31 not used */
102 DB5500_DMA_DEV32_FSMC_TX = 32,
103 DB5500_DMA_DEV33_SDMMC0_TX = 33,
104 DB5500_DMA_DEV34_SDMMC1_TX = 34,
105 DB5500_DMA_DEV35_SDMMC2_TX = 35,
106 DB5500_DMA_DEV36_SDMMC3_TX = 36,
107 DB5500_DMA_DEV37_SDMMC4_TX = 37,
108 DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
109 DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
110 DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
111 DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
112 DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
113 DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
114 DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
115 DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
116 /* 46 not used */
117 DB5500_DMA_DEV47_STM_TX = 47,
118 DB5500_DMA_DEV48_CRYPTO1_TX = 48,
119 DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
120 DB5500_DMA_DEV50_HASH1_TX = 50,
121 DB5500_DMA_DEV51_I2C1_TX = 51,
122 DB5500_DMA_DEV52_I2C3_TX = 52,
123 DB5500_DMA_DEV53_I2C2_TX = 53,
124 /* 54, 55 not used */
125 DB5500_DMA_MEMCPY_TX_1 = 56,
126 DB5500_DMA_MEMCPY_TX_2 = 57,
127 DB5500_DMA_MEMCPY_TX_3 = 58,
128 DB5500_DMA_MEMCPY_TX_4 = 59,
129 DB5500_DMA_MEMCPY_TX_5 = 60,
130 DB5500_DMA_DEV61_CRYPTO0_TX = 61,
131 DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
132 DB5500_DMA_DEV63_HASH0_TX = 63,
133};
134
135#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 08:35:21 -0400