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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-u300
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-u300')
-rw-r--r--arch/arm/mach-u300/clock.c1504
-rw-r--r--arch/arm/mach-u300/clock.h50
-rw-r--r--arch/arm/mach-u300/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-u300/include/mach/dma_channels.h69
-rw-r--r--arch/arm/mach-u300/include/mach/entry-macro.S40
-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h294
-rw-r--r--arch/arm/mach-u300/include/mach/io.h20
-rw-r--r--arch/arm/mach-u300/include/mach/memory.h42
-rw-r--r--arch/arm/mach-u300/include/mach/platform.h19
-rw-r--r--arch/arm/mach-u300/include/mach/system.h42
-rw-r--r--arch/arm/mach-u300/include/mach/vmalloc.h12
-rw-r--r--arch/arm/mach-u300/mmc.c68
-rw-r--r--arch/arm/mach-u300/mmc.h18
-rw-r--r--arch/arm/mach-u300/padmux.c367
-rw-r--r--arch/arm/mach-u300/padmux.h39
-rw-r--r--arch/arm/mach-u300/u300.c70
16 files changed, 2661 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
new file mode 100644
index 00000000000..5535dd0a78c
--- /dev/null
+++ b/arch/arm/mach-u300/clock.c
@@ -0,0 +1,1504 @@
1/*
2 *
3 * arch/arm/mach-u300/clock.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Define clocks in the app platform.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/clk.h>
20#include <linux/mutex.h>
21#include <linux/spinlock.h>
22#include <linux/debugfs.h>
23#include <linux/device.h>
24#include <linux/init.h>
25#include <linux/timer.h>
26#include <linux/io.h>
27#include <linux/seq_file.h>
28#include <linux/clkdev.h>
29
30#include <mach/hardware.h>
31#include <mach/syscon.h>
32
33#include "clock.h"
34
35/*
36 * TODO:
37 * - move all handling of the CCR register into this file and create
38 * a spinlock for the CCR register
39 * - switch to the clkdevice lookup mechanism that maps clocks to
40 * device ID:s instead when it becomes available in kernel 2.6.29.
41 * - implement rate get/set for all clocks that need it.
42 */
43
44/*
45 * Syscon clock I/O registers lock so clock requests don't collide
46 * NOTE: this is a local lock only used to lock access to clock and
47 * reset registers in syscon.
48 */
49static DEFINE_SPINLOCK(syscon_clkreg_lock);
50static DEFINE_SPINLOCK(syscon_resetreg_lock);
51
52/*
53 * The clocking hierarchy currently looks like this.
54 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
55 * The ideas is to show dependencies, so a clock higher up in the
56 * hierarchy has to be on in order for another clock to be on. Now,
57 * both CPU and DMA can actually be on top of the hierarchy, and that
58 * is not modeled currently. Instead we have the backbone AMBA bus on
59 * top. This bus cannot be programmed in any way but conceptually it
60 * needs to be active for the bridges and devices to transport data.
61 *
62 * Please be aware that a few clocks are hw controlled, which mean that
63 * the hw itself can turn on/off or change the rate of the clock when
64 * needed!
65 *
66 * AMBA bus
67 * |
68 * +- CPU
69 * +- FSMC NANDIF NAND Flash interface
70 * +- SEMI Shared Memory interface
71 * +- ISP Image Signal Processor (U335 only)
72 * +- CDS (U335 only)
73 * +- DMA Direct Memory Access Controller
74 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
75 * +- APEX
76 * +- VIDEO_ENC AVE2/3 Video Encoder
77 * +- XGAM Graphics Accelerator Controller
78 * +- AHB
79 * |
80 * +- ahb:0 AHB Bridge
81 * | |
82 * | +- ahb:1 INTCON Interrupt controller
83 * | +- ahb:3 MSPRO Memory Stick Pro controller
84 * | +- ahb:4 EMIF External Memory interface
85 * |
86 * +- fast:0 FAST bridge
87 * | |
88 * | +- fast:1 MMCSD MMC/SD card reader controller
89 * | +- fast:2 I2S0 PCM I2S channel 0 controller
90 * | +- fast:3 I2S1 PCM I2S channel 1 controller
91 * | +- fast:4 I2C0 I2C channel 0 controller
92 * | +- fast:5 I2C1 I2C channel 1 controller
93 * | +- fast:6 SPI SPI controller
94 * | +- fast:7 UART1 Secondary UART (U335 only)
95 * |
96 * +- slow:0 SLOW bridge
97 * |
98 * +- slow:1 SYSCON (not possible to control)
99 * +- slow:2 WDOG Watchdog
100 * +- slow:3 UART0 primary UART
101 * +- slow:4 TIMER_APP Application timer - used in Linux
102 * +- slow:5 KEYPAD controller
103 * +- slow:6 GPIO controller
104 * +- slow:7 RTC controller
105 * +- slow:8 BT Bus Tracer (not used currently)
106 * +- slow:9 EH Event Handler (not used currently)
107 * +- slow:a TIMER_ACC Access style timer (not used currently)
108 * +- slow:b PPM (U335 only, what is that?)
109 */
110
111/*
112 * Reset control functions. We remember if a block has been
113 * taken out of reset and don't remove the reset assertion again
114 * and vice versa. Currently we only remove resets so the
115 * enablement function is defined out.
116 */
117static void syscon_block_reset_enable(struct clk *clk)
118{
119 u16 val;
120 unsigned long iflags;
121
122 /* Not all blocks support resetting */
123 if (!clk->res_reg || !clk->res_mask)
124 return;
125 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
126 val = readw(clk->res_reg);
127 val |= clk->res_mask;
128 writew(val, clk->res_reg);
129 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
130 clk->reset = true;
131}
132
133static void syscon_block_reset_disable(struct clk *clk)
134{
135 u16 val;
136 unsigned long iflags;
137
138 /* Not all blocks support resetting */
139 if (!clk->res_reg || !clk->res_mask)
140 return;
141 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
142 val = readw(clk->res_reg);
143 val &= ~clk->res_mask;
144 writew(val, clk->res_reg);
145 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
146 clk->reset = false;
147}
148
149int __clk_get(struct clk *clk)
150{
151 u16 val;
152
153 /* The MMC and MSPRO clocks need some special set-up */
154 if (!strcmp(clk->name, "MCLK")) {
155 /* Set default MMC clock divisor to 18.9 MHz */
156 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
157 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
158 /* Disable the MMC feedback clock */
159 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
160 /* Disable MSPRO frequency */
161 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
162 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
163 }
164 if (!strcmp(clk->name, "MSPRO")) {
165 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
166 /* Disable the MMC feedback clock */
167 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
168 /* Enable MSPRO frequency */
169 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
170 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
171 }
172 return 1;
173}
174EXPORT_SYMBOL(__clk_get);
175
176void __clk_put(struct clk *clk)
177{
178}
179EXPORT_SYMBOL(__clk_put);
180
181static void syscon_clk_disable(struct clk *clk)
182{
183 unsigned long iflags;
184
185 /* Don't touch the hardware controlled clocks */
186 if (clk->hw_ctrld)
187 return;
188
189 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
190 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
191 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
192}
193
194static void syscon_clk_enable(struct clk *clk)
195{
196 unsigned long iflags;
197
198 /* Don't touch the hardware controlled clocks */
199 if (clk->hw_ctrld)
200 return;
201
202 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
203 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
204 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
205}
206
207static u16 syscon_clk_get_rate(void)
208{
209 u16 val;
210 unsigned long iflags;
211
212 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
214 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
215 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
216 return val;
217}
218
219#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
220static void enable_i2s0_vcxo(void)
221{
222 u16 val;
223 unsigned long iflags;
224
225 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
226 /* Set I2S0 to use the VCXO 26 MHz clock */
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
228 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
230 val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
232 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
233 val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
234 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
235 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
236}
237
238static void enable_i2s1_vcxo(void)
239{
240 u16 val;
241 unsigned long iflags;
242
243 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
244 /* Set I2S1 to use the VCXO 26 MHz clock */
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
246 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
248 val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
250 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
251 val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
252 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
253 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
254}
255
256static void disable_i2s0_vcxo(void)
257{
258 u16 val;
259 unsigned long iflags;
260
261 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
262 /* Disable I2S0 use of the VCXO 26 MHz clock */
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
264 val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
266 /* Deactivate VCXO if no one else is using VCXO */
267 if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
268 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
270 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
271 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
272 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
273 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
274}
275
276static void disable_i2s1_vcxo(void)
277{
278 u16 val;
279 unsigned long iflags;
280
281 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
282 /* Disable I2S1 use of the VCXO 26 MHz clock */
283 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
284 val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
285 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
286 /* Deactivate VCXO if no one else is using VCXO */
287 if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
288 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
289 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
290 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
291 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
292 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
293 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
294}
295#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
296
297
298static void syscon_clk_rate_set_mclk(unsigned long rate)
299{
300 u16 val;
301 u32 reg;
302 unsigned long iflags;
303
304 switch (rate) {
305 case 18900000:
306 val = 0x0054;
307 break;
308 case 20800000:
309 val = 0x0044;
310 break;
311 case 23100000:
312 val = 0x0043;
313 break;
314 case 26000000:
315 val = 0x0033;
316 break;
317 case 29700000:
318 val = 0x0032;
319 break;
320 case 34700000:
321 val = 0x0022;
322 break;
323 case 41600000:
324 val = 0x0021;
325 break;
326 case 52000000:
327 val = 0x0011;
328 break;
329 case 104000000:
330 val = 0x0000;
331 break;
332 default:
333 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
334 rate);
335 return;
336 }
337
338 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
339 reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
340 ~U300_SYSCON_MMF0R_MASK;
341 writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
342 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
343}
344
345void syscon_clk_rate_set_cpuclk(unsigned long rate)
346{
347 u16 val;
348 unsigned long iflags;
349
350 switch (rate) {
351 case 13000000:
352 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
353 break;
354 case 52000000:
355 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
356 break;
357 case 104000000:
358 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
359 break;
360 case 208000000:
361 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
362 break;
363 default:
364 return;
365 }
366 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
367 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
368 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
369 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
370 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
371}
372EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
373
374void clk_disable(struct clk *clk)
375{
376 unsigned long iflags;
377
378 spin_lock_irqsave(&clk->lock, iflags);
379 if (clk->usecount > 0 && !(--clk->usecount)) {
380 /* some blocks lack clocking registers and cannot be disabled */
381 if (clk->disable)
382 clk->disable(clk);
383 if (likely((u32)clk->parent))
384 clk_disable(clk->parent);
385 }
386#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
387 if (unlikely(!strcmp(clk->name, "I2S0")))
388 disable_i2s0_vcxo();
389 if (unlikely(!strcmp(clk->name, "I2S1")))
390 disable_i2s1_vcxo();
391#endif
392 spin_unlock_irqrestore(&clk->lock, iflags);
393}
394EXPORT_SYMBOL(clk_disable);
395
396int clk_enable(struct clk *clk)
397{
398 int ret = 0;
399 unsigned long iflags;
400
401 spin_lock_irqsave(&clk->lock, iflags);
402 if (clk->usecount++ == 0) {
403 if (likely((u32)clk->parent))
404 ret = clk_enable(clk->parent);
405
406 if (unlikely(ret != 0))
407 clk->usecount--;
408 else {
409 /* remove reset line (we never enable reset again) */
410 syscon_block_reset_disable(clk);
411 /* clocks without enable function are always on */
412 if (clk->enable)
413 clk->enable(clk);
414#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
415 if (unlikely(!strcmp(clk->name, "I2S0")))
416 enable_i2s0_vcxo();
417 if (unlikely(!strcmp(clk->name, "I2S1")))
418 enable_i2s1_vcxo();
419#endif
420 }
421 }
422 spin_unlock_irqrestore(&clk->lock, iflags);
423 return ret;
424
425}
426EXPORT_SYMBOL(clk_enable);
427
428/* Returns the clock rate in Hz */
429static unsigned long clk_get_rate_cpuclk(struct clk *clk)
430{
431 u16 val;
432
433 val = syscon_clk_get_rate();
434
435 switch (val) {
436 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
437 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
438 return 13000000;
439 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
440 return 52000000;
441 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
442 return 104000000;
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
444 return 208000000;
445 default:
446 break;
447 }
448 return clk->rate;
449}
450
451static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
452{
453 u16 val;
454
455 val = syscon_clk_get_rate();
456
457 switch (val) {
458 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
459 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
460 return 6500000;
461 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
462 return 26000000;
463 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
464 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
465 return 52000000;
466 default:
467 break;
468 }
469 return clk->rate;
470
471}
472
473static unsigned long clk_get_rate_emif_clk(struct clk *clk)
474{
475 u16 val;
476
477 val = syscon_clk_get_rate();
478
479 switch (val) {
480 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
481 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
482 return 13000000;
483 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
484 return 52000000;
485 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
486 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
487 return 104000000;
488 default:
489 break;
490 }
491 return clk->rate;
492
493}
494
495static unsigned long clk_get_rate_xgamclk(struct clk *clk)
496{
497 u16 val;
498
499 val = syscon_clk_get_rate();
500
501 switch (val) {
502 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
503 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
504 return 6500000;
505 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
506 return 26000000;
507 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
508 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
509 return 52000000;
510 default:
511 break;
512 }
513
514 return clk->rate;
515}
516
517static unsigned long clk_get_rate_mclk(struct clk *clk)
518{
519 u16 val;
520
521 val = syscon_clk_get_rate();
522
523 switch (val) {
524 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
525 /*
526 * Here, the 208 MHz PLL gets shut down and the always
527 * on 13 MHz PLL used for RTC etc kicks into use
528 * instead.
529 */
530 return 13000000;
531 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
532 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
533 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
534 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
535 {
536 /*
537 * This clock is under program control. The register is
538 * divided in two nybbles, bit 7-4 gives cycles-1 to count
539 * high, bit 3-0 gives cycles-1 to count low. Distribute
540 * these with no more than 1 cycle difference between
541 * low and high and add low and high to get the actual
542 * divisor. The base PLL is 208 MHz. Writing 0x00 will
543 * divide by 1 and 1 so the highest frequency possible
544 * is 104 MHz.
545 *
546 * e.g. 0x54 =>
547 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
548 */
549 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
550 U300_SYSCON_MMF0R_MASK;
551 switch (val) {
552 case 0x0054:
553 return 18900000;
554 case 0x0044:
555 return 20800000;
556 case 0x0043:
557 return 23100000;
558 case 0x0033:
559 return 26000000;
560 case 0x0032:
561 return 29700000;
562 case 0x0022:
563 return 34700000;
564 case 0x0021:
565 return 41600000;
566 case 0x0011:
567 return 52000000;
568 case 0x0000:
569 return 104000000;
570 default:
571 break;
572 }
573 }
574 default:
575 break;
576 }
577
578 return clk->rate;
579}
580
581static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
582{
583 u16 val;
584
585 val = syscon_clk_get_rate();
586
587 switch (val) {
588 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
589 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
590 return 13000000;
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
592 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
593 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
594 return 26000000;
595 default:
596 break;
597 }
598
599 return clk->rate;
600}
601
602unsigned long clk_get_rate(struct clk *clk)
603{
604 if (clk->get_rate)
605 return clk->get_rate(clk);
606 else
607 return clk->rate;
608}
609EXPORT_SYMBOL(clk_get_rate);
610
611static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
612{
613 if (rate <= 18900000)
614 return 18900000;
615 if (rate <= 20800000)
616 return 20800000;
617 if (rate <= 23100000)
618 return 23100000;
619 if (rate <= 26000000)
620 return 26000000;
621 if (rate <= 29700000)
622 return 29700000;
623 if (rate <= 34700000)
624 return 34700000;
625 if (rate <= 41600000)
626 return 41600000;
627 if (rate <= 52000000)
628 return 52000000;
629 return -EINVAL;
630}
631
632static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
633{
634 if (rate <= 13000000)
635 return 13000000;
636 if (rate <= 52000000)
637 return 52000000;
638 if (rate <= 104000000)
639 return 104000000;
640 if (rate <= 208000000)
641 return 208000000;
642 return -EINVAL;
643}
644
645/*
646 * This adjusts a requested rate to the closest exact rate
647 * a certain clock can provide. For a fixed clock it's
648 * mostly clk->rate.
649 */
650long clk_round_rate(struct clk *clk, unsigned long rate)
651{
652 /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
653 /* Else default to fixed value */
654
655 if (clk->round_rate) {
656 return (long) clk->round_rate(clk, rate);
657 } else {
658 printk(KERN_ERR "clock: Failed to round rate of %s\n",
659 clk->name);
660 }
661 return (long) clk->rate;
662}
663EXPORT_SYMBOL(clk_round_rate);
664
665static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
666{
667 syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
668 return 0;
669}
670
671static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
672{
673 syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
674 return 0;
675}
676
677int clk_set_rate(struct clk *clk, unsigned long rate)
678{
679 /* TODO: set for EMIFCLK and AHBCLK */
680 /* Else assume the clock is fixed and fail */
681 if (clk->set_rate) {
682 return clk->set_rate(clk, rate);
683 } else {
684 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
685 clk->name, rate);
686 return -EINVAL;
687 }
688}
689EXPORT_SYMBOL(clk_set_rate);
690
691/*
692 * Clock definitions. The clock parents are set to respective
693 * bridge and the clock framework makes sure that the clocks have
694 * parents activated and are brought out of reset when in use.
695 *
696 * Clocks that have hw_ctrld = true are hw controlled, and the hw
697 * can by itself turn these clocks on and off.
698 * So in other words, we don't really have to care about them.
699 */
700
701static struct clk amba_clk = {
702 .name = "AMBA",
703 .rate = 52000000, /* this varies! */
704 .hw_ctrld = true,
705 .reset = false,
706 .lock = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
707};
708
709/*
710 * These blocks are connected directly to the AMBA bus
711 * with no bridge.
712 */
713
714static struct clk cpu_clk = {
715 .name = "CPU",
716 .parent = &amba_clk,
717 .rate = 208000000, /* this varies! */
718 .hw_ctrld = true,
719 .reset = true,
720 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
721 .res_mask = U300_SYSCON_RRR_CPU_RESET_EN,
722 .set_rate = clk_set_rate_cpuclk,
723 .get_rate = clk_get_rate_cpuclk,
724 .round_rate = clk_round_rate_cpuclk,
725 .lock = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
726};
727
728static struct clk nandif_clk = {
729 .name = "FSMC",
730 .parent = &amba_clk,
731 .hw_ctrld = false,
732 .reset = true,
733 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
734 .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN,
735 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
736 .enable = syscon_clk_enable,
737 .disable = syscon_clk_disable,
738 .lock = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
739};
740
741static struct clk semi_clk = {
742 .name = "SEMI",
743 .parent = &amba_clk,
744 .rate = 0, /* FIXME */
745 /* It is not possible to reset SEMI */
746 .hw_ctrld = false,
747 .reset = false,
748 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
749 .enable = syscon_clk_enable,
750 .disable = syscon_clk_disable,
751 .lock = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
752};
753
754#ifdef CONFIG_MACH_U300_BS335
755static struct clk isp_clk = {
756 .name = "ISP",
757 .parent = &amba_clk,
758 .rate = 0, /* FIXME */
759 .hw_ctrld = false,
760 .reset = true,
761 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
762 .res_mask = U300_SYSCON_RRR_ISP_RESET_EN,
763 .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN,
764 .enable = syscon_clk_enable,
765 .disable = syscon_clk_disable,
766 .lock = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
767};
768
769static struct clk cds_clk = {
770 .name = "CDS",
771 .parent = &amba_clk,
772 .rate = 0, /* FIXME */
773 .hw_ctrld = false,
774 .reset = true,
775 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
776 .res_mask = U300_SYSCON_RRR_CDS_RESET_EN,
777 .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN,
778 .enable = syscon_clk_enable,
779 .disable = syscon_clk_disable,
780 .lock = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
781};
782#endif
783
784static struct clk dma_clk = {
785 .name = "DMA",
786 .parent = &amba_clk,
787 .rate = 52000000, /* this varies! */
788 .hw_ctrld = true,
789 .reset = true,
790 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
791 .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN,
792 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
793 .enable = syscon_clk_enable,
794 .disable = syscon_clk_disable,
795 .lock = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
796};
797
798static struct clk aaif_clk = {
799 .name = "AAIF",
800 .parent = &amba_clk,
801 .rate = 52000000, /* this varies! */
802 .hw_ctrld = true,
803 .reset = true,
804 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
805 .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN,
806 .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN,
807 .enable = syscon_clk_enable,
808 .disable = syscon_clk_disable,
809 .lock = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
810};
811
812static struct clk apex_clk = {
813 .name = "APEX",
814 .parent = &amba_clk,
815 .rate = 0, /* FIXME */
816 .hw_ctrld = true,
817 .reset = true,
818 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
819 .res_mask = U300_SYSCON_RRR_APEX_RESET_EN,
820 .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN,
821 .enable = syscon_clk_enable,
822 .disable = syscon_clk_disable,
823 .lock = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
824};
825
826static struct clk video_enc_clk = {
827 .name = "VIDEO_ENC",
828 .parent = &amba_clk,
829 .rate = 208000000, /* this varies! */
830 .hw_ctrld = false,
831 .reset = false,
832 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
833 /* This has XGAM in the name but refers to the video encoder */
834 .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
835 .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
836 .enable = syscon_clk_enable,
837 .disable = syscon_clk_disable,
838 .lock = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
839};
840
841static struct clk xgam_clk = {
842 .name = "XGAMCLK",
843 .parent = &amba_clk,
844 .rate = 52000000, /* this varies! */
845 .hw_ctrld = false,
846 .reset = true,
847 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
848 .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN,
849 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
850 .get_rate = clk_get_rate_xgamclk,
851 .enable = syscon_clk_enable,
852 .disable = syscon_clk_disable,
853 .lock = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
854};
855
856/* This clock is used to activate the video encoder */
857static struct clk ahb_clk = {
858 .name = "AHB",
859 .parent = &amba_clk,
860 .rate = 52000000, /* this varies! */
861 .hw_ctrld = false, /* This one is set to false due to HW bug */
862 .reset = true,
863 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
864 .res_mask = U300_SYSCON_RRR_AHB_RESET_EN,
865 .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN,
866 .enable = syscon_clk_enable,
867 .disable = syscon_clk_disable,
868 .get_rate = clk_get_rate_ahb_clk,
869 .lock = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
870};
871
872
873/*
874 * Clocks on the AHB bridge
875 */
876
877static struct clk ahb_subsys_clk = {
878 .name = "AHB_SUBSYS",
879 .parent = &amba_clk,
880 .rate = 52000000, /* this varies! */
881 .hw_ctrld = true,
882 .reset = false,
883 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
884 .enable = syscon_clk_enable,
885 .disable = syscon_clk_disable,
886 .get_rate = clk_get_rate_ahb_clk,
887 .lock = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
888};
889
890static struct clk intcon_clk = {
891 .name = "INTCON",
892 .parent = &ahb_subsys_clk,
893 .rate = 52000000, /* this varies! */
894 .hw_ctrld = false,
895 .reset = true,
896 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
897 .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN,
898 /* INTCON can be reset but not clock-gated */
899 .lock = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
900
901};
902
903static struct clk mspro_clk = {
904 .name = "MSPRO",
905 .parent = &ahb_subsys_clk,
906 .rate = 0, /* FIXME */
907 .hw_ctrld = false,
908 .reset = true,
909 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
910 .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN,
911 .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN,
912 .enable = syscon_clk_enable,
913 .disable = syscon_clk_disable,
914 .lock = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
915};
916
917static struct clk emif_clk = {
918 .name = "EMIF",
919 .parent = &ahb_subsys_clk,
920 .rate = 104000000, /* this varies! */
921 .hw_ctrld = false,
922 .reset = true,
923 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
924 .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN,
925 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
926 .enable = syscon_clk_enable,
927 .disable = syscon_clk_disable,
928 .get_rate = clk_get_rate_emif_clk,
929 .lock = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
930};
931
932
933/*
934 * Clocks on the FAST bridge
935 */
936static struct clk fast_clk = {
937 .name = "FAST_BRIDGE",
938 .parent = &amba_clk,
939 .rate = 13000000, /* this varies! */
940 .hw_ctrld = true,
941 .reset = true,
942 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
943 .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
944 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
945 .enable = syscon_clk_enable,
946 .disable = syscon_clk_disable,
947 .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
948};
949
950/*
951 * The MMCI apb_pclk is hardwired to the same terminal as the
952 * external MCI clock. Thus this will be referenced twice.
953 */
954static struct clk mmcsd_clk = {
955 .name = "MCLK",
956 .parent = &fast_clk,
957 .rate = 18900000, /* this varies! */
958 .hw_ctrld = false,
959 .reset = true,
960 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
961 .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE,
962 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
963 .get_rate = clk_get_rate_mclk,
964 .set_rate = clk_set_rate_mclk,
965 .round_rate = clk_round_rate_mclk,
966 .disable = syscon_clk_disable,
967 .enable = syscon_clk_enable,
968 .lock = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
969};
970
971static struct clk i2s0_clk = {
972 .name = "i2s0",
973 .parent = &fast_clk,
974 .rate = 26000000, /* this varies! */
975 .hw_ctrld = true,
976 .reset = true,
977 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
978 .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
979 .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
980 .enable = syscon_clk_enable,
981 .disable = syscon_clk_disable,
982 .get_rate = clk_get_rate_i2s_i2c_spi,
983 .lock = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
984};
985
986static struct clk i2s1_clk = {
987 .name = "i2s1",
988 .parent = &fast_clk,
989 .rate = 26000000, /* this varies! */
990 .hw_ctrld = true,
991 .reset = true,
992 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
993 .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
994 .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
995 .enable = syscon_clk_enable,
996 .disable = syscon_clk_disable,
997 .get_rate = clk_get_rate_i2s_i2c_spi,
998 .lock = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
999};
1000
1001static struct clk i2c0_clk = {
1002 .name = "I2C0",
1003 .parent = &fast_clk,
1004 .rate = 26000000, /* this varies! */
1005 .hw_ctrld = false,
1006 .reset = true,
1007 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1008 .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
1009 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
1010 .enable = syscon_clk_enable,
1011 .disable = syscon_clk_disable,
1012 .get_rate = clk_get_rate_i2s_i2c_spi,
1013 .lock = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
1014};
1015
1016static struct clk i2c1_clk = {
1017 .name = "I2C1",
1018 .parent = &fast_clk,
1019 .rate = 26000000, /* this varies! */
1020 .hw_ctrld = false,
1021 .reset = true,
1022 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1023 .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
1024 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
1025 .enable = syscon_clk_enable,
1026 .disable = syscon_clk_disable,
1027 .get_rate = clk_get_rate_i2s_i2c_spi,
1028 .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
1029};
1030
1031/*
1032 * The SPI apb_pclk is hardwired to the same terminal as the
1033 * external SPI clock. Thus this will be referenced twice.
1034 */
1035static struct clk spi_clk = {
1036 .name = "SPI",
1037 .parent = &fast_clk,
1038 .rate = 26000000, /* this varies! */
1039 .hw_ctrld = false,
1040 .reset = true,
1041 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1042 .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1043 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
1044 .enable = syscon_clk_enable,
1045 .disable = syscon_clk_disable,
1046 .get_rate = clk_get_rate_i2s_i2c_spi,
1047 .lock = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
1048};
1049
1050#ifdef CONFIG_MACH_U300_BS335
1051static struct clk uart1_pclk = {
1052 .name = "UART1_PCLK",
1053 .parent = &fast_clk,
1054 .hw_ctrld = false,
1055 .reset = true,
1056 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1057 .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1058 .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN,
1059 .enable = syscon_clk_enable,
1060 .disable = syscon_clk_disable,
1061 .lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
1062};
1063
1064/* This one is hardwired to PLL13 */
1065static struct clk uart1_clk = {
1066 .name = "UART1_CLK",
1067 .rate = 13000000,
1068 .hw_ctrld = true,
1069 .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
1070};
1071#endif
1072
1073
1074/*
1075 * Clocks on the SLOW bridge
1076 */
1077static struct clk slow_clk = {
1078 .name = "SLOW_BRIDGE",
1079 .parent = &amba_clk,
1080 .rate = 13000000,
1081 .hw_ctrld = true,
1082 .reset = true,
1083 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1084 .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1085 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1086 .enable = syscon_clk_enable,
1087 .disable = syscon_clk_disable,
1088 .lock = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
1089};
1090
1091/* TODO: implement SYSCON clock? */
1092
1093static struct clk wdog_clk = {
1094 .name = "WDOG",
1095 .parent = &slow_clk,
1096 .hw_ctrld = false,
1097 .rate = 32768,
1098 .reset = false,
1099 /* This is always on, cannot be enabled/disabled or reset */
1100 .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
1101};
1102
1103static struct clk uart0_pclk = {
1104 .name = "UART0_PCLK",
1105 .parent = &slow_clk,
1106 .hw_ctrld = false,
1107 .reset = true,
1108 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1109 .res_mask = U300_SYSCON_RSR_UART_RESET_EN,
1110 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
1111 .enable = syscon_clk_enable,
1112 .disable = syscon_clk_disable,
1113 .lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
1114};
1115
1116/* This one is hardwired to PLL13 */
1117static struct clk uart0_clk = {
1118 .name = "UART0_CLK",
1119 .parent = &slow_clk,
1120 .rate = 13000000,
1121 .hw_ctrld = true,
1122 .lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
1123};
1124
1125static struct clk keypad_clk = {
1126 .name = "KEYPAD",
1127 .parent = &slow_clk,
1128 .rate = 32768,
1129 .hw_ctrld = false,
1130 .reset = true,
1131 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1132 .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1133 .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1134 .enable = syscon_clk_enable,
1135 .disable = syscon_clk_disable,
1136 .lock = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
1137};
1138
1139static struct clk gpio_clk = {
1140 .name = "GPIO",
1141 .parent = &slow_clk,
1142 .rate = 13000000,
1143 .hw_ctrld = true,
1144 .reset = true,
1145 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1146 .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN,
1147 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
1148 .enable = syscon_clk_enable,
1149 .disable = syscon_clk_disable,
1150 .lock = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
1151};
1152
1153static struct clk rtc_clk = {
1154 .name = "RTC",
1155 .parent = &slow_clk,
1156 .rate = 32768,
1157 .hw_ctrld = true,
1158 .reset = true,
1159 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1160 .res_mask = U300_SYSCON_RSR_RTC_RESET_EN,
1161 /* This clock is always on, cannot be enabled/disabled */
1162 .lock = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
1163};
1164
1165static struct clk bustr_clk = {
1166 .name = "BUSTR",
1167 .parent = &slow_clk,
1168 .rate = 13000000,
1169 .hw_ctrld = true,
1170 .reset = true,
1171 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1172 .res_mask = U300_SYSCON_RSR_BTR_RESET_EN,
1173 .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN,
1174 .enable = syscon_clk_enable,
1175 .disable = syscon_clk_disable,
1176 .lock = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
1177};
1178
1179static struct clk evhist_clk = {
1180 .name = "EVHIST",
1181 .parent = &slow_clk,
1182 .rate = 13000000,
1183 .hw_ctrld = true,
1184 .reset = true,
1185 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1186 .res_mask = U300_SYSCON_RSR_EH_RESET_EN,
1187 .clk_val = U300_SYSCON_SBCER_EH_CLK_EN,
1188 .enable = syscon_clk_enable,
1189 .disable = syscon_clk_disable,
1190 .lock = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
1191};
1192
1193static struct clk timer_clk = {
1194 .name = "TIMER",
1195 .parent = &slow_clk,
1196 .rate = 13000000,
1197 .hw_ctrld = true,
1198 .reset = true,
1199 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1200 .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1201 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1202 .enable = syscon_clk_enable,
1203 .disable = syscon_clk_disable,
1204 .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
1205};
1206
1207/*
1208 * There is a binary divider in the hardware that divides
1209 * the 13MHz PLL by 13 down to 1 MHz.
1210 */
1211static struct clk app_timer_clk = {
1212 .name = "TIMER_APP",
1213 .parent = &slow_clk,
1214 .rate = 1000000,
1215 .hw_ctrld = true,
1216 .reset = true,
1217 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1218 .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1219 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1220 .enable = syscon_clk_enable,
1221 .disable = syscon_clk_disable,
1222 .lock = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
1223};
1224
1225#ifdef CONFIG_MACH_U300_BS335
1226static struct clk ppm_clk = {
1227 .name = "PPM",
1228 .parent = &slow_clk,
1229 .rate = 0, /* FIXME */
1230 .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */
1231 .reset = true,
1232 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1233 .res_mask = U300_SYSCON_RSR_PPM_RESET_EN,
1234 .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN,
1235 .enable = syscon_clk_enable,
1236 .disable = syscon_clk_disable,
1237 .lock = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
1238};
1239#endif
1240
1241#define DEF_LOOKUP(devid, clkref) \
1242 { \
1243 .dev_id = devid, \
1244 .clk = clkref, \
1245 }
1246
1247#define DEF_LOOKUP_CON(devid, conid, clkref) \
1248 { \
1249 .dev_id = devid, \
1250 .con_id = conid, \
1251 .clk = clkref, \
1252 }
1253
1254/*
1255 * Here we only define clocks that are meaningful to
1256 * look up through clockdevice.
1257 */
1258static struct clk_lookup lookups[] = {
1259 /* Connected directly to the AMBA bus */
1260 DEF_LOOKUP("amba", &amba_clk),
1261 DEF_LOOKUP("cpu", &cpu_clk),
1262 DEF_LOOKUP("fsmc-nand", &nandif_clk),
1263 DEF_LOOKUP("semi", &semi_clk),
1264#ifdef CONFIG_MACH_U300_BS335
1265 DEF_LOOKUP("isp", &isp_clk),
1266 DEF_LOOKUP("cds", &cds_clk),
1267#endif
1268 DEF_LOOKUP("dma", &dma_clk),
1269 DEF_LOOKUP("msl", &aaif_clk),
1270 DEF_LOOKUP("apex", &apex_clk),
1271 DEF_LOOKUP("video_enc", &video_enc_clk),
1272 DEF_LOOKUP("xgam", &xgam_clk),
1273 DEF_LOOKUP("ahb", &ahb_clk),
1274 /* AHB bridge clocks */
1275 DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
1276 DEF_LOOKUP("intcon", &intcon_clk),
1277 DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
1278 DEF_LOOKUP("mspro", &mspro_clk),
1279 DEF_LOOKUP("pl172", &emif_clk),
1280 DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
1281 /* FAST bridge clocks */
1282 DEF_LOOKUP("fast", &fast_clk),
1283 DEF_LOOKUP("mmci", &mmcsd_clk),
1284 DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
1285 /*
1286 * The .0 and .1 identifiers on these comes from the platform device
1287 * .id field and are assigned when the platform devices are registered.
1288 */
1289 DEF_LOOKUP("i2s.0", &i2s0_clk),
1290 DEF_LOOKUP("i2s.1", &i2s1_clk),
1291 DEF_LOOKUP("stu300.0", &i2c0_clk),
1292 DEF_LOOKUP("stu300.1", &i2c1_clk),
1293 DEF_LOOKUP("pl022", &spi_clk),
1294 DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
1295#ifdef CONFIG_MACH_U300_BS335
1296 DEF_LOOKUP("uart1", &uart1_clk),
1297 DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
1298#endif
1299 /* SLOW bridge clocks */
1300 DEF_LOOKUP("slow", &slow_clk),
1301 DEF_LOOKUP("coh901327_wdog", &wdog_clk),
1302 DEF_LOOKUP("uart0", &uart0_clk),
1303 DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
1304 DEF_LOOKUP("apptimer", &app_timer_clk),
1305 DEF_LOOKUP("coh901461-keypad", &keypad_clk),
1306 DEF_LOOKUP("u300-gpio", &gpio_clk),
1307 DEF_LOOKUP("rtc-coh901331", &rtc_clk),
1308 DEF_LOOKUP("bustr", &bustr_clk),
1309 DEF_LOOKUP("evhist", &evhist_clk),
1310 DEF_LOOKUP("timer", &timer_clk),
1311#ifdef CONFIG_MACH_U300_BS335
1312 DEF_LOOKUP("ppm", &ppm_clk),
1313#endif
1314};
1315
1316static void __init clk_register(void)
1317{
1318 /* Register the lookups */
1319 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1320}
1321
1322#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1323/*
1324 * The following makes it possible to view the status (especially
1325 * reference count and reset status) for the clocks in the platform
1326 * by looking into the special file <debugfs>/u300_clocks
1327 */
1328
1329/* A list of all clocks in the platform */
1330static struct clk *clks[] = {
1331 /* Top node clock for the AMBA bus */
1332 &amba_clk,
1333 /* Connected directly to the AMBA bus */
1334 &cpu_clk,
1335 &nandif_clk,
1336 &semi_clk,
1337#ifdef CONFIG_MACH_U300_BS335
1338 &isp_clk,
1339 &cds_clk,
1340#endif
1341 &dma_clk,
1342 &aaif_clk,
1343 &apex_clk,
1344 &video_enc_clk,
1345 &xgam_clk,
1346 &ahb_clk,
1347
1348 /* AHB bridge clocks */
1349 &ahb_subsys_clk,
1350 &intcon_clk,
1351 &mspro_clk,
1352 &emif_clk,
1353 /* FAST bridge clocks */
1354 &fast_clk,
1355 &mmcsd_clk,
1356 &i2s0_clk,
1357 &i2s1_clk,
1358 &i2c0_clk,
1359 &i2c1_clk,
1360 &spi_clk,
1361#ifdef CONFIG_MACH_U300_BS335
1362 &uart1_clk,
1363 &uart1_pclk,
1364#endif
1365 /* SLOW bridge clocks */
1366 &slow_clk,
1367 &wdog_clk,
1368 &uart0_clk,
1369 &uart0_pclk,
1370 &app_timer_clk,
1371 &keypad_clk,
1372 &gpio_clk,
1373 &rtc_clk,
1374 &bustr_clk,
1375 &evhist_clk,
1376 &timer_clk,
1377#ifdef CONFIG_MACH_U300_BS335
1378 &ppm_clk,
1379#endif
1380};
1381
1382static int u300_clocks_show(struct seq_file *s, void *data)
1383{
1384 struct clk *clk;
1385 int i;
1386
1387 seq_printf(s, "CLOCK DEVICE RESET STATE\t" \
1388 "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1389 seq_printf(s, "---------------------------------------------" \
1390 "-----------------------------------------\n");
1391 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1392 clk = clks[i];
1393 if (clk != ERR_PTR(-ENOENT)) {
1394 /* Format clock and device name nicely */
1395 char cdp[33];
1396 int chars;
1397
1398 chars = snprintf(&cdp[0], 17, "%s", clk->name);
1399 while (chars < 16) {
1400 cdp[chars] = ' ';
1401 chars++;
1402 }
1403 chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1404 dev_name(clk->dev) : "N/A");
1405 while (chars < 16) {
1406 cdp[chars+16] = ' ';
1407 chars++;
1408 }
1409 cdp[32] = '\0';
1410 if (clk->get_rate || clk->rate != 0)
1411 seq_printf(s,
1412 "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1413 &cdp[0],
1414 clk->reset ?
1415 "ASSERTED" : "RELEASED",
1416 clk->usecount ? "ON" : "OFF",
1417 clk->usecount,
1418 clk->hw_ctrld ? "YES" : "NO ",
1419 clk_get_rate(clk));
1420 else
1421 seq_printf(s,
1422 "%s%s\t%s\t%d\t%s\t" \
1423 "(unknown rate)\n",
1424 &cdp[0],
1425 clk->reset ?
1426 "ASSERTED" : "RELEASED",
1427 clk->usecount ? "ON" : "OFF",
1428 clk->usecount,
1429 clk->hw_ctrld ? "YES" : "NO ");
1430 }
1431 }
1432 return 0;
1433}
1434
1435static int u300_clocks_open(struct inode *inode, struct file *file)
1436{
1437 return single_open(file, u300_clocks_show, NULL);
1438}
1439
1440static const struct file_operations u300_clocks_operations = {
1441 .open = u300_clocks_open,
1442 .read = seq_read,
1443 .llseek = seq_lseek,
1444 .release = single_release,
1445};
1446
1447static int __init init_clk_read_debugfs(void)
1448{
1449 /* Expose a simple debugfs interface to view all clocks */
1450 (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1451 NULL, NULL,
1452 &u300_clocks_operations);
1453 return 0;
1454}
1455/*
1456 * This needs to come in after the core_initcall() for the
1457 * overall clocks, because debugfs is not available until
1458 * the subsystems come up.
1459 */
1460module_init(init_clk_read_debugfs);
1461#endif
1462
1463int __init u300_clock_init(void)
1464{
1465 u16 val;
1466
1467 /*
1468 * FIXME: shall all this powermanagement stuff really live here???
1469 */
1470
1471 /* Set system to run at PLL208, max performance, a known state. */
1472 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1473 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1474 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1475 /* Wait for the PLL208 to lock if not locked in yet */
1476 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1477 U300_SYSCON_CSR_PLL208_LOCK_IND));
1478
1479 /* Power management enable */
1480 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1481 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1482 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1483
1484 clk_register();
1485
1486 /*
1487 * Some of these may be on when we boot the system so make sure they
1488 * are turned OFF.
1489 */
1490 syscon_block_reset_enable(&timer_clk);
1491 timer_clk.disable(&timer_clk);
1492
1493 /*
1494 * These shall be turned on by default when we boot the system
1495 * so make sure they are ON. (Adding CPU here is a bit too much.)
1496 * These clocks will be claimed by drivers later.
1497 */
1498 syscon_block_reset_disable(&semi_clk);
1499 syscon_block_reset_disable(&emif_clk);
1500 clk_enable(&semi_clk);
1501 clk_enable(&emif_clk);
1502
1503 return 0;
1504}
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
new file mode 100644
index 00000000000..4f50ca8f901
--- /dev/null
+++ b/arch/arm/mach-u300/clock.h
@@ -0,0 +1,50 @@
1/*
2 * arch/arm/mach-u300/include/mach/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * Copyright (C) 2007-2009 ST-Ericsson AB
8 * Adopted to ST-Ericsson U300 platforms by
9 * Jonas Aaberg <jonas.aberg@stericsson.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#ifndef __MACH_CLOCK_H
18#define __MACH_CLOCK_H
19
20#include <linux/clk.h>
21
22struct clk {
23 struct list_head node;
24 struct module *owner;
25 struct device *dev;
26 const char *name;
27 struct clk *parent;
28
29 spinlock_t lock;
30 unsigned long rate;
31 bool reset;
32 __u16 clk_val;
33 __s8 usecount;
34 void __iomem * res_reg;
35 __u16 res_mask;
36
37 bool hw_ctrld;
38
39 void (*recalc) (struct clk *);
40 int (*set_rate) (struct clk *, unsigned long);
41 unsigned long (*get_rate) (struct clk *);
42 unsigned long (*round_rate) (struct clk *, unsigned long);
43 void (*init) (struct clk *);
44 void (*enable) (struct clk *);
45 void (*disable) (struct clk *);
46};
47
48int u300_clock_init(void);
49
50#endif
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
new file mode 100644
index 00000000000..92e3cc872c6
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4int __clk_get(struct clk *clk);
5void __clk_put(struct clk *clk);
6
7#endif
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
new file mode 100644
index 00000000000..b239149ba0d
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -0,0 +1,69 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/dma_channels.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * Map file for the U300 dma driver.
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef DMA_CHANNELS_H
13#define DMA_CHANNELS_H
14
15#define U300_DMA_MSL_TX_0 0
16#define U300_DMA_MSL_TX_1 1
17#define U300_DMA_MSL_TX_2 2
18#define U300_DMA_MSL_TX_3 3
19#define U300_DMA_MSL_TX_4 4
20#define U300_DMA_MSL_TX_5 5
21#define U300_DMA_MSL_TX_6 6
22#define U300_DMA_MSL_RX_0 7
23#define U300_DMA_MSL_RX_1 8
24#define U300_DMA_MSL_RX_2 9
25#define U300_DMA_MSL_RX_3 10
26#define U300_DMA_MSL_RX_4 11
27#define U300_DMA_MSL_RX_5 12
28#define U300_DMA_MSL_RX_6 13
29#define U300_DMA_MMCSD_RX_TX 14
30#define U300_DMA_MSPRO_TX 15
31#define U300_DMA_MSPRO_RX 16
32#define U300_DMA_UART0_TX 17
33#define U300_DMA_UART0_RX 18
34#define U300_DMA_APEX_TX 19
35#define U300_DMA_APEX_RX 20
36#define U300_DMA_PCM_I2S0_TX 21
37#define U300_DMA_PCM_I2S0_RX 22
38#define U300_DMA_PCM_I2S1_TX 23
39#define U300_DMA_PCM_I2S1_RX 24
40#define U300_DMA_XGAM_CDI 25
41#define U300_DMA_XGAM_PDI 26
42#define U300_DMA_SPI_TX 27
43#define U300_DMA_SPI_RX 28
44#define U300_DMA_GENERAL_PURPOSE_0 29
45#define U300_DMA_GENERAL_PURPOSE_1 30
46#define U300_DMA_GENERAL_PURPOSE_2 31
47#define U300_DMA_GENERAL_PURPOSE_3 32
48#define U300_DMA_GENERAL_PURPOSE_4 33
49#define U300_DMA_GENERAL_PURPOSE_5 34
50#define U300_DMA_GENERAL_PURPOSE_6 35
51#define U300_DMA_GENERAL_PURPOSE_7 36
52#define U300_DMA_GENERAL_PURPOSE_8 37
53#ifdef CONFIG_MACH_U300_BS335
54#define U300_DMA_UART1_TX 38
55#define U300_DMA_UART1_RX 39
56#else
57#define U300_DMA_GENERAL_PURPOSE_9 38
58#define U300_DMA_GENERAL_PURPOSE_10 39
59#endif
60
61#ifdef CONFIG_MACH_U300_BS335
62#define U300_DMA_DEVICE_CHANNELS 32
63#else
64#define U300_DMA_DEVICE_CHANNELS 30
65#endif
66#define U300_DMA_CHANNELS 40
67
68
69#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
new file mode 100644
index 00000000000..20731ae39d3
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/entry-macro.S
@@ -0,0 +1,40 @@
1/*
2 *
3 * arch-arm/mach-u300/include/mach/entry-macro.S
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Low-level IRQ helper macros for ST-Ericsson U300
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12#include <asm/hardware/vic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE
25 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
26 mov \irqnr, #0
27 teq \irqstat, #0
28 bne 1002f
291001: ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE
30 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
31 mov \irqnr, #32
32 teq \irqstat, #0
33 beq 1003f
341002: tst \irqstat, #1
35 bne 1003f
36 add \irqnr, \irqnr, #1
37 movs \irqstat, \irqstat, lsr #1
38 bne 1002b
391003: /* EQ will be set if no irqs pending */
40 .endm
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
new file mode 100644
index 00000000000..d5a71abcbae
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -0,0 +1,294 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/gpio.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * GPIO block resgister definitions and inline macros for
9 * U300 GPIO COH 901 335 or COH 901 571/3
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_GPIO_H
14#define __MACH_U300_GPIO_H
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <mach/hardware.h>
19#include <asm/irq.h>
20
21/* Switch type depending on platform/chip variant */
22#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
23#define U300_COH901335
24#endif
25#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
26#define U300_COH901571_3
27#endif
28
29/* Get base address for regs here */
30#include "u300-regs.h"
31/* IRQ numbers */
32#include "irqs.h"
33
34/*
35 * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
36 * used for anything, and often is. The event/enable etc figures are for
37 * the lowermost pin (pin 0 on each port), shift this left to match your
38 * pin if you're gonna use these values.
39 */
40#ifdef U300_COH901335
41#define U300_GPIO_PORTX_SPACING (0x1C)
42/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
43#define U300_GPIO_PXPDIR (0x00)
44#define U300_GPIO_PXPDOR (0x00)
45/* Port X Pin Config Register 32bit (R/W) */
46#define U300_GPIO_PXPCR (0x04)
47#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
48#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
49#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
50#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
51#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
52#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
53#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
54/* Port X Interrupt Event Register 32bit (R/W) */
55#define U300_GPIO_PXIEV (0x08)
56#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
57#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
58/* Port X Interrupt Enable Register 32bit (R/W) */
59#define U300_GPIO_PXIEN (0x0C)
60#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
61#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
62/* Port X Interrupt Force Register 32bit (R/W) */
63#define U300_GPIO_PXIFR (0x10)
64#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
65#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
66/* Port X Interrupt Config Register 32bit (R/W) */
67#define U300_GPIO_PXICR (0x14)
68#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
69#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
70#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
71#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
72/* Port X Pull-up Enable Register 32bit (R/W) */
73#define U300_GPIO_PXPER (0x18)
74#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
75#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
76/* Control Register 32bit (R/W) */
77#define U300_GPIO_CR (0x54)
78#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
79/* three ports of 8 bits each = GPIO pins 0..23 */
80#define U300_GPIO_NUM_PORTS 3
81#define U300_GPIO_PINS_PER_PORT 8
82#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
83#endif
84
85#ifdef U300_COH901571_3
86/*
87 * Control Register 32bit (R/W)
88 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
89 * gives the number of GPIO pins.
90 * bit 8-2 (mask 0x000001FC) contains the core version ID.
91 */
92#define U300_GPIO_CR (0x00)
93#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
94#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
95#define U300_GPIO_PORTX_SPACING (0x30)
96/* Port X Pin Data INPUT Register 32bit (R/W) */
97#define U300_GPIO_PXPDIR (0x04)
98/* Port X Pin Data OUTPUT Register 32bit (R/W) */
99#define U300_GPIO_PXPDOR (0x08)
100/* Port X Pin Config Register 32bit (R/W) */
101#define U300_GPIO_PXPCR (0x0C)
102#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
103#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
104#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
105#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
106#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
107#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
108#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
109/* Port X Pull-up Enable Register 32bit (R/W) */
110#define U300_GPIO_PXPER (0x10)
111#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
112#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
113/* Port X Interrupt Event Register 32bit (R/W) */
114#define U300_GPIO_PXIEV (0x14)
115#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
116#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
117/* Port X Interrupt Enable Register 32bit (R/W) */
118#define U300_GPIO_PXIEN (0x18)
119#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
120#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
121/* Port X Interrupt Force Register 32bit (R/W) */
122#define U300_GPIO_PXIFR (0x1C)
123#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
124#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
125/* Port X Interrupt Config Register 32bit (R/W) */
126#define U300_GPIO_PXICR (0x20)
127#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
128#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
129#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
130#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
131#ifdef CONFIG_MACH_U300_BS335
132/* seven ports of 8 bits each = GPIO pins 0..55 */
133#define U300_GPIO_NUM_PORTS 7
134#else
135/* five ports of 8 bits each = GPIO pins 0..39 */
136#define U300_GPIO_NUM_PORTS 5
137#endif
138#define U300_GPIO_PINS_PER_PORT 8
139#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
140#endif
141
142/*
143 * Individual pin assignments for the B26/S26. Notice that the
144 * actual usage of these pins depends on the PAD MUX settings, that
145 * is why the same number can potentially appear several times.
146 * In the reference design each pin is only used for one purpose.
147 * These were determined by inspecting the B26/S26 schematic:
148 * 2/1911-ROA 128 1603
149 */
150#ifdef CONFIG_MACH_U300_BS2X
151#define U300_GPIO_PIN_UART_RX 0
152#define U300_GPIO_PIN_UART_TX 1
153#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
154#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
155#define U300_GPIO_PIN_CAM_SLEEP 4
156#define U300_GPIO_PIN_CAM_REG_EN 5
157#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
158#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
159
160#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
161#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
162#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
163#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
164#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
165#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
166#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
167#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
168
169#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
170#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
171#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
172#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
173#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
174#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
175#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
176#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
177#endif
178
179/*
180 * Individual pin assignments for the B330/S330 and B365/S365.
181 * Notice that the actual usage of these pins depends on the
182 * PAD MUX settings, that is why the same number can potentially
183 * appear several times. In the reference design each pin is only
184 * used for one purpose. These were determined by inspecting the
185 * S365 schematic.
186 */
187#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
188 defined(CONFIG_MACH_U300_BS335)
189#define U300_GPIO_PIN_UART_RX 0
190#define U300_GPIO_PIN_UART_TX 1
191#define U300_GPIO_PIN_UART_CTS 2
192#define U300_GPIO_PIN_UART_RTS 3
193#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
194#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
195#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
196#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
197
198#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
199#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
200#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
201#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
202#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
203#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
204#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
205#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
206
207#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
208#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
209#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
210#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
211#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
212#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
213#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
214#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
215
216#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
217#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
218#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
219#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
220#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
221#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
222#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
223#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
224
225#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
226#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
227#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
228#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
229#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
230#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
231#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
232#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
233
234#ifdef CONFIG_MACH_U300_BS335
235
236#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
237#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
238#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
239#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
240#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
241#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
242#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
243#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
244
245#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
246#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
247#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
248#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
249#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
250#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
251#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
252#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
253#endif
254
255#endif
256
257/* translates a pin number to a port number */
258#define PIN_TO_PORT(val) (val >> 3)
259
260/* These can be found in arch/arm/mach-u300/gpio.c */
261extern int gpio_is_valid(int number);
262extern int gpio_request(unsigned gpio, const char *label);
263extern void gpio_free(unsigned gpio);
264extern int gpio_direction_input(unsigned gpio);
265extern int gpio_direction_output(unsigned gpio, int value);
266extern int gpio_register_callback(unsigned gpio,
267 int (*func)(void *arg),
268 void *);
269extern int gpio_unregister_callback(unsigned gpio);
270extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
271extern void disable_irq_on_gpio_pin(unsigned gpio);
272extern void gpio_pullup(unsigned gpio, int value);
273extern int gpio_get_value(unsigned gpio);
274extern void gpio_set_value(unsigned gpio, int value);
275
276#define gpio_get_value_cansleep gpio_get_value
277#define gpio_set_value_cansleep gpio_set_value
278
279/* wrappers to sleep-enable the previous two functions */
280static inline unsigned gpio_to_irq(unsigned gpio)
281{
282 return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
283}
284
285static inline unsigned irq_to_gpio(unsigned irq)
286{
287 /*
288 * FIXME: This is no 1-1 mapping at all, it points to the
289 * whole block of 8 pins.
290 */
291 return (irq - IRQ_U300_GPIO_PORT0) << 3;
292}
293
294#endif
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
new file mode 100644
index 00000000000..5d6b4c13b3a
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/io.h
@@ -0,0 +1,20 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/io.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Dummy IO map for being able to use writew()/readw(),
9 * writel()/readw() and similar accessor functions.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12#ifndef __MACH_IO_H
13#define __MACH_IO_H
14
15#define IO_SPACE_LIMIT 0xffffffff
16
17#define __io(a) __typesafe_io(a)
18#define __mem_pci(a) (a)
19
20#endif
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
new file mode 100644
index 00000000000..888e2e351ee
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -0,0 +1,42 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/memory.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Memory virtual/physical mapping constants.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 */
12
13#ifndef __MACH_MEMORY_H
14#define __MACH_MEMORY_H
15
16#ifdef CONFIG_MACH_U300_DUAL_RAM
17
18#define PLAT_PHYS_OFFSET UL(0x48000000)
19#define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100)
20
21#else
22
23#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
24#define PLAT_PHYS_OFFSET (0x28000000 + \
25 (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
26 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
27#else
28#define PLAT_PHYS_OFFSET (0x28000000 + \
29 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
30 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
31#endif
32#define BOOT_PARAMS_OFFSET (0x28000000 + \
33 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
34 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
35#endif
36
37/*
38 * We enable a real big DMA buffer if need be.
39 */
40#define CONSISTENT_DMA_SIZE SZ_4M
41
42#endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
new file mode 100644
index 00000000000..77d9210a82e
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/platform.h
@@ -0,0 +1,19 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/platform.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Basic platform init and mapping functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11
12#ifndef __ASSEMBLY__
13
14void u300_map_io(void);
15void u300_init_irq(void);
16void u300_init_devices(void);
17extern struct sys_timer u300_timer;
18
19#endif
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
new file mode 100644
index 00000000000..8daf13634ce
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/system.h
@@ -0,0 +1,42 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/system.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * System shutdown and reset functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12#include <asm/io.h>
13#include <asm/hardware/vic.h>
14#include <asm/irq.h>
15
16/* Forward declare this function from the watchdog */
17void coh901327_watchdog_reset(void);
18
19static inline void arch_idle(void)
20{
21 cpu_do_idle();
22}
23
24static void arch_reset(char mode, const char *cmd)
25{
26 switch (mode) {
27 case 's':
28 case 'h':
29 printk(KERN_CRIT "RESET: shutting down/rebooting system\n");
30 /* Disable interrupts */
31 local_irq_disable();
32#ifdef CONFIG_COH901327_WATCHDOG
33 coh901327_watchdog_reset();
34#endif
35 break;
36 default:
37 /* Do nothing */
38 break;
39 }
40 /* Wait for system do die/reset. */
41 while (1);
42}
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
new file mode 100644
index 00000000000..ec423b92b81
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/vmalloc.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Virtual memory allocations
9 * End must be above the I/O registers and on an even 2MiB boundary.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12#define VMALLOC_END 0xfe800000UL
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
new file mode 100644
index 00000000000..677ccef5cd3
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.c
@@ -0,0 +1,68 @@
1/*
2 *
3 * arch/arm/mach-u300/mmc.c
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Johan Lundin
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */
13#include <linux/device.h>
14#include <linux/amba/bus.h>
15#include <linux/mmc/host.h>
16#include <linux/gpio.h>
17#include <linux/dmaengine.h>
18#include <linux/amba/mmci.h>
19#include <linux/slab.h>
20#include <mach/coh901318.h>
21#include <mach/dma_channels.h>
22
23#include "mmc.h"
24#include "padmux.h"
25
26static struct mmci_platform_data mmc0_plat_data = {
27 /*
28 * Do not set ocr_mask or voltage translation function,
29 * we have a regulator we can control instead.
30 */
31 /* Nominally 2.85V on our platform */
32 .f_max = 24000000,
33 .gpio_wp = -1,
34 .gpio_cd = U300_GPIO_PIN_MMC_CD,
35 .cd_invert = true,
36 .capabilities = MMC_CAP_MMC_HIGHSPEED |
37 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
38#ifdef CONFIG_COH901318
39 .dma_filter = coh901318_filter_id,
40 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
41 /* Don't specify a TX channel, this RX channel is bidirectional */
42#endif
43};
44
45int __devinit mmc_init(struct amba_device *adev)
46{
47 struct device *mmcsd_device = &adev->dev;
48 struct pmx *pmx;
49 int ret = 0;
50
51 mmcsd_device->platform_data = &mmc0_plat_data;
52
53 /*
54 * Setup padmuxing for MMC. Since this must always be
55 * compiled into the kernel, pmx is never released.
56 */
57 pmx = pmx_get(mmcsd_device, U300_APP_PMX_MMC_SETTING);
58
59 if (IS_ERR(pmx))
60 pr_warning("Could not get padmux handle\n");
61 else {
62 ret = pmx_activate(mmcsd_device, pmx);
63 if (IS_ERR_VALUE(ret))
64 pr_warning("Could not activate padmuxing\n");
65 }
66
67 return ret;
68}
diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h
new file mode 100644
index 00000000000..92b85125abb
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.h
@@ -0,0 +1,18 @@
1/*
2 *
3 * arch/arm/mach-u300/mmc.h
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 *
9 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
10 */
11#ifndef MMC_H
12#define MMC_H
13
14#include <linux/amba/bus.h>
15
16int __devinit mmc_init(struct amba_device *adev);
17
18#endif
diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c
new file mode 100644
index 00000000000..4c93c6cefd3
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.c
@@ -0,0 +1,367 @@
1/*
2 *
3 * arch/arm/mach-u300/padmux.c
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 PADMUX functions
9 * Author: Martin Persson <martin.persson@stericsson.com>
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/device.h>
15#include <linux/err.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18#include <linux/mutex.h>
19#include <linux/string.h>
20#include <linux/bug.h>
21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
23#include <mach/u300-regs.h>
24#include <mach/syscon.h>
25#include "padmux.h"
26
27static DEFINE_MUTEX(pmx_mutex);
28
29const u32 pmx_registers[] = {
30 (U300_SYSCON_VBASE + U300_SYSCON_PMC1LR),
31 (U300_SYSCON_VBASE + U300_SYSCON_PMC1HR),
32 (U300_SYSCON_VBASE + U300_SYSCON_PMC2R),
33 (U300_SYSCON_VBASE + U300_SYSCON_PMC3R),
34 (U300_SYSCON_VBASE + U300_SYSCON_PMC4R)
35};
36
37/* High level functionality */
38
39/* Lazy dog:
40 * onmask = {
41 * {"PMC1LR" mask, "PMC1LR" value},
42 * {"PMC1HR" mask, "PMC1HR" value},
43 * {"PMC2R" mask, "PMC2R" value},
44 * {"PMC3R" mask, "PMC3R" value},
45 * {"PMC4R" mask, "PMC4R" value}
46 * }
47 */
48static struct pmx mmc_setting = {
49 .setting = U300_APP_PMX_MMC_SETTING,
50 .default_on = false,
51 .activated = false,
52 .name = "MMC",
53 .onmask = {
54 {U300_SYSCON_PMC1LR_MMCSD_MASK,
55 U300_SYSCON_PMC1LR_MMCSD_MMCSD},
56 {0, 0},
57 {0, 0},
58 {0, 0},
59 {U300_SYSCON_PMC4R_APP_MISC_12_MASK,
60 U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO}
61 },
62};
63
64static struct pmx spi_setting = {
65 .setting = U300_APP_PMX_SPI_SETTING,
66 .default_on = false,
67 .activated = false,
68 .name = "SPI",
69 .onmask = {{0, 0},
70 {U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
71 U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
72 U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
73 U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
74 U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
75 U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI},
76 {0, 0},
77 {0, 0},
78 {0, 0}
79 },
80};
81
82/* Available padmux settings */
83static struct pmx *pmx_settings[] = {
84 &mmc_setting,
85 &spi_setting,
86};
87
88static void update_registers(struct pmx *pmx, bool activate)
89{
90 u16 regval, val, mask;
91 int i;
92
93 for (i = 0; i < ARRAY_SIZE(pmx_registers); i++) {
94 if (activate)
95 val = pmx->onmask[i].val;
96 else
97 val = 0;
98
99 mask = pmx->onmask[i].mask;
100 if (mask != 0) {
101 regval = readw(pmx_registers[i]);
102 regval &= ~mask;
103 regval |= val;
104 writew(regval, pmx_registers[i]);
105 }
106 }
107}
108
109struct pmx *pmx_get(struct device *dev, enum pmx_settings setting)
110{
111 int i;
112 struct pmx *pmx = ERR_PTR(-ENOENT);
113
114 if (dev == NULL)
115 return ERR_PTR(-EINVAL);
116
117 mutex_lock(&pmx_mutex);
118 for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) {
119
120 if (setting == pmx_settings[i]->setting) {
121
122 if (pmx_settings[i]->dev != NULL) {
123 WARN(1, "padmux: required setting "
124 "in use by another consumer\n");
125 } else {
126 pmx = pmx_settings[i];
127 pmx->dev = dev;
128 dev_dbg(dev, "padmux: setting nr %d is now "
129 "bound to %s and ready to use\n",
130 setting, dev_name(dev));
131 break;
132 }
133 }
134 }
135 mutex_unlock(&pmx_mutex);
136
137 return pmx;
138}
139EXPORT_SYMBOL(pmx_get);
140
141int pmx_put(struct device *dev, struct pmx *pmx)
142{
143 int i;
144 int ret = -ENOENT;
145
146 if (pmx == NULL || dev == NULL)
147 return -EINVAL;
148
149 mutex_lock(&pmx_mutex);
150 for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) {
151
152 if (pmx->setting == pmx_settings[i]->setting) {
153
154 if (dev != pmx->dev) {
155 WARN(1, "padmux: cannot release handle as "
156 "it is bound to another consumer\n");
157 ret = -EINVAL;
158 break;
159 } else {
160 pmx_settings[i]->dev = NULL;
161 ret = 0;
162 break;
163 }
164 }
165 }
166 mutex_unlock(&pmx_mutex);
167
168 return ret;
169}
170EXPORT_SYMBOL(pmx_put);
171
172int pmx_activate(struct device *dev, struct pmx *pmx)
173{
174 int i, j, ret;
175 ret = 0;
176
177 if (pmx == NULL || dev == NULL)
178 return -EINVAL;
179
180 mutex_lock(&pmx_mutex);
181
182 /* Make sure the required bits are not used */
183 for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) {
184
185 if (pmx_settings[i]->dev == NULL || pmx_settings[i] == pmx)
186 continue;
187
188 for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) {
189
190 if (pmx_settings[i]->onmask[j].mask & pmx->
191 onmask[j].mask) {
192 /* More than one entry on the same bits */
193 WARN(1, "padmux: cannot activate "
194 "setting. Bit conflict with "
195 "an active setting\n");
196
197 ret = -EUSERS;
198 goto exit;
199 }
200 }
201 }
202 update_registers(pmx, true);
203 pmx->activated = true;
204 dev_dbg(dev, "padmux: setting nr %d is activated\n",
205 pmx->setting);
206
207exit:
208 mutex_unlock(&pmx_mutex);
209 return ret;
210}
211EXPORT_SYMBOL(pmx_activate);
212
213int pmx_deactivate(struct device *dev, struct pmx *pmx)
214{
215 int i;
216 int ret = -ENOENT;
217
218 if (pmx == NULL || dev == NULL)
219 return -EINVAL;
220
221 mutex_lock(&pmx_mutex);
222 for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) {
223
224 if (pmx_settings[i]->dev == NULL)
225 continue;
226
227 if (pmx->setting == pmx_settings[i]->setting) {
228
229 if (dev != pmx->dev) {
230 WARN(1, "padmux: cannot deactivate "
231 "pmx setting as it was activated "
232 "by another consumer\n");
233
234 ret = -EBUSY;
235 continue;
236 } else {
237 update_registers(pmx, false);
238 pmx_settings[i]->dev = NULL;
239 pmx->activated = false;
240 ret = 0;
241 dev_dbg(dev, "padmux: setting nr %d is deactivated",
242 pmx->setting);
243 break;
244 }
245 }
246 }
247 mutex_unlock(&pmx_mutex);
248
249 return ret;
250}
251EXPORT_SYMBOL(pmx_deactivate);
252
253/*
254 * For internal use only. If it is to be exported,
255 * it should be reentrant. Notice that pmx_activate
256 * (i.e. runtime settings) always override default settings.
257 */
258static int pmx_set_default(void)
259{
260 /* Used to identify several entries on the same bits */
261 u16 modbits[ARRAY_SIZE(pmx_registers)];
262
263 int i, j;
264
265 memset(modbits, 0, ARRAY_SIZE(pmx_registers) * sizeof(u16));
266
267 for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) {
268
269 if (!pmx_settings[i]->default_on)
270 continue;
271
272 for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) {
273
274 /* Make sure there is only one entry on the same bits */
275 if (modbits[j] & pmx_settings[i]->onmask[j].mask) {
276 BUG();
277 return -EUSERS;
278 }
279 modbits[j] |= pmx_settings[i]->onmask[j].mask;
280 }
281 update_registers(pmx_settings[i], true);
282 }
283 return 0;
284}
285
286#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
287static int pmx_show(struct seq_file *s, void *data)
288{
289 int i;
290 seq_printf(s, "-------------------------------------------------\n");
291 seq_printf(s, "SETTING BOUND TO DEVICE STATE\n");
292 seq_printf(s, "-------------------------------------------------\n");
293 mutex_lock(&pmx_mutex);
294 for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) {
295 /* Format pmx and device name nicely */
296 char cdp[33];
297 int chars;
298
299 chars = snprintf(&cdp[0], 17, "%s", pmx_settings[i]->name);
300 while (chars < 16) {
301 cdp[chars] = ' ';
302 chars++;
303 }
304 chars = snprintf(&cdp[16], 17, "%s", pmx_settings[i]->dev ?
305 dev_name(pmx_settings[i]->dev) : "N/A");
306 while (chars < 16) {
307 cdp[chars+16] = ' ';
308 chars++;
309 }
310 cdp[32] = '\0';
311
312 seq_printf(s,
313 "%s\t%s\n",
314 &cdp[0],
315 pmx_settings[i]->activated ?
316 "ACTIVATED" : "DEACTIVATED"
317 );
318
319 }
320 mutex_unlock(&pmx_mutex);
321 return 0;
322}
323
324static int pmx_open(struct inode *inode, struct file *file)
325{
326 return single_open(file, pmx_show, NULL);
327}
328
329static const struct file_operations pmx_operations = {
330 .owner = THIS_MODULE,
331 .open = pmx_open,
332 .read = seq_read,
333 .llseek = seq_lseek,
334 .release = single_release,
335};
336
337static int __init init_pmx_read_debugfs(void)
338{
339 /* Expose a simple debugfs interface to view pmx settings */
340 (void) debugfs_create_file("padmux", S_IFREG | S_IRUGO,
341 NULL, NULL,
342 &pmx_operations);
343 return 0;
344}
345
346/*
347 * This needs to come in after the core_initcall(),
348 * because debugfs is not available until
349 * the subsystems come up.
350 */
351module_init(init_pmx_read_debugfs);
352#endif
353
354static int __init pmx_init(void)
355{
356 int ret;
357
358 ret = pmx_set_default();
359
360 if (IS_ERR_VALUE(ret))
361 pr_crit("padmux: default settings could not be set\n");
362
363 return 0;
364}
365
366/* Should be initialized before consumers */
367core_initcall(pmx_init);
diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h
new file mode 100644
index 00000000000..6e8b8606409
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.h
@@ -0,0 +1,39 @@
1/*
2 *
3 * arch/arm/mach-u300/padmux.h
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 PADMUX API
9 * Author: Martin Persson <martin.persson@stericsson.com>
10 */
11
12#ifndef __MACH_U300_PADMUX_H
13#define __MACH_U300_PADMUX_H
14
15enum pmx_settings {
16 U300_APP_PMX_MMC_SETTING,
17 U300_APP_PMX_SPI_SETTING
18};
19
20struct pmx_onmask {
21 u16 mask; /* Mask bits */
22 u16 val; /* Value when active */
23};
24
25struct pmx {
26 struct device *dev;
27 enum pmx_settings setting;
28 char *name;
29 bool activated;
30 bool default_on;
31 struct pmx_onmask onmask[];
32};
33
34struct pmx *pmx_get(struct device *dev, enum pmx_settings setting);
35int pmx_put(struct device *dev, struct pmx *pmx);
36int pmx_activate(struct device *dev, struct pmx *pmx);
37int pmx_deactivate(struct device *dev, struct pmx *pmx);
38
39#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
new file mode 100644
index 00000000000..48b3b7f3996
--- /dev/null
+++ b/arch/arm/mach-u300/u300.c
@@ -0,0 +1,70 @@
1/*
2 *
3 * arch/arm/mach-u300/u300.c
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Platform machine definition.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/memblock.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <mach/hardware.h>
21#include <mach/platform.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/memory.h>
25
26static void __init u300_reserve(void)
27{
28 /*
29 * U300 - This platform family can share physical memory
30 * between two ARM cpus, one running Linux and the other
31 * running another OS.
32 */
33#ifdef CONFIG_MACH_U300_SINGLE_RAM
34#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
35 CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
36 memblock_reserve(PHYS_OFFSET, 0x00100000);
37#endif
38#endif
39}
40
41static void __init u300_init_machine(void)
42{
43 u300_init_devices();
44}
45
46#ifdef CONFIG_MACH_U300_BS2X
47#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
48#endif
49
50#ifdef CONFIG_MACH_U300_BS330
51#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
52#endif
53
54#ifdef CONFIG_MACH_U300_BS335
55#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
56#endif
57
58#ifdef CONFIG_MACH_U300_BS365
59#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
60#endif
61
62MACHINE_START(U300, MACH_U300_STRING)
63 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
64 .boot_params = BOOT_PARAMS_OFFSET,
65 .map_io = u300_map_io,
66 .reserve = u300_reserve,
67 .init_irq = u300_init_irq,
68 .timer = &u300_timer,
69 .init_machine = u300_init_machine,
70MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 08:21:54 -0400