Patched in Tegra support.

15 files changed, 731 insertions, 387 deletions

diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f597647d43..32a7b0f7e9f 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,16 +1,71 @@
 if ARCH_U300
 
-menu "ST-Ericsson AB U300/U335 Platform"
+menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
 config MACH_U300
         bool "U300"
-        select PINCTRL
-        select PINCTRL_COH901
-        select PINCTRL_U300
 
-comment "ST-Ericsson U300/U335 Feature Selections"
+comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
+
+choice
+        prompt "U300/U330/U335/U365 system type"
+        default MACH_U300_BS2X
+        ---help---
+        You need to select the target system, i.e. the
+        U300/U330/U335/U365 board that you want to compile your kernel
+        for.
+
+config MACH_U300_BS2X
+        bool "S26/S26/B25/B26 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S26/S25 test products. (Also works on
+                B26/B25 big boards.)
+
+config MACH_U300_BS330
+        bool "S330/B330 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S330/B330 test products.
+
+config MACH_U300_BS335
+        bool "S335/B335 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S335/B335 test products.
+
+config MACH_U300_BS365
+        bool "S365/B365 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S365/B365 test products.
+
+endchoice
+
+choice
+        prompt "Memory configuration"
+        default MACH_U300_SINGLE_RAM
+        ---help---
+        You have to config the kernel according to the physical memory
+        configuration.
+
+config MACH_U300_SINGLE_RAM
+        bool "Single RAM"
+        help
+                Select this if you want support for Single RAM phones.
+
+config MACH_U300_DUAL_RAM
+        bool "Dual RAM"
+        help
+                Select this if you want support for Dual RAM phones.
+                This is two RAM memories on different EMIFs.
+endchoice
 
 config U300_DEBUG
         bool "Debug support for U300"
@@ -18,6 +73,14 @@ config U300_DEBUG
         help
                 Debug support for U300 in sysfs, procfs etc.
 
+config MACH_U300_SEMI_IS_SHARED
+        bool "The SEMI is used by both the access and application side"
+        depends on MACH_U300
+        help
+                This makes it possible to use the SEMI (Shared External
+                Memory Interface) from both from access and application
+                side.
+
 config MACH_U300_SPIDUMMY
         bool "SSP/SPI dummy chip"
         select SPI
@@ -30,6 +93,25 @@ config MACH_U300_SPIDUMMY
                 you don't need it. Selecting this will activate the
                 SPI framework and ARM PL022 support.
 
+comment "All the settings below must match the bootloader's settings"
+
+config MACH_U300_ACCESS_MEM_SIZE
+       int "Access CPU memory allocation"
+       range 7 25
+       depends on MACH_U300_SINGLE_RAM
+       default 13
+       help
+                How much memory in MiB that the Access side CPU has allocated
+
+config MACH_U300_2MB_ALIGNMENT_FIX
+       bool "2MiB alignment fix"
+       depends on MACH_U300_SINGLE_RAM
+       default y
+       help
+                If yes and the Access side CPU has allocated an odd size in
+                MiB, this fix gives you one MiB extra that would otherwise be
+                lost due to Linux 2 MiB alignment policy.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58da39..8fd354aaf0a 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,11 +2,13 @@
 # Makefile for the linux kernel, U300 machine.
 #
 
-obj-y           := core.o timer.o
+obj-y           := core.o clock.o timer.o padmux.o
 obj-m           :=
 obj-n           :=
 obj-            :=
 
+obj-$(CONFIG_ARCH_U300)           += u300.o
+obj-$(CONFIG_MMC)                 += mmc.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot
index 87811de0bd9..6fbfc6ea2d3 100644
--- a/arch/arm/mach-u300/Makefile.boot
+++ b/arch/arm/mach-u300/Makefile.boot
@@ -1,4 +1,15 @@
-   zreladdr-y   += 0x48008000
-params_phys-y   := 0x48000100
+# Note: the following conditions must always be true:
+#   ZRELADDR == virt_to_phys(TEXTADDR)
+#   PARAMS_PHYS must be within 4MB of ZRELADDR
+#   INITRD_PHYS must be in RAM
+
+ifdef CONFIG_MACH_U300_SINGLE_RAM
+     zreladdr-y := 0x28E08000
+  params_phys-y := 0x28E00100
+else
+     zreladdr-y := 0x48008000
+  params_phys-y := 0x48000100
+endif
+
 # This isn't used.
-#initrd_phys-y  := 0x48800000
+#initrd_phys-y  := 0x29800000
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 4ce77cdc31c..399c89f14df 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2012 ST-Ericsson SA
+ * Copyright (C) 2007-2010 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -18,7 +18,6 @@
 #include <linux/termios.h>
 #include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
 #include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
@@ -26,30 +25,23 @@
 #include <linux/err.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/fsmc.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_data/clk-u300.h>
-#include <linux/platform_data/pinctrl-coh901.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
 
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
-#include <mach/irqs.h>
+#include <mach/dma_channels.h>
 
-#include "timer.h"
+#include "clock.h"
+#include "mmc.h"
 #include "spi.h"
 #include "i2c.h"
-#include "u300-gpio.h"
-#include "dma_channels.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -76,9 +68,28 @@ static struct map_desc u300_io_desc[] __initdata = {
                 .length         = SZ_32K,
                 .type           = MT_DEVICE,
         },
+        {
+                .virtual        = 0xffff2000, /* TCM memory */
+                .pfn            = __phys_to_pfn(0xffff2000),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+
+        /*
+         * This overlaps with the IRQ vectors etc at 0xffff0000, so these
+         * may have to be moved to 0x00000000 in order to use the ROM.
+         */
+        /*
+        {
+                .virtual        = U300_BOOTROM_VIRT_BASE,
+                .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
+                .length         = SZ_64K,
+                .type           = MT_ROM,
+        },
+        */
 };
 
-static void __init u300_map_io(void)
+void __init u300_map_io(void)
 {
         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 }
@@ -96,11 +107,22 @@ static struct amba_pl011_data uart0_plat_data = {
 #endif
 };
 
-/* Slow device at 0x3000 offset */
-static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
-        { IRQ_U300_UART0 }, &uart0_plat_data);
+static struct amba_device uart0_device = {
+        .dev = {
+                .coherent_dma_mask = ~0,
+                .init_name = "uart0", /* Slow device at 0x3000 offset */
+                .platform_data = &uart0_plat_data,
+        },
+        .res = {
+                .start = U300_UART0_BASE,
+                .end   = U300_UART0_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = { IRQ_U300_UART0, NO_IRQ },
+};
 
 /* The U335 have an additional UART1 on the APP CPU */
+#ifdef CONFIG_MACH_U300_BS335
 static struct amba_pl011_data uart1_plat_data = {
 #ifdef CONFIG_COH901318
         .dma_filter = coh901318_filter_id,
@@ -109,40 +131,71 @@ static struct amba_pl011_data uart1_plat_data = {
 #endif
 };
 
-/* Fast device at 0x7000 offset */
-static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
-        { IRQ_U300_UART1 }, &uart1_plat_data);
-
-/* AHB device at 0x4000 offset */
-static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
+static struct amba_device uart1_device = {
+        .dev = {
+                .coherent_dma_mask = ~0,
+                .init_name = "uart1", /* Fast device at 0x7000 offset */
+                .platform_data = &uart1_plat_data,
+        },
+        .res = {
+                .start = U300_UART1_BASE,
+                .end   = U300_UART1_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = { IRQ_U300_UART1, NO_IRQ },
+};
+#endif
 
-/* Fast device at 0x6000 offset */
-static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
-        { IRQ_U300_SPI }, NULL);
+static struct amba_device pl172_device = {
+        .dev = {
+                .init_name = "pl172", /* AHB device at 0x4000 offset */
+                .platform_data = NULL,
+        },
+        .res = {
+                .start = U300_EMIF_CFG_BASE,
+                .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
 
-/* Fast device at 0x1000 offset */
-#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 
-static struct mmci_platform_data mmcsd_platform_data = {
+/*
+ * Everything within this next ifdef deals with external devices connected to
+ * the APP SPI bus.
+ */
+static struct amba_device pl022_device = {
+        .dev = {
+                .coherent_dma_mask = ~0,
+                .init_name = "pl022", /* Fast device at 0x6000 offset */
+        },
+        .res = {
+                .start = U300_SPI_BASE,
+                .end   = U300_SPI_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_U300_SPI, NO_IRQ },
         /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
+         * This device has a DMA channel but the Linux driver does not use
+         * it currently.
          */
-        .f_max = 24000000,
-        .gpio_wp = -1,
-        .gpio_cd = U300_GPIO_PIN_MMC_CD,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-        /* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
 };
 
-static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
-        U300_MMCSD_IRQS, &mmcsd_platform_data);
+static struct amba_device mmcsd_device = {
+        .dev = {
+                .init_name = "mmci", /* Fast device at 0x1000 offset */
+                .platform_data = NULL, /* Added later */
+        },
+        .res = {
+                .start = U300_MMCSD_BASE,
+                .end   = U300_MMCSD_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
+        /*
+         * This device has a DMA channel but the Linux driver does not use
+         * it currently.
+         */
+};
 
 /*
  * The order of device declaration may be important, since some devices
@@ -150,7 +203,9 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
  */
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
+#ifdef CONFIG_MACH_U300_BS335
         &uart1_device,
+#endif
         &pl022_device,
         &pl172_device,
         &mmcsd_device,
@@ -184,6 +239,7 @@ static struct resource gpio_resources[] = {
                 .end   = IRQ_U300_GPIO_PORT2,
                 .flags = IORESOURCE_IRQ,
         },
+#ifdef U300_COH901571_3
         {
                 .name  = "gpio3",
                 .start = IRQ_U300_GPIO_PORT3,
@@ -196,6 +252,7 @@ static struct resource gpio_resources[] = {
                 .end   = IRQ_U300_GPIO_PORT4,
                 .flags = IORESOURCE_IRQ,
         },
+#ifdef CONFIG_MACH_U300_BS335
         {
                 .name  = "gpio5",
                 .start = IRQ_U300_GPIO_PORT5,
@@ -208,6 +265,8 @@ static struct resource gpio_resources[] = {
                 .end   = IRQ_U300_GPIO_PORT6,
                 .flags = IORESOURCE_IRQ,
         },
+#endif /* CONFIG_MACH_U300_BS335 */
+#endif /* U300_COH901571_3 */
 };
 
 static struct resource keypad_resources[] = {
@@ -249,18 +308,6 @@ static struct resource rtc_resources[] = {
  */
 static struct resource fsmc_resources[] = {
         {
-                .name  = "nand_addr",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_cmd",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
                 .name  = "nand_data",
                 .start = U300_NAND_CS0_PHYS_BASE,
                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
@@ -314,6 +361,51 @@ static struct resource wdog_resources[] = {
         }
 };
 
+/* TODO: These should be protected by suitable #ifdef's */
+static struct resource ave_resources[] = {
+        {
+                .name  = "AVE3e I/O Area",
+                .start = U300_VIDEOENC_BASE,
+                .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "AVE3e IRQ0",
+                .start = IRQ_U300_VIDEO_ENC_0,
+                .end   = IRQ_U300_VIDEO_ENC_0,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "AVE3e IRQ1",
+                .start = IRQ_U300_VIDEO_ENC_1,
+                .end   = IRQ_U300_VIDEO_ENC_1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "AVE3e Physmem Area",
+                .start = 0, /* 0 will be remapped to reserved memory */
+                .end   = SZ_1M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        /*
+         * The AVE3e requires two regions of 256MB that it considers
+         * "invisible". The hardware will not be able to access these
+         * addresses, so they should never point to system RAM.
+         */
+        {
+                .name  = "AVE3e Reserved 0",
+                .start = 0xd0000000,
+                .end   = 0xd0000000 + SZ_256M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "AVE3e Reserved 1",
+                .start = 0xe0000000,
+                .end   = 0xe0000000 + SZ_256M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
 static struct resource dma_resource[] = {
         {
                 .start = U300_DMAC_BASE,
@@ -327,6 +419,7 @@ static struct resource dma_resource[] = {
         }
 };
 
+#ifdef CONFIG_MACH_U300_BS335
 /* points out all dma slave channels.
  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
  * Select all channels from A to B, end of list is marked with -1,-1
@@ -339,6 +432,14 @@ static int dma_slave_channels[] = {
 static int dma_memcpy_channels[] = {
         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 
+#else /* CONFIG_MACH_U300_BS335 */
+
+static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
+
+#endif
+
 /** register dma for memory access
  *
  * active  1 means dma intends to access memory
@@ -1390,6 +1491,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .param.ctrl_lli = flags_memcpy_lli,
                 .param.ctrl_lli_last = flags_memcpy_lli_last,
         },
+#ifdef CONFIG_MACH_U300_BS335
         {
                 .number = U300_DMA_UART1_TX,
                 .name = "UART1 TX",
@@ -1400,6 +1502,28 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .name = "UART1 RX",
                 .priority_high = 0,
         }
+#else
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_9,
+                .name = "GENERAL 09",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_10,
+                .name = "GENERAL 10",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        }
+#endif
 };
 
 
@@ -1411,14 +1535,6 @@ static struct coh901318_platform coh901318_platform = {
         .max_channels = U300_DMA_CHANNELS,
 };
 
-static struct resource pinctrl_resources[] = {
-        {
-                .start = U300_SYSCON_BASE,
-                .end   = U300_SYSCON_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
 static struct platform_device wdog_device = {
         .name = "coh901327_wdog",
         .id = -1,
@@ -1440,30 +1556,11 @@ static struct platform_device i2c1_device = {
         .resource = i2c1_resources,
 };
 
-static struct platform_device pinctrl_device = {
-        .name = "pinctrl-u300",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(pinctrl_resources),
-        .resource = pinctrl_resources,
-};
-
-/*
- * The different variants have a few different versions of the
- * GPIO block, with different number of ports.
- */
-static struct u300_gpio_platform u300_gpio_plat = {
-        .ports = 7,
-        .gpio_base = 0,
-};
-
 static struct platform_device gpio_device = {
         .name = "u300-gpio",
         .id = -1,
         .num_resources = ARRAY_SIZE(gpio_resources),
         .resource = gpio_resources,
-        .dev = {
-                .platform_data = &u300_gpio_plat,
-        },
 };
 
 static struct platform_device keypad_device = {
@@ -1515,6 +1612,13 @@ static struct platform_device nand_device = {
         },
 };
 
+static struct platform_device ave_device = {
+        .name = "video_enc",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(ave_resources),
+        .resource = ave_resources,
+};
+
 static struct platform_device dma_device = {
         .name           = "coh901318",
         .id             = -1,
@@ -1526,32 +1630,6 @@ static struct platform_device dma_device = {
         },
 };
 
-static unsigned long pin_pullup_conf[] = {
-        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
-};
-
-static unsigned long pin_highz_conf[] = {
-        PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata u300_pinmux_map[] = {
-        /* anonymous maps for chip power and EMIFs */
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
-        /* per-device maps for MMC/SD, SPI and UART */
-        PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
-        /* This pin is used for clock return rather than GPIO */
-        PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
-                                    pin_pullup_conf),
-        /* This pin is used for card detect */
-        PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
-                                    pin_highz_conf),
-};
-
 /*
  * Notice that AMBA devices are initialized before platform devices.
  *
@@ -1562,45 +1640,36 @@ static struct platform_device *platform_devs[] __initdata = {
         &i2c1_device,
         &keypad_device,
         &rtc_device,
-        &pinctrl_device,
         &gpio_device,
         &nand_device,
         &wdog_device,
+        &ave_device
 };
 
+
 /*
  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
  * together so some interrupts are connected to the first one and some
  * to the second one.
  */
-static void __init u300_init_irq(void)
+void __init u300_init_irq(void)
 {
         u32 mask[2] = {0, 0};
         struct clk *clk;
         int i;
 
         /* initialize clocking early, we want to clock the INTCON */
-        u300_clk_init(U300_SYSCON_VBASE);
-
-        /* Bootstrap EMIF and SEMI clocks */
-        clk = clk_get_sys("pl172", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        clk = clk_get_sys("semi", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
+        u300_clock_init();
 
         /* Clock the interrupt controller */
         clk = clk_get_sys("intcon", NULL);
         BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
+        clk_enable(clk);
 
-        for (i = 0; i < U300_VIC_IRQS_END; i++)
+        for (i = 0; i < NR_IRQS; i++)
                 set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-                 mask[0], mask[0]);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
-                 mask[1], mask[1]);
+        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
+        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
 }
 
 
@@ -1678,11 +1747,29 @@ static void __init u300_init_check_chip(void)
         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
                "(chip ID 0x%04x)\n", chipname, val);
 
+#ifdef CONFIG_MACH_U300_BS330
+        if ((val & 0xFF00U) != 0xd800) {
+                printk(KERN_ERR "Platform configured for BS330 " \
+                       "with DB3200 but %s detected, expect problems!",
+                       chipname);
+        }
+#endif
+#ifdef CONFIG_MACH_U300_BS335
         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
                 printk(KERN_ERR "Platform configured for BS335 " \
                        " with DB3350 but %s detected, expect problems!",
                        chipname);
         }
+#endif
+#ifdef CONFIG_MACH_U300_BS365
+        if ((val & 0xFF00U) != 0xe800) {
+                printk(KERN_ERR "Platform configured for BS365 " \
+                       "with DB3210 but %s detected, expect problems!",
+                       chipname);
+        }
+#endif
+
+
 }
 
 /*
@@ -1715,7 +1802,7 @@ static void __init u300_assign_physmem(void)
         }
 }
 
-static void __init u300_init_machine(void)
+void __init u300_init_devices(void)
 {
         int i;
         u16 val;
@@ -1723,6 +1810,13 @@ static void __init u300_init_machine(void)
         /* Check what platform we run and print some status information */
         u300_init_check_chip();
 
+        /* Set system to run at PLL208, max performance, a known state. */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        /* Wait for the PLL208 to lock if not locked in yet */
+        while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
+                 U300_SYSCON_CSR_PLL208_LOCK_IND));
         /* Initialize SPI device with some board specifics */
         u300_spi_init(&pl022_device);
 
@@ -1734,10 +1828,6 @@ static void __init u300_init_machine(void)
 
         u300_assign_physmem();
 
-        /* Initialize pinmuxing */
-        pinctrl_register_mappings(u300_pinmux_map,
-                                  ARRAY_SIZE(u300_pinmux_map));
-
         /* Register subdevices on the I2C buses */
         u300_i2c_register_board_devices();
 
@@ -1747,40 +1837,25 @@ static void __init u300_init_machine(void)
         /* Register subdevices on the SPI bus */
         u300_spi_register_board_devices();
 
-        /* Enable SEMI self refresh */
+#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
+        /*
+         * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
+         * both subsystems are requesting this mode.
+         * If we not share the Acc SDRAM, this is never the case. Therefore
+         * enable it here from the App side.
+         */
         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
 }
 
-/* Forward declare this function from the watchdog */
-void coh901327_watchdog_reset(void);
-
-static void u300_restart(char mode, const char *cmd)
+static int core_module_init(void)
 {
-        switch (mode) {
-        case 's':
-        case 'h':
-#ifdef CONFIG_COH901327_WATCHDOG
-                coh901327_watchdog_reset();
-#endif
-                break;
-        default:
-                /* Do nothing */
-                break;
-        }
-        /* Wait for system do die/reset. */
-        while (1);
+        /*
+         * This needs to be initialized later: it needs the input framework
+         * to be initialized first.
+         */
+        return mmc_init(&mmcsd_device);
 }
-
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
-        .map_io         = u300_map_io,
-        .nr_irqs        = 0,
-        .init_irq       = u300_init_irq,
-        .handle_irq     = vic_handle_irq,
-        .timer          = &u300_timer,
-        .init_machine   = u300_init_machine,
-        .restart        = u300_restart,
-MACHINE_END
+module_init(core_module_init);
diff --git a/arch/arm/mach-u300/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
deleted file mode 100644
index 4e8a88fbca4..00000000000
--- a/arch/arm/mach-u300/dma_channels.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/dma_channels.h
- *
- *
- * Copyright (C) 2007-2012 ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- * Map file for the U300 dma driver.
- * Author: Per Friden <per.friden@stericsson.com>
- */
-
-#ifndef DMA_CHANNELS_H
-#define DMA_CHANNELS_H
-
-#define U300_DMA_MSL_TX_0             0
-#define U300_DMA_MSL_TX_1             1
-#define U300_DMA_MSL_TX_2             2
-#define U300_DMA_MSL_TX_3             3
-#define U300_DMA_MSL_TX_4             4
-#define U300_DMA_MSL_TX_5             5
-#define U300_DMA_MSL_TX_6             6
-#define U300_DMA_MSL_RX_0             7
-#define U300_DMA_MSL_RX_1             8
-#define U300_DMA_MSL_RX_2             9
-#define U300_DMA_MSL_RX_3             10
-#define U300_DMA_MSL_RX_4             11
-#define U300_DMA_MSL_RX_5             12
-#define U300_DMA_MSL_RX_6             13
-#define U300_DMA_MMCSD_RX_TX          14
-#define U300_DMA_MSPRO_TX             15
-#define U300_DMA_MSPRO_RX             16
-#define U300_DMA_UART0_TX             17
-#define U300_DMA_UART0_RX             18
-#define U300_DMA_APEX_TX              19
-#define U300_DMA_APEX_RX              20
-#define U300_DMA_PCM_I2S0_TX          21
-#define U300_DMA_PCM_I2S0_RX          22
-#define U300_DMA_PCM_I2S1_TX          23
-#define U300_DMA_PCM_I2S1_RX          24
-#define U300_DMA_XGAM_CDI             25
-#define U300_DMA_XGAM_PDI             26
-#define U300_DMA_SPI_TX               27
-#define U300_DMA_SPI_RX               28
-#define U300_DMA_GENERAL_PURPOSE_0    29
-#define U300_DMA_GENERAL_PURPOSE_1    30
-#define U300_DMA_GENERAL_PURPOSE_2    31
-#define U300_DMA_GENERAL_PURPOSE_3    32
-#define U300_DMA_GENERAL_PURPOSE_4    33
-#define U300_DMA_GENERAL_PURPOSE_5    34
-#define U300_DMA_GENERAL_PURPOSE_6    35
-#define U300_DMA_GENERAL_PURPOSE_7    36
-#define U300_DMA_GENERAL_PURPOSE_8    37
-#define U300_DMA_UART1_TX             38
-#define U300_DMA_UART1_RX             39
-
-#define U300_DMA_DEVICE_CHANNELS      32
-#define U300_DMA_CHANNELS             40
-
-
-#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb67b5e..03f79361259 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -222,7 +222,7 @@ static ssize_t dummy_looptest(struct device *dev,
 
 static DEVICE_ATTR(looptest, S_IRUGO, dummy_looptest, NULL);
 
-static int pl022_dummy_probe(struct spi_device *spi)
+static int __devinit pl022_dummy_probe(struct spi_device *spi)
 {
         struct dummy *p_dummy;
         int status;
@@ -251,7 +251,7 @@ out_dev_create_looptest_failed:
         return status;
 }
 
-static int pl022_dummy_remove(struct spi_device *spi)
+static int __devexit pl022_dummy_remove(struct spi_device *spi)
 {
         struct dummy *p_dummy = dev_get_drvdata(&spi->dev);
 
@@ -269,7 +269,7 @@ static struct spi_driver pl022_dummy_driver = {
                 .owner  = THIS_MODULE,
         },
         .probe  = pl022_dummy_probe,
-        .remove = pl022_dummy_remove,
+        .remove = __devexit_p(pl022_dummy_remove),
 };
 
 static int __init pl022_init_dummy(void)
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index 96800aa1316..f0394baa11f 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-u300/i2c.c
  *
- * Copyright (C) 2009-2012 ST-Ericsson AB
+ * Copyright (C) 2009 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  *
  * Register board i2c devices
@@ -9,7 +9,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/i2c.h>
-#include <linux/mfd/ab3100.h>
+#include <linux/mfd/abx500.h>
 #include <linux/regulator/machine.h>
 #include <linux/amba/bus.h>
 #include <mach/irqs.h>
@@ -60,6 +60,7 @@ static struct regulator_consumer_supply supply_ldo_c[] = {
  */
 static struct regulator_consumer_supply supply_ldo_d[] = {
         {
+                .dev = NULL,
                 .supply = "vana15", /* Powers the SoC (CPU etc) */
         },
 };
@@ -91,6 +92,7 @@ static struct regulator_consumer_supply supply_ldo_k[] = {
  */
 static struct regulator_consumer_supply supply_ldo_ext[] = {
         {
+                .dev = NULL,
                 .supply = "vext", /* External power */
         },
 };
@@ -146,6 +148,9 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .min_uV = 1800000,
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -157,6 +162,9 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .min_uV = 2500000,
                                 .max_uV = 2500000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -224,7 +232,8 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                 .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE,
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -247,8 +256,57 @@ static struct ab3100_platform_data ab3100_plf_data = {
 };
 #endif
 
+#ifdef CONFIG_AB3550_CORE
+static struct abx500_init_settings ab3550_init_settings[] = {
+        {
+                .bank = 0,
+                .reg = AB3550_IMR1,
+                .setting = 0xff
+        },
+        {
+                .bank = 0,
+                .reg = AB3550_IMR2,
+                .setting = 0xff
+        },
+        {
+                .bank = 0,
+                .reg = AB3550_IMR3,
+                .setting = 0xff
+        },
+        {
+                .bank = 0,
+                .reg = AB3550_IMR4,
+                .setting = 0xff
+        },
+        {
+                .bank = 0,
+                .reg = AB3550_IMR5,
+                /* The two most significant bits are not used */
+                .setting = 0x3f
+        },
+};
+
+static struct ab3550_platform_data ab3550_plf_data = {
+        .irq = {
+                .base = IRQ_AB3550_BASE,
+                .count = (IRQ_AB3550_END - IRQ_AB3550_BASE + 1),
+        },
+        .dev_data = {
+        },
+        .init_settings = ab3550_init_settings,
+        .init_settings_sz = ARRAY_SIZE(ab3550_init_settings),
+};
+#endif
+
 static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
-#ifdef CONFIG_AB3100_CORE
+#if defined(CONFIG_AB3550_CORE)
+        {
+                .type = "ab3550",
+                .addr = 0x4A,
+                .irq = IRQ_U300_IRQ0_EXT,
+                .platform_data = &ab3550_plf_data,
+        },
+#elif defined(CONFIG_AB3100_CORE)
         {
                 .type = "ab3100",
                 .addr = 0x48,
@@ -261,6 +319,7 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
 };
 
 static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
+#ifdef CONFIG_MACH_U300_BS335
         {
                 .type = "fwcam",
                 .addr = 0x10,
@@ -269,6 +328,9 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
                 .type = "fwcam",
                 .addr = 0x5d,
         },
+#else
+        { },
+#endif
 };
 
 void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
index 8ae8e4ab34b..df715707bea 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
  */
 #include <mach/hardware.h>
 
-        .macro  addruart, rp, rv, tmp
+        .macro  addruart, rp, rv
         /* If we move the address using MMU, use this. */
         ldr     \rp,      = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
         ldr     \rv,      = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index 21d5e76a6cd..09b1b28fa8f 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/irqs.h
  *
  *
- * Copyright (C) 2006-2012 ST-Ericsson AB
+ * Copyright (C) 2006-2009 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * IRQ channel definitions for the U300 platforms.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -12,69 +12,110 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-#define IRQ_U300_INTCON0_START          32
-#define IRQ_U300_INTCON1_START          64
+#define IRQ_U300_INTCON0_START          0
+#define IRQ_U300_INTCON1_START          32
 /* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               32
-#define IRQ_U300_IRQ1_EXT               33
-#define IRQ_U300_DMA                    34
-#define IRQ_U300_VIDEO_ENC_0            35
-#define IRQ_U300_VIDEO_ENC_1            36
-#define IRQ_U300_AAIF_RX                37
-#define IRQ_U300_AAIF_TX                38
-#define IRQ_U300_AAIF_VGPIO             39
-#define IRQ_U300_AAIF_WAKEUP            40
-#define IRQ_U300_PCM_I2S0_FRAME         41
-#define IRQ_U300_PCM_I2S0_FIFO          42
-#define IRQ_U300_PCM_I2S1_FRAME         43
-#define IRQ_U300_PCM_I2S1_FIFO          44
-#define IRQ_U300_XGAM_GAMCON            45
-#define IRQ_U300_XGAM_CDI               46
-#define IRQ_U300_XGAM_CDICON            47
-#define IRQ_U300_XGAM_PDI               49
-#define IRQ_U300_XGAM_PDICON            50
-#define IRQ_U300_XGAM_GAMEACC           51
-#define IRQ_U300_XGAM_MCIDCT            52
-#define IRQ_U300_APEX                   53
-#define IRQ_U300_UART0                  54
-#define IRQ_U300_SPI                    55
-#define IRQ_U300_TIMER_APP_OS           56
-#define IRQ_U300_TIMER_APP_DD           57
-#define IRQ_U300_TIMER_APP_GP1          58
-#define IRQ_U300_TIMER_APP_GP2          59
-#define IRQ_U300_TIMER_OS               60
-#define IRQ_U300_TIMER_MS               61
-#define IRQ_U300_KEYPAD_KEYBF           62
-#define IRQ_U300_KEYPAD_KEYBR           63
+#define IRQ_U300_IRQ0_EXT               0
+#define IRQ_U300_IRQ1_EXT               1
+#define IRQ_U300_DMA                    2
+#define IRQ_U300_VIDEO_ENC_0            3
+#define IRQ_U300_VIDEO_ENC_1            4
+#define IRQ_U300_AAIF_RX                5
+#define IRQ_U300_AAIF_TX                6
+#define IRQ_U300_AAIF_VGPIO             7
+#define IRQ_U300_AAIF_WAKEUP            8
+#define IRQ_U300_PCM_I2S0_FRAME         9
+#define IRQ_U300_PCM_I2S0_FIFO          10
+#define IRQ_U300_PCM_I2S1_FRAME         11
+#define IRQ_U300_PCM_I2S1_FIFO          12
+#define IRQ_U300_XGAM_GAMCON            13
+#define IRQ_U300_XGAM_CDI               14
+#define IRQ_U300_XGAM_CDICON            15
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
+/* MMIACC not used on the DB3210 or DB3350 chips */
+#define IRQ_U300_XGAM_MMIACC            16
+#endif
+#define IRQ_U300_XGAM_PDI               17
+#define IRQ_U300_XGAM_PDICON            18
+#define IRQ_U300_XGAM_GAMEACC           19
+#define IRQ_U300_XGAM_MCIDCT            20
+#define IRQ_U300_APEX                   21
+#define IRQ_U300_UART0                  22
+#define IRQ_U300_SPI                    23
+#define IRQ_U300_TIMER_APP_OS           24
+#define IRQ_U300_TIMER_APP_DD           25
+#define IRQ_U300_TIMER_APP_GP1          26
+#define IRQ_U300_TIMER_APP_GP2          27
+#define IRQ_U300_TIMER_OS               28
+#define IRQ_U300_TIMER_MS               29
+#define IRQ_U300_KEYPAD_KEYBF           30
+#define IRQ_U300_KEYPAD_KEYBR           31
 /* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             64
-#define IRQ_U300_GPIO_PORT1             65
-#define IRQ_U300_GPIO_PORT2             66
+#define IRQ_U300_GPIO_PORT0             32
+#define IRQ_U300_GPIO_PORT1             33
+#define IRQ_U300_GPIO_PORT2             34
 
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
+    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   67
-#define IRQ_U300_EVHIST                 68
-#define IRQ_U300_MSPRO                  69
-#define IRQ_U300_MMCSD_MCIINTR0         70
-#define IRQ_U300_MMCSD_MCIINTR1         71
-#define IRQ_U300_I2C0                   72
-#define IRQ_U300_I2C1                   73
-#define IRQ_U300_RTC                    74
-#define IRQ_U300_NFIF                   75
-#define IRQ_U300_NFIF2                  76
+#define IRQ_U300_WDOG                   35
+#define IRQ_U300_EVHIST                 36
+#define IRQ_U300_MSPRO                  37
+#define IRQ_U300_MMCSD_MCIINTR0         38
+#define IRQ_U300_MMCSD_MCIINTR1         39
+#define IRQ_U300_I2C0                   40
+#define IRQ_U300_I2C1                   41
+#define IRQ_U300_RTC                    42
+#define IRQ_U300_NFIF                   43
+#define IRQ_U300_NFIF2                  44
+#endif
+
+/* DB3150 and DB3200 have only 45 IRQs */
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
+#define U300_NR_IRQS                    45
+#endif
 
 /* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0                 77
-#define IRQ_U300_ISP_F1                 78
-#define IRQ_U300_ISP_F2                 79
-#define IRQ_U300_ISP_F3                 80
-#define IRQ_U300_ISP_F4                 81
-#define IRQ_U300_GPIO_PORT3             82
-#define IRQ_U300_SYSCON_PLL_LOCK        83
-#define IRQ_U300_UART1                  84
-#define IRQ_U300_GPIO_PORT4             85
-#define IRQ_U300_GPIO_PORT5             86
-#define IRQ_U300_GPIO_PORT6             87
-#define U300_VIC_IRQS_END               88
+#ifdef CONFIG_MACH_U300_BS335
+#define IRQ_U300_ISP_F0                 45
+#define IRQ_U300_ISP_F1                 46
+#define IRQ_U300_ISP_F2                 47
+#define IRQ_U300_ISP_F3                 48
+#define IRQ_U300_ISP_F4                 49
+#define IRQ_U300_GPIO_PORT3             50
+#define IRQ_U300_SYSCON_PLL_LOCK        51
+#define IRQ_U300_UART1                  52
+#define IRQ_U300_GPIO_PORT4             53
+#define IRQ_U300_GPIO_PORT5             54
+#define IRQ_U300_GPIO_PORT6             55
+#define U300_NR_IRQS                    56
+#endif
+
+/* The DB3210-specific interrupt lines */
+#ifdef CONFIG_MACH_U300_BS365
+#define IRQ_U300_GPIO_PORT3             35
+#define IRQ_U300_GPIO_PORT4             36
+#define IRQ_U300_WDOG                   37
+#define IRQ_U300_EVHIST                 38
+#define IRQ_U300_MSPRO                  39
+#define IRQ_U300_MMCSD_MCIINTR0         40
+#define IRQ_U300_MMCSD_MCIINTR1         41
+#define IRQ_U300_I2C0                   42
+#define IRQ_U300_I2C1                   43
+#define IRQ_U300_RTC                    44
+#define IRQ_U300_NFIF                   45
+#define IRQ_U300_NFIF2                  46
+#define IRQ_U300_SYSCON_PLL_LOCK        47
+#define U300_NR_IRQS                    48
+#endif
+
+#ifdef CONFIG_AB3550_CORE
+#define IRQ_AB3550_BASE                 (U300_NR_IRQS)
+#define IRQ_AB3550_END                  (IRQ_AB3550_BASE + 37)
+
+#define NR_IRQS                         (IRQ_AB3550_END + 1)
+#else
+#define NR_IRQS U300_NR_IRQS
+#endif
 
 #endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 10bdd0be977..7444f5c7da9 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/syscon.h
  *
  *
- * Copyright (C) 2008-2012 ST-Ericsson AB
+ * Copyright (C) 2008 ST-Ericsson AB
  *
  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
  */
@@ -36,7 +36,9 @@
 #define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
 /* Reset lines for SLOW devices 16bit (R/W) */
 #define U300_SYSCON_RSR                                         (0x0014)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
+#endif
 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
 #define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
 #define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
@@ -48,7 +50,9 @@
 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
 /* Reset lines for FAST devices 16bit (R/W) */
 #define U300_SYSCON_RFR                                         (0x0018)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
+#endif
 #define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
 #define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
@@ -58,8 +62,10 @@
 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
 /* Reset lines for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_RRR                                         (0x001c)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
 #define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
+#endif
 #define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
 #define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
 #define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
@@ -73,7 +79,9 @@
 #define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
 /* Clock enable for SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CESR                                        (0x0020)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
+#endif
 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
 #define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
 #define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
@@ -84,20 +92,24 @@
 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for FAST peripherals 16bit (R/W) */
 #define U300_SYSCON_CEFR                                        (0x0024)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
+#endif
 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
 #define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
 #define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CERR                                        (0x0028)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
 #define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
+#endif
 #define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
 #define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
@@ -112,7 +124,9 @@
 #define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
 /* Single block clock enable 16bit (-/W) */
 #define U300_SYSCON_SBCER                                       (0x002c)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
+#endif
 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
@@ -121,7 +135,9 @@
 #define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
 #define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
+#endif
 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
 #define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
@@ -131,8 +147,10 @@
 #define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
 #define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
 #define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
+#endif
 #define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
 #define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
@@ -150,7 +168,9 @@
 /* Same values as above for SBCER */
 /* Clock force SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CFSR                                        (0x003c)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
+#endif
 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
@@ -164,8 +184,10 @@
 /* Values not defined. Define if you want to use them. */
 /* Clock force the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CFRR                                        (0x44)
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
+#endif
 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
@@ -212,6 +234,91 @@
 #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
 #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
 #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
+/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
+#define U300_SYSCON_PMC1LR                                      (0x007C)
+#define U300_SYSCON_PMC1LR_MASK                                 (0xFFFF)
+#define U300_SYSCON_PMC1LR_CDI_MASK                             (0xC000)
+#define U300_SYSCON_PMC1LR_CDI_CDI                              (0x0000)
+#define U300_SYSCON_PMC1LR_CDI_EMIF                             (0x4000)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_PMC1LR_CDI_CDI2                             (0x8000)
+#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO                   (0xC000)
+#elif CONFIG_MACH_U300_BS365
+#define U300_SYSCON_PMC1LR_CDI_GPIO                             (0x8000)
+#define U300_SYSCON_PMC1LR_CDI_WCDMA                            (0xC000)
+#endif
+#define U300_SYSCON_PMC1LR_PDI_MASK                             (0x3000)
+#define U300_SYSCON_PMC1LR_PDI_PDI                              (0x0000)
+#define U300_SYSCON_PMC1LR_PDI_EGG                              (0x1000)
+#define U300_SYSCON_PMC1LR_PDI_WCDMA                            (0x3000)
+#define U300_SYSCON_PMC1LR_MMCSD_MASK                           (0x0C00)
+#define U300_SYSCON_PMC1LR_MMCSD_MMCSD                          (0x0000)
+#define U300_SYSCON_PMC1LR_MMCSD_MSPRO                          (0x0400)
+#define U300_SYSCON_PMC1LR_MMCSD_DSP                            (0x0800)
+#define U300_SYSCON_PMC1LR_MMCSD_WCDMA                          (0x0C00)
+#define U300_SYSCON_PMC1LR_ETM_MASK                             (0x0300)
+#define U300_SYSCON_PMC1LR_ETM_ACC                              (0x0000)
+#define U300_SYSCON_PMC1LR_ETM_APP                              (0x0100)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK                      (0x00C0)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC                    (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF                      (0x0040)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM                     (0x0080)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB                (0x00C0)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK                      (0x0030)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC                    (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF                      (0x0010)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM                     (0x0020)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI                      (0x0030)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK                      (0x000C)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC                    (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF                      (0x0004)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM                     (0x0008)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI                      (0x000C)
+#define U300_SYSCON_PMC1LR_EMIF_1_MASK                          (0x0003)
+#define U300_SYSCON_PMC1LR_EMIF_1_STATIC                        (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0                        (0x0001)
+#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1                        (0x0002)
+#define U300_SYSCON_PMC1LR_EMIF_1                               (0x0003)
+/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
+#define U300_SYSCON_PMC1HR                                      (0x007E)
+#define U300_SYSCON_PMC1HR_MASK                                 (0xFFFF)
+#define U300_SYSCON_PMC1HR_MISC_2_MASK                          (0xC000)
+#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO                      (0x0000)
+#define U300_SYSCON_PMC1HR_MISC_2_MSPRO                         (0x4000)
+#define U300_SYSCON_PMC1HR_MISC_2_DSP                           (0x8000)
+#define U300_SYSCON_PMC1HR_MISC_2_AAIF                          (0xC000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK                      (0x3000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO                  (0x0000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF                      (0x1000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP                       (0x2000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF                      (0x3000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK                      (0x0C00)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO                  (0x0000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC                       (0x0400)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP                       (0x0800)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF                      (0x0C00)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK                    (0x0300)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO                (0x0000)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI                     (0x0100)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF                    (0x0300)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK                    (0x00C0)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO                (0x0000)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI                     (0x0040)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF                    (0x00C0)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK                       (0x0030)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI                        (0x0010)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP                        (0x0020)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF                       (0x0030)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK                     (0x000C)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO                 (0x0000)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0                    (0x0004)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS                  (0x0008)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF                     (0x000C)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK                     (0x0003)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO                 (0x0000)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0                    (0x0001)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF                     (0x0003)
 /* Step one for killing the applications system 16bit (-/W) */
 #define U300_SYSCON_KA1R                                        (0x0080)
 #define U300_SYSCON_KA1R_MASK                                   (0xFFFF)
@@ -250,6 +357,57 @@
 #define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE                 (0x0080)
 #define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE                  (0x0040)
 #define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK                      (0x003F)
+/* Padmux 2 control */
+#define U300_SYSCON_PMC2R                                       (0x100)
+#define U300_SYSCON_PMC2R_APP_MISC_0_MASK                       (0x00C0)
+#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM                 (0x0040)
+#define U300_SYSCON_PMC2R_APP_MISC_0_MMC                        (0x0080)
+#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2                       (0x00C0)
+#define U300_SYSCON_PMC2R_APP_MISC_1_MASK                       (0x0300)
+#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM                 (0x0100)
+#define U300_SYSCON_PMC2R_APP_MISC_1_MMC                        (0x0200)
+#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2                       (0x0300)
+#define U300_SYSCON_PMC2R_APP_MISC_2_MASK                       (0x0C00)
+#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM                 (0x0400)
+#define U300_SYSCON_PMC2R_APP_MISC_2_MMC                        (0x0800)
+#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2                       (0x0C00)
+#define U300_SYSCON_PMC2R_APP_MISC_3_MASK                       (0x3000)
+#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM                 (0x1000)
+#define U300_SYSCON_PMC2R_APP_MISC_3_MMC                        (0x2000)
+#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2                       (0x3000)
+#define U300_SYSCON_PMC2R_APP_MISC_4_MASK                       (0xC000)
+#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM                 (0x4000)
+#define U300_SYSCON_PMC2R_APP_MISC_4_MMC                        (0x8000)
+#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO                   (0xC000)
+/* TODO: More SYSCON registers missing */
+#define U300_SYSCON_PMC3R                                       (0x10c)
+#define U300_SYSCON_PMC3R_APP_MISC_11_MASK                      (0xc000)
+#define U300_SYSCON_PMC3R_APP_MISC_11_SPI                       (0x4000)
+#define U300_SYSCON_PMC3R_APP_MISC_10_MASK                      (0x3000)
+#define U300_SYSCON_PMC3R_APP_MISC_10_SPI                       (0x1000)
+/* TODO: Missing other configs */
+#define U300_SYSCON_PMC4R                                       (0x168)
+#define U300_SYSCON_PMC4R_APP_MISC_12_MASK                      (0x0003)
+#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO                  (0x0000)
+#define U300_SYSCON_PMC4R_APP_MISC_13_MASK                      (0x000C)
+#define U300_SYSCON_PMC4R_APP_MISC_13_CDI                       (0x0000)
+#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA                      (0x0004)
+#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2                     (0x0008)
+#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO                  (0x000C)
+#define U300_SYSCON_PMC4R_APP_MISC_14_MASK                      (0x0030)
+#define U300_SYSCON_PMC4R_APP_MISC_14_CDI                       (0x0000)
+#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA                      (0x0010)
+#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2                      (0x0020)
+#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO                  (0x0030)
+#define U300_SYSCON_PMC4R_APP_MISC_16_MASK                      (0x0300)
+#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13               (0x0000)
+#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS             (0x0100)
+#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N       (0x0200)
 /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
 #define U300_SYSCON_S0CCR                                       (0x120)
 #define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 1e49d901f2c..035fdc9dbdb 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -18,16 +18,18 @@
  * the defines are used for setting up the I/O memory mapping.
  */
 
+#ifdef __ASSEMBLER__
+#define IOMEM(a) (a)
+#else
+#define IOMEM(a) (void __iomem *) a
+#endif
+
 /* NAND Flash CS0 */
 #define U300_NAND_CS0_PHYS_BASE         0x80000000
 
 /* NFIF */
 #define U300_NAND_IF_PHYS_BASE          0x9f800000
 
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE                   (1 << 16)
-#define PLAT_NAND_ALE                   (1 << 17)
-
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE          0xa0000000
 #define U300_AHB_PER_VIRT_BASE          0xff010000
@@ -45,7 +47,11 @@
 #define U300_BOOTROM_VIRT_BASE          0xffff0000
 
 /* SEMI config base */
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_SEMI_CONFIG_BASE           0x2FFE0000
+#else
+#define U300_SEMI_CONFIG_BASE           0x30000000
+#endif
 
 /*
  * AHB peripherals
@@ -94,8 +100,10 @@
 /* SPI controller */
 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
 
+#ifdef CONFIG_MACH_U300_BS335
 /* Fast UART1 on U335 only */
 #define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
+#endif
 
 /*
  * SLOW peripherals
@@ -144,8 +152,10 @@
  * REST peripherals
  */
 
-/* ISP (image signal processor) */
+/* ISP (image signal processor) is only available in U335 */
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_ISP_BASE                   (0xA0008000)
+#endif
 
 /* DMA Controller base */
 #define U300_DMAC_BASE                  (0xC0020000)
@@ -157,9 +167,17 @@
 #define U300_APEX_BASE                  (0xc0030000)
 
 /* Video Encoder Base */
+#ifdef CONFIG_MACH_U300_BS335
 #define U300_VIDEOENC_BASE              (0xc0080000)
+#else
+#define U300_VIDEOENC_BASE              (0xc0040000)
+#endif
 
 /* XGAM Base */
 #define U300_XGAM_BASE                  (0xd0000000)
 
+/*
+ * Virtual accessor macros for static devices
+ */
+
 #endif
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 02e6659286d..7b597e2b19e 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,9 @@
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
 #include <mach/coh901318.h>
-#include "dma_channels.h"
+#include <mach/dma_channels.h>
+
+#include "padmux.h"
 
 /*
  * The following is for the actual devices on the SSP/SPI bus
@@ -93,7 +95,25 @@ static struct pl022_ssp_controller ssp_platform_data = {
 
 void __init u300_spi_init(struct amba_device *adev)
 {
+        struct pmx *pmx;
+
         adev->dev.platform_data = &ssp_platform_data;
+        /*
+         * Setup padmuxing for SPI. Since this must always be
+         * compiled into the kernel, pmx is never released.
+         */
+        pmx = pmx_get(&adev->dev, U300_APP_PMX_SPI_SETTING);
+
+        if (IS_ERR(pmx))
+                dev_warn(&adev->dev, "Could not get padmux handle\n");
+        else {
+                int ret;
+
+                ret = pmx_activate(&adev->dev, pmx);
+                if (IS_ERR_VALUE(ret))
+                        dev_warn(&adev->dev, "Could not activate padmuxing\n");
+        }
+
 }
 
 void __init u300_spi_register_board_devices(void)
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 1da10e20e99..5f51bdeef0e 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -9,6 +9,7 @@
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
 #include <linux/interrupt.h>
+#include <linux/sched.h>
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/clockchips.h>
@@ -17,17 +18,14 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <linux/irq.h>
 
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-
-#include "timer.h"
+#include <asm/mach/irq.h>
 
 /*
  * APP side special timer registers
@@ -339,10 +337,18 @@ static struct irqaction u300_timer_irq = {
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by OMAP implementation.)
  */
+static DEFINE_CLOCK_DATA(cd);
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
 
-static u32 notrace u300_read_sched_clock(void)
+static void notrace u300_update_sched_clock(void)
 {
-        return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 
@@ -357,10 +363,10 @@ static void __init u300_timer_init(void)
         /* Clock the interrupt controller */
         clk = clk_get_sys("apptimer", NULL);
         BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
+        clk_enable(clk);
         rate = clk_get_rate(clk);
 
-        setup_sched_clock(u300_read_sched_clock, 32, rate);
+        init_sched_clock(&cd, u300_update_sched_clock, 32, rate);
 
         /*
          * Disable the "OS" and "DD" timers - these are designed for Symbian!
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index b5e9791762e..00000000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1 +0,0 @@
-extern struct sys_timer u300_timer;
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f50772e16..00000000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Individual pin assignments for the B335/S335.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_UART_CTS          2
-#define U300_GPIO_PIN_UART_RTS          3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
-
-#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */