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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-s3c2412/mach-jive.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-s3c2412/mach-jive.c')
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c664
1 files changed, 664 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
new file mode 100644
index 00000000000..5eeb47580b0
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -0,0 +1,664 @@
1/* linux/arch/arm/mach-s3c2410/mach-jive.c
2 *
3 * Copyright 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/syscore_ops.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/i2c.h>
24
25#include <video/ili9320.h>
26
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_gpio.h>
29
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
34#include <plat/regs-serial.h>
35#include <plat/nand.h>
36#include <plat/iic.h>
37
38#include <mach/regs-power.h>
39#include <mach/regs-gpio.h>
40#include <mach/regs-mem.h>
41#include <mach/regs-lcd.h>
42#include <mach/fb.h>
43
44#include <asm/mach-types.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h>
50
51#include <plat/gpio-cfg.h>
52#include <plat/clock.h>
53#include <plat/devs.h>
54#include <plat/cpu.h>
55#include <plat/pm.h>
56#include <plat/udc.h>
57
58static struct map_desc jive_iodesc[] __initdata = {
59};
60
61#define UCON S3C2410_UCON_DEFAULT
62#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
63#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
64
65static struct s3c2410_uartcfg jive_uartcfgs[] = {
66 [0] = {
67 .hwport = 0,
68 .flags = 0,
69 .ucon = UCON,
70 .ulcon = ULCON,
71 .ufcon = UFCON,
72 },
73 [1] = {
74 .hwport = 1,
75 .flags = 0,
76 .ucon = UCON,
77 .ulcon = ULCON,
78 .ufcon = UFCON,
79 },
80 [2] = {
81 .hwport = 2,
82 .flags = 0,
83 .ucon = UCON,
84 .ulcon = ULCON,
85 .ufcon = UFCON,
86 }
87};
88
89/* Jive flash assignment
90 *
91 * 0x00000000-0x00028000 : uboot
92 * 0x00028000-0x0002c000 : uboot env
93 * 0x0002c000-0x00030000 : spare
94 * 0x00030000-0x00200000 : zimage A
95 * 0x00200000-0x01600000 : cramfs A
96 * 0x01600000-0x017d0000 : zimage B
97 * 0x017d0000-0x02bd0000 : cramfs B
98 * 0x02bd0000-0x03fd0000 : yaffs
99 */
100static struct mtd_partition __initdata jive_imageA_nand_part[] = {
101
102#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
103 /* Don't allow access to the bootloader from linux */
104 {
105 .name = "uboot",
106 .offset = 0,
107 .size = (160 * SZ_1K),
108 .mask_flags = MTD_WRITEABLE, /* force read-only */
109 },
110
111 /* spare */
112 {
113 .name = "spare",
114 .offset = (176 * SZ_1K),
115 .size = (16 * SZ_1K),
116 },
117#endif
118
119 /* booted images */
120 {
121 .name = "kernel (ro)",
122 .offset = (192 * SZ_1K),
123 .size = (SZ_2M) - (192 * SZ_1K),
124 .mask_flags = MTD_WRITEABLE, /* force read-only */
125 }, {
126 .name = "root (ro)",
127 .offset = (SZ_2M),
128 .size = (20 * SZ_1M),
129 .mask_flags = MTD_WRITEABLE, /* force read-only */
130 },
131
132 /* yaffs */
133 {
134 .name = "yaffs",
135 .offset = (44 * SZ_1M),
136 .size = (20 * SZ_1M),
137 },
138
139 /* bootloader environment */
140 {
141 .name = "env",
142 .offset = (160 * SZ_1K),
143 .size = (16 * SZ_1K),
144 },
145
146 /* upgrade images */
147 {
148 .name = "zimage",
149 .offset = (22 * SZ_1M),
150 .size = (2 * SZ_1M) - (192 * SZ_1K),
151 }, {
152 .name = "cramfs",
153 .offset = (24 * SZ_1M) - (192*SZ_1K),
154 .size = (20 * SZ_1M),
155 },
156};
157
158static struct mtd_partition __initdata jive_imageB_nand_part[] = {
159
160#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
161 /* Don't allow access to the bootloader from linux */
162 {
163 .name = "uboot",
164 .offset = 0,
165 .size = (160 * SZ_1K),
166 .mask_flags = MTD_WRITEABLE, /* force read-only */
167 },
168
169 /* spare */
170 {
171 .name = "spare",
172 .offset = (176 * SZ_1K),
173 .size = (16 * SZ_1K),
174 },
175#endif
176
177 /* booted images */
178 {
179 .name = "kernel (ro)",
180 .offset = (22 * SZ_1M),
181 .size = (2 * SZ_1M) - (192 * SZ_1K),
182 .mask_flags = MTD_WRITEABLE, /* force read-only */
183 },
184 {
185 .name = "root (ro)",
186 .offset = (24 * SZ_1M) - (192 * SZ_1K),
187 .size = (20 * SZ_1M),
188 .mask_flags = MTD_WRITEABLE, /* force read-only */
189 },
190
191 /* yaffs */
192 {
193 .name = "yaffs",
194 .offset = (44 * SZ_1M),
195 .size = (20 * SZ_1M),
196 },
197
198 /* bootloader environment */
199 {
200 .name = "env",
201 .offset = (160 * SZ_1K),
202 .size = (16 * SZ_1K),
203 },
204
205 /* upgrade images */
206 {
207 .name = "zimage",
208 .offset = (192 * SZ_1K),
209 .size = (2 * SZ_1M) - (192 * SZ_1K),
210 }, {
211 .name = "cramfs",
212 .offset = (2 * SZ_1M),
213 .size = (20 * SZ_1M),
214 },
215};
216
217static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
218 [0] = {
219 .name = "flash",
220 .nr_chips = 1,
221 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
222 .partitions = jive_imageA_nand_part,
223 },
224};
225
226static struct s3c2410_platform_nand __initdata jive_nand_info = {
227 /* set taken from osiris nand timings, possibly still conservative */
228 .tacls = 30,
229 .twrph0 = 55,
230 .twrph1 = 40,
231 .sets = jive_nand_sets,
232 .nr_sets = ARRAY_SIZE(jive_nand_sets),
233};
234
235static int __init jive_mtdset(char *options)
236{
237 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
238 unsigned long set;
239
240 if (options == NULL || options[0] == '\0')
241 return 0;
242
243 if (strict_strtoul(options, 10, &set)) {
244 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
245 return 0;
246 }
247
248 switch (set) {
249 case 1:
250 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
251 nand->partitions = jive_imageB_nand_part;
252 case 0:
253 /* this is already setup in the nand info */
254 break;
255 default:
256 printk(KERN_ERR "Unknown mtd set %ld specified,"
257 "using default.", set);
258 }
259
260 return 0;
261}
262
263/* parse the mtdset= option given to the kernel command line */
264__setup("mtdset=", jive_mtdset);
265
266/* LCD timing and setup */
267
268#define LCD_XRES (240)
269#define LCD_YRES (320)
270#define LCD_LEFT_MARGIN (12)
271#define LCD_RIGHT_MARGIN (12)
272#define LCD_LOWER_MARGIN (12)
273#define LCD_UPPER_MARGIN (12)
274#define LCD_VSYNC (2)
275#define LCD_HSYNC (2)
276
277#define LCD_REFRESH (60)
278
279#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
280#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
281
282static struct s3c2410fb_display jive_vgg2432a4_display[] = {
283 [0] = {
284 .width = LCD_XRES,
285 .height = LCD_YRES,
286 .xres = LCD_XRES,
287 .yres = LCD_YRES,
288 .left_margin = LCD_LEFT_MARGIN,
289 .right_margin = LCD_RIGHT_MARGIN,
290 .upper_margin = LCD_UPPER_MARGIN,
291 .lower_margin = LCD_LOWER_MARGIN,
292 .hsync_len = LCD_HSYNC,
293 .vsync_len = LCD_VSYNC,
294
295 .pixclock = (1000000000000LL /
296 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
297
298 .bpp = 16,
299 .type = (S3C2410_LCDCON1_TFT16BPP |
300 S3C2410_LCDCON1_TFT),
301
302 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
303 S3C2410_LCDCON5_INVVLINE |
304 S3C2410_LCDCON5_INVVFRAME |
305 S3C2410_LCDCON5_INVVDEN |
306 S3C2410_LCDCON5_PWREN),
307 },
308};
309
310/* todo - put into gpio header */
311
312#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
313#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
314
315static struct s3c2410fb_mach_info jive_lcd_config = {
316 .displays = jive_vgg2432a4_display,
317 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
318 .default_display = 0,
319
320 /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
321 * and disable the pull down resistors on pins we are using for LCD
322 * data. */
323
324 .gpcup = (0xf << 1) | (0x3f << 10),
325
326 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
327 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
328 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
329 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
330 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
331
332 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
333 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
334 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
335 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
336 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
337
338 .gpdup = (0x3f << 2) | (0x3f << 10),
339
340 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
341 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
342 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
343 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
344 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
345 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
346
347 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
348 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
349 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
350 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
351 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
352 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
353};
354
355/* ILI9320 support. */
356
357static void jive_lcm_reset(unsigned int set)
358{
359 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
360
361 gpio_set_value(S3C2410_GPG(13), set);
362}
363
364#undef LCD_UPPER_MARGIN
365#define LCD_UPPER_MARGIN 2
366
367static struct ili9320_platdata jive_lcm_config = {
368 .hsize = LCD_XRES,
369 .vsize = LCD_YRES,
370
371 .reset = jive_lcm_reset,
372 .suspend = ILI9320_SUSPEND_DEEP,
373
374 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
375 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
376 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
377 .display3 = 0x0,
378 .display4 = 0x0,
379 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
380 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
381 .rgb_if2 = ILI9320_RGBIF2_DPL,
382 .interface2 = 0x0,
383 .interface3 = 0x3,
384 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
385 ILI9320_INTERFACE4_DIVE(1)),
386 .interface5 = 0x0,
387 .interface6 = 0x0,
388};
389
390/* LCD SPI support */
391
392static struct spi_gpio_platform_data jive_lcd_spi = {
393 .sck = S3C2410_GPG(8),
394 .mosi = S3C2410_GPB(8),
395 .miso = SPI_GPIO_NO_MISO,
396};
397
398static struct platform_device jive_device_lcdspi = {
399 .name = "spi-gpio",
400 .id = 1,
401 .dev.platform_data = &jive_lcd_spi,
402};
403
404
405/* WM8750 audio code SPI definition */
406
407static struct spi_gpio_platform_data jive_wm8750_spi = {
408 .sck = S3C2410_GPB(4),
409 .mosi = S3C2410_GPB(9),
410 .miso = SPI_GPIO_NO_MISO,
411};
412
413static struct platform_device jive_device_wm8750 = {
414 .name = "spi-gpio",
415 .id = 2,
416 .dev.platform_data = &jive_wm8750_spi,
417};
418
419/* JIVE SPI devices. */
420
421static struct spi_board_info __initdata jive_spi_devs[] = {
422 [0] = {
423 .modalias = "VGG2432A4",
424 .bus_num = 1,
425 .chip_select = 0,
426 .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
427 .max_speed_hz = 100000,
428 .platform_data = &jive_lcm_config,
429 .controller_data = (void *)S3C2410_GPB(7),
430 }, {
431 .modalias = "WM8750",
432 .bus_num = 2,
433 .chip_select = 0,
434 .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
435 .max_speed_hz = 100000,
436 .controller_data = (void *)S3C2410_GPH(10),
437 },
438};
439
440/* I2C bus and device configuration. */
441
442static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
443 .frequency = 80 * 1000,
444 .flags = S3C_IICFLG_FILTER,
445 .sda_delay = 2,
446};
447
448static struct i2c_board_info jive_i2c_devs[] __initdata = {
449 [0] = {
450 I2C_BOARD_INFO("lis302dl", 0x1c),
451 .irq = IRQ_EINT14,
452 },
453};
454
455/* The platform devices being used. */
456
457static struct platform_device *jive_devices[] __initdata = {
458 &s3c_device_ohci,
459 &s3c_device_rtc,
460 &s3c_device_wdt,
461 &s3c_device_i2c0,
462 &s3c_device_lcd,
463 &jive_device_lcdspi,
464 &jive_device_wm8750,
465 &s3c_device_nand,
466 &s3c_device_usbgadget,
467};
468
469static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
470 .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
471};
472
473/* Jive power management device */
474
475#ifdef CONFIG_PM
476static int jive_pm_suspend(void)
477{
478 /* Write the magic value u-boot uses to check for resume into
479 * the INFORM0 register, and ensure INFORM1 is set to the
480 * correct address to resume from. */
481
482 __raw_writel(0x2BED, S3C2412_INFORM0);
483 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
484
485 return 0;
486}
487
488static void jive_pm_resume(void)
489{
490 __raw_writel(0x0, S3C2412_INFORM0);
491}
492
493#else
494#define jive_pm_suspend NULL
495#define jive_pm_resume NULL
496#endif
497
498static struct syscore_ops jive_pm_syscore_ops = {
499 .suspend = jive_pm_suspend,
500 .resume = jive_pm_resume,
501};
502
503static void __init jive_map_io(void)
504{
505 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
506 s3c24xx_init_clocks(12000000);
507 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
508}
509
510static void jive_power_off(void)
511{
512 printk(KERN_INFO "powering system down...\n");
513
514 s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
515 s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
516}
517
518static void __init jive_machine_init(void)
519{
520 /* register system core operations for managing low level suspend */
521
522 register_syscore_ops(&jive_pm_syscore_ops);
523
524 /* write our sleep configurations for the IO. Pull down all unused
525 * IO, ensure that we have turned off all peripherals we do not
526 * need, and configure the ones we do need. */
527
528 /* Port B sleep */
529
530 __raw_writel(S3C2412_SLPCON_IN(0) |
531 S3C2412_SLPCON_PULL(1) |
532 S3C2412_SLPCON_HIGH(2) |
533 S3C2412_SLPCON_PULL(3) |
534 S3C2412_SLPCON_PULL(4) |
535 S3C2412_SLPCON_PULL(5) |
536 S3C2412_SLPCON_PULL(6) |
537 S3C2412_SLPCON_HIGH(7) |
538 S3C2412_SLPCON_PULL(8) |
539 S3C2412_SLPCON_PULL(9) |
540 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
541
542 /* Port C sleep */
543
544 __raw_writel(S3C2412_SLPCON_PULL(0) |
545 S3C2412_SLPCON_PULL(1) |
546 S3C2412_SLPCON_PULL(2) |
547 S3C2412_SLPCON_PULL(3) |
548 S3C2412_SLPCON_PULL(4) |
549 S3C2412_SLPCON_PULL(5) |
550 S3C2412_SLPCON_LOW(6) |
551 S3C2412_SLPCON_PULL(6) |
552 S3C2412_SLPCON_PULL(7) |
553 S3C2412_SLPCON_PULL(8) |
554 S3C2412_SLPCON_PULL(9) |
555 S3C2412_SLPCON_PULL(10) |
556 S3C2412_SLPCON_PULL(11) |
557 S3C2412_SLPCON_PULL(12) |
558 S3C2412_SLPCON_PULL(13) |
559 S3C2412_SLPCON_PULL(14) |
560 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
561
562 /* Port D sleep */
563
564 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
565
566 /* Port F sleep */
567
568 __raw_writel(S3C2412_SLPCON_LOW(0) |
569 S3C2412_SLPCON_LOW(1) |
570 S3C2412_SLPCON_LOW(2) |
571 S3C2412_SLPCON_EINT(3) |
572 S3C2412_SLPCON_EINT(4) |
573 S3C2412_SLPCON_EINT(5) |
574 S3C2412_SLPCON_EINT(6) |
575 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
576
577 /* Port G sleep */
578
579 __raw_writel(S3C2412_SLPCON_IN(0) |
580 S3C2412_SLPCON_IN(1) |
581 S3C2412_SLPCON_IN(2) |
582 S3C2412_SLPCON_IN(3) |
583 S3C2412_SLPCON_IN(4) |
584 S3C2412_SLPCON_IN(5) |
585 S3C2412_SLPCON_IN(6) |
586 S3C2412_SLPCON_IN(7) |
587 S3C2412_SLPCON_PULL(8) |
588 S3C2412_SLPCON_PULL(9) |
589 S3C2412_SLPCON_IN(10) |
590 S3C2412_SLPCON_PULL(11) |
591 S3C2412_SLPCON_PULL(12) |
592 S3C2412_SLPCON_PULL(13) |
593 S3C2412_SLPCON_IN(14) |
594 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
595
596 /* Port H sleep */
597
598 __raw_writel(S3C2412_SLPCON_PULL(0) |
599 S3C2412_SLPCON_PULL(1) |
600 S3C2412_SLPCON_PULL(2) |
601 S3C2412_SLPCON_PULL(3) |
602 S3C2412_SLPCON_PULL(4) |
603 S3C2412_SLPCON_PULL(5) |
604 S3C2412_SLPCON_PULL(6) |
605 S3C2412_SLPCON_IN(7) |
606 S3C2412_SLPCON_IN(8) |
607 S3C2412_SLPCON_PULL(9) |
608 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
609
610 /* initialise the power management now we've setup everything. */
611
612 s3c_pm_init();
613
614 /** TODO - check that this is after the cmdline option! */
615 s3c_nand_set_platdata(&jive_nand_info);
616
617 /* initialise the spi */
618
619 gpio_request(S3C2410_GPG(13), "lcm reset");
620 gpio_direction_output(S3C2410_GPG(13), 0);
621
622 gpio_request(S3C2410_GPB(7), "jive spi");
623 gpio_direction_output(S3C2410_GPB(7), 1);
624
625 s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
626 s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
627
628 s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
629 s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
630
631 /* initialise the WM8750 spi */
632
633 gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
634 gpio_direction_output(S3C2410_GPH(10), 1);
635
636 /* Turn off suspend on both USB ports, and switch the
637 * selectable USB port to USB device mode. */
638
639 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
640 S3C2410_MISCCR_USBSUSPND0 |
641 S3C2410_MISCCR_USBSUSPND1, 0x0);
642
643 s3c24xx_udc_set_platdata(&jive_udc_cfg);
644 s3c24xx_fb_set_platdata(&jive_lcd_config);
645
646 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
647
648 s3c_i2c0_set_platdata(&jive_i2c_cfg);
649 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
650
651 pm_power_off = jive_power_off;
652
653 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
654}
655
656MACHINE_START(JIVE, "JIVE")
657 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
658 .boot_params = S3C2410_SDRAM_PA + 0x100,
659
660 .init_irq = s3c24xx_init_irq,
661 .map_io = jive_map_io,
662 .init_machine = jive_machine_init,
663 .timer = &s3c24xx_timer,
664MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-09 07:34:04 -0400