Added missing tegra files.HEADmaster

9 files changed, 2597 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
new file mode 100644
index 00000000000..140711db6c8
--- /dev/null
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -0,0 +1,756 @@
+/* linux/arch/arm/mach-s3c2412/clock.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412,S3C2413 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/s3c2412.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* We currently have to assume that the system is running
+ * from the XTPll input, and that all ***REFCLKs are being
+ * fed from it, as we cannot read the state of OM[4] from
+ * software.
+ *
+ * It would be possible for each board initialisation to
+ * set the correct muxing at initialisation
+*/
+
+static int s3c2412_clkcon_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->ctrlbit;
+        unsigned long clkcon;
+
+        clkcon = __raw_readl(S3C2410_CLKCON);
+
+        if (enable)
+                clkcon |= clocks;
+        else
+                clkcon &= ~clocks;
+
+        __raw_writel(clkcon, S3C2410_CLKCON);
+
+        return 0;
+}
+
+static int s3c2412_upll_enable(struct clk *clk, int enable)
+{
+        unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
+        unsigned long orig = upllcon;
+
+        if (!enable)
+                upllcon |= S3C2412_PLLCON_OFF;
+        else
+                upllcon &= ~S3C2412_PLLCON_OFF;
+
+        __raw_writel(upllcon, S3C2410_UPLLCON);
+
+        /* allow ~150uS for the PLL to settle and lock */
+
+        if (enable && (orig & S3C2412_PLLCON_OFF))
+                udelay(150);
+
+        return 0;
+}
+
+/* clock selections */
+
+static struct clk clk_erefclk = {
+        .name           = "erefclk",
+};
+
+static struct clk clk_urefclk = {
+        .name           = "urefclk",
+};
+
+static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_urefclk)
+                clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
+        else if (parent == &clk_upll)
+                clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static struct clk clk_usysclk = {
+        .name           = "usysclk",
+        .parent         = &clk_xtal,
+        .ops            = &(struct clk_ops) {
+                .set_parent     = s3c2412_setparent_usysclk,
+        },
+};
+
+static struct clk clk_mrefclk = {
+        .name           = "mrefclk",
+        .parent         = &clk_xtal,
+};
+
+static struct clk clk_mdivclk = {
+        .name           = "mdivclk",
+        .parent         = &clk_xtal,
+};
+
+static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_usysclk)
+                clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
+        else if (parent == &clk_h)
+                clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+
+        if (rate > parent_rate)
+                return parent_rate;
+
+        div = parent_rate / rate;
+        if (div > 2)
+                div = 2;
+
+        return parent_rate / div;
+}
+
+static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
+}
+
+static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_usbsrc(clk, rate);
+
+        if ((parent_rate / rate) == 2)
+                clkdivn |= S3C2412_CLKDIVN_USB48DIV;
+        else
+                clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_usbsrc = {
+        .name           = "usbsrc",
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2412_getrate_usbsrc,
+                .set_rate       = s3c2412_setrate_usbsrc,
+                .round_rate     = s3c2412_roundrate_usbsrc,
+                .set_parent     = s3c2412_setparent_usbsrc,
+        },
+};
+
+static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_mdivclk)
+                clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
+        else if (parent == &clk_mpll)
+                clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static struct clk clk_msysclk = {
+        .name           = "msysclk",
+        .ops            = &(struct clk_ops) {
+                .set_parent     = s3c2412_setparent_msysclk,
+        },
+};
+
+static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long flags;
+        unsigned long clkdiv;
+        unsigned long dvs;
+
+        /* Note, we current equate fclk andf msysclk for S3C2412 */
+
+        if (parent == &clk_msysclk || parent == &clk_f)
+                dvs = 0;
+        else if (parent == &clk_h)
+                dvs = S3C2412_CLKDIVN_DVSEN;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        /* update this under irq lockdown, clkdivn is not protected
+         * by the clock system. */
+
+        local_irq_save(flags);
+
+        clkdiv  = __raw_readl(S3C2410_CLKDIVN);
+        clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
+        clkdiv |= dvs;
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static struct clk clk_armclk = {
+        .name           = "armclk",
+        .parent         = &clk_msysclk,
+        .ops            = &(struct clk_ops) {
+                .set_parent     = s3c2412_setparent_armclk,
+        },
+};
+
+/* these next clocks have an divider immediately after them,
+ * so we can register them with their divider and leave out the
+ * intermediate clock stage
+*/
+static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+
+        if (rate > parent_rate)
+                return parent_rate;
+
+        /* note, we remove the +/- 1 calculations as they cancel out */
+
+        div = (rate / parent_rate);
+
+        if (div < 1)
+                div = 1;
+        else if (div > 16)
+                div = 16;
+
+        return parent_rate / div;
+}
+
+static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_erefclk)
+                clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
+        else if (parent == &clk_mpll)
+                clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static unsigned long s3c2412_getrate_uart(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        div &= S3C2412_CLKDIVN_UARTDIV_MASK;
+        div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
+
+        return parent_rate / (div + 1);
+}
+
+static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_clksrc(clk, rate);
+
+        clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
+        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_uart = {
+        .name           = "uartclk",
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2412_getrate_uart,
+                .set_rate       = s3c2412_setrate_uart,
+                .set_parent     = s3c2412_setparent_uart,
+                .round_rate     = s3c2412_roundrate_clksrc,
+        },
+};
+
+static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_erefclk)
+                clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
+        else if (parent == &clk_mpll)
+                clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+
+static unsigned long s3c2412_getrate_i2s(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        div &= S3C2412_CLKDIVN_I2SDIV_MASK;
+        div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
+
+        return parent_rate / (div + 1);
+}
+
+static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_clksrc(clk, rate);
+
+        clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
+        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_i2s = {
+        .name           = "i2sclk",
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2412_getrate_i2s,
+                .set_rate       = s3c2412_setrate_i2s,
+                .set_parent     = s3c2412_setparent_i2s,
+                .round_rate     = s3c2412_roundrate_clksrc,
+        },
+};
+
+static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+
+        if (parent == &clk_usysclk)
+                clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
+        else if (parent == &clk_h)
+                clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        __raw_writel(clksrc, S3C2412_CLKSRC);
+        return 0;
+}
+static unsigned long s3c2412_getrate_cam(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
+
+        div &= S3C2412_CLKDIVN_CAMDIV_MASK;
+        div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
+
+        return parent_rate / (div + 1);
+}
+
+static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
+
+        rate = s3c2412_roundrate_clksrc(clk, rate);
+
+        clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
+        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
+
+        __raw_writel(clkdivn, S3C2410_CLKDIVN);
+        return 0;
+}
+
+static struct clk clk_cam = {
+        .name           = "camif-upll", /* same as 2440 name */
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2412_getrate_cam,
+                .set_rate       = s3c2412_setrate_cam,
+                .set_parent     = s3c2412_setparent_cam,
+                .round_rate     = s3c2412_roundrate_clksrc,
+        },
+};
+
+/* standard clock definitions */
+
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "nand",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_NAND,
+        }, {
+                .name           = "sdi",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_SDI,
+        }, {
+                .name           = "adc",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_ADC,
+        }, {
+                .name           = "i2c",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_IIC,
+        }, {
+                .name           = "iis",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_IIS,
+        }, {
+                .name           = "spi",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_SPI,
+        }
+};
+
+static struct clk init_clocks[] = {
+        {
+                .name           = "dma",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA0,
+        }, {
+                .name           = "dma",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA1,
+        }, {
+                .name           = "dma",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA2,
+        }, {
+                .name           = "dma",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_DMA3,
+        }, {
+                .name           = "lcd",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_LCDC,
+        }, {
+                .name           = "gpio",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_GPIO,
+        }, {
+                .name           = "usb-host",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USBH,
+        }, {
+                .name           = "usb-device",
+                .parent         = &clk_h,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USBD,
+        }, {
+                .name           = "timers",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_PWMT,
+        }, {
+                .name           = "uart",
+                .devname        = "s3c2412-uart.0",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_UART0,
+        }, {
+                .name           = "uart",
+                .devname        = "s3c2412-uart.1",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_UART1,
+        }, {
+                .name           = "uart",
+                .devname        = "s3c2412-uart.2",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_UART2,
+        }, {
+                .name           = "rtc",
+                .parent         = &clk_p,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_RTC,
+        }, {
+                .name           = "watchdog",
+                .parent         = &clk_p,
+                .ctrlbit        = 0,
+        }, {
+                .name           = "usb-bus-gadget",
+                .parent         = &clk_usb_bus,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
+        }, {
+                .name           = "usb-bus-host",
+                .parent         = &clk_usb_bus,
+                .enable         = s3c2412_clkcon_enable,
+                .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
+        }
+};
+
+/* clocks to add where we need to check their parentage */
+
+struct clk_init {
+        struct clk      *clk;
+        unsigned int     bit;
+        struct clk      *src_0;
+        struct clk      *src_1;
+};
+
+static struct clk_init clks_src[] __initdata = {
+        {
+                .clk    = &clk_usysclk,
+                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
+                .src_0  = &clk_urefclk,
+                .src_1  = &clk_upll,
+        }, {
+                .clk    = &clk_i2s,
+                .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
+                .src_0  = &clk_erefclk,
+                .src_1  = &clk_mpll,
+        }, {
+                .clk    = &clk_cam,
+                .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
+                .src_0  = &clk_usysclk,
+                .src_1  = &clk_h,
+        }, {
+                .clk    = &clk_msysclk,
+                .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
+                .src_0  = &clk_mdivclk,
+                .src_1  = &clk_mpll,
+        }, {
+                .clk    = &clk_uart,
+                .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
+                .src_0  = &clk_erefclk,
+                .src_1  = &clk_mpll,
+        }, {
+                .clk    = &clk_usbsrc,
+                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
+                .src_0  = &clk_usysclk,
+                .src_1  = &clk_h,
+        /* here we assume  OM[4] select xtal */
+        }, {
+                .clk    = &clk_erefclk,
+                .bit    = S3C2412_CLKSRC_EREFCLK_EXTCLK,
+                .src_0  = &clk_xtal,
+                .src_1  = &clk_ext,
+        }, {
+                .clk    = &clk_urefclk,
+                .bit    = S3C2412_CLKSRC_UREFCLK_EXTCLK,
+                .src_0  = &clk_xtal,
+                .src_1  = &clk_ext,
+        },
+};
+
+/* s3c2412_clk_initparents
+ *
+ * Initialise the parents for the clocks that we get at start-time
+*/
+
+static void __init s3c2412_clk_initparents(void)
+{
+        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
+        struct clk_init *cip = clks_src;
+        struct clk *src;
+        int ptr;
+        int ret;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
+                ret = s3c24xx_register_clock(cip->clk);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               cip->clk->name, ret);
+                }
+
+                src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
+
+                printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
+                clk_set_parent(cip->clk, src);
+        }
+}
+
+/* clocks to add straight away */
+
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_usb_bus,
+        &clk_mrefclk,
+        &clk_armclk,
+};
+
+int __init s3c2412_baseclk_add(void)
+{
+        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
+        unsigned int dvs;
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        clk_upll.enable = s3c2412_upll_enable;
+        clk_usb_bus.parent = &clk_usbsrc;
+        clk_usb_bus.rate = 0x0;
+
+        clk_f.parent = &clk_msysclk;
+
+        s3c2412_clk_initparents();
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+                clkp = clks[ptr];
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        /* set the dvs state according to what we got at boot time */
+
+        dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
+
+        if (dvs)
+                clk_armclk.parent = &clk_h;
+
+        printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
+
+        /* ensure usb bus clock is within correct rate of 48MHz */
+
+        if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
+                printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
+
+                /* for the moment, let's use the UPLL, and see if we can
+                 * get 48MHz */
+
+                clk_set_parent(&clk_usysclk, &clk_upll);
+                clk_set_parent(&clk_usbsrc, &clk_usysclk);
+                clk_set_rate(&clk_usbsrc, 48*1000*1000);
+        }
+
+        printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
+               (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
+               print_mhz(clk_get_rate(&clk_upll)),
+               print_mhz(clk_get_rate(&clk_usb_bus)));
+
+        /* register clocks from clock array */
+
+        clkp = init_clocks;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+                /* ensure that we note the clock state */
+
+                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        /* We must be careful disabling the clocks we are not intending to
+         * be using at boot time, as subsystems such as the LCD which do
+         * their own DMA requests to the bus can cause the system to lockup
+         * if they where in the middle of requesting bus access.
+         *
+         * Disabling the LCD clock if the LCD is active is very dangerous,
+         * and therefore the bootloader should be careful to not enable
+         * the LCD clock if it is not needed.
+        */
+
+        /* install (and disable) the clocks we do not need immediately */
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+
+                s3c2412_clkcon_enable(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+        return 0;
+}
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
new file mode 100644
index 00000000000..7abecfca0b7
--- /dev/null
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -0,0 +1,195 @@
+/* linux/arch/arm/mach-s3c2412/dma.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 DMA selection
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <mach/dma.h>
+
+#include <plat/dma-s3c24xx.h>
+#include <plat/cpu.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <plat/regs-ac97.h>
+#include <plat/regs-dma.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-sdi.h>
+#include <plat/regs-iis.h>
+#include <plat/regs-spi.h>
+
+#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
+
+static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
+        [DMACH_XD0] = {
+                .name           = "xdreq0",
+                .channels       = MAP(S3C2412_DMAREQSEL_XDREQ0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ0),
+        },
+        [DMACH_XD1] = {
+                .name           = "xdreq1",
+                .channels       = MAP(S3C2412_DMAREQSEL_XDREQ1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ1),
+        },
+        [DMACH_SDI] = {
+                .name           = "sdi",
+                .channels       = MAP(S3C2412_DMAREQSEL_SDI),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
+                .hw_addr.to     = S3C2410_PA_SDI + S3C2410_SDIDATA,
+                .hw_addr.from   = S3C2410_PA_SDI + S3C2410_SDIDATA,
+        },
+        [DMACH_SPI0] = {
+                .name           = "spi0",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
+                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
+                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
+        },
+        [DMACH_SPI1] = {
+                .name           = "spi1",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
+                .hw_addr.to     = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
+                .hw_addr.from   = S3C2410_PA_SPI + S3C2412_SPI1  + S3C2410_SPRDAT,
+        },
+        [DMACH_UART0] = {
+                .name           = "uart0",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
+                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
+        },
+        [DMACH_UART1] = {
+                .name           = "uart1",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
+                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
+        },
+        [DMACH_UART2] = {
+                .name           = "uart2",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
+                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
+        },
+        [DMACH_UART0_SRC2] = {
+                .name           = "uart0",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
+                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
+        },
+        [DMACH_UART1_SRC2] = {
+                .name           = "uart1",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
+                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
+        },
+        [DMACH_UART2_SRC2] = {
+                .name           = "uart2",
+                .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
+                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
+                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
+        },
+        [DMACH_TIMER] = {
+                .name           = "timer",
+                .channels       = MAP(S3C2412_DMAREQSEL_TIMER),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_TIMER),
+        },
+        [DMACH_I2S_IN] = {
+                .name           = "i2s-sdi",
+                .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2SRX),
+        },
+        [DMACH_I2S_OUT] = {
+                .name           = "i2s-sdo",
+                .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2STX),
+        },
+        [DMACH_USB_EP1] = {
+                .name           = "usb-ep1",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP1),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP1),
+        },
+        [DMACH_USB_EP2] = {
+                .name           = "usb-ep2",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP2),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP2),
+        },
+        [DMACH_USB_EP3] = {
+                .name           = "usb-ep3",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP3),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP3),
+        },
+        [DMACH_USB_EP4] = {
+                .name           = "usb-ep4",
+                .channels       = MAP(S3C2412_DMAREQSEL_USBEP4),
+                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP4),
+        },
+};
+
+static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
+                                  struct s3c24xx_dma_map *map,
+                                  enum s3c2410_dmasrc dir)
+{
+        unsigned long chsel;
+
+        if (dir == S3C2410_DMASRC_HW)
+                chsel = map->channels_rx[0];
+        else
+                chsel = map->channels[0];
+
+        chsel &= ~DMA_CH_VALID;
+        chsel |= S3C2412_DMAREQSEL_HW;
+
+        writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
+}
+
+static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
+                               struct s3c24xx_dma_map *map)
+{
+        s3c2412_dma_direction(chan, map, chan->source);
+}
+
+static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
+        .select         = s3c2412_dma_select,
+        .direction      = s3c2412_dma_direction,
+        .dcon_mask      = 0,
+        .map            = s3c2412_dma_mappings,
+        .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
+};
+
+static int __init s3c2412_dma_add(struct sys_device *sysdev)
+{
+        s3c2410_dma_init();
+        return s3c24xx_dma_init_map(&s3c2412_dma_sel);
+}
+
+static struct sysdev_driver s3c2412_dma_driver = {
+        .add    = s3c2412_dma_add,
+};
+
+static int __init s3c2412_dma_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
+}
+
+arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
new file mode 100644
index 00000000000..1a1aa220972
--- /dev/null
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -0,0 +1,212 @@
+/* linux/arch/arm/mach-s3c2412/irq.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/irq.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-power.h>
+
+#include <plat/cpu.h>
+#include <plat/irq.h>
+#include <plat/pm.h>
+
+#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
+#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
+
+/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
+ * having them turn up in both the INT* and the EINT* registers. Whilst
+ * both show the status, they both now need to be acked when the IRQs
+ * go off.
+*/
+
+static void
+s3c2412_irq_mask(struct irq_data *data)
+{
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
+        unsigned long mask;
+
+        mask = __raw_readl(S3C2410_INTMSK);
+        __raw_writel(mask | bitval, S3C2410_INTMSK);
+
+        mask = __raw_readl(S3C2412_EINTMASK);
+        __raw_writel(mask | bitval, S3C2412_EINTMASK);
+}
+
+static inline void
+s3c2412_irq_ack(struct irq_data *data)
+{
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
+
+        __raw_writel(bitval, S3C2412_EINTPEND);
+        __raw_writel(bitval, S3C2410_SRCPND);
+        __raw_writel(bitval, S3C2410_INTPND);
+}
+
+static inline void
+s3c2412_irq_maskack(struct irq_data *data)
+{
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
+        unsigned long mask;
+
+        mask = __raw_readl(S3C2410_INTMSK);
+        __raw_writel(mask|bitval, S3C2410_INTMSK);
+
+        mask = __raw_readl(S3C2412_EINTMASK);
+        __raw_writel(mask | bitval, S3C2412_EINTMASK);
+
+        __raw_writel(bitval, S3C2412_EINTPEND);
+        __raw_writel(bitval, S3C2410_SRCPND);
+        __raw_writel(bitval, S3C2410_INTPND);
+}
+
+static void
+s3c2412_irq_unmask(struct irq_data *data)
+{
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
+        unsigned long mask;
+
+        mask = __raw_readl(S3C2412_EINTMASK);
+        __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
+
+        mask = __raw_readl(S3C2410_INTMSK);
+        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
+}
+
+static struct irq_chip s3c2412_irq_eint0t4 = {
+        .irq_ack        = s3c2412_irq_ack,
+        .irq_mask       = s3c2412_irq_mask,
+        .irq_unmask     = s3c2412_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake,
+        .irq_set_type   = s3c_irqext_type,
+};
+
+#define INTBIT(x)       (1 << ((x) - S3C2410_IRQSUB(0)))
+
+/* CF and SDI sub interrupts */
+
+static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int subsrc, submsk;
+
+        subsrc = __raw_readl(S3C2410_SUBSRCPND);
+        submsk = __raw_readl(S3C2410_INTSUBMSK);
+
+        subsrc  &= ~submsk;
+
+        if (subsrc & INTBIT(IRQ_S3C2412_SDI))
+                generic_handle_irq(IRQ_S3C2412_SDI);
+
+        if (subsrc & INTBIT(IRQ_S3C2412_CF))
+                generic_handle_irq(IRQ_S3C2412_CF);
+}
+
+#define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
+#define SUBMSK_CFSDI    INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
+
+static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
+{
+        s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
+}
+
+static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
+{
+        s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
+}
+
+static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
+{
+        s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
+}
+
+static struct irq_chip s3c2412_irq_cfsdi = {
+        .name           = "s3c2412-cfsdi",
+        .irq_ack        = s3c2412_irq_cfsdi_ack,
+        .irq_mask       = s3c2412_irq_cfsdi_mask,
+        .irq_unmask     = s3c2412_irq_cfsdi_unmask,
+};
+
+static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
+{
+        unsigned long pwrcfg;
+
+        pwrcfg = __raw_readl(S3C2412_PWRCFG);
+        if (state)
+                pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
+        else
+                pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
+        __raw_writel(pwrcfg, S3C2412_PWRCFG);
+
+        return s3c_irq_chip.irq_set_wake(data, state);
+}
+
+static struct irq_chip s3c2412_irq_rtc_chip;
+
+static int s3c2412_irq_add(struct sys_device *sysdev)
+{
+        unsigned int irqno;
+
+        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
+                irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
+                                         handle_edge_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+
+        /* add demux support for CF/SDI */
+
+        irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
+
+        for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
+                irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
+                                         handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+
+        /* change RTC IRQ's set wake method */
+
+        s3c2412_irq_rtc_chip = s3c_irq_chip;
+        s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
+
+        irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2412_irq_driver = {
+        .add            = s3c2412_irq_add,
+};
+
+static int s3c2412_irq_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
+}
+
+arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
new file mode 100644
index 00000000000..5eeb47580b0
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -0,0 +1,664 @@
+/* linux/arch/arm/mach-s3c2410/mach-jive.c
+ *
+ * Copyright 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/syscore_ops.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <video/ili9320.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <plat/regs-serial.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
+
+#include <mach/regs-power.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/udc.h>
+
+static struct map_desc jive_iodesc[] __initdata = {
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg jive_uartcfgs[] = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        }
+};
+
+/* Jive flash assignment
+ *
+ * 0x00000000-0x00028000 : uboot
+ * 0x00028000-0x0002c000 : uboot env
+ * 0x0002c000-0x00030000 : spare
+ * 0x00030000-0x00200000 : zimage A
+ * 0x00200000-0x01600000 : cramfs A
+ * 0x01600000-0x017d0000 : zimage B
+ * 0x017d0000-0x02bd0000 : cramfs B
+ * 0x02bd0000-0x03fd0000 : yaffs
+ */
+static struct mtd_partition __initdata jive_imageA_nand_part[] = {
+
+#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
+        /* Don't allow access to the bootloader from linux */
+        {
+                .name           = "uboot",
+                .offset         = 0,
+                .size           = (160 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* spare */
+        {
+                .name           = "spare",
+                .offset         = (176 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+#endif
+
+        /* booted images */
+        {
+                .name           = "kernel (ro)",
+                .offset         = (192 * SZ_1K),
+                .size           = (SZ_2M) - (192 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        }, {
+                .name           = "root (ro)",
+                .offset         = (SZ_2M),
+                .size           = (20 * SZ_1M),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* yaffs */
+        {
+                .name           = "yaffs",
+                .offset         = (44 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+
+        /* bootloader environment */
+        {
+                .name           = "env",
+                .offset         = (160 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+
+        /* upgrade images */
+        {
+                .name           = "zimage",
+                .offset         = (22 * SZ_1M),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+        }, {
+                .name           = "cramfs",
+                .offset         = (24 * SZ_1M) - (192*SZ_1K),
+                .size           = (20 * SZ_1M),
+        },
+};
+
+static struct mtd_partition __initdata jive_imageB_nand_part[] = {
+
+#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
+        /* Don't allow access to the bootloader from linux */
+        {
+                .name           = "uboot",
+                .offset         = 0,
+                .size           = (160 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* spare */
+        {
+                .name           = "spare",
+                .offset         = (176 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+#endif
+
+        /* booted images */
+        {
+                .name           = "kernel (ro)",
+                .offset         = (22 * SZ_1M),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+        {
+                .name           = "root (ro)",
+                .offset         = (24 * SZ_1M) - (192 * SZ_1K),
+                .size           = (20 * SZ_1M),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* yaffs */
+        {
+                .name           = "yaffs",
+                .offset         = (44 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+
+        /* bootloader environment */
+        {
+                .name           = "env",
+                .offset         = (160 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+
+        /* upgrade images */
+        {
+                .name           = "zimage",
+                .offset         = (192 * SZ_1K),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+        }, {
+                .name           = "cramfs",
+                .offset         = (2 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+};
+
+static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
+        [0] = {
+                .name           = "flash",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
+                .partitions     = jive_imageA_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand __initdata jive_nand_info = {
+        /* set taken from osiris nand timings, possibly still conservative */
+        .tacls          = 30,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .sets           = jive_nand_sets,
+        .nr_sets        = ARRAY_SIZE(jive_nand_sets),
+};
+
+static int __init jive_mtdset(char *options)
+{
+        struct s3c2410_nand_set *nand = &jive_nand_sets[0];
+        unsigned long set;
+
+        if (options == NULL || options[0] == '\0')
+                return 0;
+
+        if (strict_strtoul(options, 10, &set)) {
+                printk(KERN_ERR "failed to parse mtdset=%s\n", options);
+                return 0;
+        }
+
+        switch (set) {
+        case 1:
+                nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
+                nand->partitions = jive_imageB_nand_part;
+        case 0:
+                /* this is already setup in the nand info */
+                break;
+        default:
+                printk(KERN_ERR "Unknown mtd set %ld specified,"
+                       "using default.", set);
+        }
+
+        return 0;
+}
+
+/* parse the mtdset= option given to the kernel command line */
+__setup("mtdset=", jive_mtdset);
+
+/* LCD timing and setup */
+
+#define LCD_XRES         (240)
+#define LCD_YRES         (320)
+#define LCD_LEFT_MARGIN  (12)
+#define LCD_RIGHT_MARGIN (12)
+#define LCD_LOWER_MARGIN (12)
+#define LCD_UPPER_MARGIN (12)
+#define LCD_VSYNC        (2)
+#define LCD_HSYNC        (2)
+
+#define LCD_REFRESH      (60)
+
+#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
+#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
+
+static struct s3c2410fb_display jive_vgg2432a4_display[] = {
+        [0] = {
+                .width          = LCD_XRES,
+                .height         = LCD_YRES,
+                .xres           = LCD_XRES,
+                .yres           = LCD_YRES,
+                .left_margin    = LCD_LEFT_MARGIN,
+                .right_margin   = LCD_RIGHT_MARGIN,
+                .upper_margin   = LCD_UPPER_MARGIN,
+                .lower_margin   = LCD_LOWER_MARGIN,
+                .hsync_len      = LCD_HSYNC,
+                .vsync_len      = LCD_VSYNC,
+
+                .pixclock       = (1000000000000LL /
+                                   (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
+
+                .bpp            = 16,
+                .type           = (S3C2410_LCDCON1_TFT16BPP |
+                                   S3C2410_LCDCON1_TFT),
+
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_PWREN),
+        },
+};
+
+/* todo - put into gpio header */
+
+#define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
+#define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
+
+static struct s3c2410fb_mach_info jive_lcd_config = {
+        .displays        = jive_vgg2432a4_display,
+        .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
+        .default_display = 0,
+
+        /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
+         * and disable the pull down resistors on pins we are using for LCD
+         * data. */
+
+        .gpcup          = (0xf << 1) | (0x3f << 10),
+
+        .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
+                           S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
+                           S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
+                           S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
+                           S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
+
+        .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
+                           S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
+                           S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
+                           S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
+                           S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
+
+        .gpdup          = (0x3f << 2) | (0x3f << 10),
+
+        .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
+                           S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
+                           S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
+                           S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
+                           S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
+                           S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
+
+        .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
+                           S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
+                           S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
+                           S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
+                           S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
+                           S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
+};
+
+/* ILI9320 support. */
+
+static void jive_lcm_reset(unsigned int set)
+{
+        printk(KERN_DEBUG "%s(%d)\n", __func__, set);
+
+        gpio_set_value(S3C2410_GPG(13), set);
+}
+
+#undef LCD_UPPER_MARGIN
+#define LCD_UPPER_MARGIN 2
+
+static struct ili9320_platdata jive_lcm_config = {
+        .hsize          = LCD_XRES,
+        .vsize          = LCD_YRES,
+
+        .reset          = jive_lcm_reset,
+        .suspend        = ILI9320_SUSPEND_DEEP,
+
+        .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
+        .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
+                           ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
+        .display3       = 0x0,
+        .display4       = 0x0,
+        .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
+                           ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
+        .rgb_if2        = ILI9320_RGBIF2_DPL,
+        .interface2     = 0x0,
+        .interface3     = 0x3,
+        .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
+                           ILI9320_INTERFACE4_DIVE(1)),
+        .interface5     = 0x0,
+        .interface6     = 0x0,
+};
+
+/* LCD SPI support */
+
+static struct spi_gpio_platform_data jive_lcd_spi = {
+        .sck            = S3C2410_GPG(8),
+        .mosi           = S3C2410_GPB(8),
+        .miso           = SPI_GPIO_NO_MISO,
+};
+
+static struct platform_device jive_device_lcdspi = {
+        .name           = "spi-gpio",
+        .id             = 1,
+        .dev.platform_data = &jive_lcd_spi,
+};
+
+
+/* WM8750 audio code SPI definition */
+
+static struct spi_gpio_platform_data jive_wm8750_spi = {
+        .sck            = S3C2410_GPB(4),
+        .mosi           = S3C2410_GPB(9),
+        .miso           = SPI_GPIO_NO_MISO,
+};
+
+static struct platform_device jive_device_wm8750 = {
+        .name           = "spi-gpio",
+        .id             = 2,
+        .dev.platform_data = &jive_wm8750_spi,
+};
+
+/* JIVE SPI devices. */
+
+static struct spi_board_info __initdata jive_spi_devs[] = {
+        [0] = {
+                .modalias       = "VGG2432A4",
+                .bus_num        = 1,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
+                .max_speed_hz   = 100000,
+                .platform_data  = &jive_lcm_config,
+                .controller_data = (void *)S3C2410_GPB(7),
+        }, {
+                .modalias       = "WM8750",
+                .bus_num        = 2,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
+                .max_speed_hz   = 100000,
+                .controller_data = (void *)S3C2410_GPH(10),
+        },
+};
+
+/* I2C bus and device configuration. */
+
+static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
+        .frequency      = 80 * 1000,
+        .flags          = S3C_IICFLG_FILTER,
+        .sda_delay      = 2,
+};
+
+static struct i2c_board_info jive_i2c_devs[] __initdata = {
+        [0] = {
+                I2C_BOARD_INFO("lis302dl", 0x1c),
+                .irq    = IRQ_EINT14,
+        },
+};
+
+/* The platform devices being used. */
+
+static struct platform_device *jive_devices[] __initdata = {
+        &s3c_device_ohci,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &s3c_device_i2c0,
+        &s3c_device_lcd,
+        &jive_device_lcdspi,
+        &jive_device_wm8750,
+        &s3c_device_nand,
+        &s3c_device_usbgadget,
+};
+
+static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
+        .vbus_pin       = S3C2410_GPG(1),               /* detect is on GPG1 */
+};
+
+/* Jive power management device */
+
+#ifdef CONFIG_PM
+static int jive_pm_suspend(void)
+{
+        /* Write the magic value u-boot uses to check for resume into
+         * the INFORM0 register, and ensure INFORM1 is set to the
+         * correct address to resume from. */
+
+        __raw_writel(0x2BED, S3C2412_INFORM0);
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+
+        return 0;
+}
+
+static void jive_pm_resume(void)
+{
+        __raw_writel(0x0, S3C2412_INFORM0);
+}
+
+#else
+#define jive_pm_suspend NULL
+#define jive_pm_resume NULL
+#endif
+
+static struct syscore_ops jive_pm_syscore_ops = {
+        .suspend        = jive_pm_suspend,
+        .resume         = jive_pm_resume,
+};
+
+static void __init jive_map_io(void)
+{
+        s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+}
+
+static void jive_power_off(void)
+{
+        printk(KERN_INFO "powering system down...\n");
+
+        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+        s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+}
+
+static void __init jive_machine_init(void)
+{
+        /* register system core operations for managing low level suspend */
+
+        register_syscore_ops(&jive_pm_syscore_ops);
+
+        /* write our sleep configurations for the IO. Pull down all unused
+         * IO, ensure that we have turned off all peripherals we do not
+         * need, and configure the ones we do need. */
+
+        /* Port B sleep */
+
+        __raw_writel(S3C2412_SLPCON_IN(0)   |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_HIGH(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_HIGH(7) |
+                     S3C2412_SLPCON_PULL(8) |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
+
+        /* Port C sleep */
+
+        __raw_writel(S3C2412_SLPCON_PULL(0) |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_PULL(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_LOW(6)  |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_PULL(7) |
+                     S3C2412_SLPCON_PULL(8) |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_PULL(10) |
+                     S3C2412_SLPCON_PULL(11) |
+                     S3C2412_SLPCON_PULL(12) |
+                     S3C2412_SLPCON_PULL(13) |
+                     S3C2412_SLPCON_PULL(14) |
+                     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
+
+        /* Port D sleep */
+
+        __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
+
+        /* Port F sleep */
+
+        __raw_writel(S3C2412_SLPCON_LOW(0)  |
+                     S3C2412_SLPCON_LOW(1)  |
+                     S3C2412_SLPCON_LOW(2)  |
+                     S3C2412_SLPCON_EINT(3) |
+                     S3C2412_SLPCON_EINT(4) |
+                     S3C2412_SLPCON_EINT(5) |
+                     S3C2412_SLPCON_EINT(6) |
+                     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
+
+        /* Port G sleep */
+
+        __raw_writel(S3C2412_SLPCON_IN(0)    |
+                     S3C2412_SLPCON_IN(1)    |
+                     S3C2412_SLPCON_IN(2)    |
+                     S3C2412_SLPCON_IN(3)    |
+                     S3C2412_SLPCON_IN(4)    |
+                     S3C2412_SLPCON_IN(5)    |
+                     S3C2412_SLPCON_IN(6)    |
+                     S3C2412_SLPCON_IN(7)    |
+                     S3C2412_SLPCON_PULL(8)  |
+                     S3C2412_SLPCON_PULL(9)  |
+                     S3C2412_SLPCON_IN(10)   |
+                     S3C2412_SLPCON_PULL(11) |
+                     S3C2412_SLPCON_PULL(12) |
+                     S3C2412_SLPCON_PULL(13) |
+                     S3C2412_SLPCON_IN(14)   |
+                     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
+
+        /* Port H sleep */
+
+        __raw_writel(S3C2412_SLPCON_PULL(0) |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_PULL(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_IN(7)   |
+                     S3C2412_SLPCON_IN(8)   |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
+
+        /* initialise the power management now we've setup everything. */
+
+        s3c_pm_init();
+
+        /** TODO - check that this is after the cmdline option! */
+        s3c_nand_set_platdata(&jive_nand_info);
+
+        /* initialise the spi */
+
+        gpio_request(S3C2410_GPG(13), "lcm reset");
+        gpio_direction_output(S3C2410_GPG(13), 0);
+
+        gpio_request(S3C2410_GPB(7), "jive spi");
+        gpio_direction_output(S3C2410_GPB(7), 1);
+
+        s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
+        s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
+        s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+
+        /* initialise the WM8750 spi */
+
+        gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
+        gpio_direction_output(S3C2410_GPH(10), 1);
+
+        /* Turn off suspend on both USB ports, and switch the
+         * selectable USB port to USB device mode. */
+
+        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                              S3C2410_MISCCR_USBSUSPND0 |
+                              S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+        s3c24xx_udc_set_platdata(&jive_udc_cfg);
+        s3c24xx_fb_set_platdata(&jive_lcd_config);
+
+        spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
+
+        s3c_i2c0_set_platdata(&jive_i2c_cfg);
+        i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
+
+        pm_power_off = jive_power_off;
+
+        platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
+}
+
+MACHINE_START(JIVE, "JIVE")
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = jive_map_io,
+        .init_machine   = jive_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
new file mode 100644
index 00000000000..834cfb61bcf
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -0,0 +1,160 @@
+/* linux/arch/arm/mach-s3c2412/mach-smdk2413.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Thanks to Dimity Andric (TomTom) and Steven Ryu (Samsung) for the
+ * loans of SMDK2413 to work with.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/hardware/iomd.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+//#include <asm/debug-ll.h>
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
+
+#include <mach/idle.h>
+#include <plat/udc.h>
+#include <plat/iic.h>
+#include <mach/fb.h>
+
+#include <plat/s3c2410.h>
+#include <plat/s3c2412.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <plat/common-smdk.h>
+
+static struct map_desc smdk2413_iodesc[] __initdata = {
+};
+
+static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        /* IR port */
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x43,
+                .ufcon       = 0x51,
+        }
+};
+
+
+static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = {
+        .pullup_pin = S3C2410_GPF(2),
+};
+
+
+static struct platform_device *smdk2413_devices[] __initdata = {
+        &s3c_device_ohci,
+        &s3c_device_wdt,
+        &s3c_device_i2c0,
+        &s3c_device_iis,
+        &s3c_device_usbgadget,
+};
+
+static void __init smdk2413_fixup(struct machine_desc *desc,
+                                  struct tag *tags, char **cmdline,
+                                  struct meminfo *mi)
+{
+        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
+                mi->nr_banks=1;
+                mi->bank[0].start = 0x30000000;
+                mi->bank[0].size = SZ_64M;
+        }
+}
+
+static void __init smdk2413_map_io(void)
+{
+        s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+}
+
+static void __init smdk2413_machine_init(void)
+{       /* Turn off suspend on both USB ports, and switch the
+         * selectable USB port to USB device mode. */
+
+        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                              S3C2410_MISCCR_USBSUSPND0 |
+                              S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+
+        s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
+        s3c_i2c0_set_platdata(NULL);
+
+        platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
+        smdk_machine_init();
+}
+
+MACHINE_START(S3C2413, "S3C2413")
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = smdk2413_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2413_map_io,
+        .init_machine   = smdk2413_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
+
+MACHINE_START(SMDK2412, "SMDK2412")
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = smdk2413_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2413_map_io,
+        .init_machine   = smdk2413_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
+
+MACHINE_START(SMDK2413, "SMDK2413")
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = smdk2413_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2413_map_io,
+        .init_machine   = smdk2413_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
new file mode 100644
index 00000000000..83544ebe20a
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -0,0 +1,166 @@
+/* linux/arch/arm/mach-s3c2412/mach-vstms.c
+ *
+ * (C) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
+
+#include <mach/idle.h>
+#include <mach/fb.h>
+
+#include <plat/iic.h>
+#include <plat/nand.h>
+
+#include <plat/s3c2410.h>
+#include <plat/s3c2412.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+
+static struct map_desc vstms_iodesc[] __initdata = {
+};
+
+static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        }
+};
+
+static struct mtd_partition __initdata vstms_nand_part[] = {
+        [0] = {
+                .name   = "Boot Agent",
+                .size   = 0x7C000,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "UBoot Config",
+                .offset = 0x7C000,
+                .size   = 0x4000,
+        },
+        [2] = {
+                .name   = "Kernel",
+                .offset = 0x80000,
+                .size   = 0x200000,
+        },
+        [3] = {
+                .name   = "RFS",
+                .offset = 0x280000,
+                .size   = 0x3d80000,
+        },
+};
+
+static struct s3c2410_nand_set __initdata vstms_nand_sets[] = {
+        [0] = {
+                .name           = "NAND",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(vstms_nand_part),
+                .partitions     = vstms_nand_part,
+        },
+};
+
+/* choose a set of timings which should suit most 512Mbit
+ * chips and beyond.
+*/
+
+static struct s3c2410_platform_nand __initdata vstms_nand_info = {
+        .tacls          = 20,
+        .twrph0         = 60,
+        .twrph1         = 20,
+        .nr_sets        = ARRAY_SIZE(vstms_nand_sets),
+        .sets           = vstms_nand_sets,
+};
+
+static struct platform_device *vstms_devices[] __initdata = {
+        &s3c_device_ohci,
+        &s3c_device_wdt,
+        &s3c_device_i2c0,
+        &s3c_device_iis,
+        &s3c_device_rtc,
+        &s3c_device_nand,
+};
+
+static void __init vstms_fixup(struct machine_desc *desc,
+                                  struct tag *tags, char **cmdline,
+                                  struct meminfo *mi)
+{
+        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
+                mi->nr_banks=1;
+                mi->bank[0].start = 0x30000000;
+                mi->bank[0].size = SZ_64M;
+        }
+}
+
+static void __init vstms_map_io(void)
+{
+        s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+}
+
+static void __init vstms_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&vstms_nand_info);
+
+        platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
+}
+
+MACHINE_START(VSTMS, "VSTMS")
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .fixup          = vstms_fixup,
+        .init_irq       = s3c24xx_init_irq,
+        .init_machine   = vstms_init,
+        .map_io         = vstms_map_io,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
new file mode 100644
index 00000000000..f4077efa51f
--- /dev/null
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -0,0 +1,122 @@
+/* linux/arch/arm/mach-s3c2412/pm.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/syscore_ops.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/cacheflush.h>
+#include <asm/irq.h>
+
+#include <mach/regs-power.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-dsc.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+#include <plat/s3c2412.h>
+
+extern void s3c2412_sleep_enter(void);
+
+static int s3c2412_cpu_suspend(unsigned long arg)
+{
+        unsigned long tmp;
+
+        /* set our standby method to sleep */
+
+        tmp = __raw_readl(S3C2412_PWRCFG);
+        tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP;
+        __raw_writel(tmp, S3C2412_PWRCFG);
+
+        s3c2412_sleep_enter();
+
+        panic("sleep resumed to originator?");
+}
+
+static void s3c2412_pm_prepare(void)
+{
+}
+
+static int s3c2412_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = s3c2412_pm_prepare;
+        pm_cpu_sleep = s3c2412_cpu_suspend;
+
+        return 0;
+}
+
+static struct sleep_save s3c2412_sleep[] = {
+        SAVE_ITEM(S3C2412_DSC0),
+        SAVE_ITEM(S3C2412_DSC1),
+        SAVE_ITEM(S3C2413_GPJDAT),
+        SAVE_ITEM(S3C2413_GPJCON),
+        SAVE_ITEM(S3C2413_GPJUP),
+
+        /* save the PWRCFG to get back to original sleep method */
+
+        SAVE_ITEM(S3C2412_PWRCFG),
+
+        /* save the sleep configuration anyway, just in case these
+         * get damaged during wakeup */
+
+        SAVE_ITEM(S3C2412_GPBSLPCON),
+        SAVE_ITEM(S3C2412_GPCSLPCON),
+        SAVE_ITEM(S3C2412_GPDSLPCON),
+        SAVE_ITEM(S3C2412_GPFSLPCON),
+        SAVE_ITEM(S3C2412_GPGSLPCON),
+        SAVE_ITEM(S3C2412_GPHSLPCON),
+        SAVE_ITEM(S3C2413_GPJSLPCON),
+};
+
+static struct sysdev_driver s3c2412_pm_driver = {
+        .add            = s3c2412_pm_add,
+};
+
+static __init int s3c2412_pm_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver);
+}
+
+arch_initcall(s3c2412_pm_init);
+
+static int s3c2412_pm_suspend(void)
+{
+        s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+        return 0;
+}
+
+static void s3c2412_pm_resume(void)
+{
+        unsigned long tmp;
+
+        tmp = __raw_readl(S3C2412_PWRCFG);
+        tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
+        tmp |=  S3C2412_PWRCFG_STANDBYWFI_IDLE;
+        __raw_writel(tmp, S3C2412_PWRCFG);
+
+        s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+}
+
+struct syscore_ops s3c2412_pm_syscore_ops = {
+        .suspend        = s3c2412_pm_suspend,
+        .resume         = s3c2412_pm_resume,
+};
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
new file mode 100644
index 00000000000..57a1e01e4e5
--- /dev/null
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -0,0 +1,254 @@
+/* linux/arch/arm/mach-s3c2412/s3c2412.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/sysdev.h>
+#include <linux/syscore_ops.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/irq.h>
+
+#include <mach/reset.h>
+#include <mach/idle.h>
+
+#include <plat/cpu-freq.h>
+
+#include <mach/regs-clock.h>
+#include <plat/regs-serial.h>
+#include <mach/regs-power.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-dsc.h>
+#include <plat/regs-spi.h>
+#include <mach/regs-s3c2412.h>
+
+#include <plat/s3c2412.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/pm.h>
+#include <plat/pll.h>
+#include <plat/nand-core.h>
+
+#ifndef CONFIG_CPU_S3C2412_ONLY
+void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
+
+static inline void s3c2412_init_gpio2(void)
+{
+        s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
+}
+#else
+#define s3c2412_init_gpio2() do { } while(0)
+#endif
+
+/* Initial IO mappings */
+
+static struct map_desc s3c2412_iodesc[] __initdata = {
+        IODESC_ENT(CLKPWR),
+        IODESC_ENT(TIMER),
+        IODESC_ENT(WATCHDOG),
+        {
+                .virtual = (unsigned long)S3C2412_VA_SSMC,
+                .pfn     = __phys_to_pfn(S3C2412_PA_SSMC),
+                .length  = SZ_1M,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = (unsigned long)S3C2412_VA_EBI,
+                .pfn     = __phys_to_pfn(S3C2412_PA_EBI),
+                .length  = SZ_1M,
+                .type    = MT_DEVICE,
+        },
+};
+
+/* uart registration process */
+
+void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
+
+        /* rename devices that are s3c2412/s3c2413 specific */
+        s3c_device_sdi.name  = "s3c2412-sdi";
+        s3c_device_lcd.name  = "s3c2412-lcd";
+        s3c_nand_setname("s3c2412-nand");
+
+        /* alter IRQ of SDI controller */
+
+        s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
+        s3c_device_sdi.resource[1].end   = IRQ_S3C2412_SDI;
+
+        /* spi channel related changes, s3c2412/13 specific */
+        s3c_device_spi0.name = "s3c2412-spi";
+        s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
+        s3c_device_spi1.name = "s3c2412-spi";
+        s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
+        s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
+
+}
+
+/* s3c2412_idle
+ *
+ * use the standard idle call by ensuring the idle mode
+ * in power config, then issuing the idle co-processor
+ * instruction
+*/
+
+static void s3c2412_idle(void)
+{
+        unsigned long tmp;
+
+        /* ensure our idle mode is to go to idle */
+
+        tmp = __raw_readl(S3C2412_PWRCFG);
+        tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
+        tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
+        __raw_writel(tmp, S3C2412_PWRCFG);
+
+        cpu_do_idle();
+}
+
+static void s3c2412_hard_reset(void)
+{
+        /* errata "Watch-dog/Software Reset Problem" specifies that
+         * this reset must be done with the SYSCLK sourced from
+         * EXTCLK instead of FOUT to avoid a glitch in the reset
+         * mechanism.
+         *
+         * See the watchdog section of the S3C2412 manual for more
+         * information on this fix.
+         */
+
+        __raw_writel(0x00, S3C2412_CLKSRC);
+        __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
+
+        mdelay(1);
+}
+
+/* s3c2412_map_io
+ *
+ * register the standard cpu IO areas, and any passed in from the
+ * machine specific initialisation.
+*/
+
+void __init s3c2412_map_io(void)
+{
+        /* move base of IO */
+
+        s3c2412_init_gpio2();
+
+        /* set our idle function */
+
+        s3c24xx_idle = s3c2412_idle;
+
+        /* set custom reset hook */
+
+        s3c24xx_reset_hook = s3c2412_hard_reset;
+
+        /* register our io-tables */
+
+        iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
+}
+
+void __init_or_cpufreq s3c2412_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long tmp;
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long pclk;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        /* now we've got our machine bits initialised, work out what
+         * clocks we've got */
+
+        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
+
+        clk_mpll.rate = fclk;
+
+        tmp = __raw_readl(S3C2410_CLKDIVN);
+
+        /* work out clock scalings */
+
+        hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
+        hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
+        pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
+
+        /* print brieft summary of clocks, etc */
+
+        printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
+               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
+
+        s3c24xx_setup_clocks(fclk, hclk, pclk);
+}
+
+void __init s3c2412_init_clocks(int xtal)
+{
+        /* initialise the clocks here, to allow other things like the
+         * console to use them
+         */
+
+        s3c24xx_register_baseclocks(xtal);
+        s3c2412_setup_clocks();
+        s3c2412_baseclk_add();
+}
+
+/* need to register class before we actually register the device, and
+ * we also need to ensure that it has been initialised before any of the
+ * drivers even try to use it (even if not on an s3c2412 based system)
+ * as a driver which may support both 2410 and 2440 may try and use it.
+*/
+
+struct sysdev_class s3c2412_sysclass = {
+        .name = "s3c2412-core",
+};
+
+static int __init s3c2412_core_init(void)
+{
+        return sysdev_class_register(&s3c2412_sysclass);
+}
+
+core_initcall(s3c2412_core_init);
+
+static struct sys_device s3c2412_sysdev = {
+        .cls            = &s3c2412_sysclass,
+};
+
+int __init s3c2412_init(void)
+{
+        printk("S3C2412: Initialising architecture\n");
+
+#ifdef CONFIG_PM
+        register_syscore_ops(&s3c2412_pm_syscore_ops);
+#endif
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
+
+        return sysdev_register(&s3c2412_sysdev);
+}
diff --git a/arch/arm/mach-s3c2412/sleep.S b/arch/arm/mach-s3c2412/sleep.S
new file mode 100644
index 00000000000..c82418ed714
--- /dev/null
+++ b/arch/arm/mach-s3c2412/sleep.S
@@ -0,0 +1,68 @@
+/* linux/arch/arm/mach-s3c2412/sleep.S
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 Power Manager low-level sleep support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <mach/regs-irq.h>
+
+        .text
+
+        .global s3c2412_sleep_enter
+
+s3c2412_sleep_enter:
+        mov     r0, #0                  /* argument for coprocessors */
+        ldr     r1, =S3C2410_INTPND
+        ldr     r2, =S3C2410_SRCPND
+        ldr     r3, =S3C2410_EINTPEND
+
+        teq     r0, r0
+        bl      s3c2412_sleep_enter1
+        teq     pc, r0
+        bl      s3c2412_sleep_enter1
+
+        .align  5
+
+        /* this is called twice, first with the Z flag to ensure that the
+         * instructions have been loaded into the cache, and the second
+         * time to try and suspend the system.
+        */
+s3c2412_sleep_enter1:
+        mcr     p15, 0, r0, c7, c10, 4
+        mcrne   p15, 0, r0, c7, c0, 4
+
+        /* if we return from here, it is because an interrupt was
+         * active when we tried to shutdown. Try and ack the IRQ and
+         * retry, as simply returning causes the system to lock.
+        */
+
+        ldrne   r9, [ r1 ]
+        strne   r9, [ r1 ]
+        ldrne   r9, [ r2 ]
+        strne   r9, [ r2 ]
+        ldrne   r9, [ r3 ]
+        strne   r9, [ r3 ]
+        bne     s3c2412_sleep_enter1
+
+        mov     pc, r14