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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/arm/mach-ixp4xx
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/arm/mach-ixp4xx')
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig21
-rw-r--r--arch/arm/mach-ixp4xx/Makefile4
-rw-r--r--arch/arm/mach-ixp4xx/Makefile.boot2
-rw-r--r--arch/arm/mach-ixp4xx/avila-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/avila-setup.c8
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c38
-rw-r--r--arch/arm/mach-ixp4xx/common.c144
-rw-r--r--arch/arm/mach-ixp4xx/coyote-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c8
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c7
-rw-r--r--arch/arm/mach-ixp4xx/fsg-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c7
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/goramo_mlr.c11
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/cpu.h5
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/debug-macro.S6
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h26
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h3
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h48
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/platform.h4
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/qmgr.h12
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/udc.h2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/uncompress.h3
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c17
-rw-r--r--arch/arm/mach-ixp4xx/ixdpg425-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_npe.c9
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_qmgr.c12
-rw-r--r--arch/arm/mach-ixp4xx/miccpt-pci.c77
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c7
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c7
-rw-r--r--arch/arm/mach-ixp4xx/omixp-setup.c279
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-pci.c3
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-setup.c4
44 files changed, 193 insertions, 634 deletions
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 73a2d905af8..6f991c5ae86 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,25 +179,6 @@ config MACH_GTWX5715
179 "High Speed" UART is n/c (as far as I can tell) 179 "High Speed" UART is n/c (as far as I can tell)
180 20 Pin ARM/Xscale JTAG interface on J2 180 20 Pin ARM/Xscale JTAG interface on J2
181 181
182config MACH_DEVIXP
183 bool "Omicron DEVIXP"
184 help
185 Say 'Y' here if you want your kernel to support the DEVIXP
186 board from OMICRON electronics GmbH.
187
188config MACH_MICCPT
189 bool "Omicron MICCPT"
190 select PCI
191 help
192 Say 'Y' here if you want your kernel to support the MICCPT
193 board from OMICRON electronics GmbH.
194
195config MACH_MIC256
196 bool "Omicron MIC256"
197 help
198 Say 'Y' here if you want your kernel to support the MIC256
199 board from OMICRON electronics GmbH.
200
201comment "IXP4xx Options" 182comment "IXP4xx Options"
202 183
203config IXP4XX_INDIRECT_PCI 184config IXP4XX_INDIRECT_PCI
@@ -234,8 +215,8 @@ config IXP4XX_QMGR
234 215
235config IXP4XX_NPE 216config IXP4XX_NPE
236 tristate "IXP4xx Network Processor Engine support" 217 tristate "IXP4xx Network Processor Engine support"
237 select FW_LOADER
238 select HOTPLUG 218 select HOTPLUG
219 select FW_LOADER
239 help 220 help
240 This driver supports IXP4xx built-in network coprocessors 221 This driver supports IXP4xx built-in network coprocessors
241 and is automatically selected by Ethernet and HSS drivers. 222 and is automatically selected by Ethernet and HSS drivers.
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index eded94c96dd..d807fc367dd 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -10,7 +10,6 @@ obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
10obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o 10obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
11obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o 11obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
12obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o 12obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
13obj-pci-$(CONFIG_MACH_MICCPT) += miccpt-pci.o
14obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o 13obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o
15obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o 14obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
16obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o 15obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
@@ -26,9 +25,6 @@ obj-$(CONFIG_MACH_AVILA) += avila-setup.o
26obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o 25obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
27obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o 26obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
28obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o 27obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
29obj-$(CONFIG_MACH_DEVIXP) += omixp-setup.o
30obj-$(CONFIG_MACH_MICCPT) += omixp-setup.o
31obj-$(CONFIG_MACH_MIC256) += omixp-setup.o
32obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o 28obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o
33obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o 29obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
34obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o 30obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
diff --git a/arch/arm/mach-ixp4xx/Makefile.boot b/arch/arm/mach-ixp4xx/Makefile.boot
index 9c7af91d93d..d84c5807a43 100644
--- a/arch/arm/mach-ixp4xx/Makefile.boot
+++ b/arch/arm/mach-ixp4xx/Makefile.boot
@@ -1,3 +1,3 @@
1 zreladdr-y += 0x00008000 1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3 3
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 548c7d43ade..8fea0a3c524 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -65,9 +65,10 @@ static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
65 65
66struct hw_pci avila_pci __initdata = { 66struct hw_pci avila_pci __initdata = {
67 .nr_controllers = 1, 67 .nr_controllers = 1,
68 .ops = &ixp4xx_ops,
69 .preinit = avila_pci_preinit, 68 .preinit = avila_pci_preinit,
69 .swizzle = pci_std_swizzle,
70 .setup = ixp4xx_setup, 70 .setup = ixp4xx_setup,
71 .scan = ixp4xx_scan_bus,
71 .map_irq = avila_map_irq, 72 .map_irq = avila_map_irq,
72}; 73};
73 74
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 90e42e9982c..ee19c1d383a 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -165,15 +165,13 @@ static void __init avila_init(void)
165MACHINE_START(AVILA, "Gateworks Avila Network Platform") 165MACHINE_START(AVILA, "Gateworks Avila Network Platform")
166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */ 166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
167 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
168 .init_early = ixp4xx_init_early,
169 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
170 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
171 .atag_offset = 0x100, 170 .boot_params = 0x0100,
172 .init_machine = avila_init, 171 .init_machine = avila_init,
173#if defined(CONFIG_PCI) 172#if defined(CONFIG_PCI)
174 .dma_zone_size = SZ_64M, 173 .dma_zone_size = SZ_64M,
175#endif 174#endif
176 .restart = ixp4xx_restart,
177MACHINE_END 175MACHINE_END
178 176
179 /* 177 /*
@@ -185,15 +183,13 @@ MACHINE_END
185MACHINE_START(LOFT, "Giant Shoulder Inc Loft board") 183MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
186 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */ 184 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
187 .map_io = ixp4xx_map_io, 185 .map_io = ixp4xx_map_io,
188 .init_early = ixp4xx_init_early,
189 .init_irq = ixp4xx_init_irq, 186 .init_irq = ixp4xx_init_irq,
190 .timer = &ixp4xx_timer, 187 .timer = &ixp4xx_timer,
191 .atag_offset = 0x100, 188 .boot_params = 0x0100,
192 .init_machine = avila_init, 189 .init_machine = avila_init,
193#if defined(CONFIG_PCI) 190#if defined(CONFIG_PCI)
194 .dma_zone_size = SZ_64M, 191 .dma_zone_size = SZ_64M,
195#endif 192#endif
196 .restart = ixp4xx_restart,
197MACHINE_END 193MACHINE_END
198#endif 194#endif
199 195
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 6d6bde3e15f..2131832ee6b 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -26,12 +26,12 @@
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/device.h> 27#include <linux/device.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/export.h>
30#include <asm/dma-mapping.h> 29#include <asm/dma-mapping.h>
31 30
32#include <asm/cputype.h> 31#include <asm/cputype.h>
33#include <asm/irq.h> 32#include <asm/irq.h>
34#include <asm/sizes.h> 33#include <asm/sizes.h>
34#include <asm/system.h>
35#include <asm/mach/pci.h> 35#include <asm/mach/pci.h>
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37 37
@@ -54,7 +54,7 @@ unsigned long ixp4xx_pci_reg_base = 0;
54 * these transactions are atomic or we will end up 54 * these transactions are atomic or we will end up
55 * with corrupt data on the bus or in a driver. 55 * with corrupt data on the bus or in a driver.
56 */ 56 */
57static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock); 57static DEFINE_SPINLOCK(ixp4xx_pci_lock);
58 58
59/* 59/*
60 * Read from PCI config space 60 * Read from PCI config space
@@ -62,10 +62,10 @@ static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
62static void crp_read(u32 ad_cbe, u32 *data) 62static void crp_read(u32 ad_cbe, u32 *data)
63{ 63{
64 unsigned long flags; 64 unsigned long flags;
65 raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); 65 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
66 *PCI_CRP_AD_CBE = ad_cbe; 66 *PCI_CRP_AD_CBE = ad_cbe;
67 *data = *PCI_CRP_RDATA; 67 *data = *PCI_CRP_RDATA;
68 raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 68 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
69} 69}
70 70
71/* 71/*
@@ -74,10 +74,10 @@ static void crp_read(u32 ad_cbe, u32 *data)
74static void crp_write(u32 ad_cbe, u32 data) 74static void crp_write(u32 ad_cbe, u32 data)
75{ 75{
76 unsigned long flags; 76 unsigned long flags;
77 raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); 77 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
78 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; 78 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
79 *PCI_CRP_WDATA = data; 79 *PCI_CRP_WDATA = data;
80 raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 80 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
81} 81}
82 82
83static inline int check_master_abort(void) 83static inline int check_master_abort(void)
@@ -101,7 +101,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
101 int retval = 0; 101 int retval = 0;
102 int i; 102 int i;
103 103
104 raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); 104 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
105 105
106 *PCI_NP_AD = addr; 106 *PCI_NP_AD = addr;
107 107
@@ -118,7 +118,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
118 if(check_master_abort()) 118 if(check_master_abort())
119 retval = 1; 119 retval = 1;
120 120
121 raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 121 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
122 return retval; 122 return retval;
123} 123}
124 124
@@ -127,7 +127,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
127 unsigned long flags; 127 unsigned long flags;
128 int retval = 0; 128 int retval = 0;
129 129
130 raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); 130 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
131 131
132 *PCI_NP_AD = addr; 132 *PCI_NP_AD = addr;
133 133
@@ -140,7 +140,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
140 if(check_master_abort()) 140 if(check_master_abort())
141 retval = 1; 141 retval = 1;
142 142
143 raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 143 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
144 return retval; 144 return retval;
145} 145}
146 146
@@ -149,7 +149,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
149 unsigned long flags; 149 unsigned long flags;
150 int retval = 0; 150 int retval = 0;
151 151
152 raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); 152 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
153 153
154 *PCI_NP_AD = addr; 154 *PCI_NP_AD = addr;
155 155
@@ -162,7 +162,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
162 if(check_master_abort()) 162 if(check_master_abort())
163 retval = 1; 163 retval = 1;
164 164
165 raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 165 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
166 return retval; 166 return retval;
167} 167}
168 168
@@ -397,8 +397,7 @@ void __init ixp4xx_pci_preinit(void)
397 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); 397 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
398 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); 398 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
399 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); 399 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
400 local_write_config(PCI_BASE_ADDRESS_3, 4, 400 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
401 PHYS_OFFSET + SZ_32M + SZ_16M);
402 401
403 /* 402 /*
404 * Enable CSR window at 64 MiB to allow PCI masters 403 * Enable CSR window at 64 MiB to allow PCI masters
@@ -410,7 +409,6 @@ void __init ixp4xx_pci_preinit(void)
410 * Enable the IO window to be way up high, at 0xfffffc00 409 * Enable the IO window to be way up high, at 0xfffffc00
411 */ 410 */
412 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01); 411 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
413 local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
414 } else { 412 } else {
415 printk("PCI: IXP4xx is target - No bus scan performed\n"); 413 printk("PCI: IXP4xx is target - No bus scan performed\n");
416 } 414 }
@@ -472,8 +470,9 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
472 request_resource(&ioport_resource, &res[0]); 470 request_resource(&ioport_resource, &res[0]);
473 request_resource(&iomem_resource, &res[1]); 471 request_resource(&iomem_resource, &res[1]);
474 472
475 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 473 sys->resource[0] = &res[0];
476 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 474 sys->resource[1] = &res[1];
475 sys->resource[2] = NULL;
477 476
478 platform_notify = ixp4xx_pci_platform_notify; 477 platform_notify = ixp4xx_pci_platform_notify;
479 platform_notify_remove = ixp4xx_pci_platform_notify_remove; 478 platform_notify_remove = ixp4xx_pci_platform_notify_remove;
@@ -481,6 +480,11 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
481 return 1; 480 return 1;
482} 481}
483 482
483struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
484{
485 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
486}
487
484int dma_set_coherent_mask(struct device *dev, u64 mask) 488int dma_set_coherent_mask(struct device *dev, u64 mask)
485{ 489{
486 if (mask >= SZ_64M - 1) 490 if (mask >= SZ_64M - 1)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 8c0c0e2d072..07772575d7a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -17,6 +17,7 @@
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/serial.h> 19#include <linux/serial.h>
20#include <linux/sched.h>
20#include <linux/tty.h> 21#include <linux/tty.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22#include <linux/serial_core.h> 23#include <linux/serial_core.h>
@@ -27,18 +28,14 @@
27#include <linux/clocksource.h> 28#include <linux/clocksource.h>
28#include <linux/clockchips.h> 29#include <linux/clockchips.h>
29#include <linux/io.h> 30#include <linux/io.h>
30#include <linux/export.h>
31#include <linux/gpio.h>
32 31
33#include <mach/udc.h> 32#include <mach/udc.h>
34#include <mach/hardware.h> 33#include <mach/hardware.h>
35#include <mach/io.h>
36#include <asm/uaccess.h> 34#include <asm/uaccess.h>
37#include <asm/pgtable.h> 35#include <asm/pgtable.h>
38#include <asm/page.h> 36#include <asm/page.h>
39#include <asm/irq.h> 37#include <asm/irq.h>
40#include <asm/sched_clock.h> 38#include <asm/sched_clock.h>
41#include <asm/system_misc.h>
42 39
43#include <asm/mach/map.h> 40#include <asm/mach/map.h>
44#include <asm/mach/irq.h> 41#include <asm/mach/irq.h>
@@ -53,26 +50,29 @@ static struct clock_event_device clockevent_ixp4xx;
53 *************************************************************************/ 50 *************************************************************************/
54static struct map_desc ixp4xx_io_desc[] __initdata = { 51static struct map_desc ixp4xx_io_desc[] __initdata = {
55 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ 52 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
56 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, 53 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
57 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), 54 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
58 .length = IXP4XX_PERIPHERAL_REGION_SIZE, 55 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
59 .type = MT_DEVICE 56 .type = MT_DEVICE
60 }, { /* Expansion Bus Config Registers */ 57 }, { /* Expansion Bus Config Registers */
61 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, 58 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
62 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), 59 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
63 .length = IXP4XX_EXP_CFG_REGION_SIZE, 60 .length = IXP4XX_EXP_CFG_REGION_SIZE,
64 .type = MT_DEVICE 61 .type = MT_DEVICE
65 }, { /* PCI Registers */ 62 }, { /* PCI Registers */
66 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, 63 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
67 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), 64 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
68 .length = IXP4XX_PCI_CFG_REGION_SIZE, 65 .length = IXP4XX_PCI_CFG_REGION_SIZE,
69 .type = MT_DEVICE 66 .type = MT_DEVICE
70 }, { /* Queue Manager */
71 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
72 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
73 .length = IXP4XX_QMGR_REGION_SIZE,
74 .type = MT_DEVICE
75 }, 67 },
68#ifdef CONFIG_DEBUG_LL
69 { /* Debug UART mapping */
70 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
71 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
72 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
73 .type = MT_DEVICE
74 }
75#endif
76}; 76};
77 77
78void __init ixp4xx_map_io(void) 78void __init ixp4xx_map_io(void)
@@ -105,7 +105,7 @@ static signed char irq2gpio[32] = {
105 7, 8, 9, 10, 11, 12, -1, -1, 105 7, 8, 9, 10, 11, 12, -1, -1,
106}; 106};
107 107
108static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 108int gpio_to_irq(int gpio)
109{ 109{
110 int irq; 110 int irq;
111 111
@@ -115,6 +115,7 @@ static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
115 } 115 }
116 return -EINVAL; 116 return -EINVAL;
117} 117}
118EXPORT_SYMBOL(gpio_to_irq);
118 119
119int irq_to_gpio(unsigned int irq) 120int irq_to_gpio(unsigned int irq)
120{ 121{
@@ -235,12 +236,6 @@ void __init ixp4xx_init_irq(void)
235{ 236{
236 int i = 0; 237 int i = 0;
237 238
238 /*
239 * ixp4xx does not implement the XScale PWRMODE register
240 * so it must not call cpu_do_idle().
241 */
242 disable_hlt();
243
244 /* Route all sources to IRQ instead of FIQ */ 239 /* Route all sources to IRQ instead of FIQ */
245 *IXP4XX_ICLR = 0x0; 240 *IXP4XX_ICLR = 0x0;
246 241
@@ -380,56 +375,12 @@ static struct platform_device *ixp46x_devices[] __initdata = {
380unsigned long ixp4xx_exp_bus_size; 375unsigned long ixp4xx_exp_bus_size;
381EXPORT_SYMBOL(ixp4xx_exp_bus_size); 376EXPORT_SYMBOL(ixp4xx_exp_bus_size);
382 377
383static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
384{
385 gpio_line_config(gpio, IXP4XX_GPIO_IN);
386
387 return 0;
388}
389
390static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
391 int level)
392{
393 gpio_line_set(gpio, level);
394 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
395
396 return 0;
397}
398
399static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
400{
401 int value;
402
403 gpio_line_get(gpio, &value);
404
405 return value;
406}
407
408static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
409 int value)
410{
411 gpio_line_set(gpio, value);
412}
413
414static struct gpio_chip ixp4xx_gpio_chip = {
415 .label = "IXP4XX_GPIO_CHIP",
416 .direction_input = ixp4xx_gpio_direction_input,
417 .direction_output = ixp4xx_gpio_direction_output,
418 .get = ixp4xx_gpio_get_value,
419 .set = ixp4xx_gpio_set_value,
420 .to_irq = ixp4xx_gpio_to_irq,
421 .base = 0,
422 .ngpio = 16,
423};
424
425void __init ixp4xx_sys_init(void) 378void __init ixp4xx_sys_init(void)
426{ 379{
427 ixp4xx_exp_bus_size = SZ_16M; 380 ixp4xx_exp_bus_size = SZ_16M;
428 381
429 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); 382 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
430 383
431 gpiochip_add(&ixp4xx_gpio_chip);
432
433 if (cpu_is_ixp46x()) { 384 if (cpu_is_ixp46x()) {
434 int region; 385 int region;
435 386
@@ -451,9 +402,18 @@ void __init ixp4xx_sys_init(void)
451/* 402/*
452 * sched_clock() 403 * sched_clock()
453 */ 404 */
454static u32 notrace ixp4xx_read_sched_clock(void) 405static DEFINE_CLOCK_DATA(cd);
406
407unsigned long long notrace sched_clock(void)
455{ 408{
456 return *IXP4XX_OSTS; 409 u32 cyc = *IXP4XX_OSTS;
410 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
411}
412
413static void notrace ixp4xx_update_sched_clock(void)
414{
415 u32 cyc = *IXP4XX_OSTS;
416 update_sched_clock(&cd, cyc, (u32)~0);
457} 417}
458 418
459/* 419/*
@@ -469,7 +429,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
469EXPORT_SYMBOL(ixp4xx_timer_freq); 429EXPORT_SYMBOL(ixp4xx_timer_freq);
470static void __init ixp4xx_clocksource_init(void) 430static void __init ixp4xx_clocksource_init(void)
471{ 431{
472 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); 432 init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
473 433
474 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, 434 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
475 ixp4xx_clocksource_read); 435 ixp4xx_clocksource_read);
@@ -540,55 +500,3 @@ static void __init ixp4xx_clockevent_init(void)
540 500
541 clockevents_register_device(&clockevent_ixp4xx); 501 clockevents_register_device(&clockevent_ixp4xx);
542} 502}
543
544void ixp4xx_restart(char mode, const char *cmd)
545{
546 if ( 1 && mode == 's') {
547 /* Jump into ROM at address 0 */
548 soft_restart(0);
549 } else {
550 /* Use on-chip reset capability */
551
552 /* set the "key" register to enable access to
553 * "timer" and "enable" registers
554 */
555 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
556
557 /* write 0 to the timer register for an immediate reset */
558 *IXP4XX_OSWT = 0;
559
560 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
561 }
562}
563
564#ifdef CONFIG_IXP4XX_INDIRECT_PCI
565/*
566 * In the case of using indirect PCI, we simply return the actual PCI
567 * address and our read/write implementation use that to drive the
568 * access registers. If something outside of PCI is ioremap'd, we
569 * fallback to the default.
570 */
571
572static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
573 unsigned int mtype, void *caller)
574{
575 if (!is_pci_memory(addr))
576 return __arm_ioremap_caller(addr, size, mtype, caller);
577
578 return (void __iomem *)addr;
579}
580
581static void ixp4xx_iounmap(void __iomem *addr)
582{
583 if (!is_pci_memory((__force u32)addr))
584 __iounmap(addr);
585}
586
587void __init ixp4xx_init_early(void)
588{
589 arch_ioremap_caller = ixp4xx_ioremap_caller;
590 arch_iounmap = ixp4xx_iounmap;
591}
592#else
593void __init ixp4xx_init_early(void) {}
594#endif
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index 5d14ce2aee6..71f5c9c60fc 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -48,9 +48,10 @@ static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
48 48
49struct hw_pci coyote_pci __initdata = { 49struct hw_pci coyote_pci __initdata = {
50 .nr_controllers = 1, 50 .nr_controllers = 1,
51 .ops = &ixp4xx_ops,
52 .preinit = coyote_pci_preinit, 51 .preinit = coyote_pci_preinit,
52 .swizzle = pci_std_swizzle,
53 .setup = ixp4xx_setup, 53 .setup = ixp4xx_setup,
54 .scan = ixp4xx_scan_bus,
54 .map_irq = coyote_map_irq, 55 .map_irq = coyote_map_irq,
55}; 56};
56 57
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 1b83110028d..e24564b5d93 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -110,15 +110,13 @@ static void __init coyote_init(void)
110MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") 110MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
111 /* Maintainer: MontaVista Software, Inc. */ 111 /* Maintainer: MontaVista Software, Inc. */
112 .map_io = ixp4xx_map_io, 112 .map_io = ixp4xx_map_io,
113 .init_early = ixp4xx_init_early,
114 .init_irq = ixp4xx_init_irq, 113 .init_irq = ixp4xx_init_irq,
115 .timer = &ixp4xx_timer, 114 .timer = &ixp4xx_timer,
116 .atag_offset = 0x100, 115 .boot_params = 0x0100,
117 .init_machine = coyote_init, 116 .init_machine = coyote_init,
118#if defined(CONFIG_PCI) 117#if defined(CONFIG_PCI)
119 .dma_zone_size = SZ_64M, 118 .dma_zone_size = SZ_64M,
120#endif 119#endif
121 .restart = ixp4xx_restart,
122MACHINE_END 120MACHINE_END
123#endif 121#endif
124 122
@@ -130,12 +128,10 @@ MACHINE_END
130MACHINE_START(IXDPG425, "Intel IXDPG425") 128MACHINE_START(IXDPG425, "Intel IXDPG425")
131 /* Maintainer: MontaVista Software, Inc. */ 129 /* Maintainer: MontaVista Software, Inc. */
132 .map_io = ixp4xx_map_io, 130 .map_io = ixp4xx_map_io,
133 .init_early = ixp4xx_init_early,
134 .init_irq = ixp4xx_init_irq, 131 .init_irq = ixp4xx_init_irq,
135 .timer = &ixp4xx_timer, 132 .timer = &ixp4xx_timer,
136 .atag_offset = 0x100, 133 .boot_params = 0x0100,
137 .init_machine = coyote_init, 134 .init_machine = coyote_init,
138 .restart = ixp4xx_restart,
139MACHINE_END 135MACHINE_END
140#endif 136#endif
141 137
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index 8dca7693772..0532510b5e8 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -62,9 +62,10 @@ static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
62 62
63struct hw_pci __initdata dsmg600_pci = { 63struct hw_pci __initdata dsmg600_pci = {
64 .nr_controllers = 1, 64 .nr_controllers = 1,
65 .ops = &ixp4xx_ops,
66 .preinit = dsmg600_pci_preinit, 65 .preinit = dsmg600_pci_preinit,
66 .swizzle = pci_std_swizzle,
67 .setup = ixp4xx_setup, 67 .setup = ixp4xx_setup,
68 .scan = ixp4xx_scan_bus,
68 .map_irq = dsmg600_map_irq, 69 .map_irq = dsmg600_map_irq,
69}; 70};
70 71
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 97a0af8f195..03e54515e8b 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -16,7 +16,7 @@
16 * Author: Rod Whitby <rod@whitby.id.au> 16 * Author: Rod Whitby <rod@whitby.id.au>
17 * Maintainers: http://www.nslu2-linux.org/ 17 * Maintainers: http://www.nslu2-linux.org/
18 */ 18 */
19#include <linux/gpio.h> 19
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/jiffies.h> 21#include <linux/jiffies.h>
22#include <linux/timer.h> 22#include <linux/timer.h>
@@ -31,6 +31,7 @@
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32#include <asm/mach/flash.h> 32#include <asm/mach/flash.h>
33#include <asm/mach/time.h> 33#include <asm/mach/time.h>
34#include <asm/gpio.h>
34 35
35#define DSMG600_SDA_PIN 5 36#define DSMG600_SDA_PIN 5
36#define DSMG600_SCL_PIN 4 37#define DSMG600_SCL_PIN 4
@@ -278,14 +279,12 @@ static void __init dsmg600_init(void)
278 279
279MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") 280MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
280 /* Maintainer: www.nslu2-linux.org */ 281 /* Maintainer: www.nslu2-linux.org */
281 .atag_offset = 0x100, 282 .boot_params = 0x00000100,
282 .map_io = ixp4xx_map_io, 283 .map_io = ixp4xx_map_io,
283 .init_early = ixp4xx_init_early,
284 .init_irq = ixp4xx_init_irq, 284 .init_irq = ixp4xx_init_irq,
285 .timer = &dsmg600_timer, 285 .timer = &dsmg600_timer,
286 .init_machine = dsmg600_init, 286 .init_machine = dsmg600_init,
287#if defined(CONFIG_PCI) 287#if defined(CONFIG_PCI)
288 .dma_zone_size = SZ_64M, 288 .dma_zone_size = SZ_64M,
289#endif 289#endif
290 .restart = ixp4xx_restart,
291MACHINE_END 290MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index fd4a8625b4a..d2ac803328f 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -59,9 +59,10 @@ static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
59 59
60struct hw_pci fsg_pci __initdata = { 60struct hw_pci fsg_pci __initdata = {
61 .nr_controllers = 1, 61 .nr_controllers = 1,
62 .ops = &ixp4xx_ops,
63 .preinit = fsg_pci_preinit, 62 .preinit = fsg_pci_preinit,
63 .swizzle = pci_std_swizzle,
64 .setup = ixp4xx_setup, 64 .setup = ixp4xx_setup,
65 .scan = ixp4xx_scan_bus,
65 .map_irq = fsg_map_irq, 66 .map_irq = fsg_map_irq,
66}; 67};
67 68
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 9175a25a751..23a8b361456 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -14,7 +14,7 @@
14 * Maintainers: http://www.nslu2-linux.org/ 14 * Maintainers: http://www.nslu2-linux.org/
15 * 15 *
16 */ 16 */
17#include <linux/gpio.h> 17
18#include <linux/if_ether.h> 18#include <linux/if_ether.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/serial.h> 20#include <linux/serial.h>
@@ -27,6 +27,7 @@
27#include <asm/mach-types.h> 27#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30#include <asm/gpio.h>
30 31
31#define FSG_SDA_PIN 12 32#define FSG_SDA_PIN 12
32#define FSG_SCL_PIN 13 33#define FSG_SCL_PIN 13
@@ -270,14 +271,12 @@ static void __init fsg_init(void)
270MACHINE_START(FSG, "Freecom FSG-3") 271MACHINE_START(FSG, "Freecom FSG-3")
271 /* Maintainer: www.nslu2-linux.org */ 272 /* Maintainer: www.nslu2-linux.org */
272 .map_io = ixp4xx_map_io, 273 .map_io = ixp4xx_map_io,
273 .init_early = ixp4xx_init_early,
274 .init_irq = ixp4xx_init_irq, 274 .init_irq = ixp4xx_init_irq,
275 .timer = &ixp4xx_timer, 275 .timer = &ixp4xx_timer,
276 .atag_offset = 0x100, 276 .boot_params = 0x0100,
277 .init_machine = fsg_init, 277 .init_machine = fsg_init,
278#if defined(CONFIG_PCI) 278#if defined(CONFIG_PCI)
279 .dma_zone_size = SZ_64M, 279 .dma_zone_size = SZ_64M,
280#endif 280#endif
281 .restart = ixp4xx_restart,
282MACHINE_END 281MACHINE_END
283 282
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index d9d6cc08970..76581fb467c 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -47,9 +47,10 @@ static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot,
47 47
48struct hw_pci gateway7001_pci __initdata = { 48struct hw_pci gateway7001_pci __initdata = {
49 .nr_controllers = 1, 49 .nr_controllers = 1,
50 .ops = &ixp4xx_ops,
51 .preinit = gateway7001_pci_preinit, 50 .preinit = gateway7001_pci_preinit,
51 .swizzle = pci_std_swizzle,
52 .setup = ixp4xx_setup, 52 .setup = ixp4xx_setup,
53 .scan = ixp4xx_scan_bus,
53 .map_irq = gateway7001_map_irq, 54 .map_irq = gateway7001_map_irq,
54}; 55};
55 56
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 033c7175895..d4f851bdd9a 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -97,14 +97,12 @@ static void __init gateway7001_init(void)
97MACHINE_START(GATEWAY7001, "Gateway 7001 AP") 97MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
98 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 98 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
99 .map_io = ixp4xx_map_io, 99 .map_io = ixp4xx_map_io,
100 .init_early = ixp4xx_init_early,
101 .init_irq = ixp4xx_init_irq, 100 .init_irq = ixp4xx_init_irq,
102 .timer = &ixp4xx_timer, 101 .timer = &ixp4xx_timer,
103 .atag_offset = 0x100, 102 .boot_params = 0x0100,
104 .init_machine = gateway7001_init, 103 .init_machine = gateway7001_init,
105#if defined(CONFIG_PCI) 104#if defined(CONFIG_PCI)
106 .dma_zone_size = SZ_64M, 105 .dma_zone_size = SZ_64M,
107#endif 106#endif
108 .restart = ixp4xx_restart,
109MACHINE_END 107MACHINE_END
110#endif 108#endif
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 53b8348dfcc..7548d9a2efe 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -12,10 +12,10 @@
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15#include <asm/system.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
16#include <asm/mach/flash.h> 17#include <asm/mach/flash.h>
17#include <asm/mach/pci.h> 18#include <asm/mach/pci.h>
18#include <asm/system_info.h>
19 19
20#define SLOT_ETHA 0x0B /* IDSEL = AD21 */ 20#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
21#define SLOT_ETHB 0x0C /* IDSEL = AD20 */ 21#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
@@ -330,7 +330,7 @@ static struct platform_device device_hss_tab[] = {
330}; 330};
331 331
332 332
333static struct platform_device *device_tab[7] __initdata = { 333static struct platform_device *device_tab[6] __initdata = {
334 &device_flash, /* index 0 */ 334 &device_flash, /* index 0 */
335}; 335};
336 336
@@ -474,10 +474,11 @@ static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
474 474
475static struct hw_pci gmlr_hw_pci __initdata = { 475static struct hw_pci gmlr_hw_pci __initdata = {
476 .nr_controllers = 1, 476 .nr_controllers = 1,
477 .ops = &ixp4xx_ops,
478 .preinit = gmlr_pci_preinit, 477 .preinit = gmlr_pci_preinit,
479 .postinit = gmlr_pci_postinit, 478 .postinit = gmlr_pci_postinit,
479 .swizzle = pci_std_swizzle,
480 .setup = ixp4xx_setup, 480 .setup = ixp4xx_setup,
481 .scan = ixp4xx_scan_bus,
481 .map_irq = gmlr_map_irq, 482 .map_irq = gmlr_map_irq,
482}; 483};
483 484
@@ -496,13 +497,11 @@ subsys_initcall(gmlr_pci_init);
496MACHINE_START(GORAMO_MLR, "MultiLink") 497MACHINE_START(GORAMO_MLR, "MultiLink")
497 /* Maintainer: Krzysztof Halasa */ 498 /* Maintainer: Krzysztof Halasa */
498 .map_io = ixp4xx_map_io, 499 .map_io = ixp4xx_map_io,
499 .init_early = ixp4xx_init_early,
500 .init_irq = ixp4xx_init_irq, 500 .init_irq = ixp4xx_init_irq,
501 .timer = &ixp4xx_timer, 501 .timer = &ixp4xx_timer,
502 .atag_offset = 0x100, 502 .boot_params = 0x0100,
503 .init_machine = gmlr_init, 503 .init_machine = gmlr_init,
504#if defined(CONFIG_PCI) 504#if defined(CONFIG_PCI)
505 .dma_zone_size = SZ_64M, 505 .dma_zone_size = SZ_64M,
506#endif 506#endif
507 .restart = ixp4xx_restart,
508MACHINE_END 507MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 551d114c9e1..d68fc068c38 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -67,9 +67,10 @@ static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
67 67
68struct hw_pci gtwx5715_pci __initdata = { 68struct hw_pci gtwx5715_pci __initdata = {
69 .nr_controllers = 1, 69 .nr_controllers = 1,
70 .ops = &ixp4xx_ops,
71 .preinit = gtwx5715_pci_preinit, 70 .preinit = gtwx5715_pci_preinit,
71 .swizzle = pci_std_swizzle,
72 .setup = ixp4xx_setup, 72 .setup = ixp4xx_setup,
73 .scan = ixp4xx_scan_bus,
73 .map_irq = gtwx5715_map_irq, 74 .map_irq = gtwx5715_map_irq,
74}; 75};
75 76
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 18ebc6be796..3790dffd3c3 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -165,15 +165,13 @@ static void __init gtwx5715_init(void)
165MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") 165MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
166 /* Maintainer: George Joseph */ 166 /* Maintainer: George Joseph */
167 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
168 .init_early = ixp4xx_init_early,
169 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
170 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
171 .atag_offset = 0x100, 170 .boot_params = 0x0100,
172 .init_machine = gtwx5715_init, 171 .init_machine = gtwx5715_init,
173#if defined(CONFIG_PCI) 172#if defined(CONFIG_PCI)
174 .dma_zone_size = SZ_64M, 173 .dma_zone_size = SZ_64M,
175#endif 174#endif
176 .restart = ixp4xx_restart,
177MACHINE_END 175MACHINE_END
178 176
179 177
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index ebc0ba31ce8..b2ef65db0e9 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,7 +14,6 @@
14#ifndef __ASM_ARCH_CPU_H__ 14#ifndef __ASM_ARCH_CPU_H__
15#define __ASM_ARCH_CPU_H__ 15#define __ASM_ARCH_CPU_H__
16 16
17#include <linux/io.h>
18#include <asm/cputype.h> 17#include <asm/cputype.h>
19 18
20/* Processor id value in CP15 Register 0 */ 19/* Processor id value in CP15 Register 0 */
@@ -38,7 +37,7 @@
38 37
39static inline u32 ixp4xx_read_feature_bits(void) 38static inline u32 ixp4xx_read_feature_bits(void)
40{ 39{
41 u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); 40 u32 val = ~*IXP4XX_EXP_CFG2;
42 41
43 if (cpu_is_ixp42x_rev_a0()) 42 if (cpu_is_ixp42x_rev_a0())
44 return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | 43 return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@@ -52,7 +51,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
52 51
53static inline void ixp4xx_write_feature_bits(u32 value) 52static inline void ixp4xx_write_feature_bits(u32 value)
54{ 53{
55 __raw_writel(~value, IXP4XX_EXP_CFG2); 54 *IXP4XX_EXP_CFG2 = ~value;
56} 55}
57 56
58#endif /* _ASM_ARCH_CPU_H */ 57#endif /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index ff686cbc5df..b974a49c0af 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -10,15 +10,15 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13 .macro addruart, rp, rv, tmp 13 .macro addruart, rp, rv
14#ifdef __ARMEB__ 14#ifdef __ARMEB__
15 mov \rp, #3 @ Uart regs are at off set of 3 if 15 mov \rp, #3 @ Uart regs are at off set of 3 if
16 @ byte writes used - Big Endian. 16 @ byte writes used - Big Endian.
17#else 17#else
18 mov \rp, #0 18 mov \rp, #0
19#endif 19#endif
20 orr \rv, \rp, #0xfe000000 @ virtual 20 orr \rv, \rp, #0xff000000 @ virtual
21 orr \rv, \rv, #0x00f00000 21 orr \rv, \rv, #0x00b00000
22 orr \rp, \rp, #0xc8000000 @ physical 22 orr \rp, \rp, #0xc8000000 @ physical
23 .endm 23 .endm
24 24
diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
index 79adf83e2c3..f2e14e94ed1 100644
--- a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
@@ -9,9 +9,15 @@
9 */ 9 */
10#include <mach/hardware.h> 10#include <mach/hardware.h>
11 11
12 .macro disable_fiq
13 .endm
14
12 .macro get_irqnr_preamble, base, tmp 15 .macro get_irqnr_preamble, base, tmp
13 .endm 16 .endm
14 17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) 22 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
17 ldr \irqstat, [\irqstat] @ get interrupts 23 ldr \irqstat, [\irqstat] @ get interrupts
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index 034bb2a1b80..c30e7e923a7 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -23,6 +23,8 @@
23#define PCIBIOS_MAX_MEM 0x4BFFFFFF 23#define PCIBIOS_MAX_MEM 0x4BFFFFFF
24#endif 24#endif
25 25
26#define ARCH_HAS_DMA_SET_COHERENT_MASK
27
26/* Register locations and bits */ 28/* Register locations and bits */
27#include "ixp4xx-regs.h" 29#include "ixp4xx-regs.h"
28 30
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 5cf30d1b78d..57b5410c31f 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -17,6 +17,8 @@
17 17
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19 19
20#define IO_SPACE_LIMIT 0x0000ffff
21
20extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); 22extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
21extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); 23extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
22 24
@@ -39,7 +41,11 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
39 * but in some cases the performance hit is acceptable. In addition, you 41 * but in some cases the performance hit is acceptable. In addition, you
40 * cannot mmap() PCI devices in this case. 42 * cannot mmap() PCI devices in this case.
41 */ 43 */
42#ifdef CONFIG_IXP4XX_INDIRECT_PCI 44#ifndef CONFIG_IXP4XX_INDIRECT_PCI
45
46#define __mem_pci(a) (a)
47
48#else
43 49
44/* 50/*
45 * In the case of using indirect PCI, we simply return the actual PCI 51 * In the case of using indirect PCI, we simply return the actual PCI
@@ -53,6 +59,24 @@ static inline int is_pci_memory(u32 addr)
53 return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF); 59 return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
54} 60}
55 61
62static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
63 unsigned int mtype)
64{
65 if (!is_pci_memory(addr))
66 return __arm_ioremap(addr, size, mtype);
67
68 return (void __iomem *)addr;
69}
70
71static inline void __indirect_iounmap(void __iomem *addr)
72{
73 if (!is_pci_memory((__force u32)addr))
74 __iounmap(addr);
75}
76
77#define __arch_ioremap __indirect_ioremap
78#define __arch_iounmap __indirect_iounmap
79
56#define writeb(v, p) __indirect_writeb(v, p) 80#define writeb(v, p) __indirect_writeb(v, p)
57#define writew(v, p) __indirect_writew(v, p) 81#define writew(v, p) __indirect_writew(v, p)
58#define writel(v, p) __indirect_writel(v, p) 82#define writel(v, p) __indirect_writel(v, p)
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
index cf03614d250..292d55ed211 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -75,7 +75,4 @@ struct ixp46x_ts_regs {
75#define TX_SNAPSHOT_LOCKED (1<<0) 75#define TX_SNAPSHOT_LOCKED (1<<0)
76#define RX_SNAPSHOT_LOCKED (1<<1) 76#define RX_SNAPSHOT_LOCKED (1<<1)
77 77
78/* The ptp_ixp46x module will set this variable */
79extern int ixp46x_phc_index;
80
81#endif 78#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index c5bae9c035d..97c530f66e7 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -30,43 +30,51 @@
30 * 30 *
31 * 0x50000000 0x10000000 ioremap'd EXP BUS 31 * 0x50000000 0x10000000 ioremap'd EXP BUS
32 * 32 *
33 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals 33 * 0x6000000 0x00004000 ioremap'd QMgr
34 * 34 *
35 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG 35 * 0xC0000000 0x00001000 0xffbff000 PCI CFG
36 * 36 *
37 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG 37 * 0xC4000000 0x00001000 0xffbfe000 EXP CFG
38 * 38 *
39 * 0x60000000 0x00004000 0xFEF15000 QMgr 39 * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
40 */ 40 */
41 41
42/* 42/*
43 * Queue Manager 43 * Queue Manager
44 */ 44 */
45#define IXP4XX_QMGR_BASE_PHYS 0x60000000 45#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
46#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000) 46#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
47#define IXP4XX_QMGR_REGION_SIZE 0x00004000
48 47
49/* 48/*
50 * Peripheral space, including debug UART. Must be section-aligned so that 49 * Expansion BUS Configuration registers
51 * it can be used with the low-level debug code.
52 */ 50 */
53#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 51#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
54#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) 52#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
55#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 53#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
56 54
57/* 55/*
58 * PCI Config registers 56 * PCI Config registers
59 */ 57 */
60#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 58#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
61#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) 59#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
62#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 60#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
63 61
64/* 62/*
65 * Expansion BUS Configuration registers 63 * Peripheral space
64 */
65#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
66#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
67#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
68
69/*
70 * Debug UART
71 *
72 * This is basically a remap of UART1 into a region that is section
73 * aligned so that it * can be used with the low-level debug code.
66 */ 74 */
67#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 75#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
68#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 76#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
69#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 77#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
70 78
71#define IXP4XX_EXP_CS0_OFFSET 0x00 79#define IXP4XX_EXP_CS0_OFFSET 0x00
72#define IXP4XX_EXP_CS1_OFFSET 0x04 80#define IXP4XX_EXP_CS1_OFFSET 0x04
@@ -84,7 +92,7 @@
84/* 92/*
85 * Expansion Bus Controller registers. 93 * Expansion Bus Controller registers.
86 */ 94 */
87#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) 95#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
88 96
89#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) 97#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
90#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) 98#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index 5bce94aacca..e824c02c825 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -121,16 +121,14 @@ extern unsigned long ixp4xx_timer_freq;
121 * Functions used by platform-level setup code 121 * Functions used by platform-level setup code
122 */ 122 */
123extern void ixp4xx_map_io(void); 123extern void ixp4xx_map_io(void);
124extern void ixp4xx_init_early(void);
125extern void ixp4xx_init_irq(void); 124extern void ixp4xx_init_irq(void);
126extern void ixp4xx_sys_init(void); 125extern void ixp4xx_sys_init(void);
127extern void ixp4xx_timer_init(void); 126extern void ixp4xx_timer_init(void);
128extern struct sys_timer ixp4xx_timer; 127extern struct sys_timer ixp4xx_timer;
129extern void ixp4xx_restart(char, const char *);
130extern void ixp4xx_pci_preinit(void); 128extern void ixp4xx_pci_preinit(void);
131struct pci_sys_data; 129struct pci_sys_data;
132extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); 130extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
133extern struct pci_ops ixp4xx_ops; 131extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
134 132
135/* 133/*
136 * GPIO-functions 134 * GPIO-functions
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
index 4de8da536db..9e7cad2d54c 100644
--- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
@@ -86,7 +86,7 @@ void qmgr_release_queue(unsigned int queue);
86 86
87static inline void qmgr_put_entry(unsigned int queue, u32 val) 87static inline void qmgr_put_entry(unsigned int queue, u32 val)
88{ 88{
89 struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 89 extern struct qmgr_regs __iomem *qmgr_regs;
90#if DEBUG_QMGR 90#if DEBUG_QMGR
91 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ 91 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
92 92
@@ -99,7 +99,7 @@ static inline void qmgr_put_entry(unsigned int queue, u32 val)
99static inline u32 qmgr_get_entry(unsigned int queue) 99static inline u32 qmgr_get_entry(unsigned int queue)
100{ 100{
101 u32 val; 101 u32 val;
102 const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 102 extern struct qmgr_regs __iomem *qmgr_regs;
103 val = __raw_readl(&qmgr_regs->acc[queue][0]); 103 val = __raw_readl(&qmgr_regs->acc[queue][0]);
104#if DEBUG_QMGR 104#if DEBUG_QMGR
105 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ 105 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
@@ -112,14 +112,14 @@ static inline u32 qmgr_get_entry(unsigned int queue)
112 112
113static inline int __qmgr_get_stat1(unsigned int queue) 113static inline int __qmgr_get_stat1(unsigned int queue)
114{ 114{
115 const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 115 extern struct qmgr_regs __iomem *qmgr_regs;
116 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) 116 return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
117 >> ((queue & 7) << 2)) & 0xF; 117 >> ((queue & 7) << 2)) & 0xF;
118} 118}
119 119
120static inline int __qmgr_get_stat2(unsigned int queue) 120static inline int __qmgr_get_stat2(unsigned int queue)
121{ 121{
122 const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 122 extern struct qmgr_regs __iomem *qmgr_regs;
123 BUG_ON(queue >= HALF_QUEUES); 123 BUG_ON(queue >= HALF_QUEUES);
124 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) 124 return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
125 >> ((queue & 0xF) << 1)) & 0x3; 125 >> ((queue & 0xF) << 1)) & 0x3;
@@ -145,7 +145,7 @@ static inline int qmgr_stat_empty(unsigned int queue)
145 */ 145 */
146static inline int qmgr_stat_below_low_watermark(unsigned int queue) 146static inline int qmgr_stat_below_low_watermark(unsigned int queue)
147{ 147{
148 const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 148 extern struct qmgr_regs __iomem *qmgr_regs;
149 if (queue >= HALF_QUEUES) 149 if (queue >= HALF_QUEUES)
150 return (__raw_readl(&qmgr_regs->statne_h) >> 150 return (__raw_readl(&qmgr_regs->statne_h) >>
151 (queue - HALF_QUEUES)) & 0x01; 151 (queue - HALF_QUEUES)) & 0x01;
@@ -172,7 +172,7 @@ static inline int qmgr_stat_above_high_watermark(unsigned int queue)
172 */ 172 */
173static inline int qmgr_stat_full(unsigned int queue) 173static inline int qmgr_stat_full(unsigned int queue)
174{ 174{
175 const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 175 extern struct qmgr_regs __iomem *qmgr_regs;
176 if (queue >= HALF_QUEUES) 176 if (queue >= HALF_QUEUES)
177 return (__raw_readl(&qmgr_regs->statf_h) >> 177 return (__raw_readl(&qmgr_regs->statf_h) >>
178 (queue - HALF_QUEUES)) & 0x01; 178 (queue - HALF_QUEUES)) & 0x01;
diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h
index 7bd8b96c884..80d6da2eafa 100644
--- a/arch/arm/mach-ixp4xx/include/mach/udc.h
+++ b/arch/arm/mach-ixp4xx/include/mach/udc.h
@@ -2,7 +2,7 @@
2 * arch/arm/mach-ixp4xx/include/mach/udc.h 2 * arch/arm/mach-ixp4xx/include/mach/udc.h
3 * 3 *
4 */ 4 */
5#include <linux/platform_data/pxa2xx_udc.h> 5#include <asm/mach/udc_pxa2xx.h>
6 6
7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); 7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
8 8
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index eb945a926d0..219d7c1dcdb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -41,8 +41,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
41 * Some boards are using UART2 as console 41 * Some boards are using UART2 as console
42 */ 42 */
43 if (machine_is_adi_coyote() || machine_is_gtwx5715() || 43 if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
44 machine_is_gateway7001() || machine_is_wg302v2() || 44 machine_is_gateway7001() || machine_is_wg302v2())
45 machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
46 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; 45 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
47 else 46 else
48 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; 47 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 318424dd3c5..fffd8c5e40b 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -60,9 +60,10 @@ static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
60 60
61struct hw_pci ixdp425_pci __initdata = { 61struct hw_pci ixdp425_pci __initdata = {
62 .nr_controllers = 1, 62 .nr_controllers = 1,
63 .ops = &ixp4xx_ops,
64 .preinit = ixdp425_pci_preinit, 63 .preinit = ixdp425_pci_preinit,
64 .swizzle = pci_std_swizzle,
65 .setup = ixp4xx_setup, 65 .setup = ixp4xx_setup,
66 .scan = ixp4xx_scan_bus,
66 .map_irq = ixdp425_map_irq, 67 .map_irq = ixdp425_map_irq,
67}; 68};
68 69
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 108a9d3f382..6a2927956bf 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -60,6 +60,8 @@ static struct platform_device ixdp425_flash = {
60#if defined(CONFIG_MTD_NAND_PLATFORM) || \ 60#if defined(CONFIG_MTD_NAND_PLATFORM) || \
61 defined(CONFIG_MTD_NAND_PLATFORM_MODULE) 61 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
62 62
63const char *part_probes[] = { "cmdlinepart", NULL };
64
63static struct mtd_partition ixdp425_partitions[] = { 65static struct mtd_partition ixdp425_partitions[] = {
64 { 66 {
65 .name = "ixp400 NAND FS 0", 67 .name = "ixp400 NAND FS 0",
@@ -98,6 +100,8 @@ static struct platform_nand_data ixdp425_flash_nand_data = {
98 .chip = { 100 .chip = {
99 .nr_chips = 1, 101 .nr_chips = 1,
100 .chip_delay = 30, 102 .chip_delay = 30,
103 .options = NAND_NO_AUTOINCR,
104 .part_probe_types = part_probes,
101 .partitions = ixdp425_partitions, 105 .partitions = ixdp425_partitions,
102 .nr_partitions = ARRAY_SIZE(ixdp425_partitions), 106 .nr_partitions = ARRAY_SIZE(ixdp425_partitions),
103 }, 107 },
@@ -250,15 +254,13 @@ static void __init ixdp425_init(void)
250MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") 254MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
251 /* Maintainer: MontaVista Software, Inc. */ 255 /* Maintainer: MontaVista Software, Inc. */
252 .map_io = ixp4xx_map_io, 256 .map_io = ixp4xx_map_io,
253 .init_early = ixp4xx_init_early,
254 .init_irq = ixp4xx_init_irq, 257 .init_irq = ixp4xx_init_irq,
255 .timer = &ixp4xx_timer, 258 .timer = &ixp4xx_timer,
256 .atag_offset = 0x100, 259 .boot_params = 0x0100,
257 .init_machine = ixdp425_init, 260 .init_machine = ixdp425_init,
258#if defined(CONFIG_PCI) 261#if defined(CONFIG_PCI)
259 .dma_zone_size = SZ_64M, 262 .dma_zone_size = SZ_64M,
260#endif 263#endif
261 .restart = ixp4xx_restart,
262MACHINE_END 264MACHINE_END
263#endif 265#endif
264 266
@@ -266,10 +268,9 @@ MACHINE_END
266MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") 268MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
267 /* Maintainer: MontaVista Software, Inc. */ 269 /* Maintainer: MontaVista Software, Inc. */
268 .map_io = ixp4xx_map_io, 270 .map_io = ixp4xx_map_io,
269 .init_early = ixp4xx_init_early,
270 .init_irq = ixp4xx_init_irq, 271 .init_irq = ixp4xx_init_irq,
271 .timer = &ixp4xx_timer, 272 .timer = &ixp4xx_timer,
272 .atag_offset = 0x100, 273 .boot_params = 0x0100,
273 .init_machine = ixdp425_init, 274 .init_machine = ixdp425_init,
274#if defined(CONFIG_PCI) 275#if defined(CONFIG_PCI)
275 .dma_zone_size = SZ_64M, 276 .dma_zone_size = SZ_64M,
@@ -281,10 +282,9 @@ MACHINE_END
281MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") 282MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
282 /* Maintainer: MontaVista Software, Inc. */ 283 /* Maintainer: MontaVista Software, Inc. */
283 .map_io = ixp4xx_map_io, 284 .map_io = ixp4xx_map_io,
284 .init_early = ixp4xx_init_early,
285 .init_irq = ixp4xx_init_irq, 285 .init_irq = ixp4xx_init_irq,
286 .timer = &ixp4xx_timer, 286 .timer = &ixp4xx_timer,
287 .atag_offset = 0x100, 287 .boot_params = 0x0100,
288 .init_machine = ixdp425_init, 288 .init_machine = ixdp425_init,
289#if defined(CONFIG_PCI) 289#if defined(CONFIG_PCI)
290 .dma_zone_size = SZ_64M, 290 .dma_zone_size = SZ_64M,
@@ -296,10 +296,9 @@ MACHINE_END
296MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") 296MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
297 /* Maintainer: MontaVista Software, Inc. */ 297 /* Maintainer: MontaVista Software, Inc. */
298 .map_io = ixp4xx_map_io, 298 .map_io = ixp4xx_map_io,
299 .init_early = ixp4xx_init_early,
300 .init_irq = ixp4xx_init_irq, 299 .init_irq = ixp4xx_init_irq,
301 .timer = &ixp4xx_timer, 300 .timer = &ixp4xx_timer,
302 .atag_offset = 0x100, 301 .boot_params = 0x0100,
303 .init_machine = ixdp425_init, 302 .init_machine = ixdp425_init,
304#if defined(CONFIG_PCI) 303#if defined(CONFIG_PCI)
305 .dma_zone_size = SZ_64M, 304 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index 1f8717ba13d..34efe75015e 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -42,9 +42,10 @@ static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
42 42
43struct hw_pci ixdpg425_pci __initdata = { 43struct hw_pci ixdpg425_pci __initdata = {
44 .nr_controllers = 1, 44 .nr_controllers = 1,
45 .ops = &ixp4xx_ops,
46 .preinit = ixdpg425_pci_preinit, 45 .preinit = ixdpg425_pci_preinit,
46 .swizzle = pci_std_swizzle,
47 .setup = ixp4xx_setup, 47 .setup = ixp4xx_setup,
48 .scan = ixp4xx_scan_bus,
48 .map_irq = ixdpg425_map_irq, 49 .map_irq = ixdpg425_map_irq,
49}; 50};
50 51
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index d4eb09a6286..a17ed79207a 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -116,11 +116,7 @@
116/* NPE mailbox_status value for reset */ 116/* NPE mailbox_status value for reset */
117#define RESET_MBOX_STAT 0x0000F0F0 117#define RESET_MBOX_STAT 0x0000F0F0
118 118
119#define NPE_A_FIRMWARE "NPE-A" 119const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
120#define NPE_B_FIRMWARE "NPE-B"
121#define NPE_C_FIRMWARE "NPE-C"
122
123const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE };
124 120
125#define print_npe(pri, npe, fmt, ...) \ 121#define print_npe(pri, npe, fmt, ...) \
126 printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) 122 printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
@@ -728,9 +724,6 @@ module_exit(npe_cleanup_module);
728 724
729MODULE_AUTHOR("Krzysztof Halasa"); 725MODULE_AUTHOR("Krzysztof Halasa");
730MODULE_LICENSE("GPL v2"); 726MODULE_LICENSE("GPL v2");
731MODULE_FIRMWARE(NPE_A_FIRMWARE);
732MODULE_FIRMWARE(NPE_B_FIRMWARE);
733MODULE_FIRMWARE(NPE_C_FIRMWARE);
734 727
735EXPORT_SYMBOL(npe_names); 728EXPORT_SYMBOL(npe_names);
736EXPORT_SYMBOL(npe_running); 729EXPORT_SYMBOL(npe_running);
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index 9d1b6b7c394..852f7c9f87d 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -14,7 +14,7 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <mach/qmgr.h> 15#include <mach/qmgr.h>
16 16
17static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; 17struct qmgr_regs __iomem *qmgr_regs;
18static struct resource *mem_res; 18static struct resource *mem_res;
19static spinlock_t qmgr_lock; 19static spinlock_t qmgr_lock;
20static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ 20static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
@@ -293,6 +293,12 @@ static int qmgr_init(void)
293 if (mem_res == NULL) 293 if (mem_res == NULL)
294 return -EBUSY; 294 return -EBUSY;
295 295
296 qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
297 if (qmgr_regs == NULL) {
298 err = -ENOMEM;
299 goto error_map;
300 }
301
296 /* reset qmgr registers */ 302 /* reset qmgr registers */
297 for (i = 0; i < 4; i++) { 303 for (i = 0; i < 4; i++) {
298 __raw_writel(0x33333333, &qmgr_regs->stat1[i]); 304 __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
@@ -341,6 +347,8 @@ static int qmgr_init(void)
341error_irq2: 347error_irq2:
342 free_irq(IRQ_IXP4XX_QM1, NULL); 348 free_irq(IRQ_IXP4XX_QM1, NULL);
343error_irq: 349error_irq:
350 iounmap(qmgr_regs);
351error_map:
344 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); 352 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
345 return err; 353 return err;
346} 354}
@@ -351,6 +359,7 @@ static void qmgr_remove(void)
351 free_irq(IRQ_IXP4XX_QM2, NULL); 359 free_irq(IRQ_IXP4XX_QM2, NULL);
352 synchronize_irq(IRQ_IXP4XX_QM1); 360 synchronize_irq(IRQ_IXP4XX_QM1);
353 synchronize_irq(IRQ_IXP4XX_QM2); 361 synchronize_irq(IRQ_IXP4XX_QM2);
362 iounmap(qmgr_regs);
354 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); 363 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
355} 364}
356 365
@@ -360,6 +369,7 @@ module_exit(qmgr_remove);
360MODULE_LICENSE("GPL v2"); 369MODULE_LICENSE("GPL v2");
361MODULE_AUTHOR("Krzysztof Halasa"); 370MODULE_AUTHOR("Krzysztof Halasa");
362 371
372EXPORT_SYMBOL(qmgr_regs);
363EXPORT_SYMBOL(qmgr_set_irq); 373EXPORT_SYMBOL(qmgr_set_irq);
364EXPORT_SYMBOL(qmgr_enable_irq); 374EXPORT_SYMBOL(qmgr_enable_irq);
365EXPORT_SYMBOL(qmgr_disable_irq); 375EXPORT_SYMBOL(qmgr_disable_irq);
diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c
deleted file mode 100644
index d114ccd2017..00000000000
--- a/arch/arm/mach-ixp4xx/miccpt-pci.c
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/miccpt-pci.c
3 *
4 * MICCPT board-level PCI initialization
5 *
6 * Copyright (C) 2002 Intel Corporation.
7 * Copyright (C) 2003-2004 MontaVista Software, Inc.
8 * Copyright (C) 2006 OMICRON electronics GmbH
9 *
10 * Author: Michael Jochum <michael.jochum@omicron.at>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/irq.h>
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27
28#define MAX_DEV 4
29#define IRQ_LINES 4
30
31/* PCI controller GPIO to IRQ pin mappings */
32#define INTA 1
33#define INTB 2
34#define INTC 3
35#define INTD 4
36
37
38void __init miccpt_pci_preinit(void)
39{
40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
43 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
44 ixp4xx_pci_preinit();
45}
46
47static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
48{
49 static int pci_irq_table[IRQ_LINES] = {
50 IXP4XX_GPIO_IRQ(INTA),
51 IXP4XX_GPIO_IRQ(INTB),
52 IXP4XX_GPIO_IRQ(INTC),
53 IXP4XX_GPIO_IRQ(INTD)
54 };
55
56 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
57 return pci_irq_table[(slot + pin - 2) % 4];
58
59 return -1;
60}
61
62struct hw_pci miccpt_pci __initdata = {
63 .nr_controllers = 1,
64 .ops = &ixp4xx_ops,
65 .preinit = miccpt_pci_preinit,
66 .setup = ixp4xx_setup,
67 .map_irq = miccpt_map_irq,
68};
69
70int __init miccpt_pci_init(void)
71{
72 if (machine_is_miccpt())
73 pci_common_init(&miccpt_pci);
74 return 0;
75}
76
77subsys_initcall(miccpt_pci_init);
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index 8f0eba0a680..5434ccf553e 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -58,9 +58,10 @@ static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
58 58
59struct hw_pci __initdata nas100d_pci = { 59struct hw_pci __initdata nas100d_pci = {
60 .nr_controllers = 1, 60 .nr_controllers = 1,
61 .ops = &ixp4xx_ops,
62 .preinit = nas100d_pci_preinit, 61 .preinit = nas100d_pci_preinit,
62 .swizzle = pci_std_swizzle,
63 .setup = ixp4xx_setup, 63 .setup = ixp4xx_setup,
64 .scan = ixp4xx_scan_bus,
64 .map_irq = nas100d_map_irq, 65 .map_irq = nas100d_map_irq,
65}; 66};
66 67
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 33cb0955b6b..afb51879d9a 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -17,7 +17,7 @@
17 * Maintainers: http://www.nslu2-linux.org/ 17 * Maintainers: http://www.nslu2-linux.org/
18 * 18 *
19 */ 19 */
20#include <linux/gpio.h> 20
21#include <linux/if_ether.h> 21#include <linux/if_ether.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/jiffies.h> 23#include <linux/jiffies.h>
@@ -32,6 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/mach/flash.h> 34#include <asm/mach/flash.h>
35#include <asm/gpio.h>
35 36
36#define NAS100D_SDA_PIN 5 37#define NAS100D_SDA_PIN 5
37#define NAS100D_SCL_PIN 6 38#define NAS100D_SCL_PIN 6
@@ -313,14 +314,12 @@ static void __init nas100d_init(void)
313 314
314MACHINE_START(NAS100D, "Iomega NAS 100d") 315MACHINE_START(NAS100D, "Iomega NAS 100d")
315 /* Maintainer: www.nslu2-linux.org */ 316 /* Maintainer: www.nslu2-linux.org */
316 .atag_offset = 0x100, 317 .boot_params = 0x00000100,
317 .map_io = ixp4xx_map_io, 318 .map_io = ixp4xx_map_io,
318 .init_early = ixp4xx_init_early,
319 .init_irq = ixp4xx_init_irq, 319 .init_irq = ixp4xx_init_irq,
320 .timer = &ixp4xx_timer, 320 .timer = &ixp4xx_timer,
321 .init_machine = nas100d_init, 321 .init_machine = nas100d_init,
322#if defined(CONFIG_PCI) 322#if defined(CONFIG_PCI)
323 .dma_zone_size = SZ_64M, 323 .dma_zone_size = SZ_64M,
324#endif 324#endif
325 .restart = ixp4xx_restart,
326MACHINE_END 325MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 032defe111a..b57160535e4 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -54,9 +54,10 @@ static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
54 54
55struct hw_pci __initdata nslu2_pci = { 55struct hw_pci __initdata nslu2_pci = {
56 .nr_controllers = 1, 56 .nr_controllers = 1,
57 .ops = &ixp4xx_ops,
58 .preinit = nslu2_pci_preinit, 57 .preinit = nslu2_pci_preinit,
58 .swizzle = pci_std_swizzle,
59 .setup = ixp4xx_setup, 59 .setup = ixp4xx_setup,
60 .scan = ixp4xx_scan_bus,
60 .map_irq = nslu2_map_irq, 61 .map_irq = nslu2_map_irq,
61}; 62};
62 63
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index e2903faaebb..69e40f2cf09 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -16,7 +16,7 @@
16 * Maintainers: http://www.nslu2-linux.org/ 16 * Maintainers: http://www.nslu2-linux.org/
17 * 17 *
18 */ 18 */
19#include <linux/gpio.h> 19
20#include <linux/if_ether.h> 20#include <linux/if_ether.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/serial.h> 22#include <linux/serial.h>
@@ -30,6 +30,7 @@
30#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
31#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
32#include <asm/mach/time.h> 32#include <asm/mach/time.h>
33#include <asm/gpio.h>
33 34
34#define NSLU2_SDA_PIN 7 35#define NSLU2_SDA_PIN 7
35#define NSLU2_SCL_PIN 6 36#define NSLU2_SCL_PIN 6
@@ -299,14 +300,12 @@ static void __init nslu2_init(void)
299 300
300MACHINE_START(NSLU2, "Linksys NSLU2") 301MACHINE_START(NSLU2, "Linksys NSLU2")
301 /* Maintainer: www.nslu2-linux.org */ 302 /* Maintainer: www.nslu2-linux.org */
302 .atag_offset = 0x100, 303 .boot_params = 0x00000100,
303 .map_io = ixp4xx_map_io, 304 .map_io = ixp4xx_map_io,
304 .init_early = ixp4xx_init_early,
305 .init_irq = ixp4xx_init_irq, 305 .init_irq = ixp4xx_init_irq,
306 .timer = &nslu2_timer, 306 .timer = &nslu2_timer,
307 .init_machine = nslu2_init, 307 .init_machine = nslu2_init,
308#if defined(CONFIG_PCI) 308#if defined(CONFIG_PCI)
309 .dma_zone_size = SZ_64M, 309 .dma_zone_size = SZ_64M,
310#endif 310#endif
311 .restart = ixp4xx_restart,
312MACHINE_END 311MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
deleted file mode 100644
index 158ddb79821..00000000000
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ /dev/null
@@ -1,279 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/omixp-setup.c
3 *
4 * omicron ixp4xx board setup
5 * Copyright (C) 2009 OMICRON electronics GmbH
6 *
7 * based nslu2-setup.c, ixdp425-setup.c:
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/serial.h>
17#include <linux/serial_8250.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/partitions.h>
20#ifdef CONFIG_LEDS_CLASS
21#include <linux/leds.h>
22#endif
23
24#include <asm/setup.h>
25#include <asm/memory.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/flash.h>
29
30static struct resource omixp_flash_resources[] = {
31 {
32 .flags = IORESOURCE_MEM,
33 }, {
34 .flags = IORESOURCE_MEM,
35 },
36};
37
38static struct mtd_partition omixp_partitions[] = {
39 {
40 .name = "Recovery Bootloader",
41 .size = 0x00020000,
42 .offset = 0,
43 }, {
44 .name = "Calibration Data",
45 .size = 0x00020000,
46 .offset = 0x00020000,
47 }, {
48 .name = "Recovery FPGA",
49 .size = 0x00020000,
50 .offset = 0x00040000,
51 }, {
52 .name = "Release Bootloader",
53 .size = 0x00020000,
54 .offset = 0x00060000,
55 }, {
56 .name = "Release FPGA",
57 .size = 0x00020000,
58 .offset = 0x00080000,
59 }, {
60 .name = "Kernel",
61 .size = 0x00160000,
62 .offset = 0x000a0000,
63 }, {
64 .name = "Filesystem",
65 .size = 0x00C00000,
66 .offset = 0x00200000,
67 }, {
68 .name = "Persistent Storage",
69 .size = 0x00200000,
70 .offset = 0x00E00000,
71 },
72};
73
74static struct flash_platform_data omixp_flash_data[] = {
75 {
76 .map_name = "cfi_probe",
77 .parts = omixp_partitions,
78 .nr_parts = ARRAY_SIZE(omixp_partitions),
79 }, {
80 .map_name = "cfi_probe",
81 .parts = NULL,
82 .nr_parts = 0,
83 },
84};
85
86static struct platform_device omixp_flash_device[] = {
87 {
88 .name = "IXP4XX-Flash",
89 .id = 0,
90 .dev = {
91 .platform_data = &omixp_flash_data[0],
92 },
93 .resource = &omixp_flash_resources[0],
94 .num_resources = 1,
95 }, {
96 .name = "IXP4XX-Flash",
97 .id = 1,
98 .dev = {
99 .platform_data = &omixp_flash_data[1],
100 },
101 .resource = &omixp_flash_resources[1],
102 .num_resources = 1,
103 },
104};
105
106/* Swap UART's - These boards have the console on UART2. The following
107 * configuration is used:
108 * ttyS0 .. UART2
109 * ttyS1 .. UART1
110 * This way standard images can be used with the kernel that expect
111 * the console on ttyS0.
112 */
113static struct resource omixp_uart_resources[] = {
114 {
115 .start = IXP4XX_UART2_BASE_PHYS,
116 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
117 .flags = IORESOURCE_MEM,
118 }, {
119 .start = IXP4XX_UART1_BASE_PHYS,
120 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
121 .flags = IORESOURCE_MEM,
122 },
123};
124
125static struct plat_serial8250_port omixp_uart_data[] = {
126 {
127 .mapbase = IXP4XX_UART2_BASE_PHYS,
128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
129 .irq = IRQ_IXP4XX_UART2,
130 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
131 .iotype = UPIO_MEM,
132 .regshift = 2,
133 .uartclk = IXP4XX_UART_XTAL,
134 }, {
135 .mapbase = IXP4XX_UART1_BASE_PHYS,
136 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
137 .irq = IRQ_IXP4XX_UART1,
138 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
139 .iotype = UPIO_MEM,
140 .regshift = 2,
141 .uartclk = IXP4XX_UART_XTAL,
142 }, {
143 /* list termination */
144 }
145};
146
147static struct platform_device omixp_uart = {
148 .name = "serial8250",
149 .id = PLAT8250_DEV_PLATFORM,
150 .dev.platform_data = omixp_uart_data,
151 .num_resources = 2,
152 .resource = omixp_uart_resources,
153};
154
155static struct gpio_led mic256_led_pins[] = {
156 {
157 .name = "LED-A",
158 .gpio = 7,
159 },
160};
161
162static struct gpio_led_platform_data mic256_led_data = {
163 .num_leds = ARRAY_SIZE(mic256_led_pins),
164 .leds = mic256_led_pins,
165};
166
167static struct platform_device mic256_leds = {
168 .name = "leds-gpio",
169 .id = -1,
170 .dev.platform_data = &mic256_led_data,
171};
172
173/* Built-in 10/100 Ethernet MAC interfaces */
174static struct eth_plat_info ixdp425_plat_eth[] = {
175 {
176 .phy = 0,
177 .rxq = 3,
178 .txreadyq = 20,
179 }, {
180 .phy = 1,
181 .rxq = 4,
182 .txreadyq = 21,
183 },
184};
185
186static struct platform_device ixdp425_eth[] = {
187 {
188 .name = "ixp4xx_eth",
189 .id = IXP4XX_ETH_NPEB,
190 .dev.platform_data = ixdp425_plat_eth,
191 }, {
192 .name = "ixp4xx_eth",
193 .id = IXP4XX_ETH_NPEC,
194 .dev.platform_data = ixdp425_plat_eth + 1,
195 },
196};
197
198
199static struct platform_device *devixp_pldev[] __initdata = {
200 &omixp_uart,
201 &omixp_flash_device[0],
202 &ixdp425_eth[0],
203 &ixdp425_eth[1],
204};
205
206static struct platform_device *mic256_pldev[] __initdata = {
207 &omixp_uart,
208 &omixp_flash_device[0],
209 &mic256_leds,
210 &ixdp425_eth[0],
211 &ixdp425_eth[1],
212};
213
214static struct platform_device *miccpt_pldev[] __initdata = {
215 &omixp_uart,
216 &omixp_flash_device[0],
217 &omixp_flash_device[1],
218 &ixdp425_eth[0],
219 &ixdp425_eth[1],
220};
221
222static void __init omixp_init(void)
223{
224 ixp4xx_sys_init();
225
226 /* 16MiB Boot Flash */
227 omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
228 omixp_flash_resources[0].end = IXP4XX_EXP_BUS_END(0);
229
230 /* 32 MiB Data Flash */
231 omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
232 omixp_flash_resources[1].end = IXP4XX_EXP_BUS_END(2);
233
234 if (machine_is_devixp())
235 platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev));
236 else if (machine_is_miccpt())
237 platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev));
238 else if (machine_is_mic256())
239 platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev));
240}
241
242#ifdef CONFIG_MACH_DEVIXP
243MACHINE_START(DEVIXP, "Omicron DEVIXP")
244 .atag_offset = 0x100,
245 .map_io = ixp4xx_map_io,
246 .init_early = ixp4xx_init_early,
247 .init_irq = ixp4xx_init_irq,
248 .timer = &ixp4xx_timer,
249 .init_machine = omixp_init,
250 .restart = ixp4xx_restart,
251MACHINE_END
252#endif
253
254#ifdef CONFIG_MACH_MICCPT
255MACHINE_START(MICCPT, "Omicron MICCPT")
256 .atag_offset = 0x100,
257 .map_io = ixp4xx_map_io,
258 .init_early = ixp4xx_init_early,
259 .init_irq = ixp4xx_init_irq,
260 .timer = &ixp4xx_timer,
261 .init_machine = omixp_init,
262#if defined(CONFIG_PCI)
263 .dma_zone_size = SZ_64M,
264#endif
265 .restart = ixp4xx_restart,
266MACHINE_END
267#endif
268
269#ifdef CONFIG_MACH_MIC256
270MACHINE_START(MIC256, "Omicron MIC256")
271 .atag_offset = 0x100,
272 .map_io = ixp4xx_map_io,
273 .init_early = ixp4xx_init_early,
274 .init_irq = ixp4xx_init_irq,
275 .timer = &ixp4xx_timer,
276 .init_machine = omixp_init,
277 .restart = ixp4xx_restart,
278MACHINE_END
279#endif
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c
index a4220fa5e0c..0bc3f34c282 100644
--- a/arch/arm/mach-ixp4xx/vulcan-pci.c
+++ b/arch/arm/mach-ixp4xx/vulcan-pci.c
@@ -56,9 +56,10 @@ static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
56 56
57struct hw_pci vulcan_pci __initdata = { 57struct hw_pci vulcan_pci __initdata = {
58 .nr_controllers = 1, 58 .nr_controllers = 1,
59 .ops = &ixp4xx_ops,
60 .preinit = vulcan_pci_preinit, 59 .preinit = vulcan_pci_preinit,
60 .swizzle = pci_std_swizzle,
61 .setup = ixp4xx_setup, 61 .setup = ixp4xx_setup,
62 .scan = ixp4xx_scan_bus,
62 .map_irq = vulcan_map_irq, 63 .map_irq = vulcan_map_irq,
63}; 64};
64 65
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 2798f435aaf..045336c833a 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -237,13 +237,11 @@ static void __init vulcan_init(void)
237MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan") 237MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
238 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 238 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
239 .map_io = ixp4xx_map_io, 239 .map_io = ixp4xx_map_io,
240 .init_early = ixp4xx_init_early,
241 .init_irq = ixp4xx_init_irq, 240 .init_irq = ixp4xx_init_irq,
242 .timer = &ixp4xx_timer, 241 .timer = &ixp4xx_timer,
243 .atag_offset = 0x100, 242 .boot_params = 0x0100,
244 .init_machine = vulcan_init, 243 .init_machine = vulcan_init,
245#if defined(CONFIG_PCI) 244#if defined(CONFIG_PCI)
246 .dma_zone_size = SZ_64M, 245 .dma_zone_size = SZ_64M,
247#endif 246#endif
248 .restart = ixp4xx_restart,
249MACHINE_END 247MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index c92e5b82af3..f27dfcfe811 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -46,9 +46,10 @@ static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
46 46
47struct hw_pci wg302v2_pci __initdata = { 47struct hw_pci wg302v2_pci __initdata = {
48 .nr_controllers = 1, 48 .nr_controllers = 1,
49 .ops = &ixp4xx_ops,
50 .preinit = wg302v2_pci_preinit, 49 .preinit = wg302v2_pci_preinit,
50 .swizzle = pci_std_swizzle,
51 .setup = ixp4xx_setup, 51 .setup = ixp4xx_setup,
52 .scan = ixp4xx_scan_bus,
52 .map_irq = wg302v2_map_irq, 53 .map_irq = wg302v2_map_irq,
53}; 54};
54 55
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index a785175b115..40b9fad800b 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -98,14 +98,12 @@ static void __init wg302v2_init(void)
98MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2") 98MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
99 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 99 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
100 .map_io = ixp4xx_map_io, 100 .map_io = ixp4xx_map_io,
101 .init_early = ixp4xx_init_early,
102 .init_irq = ixp4xx_init_irq, 101 .init_irq = ixp4xx_init_irq,
103 .timer = &ixp4xx_timer, 102 .timer = &ixp4xx_timer,
104 .atag_offset = 0x100, 103 .boot_params = 0x0100,
105 .init_machine = wg302v2_init, 104 .init_machine = wg302v2_init,
106#if defined(CONFIG_PCI) 105#if defined(CONFIG_PCI)
107 .dma_zone_size = SZ_64M, 106 .dma_zone_size = SZ_64M,
108#endif 107#endif
109 .restart = ixp4xx_restart,
110MACHINE_END 108MACHINE_END
111#endif 109#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 17:59:11 -0400