From 8dea78da5cee153b8af9c07a2745f6c55057fe12 Mon Sep 17 00:00:00 2001 From: Jonathan Herman Date: Thu, 17 Jan 2013 16:15:55 -0500 Subject: Patched in Tegra support. --- arch/arm/mach-ixp4xx/Kconfig | 21 +- arch/arm/mach-ixp4xx/Makefile | 4 - arch/arm/mach-ixp4xx/Makefile.boot | 2 +- arch/arm/mach-ixp4xx/avila-pci.c | 3 +- arch/arm/mach-ixp4xx/avila-setup.c | 8 +- arch/arm/mach-ixp4xx/common-pci.c | 38 ++-- arch/arm/mach-ixp4xx/common.c | 144 +++--------- arch/arm/mach-ixp4xx/coyote-pci.c | 3 +- arch/arm/mach-ixp4xx/coyote-setup.c | 8 +- arch/arm/mach-ixp4xx/dsmg600-pci.c | 3 +- arch/arm/mach-ixp4xx/dsmg600-setup.c | 7 +- arch/arm/mach-ixp4xx/fsg-pci.c | 3 +- arch/arm/mach-ixp4xx/fsg-setup.c | 7 +- arch/arm/mach-ixp4xx/gateway7001-pci.c | 3 +- arch/arm/mach-ixp4xx/gateway7001-setup.c | 4 +- arch/arm/mach-ixp4xx/goramo_mlr.c | 11 +- arch/arm/mach-ixp4xx/gtwx5715-pci.c | 3 +- arch/arm/mach-ixp4xx/gtwx5715-setup.c | 4 +- arch/arm/mach-ixp4xx/include/mach/cpu.h | 5 +- arch/arm/mach-ixp4xx/include/mach/debug-macro.S | 6 +- arch/arm/mach-ixp4xx/include/mach/entry-macro.S | 6 + arch/arm/mach-ixp4xx/include/mach/hardware.h | 2 + arch/arm/mach-ixp4xx/include/mach/io.h | 26 ++- arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 3 - arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | 48 ++-- arch/arm/mach-ixp4xx/include/mach/platform.h | 4 +- arch/arm/mach-ixp4xx/include/mach/qmgr.h | 12 +- arch/arm/mach-ixp4xx/include/mach/udc.h | 2 +- arch/arm/mach-ixp4xx/include/mach/uncompress.h | 3 +- arch/arm/mach-ixp4xx/ixdp425-pci.c | 3 +- arch/arm/mach-ixp4xx/ixdp425-setup.c | 17 +- arch/arm/mach-ixp4xx/ixdpg425-pci.c | 3 +- arch/arm/mach-ixp4xx/ixp4xx_npe.c | 9 +- arch/arm/mach-ixp4xx/ixp4xx_qmgr.c | 12 +- arch/arm/mach-ixp4xx/miccpt-pci.c | 77 ------- arch/arm/mach-ixp4xx/nas100d-pci.c | 3 +- arch/arm/mach-ixp4xx/nas100d-setup.c | 7 +- arch/arm/mach-ixp4xx/nslu2-pci.c | 3 +- arch/arm/mach-ixp4xx/nslu2-setup.c | 7 +- arch/arm/mach-ixp4xx/omixp-setup.c | 279 ------------------------ arch/arm/mach-ixp4xx/vulcan-pci.c | 3 +- arch/arm/mach-ixp4xx/vulcan-setup.c | 4 +- arch/arm/mach-ixp4xx/wg302v2-pci.c | 3 +- arch/arm/mach-ixp4xx/wg302v2-setup.c | 4 +- 44 files changed, 193 insertions(+), 634 deletions(-) delete mode 100644 arch/arm/mach-ixp4xx/miccpt-pci.c delete mode 100644 arch/arm/mach-ixp4xx/omixp-setup.c (limited to 'arch/arm/mach-ixp4xx') diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 73a2d905af8..6f991c5ae86 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -179,25 +179,6 @@ config MACH_GTWX5715 "High Speed" UART is n/c (as far as I can tell) 20 Pin ARM/Xscale JTAG interface on J2 -config MACH_DEVIXP - bool "Omicron DEVIXP" - help - Say 'Y' here if you want your kernel to support the DEVIXP - board from OMICRON electronics GmbH. - -config MACH_MICCPT - bool "Omicron MICCPT" - select PCI - help - Say 'Y' here if you want your kernel to support the MICCPT - board from OMICRON electronics GmbH. - -config MACH_MIC256 - bool "Omicron MIC256" - help - Say 'Y' here if you want your kernel to support the MIC256 - board from OMICRON electronics GmbH. - comment "IXP4xx Options" config IXP4XX_INDIRECT_PCI @@ -234,8 +215,8 @@ config IXP4XX_QMGR config IXP4XX_NPE tristate "IXP4xx Network Processor Engine support" - select FW_LOADER select HOTPLUG + select FW_LOADER help This driver supports IXP4xx built-in network coprocessors and is automatically selected by Ethernet and HSS drivers. diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index eded94c96dd..d807fc367dd 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -10,7 +10,6 @@ obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o -obj-pci-$(CONFIG_MACH_MICCPT) += miccpt-pci.o obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o @@ -26,9 +25,6 @@ obj-$(CONFIG_MACH_AVILA) += avila-setup.o obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o -obj-$(CONFIG_MACH_DEVIXP) += omixp-setup.o -obj-$(CONFIG_MACH_MICCPT) += omixp-setup.o -obj-$(CONFIG_MACH_MIC256) += omixp-setup.o obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o diff --git a/arch/arm/mach-ixp4xx/Makefile.boot b/arch/arm/mach-ixp4xx/Makefile.boot index 9c7af91d93d..d84c5807a43 100644 --- a/arch/arm/mach-ixp4xx/Makefile.boot +++ b/arch/arm/mach-ixp4xx/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y += 0x00008000 + zreladdr-y := 0x00008000 params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 548c7d43ade..8fea0a3c524 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -65,9 +65,10 @@ static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci avila_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = avila_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = avila_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c index 90e42e9982c..ee19c1d383a 100644 --- a/arch/arm/mach-ixp4xx/avila-setup.c +++ b/arch/arm/mach-ixp4xx/avila-setup.c @@ -165,15 +165,13 @@ static void __init avila_init(void) MACHINE_START(AVILA, "Gateworks Avila Network Platform") /* Maintainer: Deepak Saxena */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = avila_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END /* @@ -185,15 +183,13 @@ MACHINE_END MACHINE_START(LOFT, "Giant Shoulder Inc Loft board") /* Maintainer: Tom Billman */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = avila_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 6d6bde3e15f..2131832ee6b 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -26,12 +26,12 @@ #include #include #include -#include #include #include #include #include +#include #include #include @@ -54,7 +54,7 @@ unsigned long ixp4xx_pci_reg_base = 0; * these transactions are atomic or we will end up * with corrupt data on the bus or in a driver. */ -static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock); +static DEFINE_SPINLOCK(ixp4xx_pci_lock); /* * Read from PCI config space @@ -62,10 +62,10 @@ static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock); static void crp_read(u32 ad_cbe, u32 *data) { unsigned long flags; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); + spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_CRP_AD_CBE = ad_cbe; *data = *PCI_CRP_RDATA; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); } /* @@ -74,10 +74,10 @@ static void crp_read(u32 ad_cbe, u32 *data) static void crp_write(u32 ad_cbe, u32 data) { unsigned long flags; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); + spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; *PCI_CRP_WDATA = data; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); } static inline int check_master_abort(void) @@ -101,7 +101,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) int retval = 0; int i; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); + spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_NP_AD = addr; @@ -118,7 +118,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) if(check_master_abort()) retval = 1; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); return retval; } @@ -127,7 +127,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) unsigned long flags; int retval = 0; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); + spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_NP_AD = addr; @@ -140,7 +140,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) if(check_master_abort()) retval = 1; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); return retval; } @@ -149,7 +149,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) unsigned long flags; int retval = 0; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); + spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_NP_AD = addr; @@ -162,7 +162,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) if(check_master_abort()) retval = 1; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); return retval; } @@ -397,8 +397,7 @@ void __init ixp4xx_pci_preinit(void) local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); - local_write_config(PCI_BASE_ADDRESS_3, 4, - PHYS_OFFSET + SZ_32M + SZ_16M); + local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); /* * Enable CSR window at 64 MiB to allow PCI masters @@ -410,7 +409,6 @@ void __init ixp4xx_pci_preinit(void) * Enable the IO window to be way up high, at 0xfffffc00 */ local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01); - local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */ } else { printk("PCI: IXP4xx is target - No bus scan performed\n"); } @@ -472,8 +470,9 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) request_resource(&ioport_resource, &res[0]); request_resource(&iomem_resource, &res[1]); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; platform_notify = ixp4xx_pci_platform_notify; platform_notify_remove = ixp4xx_pci_platform_notify_remove; @@ -481,6 +480,11 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) return 1; } +struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); +} + int dma_set_coherent_mask(struct device *dev, u64 mask) { if (mask >= SZ_64M - 1) diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 8c0c0e2d072..07772575d7a 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -27,18 +28,14 @@ #include #include #include -#include -#include #include #include -#include #include #include #include #include #include -#include #include #include @@ -53,26 +50,29 @@ static struct clock_event_device clockevent_ixp4xx; *************************************************************************/ static struct map_desc ixp4xx_io_desc[] __initdata = { { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ - .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, + .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), .length = IXP4XX_PERIPHERAL_REGION_SIZE, .type = MT_DEVICE }, { /* Expansion Bus Config Registers */ - .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, + .virtual = IXP4XX_EXP_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), .length = IXP4XX_EXP_CFG_REGION_SIZE, .type = MT_DEVICE }, { /* PCI Registers */ - .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, + .virtual = IXP4XX_PCI_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), .length = IXP4XX_PCI_CFG_REGION_SIZE, .type = MT_DEVICE - }, { /* Queue Manager */ - .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT, - .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS), - .length = IXP4XX_QMGR_REGION_SIZE, - .type = MT_DEVICE }, +#ifdef CONFIG_DEBUG_LL + { /* Debug UART mapping */ + .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, + .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), + .length = IXP4XX_DEBUG_UART_REGION_SIZE, + .type = MT_DEVICE + } +#endif }; void __init ixp4xx_map_io(void) @@ -105,7 +105,7 @@ static signed char irq2gpio[32] = { 7, 8, 9, 10, 11, 12, -1, -1, }; -static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) +int gpio_to_irq(int gpio) { int irq; @@ -115,6 +115,7 @@ static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) } return -EINVAL; } +EXPORT_SYMBOL(gpio_to_irq); int irq_to_gpio(unsigned int irq) { @@ -235,12 +236,6 @@ void __init ixp4xx_init_irq(void) { int i = 0; - /* - * ixp4xx does not implement the XScale PWRMODE register - * so it must not call cpu_do_idle(). - */ - disable_hlt(); - /* Route all sources to IRQ instead of FIQ */ *IXP4XX_ICLR = 0x0; @@ -380,56 +375,12 @@ static struct platform_device *ixp46x_devices[] __initdata = { unsigned long ixp4xx_exp_bus_size; EXPORT_SYMBOL(ixp4xx_exp_bus_size); -static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - gpio_line_config(gpio, IXP4XX_GPIO_IN); - - return 0; -} - -static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, - int level) -{ - gpio_line_set(gpio, level); - gpio_line_config(gpio, IXP4XX_GPIO_OUT); - - return 0; -} - -static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio) -{ - int value; - - gpio_line_get(gpio, &value); - - return value; -} - -static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, - int value) -{ - gpio_line_set(gpio, value); -} - -static struct gpio_chip ixp4xx_gpio_chip = { - .label = "IXP4XX_GPIO_CHIP", - .direction_input = ixp4xx_gpio_direction_input, - .direction_output = ixp4xx_gpio_direction_output, - .get = ixp4xx_gpio_get_value, - .set = ixp4xx_gpio_set_value, - .to_irq = ixp4xx_gpio_to_irq, - .base = 0, - .ngpio = 16, -}; - void __init ixp4xx_sys_init(void) { ixp4xx_exp_bus_size = SZ_16M; platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); - gpiochip_add(&ixp4xx_gpio_chip); - if (cpu_is_ixp46x()) { int region; @@ -451,9 +402,18 @@ void __init ixp4xx_sys_init(void) /* * sched_clock() */ -static u32 notrace ixp4xx_read_sched_clock(void) +static DEFINE_CLOCK_DATA(cd); + +unsigned long long notrace sched_clock(void) { - return *IXP4XX_OSTS; + u32 cyc = *IXP4XX_OSTS; + return cyc_to_sched_clock(&cd, cyc, (u32)~0); +} + +static void notrace ixp4xx_update_sched_clock(void) +{ + u32 cyc = *IXP4XX_OSTS; + update_sched_clock(&cd, cyc, (u32)~0); } /* @@ -469,7 +429,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; EXPORT_SYMBOL(ixp4xx_timer_freq); static void __init ixp4xx_clocksource_init(void) { - setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); + init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq); clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, ixp4xx_clocksource_read); @@ -540,55 +500,3 @@ static void __init ixp4xx_clockevent_init(void) clockevents_register_device(&clockevent_ixp4xx); } - -void ixp4xx_restart(char mode, const char *cmd) -{ - if ( 1 && mode == 's') { - /* Jump into ROM at address 0 */ - soft_restart(0); - } else { - /* Use on-chip reset capability */ - - /* set the "key" register to enable access to - * "timer" and "enable" registers - */ - *IXP4XX_OSWK = IXP4XX_WDT_KEY; - - /* write 0 to the timer register for an immediate reset */ - *IXP4XX_OSWT = 0; - - *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE; - } -} - -#ifdef CONFIG_IXP4XX_INDIRECT_PCI -/* - * In the case of using indirect PCI, we simply return the actual PCI - * address and our read/write implementation use that to drive the - * access registers. If something outside of PCI is ioremap'd, we - * fallback to the default. - */ - -static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size, - unsigned int mtype, void *caller) -{ - if (!is_pci_memory(addr)) - return __arm_ioremap_caller(addr, size, mtype, caller); - - return (void __iomem *)addr; -} - -static void ixp4xx_iounmap(void __iomem *addr) -{ - if (!is_pci_memory((__force u32)addr)) - __iounmap(addr); -} - -void __init ixp4xx_init_early(void) -{ - arch_ioremap_caller = ixp4xx_ioremap_caller; - arch_iounmap = ixp4xx_iounmap; -} -#else -void __init ixp4xx_init_early(void) {} -#endif diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 5d14ce2aee6..71f5c9c60fc 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -48,9 +48,10 @@ static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci coyote_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = coyote_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = coyote_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index 1b83110028d..e24564b5d93 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c @@ -110,15 +110,13 @@ static void __init coyote_init(void) MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") /* Maintainer: MontaVista Software, Inc. */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = coyote_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END #endif @@ -130,12 +128,10 @@ MACHINE_END MACHINE_START(IXDPG425, "Intel IXDPG425") /* Maintainer: MontaVista Software, Inc. */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = coyote_init, - .restart = ixp4xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 8dca7693772..0532510b5e8 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -62,9 +62,10 @@ static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata dsmg600_pci = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = dsmg600_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = dsmg600_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index 97a0af8f195..03e54515e8b 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -16,7 +16,7 @@ * Author: Rod Whitby * Maintainers: http://www.nslu2-linux.org/ */ -#include + #include #include #include @@ -31,6 +31,7 @@ #include #include #include +#include #define DSMG600_SDA_PIN 5 #define DSMG600_SCL_PIN 4 @@ -278,14 +279,12 @@ static void __init dsmg600_init(void) MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") /* Maintainer: www.nslu2-linux.org */ - .atag_offset = 0x100, + .boot_params = 0x00000100, .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &dsmg600_timer, .init_machine = dsmg600_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index fd4a8625b4a..d2ac803328f 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -59,9 +59,10 @@ static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci fsg_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = fsg_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = fsg_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c index 9175a25a751..23a8b361456 100644 --- a/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/arch/arm/mach-ixp4xx/fsg-setup.c @@ -14,7 +14,7 @@ * Maintainers: http://www.nslu2-linux.org/ * */ -#include + #include #include #include @@ -27,6 +27,7 @@ #include #include #include +#include #define FSG_SDA_PIN 12 #define FSG_SCL_PIN 13 @@ -270,14 +271,12 @@ static void __init fsg_init(void) MACHINE_START(FSG, "Freecom FSG-3") /* Maintainer: www.nslu2-linux.org */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = fsg_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index d9d6cc08970..76581fb467c 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -47,9 +47,10 @@ static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot, struct hw_pci gateway7001_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = gateway7001_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = gateway7001_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c index 033c7175895..d4f851bdd9a 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-setup.c +++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c @@ -97,14 +97,12 @@ static void __init gateway7001_init(void) MACHINE_START(GATEWAY7001, "Gateway 7001 AP") /* Maintainer: Imre Kaloz */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = gateway7001_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index 53b8348dfcc..7548d9a2efe 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -12,10 +12,10 @@ #include #include #include +#include #include #include #include -#include #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ @@ -330,7 +330,7 @@ static struct platform_device device_hss_tab[] = { }; -static struct platform_device *device_tab[7] __initdata = { +static struct platform_device *device_tab[6] __initdata = { &device_flash, /* index 0 */ }; @@ -474,10 +474,11 @@ static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci gmlr_hw_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = gmlr_pci_preinit, .postinit = gmlr_pci_postinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = gmlr_map_irq, }; @@ -496,13 +497,11 @@ subsys_initcall(gmlr_pci_init); MACHINE_START(GORAMO_MLR, "MultiLink") /* Maintainer: Krzysztof Halasa */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = gmlr_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 551d114c9e1..d68fc068c38 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -67,9 +67,10 @@ static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci gtwx5715_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = gtwx5715_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = gtwx5715_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 18ebc6be796..3790dffd3c3 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -165,15 +165,13 @@ static void __init gtwx5715_init(void) MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") /* Maintainer: George Joseph */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = gtwx5715_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index ebc0ba31ce8..b2ef65db0e9 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -14,7 +14,6 @@ #ifndef __ASM_ARCH_CPU_H__ #define __ASM_ARCH_CPU_H__ -#include #include /* Processor id value in CP15 Register 0 */ @@ -38,7 +37,7 @@ static inline u32 ixp4xx_read_feature_bits(void) { - u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); + u32 val = ~*IXP4XX_EXP_CFG2; if (cpu_is_ixp42x_rev_a0()) return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | @@ -52,7 +51,7 @@ static inline u32 ixp4xx_read_feature_bits(void) static inline void ixp4xx_write_feature_bits(u32 value) { - __raw_writel(~value, IXP4XX_EXP_CFG2); + *IXP4XX_EXP_CFG2 = ~value; } #endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S index ff686cbc5df..b974a49c0af 100644 --- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S @@ -10,15 +10,15 @@ * published by the Free Software Foundation. */ - .macro addruart, rp, rv, tmp + .macro addruart, rp, rv #ifdef __ARMEB__ mov \rp, #3 @ Uart regs are at off set of 3 if @ byte writes used - Big Endian. #else mov \rp, #0 #endif - orr \rv, \rp, #0xfe000000 @ virtual - orr \rv, \rv, #0x00f00000 + orr \rv, \rp, #0xff000000 @ virtual + orr \rv, \rv, #0x00b00000 orr \rp, \rp, #0xc8000000 @ physical .endm diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S index 79adf83e2c3..f2e14e94ed1 100644 --- a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S +++ b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S @@ -9,9 +9,15 @@ */ #include + .macro disable_fiq + .endm + .macro get_irqnr_preamble, base, tmp .endm + .macro arch_ret_to_user, tmp1, tmp2 + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) ldr \irqstat, [\irqstat] @ get interrupts diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index 034bb2a1b80..c30e7e923a7 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -23,6 +23,8 @@ #define PCIBIOS_MAX_MEM 0x4BFFFFFF #endif +#define ARCH_HAS_DMA_SET_COHERENT_MASK + /* Register locations and bits */ #include "ixp4xx-regs.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 5cf30d1b78d..57b5410c31f 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -17,6 +17,8 @@ #include +#define IO_SPACE_LIMIT 0x0000ffff + extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); @@ -39,7 +41,11 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); * but in some cases the performance hit is acceptable. In addition, you * cannot mmap() PCI devices in this case. */ -#ifdef CONFIG_IXP4XX_INDIRECT_PCI +#ifndef CONFIG_IXP4XX_INDIRECT_PCI + +#define __mem_pci(a) (a) + +#else /* * In the case of using indirect PCI, we simply return the actual PCI @@ -53,6 +59,24 @@ static inline int is_pci_memory(u32 addr) return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF); } +static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, + unsigned int mtype) +{ + if (!is_pci_memory(addr)) + return __arm_ioremap(addr, size, mtype); + + return (void __iomem *)addr; +} + +static inline void __indirect_iounmap(void __iomem *addr) +{ + if (!is_pci_memory((__force u32)addr)) + __iounmap(addr); +} + +#define __arch_ioremap __indirect_ioremap +#define __arch_iounmap __indirect_iounmap + #define writeb(v, p) __indirect_writeb(v, p) #define writew(v, p) __indirect_writew(v, p) #define writel(v, p) __indirect_writel(v, p) diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h index cf03614d250..292d55ed211 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h @@ -75,7 +75,4 @@ struct ixp46x_ts_regs { #define TX_SNAPSHOT_LOCKED (1<<0) #define RX_SNAPSHOT_LOCKED (1<<1) -/* The ptp_ixp46x module will set this variable */ -extern int ixp46x_phc_index; - #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index c5bae9c035d..97c530f66e7 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h @@ -30,43 +30,51 @@ * * 0x50000000 0x10000000 ioremap'd EXP BUS * - * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals + * 0x6000000 0x00004000 ioremap'd QMgr * - * 0xC0000000 0x00001000 0xFEF13000 PCI CFG + * 0xC0000000 0x00001000 0xffbff000 PCI CFG * - * 0xC4000000 0x00001000 0xFEF14000 EXP CFG + * 0xC4000000 0x00001000 0xffbfe000 EXP CFG * - * 0x60000000 0x00004000 0xFEF15000 QMgr + * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals */ /* * Queue Manager */ -#define IXP4XX_QMGR_BASE_PHYS 0x60000000 -#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000) -#define IXP4XX_QMGR_REGION_SIZE 0x00004000 +#define IXP4XX_QMGR_BASE_PHYS (0x60000000) +#define IXP4XX_QMGR_REGION_SIZE (0x00004000) /* - * Peripheral space, including debug UART. Must be section-aligned so that - * it can be used with the low-level debug code. + * Expansion BUS Configuration registers */ -#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 -#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) -#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 +#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) +#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000) +#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) /* * PCI Config registers */ -#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 -#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) -#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 +#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) +#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000) +#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) /* - * Expansion BUS Configuration registers + * Peripheral space + */ +#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) +#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000) +#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000) + +/* + * Debug UART + * + * This is basically a remap of UART1 into a region that is section + * aligned so that it * can be used with the low-level debug code. */ -#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 -#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 -#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 +#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) +#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) +#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) #define IXP4XX_EXP_CS0_OFFSET 0x00 #define IXP4XX_EXP_CS1_OFFSET 0x04 @@ -84,7 +92,7 @@ /* * Expansion Bus Controller registers. */ -#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) +#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h index 5bce94aacca..e824c02c825 100644 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h @@ -121,16 +121,14 @@ extern unsigned long ixp4xx_timer_freq; * Functions used by platform-level setup code */ extern void ixp4xx_map_io(void); -extern void ixp4xx_init_early(void); extern void ixp4xx_init_irq(void); extern void ixp4xx_sys_init(void); extern void ixp4xx_timer_init(void); extern struct sys_timer ixp4xx_timer; -extern void ixp4xx_restart(char, const char *); extern void ixp4xx_pci_preinit(void); struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_ops ixp4xx_ops; +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); /* * GPIO-functions diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h index 4de8da536db..9e7cad2d54c 100644 --- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h +++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h @@ -86,7 +86,7 @@ void qmgr_release_queue(unsigned int queue); static inline void qmgr_put_entry(unsigned int queue, u32 val) { - struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; + extern struct qmgr_regs __iomem *qmgr_regs; #if DEBUG_QMGR BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ @@ -99,7 +99,7 @@ static inline void qmgr_put_entry(unsigned int queue, u32 val) static inline u32 qmgr_get_entry(unsigned int queue) { u32 val; - const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; + extern struct qmgr_regs __iomem *qmgr_regs; val = __raw_readl(&qmgr_regs->acc[queue][0]); #if DEBUG_QMGR BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ @@ -112,14 +112,14 @@ static inline u32 qmgr_get_entry(unsigned int queue) static inline int __qmgr_get_stat1(unsigned int queue) { - const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; + extern struct qmgr_regs __iomem *qmgr_regs; return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) >> ((queue & 7) << 2)) & 0xF; } static inline int __qmgr_get_stat2(unsigned int queue) { - const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; + extern struct qmgr_regs __iomem *qmgr_regs; BUG_ON(queue >= HALF_QUEUES); return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) >> ((queue & 0xF) << 1)) & 0x3; @@ -145,7 +145,7 @@ static inline int qmgr_stat_empty(unsigned int queue) */ static inline int qmgr_stat_below_low_watermark(unsigned int queue) { - const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; + extern struct qmgr_regs __iomem *qmgr_regs; if (queue >= HALF_QUEUES) return (__raw_readl(&qmgr_regs->statne_h) >> (queue - HALF_QUEUES)) & 0x01; @@ -172,7 +172,7 @@ static inline int qmgr_stat_above_high_watermark(unsigned int queue) */ static inline int qmgr_stat_full(unsigned int queue) { - const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; + extern struct qmgr_regs __iomem *qmgr_regs; if (queue >= HALF_QUEUES) return (__raw_readl(&qmgr_regs->statf_h) >> (queue - HALF_QUEUES)) & 0x01; diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h index 7bd8b96c884..80d6da2eafa 100644 --- a/arch/arm/mach-ixp4xx/include/mach/udc.h +++ b/arch/arm/mach-ixp4xx/include/mach/udc.h @@ -2,7 +2,7 @@ * arch/arm/mach-ixp4xx/include/mach/udc.h * */ -#include +#include extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h index eb945a926d0..219d7c1dcdb 100644 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -41,8 +41,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) * Some boards are using UART2 as console */ if (machine_is_adi_coyote() || machine_is_gtwx5715() || - machine_is_gateway7001() || machine_is_wg302v2() || - machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) + machine_is_gateway7001() || machine_is_wg302v2()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 318424dd3c5..fffd8c5e40b 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -60,9 +60,10 @@ static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdp425_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = ixdp425_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = ixdp425_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 108a9d3f382..6a2927956bf 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -60,6 +60,8 @@ static struct platform_device ixdp425_flash = { #if defined(CONFIG_MTD_NAND_PLATFORM) || \ defined(CONFIG_MTD_NAND_PLATFORM_MODULE) +const char *part_probes[] = { "cmdlinepart", NULL }; + static struct mtd_partition ixdp425_partitions[] = { { .name = "ixp400 NAND FS 0", @@ -98,6 +100,8 @@ static struct platform_nand_data ixdp425_flash_nand_data = { .chip = { .nr_chips = 1, .chip_delay = 30, + .options = NAND_NO_AUTOINCR, + .part_probe_types = part_probes, .partitions = ixdp425_partitions, .nr_partitions = ARRAY_SIZE(ixdp425_partitions), }, @@ -250,15 +254,13 @@ static void __init ixdp425_init(void) MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") /* Maintainer: MontaVista Software, Inc. */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END #endif @@ -266,10 +268,9 @@ MACHINE_END MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") /* Maintainer: MontaVista Software, Inc. */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, @@ -281,10 +282,9 @@ MACHINE_END MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") /* Maintainer: MontaVista Software, Inc. */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, @@ -296,10 +296,9 @@ MACHINE_END MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") /* Maintainer: MontaVista Software, Inc. */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 1f8717ba13d..34efe75015e 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -42,9 +42,10 @@ static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdpg425_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = ixdpg425_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = ixdpg425_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index d4eb09a6286..a17ed79207a 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -116,11 +116,7 @@ /* NPE mailbox_status value for reset */ #define RESET_MBOX_STAT 0x0000F0F0 -#define NPE_A_FIRMWARE "NPE-A" -#define NPE_B_FIRMWARE "NPE-B" -#define NPE_C_FIRMWARE "NPE-C" - -const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE }; +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" }; #define print_npe(pri, npe, fmt, ...) \ printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) @@ -728,9 +724,6 @@ module_exit(npe_cleanup_module); MODULE_AUTHOR("Krzysztof Halasa"); MODULE_LICENSE("GPL v2"); -MODULE_FIRMWARE(NPE_A_FIRMWARE); -MODULE_FIRMWARE(NPE_B_FIRMWARE); -MODULE_FIRMWARE(NPE_C_FIRMWARE); EXPORT_SYMBOL(npe_names); EXPORT_SYMBOL(npe_running); diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c index 9d1b6b7c394..852f7c9f87d 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c @@ -14,7 +14,7 @@ #include #include -static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT; +struct qmgr_regs __iomem *qmgr_regs; static struct resource *mem_res; static spinlock_t qmgr_lock; static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ @@ -293,6 +293,12 @@ static int qmgr_init(void) if (mem_res == NULL) return -EBUSY; + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); + if (qmgr_regs == NULL) { + err = -ENOMEM; + goto error_map; + } + /* reset qmgr registers */ for (i = 0; i < 4; i++) { __raw_writel(0x33333333, &qmgr_regs->stat1[i]); @@ -341,6 +347,8 @@ static int qmgr_init(void) error_irq2: free_irq(IRQ_IXP4XX_QM1, NULL); error_irq: + iounmap(qmgr_regs); +error_map: release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); return err; } @@ -351,6 +359,7 @@ static void qmgr_remove(void) free_irq(IRQ_IXP4XX_QM2, NULL); synchronize_irq(IRQ_IXP4XX_QM1); synchronize_irq(IRQ_IXP4XX_QM2); + iounmap(qmgr_regs); release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); } @@ -360,6 +369,7 @@ module_exit(qmgr_remove); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Krzysztof Halasa"); +EXPORT_SYMBOL(qmgr_regs); EXPORT_SYMBOL(qmgr_set_irq); EXPORT_SYMBOL(qmgr_enable_irq); EXPORT_SYMBOL(qmgr_disable_irq); diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c deleted file mode 100644 index d114ccd2017..00000000000 --- a/arch/arm/mach-ixp4xx/miccpt-pci.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/miccpt-pci.c - * - * MICCPT board-level PCI initialization - * - * Copyright (C) 2002 Intel Corporation. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * Copyright (C) 2006 OMICRON electronics GmbH - * - * Author: Michael Jochum - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_DEV 4 -#define IRQ_LINES 4 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 1 -#define INTB 2 -#define INTC 3 -#define INTD 4 - - -void __init miccpt_pci_preinit(void) -{ - irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - ixp4xx_pci_preinit(); -} - -static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static int pci_irq_table[IRQ_LINES] = { - IXP4XX_GPIO_IRQ(INTA), - IXP4XX_GPIO_IRQ(INTB), - IXP4XX_GPIO_IRQ(INTC), - IXP4XX_GPIO_IRQ(INTD) - }; - - if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) - return pci_irq_table[(slot + pin - 2) % 4]; - - return -1; -} - -struct hw_pci miccpt_pci __initdata = { - .nr_controllers = 1, - .ops = &ixp4xx_ops, - .preinit = miccpt_pci_preinit, - .setup = ixp4xx_setup, - .map_irq = miccpt_map_irq, -}; - -int __init miccpt_pci_init(void) -{ - if (machine_is_miccpt()) - pci_common_init(&miccpt_pci); - return 0; -} - -subsys_initcall(miccpt_pci_init); diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index 8f0eba0a680..5434ccf553e 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -58,9 +58,10 @@ static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata nas100d_pci = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = nas100d_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = nas100d_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 33cb0955b6b..afb51879d9a 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -17,7 +17,7 @@ * Maintainers: http://www.nslu2-linux.org/ * */ -#include + #include #include #include @@ -32,6 +32,7 @@ #include #include #include +#include #define NAS100D_SDA_PIN 5 #define NAS100D_SCL_PIN 6 @@ -313,14 +314,12 @@ static void __init nas100d_init(void) MACHINE_START(NAS100D, "Iomega NAS 100d") /* Maintainer: www.nslu2-linux.org */ - .atag_offset = 0x100, + .boot_params = 0x00000100, .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .init_machine = nas100d_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 032defe111a..b57160535e4 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -54,9 +54,10 @@ static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata nslu2_pci = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = nslu2_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = nslu2_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index e2903faaebb..69e40f2cf09 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -16,7 +16,7 @@ * Maintainers: http://www.nslu2-linux.org/ * */ -#include + #include #include #include @@ -30,6 +30,7 @@ #include #include #include +#include #define NSLU2_SDA_PIN 7 #define NSLU2_SCL_PIN 6 @@ -299,14 +300,12 @@ static void __init nslu2_init(void) MACHINE_START(NSLU2, "Linksys NSLU2") /* Maintainer: www.nslu2-linux.org */ - .atag_offset = 0x100, + .boot_params = 0x00000100, .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &nslu2_timer, .init_machine = nslu2_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c deleted file mode 100644 index 158ddb79821..00000000000 --- a/arch/arm/mach-ixp4xx/omixp-setup.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/omixp-setup.c - * - * omicron ixp4xx board setup - * Copyright (C) 2009 OMICRON electronics GmbH - * - * based nslu2-setup.c, ixdp425-setup.c: - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_LEDS_CLASS -#include -#endif - -#include -#include -#include -#include -#include - -static struct resource omixp_flash_resources[] = { - { - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_MEM, - }, -}; - -static struct mtd_partition omixp_partitions[] = { - { - .name = "Recovery Bootloader", - .size = 0x00020000, - .offset = 0, - }, { - .name = "Calibration Data", - .size = 0x00020000, - .offset = 0x00020000, - }, { - .name = "Recovery FPGA", - .size = 0x00020000, - .offset = 0x00040000, - }, { - .name = "Release Bootloader", - .size = 0x00020000, - .offset = 0x00060000, - }, { - .name = "Release FPGA", - .size = 0x00020000, - .offset = 0x00080000, - }, { - .name = "Kernel", - .size = 0x00160000, - .offset = 0x000a0000, - }, { - .name = "Filesystem", - .size = 0x00C00000, - .offset = 0x00200000, - }, { - .name = "Persistent Storage", - .size = 0x00200000, - .offset = 0x00E00000, - }, -}; - -static struct flash_platform_data omixp_flash_data[] = { - { - .map_name = "cfi_probe", - .parts = omixp_partitions, - .nr_parts = ARRAY_SIZE(omixp_partitions), - }, { - .map_name = "cfi_probe", - .parts = NULL, - .nr_parts = 0, - }, -}; - -static struct platform_device omixp_flash_device[] = { - { - .name = "IXP4XX-Flash", - .id = 0, - .dev = { - .platform_data = &omixp_flash_data[0], - }, - .resource = &omixp_flash_resources[0], - .num_resources = 1, - }, { - .name = "IXP4XX-Flash", - .id = 1, - .dev = { - .platform_data = &omixp_flash_data[1], - }, - .resource = &omixp_flash_resources[1], - .num_resources = 1, - }, -}; - -/* Swap UART's - These boards have the console on UART2. The following - * configuration is used: - * ttyS0 .. UART2 - * ttyS1 .. UART1 - * This way standard images can be used with the kernel that expect - * the console on ttyS0. - */ -static struct resource omixp_uart_resources[] = { - { - .start = IXP4XX_UART2_BASE_PHYS, - .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IXP4XX_UART1_BASE_PHYS, - .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct plat_serial8250_port omixp_uart_data[] = { - { - .mapbase = IXP4XX_UART2_BASE_PHYS, - .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, - .irq = IRQ_IXP4XX_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, { - .mapbase = IXP4XX_UART1_BASE_PHYS, - .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, - .irq = IRQ_IXP4XX_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, { - /* list termination */ - } -}; - -static struct platform_device omixp_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = omixp_uart_data, - .num_resources = 2, - .resource = omixp_uart_resources, -}; - -static struct gpio_led mic256_led_pins[] = { - { - .name = "LED-A", - .gpio = 7, - }, -}; - -static struct gpio_led_platform_data mic256_led_data = { - .num_leds = ARRAY_SIZE(mic256_led_pins), - .leds = mic256_led_pins, -}; - -static struct platform_device mic256_leds = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &mic256_led_data, -}; - -/* Built-in 10/100 Ethernet MAC interfaces */ -static struct eth_plat_info ixdp425_plat_eth[] = { - { - .phy = 0, - .rxq = 3, - .txreadyq = 20, - }, { - .phy = 1, - .rxq = 4, - .txreadyq = 21, - }, -}; - -static struct platform_device ixdp425_eth[] = { - { - .name = "ixp4xx_eth", - .id = IXP4XX_ETH_NPEB, - .dev.platform_data = ixdp425_plat_eth, - }, { - .name = "ixp4xx_eth", - .id = IXP4XX_ETH_NPEC, - .dev.platform_data = ixdp425_plat_eth + 1, - }, -}; - - -static struct platform_device *devixp_pldev[] __initdata = { - &omixp_uart, - &omixp_flash_device[0], - &ixdp425_eth[0], - &ixdp425_eth[1], -}; - -static struct platform_device *mic256_pldev[] __initdata = { - &omixp_uart, - &omixp_flash_device[0], - &mic256_leds, - &ixdp425_eth[0], - &ixdp425_eth[1], -}; - -static struct platform_device *miccpt_pldev[] __initdata = { - &omixp_uart, - &omixp_flash_device[0], - &omixp_flash_device[1], - &ixdp425_eth[0], - &ixdp425_eth[1], -}; - -static void __init omixp_init(void) -{ - ixp4xx_sys_init(); - - /* 16MiB Boot Flash */ - omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0); - omixp_flash_resources[0].end = IXP4XX_EXP_BUS_END(0); - - /* 32 MiB Data Flash */ - omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2); - omixp_flash_resources[1].end = IXP4XX_EXP_BUS_END(2); - - if (machine_is_devixp()) - platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev)); - else if (machine_is_miccpt()) - platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev)); - else if (machine_is_mic256()) - platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev)); -} - -#ifdef CONFIG_MACH_DEVIXP -MACHINE_START(DEVIXP, "Omicron DEVIXP") - .atag_offset = 0x100, - .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, - .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, - .init_machine = omixp_init, - .restart = ixp4xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICCPT -MACHINE_START(MICCPT, "Omicron MICCPT") - .atag_offset = 0x100, - .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, - .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, - .init_machine = omixp_init, -#if defined(CONFIG_PCI) - .dma_zone_size = SZ_64M, -#endif - .restart = ixp4xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MIC256 -MACHINE_START(MIC256, "Omicron MIC256") - .atag_offset = 0x100, - .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, - .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, - .init_machine = omixp_init, - .restart = ixp4xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index a4220fa5e0c..0bc3f34c282 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -56,9 +56,10 @@ static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci vulcan_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = vulcan_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = vulcan_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c index 2798f435aaf..045336c833a 100644 --- a/arch/arm/mach-ixp4xx/vulcan-setup.c +++ b/arch/arm/mach-ixp4xx/vulcan-setup.c @@ -237,13 +237,11 @@ static void __init vulcan_init(void) MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan") /* Maintainer: Marc Zyngier */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = vulcan_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index c92e5b82af3..f27dfcfe811 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -46,9 +46,10 @@ static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci wg302v2_pci __initdata = { .nr_controllers = 1, - .ops = &ixp4xx_ops, .preinit = wg302v2_pci_preinit, + .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, .map_irq = wg302v2_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c index a785175b115..40b9fad800b 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-setup.c +++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c @@ -98,14 +98,12 @@ static void __init wg302v2_init(void) MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2") /* Maintainer: Imre Kaloz */ .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, - .atag_offset = 0x100, + .boot_params = 0x0100, .init_machine = wg302v2_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, #endif - .restart = ixp4xx_restart, MACHINE_END #endif -- cgit v1.2.2