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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-ixp23xx
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-ixp23xx')
-rw-r--r--arch/arm/mach-ixp23xx/Kconfig25
-rw-r--r--arch/arm/mach-ixp23xx/Makefile11
-rw-r--r--arch/arm/mach-ixp23xx/Makefile.boot2
-rw-r--r--arch/arm/mach-ixp23xx/core.c446
-rw-r--r--arch/arm/mach-ixp23xx/espresso.c93
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/debug-macro.S25
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/entry-macro.S37
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/hardware.h32
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/io.h52
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/irqs.h223
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/ixdp2351.h89
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/ixp23xx.h298
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/memory.h34
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/platform.h57
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/system.h33
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/time.h3
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/timex.h7
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/uncompress.h40
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/vmalloc.h10
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c336
-rw-r--r--arch/arm/mach-ixp23xx/pci.c293
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c180
22 files changed, 2326 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
new file mode 100644
index 00000000000..982670ec386
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Kconfig
@@ -0,0 +1,25 @@
1if ARCH_IXP23XX
2
3config ARCH_SUPPORTS_BIG_ENDIAN
4 bool
5 default y
6
7menu "Intel IXP23xx Implementation Options"
8
9comment "IXP23xx Platforms"
10
11config MACH_ESPRESSO
12 bool "Support IP Fabrics Double Espresso platform"
13 help
14
15config MACH_IXDP2351
16 bool "Support Intel IXDP2351 platform"
17 help
18
19config MACH_ROADRUNNER
20 bool "Support ADI RoadRunner platform"
21 help
22
23endmenu
24
25endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
new file mode 100644
index 00000000000..288b371b6d0
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel.
3#
4obj-y := core.o pci.o
5obj-m :=
6obj-n :=
7obj- :=
8
9obj-$(CONFIG_MACH_ESPRESSO) += espresso.o
10obj-$(CONFIG_MACH_IXDP2351) += ixdp2351.o
11obj-$(CONFIG_MACH_ROADRUNNER) += roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
new file mode 100644
index 00000000000..d5561ad15ba
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile.boot
@@ -0,0 +1,2 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
new file mode 100644
index 00000000000..a1bee33d183
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -0,0 +1,446 @@
1/*
2 * arch/arm/mach-ixp23xx/core.c
3 *
4 * Core routines for IXP23xx chips
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/serial_8250.h>
26#include <linux/serial_core.h>
27#include <linux/device.h>
28#include <linux/mm.h>
29#include <linux/time.h>
30#include <linux/timex.h>
31
32#include <asm/types.h>
33#include <asm/setup.h>
34#include <asm/memory.h>
35#include <mach/hardware.h>
36#include <asm/irq.h>
37#include <asm/system.h>
38#include <asm/tlbflush.h>
39#include <asm/pgtable.h>
40
41#include <asm/mach/map.h>
42#include <asm/mach/time.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/arch.h>
45
46
47/*************************************************************************
48 * Chip specific mappings shared by all IXP23xx systems
49 *************************************************************************/
50static struct map_desc ixp23xx_io_desc[] __initdata = {
51 { /* XSI-CPP CSRs */
52 .virtual = IXP23XX_XSI2CPP_CSR_VIRT,
53 .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
54 .length = IXP23XX_XSI2CPP_CSR_SIZE,
55 .type = MT_DEVICE,
56 }, { /* Expansion Bus Config */
57 .virtual = IXP23XX_EXP_CFG_VIRT,
58 .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
59 .length = IXP23XX_EXP_CFG_SIZE,
60 .type = MT_DEVICE,
61 }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
62 .virtual = IXP23XX_PERIPHERAL_VIRT,
63 .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
64 .length = IXP23XX_PERIPHERAL_SIZE,
65 .type = MT_DEVICE,
66 }, { /* CAP CSRs */
67 .virtual = IXP23XX_CAP_CSR_VIRT,
68 .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
69 .length = IXP23XX_CAP_CSR_SIZE,
70 .type = MT_DEVICE,
71 }, { /* MSF CSRs */
72 .virtual = IXP23XX_MSF_CSR_VIRT,
73 .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
74 .length = IXP23XX_MSF_CSR_SIZE,
75 .type = MT_DEVICE,
76 }, { /* PCI I/O Space */
77 .virtual = IXP23XX_PCI_IO_VIRT,
78 .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
79 .length = IXP23XX_PCI_IO_SIZE,
80 .type = MT_DEVICE,
81 }, { /* PCI Config Space */
82 .virtual = IXP23XX_PCI_CFG_VIRT,
83 .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
84 .length = IXP23XX_PCI_CFG_SIZE,
85 .type = MT_DEVICE,
86 }, { /* PCI local CFG CSRs */
87 .virtual = IXP23XX_PCI_CREG_VIRT,
88 .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
89 .length = IXP23XX_PCI_CREG_SIZE,
90 .type = MT_DEVICE,
91 }, { /* PCI MEM Space */
92 .virtual = IXP23XX_PCI_MEM_VIRT,
93 .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
94 .length = IXP23XX_PCI_MEM_SIZE,
95 .type = MT_DEVICE,
96 }
97};
98
99void __init ixp23xx_map_io(void)
100{
101 iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
102}
103
104
105/***************************************************************************
106 * IXP23xx Interrupt Handling
107 ***************************************************************************/
108enum ixp23xx_irq_type {
109 IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
110};
111
112static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
113
114static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type)
115{
116 int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
117 u32 int_style;
118 enum ixp23xx_irq_type irq_type;
119 volatile u32 *int_reg;
120
121 /*
122 * Only GPIOs 6-15 are wired to interrupts on IXP23xx
123 */
124 if (line < 6 || line > 15)
125 return -EINVAL;
126
127 switch (type) {
128 case IRQ_TYPE_EDGE_BOTH:
129 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
130 irq_type = IXP23XX_IRQ_EDGE;
131 break;
132 case IRQ_TYPE_EDGE_RISING:
133 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
134 irq_type = IXP23XX_IRQ_EDGE;
135 break;
136 case IRQ_TYPE_EDGE_FALLING:
137 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
138 irq_type = IXP23XX_IRQ_EDGE;
139 break;
140 case IRQ_TYPE_LEVEL_HIGH:
141 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
142 irq_type = IXP23XX_IRQ_LEVEL;
143 break;
144 case IRQ_TYPE_LEVEL_LOW:
145 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
146 irq_type = IXP23XX_IRQ_LEVEL;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 ixp23xx_config_irq(d->irq, irq_type);
153
154 if (line >= 8) { /* pins 8-15 */
155 line -= 8;
156 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
157 } else { /* pins 0-7 */
158 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
159 }
160
161 /*
162 * Clear pending interrupts
163 */
164 *IXP23XX_GPIO_GPISR = (1 << line);
165
166 /* Clear the style for the appropriate pin */
167 *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
168 (line * IXP23XX_GPIO_STYLE_SIZE));
169
170 /* Set the new style */
171 *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
172
173 return 0;
174}
175
176static void ixp23xx_irq_mask(struct irq_data *d)
177{
178 volatile unsigned long *intr_reg;
179 unsigned int irq = d->irq;
180
181 if (irq >= 56)
182 irq += 8;
183
184 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
185 *intr_reg &= ~(1 << (irq % 32));
186}
187
188static void ixp23xx_irq_ack(struct irq_data *d)
189{
190 int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
191
192 if ((line < 6) || (line > 15))
193 return;
194
195 *IXP23XX_GPIO_GPISR = (1 << line);
196}
197
198/*
199 * Level triggered interrupts on GPIO lines can only be cleared when the
200 * interrupt condition disappears.
201 */
202static void ixp23xx_irq_level_unmask(struct irq_data *d)
203{
204 volatile unsigned long *intr_reg;
205 unsigned int irq = d->irq;
206
207 ixp23xx_irq_ack(d);
208
209 if (irq >= 56)
210 irq += 8;
211
212 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
213 *intr_reg |= (1 << (irq % 32));
214}
215
216static void ixp23xx_irq_edge_unmask(struct irq_data *d)
217{
218 volatile unsigned long *intr_reg;
219 unsigned int irq = d->irq;
220
221 if (irq >= 56)
222 irq += 8;
223
224 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
225 *intr_reg |= (1 << (irq % 32));
226}
227
228static struct irq_chip ixp23xx_irq_level_chip = {
229 .irq_ack = ixp23xx_irq_mask,
230 .irq_mask = ixp23xx_irq_mask,
231 .irq_unmask = ixp23xx_irq_level_unmask,
232 .irq_set_type = ixp23xx_irq_set_type
233};
234
235static struct irq_chip ixp23xx_irq_edge_chip = {
236 .irq_ack = ixp23xx_irq_ack,
237 .irq_mask = ixp23xx_irq_mask,
238 .irq_unmask = ixp23xx_irq_edge_unmask,
239 .irq_set_type = ixp23xx_irq_set_type
240};
241
242static void ixp23xx_pci_irq_mask(struct irq_data *d)
243{
244 unsigned int irq = d->irq;
245
246 *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
247}
248
249static void ixp23xx_pci_irq_unmask(struct irq_data *d)
250{
251 unsigned int irq = d->irq;
252
253 *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
254}
255
256/*
257 * TODO: Should this just be done at ASM level?
258 */
259static void pci_handler(unsigned int irq, struct irq_desc *desc)
260{
261 u32 pci_interrupt;
262 unsigned int irqno;
263
264 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
265
266 desc->irq_data.chip->irq_ack(&desc->irq_data);
267
268 /* See which PCI_INTA, or PCI_INTB interrupted */
269 if (pci_interrupt & (1 << 26)) {
270 irqno = IRQ_IXP23XX_INTB;
271 } else if (pci_interrupt & (1 << 27)) {
272 irqno = IRQ_IXP23XX_INTA;
273 } else {
274 BUG();
275 }
276
277 generic_handle_irq(irqno);
278
279 desc->irq_data.chip->irq_unmask(&desc->irq_data);
280}
281
282static struct irq_chip ixp23xx_pci_irq_chip = {
283 .irq_ack = ixp23xx_pci_irq_mask,
284 .irq_mask = ixp23xx_pci_irq_mask,
285 .irq_unmask = ixp23xx_pci_irq_unmask
286};
287
288static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
289{
290 switch (type) {
291 case IXP23XX_IRQ_LEVEL:
292 irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
293 handle_level_irq);
294 break;
295 case IXP23XX_IRQ_EDGE:
296 irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
297 handle_edge_irq);
298 break;
299 }
300 set_irq_flags(irq, IRQF_VALID);
301}
302
303void __init ixp23xx_init_irq(void)
304{
305 int irq;
306
307 /* Route everything to IRQ */
308 *IXP23XX_INTR_SEL1 = 0x0;
309 *IXP23XX_INTR_SEL2 = 0x0;
310 *IXP23XX_INTR_SEL3 = 0x0;
311 *IXP23XX_INTR_SEL4 = 0x0;
312
313 /* Mask all sources */
314 *IXP23XX_INTR_EN1 = 0x0;
315 *IXP23XX_INTR_EN2 = 0x0;
316 *IXP23XX_INTR_EN3 = 0x0;
317 *IXP23XX_INTR_EN4 = 0x0;
318
319 /*
320 * Configure all IRQs for level-sensitive operation
321 */
322 for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
323 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
324 }
325
326 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
327 irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
328 handle_level_irq);
329 set_irq_flags(irq, IRQF_VALID);
330 }
331
332 irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
333}
334
335
336/*************************************************************************
337 * Timer-tick functions for IXP23xx
338 *************************************************************************/
339#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
340
341static unsigned long next_jiffy_time;
342
343static unsigned long
344ixp23xx_gettimeoffset(void)
345{
346 unsigned long elapsed;
347
348 elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
349
350 return elapsed / CLOCK_TICKS_PER_USEC;
351}
352
353static irqreturn_t
354ixp23xx_timer_interrupt(int irq, void *dev_id)
355{
356 /* Clear Pending Interrupt by writing '1' to it */
357 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
358 while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
359 timer_tick();
360 next_jiffy_time += LATCH;
361 }
362
363 return IRQ_HANDLED;
364}
365
366static struct irqaction ixp23xx_timer_irq = {
367 .name = "IXP23xx Timer Tick",
368 .handler = ixp23xx_timer_interrupt,
369 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
370};
371
372void __init ixp23xx_init_timer(void)
373{
374 /* Clear Pending Interrupt by writing '1' to it */
375 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
376
377 /* Setup the Timer counter value */
378 *IXP23XX_TIMER1_RELOAD =
379 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
380
381 *IXP23XX_TIMER_CONT = 0;
382 next_jiffy_time = LATCH;
383
384 /* Connect the interrupt handler and enable the interrupt */
385 setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
386}
387
388struct sys_timer ixp23xx_timer = {
389 .init = ixp23xx_init_timer,
390 .offset = ixp23xx_gettimeoffset,
391};
392
393
394/*************************************************************************
395 * IXP23xx Platform Initialization
396 *************************************************************************/
397static struct resource ixp23xx_uart_resources[] = {
398 {
399 .start = IXP23XX_UART1_PHYS,
400 .end = IXP23XX_UART1_PHYS + 0x0fff,
401 .flags = IORESOURCE_MEM
402 }, {
403 .start = IXP23XX_UART2_PHYS,
404 .end = IXP23XX_UART2_PHYS + 0x0fff,
405 .flags = IORESOURCE_MEM
406 }
407};
408
409static struct plat_serial8250_port ixp23xx_uart_data[] = {
410 {
411 .mapbase = IXP23XX_UART1_PHYS,
412 .membase = (char *)(IXP23XX_UART1_VIRT + 3),
413 .irq = IRQ_IXP23XX_UART1,
414 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
415 .iotype = UPIO_MEM,
416 .regshift = 2,
417 .uartclk = IXP23XX_UART_XTAL,
418 }, {
419 .mapbase = IXP23XX_UART2_PHYS,
420 .membase = (char *)(IXP23XX_UART2_VIRT + 3),
421 .irq = IRQ_IXP23XX_UART2,
422 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
423 .iotype = UPIO_MEM,
424 .regshift = 2,
425 .uartclk = IXP23XX_UART_XTAL,
426 },
427 { },
428};
429
430static struct platform_device ixp23xx_uart = {
431 .name = "serial8250",
432 .id = 0,
433 .dev.platform_data = ixp23xx_uart_data,
434 .num_resources = 2,
435 .resource = ixp23xx_uart_resources,
436};
437
438static struct platform_device *ixp23xx_devices[] __initdata = {
439 &ixp23xx_uart,
440};
441
442void __init ixp23xx_sys_init(void)
443{
444 *IXP23XX_EXP_UNIT_FUSE |= 0xf;
445 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
446}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
new file mode 100644
index 00000000000..e25e5fe183b
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -0,0 +1,93 @@
1/*
2 * arch/arm/mach-ixp23xx/espresso.c
3 *
4 * Double Espresso-specific routines
5 *
6 * Author: Lennert Buytenhek <buytenh@wantstofly.org>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/spinlock.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/bitops.h>
21#include <linux/ioport.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_core.h>
24#include <linux/device.h>
25#include <linux/mm.h>
26#include <linux/pci.h>
27#include <linux/mtd/physmap.h>
28
29#include <asm/types.h>
30#include <asm/setup.h>
31#include <asm/memory.h>
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35#include <asm/system.h>
36#include <asm/tlbflush.h>
37#include <asm/pgtable.h>
38
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/pci.h>
43
44static int __init espresso_pci_init(void)
45{
46 if (machine_is_espresso())
47 ixp23xx_pci_slave_init();
48
49 return 0;
50};
51subsys_initcall(espresso_pci_init);
52
53static struct physmap_flash_data espresso_flash_data = {
54 .width = 2,
55};
56
57static struct resource espresso_flash_resource = {
58 .start = 0x90000000,
59 .end = 0x91ffffff,
60 .flags = IORESOURCE_MEM,
61};
62
63static struct platform_device espresso_flash = {
64 .name = "physmap-flash",
65 .id = 0,
66 .dev = {
67 .platform_data = &espresso_flash_data,
68 },
69 .num_resources = 1,
70 .resource = &espresso_flash_resource,
71};
72
73static void __init espresso_init(void)
74{
75 platform_device_register(&espresso_flash);
76
77 /*
78 * Mark flash as writeable.
79 */
80 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
81 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
82
83 ixp23xx_sys_init();
84}
85
86MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
87 /* Maintainer: Lennert Buytenhek */
88 .map_io = ixp23xx_map_io,
89 .init_irq = ixp23xx_init_irq,
90 .timer = &ixp23xx_timer,
91 .boot_params = 0x00000100,
92 .init_machine = espresso_init,
93MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
new file mode 100644
index 00000000000..f7c6eef7fa2
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
@@ -0,0 +1,25 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <mach/ixp23xx.h>
14
15 .macro addruart, rp, rv
16 ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical
17 ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual
18#ifdef __ARMEB__
19 orr \rp, \rp, #0x00000003
20 orr \rv, \rv, #0x00000003
21#endif
22 .endm
23
24#define UART_SHIFT 2
25#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
new file mode 100644
index 00000000000..3f5338a7bbd
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/entry-macro.S
3 */
4
5 .macro disable_fiq
6 .endm
7
8 .macro get_irqnr_preamble, base, tmp
9 .endm
10
11 .macro arch_ret_to_user, tmp1, tmp2
12 .endm
13
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
16 ldr \irqnr, [\irqnr] @ get interrupt number
17 cmp \irqnr, #0x0 @ spurious interrupt ?
18 movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits
19 subne \irqnr, \irqnr, #1 @ convert to 0 based
20
21#if 0
22 cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
23 bne 1001f
24 mov \irqnr, #IRQ_IXP23XX_INTA
25
26 ldr \irqnr, =0xf5000030
27
28 mov \tmp, #(1<<26)
29 tst \irqnr, \tmp
30 movne \irqnr, #IRQ_IXP23XX_INTB
31
32 mov \tmp, #(1<<27)
33 tst \irqnr, \tmp
34 movne \irqnr, #IRQ_IXP23XX_INTA
351001:
36#endif
37 .endm
diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h
new file mode 100644
index 00000000000..60e55fa1023
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/hardware.h
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/hardware.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 * Copyricht (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Hardware definitions for IXP23XX based systems
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17/* PCI IO info */
18
19#include "ixp23xx.h"
20
21/*
22 * Platform helper functions
23 */
24#include "platform.h"
25
26/*
27 * Platform-specific headers
28 */
29#include "ixdp2351.h"
30
31
32#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
new file mode 100644
index 00000000000..a1749d0fd89
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -0,0 +1,52 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2003-2005 Intel Corp.
8 * Copyright (C) 2005 MontaVista Software, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IO_H
16#define __ASM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21#define __mem_pci(a) (a)
22
23static inline void __iomem *
24ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
25{
26 if (addr >= IXP23XX_PCI_MEM_START &&
27 addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
28 if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
29 return NULL;
30
31 return (void __iomem *)
32 ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
33 }
34
35 return __arm_ioremap(addr, size, mtype);
36}
37
38static inline void
39ixp23xx_iounmap(void __iomem *addr)
40{
41 if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
42 (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
43 return;
44
45 __iounmap(addr);
46}
47
48#define __arch_ioremap ixp23xx_ioremap
49#define __arch_iounmap ixp23xx_iounmap
50
51
52#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/irqs.h b/arch/arm/mach-ixp23xx/include/mach/irqs.h
new file mode 100644
index 00000000000..3af33a04b8a
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/irqs.h
@@ -0,0 +1,223 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/irqs.h
3 *
4 * IRQ definitions for IXP23XX based systems
5 *
6 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Copyright (C) 2003-2004 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IRQS_H
16#define __ASM_ARCH_IRQS_H
17
18#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1
19#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS
20
21
22#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */
23#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */
24#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */
25#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */
26#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */
27#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */
28#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */
29#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */
30#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */
31#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */
32#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */
33#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */
34#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */
35#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */
36#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */
37#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */
38#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */
39#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */
40#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */
41#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */
42#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */
43#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */
44#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */
45#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */
46#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */
47#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */
48#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */
49#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */
50#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */
51#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */
52#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */
53#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */
54#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */
55#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */
56#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */
57#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */
58#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */
59#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */
60#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */
61#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */
62#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */
63#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */
64#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */
65#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */
66#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */
67#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */
68#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */
69#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */
70#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */
71#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */
72#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */
73#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */
74#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */
75#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */
76#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */
77#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */
78#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */
79#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */
80#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */
81#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */
82#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */
83#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */
84#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */
85#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */
86#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */
87#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */
88#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */
89#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */
90#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */
91#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */
92#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */
93#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */
94#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */
95#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */
96#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */
97#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */
98#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */
99#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */
100#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */
101#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */
102#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */
103#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */
104#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */
105#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */
106#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */
107#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */
108#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */
109#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */
110#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */
111#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */
112#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */
113#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */
114#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */
115#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */
116#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */
117#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */
118#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */
119#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */
120#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */
121#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */
122#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */
123#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */
124#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */
125#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */
126#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */
127#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */
128#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */
129#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */
130#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */
131#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */
132#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */
133#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */
134#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */
135#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */
136#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */
137#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */
138#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */
139#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */
140#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */
141#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */
142
143#define NUM_IXP23XX_RAW_IRQS 120
144
145#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */
146#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */
147
148#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1)
149
150/*
151 * We default to 32 per-board IRQs. Increase this number if you need
152 * more, but keep it realistic.
153 */
154#define NR_IXP23XX_MACH_IRQS 32
155
156#define NR_IRQS (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
157
158#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq))
159
160
161/*
162 * IXDP2351-specific interrupts
163 */
164
165/*
166 * External PCI interrupts signaled through INTB
167 *
168 */
169#define IXDP2351_INTB_IRQ_BASE 0
170#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0)
171#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1)
172#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2)
173#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3)
174#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4)
175#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5)
176#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6)
177#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7)
178#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8)
179
180#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0))
181#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq))
182#define IXDP2351_INTB_IRQ_VALID 0x01FF
183#define IXDP2351_INTB_IRQ_NUM 16
184
185/*
186 * Other external interrupts signaled through INTA
187 */
188#define IXDP2351_INTA_IRQ_BASE 16
189#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16)
190#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17)
191#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18)
192#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19)
193#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20)
194#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21)
195#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24)
196#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25)
197#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26)
198#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27)
199#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28)
200#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29)
201#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30)
202#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31)
203
204#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16))
205#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq))
206#define IXDP2351_INTA_IRQ_VALID 0xFF3F
207#define IXDP2351_INTA_IRQ_NUM 16
208
209
210/*
211 * ADI RoadRunner IRQs
212 */
213#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA
214#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB
215#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11
216#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12
217
218/*
219 * Put new board definitions here
220 */
221
222
223#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
new file mode 100644
index 00000000000..663951027de
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
@@ -0,0 +1,89 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
3 *
4 * Register and other defines for IXDP2351
5 *
6 * Copyright (c) 2002-2004 Intel Corp.
7 * Copytight (c) 2005 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __ASM_ARCH_IXDP2351_H
16#define __ASM_ARCH_IXDP2351_H
17
18/*
19 * NP module memory map
20 */
21#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE)
22#define IXDP2351_NP_PHYS_SIZE 0x00100000
23#define IXDP2351_NP_VIRT_BASE 0xeff00000
24
25#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE)
26#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16)
27
28#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
29
30#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
31
32#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00)
33#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02)
34#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04)
35
36/*
37 * Base board module memory map
38 */
39
40#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE)
41#define IXDP2351_BB_SIZE 0x01000000
42#define IXDP2351_BB_BASE_VIRT (0xee000000)
43
44#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset)
45
46#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0)
47#define IXDP2351_NVRAM_SIZE (0x20000)
48
49#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000)
50#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0)
51#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000)
52#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000)
53#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000)
54#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000)
55
56/*
57 * On board CPLD registers
58 */
59#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
60
61#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00)
62#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04)
63
64#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA
65#define IXDP2351_CPLD_RESET1_ENABLE 0x8000
66
67#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08)
68#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
69#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
70#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18)
71#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C)
72#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */
73#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */
74#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */
75#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */
76#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28)
77#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C)
78 /* Interrupt bits are defined in irqs.h */
79#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30)
80#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34)
81
82/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */
83/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */
84/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */
85/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */
86/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */
87
88
89#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
new file mode 100644
index 00000000000..6d02481b1d6
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
@@ -0,0 +1,298 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
3 *
4 * Register definitions for IXP23XX
5 *
6 * Copyright (C) 2003-2005 Intel Corporation.
7 * Copyright (C) 2005 MontaVista Software, Inc.
8 *
9 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_IXP23XX_H
17#define __ASM_ARCH_IXP23XX_H
18
19/*
20 * IXP2300 linux memory map:
21 *
22 * virt phys size
23 * fffd0000 a0000000 64K XSI2CPP_CSR
24 * fffc0000 c4000000 4K EXP_CFG
25 * fff00000 c8000000 64K PERIPHERAL
26 * fe000000 1c0000000 16M CAP_CSR
27 * fd000000 1c8000000 16M MSF_CSR
28 * fb000000 16M ---
29 * fa000000 1d8000000 32M PCI_IO
30 * f8000000 1da000000 32M PCI_CFG
31 * f6000000 1de000000 32M PCI_CREG
32 * f4000000 32M ---
33 * f0000000 1e0000000 64M PCI_MEM
34 * e[c-f]000000 per-platform mappings
35 */
36
37
38/****************************************************************************
39 * Static mappings.
40 ****************************************************************************/
41#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000
42#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000
43#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000
44
45#define IXP23XX_EXP_CFG_PHYS 0xc4000000
46#define IXP23XX_EXP_CFG_VIRT 0xfffc0000
47#define IXP23XX_EXP_CFG_SIZE 0x00001000
48
49#define IXP23XX_PERIPHERAL_PHYS 0xc8000000
50#define IXP23XX_PERIPHERAL_VIRT 0xfff00000
51#define IXP23XX_PERIPHERAL_SIZE 0x00010000
52
53#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL
54#define IXP23XX_CAP_CSR_VIRT 0xfe000000
55#define IXP23XX_CAP_CSR_SIZE 0x01000000
56
57#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL
58#define IXP23XX_MSF_CSR_VIRT 0xfd000000
59#define IXP23XX_MSF_CSR_SIZE 0x01000000
60
61#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL
62#define IXP23XX_PCI_IO_VIRT 0xfa000000
63#define IXP23XX_PCI_IO_SIZE 0x02000000
64
65#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL
66#define IXP23XX_PCI_CFG_VIRT 0xf8000000
67#define IXP23XX_PCI_CFG_SIZE 0x02000000
68#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT
69#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000)
70
71#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL
72#define IXP23XX_PCI_CREG_VIRT 0xf6000000
73#define IXP23XX_PCI_CREG_SIZE 0x02000000
74#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000)
75
76#define IXP23XX_PCI_MEM_START 0xe0000000
77#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL
78#define IXP23XX_PCI_MEM_VIRT 0xf0000000
79#define IXP23XX_PCI_MEM_SIZE 0x04000000
80
81
82/****************************************************************************
83 * XSI2CPP CSRs.
84 ****************************************************************************/
85#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
86#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8)
87#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19)
88#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20)
89#define IXP23XX_CPP2XSI_COH_OFF (1 << 21)
90
91
92/****************************************************************************
93 * Expansion Bus Config.
94 ****************************************************************************/
95#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
96#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00)
97#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04)
98#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08)
99#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c)
100#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10)
101#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14)
102#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18)
103#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c)
104#define IXP23XX_FLASH_WRITABLE (0x2)
105#define IXP23XX_FLASH_BUS8 (0x1)
106
107#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20)
108#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24)
109#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31)
110#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22)
111#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21)
112#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19)
113#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18)
114#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16)
115#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14)
116#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13)
117#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12)
118#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5)
119#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4)
120#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3)
121#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2)
122#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1)
123#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0)
124
125#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28)
126#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30)
127#define IXP23XX_EXP_CFG_FUSE IXP23XX_EXP_CFG_REG(0x34)
128
129#define IXP23XX_EXP_BUS_PHYS 0x90000000
130#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000
131
132#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000)
133#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000)
134#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000)
135#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000)
136#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000)
137#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000)
138#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000)
139#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000)
140
141
142/****************************************************************************
143 * Peripherals.
144 ****************************************************************************/
145#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000)
146#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000)
147#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000)
148#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000)
149#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000)
150#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000)
151#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000)
152#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000)
153#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000)
154#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000)
155#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000)
156#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000)
157#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000)
158#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000)
159
160#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000)
161#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000)
162#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000)
163#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000)
164#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000)
165#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000)
166#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000)
167#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000)
168#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000)
169#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000)
170#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000)
171#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000)
172#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000)
173#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000)
174
175
176/****************************************************************************
177 * Interrupt controller.
178 ****************************************************************************/
179#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
180#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00)
181#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04)
182#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08)
183#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c)
184#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10)
185#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14)
186#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18)
187#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c)
188#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20)
189#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24)
190#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28)
191#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c)
192#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30)
193#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34)
194#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38)
195#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c)
196#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54
197
198
199/****************************************************************************
200 * GPIO.
201 ****************************************************************************/
202#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
203#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00)
204#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04)
205#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08)
206#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c)
207#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10)
208#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14)
209#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18)
210#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c)
211
212#define IXP23XX_GPIO_STYLE_MASK 0x7
213#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0
214#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1
215#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2
216#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
217#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
218
219#define IXP23XX_GPIO_STYLE_SIZE 3
220
221
222/****************************************************************************
223 * Timer.
224 ****************************************************************************/
225#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
226#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00)
227#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04)
228#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08)
229#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c)
230#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10)
231#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14)
232#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18)
233#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c)
234#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e
235#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20)
236#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24)
237#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28)
238
239#define IXP23XX_TIMER_ENABLE (1 << 0)
240#define IXP23XX_TIMER_ONE_SHOT (1 << 1)
241/* Low order bits of reload value ignored */
242#define IXP23XX_TIMER_RELOAD_MASK (0x3)
243#define IXP23XX_TIMER_DISABLED (0x0)
244#define IXP23XX_TIMER1_INT_PEND (1 << 0)
245#define IXP23XX_TIMER2_INT_PEND (1 << 1)
246#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2)
247#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3)
248#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
249
250
251/****************************************************************************
252 * CAP CSRs.
253 ****************************************************************************/
254#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
255#define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00)
256#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04)
257#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08)
258#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c)
259#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10)
260#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18)
261
262#define IXP23XX_ENABLE_WATCHDOG (1 << 24)
263#define IXP23XX_SHPC_INIT_COMP (1 << 21)
264#define IXP23XX_RST_ALL (1 << 16)
265#define IXP23XX_RESET_PCI (1 << 2)
266#define IXP23XX_PCI_UNIT_RESET (1 << 1)
267#define IXP23XX_XSCALE_RESET (1 << 0)
268
269#define IXP23XX_UENGINE_CSR_VIRT_BASE (IXP23XX_CAP_CSR_VIRT + 0x18000)
270
271
272/****************************************************************************
273 * PCI CSRs.
274 ****************************************************************************/
275#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
276#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04)
277#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14)
278#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18)
279
280
281#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
282#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030)
283#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034)
284#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
285#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
286#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c)
287#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140)
288#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148)
289#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c)
290#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150)
291#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150)
292#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154)
293#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158)
294#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c)
295#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160)
296
297
298#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
new file mode 100644
index 00000000000..6cf0704e946
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/memory.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/memory.h
3 *
4 * Copyright (c) 2003-2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15#include <mach/hardware.h>
16
17/*
18 * Physical DRAM offset.
19 */
20#define PLAT_PHYS_OFFSET (0x00000000)
21
22#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)
23
24#define __phys_to_bus(x) ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
25#define __bus_to_phys(x) ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
26
27#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
28#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
29#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
30#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
31
32#define arch_is_coherent() 1
33
34#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h
new file mode 100644
index 00000000000..db9d9416e5e
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/platform.h
@@ -0,0 +1,57 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASSEMBLY__
16
17static inline unsigned long ixp2000_reg_read(volatile void *reg)
18{
19 return *((volatile unsigned long *)reg);
20}
21
22static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
23{
24 *((volatile unsigned long *)reg) = val;
25}
26
27static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
28{
29 *((volatile unsigned long *)reg) = val;
30}
31
32struct pci_sys_data;
33
34void ixp23xx_map_io(void);
35void ixp23xx_init_irq(void);
36void ixp23xx_sys_init(void);
37int ixp23xx_pci_setup(int, struct pci_sys_data *);
38void ixp23xx_pci_preinit(void);
39struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
40void ixp23xx_pci_slave_init(void);
41
42extern struct sys_timer ixp23xx_timer;
43
44#define IXP23XX_UART_XTAL 14745600
45
46#ifndef __ASSEMBLY__
47/*
48 * Is system memory on the XSI or CPP bus?
49 */
50static inline unsigned ixp23xx_cpp_boot(void)
51{
52 return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
53}
54#endif
55
56
57#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
new file mode 100644
index 00000000000..8920ff2dff1
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/system.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/system.h
3 *
4 * Copyright (C) 2003 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <mach/hardware.h>
12#include <asm/mach-types.h>
13
14static inline void arch_idle(void)
15{
16#if 0
17 if (!hlt_counter)
18 cpu_do_idle();
19#endif
20}
21
22static inline void arch_reset(char mode, const char *cmd)
23{
24 /* First try machine specific support */
25 if (machine_is_ixdp2351()) {
26 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
27 (void) *IXDP2351_CPLD_RESET1_REG;
28 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
29 }
30
31 /* Use on-chip reset capability */
32 *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
33}
diff --git a/arch/arm/mach-ixp23xx/include/mach/time.h b/arch/arm/mach-ixp23xx/include/mach/time.h
new file mode 100644
index 00000000000..b61dafc884a
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/time.h
@@ -0,0 +1,3 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/time.h
3 */
diff --git a/arch/arm/mach-ixp23xx/include/mach/timex.h b/arch/arm/mach-ixp23xx/include/mach/timex.h
new file mode 100644
index 00000000000..e341e9cf9c3
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/timex.h
@@ -0,0 +1,7 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/timex.h
3 *
4 * XScale architecture timex specifications
5 */
6
7#define CLOCK_TICK_RATE 75000000
diff --git a/arch/arm/mach-ixp23xx/include/mach/uncompress.h b/arch/arm/mach-ixp23xx/include/mach/uncompress.h
new file mode 100644
index 00000000000..8b4c358d2c0
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/uncompress.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/uncompress.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include <mach/ixp23xx.h>
15#include <linux/serial_reg.h>
16
17#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS)
18
19static inline void putc(char c)
20{
21 int j;
22
23 for (j = 0; j < 0x1000; j++) {
24 if (UART_BASE[UART_LSR] & UART_LSR_THRE)
25 break;
26 barrier();
27 }
28
29 UART_BASE[UART_TX] = c;
30}
31
32static inline void flush(void)
33{
34}
35
36#define arch_decomp_setup()
37#define arch_decomp_wdog()
38
39
40#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
new file mode 100644
index 00000000000..896c56a1c00
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/vmalloc.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc.
5 *
6 * NPU mappings end at 0xf0000000 and we allocate 64MB for board
7 * specific static I/O.
8 */
9
10#define VMALLOC_END (0xec000000UL)
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
new file mode 100644
index 00000000000..ec028e35f40
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -0,0 +1,336 @@
1/*
2 * arch/arm/mach-ixp23xx/ixdp2351.c
3 *
4 * IXDP2351 board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/ioport.h>
27#include <linux/serial_8250.h>
28#include <linux/serial_core.h>
29#include <linux/device.h>
30#include <linux/mm.h>
31#include <linux/pci.h>
32#include <linux/mtd/physmap.h>
33
34#include <asm/types.h>
35#include <asm/setup.h>
36#include <asm/memory.h>
37#include <mach/hardware.h>
38#include <asm/mach-types.h>
39#include <asm/system.h>
40#include <asm/tlbflush.h>
41#include <asm/pgtable.h>
42
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/pci.h>
47
48/*
49 * IXDP2351 Interrupt Handling
50 */
51static void ixdp2351_inta_mask(struct irq_data *d)
52{
53 *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
54}
55
56static void ixdp2351_inta_unmask(struct irq_data *d)
57{
58 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
59}
60
61static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
62{
63 u16 ex_interrupt =
64 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
65 int i;
66
67 desc->irq_data.chip->irq_mask(&desc->irq_data);
68
69 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
70 if (ex_interrupt & (1 << i)) {
71 int cpld_irq =
72 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
73 generic_handle_irq(cpld_irq);
74 }
75 }
76
77 desc->irq_data.chip->irq_unmask(&desc->irq_data);
78}
79
80static struct irq_chip ixdp2351_inta_chip = {
81 .irq_ack = ixdp2351_inta_mask,
82 .irq_mask = ixdp2351_inta_mask,
83 .irq_unmask = ixdp2351_inta_unmask
84};
85
86static void ixdp2351_intb_mask(struct irq_data *d)
87{
88 *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
89}
90
91static void ixdp2351_intb_unmask(struct irq_data *d)
92{
93 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
94}
95
96static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
97{
98 u16 ex_interrupt =
99 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
100 int i;
101
102 desc->irq_data.chip->irq_ack(&desc->irq_data);
103
104 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
105 if (ex_interrupt & (1 << i)) {
106 int cpld_irq =
107 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
108 generic_handle_irq(cpld_irq);
109 }
110 }
111
112 desc->irq_data.chip->irq_unmask(&desc->irq_data);
113}
114
115static struct irq_chip ixdp2351_intb_chip = {
116 .irq_ack = ixdp2351_intb_mask,
117 .irq_mask = ixdp2351_intb_mask,
118 .irq_unmask = ixdp2351_intb_unmask
119};
120
121void __init ixdp2351_init_irq(void)
122{
123 int irq;
124
125 /* Mask all interrupts from CPLD, disable simulation */
126 *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
127 *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
128 *IXDP2351_CPLD_INTA_SIM_REG = 0;
129 *IXDP2351_CPLD_INTB_SIM_REG = 0;
130
131 ixp23xx_init_irq();
132
133 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
134 irq <
135 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
136 irq++) {
137 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
138 set_irq_flags(irq, IRQF_VALID);
139 irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
140 handle_level_irq);
141 }
142 }
143
144 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
145 irq <
146 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
147 irq++) {
148 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
149 set_irq_flags(irq, IRQF_VALID);
150 irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
151 handle_level_irq);
152 }
153 }
154
155 irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
156 irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
157}
158
159/*
160 * IXDP2351 PCI
161 */
162
163/*
164 * This board does not do normal PCI IRQ routing, or any
165 * sort of swizzling, so we just need to check where on the
166 * bus the device is and figure out what CPLD pin it is
167 * being routed to.
168 */
169#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
170
171static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
172{
173 u8 bus = dev->bus->number;
174 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
175 struct pci_bus *tmp_bus = dev->bus;
176
177 /* Primary bus, no interrupts here */
178 if (!bus)
179 return -1;
180
181 /* Lookup first leaf in bus tree */
182 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
183 tmp_bus = tmp_bus->parent;
184
185 /* Select between known bridges */
186 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
187 /* Device is located after first bridge */
188 case 0x0008:
189 if (tmp_bus == dev->bus) {
190 /* Device is located directy after first bridge */
191 switch (devpin) {
192 /* Onboard 82546 */
193 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
194 return IRQ_IXDP2351_INTA_82546;
195 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
196 return IRQ_IXDP2351_INTB_82546;
197 /* PMC SLOT */
198 case DEVPIN(0, 1): /* PMCP INTA# */
199 case DEVPIN(2, 4): /* PMCS INTD# */
200 return IRQ_IXDP2351_SPCI_PMC_INTA;
201 case DEVPIN(0, 2): /* PMCP INTB# */
202 case DEVPIN(2, 1): /* PMCS INTA# */
203 return IRQ_IXDP2351_SPCI_PMC_INTB;
204 case DEVPIN(0, 3): /* PMCP INTC# */
205 case DEVPIN(2, 2): /* PMCS INTB# */
206 return IRQ_IXDP2351_SPCI_PMC_INTC;
207 case DEVPIN(0, 4): /* PMCP INTD# */
208 case DEVPIN(2, 3): /* PMCS INTC# */
209 return IRQ_IXDP2351_SPCI_PMC_INTD;
210 }
211 } else {
212 /* Device is located indirectly after first bridge */
213 /* Not supported now */
214 return -1;
215 }
216 break;
217 case 0x0010:
218 if (tmp_bus == dev->bus) {
219 /* Device is located directy after second bridge */
220 /* Secondary bus of second bridge */
221 switch (devpin) {
222 case DEVPIN(0, 1): /* DB#0 */
223 case DEVPIN(0, 2):
224 case DEVPIN(0, 3):
225 case DEVPIN(0, 4):
226 return IRQ_IXDP2351_SPCI_DB_0;
227 case DEVPIN(1, 1): /* DB#1 */
228 case DEVPIN(1, 2):
229 case DEVPIN(1, 3):
230 case DEVPIN(1, 4):
231 return IRQ_IXDP2351_SPCI_DB_1;
232 case DEVPIN(2, 1): /* FIC1 */
233 case DEVPIN(2, 2):
234 case DEVPIN(2, 3):
235 case DEVPIN(2, 4):
236 case DEVPIN(3, 1): /* FIC2 */
237 case DEVPIN(3, 2):
238 case DEVPIN(3, 3):
239 case DEVPIN(3, 4):
240 return IRQ_IXDP2351_SPCI_FIC;
241 }
242 } else {
243 /* Device is located indirectly after second bridge */
244 /* Not supported now */
245 return -1;
246 }
247 break;
248 }
249
250 return -1;
251}
252
253struct hw_pci ixdp2351_pci __initdata = {
254 .nr_controllers = 1,
255 .preinit = ixp23xx_pci_preinit,
256 .setup = ixp23xx_pci_setup,
257 .scan = ixp23xx_pci_scan_bus,
258 .map_irq = ixdp2351_map_irq,
259};
260
261int __init ixdp2351_pci_init(void)
262{
263 if (machine_is_ixdp2351())
264 pci_common_init(&ixdp2351_pci);
265
266 return 0;
267}
268
269subsys_initcall(ixdp2351_pci_init);
270
271/*
272 * IXDP2351 Static Mapped I/O
273 */
274static struct map_desc ixdp2351_io_desc[] __initdata = {
275 {
276 .virtual = IXDP2351_NP_VIRT_BASE,
277 .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
278 .length = IXDP2351_NP_PHYS_SIZE,
279 .type = MT_DEVICE
280 }, {
281 .virtual = IXDP2351_BB_BASE_VIRT,
282 .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
283 .length = IXDP2351_BB_SIZE,
284 .type = MT_DEVICE
285 }
286};
287
288static void __init ixdp2351_map_io(void)
289{
290 ixp23xx_map_io();
291 iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
292}
293
294static struct physmap_flash_data ixdp2351_flash_data = {
295 .width = 1,
296};
297
298static struct resource ixdp2351_flash_resource = {
299 .start = 0x90000000,
300 .end = 0x93ffffff,
301 .flags = IORESOURCE_MEM,
302};
303
304static struct platform_device ixdp2351_flash = {
305 .name = "physmap-flash",
306 .id = 0,
307 .dev = {
308 .platform_data = &ixdp2351_flash_data,
309 },
310 .num_resources = 1,
311 .resource = &ixdp2351_flash_resource,
312};
313
314static void __init ixdp2351_init(void)
315{
316 platform_device_register(&ixdp2351_flash);
317
318 /*
319 * Mark flash as writeable
320 */
321 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
322 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
323 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
324 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
325
326 ixp23xx_sys_init();
327}
328
329MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
330 /* Maintainer: MontaVista Software, Inc. */
331 .map_io = ixdp2351_map_io,
332 .init_irq = ixdp2351_init_irq,
333 .timer = &ixp23xx_timer,
334 .boot_params = 0x00000100,
335 .init_machine = ixdp2351_init,
336MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
new file mode 100644
index 00000000000..e6be5711c70
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -0,0 +1,293 @@
1/*
2 * arch/arm/mach-ixp23xx/pci.c
3 *
4 * PCI routines for IXP23XX based systems
5 *
6 * Copyright (c) 2005 MontaVista Software, Inc.
7 *
8 * based on original code:
9 *
10 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
11 * Copyright 2002-2005 Intel Corp.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/interrupt.h>
23#include <linux/mm.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/sizes.h>
31#include <asm/system.h>
32#include <asm/mach/pci.h>
33#include <mach/hardware.h>
34
35extern int (*external_fault) (unsigned long, struct pt_regs *);
36
37static volatile int pci_master_aborts = 0;
38
39#ifdef DEBUG
40#define DBG(x...) printk(x)
41#else
42#define DBG(x...)
43#endif
44
45int clear_master_aborts(void);
46
47static u32
48*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
49{
50 u32 *paddress;
51
52 /*
53 * Must be dword aligned
54 */
55 where &= ~3;
56
57 /*
58 * For top bus, generate type 0, else type 1
59 */
60 if (!bus_nr) {
61 if (PCI_SLOT(devfn) >= 8)
62 return 0;
63
64 paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
65 | (1 << (PCI_SLOT(devfn) + 16))
66 | (PCI_FUNC(devfn) << 8) | where);
67 } else {
68 paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
69 | (bus_nr << 16)
70 | (PCI_SLOT(devfn) << 11)
71 | (PCI_FUNC(devfn) << 8) | where);
72 }
73
74 return paddress;
75}
76
77/*
78 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
79 * 0 and 3 are not valid indexes...
80 */
81static u32 bytemask[] = {
82 /*0*/ 0,
83 /*1*/ 0xff,
84 /*2*/ 0xffff,
85 /*3*/ 0,
86 /*4*/ 0xffffffff,
87};
88
89static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 *value)
91{
92 u32 n;
93 u32 *addr;
94
95 n = where % 4;
96
97 DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
98 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
99
100 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
101 if (!addr)
102 return PCIBIOS_DEVICE_NOT_FOUND;
103
104 pci_master_aborts = 0;
105 *value = (*addr >> (8*n)) & bytemask[size];
106 if (pci_master_aborts) {
107 pci_master_aborts = 0;
108 *value = 0xffffffff;
109 return PCIBIOS_DEVICE_NOT_FOUND;
110 }
111
112 return PCIBIOS_SUCCESSFUL;
113}
114
115/*
116 * We don't do error checking on the address for writes.
117 * It's assumed that the user checked for the device existing first
118 * by doing a read first.
119 */
120static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 value)
122{
123 u32 mask;
124 u32 *addr;
125 u32 temp;
126
127 mask = ~(bytemask[size] << ((where % 0x4) * 8));
128 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
129 if (!addr)
130 return PCIBIOS_DEVICE_NOT_FOUND;
131 temp = (u32) (value) << ((where % 0x4) * 8);
132 *addr = (*addr & mask) | temp;
133
134 clear_master_aborts();
135
136 return PCIBIOS_SUCCESSFUL;
137}
138
139struct pci_ops ixp23xx_pci_ops = {
140 .read = ixp23xx_pci_read_config,
141 .write = ixp23xx_pci_write_config,
142};
143
144struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
145{
146 return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
147}
148
149int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
150{
151 volatile unsigned long temp;
152 unsigned long flags;
153
154 pci_master_aborts = 1;
155
156 local_irq_save(flags);
157 temp = *IXP23XX_PCI_CONTROL;
158
159 /*
160 * master abort and cmd tgt err
161 */
162 if (temp & ((1 << 8) | (1 << 5)))
163 *IXP23XX_PCI_CONTROL = temp;
164
165 temp = *IXP23XX_PCI_CMDSTAT;
166
167 if (temp & (1 << 29))
168 *IXP23XX_PCI_CMDSTAT = temp;
169 local_irq_restore(flags);
170
171 /*
172 * If it was an imprecise abort, then we need to correct the
173 * return address to be _after_ the instruction.
174 */
175 if (fsr & (1 << 10))
176 regs->ARM_pc += 4;
177
178 return 0;
179}
180
181int clear_master_aborts(void)
182{
183 volatile u32 temp;
184
185 temp = *IXP23XX_PCI_CONTROL;
186
187 /*
188 * master abort and cmd tgt err
189 */
190 if (temp & ((1 << 8) | (1 << 5)))
191 *IXP23XX_PCI_CONTROL = temp;
192
193 temp = *IXP23XX_PCI_CMDSTAT;
194
195 if (temp & (1 << 29))
196 *IXP23XX_PCI_CMDSTAT = temp;
197
198 return 0;
199}
200
201static void __init ixp23xx_pci_common_init(void)
202{
203#ifdef __ARMEB__
204 *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
205#endif
206 /*
207 * ADDR_31 needs to be clear for PCI memory access to CPP memory
208 */
209 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
210 *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
211
212 /*
213 * Select correct memory for PCI inbound transactions
214 */
215 if (ixp23xx_cpp_boot()) {
216 *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
217 } else {
218 *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
219
220 /*
221 * Enable coherency on A2 silicon.
222 */
223 if (arch_is_coherent())
224 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
225 }
226}
227
228void __init ixp23xx_pci_preinit(void)
229{
230 pcibios_min_io = 0;
231 pcibios_min_mem = 0xe0000000;
232
233 pci_set_flags(0);
234
235 ixp23xx_pci_common_init();
236
237 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
238 "PCI config cycle to non-existent device");
239
240 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
241}
242
243/*
244 * Prevent PCI layer from seeing the inbound host-bridge resources
245 */
246static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
247{
248 int i;
249
250 dev->class &= 0xff;
251 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
252 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
253 dev->resource[i].start = 0;
254 dev->resource[i].end = 0;
255 dev->resource[i].flags = 0;
256 }
257}
258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
259
260/*
261 * IXP2300 systems often have large resource requirements, so we just
262 * use our own resource space.
263 */
264static struct resource ixp23xx_pci_mem_space = {
265 .start = IXP23XX_PCI_MEM_START,
266 .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
267 .flags = IORESOURCE_MEM,
268 .name = "PCI Mem Space"
269};
270
271static struct resource ixp23xx_pci_io_space = {
272 .start = 0x00000100,
273 .end = 0x01ffffff,
274 .flags = IORESOURCE_IO,
275 .name = "PCI I/O Space"
276};
277
278int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
279{
280 if (nr >= 1)
281 return 0;
282
283 sys->resource[0] = &ixp23xx_pci_io_space;
284 sys->resource[1] = &ixp23xx_pci_mem_space;
285 sys->resource[2] = NULL;
286
287 return 1;
288}
289
290void __init ixp23xx_pci_slave_init(void)
291{
292 ixp23xx_pci_common_init();
293}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
new file mode 100644
index 00000000000..844551d2368
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-ixp23xx/roadrunner.c
3 *
4 * RoadRunner board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/ioport.h>
26#include <linux/serial_8250.h>
27#include <linux/serial_core.h>
28#include <linux/device.h>
29#include <linux/mm.h>
30#include <linux/pci.h>
31#include <linux/mtd/physmap.h>
32
33#include <asm/types.h>
34#include <asm/setup.h>
35#include <asm/memory.h>
36#include <mach/hardware.h>
37#include <asm/mach-types.h>
38#include <asm/irq.h>
39#include <asm/system.h>
40#include <asm/tlbflush.h>
41#include <asm/pgtable.h>
42
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/pci.h>
47
48/*
49 * Interrupt mapping
50 */
51#define INTA IRQ_ROADRUNNER_PCI_INTA
52#define INTB IRQ_ROADRUNNER_PCI_INTB
53#define INTC IRQ_ROADRUNNER_PCI_INTC
54#define INTD IRQ_ROADRUNNER_PCI_INTD
55
56#define INTC_PIN IXP23XX_GPIO_PIN_11
57#define INTD_PIN IXP23XX_GPIO_PIN_12
58
59static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel,
60 u8 pin)
61{
62 static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
63 static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
64 static int usb_irq[] = {INTB, INTC, INTD, -1};
65 static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
66 static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
67
68 switch(dev->bus->number) {
69 case 0:
70 switch(dev->devfn) {
71 case 0x0: // PCI-PCI bridge
72 break;
73 case 0x8: // PCI Card Slot
74 return pci_card_slot_irq[pin - 1];
75 case 0x10: // PMC Slot
76 return pmc_card_slot_irq[pin - 1];
77 case 0x18: // PMC Slot Secondary Agent
78 break;
79 case 0x20: // IXP Processor
80 break;
81 default:
82 return NO_IRQ;
83 }
84 break;
85
86 case 1:
87 switch(dev->devfn) {
88 case 0x0: // IDE Controller
89 return (pin == 1) ? INTC : -1;
90 case 0x8: // USB fun 0
91 case 0x9: // USB fun 1
92 case 0xa: // USB fun 2
93 return usb_irq[pin - 1];
94 case 0x10: // Mini PCI 1
95 return mini_pci_1_irq[pin-1];
96 case 0x18: // Mini PCI 2
97 return mini_pci_2_irq[pin-1];
98 case 0x20: // MEM slot
99 return (pin == 1) ? INTA : -1;
100 default:
101 return NO_IRQ;
102 }
103 break;
104
105 default:
106 return NO_IRQ;
107 }
108
109 return NO_IRQ;
110}
111
112static void __init roadrunner_pci_preinit(void)
113{
114 irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
115 irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
116
117 ixp23xx_pci_preinit();
118}
119
120static struct hw_pci roadrunner_pci __initdata = {
121 .nr_controllers = 1,
122 .preinit = roadrunner_pci_preinit,
123 .setup = ixp23xx_pci_setup,
124 .scan = ixp23xx_pci_scan_bus,
125 .map_irq = roadrunner_map_irq,
126};
127
128static int __init roadrunner_pci_init(void)
129{
130 if (machine_is_roadrunner())
131 pci_common_init(&roadrunner_pci);
132
133 return 0;
134};
135
136subsys_initcall(roadrunner_pci_init);
137
138static struct physmap_flash_data roadrunner_flash_data = {
139 .width = 2,
140};
141
142static struct resource roadrunner_flash_resource = {
143 .start = 0x90000000,
144 .end = 0x93ffffff,
145 .flags = IORESOURCE_MEM,
146};
147
148static struct platform_device roadrunner_flash = {
149 .name = "physmap-flash",
150 .id = 0,
151 .dev = {
152 .platform_data = &roadrunner_flash_data,
153 },
154 .num_resources = 1,
155 .resource = &roadrunner_flash_resource,
156};
157
158static void __init roadrunner_init(void)
159{
160 platform_device_register(&roadrunner_flash);
161
162 /*
163 * Mark flash as writeable
164 */
165 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
166 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
167 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
168 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
169
170 ixp23xx_sys_init();
171}
172
173MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
174 /* Maintainer: Deepak Saxena */
175 .map_io = ixp23xx_map_io,
176 .init_irq = ixp23xx_init_irq,
177 .timer = &ixp23xx_timer,
178 .boot_params = 0x00000100,
179 .init_machine = roadrunner_init,
180MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 23:35:32 -0400