Added missing tegra files.HEADmaster

13 files changed, 5623 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
new file mode 100644
index 00000000000..69d1322add3
--- /dev/null
+++ b/arch/arm/mach-imx/cache-l2x0.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ * Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/hardware.h>
+
+static int mxc_init_l2x0(void)
+{
+        void __iomem *l2x0_base;
+        void __iomem *clkctl_base;
+
+        if (!cpu_is_mx31() && !cpu_is_mx35())
+                return 0;
+
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value.
+ */
+#define L2_MEM_VAL 0x10
+
+        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+        if (clkctl_base != NULL) {
+                writel(0x00000515, clkctl_base + L2_MEM_VAL);
+                iounmap(clkctl_base);
+        } else {
+                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+        }
+
+        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
+        if (IS_ERR(l2x0_base)) {
+                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+                                PTR_ERR(l2x0_base));
+                return 0;
+        }
+
+        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+
+        return 0;
+}
+arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
new file mode 100644
index 00000000000..4aabeb24156
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -0,0 +1,636 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/math64.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+/* CCM register addresses */
+#define CCM_CSCR        IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
+#define CCM_PCDR        IO_ADDR_CCM(0x20)
+
+#define CCM_CSCR_CLKO_OFFSET    29
+#define CCM_CSCR_CLKO_MASK      (0x7 << 29)
+#define CCM_CSCR_USB_OFFSET     26
+#define CCM_CSCR_USB_MASK       (0x7 << 26)
+#define CCM_CSCR_OSC_EN_SHIFT   17
+#define CCM_CSCR_SYSTEM_SEL     (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET    10
+#define CCM_CSCR_BCLK_MASK      (0xf << 10)
+#define CCM_CSCR_PRESC          (1 << 15)
+
+#define CCM_PCDR_PCLK3_OFFSET   16
+#define CCM_PCDR_PCLK3_MASK     (0x7f << 16)
+#define CCM_PCDR_PCLK2_OFFSET   4
+#define CCM_PCDR_PCLK2_MASK     (0xf << 4)
+#define CCM_PCDR_PCLK1_OFFSET   0
+#define CCM_PCDR_PCLK1_MASK     0xf
+
+#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+/* SCM register addresses */
+#define SCM_GCCR        IO_ADDR_SCM(0xc)
+
+#define SCM_GCCR_DMA_CLK_EN_OFFSET      3
+#define SCM_GCCR_CSI_CLK_EN_OFFSET      2
+#define SCM_GCCR_MMA_CLK_EN_OFFSET      1
+#define SCM_GCCR_USBD_CLK_EN_OFFSET     0
+
+static int _clk_enable(struct clk *clk)
+{
+        unsigned int reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        unsigned int reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
+                               struct clk *parent)
+{
+        int i;
+
+        for (i = 0; i < size; i++)
+                if (parent == clk_arr[i])
+                        return i;
+
+        return -EINVAL;
+}
+
+static unsigned long
+_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
+{
+        int div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > limit)
+                div = limit;
+
+        return parent_rate / div;
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+static unsigned long clk16m_get_rate(struct clk *clk)
+{
+        return 16000000;
+}
+
+static struct clk clk16m = {
+        .get_rate = clk16m_get_rate,
+        .enable = _clk_enable,
+        .enable_reg = CCM_CSCR,
+        .enable_shift = CCM_CSCR_OSC_EN_SHIFT,
+        .disable = _clk_disable,
+};
+
+/* in Hz */
+static unsigned long clk32_rate;
+
+static unsigned long clk32_get_rate(struct clk *clk)
+{
+        return clk32_rate;
+}
+
+static struct clk clk32 = {
+        .get_rate = clk32_get_rate,
+};
+
+static unsigned long clk32_premult_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) * 512;
+}
+
+static struct clk clk32_premult = {
+        .parent = &clk32,
+        .get_rate = clk32_premult_get_rate,
+};
+
+static const struct clk *prem_clk_clocks[] = {
+        &clk32_premult,
+        &clk16m,
+};
+
+static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int i;
+        unsigned int reg = __raw_readl(CCM_CSCR);
+
+        i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
+                                parent);
+
+        switch (i) {
+        case 0:
+                reg &= ~CCM_CSCR_SYSTEM_SEL;
+                break;
+        case 1:
+                reg |= CCM_CSCR_SYSTEM_SEL;
+                break;
+        default:
+                return i;
+        }
+
+        __raw_writel(reg, CCM_CSCR);
+
+        return 0;
+}
+
+static struct clk prem_clk = {
+        .set_parent = prem_clk_set_parent,
+};
+
+static unsigned long system_clk_get_rate(struct clk *clk)
+{
+        return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
+                              clk_get_rate(clk->parent));
+}
+
+static struct clk system_clk = {
+        .parent = &prem_clk,
+        .get_rate = system_clk_get_rate,
+};
+
+static unsigned long mcu_clk_get_rate(struct clk *clk)
+{
+        return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
+                              clk_get_rate(clk->parent));
+}
+
+static struct clk mcu_clk = {
+        .parent = &clk32_premult,
+        .get_rate = mcu_clk_get_rate,
+};
+
+static unsigned long fclk_get_rate(struct clk *clk)
+{
+        unsigned long fclk = clk_get_rate(clk->parent);
+
+        if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
+                fclk /= 2;
+
+        return fclk;
+}
+
+static struct clk fclk = {
+        .parent = &mcu_clk,
+        .get_rate = fclk_get_rate,
+};
+
+/*
+ *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
+ */
+static unsigned long hclk_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
+                        CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
+}
+
+static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        return _clk_simple_round_rate(clk, rate, 16);
+}
+
+static int hclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        unsigned int reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 16 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_BCLK_MASK;
+        reg |= div << CCM_CSCR_BCLK_OFFSET;
+        __raw_writel(reg, CCM_CSCR);
+
+        return 0;
+}
+
+static struct clk hclk = {
+        .parent = &system_clk,
+        .get_rate = hclk_get_rate,
+        .round_rate = hclk_round_rate,
+        .set_rate = hclk_set_rate,
+};
+
+static unsigned long clk48m_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
+                        CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
+}
+
+static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
+{
+        return _clk_simple_round_rate(clk, rate, 8);
+}
+
+static int clk48m_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        unsigned int reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_USB_MASK;
+        reg |= div << CCM_CSCR_USB_OFFSET;
+        __raw_writel(reg, CCM_CSCR);
+
+        return 0;
+}
+
+static struct clk clk48m = {
+        .parent = &system_clk,
+        .get_rate = clk48m_get_rate,
+        .round_rate = clk48m_round_rate,
+        .set_rate = clk48m_set_rate,
+};
+
+/*
+ *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
+ */
+static unsigned long perclk1_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
+                        CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
+}
+
+static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
+{
+        return _clk_simple_round_rate(clk, rate, 16);
+}
+
+static int perclk1_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        unsigned int reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 16 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_PCDR);
+        reg &= ~CCM_PCDR_PCLK1_MASK;
+        reg |= div << CCM_PCDR_PCLK1_OFFSET;
+        __raw_writel(reg, CCM_PCDR);
+
+        return 0;
+}
+
+/*
+ *  get peripheral clock 2 ( LCD, SD, SPI[12] )
+ */
+static unsigned long perclk2_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
+                        CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
+}
+
+static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
+{
+        return _clk_simple_round_rate(clk, rate, 16);
+}
+
+static int perclk2_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        unsigned int reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 16 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_PCDR);
+        reg &= ~CCM_PCDR_PCLK2_MASK;
+        reg |= div << CCM_PCDR_PCLK2_OFFSET;
+        __raw_writel(reg, CCM_PCDR);
+
+        return 0;
+}
+
+/*
+ *  get peripheral clock 3 ( SSI )
+ */
+static unsigned long perclk3_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
+                        CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
+}
+
+static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
+{
+        return _clk_simple_round_rate(clk, rate, 128);
+}
+
+static int perclk3_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        unsigned int reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 128 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_PCDR);
+        reg &= ~CCM_PCDR_PCLK3_MASK;
+        reg |= div << CCM_PCDR_PCLK3_OFFSET;
+        __raw_writel(reg, CCM_PCDR);
+
+        return 0;
+}
+
+static struct clk perclk[] = {
+        {
+                .id = 0,
+                .parent = &system_clk,
+                .get_rate = perclk1_get_rate,
+                .round_rate = perclk1_round_rate,
+                .set_rate = perclk1_set_rate,
+        }, {
+                .id = 1,
+                .parent = &system_clk,
+                .get_rate = perclk2_get_rate,
+                .round_rate = perclk2_round_rate,
+                .set_rate = perclk2_set_rate,
+        }, {
+                .id = 2,
+                .parent = &system_clk,
+                .get_rate = perclk3_get_rate,
+                .round_rate = perclk3_round_rate,
+                .set_rate = perclk3_set_rate,
+        }
+};
+
+static const struct clk *clko_clocks[] = {
+        &perclk[0],
+        &hclk,
+        &clk48m,
+        &clk16m,
+        &prem_clk,
+        &fclk,
+};
+
+static int clko_set_parent(struct clk *clk, struct clk *parent)
+{
+        int i;
+        unsigned int reg;
+
+        i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
+        if (i < 0)
+                return i;
+
+        reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
+        reg |= i << CCM_CSCR_CLKO_OFFSET;
+        __raw_writel(reg, CCM_CSCR);
+
+        if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
+                clk->set_rate = _clk_parent_set_rate;
+                clk->round_rate = _clk_parent_round_rate;
+        } else {
+                clk->set_rate = NULL;
+                clk->round_rate = NULL;
+        }
+
+        return 0;
+}
+
+static struct clk clko_clk = {
+        .set_parent = clko_set_parent,
+};
+
+static struct clk dma_clk = {
+        .parent = &hclk,
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+        .enable = _clk_enable,
+        .enable_reg = SCM_GCCR,
+        .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk csi_clk = {
+        .parent = &hclk,
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+        .enable = _clk_enable,
+        .enable_reg = SCM_GCCR,
+        .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mma_clk = {
+        .parent = &hclk,
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+        .enable = _clk_enable,
+        .enable_reg = SCM_GCCR,
+        .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk usbd_clk = {
+        .parent = &clk48m,
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+        .enable = _clk_enable,
+        .enable_reg = SCM_GCCR,
+        .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk gpt_clk = {
+        .parent = &perclk[0],
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk uart_clk = {
+        .parent = &perclk[0],
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk i2c_clk = {
+        .parent = &hclk,
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk spi_clk = {
+        .parent = &perclk[1],
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk sdhc_clk = {
+        .parent = &perclk[1],
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk lcdc_clk = {
+        .parent = &perclk[1],
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk mshc_clk = {
+        .parent = &hclk,
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk ssi_clk = {
+        .parent = &perclk[2],
+        .round_rate = _clk_parent_round_rate,
+        .set_rate = _clk_parent_set_rate,
+};
+
+static struct clk rtc_clk = {
+        .parent = &clk32,
+};
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] __initdata = {
+        _REGISTER_CLOCK(NULL, "dma", dma_clk)
+        _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK(NULL, "mma", mma_clk)
+        _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+        _REGISTER_CLOCK("imx1-uart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("imx1-uart.1", NULL, uart_clk)
+        _REGISTER_CLOCK("imx1-uart.2", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
+        _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
+        _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
+};
+
+int __init mx1_clocks_init(unsigned long fref)
+{
+        unsigned int reg;
+
+        /* disable clocks we are able to */
+        __raw_writel(0, SCM_GCCR);
+
+        clk32_rate = fref;
+        reg = __raw_readl(CCM_CSCR);
+
+        /* detect clock reference for system PLL */
+        if (reg & CCM_CSCR_SYSTEM_SEL) {
+                prem_clk.parent = &clk16m;
+        } else {
+                /* ensure that oscillator is disabled */
+                reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
+                __raw_writel(reg, CCM_CSCR);
+                prem_clk.parent = &clk32_premult;
+        }
+
+        /* detect reference for CLKO */
+        reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
+        clko_clk.parent = (struct clk *)clko_clocks[reg];
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        clk_enable(&hclk);
+        clk_enable(&fclk);
+
+        mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+                        MX1_TIM1_INT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
new file mode 100644
index 00000000000..ee15d8c9db0
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -0,0 +1,1239 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/div64.h>
+
+#define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR                IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
+#define CCM_PCDR0               IO_ADDR_CCM(0x18)
+#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0               IO_ADDR_CCM(0x20)
+#define CCM_PCCR1               IO_ADDR_CCM(0x24)
+#define CCM_CCSR                IO_ADDR_CCM(0x28)
+#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_PRESC_OFFSET   29
+#define CCM_CSCR_PRESC_MASK     (0x7 << CCM_CSCR_PRESC_OFFSET)
+
+#define CCM_CSCR_USB_OFFSET     26
+#define CCM_CSCR_USB_MASK       (0x7 << CCM_CSCR_USB_OFFSET)
+#define CCM_CSCR_SD_OFFSET      24
+#define CCM_CSCR_SD_MASK        (0x3 << CCM_CSCR_SD_OFFSET)
+#define CCM_CSCR_SPLLRES        (1 << 22)
+#define CCM_CSCR_MPLLRES        (1 << 21)
+#define CCM_CSCR_SSI2_OFFSET    20
+#define CCM_CSCR_SSI2           (1 << CCM_CSCR_SSI2_OFFSET)
+#define CCM_CSCR_SSI1_OFFSET    19
+#define CCM_CSCR_SSI1           (1 << CCM_CSCR_SSI1_OFFSET)
+#define CCM_CSCR_FIR_OFFSET     18
+#define CCM_CSCR_FIR            (1 << CCM_CSCR_FIR_OFFSET)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET    10
+#define CCM_CSCR_BCLK_MASK      (0xf << CCM_CSCR_BCLK_OFFSET)
+#define CCM_CSCR_IPDIV_OFFSET   9
+#define CCM_CSCR_IPDIV          (1 << CCM_CSCR_IPDIV_OFFSET)
+
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           1
+
+#define CCM_MPCTL0_CPLM         (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET    26
+#define CCM_MPCTL0_PD_MASK      (0xf << 26)
+#define CCM_MPCTL0_MFD_OFFSET   16
+#define CCM_MPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_MPCTL0_MFI_OFFSET   10
+#define CCM_MPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_MPCTL0_MFN_OFFSET   0
+#define CCM_MPCTL0_MFN_MASK     0x3ff
+
+#define CCM_MPCTL1_LF           (1 << 15)
+#define CCM_MPCTL1_BRMO         (1 << 6)
+
+#define CCM_SPCTL0_CPLM         (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET    26
+#define CCM_SPCTL0_PD_MASK      (0xf << 26)
+#define CCM_SPCTL0_MFD_OFFSET   16
+#define CCM_SPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_SPCTL0_MFI_OFFSET   10
+#define CCM_SPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_SPCTL0_MFN_OFFSET   0
+#define CCM_SPCTL0_MFN_MASK     0x3ff
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET       16
+#define CCM_OSC26MCTL_PEAK_MASK         (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET        8
+#define CCM_OSC26MCTL_AGC_MASK          (0x3f << 8)
+#define CCM_OSC26MCTL_ANATEST_OFFSET    0
+#define CCM_OSC26MCTL_ANATEST_MASK      0x3f
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET    26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK      (0x3f << 26)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET    16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK      (0x3f << 16)
+#define CCM_PCDR0_NFCDIV_OFFSET         12
+#define CCM_PCDR0_NFCDIV_MASK           (0xf << 12)
+#define CCM_PCDR0_48MDIV_OFFSET         5
+#define CCM_PCDR0_48MDIV_MASK           (0x7 << CCM_PCDR0_48MDIV_OFFSET)
+#define CCM_PCDR0_FIRIDIV_OFFSET        0
+#define CCM_PCDR0_FIRIDIV_MASK          0x1f
+#define CCM_PCDR1_PERDIV4_OFFSET        24
+#define CCM_PCDR1_PERDIV4_MASK          (0x3f << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET        16
+#define CCM_PCDR1_PERDIV3_MASK          (0x3f << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET        8
+#define CCM_PCDR1_PERDIV2_MASK          (0x3f << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET        0
+#define CCM_PCDR1_PERDIV1_MASK          0x3f
+
+#define CCM_PCCR_HCLK_CSI_OFFSET        31
+#define CCM_PCCR_HCLK_CSI_REG           CCM_PCCR0
+#define CCM_PCCR_HCLK_DMA_OFFSET        30
+#define CCM_PCCR_HCLK_DMA_REG           CCM_PCCR0
+#define CCM_PCCR_HCLK_BROM_OFFSET       28
+#define CCM_PCCR_HCLK_BROM_REG          CCM_PCCR0
+#define CCM_PCCR_HCLK_EMMA_OFFSET       27
+#define CCM_PCCR_HCLK_EMMA_REG          CCM_PCCR0
+#define CCM_PCCR_HCLK_LCDC_OFFSET       26
+#define CCM_PCCR_HCLK_LCDC_REG          CCM_PCCR0
+#define CCM_PCCR_HCLK_SLCDC_OFFSET      25
+#define CCM_PCCR_HCLK_SLCDC_REG         CCM_PCCR0
+#define CCM_PCCR_HCLK_USBOTG_OFFSET     24
+#define CCM_PCCR_HCLK_USBOTG_REG        CCM_PCCR0
+#define CCM_PCCR_HCLK_BMI_OFFSET        23
+#define CCM_PCCR_BMI_MASK               (1 << CCM_PCCR_BMI_MASK)
+#define CCM_PCCR_HCLK_BMI_REG           CCM_PCCR0
+#define CCM_PCCR_PERCLK4_OFFSET         22
+#define CCM_PCCR_PERCLK4_REG            CCM_PCCR0
+#define CCM_PCCR_SLCDC_OFFSET           21
+#define CCM_PCCR_SLCDC_REG              CCM_PCCR0
+#define CCM_PCCR_FIRI_BAUD_OFFSET       20
+#define CCM_PCCR_FIRI_BAUD_MASK         (1 << CCM_PCCR_FIRI_BAUD_MASK)
+#define CCM_PCCR_FIRI_BAUD_REG          CCM_PCCR0
+#define CCM_PCCR_NFC_OFFSET             19
+#define CCM_PCCR_NFC_REG                CCM_PCCR0
+#define CCM_PCCR_LCDC_OFFSET            18
+#define CCM_PCCR_LCDC_REG               CCM_PCCR0
+#define CCM_PCCR_SSI1_BAUD_OFFSET       17
+#define CCM_PCCR_SSI1_BAUD_REG          CCM_PCCR0
+#define CCM_PCCR_SSI2_BAUD_OFFSET       16
+#define CCM_PCCR_SSI2_BAUD_REG          CCM_PCCR0
+#define CCM_PCCR_EMMA_OFFSET            15
+#define CCM_PCCR_EMMA_REG               CCM_PCCR0
+#define CCM_PCCR_USBOTG_OFFSET          14
+#define CCM_PCCR_USBOTG_REG             CCM_PCCR0
+#define CCM_PCCR_DMA_OFFSET             13
+#define CCM_PCCR_DMA_REG                CCM_PCCR0
+#define CCM_PCCR_I2C1_OFFSET            12
+#define CCM_PCCR_I2C1_REG               CCM_PCCR0
+#define CCM_PCCR_GPIO_OFFSET            11
+#define CCM_PCCR_GPIO_REG               CCM_PCCR0
+#define CCM_PCCR_SDHC2_OFFSET           10
+#define CCM_PCCR_SDHC2_REG              CCM_PCCR0
+#define CCM_PCCR_SDHC1_OFFSET           9
+#define CCM_PCCR_SDHC1_REG              CCM_PCCR0
+#define CCM_PCCR_FIRI_OFFSET            8
+#define CCM_PCCR_FIRI_MASK              (1 << CCM_PCCR_BAUD_MASK)
+#define CCM_PCCR_FIRI_REG               CCM_PCCR0
+#define CCM_PCCR_SSI2_IPG_OFFSET        7
+#define CCM_PCCR_SSI2_REG               CCM_PCCR0
+#define CCM_PCCR_SSI1_IPG_OFFSET        6
+#define CCM_PCCR_SSI1_REG               CCM_PCCR0
+#define CCM_PCCR_CSPI2_OFFSET           5
+#define CCM_PCCR_CSPI2_REG              CCM_PCCR0
+#define CCM_PCCR_CSPI1_OFFSET           4
+#define CCM_PCCR_CSPI1_REG              CCM_PCCR0
+#define CCM_PCCR_UART4_OFFSET           3
+#define CCM_PCCR_UART4_REG              CCM_PCCR0
+#define CCM_PCCR_UART3_OFFSET           2
+#define CCM_PCCR_UART3_REG              CCM_PCCR0
+#define CCM_PCCR_UART2_OFFSET           1
+#define CCM_PCCR_UART2_REG              CCM_PCCR0
+#define CCM_PCCR_UART1_OFFSET           0
+#define CCM_PCCR_UART1_REG              CCM_PCCR0
+
+#define CCM_PCCR_OWIRE_OFFSET           31
+#define CCM_PCCR_OWIRE_REG              CCM_PCCR1
+#define CCM_PCCR_KPP_OFFSET             30
+#define CCM_PCCR_KPP_REG                CCM_PCCR1
+#define CCM_PCCR_RTC_OFFSET             29
+#define CCM_PCCR_RTC_REG                CCM_PCCR1
+#define CCM_PCCR_PWM_OFFSET             28
+#define CCM_PCCR_PWM_REG                CCM_PCCR1
+#define CCM_PCCR_GPT3_OFFSET            27
+#define CCM_PCCR_GPT3_REG               CCM_PCCR1
+#define CCM_PCCR_GPT2_OFFSET            26
+#define CCM_PCCR_GPT2_REG               CCM_PCCR1
+#define CCM_PCCR_GPT1_OFFSET            25
+#define CCM_PCCR_GPT1_REG               CCM_PCCR1
+#define CCM_PCCR_WDT_OFFSET             24
+#define CCM_PCCR_WDT_REG                CCM_PCCR1
+#define CCM_PCCR_CSPI3_OFFSET           23
+#define CCM_PCCR_CSPI3_REG              CCM_PCCR1
+
+#define CCM_PCCR_CSPI1_MASK             (1 << CCM_PCCR_CSPI1_OFFSET)
+#define CCM_PCCR_CSPI2_MASK             (1 << CCM_PCCR_CSPI2_OFFSET)
+#define CCM_PCCR_CSPI3_MASK             (1 << CCM_PCCR_CSPI3_OFFSET)
+#define CCM_PCCR_DMA_MASK               (1 << CCM_PCCR_DMA_OFFSET)
+#define CCM_PCCR_EMMA_MASK              (1 << CCM_PCCR_EMMA_OFFSET)
+#define CCM_PCCR_GPIO_MASK              (1 << CCM_PCCR_GPIO_OFFSET)
+#define CCM_PCCR_GPT1_MASK              (1 << CCM_PCCR_GPT1_OFFSET)
+#define CCM_PCCR_GPT2_MASK              (1 << CCM_PCCR_GPT2_OFFSET)
+#define CCM_PCCR_GPT3_MASK              (1 << CCM_PCCR_GPT3_OFFSET)
+#define CCM_PCCR_HCLK_BROM_MASK         (1 << CCM_PCCR_HCLK_BROM_OFFSET)
+#define CCM_PCCR_HCLK_CSI_MASK          (1 << CCM_PCCR_HCLK_CSI_OFFSET)
+#define CCM_PCCR_HCLK_DMA_MASK          (1 << CCM_PCCR_HCLK_DMA_OFFSET)
+#define CCM_PCCR_HCLK_EMMA_MASK         (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
+#define CCM_PCCR_HCLK_LCDC_MASK         (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
+#define CCM_PCCR_HCLK_SLCDC_MASK        (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
+#define CCM_PCCR_HCLK_USBOTG_MASK       (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
+#define CCM_PCCR_I2C1_MASK              (1 << CCM_PCCR_I2C1_OFFSET)
+#define CCM_PCCR_KPP_MASK               (1 << CCM_PCCR_KPP_OFFSET)
+#define CCM_PCCR_LCDC_MASK              (1 << CCM_PCCR_LCDC_OFFSET)
+#define CCM_PCCR_NFC_MASK               (1 << CCM_PCCR_NFC_OFFSET)
+#define CCM_PCCR_OWIRE_MASK             (1 << CCM_PCCR_OWIRE_OFFSET)
+#define CCM_PCCR_PERCLK4_MASK           (1 << CCM_PCCR_PERCLK4_OFFSET)
+#define CCM_PCCR_PWM_MASK               (1 << CCM_PCCR_PWM_OFFSET)
+#define CCM_PCCR_RTC_MASK               (1 << CCM_PCCR_RTC_OFFSET)
+#define CCM_PCCR_SDHC1_MASK             (1 << CCM_PCCR_SDHC1_OFFSET)
+#define CCM_PCCR_SDHC2_MASK             (1 << CCM_PCCR_SDHC2_OFFSET)
+#define CCM_PCCR_SLCDC_MASK             (1 << CCM_PCCR_SLCDC_OFFSET)
+#define CCM_PCCR_SSI1_BAUD_MASK         (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
+#define CCM_PCCR_SSI1_IPG_MASK          (1 << CCM_PCCR_SSI1_IPG_OFFSET)
+#define CCM_PCCR_SSI2_BAUD_MASK         (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
+#define CCM_PCCR_SSI2_IPG_MASK          (1 << CCM_PCCR_SSI2_IPG_OFFSET)
+#define CCM_PCCR_UART1_MASK             (1 << CCM_PCCR_UART1_OFFSET)
+#define CCM_PCCR_UART2_MASK             (1 << CCM_PCCR_UART2_OFFSET)
+#define CCM_PCCR_UART3_MASK             (1 << CCM_PCCR_UART3_OFFSET)
+#define CCM_PCCR_UART4_MASK             (1 << CCM_PCCR_UART4_OFFSET)
+#define CCM_PCCR_USBOTG_MASK            (1 << CCM_PCCR_USBOTG_OFFSET)
+#define CCM_PCCR_WDT_MASK               (1 << CCM_PCCR_WDT_OFFSET)
+
+#define CCM_CCSR_32KSR          (1 << 15)
+
+#define CCM_CCSR_CLKMODE1       (1 << 9)
+#define CCM_CCSR_CLKMODE0       (1 << 8)
+
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK   0x1f
+
+#define SYS_FMCR                0x14    /* Functional Muxing Control Reg */
+#define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
+
+static int _clk_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long _clk_generic_round_rate(struct clk *clk,
+                        unsigned long rate,
+                        u32 max_divisor)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > max_divisor)
+                div = max_divisor;
+
+        return parent_rate / div;
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg |= CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+
+        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
+                ;
+        return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+}
+
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        return _clk_generic_round_rate(clk, rate, 64);
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg =
+            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+                                       (clk->id << 3));
+        reg |= div << (clk->id << 3);
+        __raw_writel(reg, CCM_PCDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_usb_recalc(struct clk *clk)
+{
+        unsigned long usb_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+        return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long _clk_usb_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        return _clk_generic_round_rate(clk, rate, 8);
+}
+
+static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = CSCR() & ~CCM_CSCR_USB_MASK;
+        reg |= div << CCM_CSCR_USB_OFFSET;
+        __raw_writel(reg, CCM_CSCR);
+
+        return 0;
+}
+
+static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
+
+        return 2UL * parent_rate / pdf;
+}
+
+static unsigned long _clk_ssi1_recalc(struct clk *clk)
+{
+        return _clk_ssix_recalc(clk,
+                (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
+                >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
+}
+
+static unsigned long _clk_ssi2_recalc(struct clk *clk)
+{
+        return _clk_ssix_recalc(clk,
+                (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+                CCM_PCDR0_SSI2BAUDDIV_OFFSET);
+}
+
+static unsigned long _clk_nfc_recalc(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
+                >> CCM_PCDR0_NFCDIV_OFFSET;
+
+        return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+static unsigned long external_high_reference; /* in Hz */
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+        return external_high_reference;
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz.
+ */
+static struct clk ckih_clk = {
+        .get_rate = get_high_reference_clock_rate,
+};
+
+static unsigned long external_low_reference; /* in Hz */
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+        return external_low_reference;
+}
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+static struct clk ckil_clk = {
+        .get_rate = get_low_reference_clock_rate,
+};
+
+
+static unsigned long _clk_fpm_recalc(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) * 512;
+}
+
+/* Output of frequency pre multiplier */
+static struct clk fpm_clk = {
+        .parent = &ckil_clk,
+        .get_rate = _clk_fpm_recalc,
+};
+
+static unsigned long get_mpll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_MPCTL0);
+        pdf = (reg & CCM_MPCTL0_PD_MASK)  >> CCM_MPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk mpll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = get_mpll_clk,
+};
+
+static unsigned long _clk_fclk_get_rate(struct clk *clk)
+{
+        unsigned long parent_rate;
+        u32 div;
+
+        div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+        parent_rate = clk_get_rate(clk->parent);
+
+        return parent_rate / (div+1);
+}
+
+static struct clk fclk_clk = {
+        .parent = &mpll_clk,
+        .get_rate = _clk_fclk_get_rate
+};
+
+static unsigned long get_spll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_SPCTL0);
+        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk spll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = get_spll_clk,
+        .enable = _clk_spll_enable,
+        .disable = _clk_spll_disable,
+};
+
+static unsigned long get_hclk_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long bclk_pdf;
+
+        bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
+                >> CCM_CSCR_BCLK_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (bclk_pdf + 1);
+}
+
+static struct clk hclk_clk = {
+        .parent = &fclk_clk,
+        .get_rate = get_hclk_clk,
+};
+
+static unsigned long get_ipg_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long ipg_pdf;
+
+        ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (ipg_pdf + 1);
+}
+
+static struct clk ipg_clk = {
+        .parent = &hclk_clk,
+        .get_rate = get_ipg_clk,
+};
+
+static unsigned long _clk_perclkx_recalc(struct clk *clk)
+{
+        unsigned long perclk_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return 0;
+
+        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+        return parent_rate / (perclk_pdf + 1);
+}
+
+static struct clk per_clk[] = {
+        {
+                .id = 0,
+                .parent = &mpll_clk,
+                .get_rate = _clk_perclkx_recalc,
+        }, {
+                .id = 1,
+                .parent = &mpll_clk,
+                .get_rate = _clk_perclkx_recalc,
+        }, {
+                .id = 2,
+                .parent = &mpll_clk,
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                /* Enable/Disable done via lcd_clkc[1] */
+        }, {
+                .id = 3,
+                .parent = &mpll_clk,
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                /* Enable/Disable done via csi_clk[1] */
+        },
+};
+
+static struct clk uart_ipg_clk[];
+
+static struct clk uart_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[1],
+        }, {
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[2],
+        }, {
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[3],
+        },
+};
+
+static struct clk uart_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART1_REG,
+                .enable_shift = CCM_PCCR_UART1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART2_REG,
+                .enable_shift = CCM_PCCR_UART2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART3_REG,
+                .enable_shift = CCM_PCCR_UART3_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART4_REG,
+                .enable_shift = CCM_PCCR_UART4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt_ipg_clk[];
+
+static struct clk gpt_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &gpt_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &gpt_ipg_clk[1],
+        }, {
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &gpt_ipg_clk[2],
+        },
+};
+
+static struct clk gpt_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_GPT1_REG,
+                .enable_shift = CCM_PCCR_GPT1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_GPT2_REG,
+                .enable_shift = CCM_PCCR_GPT2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_GPT3_REG,
+                .enable_shift = CCM_PCCR_GPT3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk pwm_clk[] = {
+        {
+                .parent = &per_clk[0],
+                .secondary = &pwm_clk[1],
+        }, {
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_PWM_REG,
+                .enable_shift = CCM_PCCR_PWM_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc_ipg_clk[];
+
+static struct clk sdhc_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &sdhc_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &sdhc_ipg_clk[1],
+        },
+};
+
+static struct clk sdhc_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SDHC1_REG,
+                .enable_shift = CCM_PCCR_SDHC1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SDHC2_REG,
+                .enable_shift = CCM_PCCR_SDHC2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi_ipg_clk[];
+
+static struct clk cspi_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &cspi_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &cspi_ipg_clk[1],
+        }, {
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &cspi_ipg_clk[2],
+        },
+};
+
+static struct clk cspi_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_CSPI1_REG,
+                .enable_shift = CCM_PCCR_CSPI1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_CSPI2_REG,
+                .enable_shift = CCM_PCCR_CSPI2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_CSPI3_REG,
+                .enable_shift = CCM_PCCR_CSPI3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk lcdc_clk[] = {
+        {
+                .parent = &per_clk[2],
+                .secondary = &lcdc_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .parent = &ipg_clk,
+                .secondary = &lcdc_clk[2],
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_LCDC_REG,
+                .enable_shift = CCM_PCCR_LCDC_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
+                .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk csi_clk[] = {
+        {
+                .parent = &per_clk[3],
+                .secondary = &csi_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_CSI_REG,
+                .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk usb_clk[] = {
+        {
+                .parent = &spll_clk,
+                .secondary = &usb_clk[1],
+                .get_rate = _clk_usb_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_USBOTG_REG,
+                .enable_shift = CCM_PCCR_USBOTG_OFFSET,
+                .disable = _clk_disable,
+                .round_rate = _clk_usb_round_rate,
+                .set_rate = _clk_usb_set_rate,
+        }, {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
+                .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk ssi_ipg_clk[];
+
+static struct clk ssi_clk[] = {
+        {
+                .id = 0,
+                .parent = &mpll_clk,
+                .secondary = &ssi_ipg_clk[0],
+                .get_rate = _clk_ssi1_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
+                .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &mpll_clk,
+                .secondary = &ssi_ipg_clk[1],
+                .get_rate = _clk_ssi2_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
+                .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk ssi_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI1_REG,
+                .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI2_REG,
+                .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+
+static struct clk nfc_clk = {
+        .parent = &fclk_clk,
+        .get_rate = _clk_nfc_recalc,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_NFC_REG,
+        .enable_shift = CCM_PCCR_NFC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk dma_clk[] = {
+        {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_DMA_REG,
+                .enable_shift = CCM_PCCR_DMA_OFFSET,
+                .disable = _clk_disable,
+                .secondary = &dma_clk[1],
+        },  {
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_DMA_REG,
+                .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk brom_clk = {
+        .parent = &hclk_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_HCLK_BROM_REG,
+        .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk emma_clk[] = {
+        {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_EMMA_REG,
+                .enable_shift = CCM_PCCR_EMMA_OFFSET,
+                .disable = _clk_disable,
+                .secondary = &emma_clk[1],
+        }, {
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
+                .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk slcdc_clk[] = {
+        {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SLCDC_REG,
+                .enable_shift = CCM_PCCR_SLCDC_OFFSET,
+                .disable = _clk_disable,
+                .secondary = &slcdc_clk[1],
+        }, {
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
+                .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk wdog_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_WDT_REG,
+        .enable_shift = CCM_PCCR_WDT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_GPIO_REG,
+        .enable_shift = CCM_PCCR_GPIO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk i2c_clk = {
+        .id = 0,
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_I2C1_REG,
+        .enable_shift = CCM_PCCR_I2C1_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_KPP_REG,
+        .enable_shift = CCM_PCCR_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_OWIRE_REG,
+        .enable_shift = CCM_PCCR_OWIRE_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_RTC_REG,
+        .enable_shift = CCM_PCCR_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+        return _clk_generic_round_rate(clk, rate, 8);
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = __raw_readl(CCM_PCDR0);
+
+        if (clk->parent == &usb_clk[0]) {
+                reg &= ~CCM_PCDR0_48MDIV_MASK;
+                reg |= div << CCM_PCDR0_48MDIV_OFFSET;
+        }
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_clko_recalc(struct clk *clk)
+{
+        u32 div = 0;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->parent == &usb_clk[0]) /* 48M */
+                div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
+                         >> CCM_PCDR0_48MDIV_OFFSET;
+        div++;
+
+        return parent_rate / div;
+}
+
+static struct clk clko_clk;
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+        if (parent == &ckil_clk)
+                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &fpm_clk)
+                reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == mpll_clk.parent)
+                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == spll_clk.parent)
+                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mpll_clk)
+                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &spll_clk)
+                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &fclk_clk)
+                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &hclk_clk)
+                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[0])
+                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[1])
+                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[2])
+                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[3])
+                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi_clk[0])
+                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi_clk[1])
+                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_clk[0])
+                reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &clko_clk)
+                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, CCM_CCSR);
+
+        return 0;
+}
+
+static struct clk clko_clk = {
+        .get_rate = _clk_clko_recalc,
+        .set_rate = _clk_clko_set_rate,
+        .round_rate = _clk_clko_round_rate,
+        .set_parent = _clk_clko_set_parent,
+};
+
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] = {
+/* It's unlikely that any driver wants one of them directly:
+        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+        _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
+        _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
+        _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
+        _REGISTER_CLOCK(NULL, "spll", spll_clk)
+        _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
+        _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
+        _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
+*/
+        _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
+        _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
+        _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
+        _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
+        _REGISTER_CLOCK(NULL, "clko", clko_clk)
+        _REGISTER_CLOCK("imx21-uart.0", NULL, uart_clk[0])
+        _REGISTER_CLOCK("imx21-uart.1", NULL, uart_clk[1])
+        _REGISTER_CLOCK("imx21-uart.2", NULL, uart_clk[2])
+        _REGISTER_CLOCK("imx21-uart.3", NULL, uart_clk[3])
+        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
+        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
+        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
+        _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
+        _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
+        _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
+        _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
+        _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
+        _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
+        _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
+        _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
+        _REGISTER_CLOCK(NULL, "brom", brom_clk)
+        _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
+        _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK(NULL, "owire", owire_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+};
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+        u32 cscr;
+
+        external_low_reference = lref;
+        external_high_reference = href;
+
+        /* detect clock reference for both system PLL */
+        cscr = CSCR();
+        if (cscr & CCM_CSCR_MCU)
+                mpll_clk.parent = &ckih_clk;
+        else
+                mpll_clk.parent = &fpm_clk;
+
+        if (cscr & CCM_CSCR_SP)
+                spll_clk.parent = &ckih_clk;
+        else
+                spll_clk.parent = &fpm_clk;
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        /* Turn off all clock gates */
+        __raw_writel(0, CCM_PCCR0);
+        __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
+
+        /* This turns of the serial PLL as well */
+        spll_clk.disable(&spll_clk);
+
+        /* This will propagate to all children and init all the clock rates. */
+        clk_enable(&per_clk[0]);
+        clk_enable(&gpio_clk);
+
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+        clk_enable(&uart_clk[0]);
+#endif
+
+        mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
+                        MX21_INT_GPT1);
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
new file mode 100644
index 00000000000..e63e23504fe
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+
+#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+
+#define CCM_MPCTL       0x00
+#define CCM_UPCTL       0x04
+#define CCM_CCTL        0x08
+#define CCM_CGCR0       0x0C
+#define CCM_CGCR1       0x10
+#define CCM_CGCR2       0x14
+#define CCM_PCDR0       0x18
+#define CCM_PCDR1       0x1C
+#define CCM_PCDR2       0x20
+#define CCM_PCDR3       0x24
+#define CCM_RCSR        0x28
+#define CCM_CRDR        0x2C
+#define CCM_DCVR0       0x30
+#define CCM_DCVR1       0x34
+#define CCM_DCVR2       0x38
+#define CCM_DCVR3       0x3c
+#define CCM_LTR0        0x40
+#define CCM_LTR1        0x44
+#define CCM_LTR2        0x48
+#define CCM_LTR3        0x4c
+
+static unsigned long get_rate_mpll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+static unsigned long get_rate_upll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+unsigned long get_rate_arm(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_mpll();
+
+        if (cctl & (1 << 14))
+                rate = (rate * 3) >> 2;
+
+        return rate / ((cctl >> 30) + 1);
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+
+        return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        return get_rate_ahb(NULL) >> 1;
+}
+
+static unsigned long get_rate_per(int per)
+{
+        unsigned long ofs = (per & 0x3) * 8;
+        unsigned long reg = per & ~0x3;
+        unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
+        unsigned long fref;
+
+        if (readl(CRM_BASE + 0x64) & (1 << per))
+                fref = get_rate_upll();
+        else
+                fref = get_rate_ahb(NULL);
+
+        return fref / (val + 1);
+}
+
+static unsigned long get_rate_uart(struct clk *clk)
+{
+        return get_rate_per(15);
+}
+
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+        return get_rate_per(14);
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+        return get_rate_per(13);
+}
+
+static unsigned long get_rate_i2c(struct clk *clk)
+{
+        return get_rate_per(6);
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        return get_rate_per(8);
+}
+
+static unsigned long get_rate_gpt(struct clk *clk)
+{
+        return get_rate_per(5);
+}
+
+static unsigned long get_rate_lcdc(struct clk *clk)
+{
+        return get_rate_per(7);
+}
+
+static unsigned long get_rate_esdhc1(struct clk *clk)
+{
+        return get_rate_per(3);
+}
+
+static unsigned long get_rate_esdhc2(struct clk *clk)
+{
+        return get_rate_per(4);
+}
+
+static unsigned long get_rate_csi(struct clk *clk)
+{
+        return get_rate_per(0);
+}
+
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_upll();
+
+        return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
+}
+
+static int clk_cgcr_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void clk_cgcr_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, s)        \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = CRM_BASE + er,        \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .set_rate       = sr,                   \
+                .enable         = clk_cgcr_enable,      \
+                .disable        = clk_cgcr_disable,     \
+                .secondary      = s,                    \
+        }
+
+/*
+ * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
+ * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
+ * taken from the Freescale released BSP.
+ *
+ * bit  reg     offset  clock
+ *
+ * 0    CGCR1   0       AUDMUX
+ * 12   CGCR1   12      ESAI
+ * 16   CGCR1   16      GPIO1
+ * 17   CGCR1   17      GPIO2
+ * 18   CGCR1   18      GPIO3
+ * 23   CGCR1   23      I2C1
+ * 24   CGCR1   24      I2C2
+ * 25   CGCR1   25      I2C3
+ * 27   CGCR1   27      IOMUXC
+ * 28   CGCR1   28      KPP
+ * 30   CGCR1   30      OWIRE
+ * 36   CGCR2   4       RTIC
+ * 51   CGCR2   19      WDOG
+ */
+
+DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
+DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
+DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1,  NULL, NULL);
+DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,  NULL,
+                &esdhc1_ahb_clk);
+DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
+DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
+                &esdhc2_ahb_clk);
+DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL,       NULL, NULL);
+DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
+DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
+DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
+DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
+DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
+DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
+DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
+DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
+DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
+DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
+DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
+DEFINE_CLOCK(pwm1_clk,   0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(pwm2_clk,   0, CCM_CGCR2,  0, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(pwm3_clk,   0, CCM_CGCR2,  1, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(pwm4_clk,   0, CCM_CGCR2,  2, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
+DEFINE_CLOCK(fec_clk,    0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
+DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(lcdc_clk,   0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
+DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
+DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2,  6, get_rate_ipg, NULL, &sdma_ahb_clk);
+DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
+                &esdhc1_per_clk);
+DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
+                &esdhc2_per_clk);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
+DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
+DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(can2_clk,   1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
+
+#define _REGISTER_CLOCK(d, n, c)        \
+        {                               \
+                .dev_id = d,            \
+                .con_id = n,            \
+                .clk = &c,              \
+        },
+
+static struct clk_lookup lookups[] = {
+        /* i.mx25 has the i.mx21 type uart */
+        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        /* i.mx25 has the i.mx35 type cspi */
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
+        _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
+        _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
+        _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
+        /* i.mx25 has the i.mx35 type sdma */
+        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+};
+
+int __init mx25_clocks_init(void)
+{
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        /* Turn off all clocks except the ones we need to survive, namely:
+         * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
+         * SCC
+         */
+        __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
+        __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
+        __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+        clk_enable(&uart1_clk);
+#endif
+
+        /* Clock source for lcdc and csi is upll */
+        __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
+                        CRM_BASE + 0x64);
+
+        /* Clock source for gpt is ahb_div */
+        __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
+
+        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
new file mode 100644
index 00000000000..6912b821b37
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -0,0 +1,764 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+
+#include <asm/div64.h>
+
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+#define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR                IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
+#define CCM_PCDR0               IO_ADDR_CCM(0x18)
+#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0               IO_ADDR_CCM(0x20)
+#define CCM_PCCR1               IO_ADDR_CCM(0x24)
+#define CCM_CCSR                IO_ADDR_CCM(0x28)
+#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_UPDATE_DIS     (1 << 31)
+#define CCM_CSCR_SSI2           (1 << 23)
+#define CCM_CSCR_SSI1           (1 << 22)
+#define CCM_CSCR_VPU            (1 << 21)
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+static struct clk mpll_main1_clk, mpll_main2_clk;
+
+static int clk_pccr_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        if (!clk->enable_reg)
+                return 0;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void clk_pccr_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        if (!clk->enable_reg)
+                return;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int clk_spll_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg |= CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+
+        while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
+
+        return 0;
+}
+
+static void clk_spll_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+}
+
+static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+{
+        int cscr = __raw_readl(CCM_CSCR);
+
+        if (clk->parent == parent)
+                return 0;
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+                if (parent == &mpll_main1_clk) {
+                        cscr |= CCM_CSCR_ARM_SRC;
+                } else {
+                        if (parent == &mpll_main2_clk)
+                                cscr &= ~CCM_CSCR_ARM_SRC;
+                        else
+                                return -EINVAL;
+                }
+                __raw_writel(cscr, CCM_CSCR);
+                clk->parent = parent;
+                return 0;
+        }
+        return -ENODEV;
+}
+
+static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
+{
+        int div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 4)
+                div = 4;
+
+        return parent_rate / div;
+}
+
+static int set_rate_cpu(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        uint32_t reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 4 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_CSCR);
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+                reg &= ~(3 << 12);
+                reg |= div << 12;
+                reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
+                __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
+        } else {
+                printk(KERN_ERR "Can't set CPU frequency!\n");
+        }
+
+        return 0;
+}
+
+static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 64)
+                div = 64;
+
+        return parent_rate / div;
+}
+
+static int set_rate_per(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
+        reg |= div << (clk->id << 3);
+        __raw_writel(reg, CCM_PCDR1);
+
+        return 0;
+}
+
+static unsigned long get_rate_usb(struct clk *clk)
+{
+        unsigned long usb_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
+
+        return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                pdf += 4;  /* MX27 TO2+ */
+        else
+                pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
+
+        return 2UL * parent_rate / pdf;
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+        return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
+}
+
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+        return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
+        else
+                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
+
+        return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long get_rate_vpu(struct clk *clk)
+{
+        unsigned long vpu_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
+                vpu_pdf += 4;
+        } else {
+                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
+                vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+        }
+
+        return 2UL * parent_rate / vpu_pdf;
+}
+
+static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static unsigned long get_rate_parent(struct clk *clk)
+{
+        return clk_get_rate(clk->parent);
+}
+
+static int set_rate_parent(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+/* in Hz */
+static unsigned long external_high_reference = 26000000;
+
+static unsigned long get_rate_high_reference(struct clk *clk)
+{
+        return external_high_reference;
+}
+
+/* in Hz */
+static unsigned long external_low_reference = 32768;
+
+static unsigned long get_rate_low_reference(struct clk *clk)
+{
+        return external_low_reference;
+}
+
+static unsigned long get_rate_fpm(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) * 1024;
+}
+
+static unsigned long get_rate_mpll(struct clk *clk)
+{
+        return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
+                        clk_get_rate(clk->parent));
+}
+
+static unsigned long get_rate_mpll_main(struct clk *clk)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        /* i.MX27 TO2:
+         * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
+         * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
+         */
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
+                return 2UL * parent_rate / 3UL;
+
+        return parent_rate;
+}
+
+static unsigned long get_rate_spll(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long rate;
+
+        rate = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_SPCTL0);
+
+        /* On TO2 we have to write the value back. Otherwise we
+         * read 0 from this register the next time.
+         */
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                __raw_writel(reg, CCM_SPCTL0);
+
+        return mxc_decode_pll(reg, rate);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+        u32 div;
+        unsigned long rate;
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
+        else
+                div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (div + 1);
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long rate, bclk_pdf;
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
+        else
+                bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (bclk_pdf + 1);
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        unsigned long rate, ipg_pdf;
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+                return clk_get_rate(clk->parent);
+        else
+                ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (ipg_pdf + 1);
+}
+
+static unsigned long get_rate_per(struct clk *clk)
+{
+        unsigned long perclk_pdf, parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return 0;
+
+        perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
+
+        return parent_rate / (perclk_pdf + 1);
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+static struct clk ckih_clk = {
+        .get_rate       = get_rate_high_reference,
+};
+
+static struct clk mpll_clk = {
+        .parent         = &ckih_clk,
+        .get_rate       = get_rate_mpll,
+};
+
+/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+ * It provides the clock source whose rate is same as MPLL
+ */
+static struct clk mpll_main1_clk = {
+        .id             = 0,
+        .parent         = &mpll_clk,
+        .get_rate       = get_rate_mpll_main,
+};
+
+/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+ * It provides the clock source whose rate is same MPLL * 2 / 3
+ */
+static struct clk mpll_main2_clk = {
+        .id             = 1,
+        .parent         = &mpll_clk,
+        .get_rate       = get_rate_mpll_main,
+};
+
+static struct clk ahb_clk = {
+        .parent         = &mpll_main2_clk,
+        .get_rate       = get_rate_ahb,
+};
+
+static struct clk ipg_clk = {
+        .parent         = &ahb_clk,
+        .get_rate       = get_rate_ipg,
+};
+
+static struct clk cpu_clk = {
+        .parent = &mpll_main2_clk,
+        .set_parent = clk_cpu_set_parent,
+        .round_rate = round_rate_cpu,
+        .get_rate = get_rate_cpu,
+        .set_rate = set_rate_cpu,
+};
+
+static struct clk spll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = get_rate_spll,
+        .enable = clk_spll_enable,
+        .disable = clk_spll_disable,
+};
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+static struct clk ckil_clk = {
+        .get_rate = get_rate_low_reference,
+};
+
+/* Output of frequency pre multiplier */
+static struct clk fpm_clk = {
+        .parent = &ckil_clk,
+        .get_rate = get_rate_fpm,
+};
+
+#define PCCR0 CCM_PCCR0
+#define PCCR1 CCM_PCCR1
+
+#define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .enable         = clk_pccr_enable,      \
+                .disable        = clk_pccr_disable,     \
+                .secondary      = s,                    \
+                .parent         = p,                    \
+        }
+
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
+        static struct clk name = {                              \
+                .id             = i,                            \
+                .enable_reg     = er,                           \
+                .enable_shift   = es,                           \
+                .get_rate       = get_rate_##getsetround,       \
+                .set_rate       = set_rate_##getsetround,       \
+                .round_rate     = round_rate_##getsetround,     \
+                .enable         = clk_pccr_enable,              \
+                .disable        = clk_pccr_disable,             \
+                .secondary      = s,                            \
+                .parent         = p,                            \
+        }
+
+/* Forward declaration to keep the following list in order */
+static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
+                  dma_clk1, lcdc_clk2, vpu_clk1;
+
+/* All clocks we can gate through PCCRx in the order of PCCRx bits */
+DEFINE_CLOCK(ssi2_clk1,    1, PCCR0,  0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ssi1_clk1,    0, PCCR0,  1, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(slcdc_clk,    0, PCCR0,  2, NULL, &slcdc_clk1, &ahb_clk);
+DEFINE_CLOCK(sdhc3_clk1,   0, PCCR0,  3, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdhc2_clk1,   0, PCCR0,  4, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdhc1_clk1,   0, PCCR0,  5, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(scc_clk,      0, PCCR0,  6, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sahara2_clk,  0, PCCR0,  7, NULL, &sahara2_clk1, &ahb_clk);
+DEFINE_CLOCK(rtic_clk,     0, PCCR0,  8, NULL, &rtic_clk1, &ahb_clk);
+DEFINE_CLOCK(rtc_clk,      0, PCCR0,  9, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pwm_clk1,     0, PCCR0, 11, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(owire_clk,    0, PCCR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(mstick_clk1,  0, PCCR0, 13, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(lcdc_clk1,    0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
+DEFINE_CLOCK(kpp_clk,      0, PCCR0, 15, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(iim_clk,      0, PCCR0, 16, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(i2c2_clk,     1, PCCR0, 17, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(i2c1_clk,     0, PCCR0, 18, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt6_clk1,    0, PCCR0, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt5_clk1,    0, PCCR0, 20, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt4_clk1,    0, PCCR0, 21, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt3_clk1,    0, PCCR0, 22, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt2_clk1,    0, PCCR0, 23, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt1_clk1,    0, PCCR0, 24, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpio_clk,     0, PCCR0, 25, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(fec_clk,      0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
+DEFINE_CLOCK(emma_clk,     0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
+DEFINE_CLOCK(dma_clk,      0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
+DEFINE_CLOCK(cspi13_clk1,  0, PCCR0, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi2_clk1,   0, PCCR0, 30, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi1_clk1,   0, PCCR0, 31, NULL, NULL, &ipg_clk);
+
+DEFINE_CLOCK(mstick_clk,   0, PCCR1,  2, NULL, &mstick_clk1, &ipg_clk);
+DEFINE_CLOCK(nfc_clk,      0, PCCR1,  3, get_rate_nfc, NULL, &cpu_clk);
+DEFINE_CLOCK(ssi2_clk,     1, PCCR1,  4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
+DEFINE_CLOCK(ssi1_clk,     0, PCCR1,  5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
+DEFINE_CLOCK(vpu_clk,      0, PCCR1,  6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
+DEFINE_CLOCK1(per4_clk,    3, PCCR1,  7, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per3_clk,    2, PCCR1,  8, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per2_clk,    1, PCCR1,  9, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per1_clk,    0, PCCR1, 10, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK(usb_clk1,     0, PCCR1, 11, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(slcdc_clk1,   0, PCCR1, 12, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(rtic_clk1,    0, PCCR1, 14, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(lcdc_clk2,    0, PCCR1, 15, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(vpu_clk1,     0, PCCR1, 16, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(fec_clk1,     0, PCCR1, 17, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(emma_clk1,    0, PCCR1, 18, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(ata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
+DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart5_clk1,   0, PCCR1, 27, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart4_clk1,   0, PCCR1, 28, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart3_clk1,   0, PCCR1, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
+
+/* Clocks we cannot directly gate, but drivers need their rates */
+DEFINE_CLOCK(cspi1_clk,    0, NULL,   0, NULL, &cspi1_clk1, &per2_clk);
+DEFINE_CLOCK(cspi2_clk,    1, NULL,   0, NULL, &cspi2_clk1, &per2_clk);
+DEFINE_CLOCK(cspi3_clk,    2, NULL,   0, NULL, &cspi13_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc1_clk,    0, NULL,   0, NULL, &sdhc1_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc2_clk,    1, NULL,   0, NULL, &sdhc2_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc3_clk,    2, NULL,   0, NULL, &sdhc3_clk1, &per2_clk);
+DEFINE_CLOCK(pwm_clk,      0, NULL,   0, NULL, &pwm_clk1, &per1_clk);
+DEFINE_CLOCK(gpt1_clk,     0, NULL,   0, NULL, &gpt1_clk1, &per1_clk);
+DEFINE_CLOCK(gpt2_clk,     1, NULL,   0, NULL, &gpt2_clk1, &per1_clk);
+DEFINE_CLOCK(gpt3_clk,     2, NULL,   0, NULL, &gpt3_clk1, &per1_clk);
+DEFINE_CLOCK(gpt4_clk,     3, NULL,   0, NULL, &gpt4_clk1, &per1_clk);
+DEFINE_CLOCK(gpt5_clk,     4, NULL,   0, NULL, &gpt5_clk1, &per1_clk);
+DEFINE_CLOCK(gpt6_clk,     5, NULL,   0, NULL, &gpt6_clk1, &per1_clk);
+DEFINE_CLOCK(uart1_clk,    0, NULL,   0, NULL, &uart1_clk1, &per1_clk);
+DEFINE_CLOCK(uart2_clk,    1, NULL,   0, NULL, &uart2_clk1, &per1_clk);
+DEFINE_CLOCK(uart3_clk,    2, NULL,   0, NULL, &uart3_clk1, &per1_clk);
+DEFINE_CLOCK(uart4_clk,    3, NULL,   0, NULL, &uart4_clk1, &per1_clk);
+DEFINE_CLOCK(uart5_clk,    4, NULL,   0, NULL, &uart5_clk1, &per1_clk);
+DEFINE_CLOCK(uart6_clk,    5, NULL,   0, NULL, &uart6_clk1, &per1_clk);
+DEFINE_CLOCK1(lcdc_clk,    0, NULL,   0, parent, &lcdc_clk1, &per3_clk);
+DEFINE_CLOCK1(csi_clk,     0, NULL,   0, parent, &csi_clk1, &per4_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        /* i.mx27 has the i.mx21 type uart */
+        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk)
+        _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
+        _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
+        _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
+        _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
+        _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
+        _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+        _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
+        _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
+        _REGISTER_CLOCK(NULL, "dma", dma_clk)
+        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+        _REGISTER_CLOCK(NULL, "brom", brom_clk)
+        _REGISTER_CLOCK(NULL, "emma", emma_clk)
+        _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
+        _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK(NULL, "emi", emi_clk)
+        _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
+        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
+        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+        _REGISTER_CLOCK(NULL, "scc", scc_clk)
+};
+
+/* Adjust the clock path for TO2 and later */
+static void __init to2_adjust_clocks(void)
+{
+        unsigned long cscr = __raw_readl(CCM_CSCR);
+
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+                if (cscr & CCM_CSCR_ARM_SRC)
+                        cpu_clk.parent = &mpll_main1_clk;
+
+                if (!(cscr & CCM_CSCR_SSI2))
+                        ssi1_clk.parent = &spll_clk;
+
+                if (!(cscr & CCM_CSCR_SSI1))
+                        ssi1_clk.parent = &spll_clk;
+
+                if (!(cscr & CCM_CSCR_VPU))
+                        vpu_clk.parent = &spll_clk;
+        } else {
+                cpu_clk.parent = &mpll_clk;
+                cpu_clk.set_parent = NULL;
+                cpu_clk.round_rate = NULL;
+                cpu_clk.set_rate = NULL;
+                ahb_clk.parent = &mpll_clk;
+
+                per1_clk.parent = &mpll_clk;
+                per2_clk.parent = &mpll_clk;
+                per3_clk.parent = &mpll_clk;
+                per4_clk.parent = &mpll_clk;
+
+                ssi1_clk.parent = &mpll_clk;
+                ssi2_clk.parent = &mpll_clk;
+
+                vpu_clk.parent = &mpll_clk;
+        }
+}
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx27_clocks_init(unsigned long fref)
+{
+        u32 cscr = __raw_readl(CCM_CSCR);
+
+        external_high_reference = fref;
+
+        /* detect clock reference for both system PLLs */
+        if (cscr & CCM_CSCR_MCU)
+                mpll_clk.parent = &ckih_clk;
+        else
+                mpll_clk.parent = &fpm_clk;
+
+        if (cscr & CCM_CSCR_SP)
+                spll_clk.parent = &ckih_clk;
+        else
+                spll_clk.parent = &fpm_clk;
+
+        to2_adjust_clocks();
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        /* Turn off all clocks we do not need */
+        __raw_writel(0, CCM_PCCR0);
+        __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
+
+        spll_clk.disable(&spll_clk);
+
+        /* enable basic clocks */
+        clk_enable(&per1_clk);
+        clk_enable(&gpio_clk);
+        clk_enable(&emi_clk);
+        clk_enable(&iim_clk);
+
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+        clk_enable(&uart1_clk);
+#endif
+
+        mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+                        MX27_INT_GPT1);
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
new file mode 100644
index 00000000000..d973770b1f9
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -0,0 +1,630 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <asm/div64.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/mx31.h>
+#include <mach/common.h>
+
+#include "crmregs-imx31.h"
+
+#define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
+
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
+{
+        u32 min_pre, temp_pre, old_err, err;
+
+        if (div >= 512) {
+                *pre = 8;
+                *post = 64;
+        } else if (div >= 64) {
+                min_pre = (div - 1) / 64 + 1;
+                old_err = 8;
+                for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+                        err = div % temp_pre;
+                        if (err == 0) {
+                                *pre = temp_pre;
+                                break;
+                        }
+                        err = temp_pre - err;
+                        if (err < old_err) {
+                                old_err = err;
+                                *pre = temp_pre;
+                        }
+                }
+                *post = (div + *pre - 1) / *pre;
+        } else if (div <= 8) {
+                *pre = div;
+                *post = 1;
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+
+static struct clk mcu_pll_clk;
+static struct clk serial_pll_clk;
+static struct clk ipg_clk;
+static struct clk ckih_clk;
+
+static int cgr_enable(struct clk *clk)
+{
+        u32 reg;
+
+        if (!clk->enable_reg)
+                return 0;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 3 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void cgr_disable(struct clk *clk)
+{
+        u32 reg;
+
+        if (!clk->enable_reg)
+                return;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+
+        /* special case for EMI clock */
+        if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
+                reg |= (1 << clk->enable_shift);
+
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long pll_ref_get_rate(void)
+{
+        unsigned long ccmr;
+        unsigned int prcs;
+
+        ccmr = __raw_readl(MXC_CCM_CCMR);
+        prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
+        if (prcs == 0x1)
+                return CKIL_CLK_FREQ * 1024;
+        else
+                return clk_get_rate(&ckih_clk);
+}
+
+static unsigned long usb_pll_get_rate(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(MXC_CCM_UPCTL);
+
+        return mxc_decode_pll(reg, pll_ref_get_rate());
+}
+
+static unsigned long serial_pll_get_rate(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(MXC_CCM_SRPCTL);
+
+        return mxc_decode_pll(reg, pll_ref_get_rate());
+}
+
+static unsigned long mcu_pll_get_rate(struct clk *clk)
+{
+        unsigned long reg, ccmr;
+
+        ccmr = __raw_readl(MXC_CCM_CCMR);
+
+        if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
+                return clk_get_rate(&ckih_clk);
+
+        reg = __raw_readl(MXC_CCM_MPCTL);
+
+        return mxc_decode_pll(reg, pll_ref_get_rate());
+}
+
+static int usb_pll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg |= MXC_CCM_CCMR_UPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+
+        /* No lock bit on MX31, so using max time from spec */
+        udelay(80);
+
+        return 0;
+}
+
+static void usb_pll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_UPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+static int serial_pll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg |= MXC_CCM_CCMR_SPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+
+        /* No lock bit on MX31, so using max time from spec */
+        udelay(80);
+
+        return 0;
+}
+
+static void serial_pll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_SPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
+#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
+#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
+
+static unsigned long mcu_main_get_rate(struct clk *clk)
+{
+        u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
+
+        if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
+                return clk_get_rate(&serial_pll_clk);
+        else
+                return clk_get_rate(&mcu_pll_clk);
+}
+
+static unsigned long ahb_get_rate(struct clk *clk)
+{
+        unsigned long max_pdf;
+
+        max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
+                       MXC_CCM_PDR0_MAX_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (max_pdf + 1);
+}
+
+static unsigned long ipg_get_rate(struct clk *clk)
+{
+        unsigned long ipg_pdf;
+
+        ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
+                       MXC_CCM_PDR0_IPG_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ipg_pdf + 1);
+}
+
+static unsigned long nfc_get_rate(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+
+        nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
+                       MXC_CCM_PDR0_NFC_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (nfc_pdf + 1);
+}
+
+static unsigned long hsp_get_rate(struct clk *clk)
+{
+        unsigned long hsp_pdf;
+
+        hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
+                       MXC_CCM_PDR0_HSP_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (hsp_pdf + 1);
+}
+
+static unsigned long usb_get_rate(struct clk *clk)
+{
+        unsigned long usb_pdf, usb_prepdf;
+
+        usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
+                       MXC_CCM_PDR1_USB_PODF_OFFSET);
+        usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
+                          MXC_CCM_PDR1_USB_PRDF_OFFSET);
+        return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
+}
+
+static unsigned long csi_get_rate(struct clk *clk)
+{
+        u32 reg, pre, post;
+
+        reg = __raw_readl(MXC_CCM_PDR0);
+        pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
+            MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+        pre++;
+        post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
+            MXC_CCM_PDR0_CSI_PODF_OFFSET;
+        post++;
+        return clk_get_rate(clk->parent) / (pre * post);
+}
+
+static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 pre, post, parent = clk_get_rate(clk->parent);
+        u32 div = parent / rate;
+
+        if (parent % rate)
+                div++;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        return parent / (pre * post);
+}
+
+static int csi_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if ((parent / div) != rate)
+                return -EINVAL;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        /* Set CSI clock divider */
+        reg = __raw_readl(MXC_CCM_PDR0) &
+            ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
+        reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
+        reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+        __raw_writel(reg, MXC_CCM_PDR0);
+
+        return 0;
+}
+
+static unsigned long ssi1_get_rate(struct clk *clk)
+{
+        unsigned long ssi1_pdf, ssi1_prepdf;
+
+        ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
+                        MXC_CCM_PDR1_SSI1_PODF_OFFSET);
+        ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
+}
+
+static unsigned long ssi2_get_rate(struct clk *clk)
+{
+        unsigned long ssi2_pdf, ssi2_prepdf;
+
+        ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
+                        MXC_CCM_PDR1_SSI2_PODF_OFFSET);
+        ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
+}
+
+static unsigned long firi_get_rate(struct clk *clk)
+{
+        unsigned long firi_pdf, firi_prepdf;
+
+        firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
+                        MXC_CCM_PDR1_FIRI_PODF_OFFSET);
+        firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
+}
+
+static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 pre, post;
+        u32 parent = clk_get_rate(clk->parent);
+        u32 div = parent / rate;
+
+        if (parent % rate)
+                div++;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        return parent / (pre * post);
+
+}
+
+static int firi_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if ((parent / div) != rate)
+                return -EINVAL;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        /* Set FIRI clock divider */
+        reg = __raw_readl(MXC_CCM_PDR1) &
+            ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
+        reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
+        reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_PDR1);
+
+        return 0;
+}
+
+static unsigned long mbx_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 2;
+}
+
+static unsigned long mstick1_get_rate(struct clk *clk)
+{
+        unsigned long msti_pdf;
+
+        msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
+                        MXC_CCM_PDR2_MST1_PDF_OFFSET);
+        return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long mstick2_get_rate(struct clk *clk)
+{
+        unsigned long msti_pdf;
+
+        msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
+                        MXC_CCM_PDR2_MST2_PDF_OFFSET);
+        return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
+static struct clk ckih_clk = {
+        .get_rate = clk_ckih_get_rate,
+};
+
+static struct clk mcu_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = mcu_pll_get_rate,
+};
+
+static struct clk mcu_main_clk = {
+        .parent = &mcu_pll_clk,
+        .get_rate = mcu_main_get_rate,
+};
+
+static struct clk serial_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = serial_pll_get_rate,
+        .enable = serial_pll_enable,
+        .disable = serial_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = usb_pll_get_rate,
+        .enable = usb_pll_enable,
+        .disable = usb_pll_disable,
+};
+
+static struct clk ahb_clk = {
+        .parent = &mcu_main_clk,
+        .get_rate = ahb_get_rate,
+};
+
+#define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .enable         = cgr_enable,           \
+                .disable        = cgr_disable,          \
+                .secondary      = s,                    \
+                .parent         = p,                    \
+        }
+
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
+        static struct clk name = {                              \
+                .id             = i,                            \
+                .enable_reg     = er,                           \
+                .enable_shift   = es,                           \
+                .get_rate       = getsetround##_get_rate,       \
+                .set_rate       = getsetround##_set_rate,       \
+                .round_rate     = getsetround##_round_rate,     \
+                .enable         = cgr_enable,                   \
+                .disable        = cgr_disable,                  \
+                .secondary      = s,                            \
+                .parent         = p,                            \
+        }
+
+DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
+
+DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart2_clk,   1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(ssi1_clk,    0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
+DEFINE_CLOCK(i2c1_clk,    0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(i2c2_clk,    1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
+
+DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
+DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
+DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(kpp_clk,     0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ipu_clk,     0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
+DEFINE_CLOCK(uart3_clk,   2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart4_clk,   3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart5_clk,   4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(owire_clk,   0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
+
+DEFINE_CLOCK(ssi2_clk,    1, MXC_CCM_CGR2,  0, ssi2_get_rate, NULL, &serial_pll_clk);
+DEFINE_CLOCK(cspi1_clk,   0, MXC_CCM_CGR2,  2, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi2_clk,   1, MXC_CCM_CGR2,  4, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(mbx_clk,     0, MXC_CCM_CGR2,  6, mbx_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(emi_clk,     0, MXC_CCM_CGR2,  8, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(rtic_clk,    0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK1(firi_clk,   0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
+
+DEFINE_CLOCK(sdma_clk2,   0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "emi", emi_clk)
+        _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+        _REGISTER_CLOCK(NULL, "epit", epit1_clk)
+        _REGISTER_CLOCK(NULL, "epit", epit2_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
+        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
+        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
+        /* i.mx31 has the i.mx21 type uart */
+        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
+        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK(NULL, "firi", firi_clk)
+        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+        _REGISTER_CLOCK(NULL, "rng", rng_clk)
+        _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
+        _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
+        _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
+        _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
+        _REGISTER_CLOCK(NULL, "scc", scc_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
+        _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
+        _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
+};
+
+int __init mx31_clocks_init(unsigned long fref)
+{
+        u32 reg;
+
+        ckih_rate = fref;
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        /* change the csi_clk parent if necessary */
+        reg = __raw_readl(MXC_CCM_CCMR);
+        if (!(reg & MXC_CCM_CCMR_CSCS))
+                if (clk_set_parent(&csi_clk, &usb_pll_clk))
+                        pr_err("%s: error changing csi_clk parent\n", __func__);
+
+
+        /* Turn off all possible clocks */
+        __raw_writel((3 << 4), MXC_CCM_CGR0);
+        __raw_writel(0, MXC_CCM_CGR1);
+        __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
+                     1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
+                                           MX32, but still required to be set */
+                     MXC_CCM_CGR2);
+
+        /*
+         * Before turning off usb_pll make sure ipg_per_clk is generated
+         * by ipg_clk and not usb_pll.
+         */
+        __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
+
+        usb_pll_disable(&usb_pll_clk);
+
+        pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
+
+        clk_enable(&gpt_clk);
+        clk_enable(&emi_clk);
+        clk_enable(&iim_clk);
+
+        clk_enable(&serial_pll_clk);
+
+        mx31_read_cpu_rev();
+
+        if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
+                reg = __raw_readl(MXC_CCM_PMCR1);
+                /* No PLL restart on DVFS switch; enable auto EMI handshake */
+                reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
+                __raw_writel(reg, MXC_CCM_PMCR1);
+        }
+
+        mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
+                        MX31_INT_GPT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
new file mode 100644
index 00000000000..88b62a071ae
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#define CCM_BASE        MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
+
+#define CCM_CCMR        0x00
+#define CCM_PDR0        0x04
+#define CCM_PDR1        0x08
+#define CCM_PDR2        0x0C
+#define CCM_PDR3        0x10
+#define CCM_PDR4        0x14
+#define CCM_RCSR        0x18
+#define CCM_MPCTL       0x1C
+#define CCM_PPCTL       0x20
+#define CCM_ACMR        0x24
+#define CCM_COSR        0x28
+#define CCM_CGR0        0x2C
+#define CCM_CGR1        0x30
+#define CCM_CGR2        0x34
+#define CCM_CGR3        0x38
+
+#ifdef HAVE_SET_RATE_SUPPORT
+static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
+{
+        u32 min_pre, temp_pre, old_err, err;
+
+        min_pre = (div - 1) / maxpost + 1;
+        old_err = 8;
+
+        for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+                if (div > (temp_pre * maxpost))
+                        break;
+
+                if (div < (temp_pre * temp_pre))
+                        continue;
+
+                err = div % temp_pre;
+
+                if (err == 0) {
+                        *pre = temp_pre;
+                        break;
+                }
+
+                err = temp_pre - err;
+
+                if (err < old_err) {
+                        old_err = err;
+                        *pre = temp_pre;
+                }
+        }
+
+        *post = (div + *pre - 1) / *pre;
+}
+
+/* get the best values for a 3-bit divider combined with a 6-bit divider */
+static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
+{
+        if (div >= 512) {
+                *pre = 8;
+                *post = 64;
+        } else if (div >= 64) {
+                calc_dividers(div, pre, post, 64);
+        } else if (div <= 8) {
+                *pre = div;
+                *post = 1;
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+
+/* get the best values for two cascaded 3-bit dividers */
+static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
+{
+        if (div >= 64) {
+                *pre = *post = 8;
+        } else if (div > 8) {
+                calc_dividers(div, pre, post, 8);
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+#endif
+
+static unsigned long get_rate_mpll(void)
+{
+        ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+static unsigned long get_rate_ppll(void)
+{
+        ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
+
+        return mxc_decode_pll(ppctl, 24000000);
+}
+
+struct arm_ahb_div {
+        unsigned char arm, ahb, sel;
+};
+
+static struct arm_ahb_div clk_consumer[] = {
+        { .arm = 1, .ahb = 4, .sel = 0},
+        { .arm = 1, .ahb = 3, .sel = 1},
+        { .arm = 2, .ahb = 2, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 4, .ahb = 1, .sel = 0},
+        { .arm = 1, .ahb = 5, .sel = 0},
+        { .arm = 1, .ahb = 8, .sel = 0},
+        { .arm = 1, .ahb = 6, .sel = 1},
+        { .arm = 2, .ahb = 4, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 4, .ahb = 2, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static unsigned long get_rate_arm(void)
+{
+        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        struct arm_ahb_div *aad;
+        unsigned long fref = get_rate_mpll();
+
+        aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+        if (aad->sel)
+                fref = fref * 3 / 4;
+
+        return fref / aad->arm;
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        struct arm_ahb_div *aad;
+        unsigned long fref = get_rate_arm();
+
+        aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+
+        return fref / aad->ahb;
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        return get_rate_ahb(NULL) >> 1;
+}
+
+static unsigned long get_rate_uart(struct clk *clk)
+{
+        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
+
+        if (pdr3 & (1 << 14))
+                return get_rate_arm() / div;
+        else
+                return get_rate_ppll() / div;
+}
+
+static unsigned long get_rate_sdhc(struct clk *clk)
+{
+        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+        unsigned long div, rate;
+
+        if (pdr3 & (1 << 6))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        switch (clk->id) {
+        default:
+        case 0:
+                div = pdr3 & 0x3f;
+                break;
+        case 1:
+                div = (pdr3 >> 8) & 0x3f;
+                break;
+        case 2:
+                div = (pdr3 >> 16) & 0x3f;
+                break;
+        }
+
+        return rate / (div + 1);
+}
+
+static unsigned long get_rate_mshc(struct clk *clk)
+{
+        unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
+        unsigned long div1, div2, rate;
+
+        if (pdr1 & (1 << 7))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        div1 = (pdr1 >> 29) & 0x7;
+        div2 = (pdr1 >> 22) & 0x3f;
+
+        return rate / ((div1 + 1) * (div2 + 1));
+}
+
+static unsigned long get_rate_ssi(struct clk *clk)
+{
+        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long div1, div2, rate;
+
+        if (pdr2 & (1 << 6))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        switch (clk->id) {
+        default:
+        case 0:
+                div1 = pdr2 & 0x3f;
+                div2 = (pdr2 >> 24) & 0x7;
+                break;
+        case 1:
+                div1 = (pdr2 >> 8) & 0x3f;
+                div2 = (pdr2 >> 27) & 0x7;
+                break;
+        }
+
+        return rate / ((div1 + 1) * (div2 + 1));
+}
+
+static unsigned long get_rate_csi(struct clk *clk)
+{
+        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long rate;
+
+        if (pdr2 & (1 << 7))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        return rate / (((pdr2 >> 16) & 0x3f) + 1);
+}
+
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long rate;
+
+        if (pdr4 & (1 << 9))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        return rate / (((pdr4 >> 22) & 0x3f) + 1);
+}
+
+static unsigned long get_rate_ipg_per(struct clk *clk)
+{
+        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long div;
+
+        if (pdr0 & (1 << 26)) {
+                div = (pdr4 >> 16) & 0x3f;
+                return get_rate_arm() / (div + 1);
+        } else {
+                div = (pdr0 >> 12) & 0x7;
+                return get_rate_ahb(NULL) / (div + 1);
+        }
+}
+
+static unsigned long get_rate_hsp(struct clk *clk)
+{
+        unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+        unsigned long fref = get_rate_mpll();
+
+        if (fref > 400 * 1000 * 1000) {
+                switch (hsp_podf) {
+                case 0:
+                        return fref >> 2;
+                case 1:
+                        return fref >> 3;
+                case 2:
+                        return fref / 3;
+                }
+        } else {
+                switch (hsp_podf) {
+                case 0:
+                case 2:
+                        return fref / 3;
+                case 1:
+                        return fref / 6;
+                }
+        }
+
+        return 0;
+}
+
+static int clk_cgr_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 3 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void clk_cgr_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = CCM_BASE + er,        \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .set_rate       = sr,                   \
+                .enable         = clk_cgr_enable,       \
+                .disable        = clk_cgr_disable,      \
+        }
+
+DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
+DEFINE_CLOCK(ata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
+/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
+DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
+DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
+DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
+DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg, NULL);
+DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
+DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
+
+DEFINE_CLOCK(fec_clk,    0, CCM_CGR1,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(gpio1_clk,  0, CCM_CGR1,  2, NULL, NULL);
+DEFINE_CLOCK(gpio2_clk,  1, CCM_CGR1,  4, NULL, NULL);
+DEFINE_CLOCK(gpio3_clk,  2, CCM_CGR1,  6, NULL, NULL);
+DEFINE_CLOCK(gpt_clk,    0, CCM_CGR1,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_hsp, NULL);
+DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
+DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
+DEFINE_CLOCK(owire_clk,  0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(pwm_clk,    0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(rngc_clk,   0, CCM_CGR1, 30, get_rate_ipg, NULL);
+
+DEFINE_CLOCK(rtc_clk,    0, CCM_CGR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(rtic_clk,   0, CCM_CGR2,  2, get_rate_ahb, NULL);
+DEFINE_CLOCK(scc_clk,    0, CCM_CGR2,  4, get_rate_ipg, NULL);
+DEFINE_CLOCK(sdma_clk,   0, CCM_CGR2,  6, NULL, NULL);
+DEFINE_CLOCK(spba_clk,   0, CCM_CGR2,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(spdif_clk,  0, CCM_CGR2, 10, NULL, NULL);
+DEFINE_CLOCK(ssi1_clk,   0, CCM_CGR2, 12, get_rate_ssi, NULL);
+DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
+DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
+DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
+DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
+
+DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
+DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
+DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
+
+DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);
+
+static int clk_dummy_enable(struct clk *clk)
+{
+        return 0;
+}
+
+static void clk_dummy_disable(struct clk *clk)
+{
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        unsigned long div1;
+
+        div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
+
+        return get_rate_ahb(NULL) / div1;
+}
+
+/* NAND Controller: It seems it can't be disabled */
+static struct clk nfc_clk = {
+        .id             = 0,
+        .enable_reg     = 0,
+        .enable_shift   = 0,
+        .get_rate       = get_rate_nfc,
+        .set_rate       = NULL, /* set_rate_nfc, */
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable
+};
+
+#define _REGISTER_CLOCK(d, n, c)        \
+        {                               \
+                .dev_id = d,            \
+                .con_id = n,            \
+                .clk = &c,              \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
+        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK(NULL, "ect", ect_clk)
+        _REGISTER_CLOCK(NULL, "edio", edio_clk)
+        _REGISTER_CLOCK(NULL, "emi", emi_clk)
+        _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
+        _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
+        _REGISTER_CLOCK(NULL, "esai", esai_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx35.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx35.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx35.2", NULL, esdhc3_clk)
+        /* i.mx35 has the i.mx27 type fec */
+        _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
+        _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
+        _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
+        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
+        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
+        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
+        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+        _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+        _REGISTER_CLOCK(NULL, "scc", scc_clk)
+        _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+        _REGISTER_CLOCK(NULL, "spba", spba_clk)
+        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        /* i.mx35 has the i.mx21 type uart */
+        _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK(NULL, "max", max_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+        _REGISTER_CLOCK(NULL, "csi", csi_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
+        _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+};
+
+int __init mx35_clocks_init()
+{
+        unsigned int cgr2 = 3 << 26, cgr3 = 0;
+
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+        cgr2 |= 3 << 16;
+#endif
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        /* Turn off all clocks except the ones we need to survive, namely:
+         * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
+         */
+        __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
+        __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
+                        CCM_BASE + CCM_CGR1);
+
+        /*
+         * Check if we came up in internal boot mode. If yes, we need some
+         * extra clocks turned on, otherwise the MX35 boot ROM code will
+         * hang after a watchdog reset.
+         */
+        if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
+                /* Additionally turn on UART1, SCC, and IIM clocks */
+                cgr2 |= 3 << 16 | 3 << 4;
+                cgr3 |= 3 << 2;
+        }
+
+        __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
+        __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
+
+        clk_enable(&iim_clk);
+        mx35_read_cpu_rev();
+
+#ifdef CONFIG_MXC_USE_EPIT
+        epit_timer_init(&epit1_clk,
+                        MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+#else
+        mxc_timer_init(&gpt_clk,
+                        MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
+#endif
+
+        return 0;
+}
diff --git a/arch/arm/mach-imx/crmregs-imx31.h b/arch/arm/mach-imx/crmregs-imx31.h
new file mode 100644
index 00000000000..37a8a07beda
--- /dev/null
+++ b/arch/arm/mach-imx/crmregs-imx31.h
@@ -0,0 +1,248 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+
+#define CKIH_CLK_FREQ           26000000
+#define CKIH_CLK_FREQ_27MHZ     27000000
+#define CKIL_CLK_FREQ           32768
+
+#define MXC_CCM_BASE            MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
+
+/* Register addresses */
+#define MXC_CCM_CCMR            (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_PDR0            (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_PDR1            (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_RCSR            (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_MPCTL           (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_UPCTL           (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_SRPCTL          (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_COSR            (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CGR0            (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CGR1            (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CGR2            (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_WIMR            (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_LDC             (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_DCVR0           (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_DCVR1           (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_DCVR2           (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_DCVR3           (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_LTR0            (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_LTR1            (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_LTR2            (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_LTR3            (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_LTBR0           (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_LTBR1           (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_PMCR0           (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_PMCR1           (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_PDR2            (MXC_CCM_BASE + 0x64)
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_WBEN                       (1 << 27)
+#define MXC_CCM_CCMR_CSCS                       (1 << 25)
+#define MXC_CCM_CCMR_PERCS                      (1 << 24)
+#define MXC_CCM_CCMR_SSI1S_OFFSET               18
+#define MXC_CCM_CCMR_SSI1S_MASK                 (0x3 << 18)
+#define MXC_CCM_CCMR_SSI2S_OFFSET               21
+#define MXC_CCM_CCMR_SSI2S_MASK                 (0x3 << 21)
+#define MXC_CCM_CCMR_LPM_OFFSET                 14
+#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_FIRS_OFFSET                11
+#define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
+#define MXC_CCM_CCMR_UPE                        (1 << 9)
+#define MXC_CCM_CCMR_SPE                        (1 << 8)
+#define MXC_CCM_CCMR_MDS                        (1 << 7)
+#define MXC_CCM_CCMR_SBYCS                      (1 << 4)
+#define MXC_CCM_CCMR_MPE                        (1 << 3)
+#define MXC_CCM_CCMR_PRCS_OFFSET                1
+#define MXC_CCM_CCMR_PRCS_MASK                  (0x3 << 1)
+
+#define MXC_CCM_PDR0_CSI_PODF_OFFSET            26
+#define MXC_CCM_PDR0_CSI_PODF_MASK              (0x3F << 26)
+#define MXC_CCM_PDR0_CSI_PRDF_OFFSET            23
+#define MXC_CCM_PDR0_CSI_PRDF_MASK              (0x7 << 23)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET            16
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x1F << 16)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET            11
+#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x7 << 11)
+#define MXC_CCM_PDR0_NFC_PODF_OFFSET            8
+#define MXC_CCM_PDR0_NFC_PODF_MASK              (0x7 << 8)
+#define MXC_CCM_PDR0_IPG_PODF_OFFSET            6
+#define MXC_CCM_PDR0_IPG_PODF_MASK              (0x3 << 6)
+#define MXC_CCM_PDR0_MAX_PODF_OFFSET            3
+#define MXC_CCM_PDR0_MAX_PODF_MASK              (0x7 << 3)
+#define MXC_CCM_PDR0_MCU_PODF_OFFSET            0
+#define MXC_CCM_PDR0_MCU_PODF_MASK              0x7
+
+#define MXC_CCM_PDR1_USB_PRDF_OFFSET            30
+#define MXC_CCM_PDR1_USB_PRDF_MASK              (0x3 << 30)
+#define MXC_CCM_PDR1_USB_PODF_OFFSET            27
+#define MXC_CCM_PDR1_USB_PODF_MASK              (0x7 << 27)
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET       24
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK         (0x7 << 24)
+#define MXC_CCM_PDR1_FIRI_PODF_OFFSET           18
+#define MXC_CCM_PDR1_FIRI_PODF_MASK             (0x3F << 18)
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET       15
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK         (0x7 << 15)
+#define MXC_CCM_PDR1_SSI2_PODF_OFFSET           9
+#define MXC_CCM_PDR1_SSI2_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET       6
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK         (0x7 << 6)
+#define MXC_CCM_PDR1_SSI1_PODF_OFFSET           0
+#define MXC_CCM_PDR1_SSI1_PODF_MASK             0x3F
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_NF16B                      0x80000000
+
+/*
+ * LTR0 register offsets
+ */
+#define MXC_CCM_LTR0_DIV3CK_OFFSET              1
+#define MXC_CCM_LTR0_DIV3CK_MASK                (0x3 << 1)
+#define MXC_CCM_LTR0_DNTHR_OFFSET               16
+#define MXC_CCM_LTR0_DNTHR_MASK                 (0x3F << 16)
+#define MXC_CCM_LTR0_UPTHR_OFFSET               22
+#define MXC_CCM_LTR0_UPTHR_MASK                 (0x3F << 22)
+
+/*
+ * LTR1 register offsets
+ */
+#define MXC_CCM_LTR1_PNCTHR_OFFSET              0
+#define MXC_CCM_LTR1_PNCTHR_MASK                0x3F
+#define MXC_CCM_LTR1_UPCNT_OFFSET               6
+#define MXC_CCM_LTR1_UPCNT_MASK                 (0xFF << 6)
+#define MXC_CCM_LTR1_DNCNT_OFFSET               14
+#define MXC_CCM_LTR1_DNCNT_MASK                 (0xFF << 14)
+#define MXC_CCM_LTR1_LTBRSR_MASK                0x400000
+#define MXC_CCM_LTR1_LTBRSR_OFFSET              22
+#define MXC_CCM_LTR1_LTBRSR                     0x400000
+#define MXC_CCM_LTR1_LTBRSH                     0x800000
+
+/*
+ * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
+ */
+#define MXC_CCM_LTR2_WSW_OFFSET(x)              (11 + (x) * 3)
+#define MXC_CCM_LTR2_WSW_MASK(x)                (0x7 << \
+                                        MXC_CCM_LTR2_WSW_OFFSET((x)))
+#define MXC_CCM_LTR2_EMAC_OFFSET                0
+#define MXC_CCM_LTR2_EMAC_MASK                  0x1FF
+
+/*
+ * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
+ */
+#define MXC_CCM_LTR3_WSW_OFFSET(x)              (5 + (x) * 3)
+#define MXC_CCM_LTR3_WSW_MASK(x)                (0x7 << \
+                                        MXC_CCM_LTR3_WSW_OFFSET((x)))
+
+#define MXC_CCM_PMCR0_DFSUP1                    0x80000000
+#define MXC_CCM_PMCR0_DFSUP1_SPLL               (0 << 31)
+#define MXC_CCM_PMCR0_DFSUP1_MPLL               (1 << 31)
+#define MXC_CCM_PMCR0_DFSUP0                    0x40000000
+#define MXC_CCM_PMCR0_DFSUP0_PLL                (0 << 30)
+#define MXC_CCM_PMCR0_DFSUP0_PDR                (1 << 30)
+#define MXC_CCM_PMCR0_DFSUP_MASK                (0x3 << 30)
+
+#define DVSUP_TURBO                             0
+#define DVSUP_HIGH                              1
+#define DVSUP_MEDIUM                            2
+#define DVSUP_LOW                               3
+#define MXC_CCM_PMCR0_DVSUP_TURBO               (DVSUP_TURBO << 28)
+#define MXC_CCM_PMCR0_DVSUP_HIGH                (DVSUP_HIGH << 28)
+#define MXC_CCM_PMCR0_DVSUP_MEDIUM              (DVSUP_MEDIUM << 28)
+#define MXC_CCM_PMCR0_DVSUP_LOW                 (DVSUP_LOW << 28)
+#define MXC_CCM_PMCR0_DVSUP_OFFSET              28
+#define MXC_CCM_PMCR0_DVSUP_MASK                (0x3 << 28)
+#define MXC_CCM_PMCR0_UDSC                      0x08000000
+#define MXC_CCM_PMCR0_UDSC_MASK                 (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_UP                   (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_DOWN                 (0 << 27)
+
+#define MXC_CCM_PMCR0_VSCNT_1                   (0x0 << 24)
+#define MXC_CCM_PMCR0_VSCNT_2                   (0x1 << 24)
+#define MXC_CCM_PMCR0_VSCNT_3                   (0x2 << 24)
+#define MXC_CCM_PMCR0_VSCNT_4                   (0x3 << 24)
+#define MXC_CCM_PMCR0_VSCNT_5                   (0x4 << 24)
+#define MXC_CCM_PMCR0_VSCNT_6                   (0x5 << 24)
+#define MXC_CCM_PMCR0_VSCNT_7                   (0x6 << 24)
+#define MXC_CCM_PMCR0_VSCNT_8                   (0x7 << 24)
+#define MXC_CCM_PMCR0_VSCNT_OFFSET              24
+#define MXC_CCM_PMCR0_VSCNT_MASK                (0x7 << 24)
+#define MXC_CCM_PMCR0_DVFEV                     0x00800000
+#define MXC_CCM_PMCR0_DVFIS                     0x00400000
+#define MXC_CCM_PMCR0_LBMI                      0x00200000
+#define MXC_CCM_PMCR0_LBFL                      0x00100000
+#define MXC_CCM_PMCR0_LBCF_4                    (0x0 << 18)
+#define MXC_CCM_PMCR0_LBCF_8                    (0x1 << 18)
+#define MXC_CCM_PMCR0_LBCF_12                   (0x2 << 18)
+#define MXC_CCM_PMCR0_LBCF_16                   (0x3 << 18)
+#define MXC_CCM_PMCR0_LBCF_OFFSET               18
+#define MXC_CCM_PMCR0_LBCF_MASK                 (0x3 << 18)
+#define MXC_CCM_PMCR0_PTVIS                     0x00020000
+#define MXC_CCM_PMCR0_UPDTEN                    0x00010000
+#define MXC_CCM_PMCR0_UPDTEN_MASK               (0x1 << 16)
+#define MXC_CCM_PMCR0_FSVAIM                    0x00008000
+#define MXC_CCM_PMCR0_FSVAI_OFFSET              13
+#define MXC_CCM_PMCR0_FSVAI_MASK                (0x3 << 13)
+#define MXC_CCM_PMCR0_DPVCR                     0x00001000
+#define MXC_CCM_PMCR0_DPVV                      0x00000800
+#define MXC_CCM_PMCR0_WFIM                      0x00000400
+#define MXC_CCM_PMCR0_DRCE3                     0x00000200
+#define MXC_CCM_PMCR0_DRCE2                     0x00000100
+#define MXC_CCM_PMCR0_DRCE1                     0x00000080
+#define MXC_CCM_PMCR0_DRCE0                     0x00000040
+#define MXC_CCM_PMCR0_DCR                       0x00000020
+#define MXC_CCM_PMCR0_DVFEN                     0x00000010
+#define MXC_CCM_PMCR0_PTVAIM                    0x00000008
+#define MXC_CCM_PMCR0_PTVAI_OFFSET              1
+#define MXC_CCM_PMCR0_PTVAI_MASK                (0x3 << 1)
+#define MXC_CCM_PMCR0_DPTEN                     0x00000001
+
+#define MXC_CCM_PMCR1_DVGP_OFFSET               0
+#define MXC_CCM_PMCR1_DVGP_MASK                 (0xF)
+
+#define MXC_CCM_PMCR1_PLLRDIS                      (0x1 << 7)
+#define MXC_CCM_PMCR1_EMIRQ_EN                      (0x1 << 8)
+
+#define MXC_CCM_DCVR_ULV_MASK                   (0x3FF << 22)
+#define MXC_CCM_DCVR_ULV_OFFSET                 22
+#define MXC_CCM_DCVR_LLV_MASK                   (0x3FF << 12)
+#define MXC_CCM_DCVR_LLV_OFFSET                 12
+#define MXC_CCM_DCVR_ELV_MASK                   (0x3FF << 2)
+#define MXC_CCM_DCVR_ELV_OFFSET                 2
+
+#define MXC_CCM_PDR2_MST2_PDF_MASK              (0x3F << 7)
+#define MXC_CCM_PDR2_MST2_PDF_OFFSET            7
+#define MXC_CCM_PDR2_MST1_PDF_MASK              0x3F
+#define MXC_CCM_PDR2_MST1_PDF_OFFSET            0
+
+#define MXC_CCM_COSR_CLKOSEL_MASK               0x0F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET             0
+#define MXC_CCM_COSR_CLKOUTDIV_MASK             (0x07 << 6)
+#define MXC_CCM_COSR_CLKOUTDIV_OFFSET           6
+#define MXC_CCM_COSR_CLKOEN                     (1 << 9)
+
+/*
+ * PMCR0 register offsets
+ */
+#define MXC_CCM_PMCR0_LBFL_OFFSET   20
+#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
+#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
+
+#endif                          /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
new file mode 100644
index 00000000000..42afc29a7da
--- /dev/null
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -0,0 +1,846 @@
+/*
+ *  linux/arch/arm/plat-mxc/dma-v1.c
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/scatterlist.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/dma-v1.h>
+
+#define DMA_DCR     0x00                /* Control Register */
+#define DMA_DISR    0x04                /* Interrupt status Register */
+#define DMA_DIMR    0x08                /* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
+#define DMA_DRTOSR  0x10                /* Request timeout Register */
+#define DMA_DSESR   0x14                /* Transfer Error Status Register */
+#define DMA_DBOSR   0x18                /* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
+#define DMA_WSRA    0x40                /* W-Size Register A */
+#define DMA_XSRA    0x44                /* X-Size Register A */
+#define DMA_YSRA    0x48                /* Y-Size Register A */
+#define DMA_WSRB    0x4c                /* W-Size Register B */
+#define DMA_XSRB    0x50                /* X-Size Register B */
+#define DMA_YSRB    0x54                /* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * struct imx_dma_channel - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imx_dma_channel only as extension to it.
+ */
+
+struct imx_dma_channel {
+        const char *name;
+        void (*irq_handler) (int, void *);
+        void (*err_handler) (int, void *, int errcode);
+        void (*prog_handler) (int, void *, struct scatterlist *);
+        void *data;
+        unsigned int dma_mode;
+        struct scatterlist *sg;
+        unsigned int resbytes;
+        int dma_num;
+
+        int in_use;
+
+        u32 ccr_from_device;
+        u32 ccr_to_device;
+
+        struct timer_list watchdog;
+
+        int hw_chaining;
+};
+
+static void __iomem *imx_dmav1_baseaddr;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
+{
+        __raw_writel(val, imx_dmav1_baseaddr + offset);
+}
+
+static unsigned imx_dmav1_readl(unsigned offset)
+{
+        return __raw_readl(imx_dmav1_baseaddr + offset);
+}
+
+static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
+
+static struct clk *dma_clk;
+
+static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
+{
+        if (cpu_is_mx27())
+                return imxdma->hw_chaining;
+        else
+                return 0;
+}
+
+/*
+ * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long now;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return 0;
+        }
+
+        now = min(imxdma->resbytes, sg->length);
+        if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+                imxdma->resbytes -= now;
+
+        if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+                imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
+        else
+                imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
+
+        imx_dmav1_writel(now, DMA_CNTR(channel));
+
+        pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+                "size 0x%08x\n", channel,
+                 imx_dmav1_readl(DMA_DAR(channel)),
+                 imx_dmav1_readl(DMA_SAR(channel)),
+                 imx_dmav1_readl(DMA_CNTR(channel)));
+
+        return now;
+}
+
+/**
+ * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
+ * device transfer
+ *
+ * @channel: i.MX DMA channel number
+ * @dma_address: the DMA/physical memory address of the linear data block
+ *              to transfer
+ * @dma_length: length of the data block in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ *              Zero indicates success.
+ */
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+                     unsigned int dma_length, unsigned int dev_addr,
+                     unsigned int dmamode)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        imxdma->sg = NULL;
+        imxdma->dma_mode = dmamode;
+
+        if (!dma_address) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if (!dma_length) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+                pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+                        "dev_addr=0x%08x for read\n",
+                        channel, __func__, (unsigned int)dma_address,
+                        dma_length, dev_addr);
+
+                imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+                imx_dmav1_writel(dma_address, DMA_DAR(channel));
+                imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
+        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+                pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+                        "dev_addr=0x%08x for write\n",
+                        channel, __func__, (unsigned int)dma_address,
+                        dma_length, dev_addr);
+
+                imx_dmav1_writel(dma_address, DMA_SAR(channel));
+                imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+                imx_dmav1_writel(imxdma->ccr_to_device,
+                                DMA_CCR(channel));
+        } else {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_single);
+
+/**
+ * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
+ * @channel: i.MX DMA channel number
+ * @sg: pointer to the scatter-gather list/vector
+ * @sgcount: scatter-gather list hungs count
+ * @dma_length: total length of the transfer request in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * The function sets up DMA channel state and registers to be ready for
+ * transfer specified by provided parameters. The scatter-gather emulation
+ * is set up according to the parameters.
+ *
+ * The full preparation of the transfer requires setup of more register
+ * by the caller before imx_dma_enable() can be called.
+ *
+ * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
+ *
+ * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
+ *
+ * %CCR(channel) has to specify transfer parameters, the next settings is
+ * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
+ * specified
+ *
+ * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
+ *
+ * The typical setup for %DMA_MODE_WRITE is specified by next options
+ * combination
+ *
+ * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
+ *
+ * Be careful here and do not mistakenly mix source and target device
+ * port sizes constants, they are really different:
+ * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
+ * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ * Zero indicates success.
+ */
+int
+imx_dma_setup_sg(int channel,
+                 struct scatterlist *sg, unsigned int sgcount,
+                 unsigned int dma_length, unsigned int dev_addr,
+                 unsigned int dmamode)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        if (imxdma->in_use)
+                return -EBUSY;
+
+        imxdma->sg = sg;
+        imxdma->dma_mode = dmamode;
+        imxdma->resbytes = dma_length;
+
+        if (!sg || !sgcount) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if (!sg->length) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+                pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+                        "dev_addr=0x%08x for read\n",
+                        channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+                imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+                imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
+        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+                pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+                        "dev_addr=0x%08x for write\n",
+                        channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+                imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+                imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
+        } else {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        imx_dma_sg_next(channel, sg);
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_sg);
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+        unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        u32 dreq = 0;
+
+        imxdma->hw_chaining = 0;
+
+        if (hw_chaining) {
+                imxdma->hw_chaining = 1;
+                if (!imx_dma_hw_chain(imxdma))
+                        return -EINVAL;
+        }
+
+        if (dmareq)
+                dreq = CCR_REN;
+
+        imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
+        imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+        imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_config_channel);
+
+void imx_dma_config_burstlen(int channel, unsigned int burstlen)
+{
+        imx_dmav1_writel(burstlen, DMA_BLR(channel));
+}
+EXPORT_SYMBOL(imx_dma_config_burstlen);
+
+/**
+ * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @irq_handler: the pointer to the function called if the transfer
+ *              ends successfully
+ * @err_handler: the pointer to the function called if the premature
+ *              end caused by error occurs
+ * @data: user specified value to be passed to the handlers
+ */
+int
+imx_dma_setup_handlers(int channel,
+                       void (*irq_handler) (int, void *),
+                       void (*err_handler) (int, void *, int),
+                       void *data)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        imx_dmav1_writel(1 << channel, DMA_DISR);
+        imxdma->irq_handler = irq_handler;
+        imxdma->err_handler = err_handler;
+        imxdma->data = data;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_handlers);
+
+/**
+ * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @prog_handler: the pointer to the function called if the transfer progresses
+ */
+int
+imx_dma_setup_progression_handler(int channel,
+                        void (*prog_handler) (int, void*, struct scatterlist*))
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        imxdma->prog_handler = prog_handler;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_progression_handler);
+
+/**
+ * imx_dma_enable - function to start i.MX DMA channel operation
+ * @channel: i.MX DMA channel number
+ *
+ * The channel has to be allocated by driver through imx_dma_request()
+ * or imx_dma_request_by_prio() function.
+ * The transfer parameters has to be set to the channel registers through
+ * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
+ * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
+ * be set prior this function call by the channel user.
+ */
+void imx_dma_enable(int channel)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return;
+        }
+
+        if (imxdma->in_use)
+                return;
+
+        local_irq_save(flags);
+
+        imx_dmav1_writel(1 << channel, DMA_DISR);
+        imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+        imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+                CCR_ACRPT, DMA_CCR(channel));
+
+        if ((cpu_is_mx21() || cpu_is_mx27()) &&
+                        imxdma->sg && imx_dma_hw_chain(imxdma)) {
+                imxdma->sg = sg_next(imxdma->sg);
+                if (imxdma->sg) {
+                        u32 tmp;
+                        imx_dma_sg_next(channel, imxdma->sg);
+                        tmp = imx_dmav1_readl(DMA_CCR(channel));
+                        imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+                                DMA_CCR(channel));
+                }
+        }
+        imxdma->in_use = 1;
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_enable);
+
+/**
+ * imx_dma_disable - stop, finish i.MX DMA channel operatin
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_disable(int channel)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+        if (imx_dma_hw_chain(imxdma))
+                del_timer(&imxdma->watchdog);
+
+        local_irq_save(flags);
+        imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+        imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+                        DMA_CCR(channel));
+        imx_dmav1_writel(1 << channel, DMA_DISR);
+        imxdma->in_use = 0;
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_disable);
+
+static void imx_dma_watchdog(unsigned long chno)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+        imx_dmav1_writel(0, DMA_CCR(chno));
+        imxdma->in_use = 0;
+        imxdma->sg = NULL;
+
+        if (imxdma->err_handler)
+                imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
+}
+
+static irqreturn_t dma_err_handler(int irq, void *dev_id)
+{
+        int i, disr;
+        struct imx_dma_channel *imxdma;
+        unsigned int err_mask;
+        int errcode;
+
+        disr = imx_dmav1_readl(DMA_DISR);
+
+        err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+                   imx_dmav1_readl(DMA_DRTOSR) |
+                   imx_dmav1_readl(DMA_DSESR)  |
+                   imx_dmav1_readl(DMA_DBOSR);
+
+        if (!err_mask)
+                return IRQ_HANDLED;
+
+        imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                if (!(err_mask & (1 << i)))
+                        continue;
+                imxdma = &imx_dma_channels[i];
+                errcode = 0;
+
+                if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+                        imx_dmav1_writel(1 << i, DMA_DBTOSR);
+                        errcode |= IMX_DMA_ERR_BURST;
+                }
+                if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+                        imx_dmav1_writel(1 << i, DMA_DRTOSR);
+                        errcode |= IMX_DMA_ERR_REQUEST;
+                }
+                if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+                        imx_dmav1_writel(1 << i, DMA_DSESR);
+                        errcode |= IMX_DMA_ERR_TRANSFER;
+                }
+                if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+                        imx_dmav1_writel(1 << i, DMA_DBOSR);
+                        errcode |= IMX_DMA_ERR_BUFFER;
+                }
+                if (imxdma->name && imxdma->err_handler) {
+                        imxdma->err_handler(i, imxdma->data, errcode);
+                        continue;
+                }
+
+                imx_dma_channels[i].sg = NULL;
+
+                printk(KERN_WARNING
+                       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
+                       i, imxdma->name,
+                       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+                       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+                       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+                       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+        }
+        return IRQ_HANDLED;
+}
+
+static void dma_irq_handle_channel(int chno)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+        if (!imxdma->name) {
+                /*
+                 * IRQ for an unregistered DMA channel:
+                 * let's clear the interrupts and disable it.
+                 */
+                printk(KERN_WARNING
+                       "spurious IRQ for DMA channel %d\n", chno);
+                return;
+        }
+
+        if (imxdma->sg) {
+                u32 tmp;
+                struct scatterlist *current_sg = imxdma->sg;
+                imxdma->sg = sg_next(imxdma->sg);
+
+                if (imxdma->sg) {
+                        imx_dma_sg_next(chno, imxdma->sg);
+
+                        tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+                        if (imx_dma_hw_chain(imxdma)) {
+                                /* FIXME: The timeout should probably be
+                                 * configurable
+                                 */
+                                mod_timer(&imxdma->watchdog,
+                                        jiffies + msecs_to_jiffies(500));
+
+                                tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+                                imx_dmav1_writel(tmp, DMA_CCR(chno));
+                        } else {
+                                imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+                                tmp |= CCR_CEN;
+                        }
+
+                        imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+                        if (imxdma->prog_handler)
+                                imxdma->prog_handler(chno, imxdma->data,
+                                                current_sg);
+
+                        return;
+                }
+
+                if (imx_dma_hw_chain(imxdma)) {
+                        del_timer(&imxdma->watchdog);
+                        return;
+                }
+        }
+
+        imx_dmav1_writel(0, DMA_CCR(chno));
+        imxdma->in_use = 0;
+        if (imxdma->irq_handler)
+                imxdma->irq_handler(chno, imxdma->data);
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+        int i, disr;
+
+        if (cpu_is_mx21() || cpu_is_mx27())
+                dma_err_handler(irq, dev_id);
+
+        disr = imx_dmav1_readl(DMA_DISR);
+
+        pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+                     disr);
+
+        imx_dmav1_writel(disr, DMA_DISR);
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                if (disr & (1 << i))
+                        dma_irq_handle_channel(i);
+        }
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * imx_dma_request - request/allocate specified channel number
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ */
+int imx_dma_request(int channel, const char *name)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+        int ret = 0;
+
+        /* basic sanity checks */
+        if (!name)
+                return -EINVAL;
+
+        if (channel >= IMX_DMA_CHANNELS) {
+                printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
+                       __func__, channel);
+                return -EINVAL;
+        }
+
+        local_irq_save(flags);
+        if (imxdma->name) {
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+        memset(imxdma, 0, sizeof(*imxdma));
+        imxdma->name = name;
+        local_irq_restore(flags); /* request_irq() can block */
+
+        if (cpu_is_mx21() || cpu_is_mx27()) {
+                ret = request_irq(MX2x_INT_DMACH0 + channel,
+                                dma_irq_handler, 0, "DMA", NULL);
+                if (ret) {
+                        imxdma->name = NULL;
+                        pr_crit("Can't register IRQ %d for DMA channel %d\n",
+                                        MX2x_INT_DMACH0 + channel, channel);
+                        return ret;
+                }
+                init_timer(&imxdma->watchdog);
+                imxdma->watchdog.function = &imx_dma_watchdog;
+                imxdma->watchdog.data = channel;
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(imx_dma_request);
+
+/**
+ * imx_dma_free - release previously acquired channel
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_free(int channel)
+{
+        unsigned long flags;
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT
+                       "%s: trying to free free channel %d\n",
+                       __func__, channel);
+                return;
+        }
+
+        local_irq_save(flags);
+        /* Disable interrupts */
+        imx_dma_disable(channel);
+        imxdma->name = NULL;
+
+        if (cpu_is_mx21() || cpu_is_mx27())
+                free_irq(MX2x_INT_DMACH0 + channel, NULL);
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_free);
+
+/**
+ * imx_dma_request_by_prio - find and request some of free channels best
+ * suiting requested priority
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ *
+ * This function tries to find a free channel in the specified priority group
+ * if the priority cannot be achieved it tries to look for free channel
+ * in the higher and then even lower priority groups.
+ *
+ * Return value: If there is no free channel to allocate, -%ENODEV is returned.
+ *               On successful allocation channel is returned.
+ */
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
+{
+        int i;
+        int best;
+
+        switch (prio) {
+        case (DMA_PRIO_HIGH):
+                best = 8;
+                break;
+        case (DMA_PRIO_MEDIUM):
+                best = 4;
+                break;
+        case (DMA_PRIO_LOW):
+        default:
+                best = 0;
+                break;
+        }
+
+        for (i = best; i < IMX_DMA_CHANNELS; i++)
+                if (!imx_dma_request(i, name))
+                        return i;
+
+        for (i = best - 1; i >= 0; i--)
+                if (!imx_dma_request(i, name))
+                        return i;
+
+        printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
+
+        return -ENODEV;
+}
+EXPORT_SYMBOL(imx_dma_request_by_prio);
+
+static int __init imx_dma_init(void)
+{
+        int ret = 0;
+        int i;
+
+        if (cpu_is_mx1())
+                imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+        else if (cpu_is_mx21())
+                imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+        else if (cpu_is_mx27())
+                imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+        else
+                return 0;
+
+        dma_clk = clk_get(NULL, "dma");
+        if (IS_ERR(dma_clk))
+                return PTR_ERR(dma_clk);
+        clk_enable(dma_clk);
+
+        /* reset DMA module */
+        imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+        if (cpu_is_mx1()) {
+                ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
+                if (ret) {
+                        pr_crit("Wow!  Can't register IRQ for DMA\n");
+                        return ret;
+                }
+
+                ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
+                if (ret) {
+                        pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
+                        free_irq(MX1_DMA_INT, NULL);
+                        return ret;
+                }
+        }
+
+        /* enable DMA module */
+        imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+        /* clear all interrupts */
+        imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+        /* disable interrupts */
+        imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                imx_dma_channels[i].sg = NULL;
+                imx_dma_channels[i].dma_num = i;
+        }
+
+        return ret;
+}
+
+arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
new file mode 100644
index 00000000000..df5f522da6b
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,10 @@
+#ifndef __MACH_DMA_MX1_MX2_H__
+#define __MACH_DMA_MX1_MX2_H__
+/*
+ * Don't use this header in new code, it will go away when all users are
+ * converted to mach/dma-v1.h
+ */
+
+#include <mach/dma-v1.h>
+
+#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
new file mode 100644
index 00000000000..ac6fd713828
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-v1.h
@@ -0,0 +1,103 @@
+/*
+ *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_DMA_V1_H__
+#define __MACH_DMA_V1_H__
+
+#define imx_has_dma_v1()        (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
+
+#include <mach/dma.h>
+
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_MODE_READ           0
+#define DMA_MODE_WRITE          1
+#define DMA_MODE_MASK           1
+
+#define MX1_DMA_REG(offset)     MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
+
+/* DMA Interrupt Mask Register */
+#define MX1_DMA_DIMR            MX1_DMA_REG(0x08)
+
+/* Channel Control Register */
+#define MX1_DMA_CCR(x)          MX1_DMA_REG(0x8c + ((x) << 6))
+
+#define IMX_DMA_MEMSIZE_32      (0 << 4)
+#define IMX_DMA_MEMSIZE_8       (1 << 4)
+#define IMX_DMA_MEMSIZE_16      (2 << 4)
+#define IMX_DMA_TYPE_LINEAR     (0 << 10)
+#define IMX_DMA_TYPE_2D         (1 << 10)
+#define IMX_DMA_TYPE_FIFO       (2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+        unsigned int config_mem, unsigned int dmareq, int hw_chaining);
+
+void
+imx_dma_config_burstlen(int channel, unsigned int burstlen);
+
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+                unsigned int dma_length, unsigned int dev_addr,
+                unsigned int dmamode);
+
+
+/*
+ * Use this flag as the dma_length argument to imx_dma_setup_sg()
+ * to create an endless running dma loop. The end of the scatterlist
+ * must be linked to the beginning for this to work.
+ */
+#define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
+
+int
+imx_dma_setup_sg(int channel, struct scatterlist *sg,
+                unsigned int sgcount, unsigned int dma_length,
+                unsigned int dev_addr, unsigned int dmamode);
+
+int
+imx_dma_setup_handlers(int channel,
+                void (*irq_handler) (int, void *),
+                void (*err_handler) (int, void *, int), void *data);
+
+int
+imx_dma_setup_progression_handler(int channel,
+                void (*prog_handler) (int, void*, struct scatterlist*));
+
+void imx_dma_enable(int channel);
+
+void imx_dma_disable(int channel);
+
+int imx_dma_request(int channel, const char *name);
+
+void imx_dma_free(int channel);
+
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
+
+#endif  /* __MACH_DMA_V1_H__ */
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
new file mode 100644
index 00000000000..b7c55e7db00
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -0,0 +1,91 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/devices-common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/irqs.h>
+
+static struct map_desc mx31_io_desc[] __initdata = {
+        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx31_map_io(void)
+{
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+
+void __init imx31_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+}
+
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+}
+
+static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
+        .per_2_per_addr = 1677,
+};
+
+static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 423,
+        .ap_2_bp_addr = 829,
+        .bp_2_ap_addr = 1029,
+};
+
+static struct sdma_platform_data imx31_sdma_pdata __initdata = {
+        .fw_name = "sdma-imx31-to2.bin",
+        .script_addrs = &imx31_to2_sdma_script,
+};
+
+void __init imx31_soc_init(void)
+{
+        int to_version = mx31_revision() >> 4;
+
+        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
+
+        if (to_version == 1) {
+                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
+                        strlen(imx31_sdma_pdata.fw_name));
+                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
+        }
+
+        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
new file mode 100644
index 00000000000..f49bac7a1ed
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -0,0 +1,109 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/common.h>
+#include <mach/devices-common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/irqs.h>
+
+static struct map_desc mx35_io_desc[] __initdata = {
+        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+void __init mx35_map_io(void)
+{
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+
+void __init imx35_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+}
+
+void __init mx35_init_irq(void)
+{
+        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+}
+
+static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .uartsh_2_mcu_addr = 1183,
+        .per_2_shp_addr = 1033,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1333,
+        .mcu_2_ata_addr = 1252,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1111,
+        .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1597,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1270,
+        .per_2_shp_addr = 1120,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1429,
+        .mcu_2_ata_addr = 1339,
+        .app_2_per_addr = 1531,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1198,
+        .shp_2_mcu_addr = 979,
+};
+
+static struct sdma_platform_data imx35_sdma_pdata __initdata = {
+        .fw_name = "sdma-imx35-to2.bin",
+        .script_addrs = &imx35_to2_sdma_script,
+};
+
+void __init imx35_soc_init(void)
+{
+        int to_version = mx35_revision() >> 4;
+
+        /* i.mx35 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+
+        if (to_version == 1) {
+                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
+                        strlen(imx35_sdma_pdata.fw_name));
+                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
+        }
+
+        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+}