Patched in Tegra support.

199 files changed, 844 insertions, 24646 deletions

diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c
deleted file mode 100644
index 13437735296..00000000000
--- a/arch/arm/mach-imx/3ds_debugboard.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/smsc911x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include "hardware.h"
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR(n)    (n + 0x0)
-/* External UART */
-#define UARTA_BASE_ADDR(n)      (n + 0x8000)
-#define UARTB_BASE_ADDR(n)      (n + 0x10000)
-
-#define BOARD_IO_ADDR(n)        (n + 0x20000)
-/* LED switchs */
-#define LED_SWITCH_REG          0x00
-/* buttons */
-#define SWITCH_BUTTONS_REG      0x08
-/* status, interrupt */
-#define INTR_STATUS_REG 0x10
-#define INTR_MASK_REG           0x38
-#define INTR_RESET_REG          0x20
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER1_REG       0x40
-#define MAGIC_NUMBER2_REG       0x48
-/* CPLD code version */
-#define CPLD_CODE_VER_REG       0x50
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER3_REG       0x58
-/* module reset register*/
-#define MODULE_RESET_REG        0x60
-/* CPU ID and Personality ID */
-#define MCU_BOARD_ID_REG        0x68
-
-#define MXC_MAX_EXP_IO_LINES    16
-
-/* interrupts like external uart , external ethernet etc*/
-#define EXPIO_INT_ENET          0
-#define EXPIO_INT_XUART_A       1
-#define EXPIO_INT_XUART_B       2
-#define EXPIO_INT_BUTTON_A      3
-#define EXPIO_INT_BUTTON_B      4
-
-static void __iomem *brd_io;
-static struct irq_domain *domain;
-
-static struct resource smsc911x_resources[] = {
-        {
-                .flags = IORESOURCE_MEM,
-        } , {
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
-        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
-};
-
-static struct platform_device smsc_lan9217_device = {
-        .name = "smsc911x",
-        .id = -1,
-        .dev = {
-                .platform_data = &smsc911x_config,
-        },
-        .num_resources = ARRAY_SIZE(smsc911x_resources),
-        .resource = smsc911x_resources,
-};
-
-static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
-{
-        u32 imr_val;
-        u32 int_valid;
-        u32 expio_irq;
-
-        /* irq = gpio irq number */
-        desc->irq_data.chip->irq_mask(&desc->irq_data);
-
-        imr_val = __raw_readw(brd_io + INTR_MASK_REG);
-        int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
-
-        expio_irq = 0;
-        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-                if ((int_valid & 1) == 0)
-                        continue;
-                generic_handle_irq(irq_find_mapping(domain, expio_irq));
-        }
-
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * Irq is an expio virtual irq number
- */
-static void expio_mask_irq(struct irq_data *d)
-{
-        u16 reg;
-        u32 expio = d->hwirq;
-
-        reg = __raw_readw(brd_io + INTR_MASK_REG);
-        reg |= (1 << expio);
-        __raw_writew(reg, brd_io + INTR_MASK_REG);
-}
-
-static void expio_ack_irq(struct irq_data *d)
-{
-        u32 expio = d->hwirq;
-
-        __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
-        __raw_writew(0, brd_io + INTR_RESET_REG);
-        expio_mask_irq(d);
-}
-
-static void expio_unmask_irq(struct irq_data *d)
-{
-        u16 reg;
-        u32 expio = d->hwirq;
-
-        reg = __raw_readw(brd_io + INTR_MASK_REG);
-        reg &= ~(1 << expio);
-        __raw_writew(reg, brd_io + INTR_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-        .irq_ack = expio_ack_irq,
-        .irq_mask = expio_mask_irq,
-        .irq_unmask = expio_unmask_irq,
-};
-
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-int __init mxc_expio_init(u32 base, u32 intr_gpio)
-{
-        u32 p_irq = gpio_to_irq(intr_gpio);
-        int irq_base;
-        int i;
-
-        brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
-        if (brd_io == NULL)
-                return -ENOMEM;
-
-        if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
-            (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
-            (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
-                pr_info("3-Stack Debug board not detected\n");
-                iounmap(brd_io);
-                brd_io = NULL;
-                return -ENODEV;
-        }
-
-        pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
-                readw(brd_io + CPLD_CODE_VER_REG));
-
-        /*
-         * Configure INT line as GPIO input
-         */
-        gpio_request(intr_gpio, "expio_pirq");
-        gpio_direction_input(intr_gpio);
-
-        /* disable the interrupt and clear the status */
-        __raw_writew(0, brd_io + INTR_MASK_REG);
-        __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
-        __raw_writew(0, brd_io + INTR_RESET_REG);
-        __raw_writew(0x1F, brd_io + INTR_MASK_REG);
-
-        irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
-        WARN_ON(irq_base < 0);
-
-        domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
-                                       &irq_domain_simple_ops, NULL);
-        WARN_ON(!domain);
-
-        for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
-                irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-        irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
-        irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
-
-        /* Register Lan device on the debugboard */
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
-        smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
-        smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
-        smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
-        platform_device_register(&smsc_lan9217_device);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/3ds_debugboard.h b/arch/arm/mach-imx/3ds_debugboard.h
deleted file mode 100644
index 9fd6cb3f8fa..00000000000
--- a/arch/arm/mach-imx/3ds_debugboard.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_3DS_DB_H__
-#define __ASM_ARCH_MXC_3DS_DB_H__
-
-extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
-
-#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3e628fd7a67..0519dd7f034 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,183 +1,65 @@
-config ARCH_MXC
-        bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_PATCH_PHYS_VIRT
-        select AUTO_ZRELADDR if !ZBOOT_ROM
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_IRQ_CHIP
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          Support for Freescale MXC/iMX-based family of processors
-
-menu "Freescale i.MX support"
-        depends on ARCH_MXC
-
-config MXC_IRQ_PRIOR
-        bool "Use IRQ priority"
-        help
-          Select this if you want to use prioritized IRQ handling.
-          This feature prevents higher priority ISR to be interrupted
-          by lower priority IRQ even IRQF_DISABLED flag is not set.
-          This may be useful in embedded applications, where are strong
-          requirements for timing.
-          Say N here, unless you have a specialized requirement.
-
-config MXC_TZIC
+config IMX_HAVE_DMA_V1
         bool
-
-config MXC_AVIC
-        bool
-
-config MXC_DEBUG_BOARD
-        bool "Enable MXC debug board(for 3-stack)"
-        help
-          The debug board is an integral part of the MXC 3-stack(PDK)
-          platforms, it can be attached or removed from the peripheral
-          board. On debug board, several debug devices(ethernet, UART,
-          buttons, LEDs and JTAG) are implemented. Between the MCU and
-          these devices, a CPLD is added as a bridge which performs
-          data/address de-multiplexing and decode, signal level shift,
-          interrupt control and various board functions.
-
-config HAVE_EPIT
-        bool
-
-config MXC_USE_EPIT
-        bool "Use EPIT instead of GPT"
-        depends on HAVE_EPIT
-        help
-          Use EPIT as the system timer on systems that have it. Normally you
-          don't have a reason to do so as the EPIT has the same features and
-          uses the same clocks as the GPT. Anyway, on some systems the GPT
-          may be in use for other purposes.
-
-config MXC_ULPI
-        bool
-
-config ARCH_HAS_RNGA
-        bool
-
-config IRAM_ALLOC
-        bool
-        select GENERIC_ALLOCATOR
-
-config HAVE_IMX_GPC
-        bool
-
-config HAVE_IMX_MMDC
-        bool
-
-config HAVE_IMX_SRC
-        def_bool y if SMP
-
-config IMX_HAVE_IOMUX_V1
-        bool
-
-config ARCH_MXC_IOMUX_V3
-        bool
-
-config ARCH_MX1
-        bool
-
-config MACH_MX21
-        bool
-
-config ARCH_MX25
-        bool
-
-config MACH_MX27
-        bool
-
-config ARCH_MX5
-        bool
-
-config ARCH_MX50
-        bool
-
-config ARCH_MX51
+#
+# ARCH_MX31 and ARCH_MX35 are left for compatibility
+# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
+# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
+# more sensible) names are used: SOC_IMX31 and SOC_IMX35
+config ARCH_MX31
         bool
 
-config ARCH_MX53
+config ARCH_MX35
         bool
 
 config SOC_IMX1
         bool
-        select ARCH_MX1
-        select COMMON_CLK
         select CPU_ARM920T
+        select IMX_HAVE_DMA_V1
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
 
 config SOC_IMX21
         bool
-        select COMMON_CLK
         select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
         select IMX_HAVE_IOMUX_V1
-        select MACH_MX21
         select MXC_AVIC
 
 config SOC_IMX25
         bool
-        select ARCH_MX25
-        select ARCH_MXC_IOMUX_V3
-        select COMMON_CLK
         select CPU_ARM926T
-        select HAVE_CAN_FLEXCAN if CAN
+        select ARCH_MXC_AUDMUX_V2
+        select ARCH_MXC_IOMUX_V3
         select MXC_AVIC
 
 config SOC_IMX27
         bool
-        select COMMON_CLK
         select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
         select IMX_HAVE_IOMUX_V1
-        select MACH_MX27
         select MXC_AVIC
 
 config SOC_IMX31
         bool
-        select COMMON_CLK
         select CPU_V6
         select IMX_HAVE_PLATFORM_MXC_RNGA
+        select ARCH_MXC_AUDMUX_V2
+        select ARCH_MX31
         select MXC_AVIC
-        select SMP_ON_UP if SMP
 
 config SOC_IMX35
         bool
+        select CPU_V6
         select ARCH_MXC_IOMUX_V3
-        select COMMON_CLK
-        select CPU_V6K
-        select HAVE_CAN_FLEXCAN if CAN
+        select ARCH_MXC_AUDMUX_V2
         select HAVE_EPIT
+        select ARCH_MX35
         select MXC_AVIC
-        select SMP_ON_UP if SMP
-
-config SOC_IMX5
-        bool
-        select ARCH_HAS_CPUFREQ
-        select ARCH_MX5
-        select ARCH_MXC_IOMUX_V3
-        select COMMON_CLK
-        select CPU_V7
-        select MXC_TZIC
 
-config SOC_IMX50
-        bool
-        select ARCH_MX50
-        select SOC_IMX5
 
-config  SOC_IMX51
-        bool
-        select ARCH_MX5
-        select ARCH_MX51
-        select PINCTRL
-        select PINCTRL_IMX51
-        select SOC_IMX5
-
-if ARCH_MULTI_V4T
+if ARCH_MX1
 
 comment "MX1 platforms:"
 config MACH_MXLADS
@@ -185,10 +67,10 @@ config MACH_MXLADS
 
 config ARCH_MX1ADS
         bool "MX1ADS platform"
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
         select MACH_MXLADS
         select SOC_IMX1
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Say Y here if you are using Motorola MX1ADS/MXLADS boards
 
@@ -200,51 +82,73 @@ config MACH_SCB9328
 
 config MACH_APF9328
         bool "APF9328"
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
         select SOC_IMX1
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Say Yes here if you are using the Armadeus APF9328 development board
 
 endif
 
-if ARCH_MULTI_V5
+if ARCH_MX2
+
+choice
+        prompt "CPUs:"
+        default MACH_MX21
+
+config MACH_MX21
+        bool "i.MX21 support"
+        help
+          This enables support for Freescale's MX2 based i.MX21 processor.
+
+config MACH_MX27
+        bool "i.MX27 support"
+        help
+          This enables support for Freescale's MX2 based i.MX27 processor.
+
+endchoice
+
+endif
+
+if MACH_MX21
 
 comment "MX21 platforms:"
 
 config MACH_MX21ADS
         bool "MX21ADS platform"
+        select SOC_IMX21
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select SOC_IMX21
         help
           Include support for MX21ADS platform. This includes specific
           configurations for the board and its peripherals.
 
+endif
+
+if ARCH_MX25
+
 comment "MX25 platforms:"
 
 config MACH_MX25_3DS
         bool "Support MX25PDK (3DS) Platform"
-        select IMX_HAVE_PLATFORM_FLEXCAN
+        select SOC_IMX25
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMXDI_RTC
-        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select SOC_IMX25
 
-config MACH_EUKREA_CPUIMX25SD
+config MACH_EUKREA_CPUIMX25
         bool "Support Eukrea CPUIMX25 Platform"
+        select SOC_IMX25
         select IMX_HAVE_PLATFORM_FLEXCAN
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMXDI_RTC
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
@@ -253,18 +157,16 @@ config MACH_EUKREA_CPUIMX25SD
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX25
 
 choice
         prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX25SD
+        depends on MACH_EUKREA_CPUIMX25
         default MACH_EUKREA_MBIMXSD25_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD25_BASEBOARD
         bool "Eukrea MBIMXSD development board"
         select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
         help
           This adds board specific devices that can be found on Eukrea's
@@ -272,30 +174,28 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
 
 endchoice
 
-config MACH_IMX25_DT
-        bool "Support i.MX25 platforms from device tree"
-        select SOC_IMX25
-        help
-          Include support for Freescale i.MX25 based platforms
-          using the device tree for discovery
+endif
+
+if MACH_MX27
 
 comment "MX27 platforms:"
 
 config MACH_MX27ADS
         bool "MX27ADS platform"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
-        select SOC_IMX27
         help
           Include support for MX27ADS platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCM038
         bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -304,7 +204,6 @@ config MACH_PCM038
         select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX27
         help
           Include support for phyCORE-i.MX27 (aka pcm038) platform. This
           includes specific configurations for the module and its peripherals.
@@ -326,6 +225,7 @@ endchoice
 
 config MACH_CPUIMX27
         bool "Eukrea CPUIMX27 module"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
@@ -334,7 +234,6 @@ config MACH_CPUIMX27
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX27
         help
           Include support for Eukrea CPUIMX27 platform. This includes
           specific configurations for the module and its peripherals.
@@ -376,36 +275,31 @@ endchoice
 
 config MACH_MX27_3DS
         bool "MX27PDK platform"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MX2_CAMERA
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX27
         help
           Include support for MX27PDK platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_IMX27_VISSTRIM_M10
         bool "Vista Silicon i.MX27 Visstrim_m10"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MX2_CAMERA
-        select IMX_HAVE_PLATFORM_MX2_EMMA
-        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
-        select LEDS_GPIO_REGISTER
-        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         help
           Include support for Visstrim_m10 platform and its different variants.
           This includes specific configurations for the board and its
@@ -413,15 +307,16 @@ config MACH_IMX27_VISSTRIM_M10
 
 config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_IMX_UART
         select SOC_IMX27
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_SSI
         help
           Include support for MX27 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_FB
@@ -434,52 +329,44 @@ config MACH_PCA100
         select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX27
         help
           Include support for phyCARD-s (aka pca100) platform. This
           includes specific configurations for the module and its peripherals.
 
 config MACH_MXT_TD60
         bool "Maxtrack i-MXT TD60"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select SOC_IMX27
         help
           Include support for i-MXT (aka td60) platform. This
           includes specific configurations for the module and its peripherals.
 
 config MACH_IMX27IPCAM
         bool "IMX27 IPCAM platform"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_UART
-        select SOC_IMX27
         help
           Include support for IMX27 IPCAM platform. This includes specific
           configurations for the board and its peripherals.
 
-config MACH_IMX27_DT
-        bool "Support i.MX27 platforms from device tree"
-        select SOC_IMX27
-        help
-          Include support for Freescale i.MX27 based platforms
-          using the device tree for discovery
-
 endif
 
-if ARCH_MULTI_V6
+if ARCH_MX3
 
 comment "MX31 platforms:"
 
 config MACH_MX31ADS
         bool "Support MX31ADS platforms"
-        default y
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
-        select SOC_IMX31
+        default y
         help
           Include support for MX31ADS platform. This includes specific
           configurations for the board and its peripherals.
@@ -497,19 +384,21 @@ config MACH_MX31ADS_WM1133_EV1
 
 config MACH_MX31LILLY
         bool "Support MX31 LILLY-1131 platforms (INCO startec)"
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX31
         help
           Include support for mx31 based LILLY1131 modules. This includes
           specific configurations for the board and its peripherals.
 
 config MACH_MX31LITE
         bool "Support MX31 LITEKIT (LogicPD)"
+        select SOC_IMX31
+        select MXC_ULPI if USB_ULPI
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -518,14 +407,13 @@ config MACH_MX31LITE
         select IMX_HAVE_PLATFORM_MXC_RTC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
-        select SOC_IMX31
         help
           Include support for MX31 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCM037
         bool "Support Phytec pcm037 (i.MX31) platforms"
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
@@ -536,7 +424,6 @@ config MACH_PCM037
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX31
         help
           Include support for Phytec pcm037 platform. This includes
           specific configurations for the board and its peripherals.
@@ -553,20 +440,18 @@ config MACH_PCM037_EET
 
 config MACH_MX31_3DS
         bool "Support MX31PDK (3DS)"
+        select SOC_IMX31
+        select MXC_DEBUG_BOARD
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_DEBUG_BOARD
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX31
         help
           Include support for MX31PDK (3DS) platform. This includes specific
           configurations for the board and its peripherals.
@@ -582,10 +467,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
 
 config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -593,22 +477,21 @@ config MACH_MX31MOBOARD
         select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX31
         help
           Include support for mx31moboard platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_QONG
         bool "Support Dave/DENX QongEVB-LITE platform"
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
         select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for Dave/DENX QongEVB-LITE platform. This includes
           specific configurations for the board and its peripherals.
 
 config MACH_ARMADILLO5X0
         bool "Support Atmark Armadillo-500 Development Base Board"
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -617,39 +500,32 @@ config MACH_ARMADILLO5X0
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX31
         help
           Include support for Atmark Armadillo-500 platform. This includes
           specific configurations for the board and its peripherals.
 
 config MACH_KZM_ARM11_01
         bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
-        select IMX_HAVE_PLATFORM_IMX_UART
         select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for KZM-ARM11-01. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_BUG
         bool "Support Buglabs BUGBase platform"
-        default y
-        select IMX_HAVE_PLATFORM_IMX_UART
         select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        default y
         help
           Include support for BUGBase 1.3 platform. This includes specific
           configurations for the board and its peripherals.
 
-config MACH_IMX31_DT
-        bool "Support i.MX31 platforms from device tree"
-        select SOC_IMX31
-        help
-          Include support for Freescale i.MX31 based platforms
-          using the device tree for discovery.
-
 comment "MX35 platforms:"
 
 config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
+        select SOC_IMX35
         select IMX_HAVE_PLATFORM_FLEXCAN
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
@@ -661,31 +537,28 @@ config MACH_PCM043
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX35
         help
           Include support for Phytec pcm043 platform. This includes
           specific configurations for the board and its peripherals.
 
 config MACH_MX35_3DS
         bool "Support MX35PDK platform"
+        select SOC_IMX35
+        select MXC_DEBUG_BOARD
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_MXC_RTC
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_DEBUG_BOARD
-        select SOC_IMX35
         help
           Include support for MX35PDK platform. This includes specific
           configurations for the board and its peripherals.
 
-config MACH_EUKREA_CPUIMX35SD
+config MACH_EUKREA_CPUIMX35
         bool "Support Eukrea CPUIMX35 Platform"
+        select SOC_IMX35
         select IMX_HAVE_PLATFORM_FLEXCAN
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
@@ -695,14 +568,13 @@ config MACH_EUKREA_CPUIMX35SD
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select MXC_ULPI if USB_ULPI
-        select SOC_IMX35
         help
           Include support for Eukrea CPUIMX35 platform. This includes
           specific configurations for the board and its peripherals.
 
 choice
         prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX35SD
+        depends on MACH_EUKREA_CPUIMX35
         default MACH_EUKREA_MBIMXSD35_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD35_BASEBOARD
@@ -710,7 +582,6 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
         select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IPU_CORE
-        select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
         help
           This adds board specific devices that can be found on Eukrea's
@@ -720,151 +591,18 @@ endchoice
 
 config MACH_VPR200
         bool "Support VPR200 platform"
+        select SOC_IMX35
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select SOC_IMX35
         help
           Include support for VPR200 platform. This includes specific
           configurations for the board and its peripherals.
 
 endif
-
-if ARCH_MULTI_V7
-
-comment "i.MX5 platforms:"
-
-config MACH_MX50_RDP
-        bool "Support MX50 reference design platform"
-        depends on BROKEN
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select SOC_IMX50
-        help
-          Include support for MX50 reference design platform (RDP) board. This
-          includes specific configurations for the board and its peripherals.
-
-comment "i.MX51 machines:"
-
-config MACH_IMX51_DT
-        bool "Support i.MX51 platforms from device tree"
-        select MACH_MX51_BABBAGE
-        select SOC_IMX51
-        help
-          Include support for Freescale i.MX51 based platforms
-          using the device tree for discovery
-
-config MACH_MX51_BABBAGE
-        bool "Support MX51 BABBAGE platforms"
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select SOC_IMX51
-        help
-          Include support for MX51 Babbage platform, also known as MX51EVK in
-          u-boot. This includes specific configurations for the board and its
-          peripherals.
-
-config MACH_MX51_3DS
-        bool "Support MX51PDK (3DS)"
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_DEBUG_BOARD
-        select SOC_IMX51
-        help
-          Include support for MX51PDK (3DS) platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_EUKREA_CPUIMX51SD
-        bool "Support Eukrea CPUIMX51SD module"
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select SOC_IMX51
-        help
-          Include support for Eukrea CPUIMX51SD platform. This includes
-          specific configurations for the module and its peripherals.
-
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX51SD
-        default MACH_EUKREA_MBIMXSD51_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD51_BASEBOARD
-        prompt "Eukrea MBIMXSD development board"
-        bool
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMXSD evaluation board.
-
-endchoice
-
-comment "Device tree only"
-
-config  SOC_IMX53
-        bool "i.MX53 support"
-        select ARCH_MX5
-        select ARCH_MX53
-        select HAVE_CAN_FLEXCAN if CAN
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select PINCTRL
-        select PINCTRL_IMX53
-        select SOC_IMX5
-
-        help
-          This enables support for Freescale i.MX53 processor.
-
-config SOC_IMX6Q
-        bool "i.MX6 Quad support"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_OPP
-        select ARM_CPU_SUSPEND if PM
-        select ARM_ERRATA_754322
-        select ARM_ERRATA_764369 if SMP
-        select ARM_ERRATA_775420
-        select ARM_GIC
-        select COMMON_CLK
-        select CPU_V7
-        select HAVE_ARM_SCU
-        select HAVE_CAN_FLEXCAN if CAN
-        select HAVE_IMX_GPC
-        select HAVE_IMX_MMDC
-        select HAVE_SMP
-        select MFD_SYSCON
-        select PINCTRL
-        select PINCTRL_IMX6Q
-        select PL310_ERRATA_588369 if CACHE_PL310
-        select PL310_ERRATA_727915 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
-        select PM_OPP if PM
-
-        help
-          This enables support for Freescale i.MX6 Quad processor.
-
-endif
-
-source "arch/arm/mach-imx/devices/Kconfig"
-
-endmenu
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0634b3152c2..e9eb36dad88 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,39 +1,16 @@
-obj-y := time.o cpu.o system.o irq-common.o
+obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
-obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
-obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
+obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
-obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
 
-obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
-
-imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
-
-obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
-                            clk-pfd.o clk-busy.o clk.o
-
-obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
-obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
-
-obj-$(CONFIG_MXC_TZIC) += tzic.o
-obj-$(CONFIG_MXC_AVIC) += avic.o
-
-obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
-obj-$(CONFIG_MXC_ULPI) += ulpi.o
-obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
-obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-
-ifdef CONFIG_SND_IMX_SOC
-obj-y += ssi-fiq.o
-obj-y += ssi-fiq-ksym.o
-endif
+obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -48,9 +25,8 @@ obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 
 # i.MX25 based machines
 obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
-obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
 
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
@@ -64,7 +40,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
 obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
-obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
 
 # i.MX31 based machines
 obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
@@ -79,36 +54,10 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
 obj-$(CONFIG_MACH_BUG) += mach-bug.o
-obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
 
 # i.MX35 based machines
 obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
 obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
-
-obj-$(CONFIG_DEBUG_LL) += lluart.o
-obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
-obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
-obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-AFLAGS_headsmp.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SMP) += headsmp.o platsmp.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
-
-ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
-endif
-
-# i.MX5 based machines
-obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
-obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
-obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
-
-obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
-
-obj-y += devices/
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index b27815de847..ebee18b3884 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -1,39 +1,19 @@
-zreladdr-$(CONFIG_SOC_IMX1)     += 0x08008000
-params_phys-$(CONFIG_SOC_IMX1)  := 0x08000100
-initrd_phys-$(CONFIG_SOC_IMX1)  := 0x08800000
+zreladdr-$(CONFIG_ARCH_MX1)     := 0x08008000
+params_phys-$(CONFIG_ARCH_MX1)  := 0x08000100
+initrd_phys-$(CONFIG_ARCH_MX1)  := 0x08800000
 
-zreladdr-$(CONFIG_SOC_IMX21)    += 0xC0008000
-params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
-initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
+zreladdr-$(CONFIG_MACH_MX21)    := 0xC0008000
+params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
+initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
 
-zreladdr-$(CONFIG_SOC_IMX25)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
+zreladdr-$(CONFIG_ARCH_MX25)    := 0x80008000
+params_phys-$(CONFIG_ARCH_MX25) := 0x80000100
+initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
 
-zreladdr-$(CONFIG_SOC_IMX27)    += 0xA0008000
-params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
-initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
+zreladdr-$(CONFIG_MACH_MX27)    := 0xA0008000
+params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
+initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
 
-zreladdr-$(CONFIG_SOC_IMX31)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX35)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX50)    += 0x70008000
-params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
-initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
-
-zreladdr-$(CONFIG_SOC_IMX51)    += 0x90008000
-params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
-initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
-
-zreladdr-$(CONFIG_SOC_IMX53)    += 0x70008000
-params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
-initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
-
-zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
-params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
-initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
+zreladdr-$(CONFIG_ARCH_MX3)     := 0x80008000
+params_phys-$(CONFIG_ARCH_MX3)  := 0x80000100
+initrd_phys-$(CONFIG_ARCH_MX3)  := 0x80800000
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
deleted file mode 100644
index 0eff23ed92b..00000000000
--- a/arch/arm/mach-imx/avic.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <asm/mach/irq.h>
-#include <asm/exception.h>
-
-#include "common.h"
-#include "hardware.h"
-#include "irq-common.h"
-
-#define AVIC_INTCNTL            0x00    /* int control reg */
-#define AVIC_NIMASK             0x04    /* int mask reg */
-#define AVIC_INTENNUM           0x08    /* int enable number reg */
-#define AVIC_INTDISNUM          0x0C    /* int disable number reg */
-#define AVIC_INTENABLEH         0x10    /* int enable reg high */
-#define AVIC_INTENABLEL         0x14    /* int enable reg low */
-#define AVIC_INTTYPEH           0x18    /* int type reg high */
-#define AVIC_INTTYPEL           0x1C    /* int type reg low */
-#define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
-#define AVIC_NIVECSR            0x40    /* norm int vector/status */
-#define AVIC_FIVECSR            0x44    /* fast int vector/status */
-#define AVIC_INTSRCH            0x48    /* int source reg high */
-#define AVIC_INTSRCL            0x4C    /* int source reg low */
-#define AVIC_INTFRCH            0x50    /* int force reg high */
-#define AVIC_INTFRCL            0x54    /* int force reg low */
-#define AVIC_NIPNDH             0x58    /* norm int pending high */
-#define AVIC_NIPNDL             0x5C    /* norm int pending low */
-#define AVIC_FIPNDH             0x60    /* fast int pending high */
-#define AVIC_FIPNDL             0x64    /* fast int pending low */
-
-#define AVIC_NUM_IRQS 64
-
-void __iomem *avic_base;
-static struct irq_domain *domain;
-
-static u32 avic_saved_mask_reg[2];
-
-#ifdef CONFIG_MXC_IRQ_PRIOR
-static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
-{
-        struct irq_data *d = irq_get_irq_data(irq);
-        unsigned int temp;
-        unsigned int mask = 0x0F << irq % 8 * 4;
-
-        irq = d->hwirq;
-
-        if (irq >= AVIC_NUM_IRQS)
-                return -EINVAL;
-
-        temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
-        temp &= ~mask;
-        temp |= prio & mask;
-
-        __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
-
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_FIQ
-static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
-{
-        struct irq_data *d = irq_get_irq_data(irq);
-        unsigned int irqt;
-
-        irq = d->hwirq;
-
-        if (irq >= AVIC_NUM_IRQS)
-                return -EINVAL;
-
-        if (irq < AVIC_NUM_IRQS / 2) {
-                irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
-                __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
-        } else {
-                irq -= AVIC_NUM_IRQS / 2;
-                irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
-                __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
-        }
-
-        return 0;
-}
-#endif /* CONFIG_FIQ */
-
-
-static struct mxc_extra_irq avic_extra_irq = {
-#ifdef CONFIG_MXC_IRQ_PRIOR
-        .set_priority = avic_irq_set_priority,
-#endif
-#ifdef CONFIG_FIQ
-        .set_irq_fiq = avic_set_irq_fiq,
-#endif
-};
-
-#ifdef CONFIG_PM
-static void avic_irq_suspend(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct irq_chip_type *ct = gc->chip_types;
-        int idx = d->hwirq >> 5;
-
-        avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
-        __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
-}
-
-static void avic_irq_resume(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct irq_chip_type *ct = gc->chip_types;
-        int idx = d->hwirq >> 5;
-
-        __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
-}
-
-#else
-#define avic_irq_suspend NULL
-#define avic_irq_resume NULL
-#endif
-
-static __init void avic_init_gc(int idx, unsigned int irq_start)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
-                                    handle_level_irq);
-        gc->private = &avic_extra_irq;
-        gc->wake_enabled = IRQ_MSK(32);
-
-        ct = gc->chip_types;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->chip.irq_ack = irq_gc_mask_clr_bit;
-        ct->chip.irq_set_wake = irq_gc_set_wake;
-        ct->chip.irq_suspend = avic_irq_suspend;
-        ct->chip.irq_resume = avic_irq_resume;
-        ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
-        ct->regs.ack = ct->regs.mask;
-
-        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
-}
-
-asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
-{
-        u32 nivector;
-
-        do {
-                nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
-                if (nivector == 0xffff)
-                        break;
-
-                handle_IRQ(irq_find_mapping(domain, nivector), regs);
-        } while (1);
-}
-
-/*
- * This function initializes the AVIC hardware and disables all the
- * interrupts. It registers the interrupt enable and disable functions
- * to the kernel for each interrupt source.
- */
-void __init mxc_init_irq(void __iomem *irqbase)
-{
-        struct device_node *np;
-        int irq_base;
-        int i;
-
-        avic_base = irqbase;
-
-        /* put the AVIC into the reset value with
-         * all interrupts disabled
-         */
-        __raw_writel(0, avic_base + AVIC_INTCNTL);
-        __raw_writel(0x1f, avic_base + AVIC_NIMASK);
-
-        /* disable all interrupts */
-        __raw_writel(0, avic_base + AVIC_INTENABLEH);
-        __raw_writel(0, avic_base + AVIC_INTENABLEL);
-
-        /* all IRQ no FIQ */
-        __raw_writel(0, avic_base + AVIC_INTTYPEH);
-        __raw_writel(0, avic_base + AVIC_INTTYPEL);
-
-        irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
-        WARN_ON(irq_base < 0);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,avic");
-        domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
-                                       &irq_domain_simple_ops, NULL);
-        WARN_ON(!domain);
-
-        for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
-                avic_init_gc(i, irq_base);
-
-        /* Set default priority value (0) for all IRQ's */
-        for (i = 0; i < 8; i++)
-                __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
-
-#ifdef CONFIG_FIQ
-        /* Initialize FIQ */
-        init_FIQ(FIQ_START);
-#endif
-
-        printk(KERN_INFO "MXC IRQ initialized\n");
-}
diff --git a/arch/arm/mach-imx/board-mx31lilly.h b/arch/arm/mach-imx/board-mx31lilly.h
deleted file mode 100644
index 0df71bfefbb..00000000000
--- a/arch/arm/mach-imx/board-mx31lilly.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * Based on code for mobots boards,
- *   Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
-#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
-
-#ifndef __ASSEMBLY__
-
-enum mx31lilly_boards {
-        MX31LILLY_NOBOARD       = 0,
-        MX31LILLY_DB            = 1,
-};
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- */
-
-extern void mx31lilly_db_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */
diff --git a/arch/arm/mach-imx/board-mx31lite.h b/arch/arm/mach-imx/board-mx31lite.h
deleted file mode 100644
index c1ad0ae807c..00000000000
--- a/arch/arm/mach-imx/board-mx31lite.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * Based on code for mobots boards,
- *   Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-
-#ifndef __ASSEMBLY__
-
-enum mx31lite_boards {
-        MX31LITE_NOBOARD        = 0,
-        MX31LITE_DB             = 1,
-};
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- */
-
-extern void mx31lite_db_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/mach-imx/board-mx31moboard.h b/arch/arm/mach-imx/board-mx31moboard.h
deleted file mode 100644
index de14543891c..00000000000
--- a/arch/arm/mach-imx/board-mx31moboard.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
-#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
-
-#ifndef __ASSEMBLY__
-
-enum mx31moboard_boards {
-        MX31NOBOARD     = 0,
-        MX31DEVBOARD    = 1,
-        MX31MARXBOT     = 2,
-        MX31SMARTBOT    = 3,
-        MX31EYEBOT      = 4,
-};
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- */
-
-extern void mx31moboard_devboard_init(void);
-extern void mx31moboard_marxbot_init(void);
-extern void mx31moboard_smartbot_init(int board);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */
diff --git a/arch/arm/mach-imx/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h
deleted file mode 100644
index 6f371e35753..00000000000
--- a/arch/arm/mach-imx/board-pcm038.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
-#define __ASM_ARCH_MXC_BOARD_PCM038_H__
-
-#ifndef __ASSEMBLY__
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- * TODO: Add your own baseboard init function and call it from
- * inside pcm038_init().
- *
- * This example here is for the development board. Refer pcm970-baseboard.c
- */
-
-extern void pcm970_baseboard_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
deleted file mode 100644
index 1ab91b5209e..00000000000
--- a/arch/arm/mach-imx/clk-busy.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/jiffies.h>
-#include <linux/err.h>
-#include "clk.h"
-
-static int clk_busy_wait(void __iomem *reg, u8 shift)
-{
-        unsigned long timeout = jiffies + msecs_to_jiffies(10);
-
-        while (readl_relaxed(reg) & (1 << shift))
-                if (time_after(jiffies, timeout))
-                        return -ETIMEDOUT;
-
-        return 0;
-}
-
-struct clk_busy_divider {
-        struct clk_divider div;
-        const struct clk_ops *div_ops;
-        void __iomem *reg;
-        u8 shift;
-};
-
-static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
-{
-        struct clk_divider *div = container_of(hw, struct clk_divider, hw);
-
-        return container_of(div, struct clk_busy_divider, div);
-}
-
-static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw,
-                                                  unsigned long parent_rate)
-{
-        struct clk_busy_divider *busy = to_clk_busy_divider(hw);
-
-        return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate);
-}
-
-static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate,
-                                        unsigned long *prate)
-{
-        struct clk_busy_divider *busy = to_clk_busy_divider(hw);
-
-        return busy->div_ops->round_rate(&busy->div.hw, rate, prate);
-}
-
-static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_busy_divider *busy = to_clk_busy_divider(hw);
-        int ret;
-
-        ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate);
-        if (!ret)
-                ret = clk_busy_wait(busy->reg, busy->shift);
-
-        return ret;
-}
-
-static struct clk_ops clk_busy_divider_ops = {
-        .recalc_rate = clk_busy_divider_recalc_rate,
-        .round_rate = clk_busy_divider_round_rate,
-        .set_rate = clk_busy_divider_set_rate,
-};
-
-struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
-                                 void __iomem *reg, u8 shift, u8 width,
-                                 void __iomem *busy_reg, u8 busy_shift)
-{
-        struct clk_busy_divider *busy;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        busy = kzalloc(sizeof(*busy), GFP_KERNEL);
-        if (!busy)
-                return ERR_PTR(-ENOMEM);
-
-        busy->reg = busy_reg;
-        busy->shift = busy_shift;
-
-        busy->div.reg = reg;
-        busy->div.shift = shift;
-        busy->div.width = width;
-        busy->div.lock = &imx_ccm_lock;
-        busy->div_ops = &clk_divider_ops;
-
-        init.name = name;
-        init.ops = &clk_busy_divider_ops;
-        init.flags = CLK_SET_RATE_PARENT;
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-
-        busy->div.hw.init = &init;
-
-        clk = clk_register(NULL, &busy->div.hw);
-        if (IS_ERR(clk))
-                kfree(busy);
-
-        return clk;
-}
-
-struct clk_busy_mux {
-        struct clk_mux mux;
-        const struct clk_ops *mux_ops;
-        void __iomem *reg;
-        u8 shift;
-};
-
-static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
-{
-        struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
-
-        return container_of(mux, struct clk_busy_mux, mux);
-}
-
-static u8 clk_busy_mux_get_parent(struct clk_hw *hw)
-{
-        struct clk_busy_mux *busy = to_clk_busy_mux(hw);
-
-        return busy->mux_ops->get_parent(&busy->mux.hw);
-}
-
-static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_busy_mux *busy = to_clk_busy_mux(hw);
-        int ret;
-
-        ret = busy->mux_ops->set_parent(&busy->mux.hw, index);
-        if (!ret)
-                ret = clk_busy_wait(busy->reg, busy->shift);
-
-        return ret;
-}
-
-struct clk_ops clk_busy_mux_ops = {
-        .get_parent = clk_busy_mux_get_parent,
-        .set_parent = clk_busy_mux_set_parent,
-};
-
-struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
-                             u8 width, void __iomem *busy_reg, u8 busy_shift,
-                             const char **parent_names, int num_parents)
-{
-        struct clk_busy_mux *busy;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        busy = kzalloc(sizeof(*busy), GFP_KERNEL);
-        if (!busy)
-                return ERR_PTR(-ENOMEM);
-
-        busy->reg = busy_reg;
-        busy->shift = busy_shift;
-
-        busy->mux.reg = reg;
-        busy->mux.shift = shift;
-        busy->mux.width = width;
-        busy->mux.lock = &imx_ccm_lock;
-        busy->mux_ops = &clk_mux_ops;
-
-        init.name = name;
-        init.ops = &clk_busy_mux_ops;
-        init.flags = 0;
-        init.parent_names = parent_names;
-        init.num_parents = num_parents;
-
-        busy->mux.hw.init = &init;
-
-        clk = clk_register(NULL, &busy->mux.hw);
-        if (IS_ERR(clk))
-                kfree(busy);
-
-        return clk;
-}
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
deleted file mode 100644
index cc49c7ae186..00000000000
--- a/arch/arm/mach-imx/clk-gate2.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
- * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Gated clock implementation
- */
-
-#include <linux/clk-provider.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/string.h>
-
-/**
- * DOC: basic gatable clock which can gate and ungate it's ouput
- *
- * Traits of this clock:
- * prepare - clk_(un)prepare only ensures parent is (un)prepared
- * enable - clk_enable and clk_disable are functional & control gating
- * rate - inherits rate from parent.  No clk_set_rate support
- * parent - fixed parent.  No clk_set_parent support
- */
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static int clk_gate2_enable(struct clk_hw *hw)
-{
-        struct clk_gate *gate = to_clk_gate(hw);
-        u32 reg;
-        unsigned long flags = 0;
-
-        if (gate->lock)
-                spin_lock_irqsave(gate->lock, flags);
-
-        reg = readl(gate->reg);
-        reg |= 3 << gate->bit_idx;
-        writel(reg, gate->reg);
-
-        if (gate->lock)
-                spin_unlock_irqrestore(gate->lock, flags);
-
-        return 0;
-}
-
-static void clk_gate2_disable(struct clk_hw *hw)
-{
-        struct clk_gate *gate = to_clk_gate(hw);
-        u32 reg;
-        unsigned long flags = 0;
-
-        if (gate->lock)
-                spin_lock_irqsave(gate->lock, flags);
-
-        reg = readl(gate->reg);
-        reg &= ~(3 << gate->bit_idx);
-        writel(reg, gate->reg);
-
-        if (gate->lock)
-                spin_unlock_irqrestore(gate->lock, flags);
-}
-
-static int clk_gate2_is_enabled(struct clk_hw *hw)
-{
-        u32 reg;
-        struct clk_gate *gate = to_clk_gate(hw);
-
-        reg = readl(gate->reg);
-
-        if (((reg >> gate->bit_idx) & 3) == 3)
-                return 1;
-
-        return 0;
-}
-
-static struct clk_ops clk_gate2_ops = {
-        .enable = clk_gate2_enable,
-        .disable = clk_gate2_disable,
-        .is_enabled = clk_gate2_is_enabled,
-};
-
-struct clk *clk_register_gate2(struct device *dev, const char *name,
-                const char *parent_name, unsigned long flags,
-                void __iomem *reg, u8 bit_idx,
-                u8 clk_gate2_flags, spinlock_t *lock)
-{
-        struct clk_gate *gate;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-        if (!gate)
-                return ERR_PTR(-ENOMEM);
-
-        /* struct clk_gate assignments */
-        gate->reg = reg;
-        gate->bit_idx = bit_idx;
-        gate->flags = clk_gate2_flags;
-        gate->lock = lock;
-
-        init.name = name;
-        init.ops = &clk_gate2_ops;
-        init.flags = flags;
-        init.parent_names = parent_name ? &parent_name : NULL;
-        init.num_parents = parent_name ? 1 : 0;
-
-        gate->hw.init = &init;
-
-        clk = clk_register(dev, &gate->hw);
-        if (IS_ERR(clk))
-                kfree(gate);
-
-        return clk;
-}
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
deleted file mode 100644
index 15f9d223cf0..00000000000
--- a/arch/arm/mach-imx/clk-imx1.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-
-/* CCM register addresses */
-#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
-
-#define CCM_CSCR        IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
-#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
-#define CCM_PCDR        IO_ADDR_CCM(0x20)
-
-/* SCM register addresses */
-#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
-
-#define SCM_GCCR        IO_ADDR_SCM(0xc)
-
-static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
-static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
-                                "fclk", };
-enum imx1_clks {
-        dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
-        fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
-        mma_gate, usbd_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
-
-int __init mx1_clocks_init(unsigned long fref)
-{
-        int i;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[clk32] = imx_clk_fixed("clk32", fref);
-        clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
-        clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
-        clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
-        clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
-                        ARRAY_SIZE(prem_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
-        clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
-        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
-        clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
-        clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
-        clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
-        clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
-        clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
-        clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
-                        ARRAY_SIZE(clko_sel_clks));
-        clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
-        clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
-        clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
-        clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("imx1 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
-        clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
-        clk_register_clkdev(clk[mma_gate], "mma", NULL);
-        clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
-        clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
-        clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
-        clk_register_clkdev(clk[hclk], "mshc", NULL);
-        clk_register_clkdev(clk[per3], "ssi", NULL);
-        clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0");
-        clk_register_clkdev(clk[clko], "clko", NULL);
-
-        mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
deleted file mode 100644
index d7ed66091a2..00000000000
--- a/arch/arm/mach-imx/clk-imx21.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/err.h>
-
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-
-#define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-static const char *mpll_sel_clks[] = { "fpm", "ckih", };
-static const char *spll_sel_clks[] = { "fpm", "ckih", };
-
-enum imx21_clks {
-        ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
-        per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
-        uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
-        pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
-        lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
-        per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
-        ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
-        emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
-        gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx21_clocks_init(unsigned long lref, unsigned long href)
-{
-        int i;
-
-        clk[ckil] = imx_clk_fixed("ckil", lref);
-        clk[ckih] = imx_clk_fixed("ckih", href);
-        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
-        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-                        ARRAY_SIZE(mpll_sel_clks));
-        clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
-                        ARRAY_SIZE(spll_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
-        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
-        clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
-        clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
-        clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
-        clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
-        clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
-        clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
-        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
-        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
-        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
-        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
-        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
-        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
-        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
-        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
-        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
-        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
-        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
-        clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
-        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
-        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
-        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
-        clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
-        clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
-        clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
-        clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
-        clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
-        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
-        clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
-        clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
-        clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
-        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
-        clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
-        clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
-        clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
-        clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
-        clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
-        clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
-        clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
-        clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
-        clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
-        clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX21 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[per1], "per1", NULL);
-        clk_register_clkdev(clk[per2], "per2", NULL);
-        clk_register_clkdev(clk[per3], "per3", NULL);
-        clk_register_clkdev(clk[per4], "per4", NULL);
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
-        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
-        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
-        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
-        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
-        clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
-        clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
-        clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
-        clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
-        clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
-        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
-        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[brom_gate], "brom", NULL);
-        clk_register_clkdev(clk[emma_gate], "emma", NULL);
-        clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
-        clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
-        clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
-        clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
-        clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
-        clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
-
-        mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
deleted file mode 100644
index b197aa73dc4..00000000000
--- a/arch/arm/mach-imx/clk-imx25.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-#include "mx25.h"
-
-#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
-
-#define CCM_MPCTL       0x00
-#define CCM_UPCTL       0x04
-#define CCM_CCTL        0x08
-#define CCM_CGCR0       0x0C
-#define CCM_CGCR1       0x10
-#define CCM_CGCR2       0x14
-#define CCM_PCDR0       0x18
-#define CCM_PCDR1       0x1C
-#define CCM_PCDR2       0x20
-#define CCM_PCDR3       0x24
-#define CCM_RCSR        0x28
-#define CCM_CRDR        0x2C
-#define CCM_DCVR0       0x30
-#define CCM_DCVR1       0x34
-#define CCM_DCVR2       0x38
-#define CCM_DCVR3       0x3c
-#define CCM_LTR0        0x40
-#define CCM_LTR1        0x44
-#define CCM_LTR2        0x48
-#define CCM_LTR3        0x4c
-#define CCM_MCR         0x64
-
-#define ccm(x)  (CRM_BASE + (x))
-
-static struct clk_onecell_data clk_data;
-
-static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
-static const char *per_sel_clks[] = { "ahb", "upll", };
-
-enum mx25_clks {
-        dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
-        per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
-        per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
-        per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
-        per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
-        csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
-        gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
-        pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
-        uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
-        esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
-        reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
-        cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
-        reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
-        gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
-        iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
-        pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
-        sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
-        uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
-        wdt_ipg, clk_max
-};
-
-static struct clk *clk[clk_max];
-
-static int __init __mx25_clocks_init(unsigned long osc_rate)
-{
-        int i;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[osc] = imx_clk_fixed("osc", osc_rate);
-        clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
-        clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
-        clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
-        clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
-        clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
-        clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
-        clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); 
-        clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
-        clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
-        clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
-        clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
-        clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
-        clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
-        clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
-        clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
-        clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
-        clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
-        clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
-        clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
-        clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
-        clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
-        clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
-        clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
-        clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
-        clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
-        clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
-        clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0),  1);
-        clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0),  2);
-        clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0),  3);
-        clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0),  4);
-        clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0),  5);
-        clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0),  6);
-        clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0),  7);
-        clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0),  8);
-        clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0),  9);
-        clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0),  10);
-        clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0),  11);
-        clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0),  12);
-        clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
-        clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
-        clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
-        clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16);
-        /* CCM_CGCR0(17): reserved */
-        clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
-        clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19);
-        clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20);
-        clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
-        clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
-        clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
-        clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
-        clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25);
-        clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
-        clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27);
-        clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
-        /* CCM_CGCR0(29-31): reserved */
-        /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */
-        clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1),  2);
-        clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1),  3);
-        clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1),  4);
-        clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1),  5);
-        clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1),  6);
-        clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1),  7);
-        clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1),  8);
-        clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1),  9);
-        clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1),  10);
-        clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1),  11);
-        /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */
-        clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
-        clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
-        clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
-        /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */
-        /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */
-        /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */
-        clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19);
-        clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20);
-        clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21);
-        clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22);
-        /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */
-        /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */
-        /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */
-        clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
-        /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */
-        /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */
-        clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
-        clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
-        /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */
-        clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
-        clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2),  0);
-        clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2),  1);
-        clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2),  2);
-        clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2),  3);
-        /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */
-        clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2),  5);
-        clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2),  6);
-        clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2),  7);
-        clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2),  8);
-        clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2),  9);
-        clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2),  10);
-        clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
-        clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
-        clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
-        clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
-        clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
-        clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
-        clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
-        clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
-        /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
-        clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX25 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_prepare_enable(clk[emi_ahb]);
-
-        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-
-        return 0;
-}
-
-int __init mx25_clocks_init(void)
-{
-        __mx25_clocks_init(24000000);
-
-        /* i.mx25 has the i.mx21 type uart */
-        clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
-        clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
-        /* i.mx25 has the i.mx35 type cspi */
-        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
-        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
-        clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
-        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
-        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
-        clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
-        clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
-        clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
-        clk_register_clkdev(clk[dummy], "audmux", NULL);
-        clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
-        clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
-        /* i.mx25 has the i.mx35 type sdma */
-        clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
-        clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
-        clk_register_clkdev(clk[iim_ipg], "iim", NULL);
-
-        mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
-
-        return 0;
-}
-
-int __init mx25_clocks_init_dt(void)
-{
-        struct device_node *np;
-        void __iomem *base;
-        int irq;
-        unsigned long osc_rate = 24000000;
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        osc_rate = rate;
-        }
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
-        clk_data.clks = clk;
-        clk_data.clk_num = ARRAY_SIZE(clk);
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
-        __mx25_clocks_init(osc_rate);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-
-        mxc_timer_init(base, irq);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
deleted file mode 100644
index 4c1d1e4efc7..00000000000
--- a/arch/arm/mach-imx/clk-imx27.c
+++ /dev/null
@@ -1,305 +0,0 @@
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-
-#define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_UPDATE_DIS     (1 << 31)
-#define CCM_CSCR_SSI2           (1 << 23)
-#define CCM_CSCR_SSI1           (1 << 22)
-#define CCM_CSCR_VPU            (1 << 21)
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
-
-static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
-static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
-static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
-static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
-static const char *clko_sel_clks[] = {
-        "ckil", "fpm", "ckih", "ckih",
-        "ckih", "mpll", "spll", "cpu_div",
-        "ahb", "ipg", "per1_div", "per2_div",
-        "per3_div", "per4_div", "ssi1_div", "ssi2_div",
-        "nfc_div", "mshc_div", "vpu_div", "60m",
-        "32k", "usb_div", "dptc",
-};
-
-static const char *ssi_sel_clks[] = { "spll", "mpll", };
-
-enum mx27_clks {
-        dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
-        per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
-        clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
-        clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
-        sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
-        rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
-        kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
-        gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
-        gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
-        emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
-        cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
-        vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
-        usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
-        vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
-        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
-        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
-        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
-        mpll_sel, clk_max
-};
-
-static struct clk *clk[clk_max];
-
-int __init mx27_clocks_init(unsigned long fref)
-{
-        int i;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckih] = imx_clk_fixed("ckih", fref);
-        clk[ckil] = imx_clk_fixed("ckil", 32768);
-        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
-        clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
-
-        clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
-                        mpll_osc_sel_clks,
-                        ARRAY_SIZE(mpll_osc_sel_clks));
-        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-                        ARRAY_SIZE(mpll_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
-        clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
-
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
-                clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
-        } else {
-                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
-                clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
-        }
-
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
-        clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
-        clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
-        clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
-        clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
-        clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
-        clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
-        clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
-        clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
-        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
-        else
-                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
-        clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
-        clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
-        clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
-        clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
-        clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
-        clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
-        clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
-        clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
-        clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
-        clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
-        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
-        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
-        clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
-        clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
-        clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
-        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
-        clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
-        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
-        clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
-        clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
-        clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
-        clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
-        clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
-        clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
-        clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
-        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
-        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
-        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
-        clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
-        clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
-        clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
-        clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
-        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
-        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
-        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
-        clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
-        clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
-        clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
-        clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
-        clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
-        clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
-        clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
-        clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
-        clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
-        clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
-        clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
-        clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
-        clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
-        clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
-        clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
-        clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
-        clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
-        clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
-        clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
-        clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
-        clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
-        clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
-        clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
-        clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
-        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
-        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
-        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
-        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX27 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
-        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
-        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
-        clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
-        clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
-        clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
-        clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
-        clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
-        clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
-        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
-        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
-        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
-        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
-        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
-        clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
-        clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
-        clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
-        clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
-        clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
-        clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
-        clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
-        clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
-        clk_register_clkdev(clk[cpu_div], "cpu", NULL);
-        clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
-        clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
-
-        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
-
-        clk_prepare_enable(clk[emi_ahb_gate]);
-
-        imx_print_silicon_rev("i.MX27", mx27_revision());
-
-        return 0;
-}
-
-#ifdef CONFIG_OF
-int __init mx27_clocks_init_dt(void)
-{
-        struct device_node *np;
-        u32 fref = 26000000; /* default */
-
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
-                        continue;
-
-                if (!of_property_read_u32(np, "clock-frequency", &fref))
-                        break;
-        }
-
-        return mx27_clocks_init(fref);
-}
-#endif
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
deleted file mode 100644
index 8be64e0a4ac..00000000000
--- a/arch/arm/mach-imx/clk-imx31.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/of.h>
-
-#include "clk.h"
-#include "common.h"
-#include "crmregs-imx3.h"
-#include "hardware.h"
-#include "mx31.h"
-
-static const char *mcu_main_sel[] = { "spll", "mpll", };
-static const char *per_sel[] = { "per_div", "ipg", };
-static const char *csi_sel[] = { "upll", "spll", };
-static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
-
-enum mx31_clks {
-        ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
-        per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
-        fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
-        iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
-        uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
-        mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
-        sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
-        uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
-        gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
-
-int __init mx31_clocks_init(unsigned long fref)
-{
-        void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
-        int i;
-
-        clk[ckih] = imx_clk_fixed("ckih", fref);
-        clk[ckil] = imx_clk_fixed("ckil", 32768);
-        clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
-        clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL);
-        clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL);
-        clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
-        clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
-        clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
-        clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
-        clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
-        clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
-        clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
-        clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
-        clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
-        clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
-        clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
-        clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
-        clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
-        clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
-        clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
-        clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
-        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
-        clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
-        clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
-        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
-        clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
-        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
-        clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
-        clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
-        clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
-        clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
-        clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
-        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
-        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
-        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
-        clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
-        clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
-        clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
-        clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
-        clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
-        clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
-        clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
-        clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
-        clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
-        clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
-        clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
-        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
-        clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
-        clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
-        clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
-        clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
-        clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
-        clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
-        clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
-        clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
-        clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
-        clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
-        clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("imx31 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
-        clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
-        clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
-        clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
-        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc");
-        clk_register_clkdev(clk[epit1_gate], "epit", NULL);
-        clk_register_clkdev(clk[epit2_gate], "epit", NULL);
-        clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
-        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
-        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
-        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
-        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
-        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
-        /* i.mx31 has the i.mx21 type uart */
-        clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
-        clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
-        clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[firi_gate], "firi", NULL);
-        clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
-        clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
-        clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
-        clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
-        clk_register_clkdev(clk[iim_gate], "iim", NULL);
-
-        clk_set_parent(clk[csi], clk[upll]);
-        clk_prepare_enable(clk[emi_gate]);
-        clk_prepare_enable(clk[iim_gate]);
-        mx31_revision();
-        clk_disable_unprepare(clk[iim_gate]);
-
-        mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
-
-        return 0;
-}
-
-#ifdef CONFIG_OF
-int __init mx31_clocks_init_dt(void)
-{
-        struct device_node *np;
-        u32 fref = 26000000; /* default */
-
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
-                        continue;
-
-                if (!of_property_read_u32(np, "clock-frequency", &fref))
-                        break;
-        }
-
-        return mx31_clocks_init(fref);
-}
-#endif
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
deleted file mode 100644
index 66f3d65ea27..00000000000
--- a/arch/arm/mach-imx/clk-imx35.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-#include <linux/err.h>
-
-#include "crmregs-imx3.h"
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-
-struct arm_ahb_div {
-        unsigned char arm, ahb, sel;
-};
-
-static struct arm_ahb_div clk_consumer[] = {
-        { .arm = 1, .ahb = 4, .sel = 0},
-        { .arm = 1, .ahb = 3, .sel = 1},
-        { .arm = 2, .ahb = 2, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 4, .ahb = 1, .sel = 0},
-        { .arm = 1, .ahb = 5, .sel = 0},
-        { .arm = 1, .ahb = 8, .sel = 0},
-        { .arm = 1, .ahb = 6, .sel = 1},
-        { .arm = 2, .ahb = 4, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 4, .ahb = 2, .sel = 0},
-        { .arm = 0, .ahb = 0, .sel = 0},
-};
-
-static char hsp_div_532[] = { 4, 8, 3, 0 };
-static char hsp_div_400[] = { 3, 6, 3, 0 };
-
-static const char *std_sel[] = {"ppll", "arm"};
-static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
-
-enum mx35_clks {
-        ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
-        arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
-        esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
-        spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
-        ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate,
-        audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate,
-        edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
-        esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate,
-        gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate,
-        kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
-        rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
-        ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
-        wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
-        gpu2d_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
-
-int __init mx35_clocks_init()
-{
-        void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
-        u32 pdr0, consumer_sel, hsp_sel;
-        struct arm_ahb_div *aad;
-        unsigned char *hsp_div;
-        int i;
-
-        pdr0 = __raw_readl(base + MXC_CCM_PDR0);
-        consumer_sel = (pdr0 >> 16) & 0xf;
-        aad = &clk_consumer[consumer_sel];
-        if (!aad->arm) {
-                pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
-                /*
-                 * We are basically stuck. Continue with a default entry and hope we
-                 * get far enough to actually show the above message
-                 */
-                aad = &clk_consumer[0];
-        }
-
-        clk[ckih] = imx_clk_fixed("ckih", 24000000);
-        clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
-        clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
-
-        clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
-
-        if (aad->sel)
-                clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
-        else
-                clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
-
-        if (clk_get_rate(clk[arm]) > 400000000)
-                hsp_div = hsp_div_532;
-        else
-                hsp_div = hsp_div_400;
-
-        hsp_sel = (pdr0 >> 20) & 0x3;
-        if (!hsp_div[hsp_sel]) {
-                pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
-                hsp_sel = 0;
-        }
-
-        clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
-
-        clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
-        clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
-
-        clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
-        clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
-        clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
-
-        clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
-        clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
-
-        clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
-        clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
-        clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
-        clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
-
-        clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
-        clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ 
-        clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
-
-        clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
-        clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
-        clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
-        clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
-        clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
-
-        clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
-        clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
-
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
-
-        clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
-        clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
-
-        clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
-        clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
-        clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
-        clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0,  6);
-        clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0,  8);
-        clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
-        clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
-        clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
-        clk[edio_gate] = imx_clk_gate2("edio_gate",   "ipg", base + MX35_CCM_CGR0, 16);
-        clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
-        clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
-        clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
-        clk[esai_gate] = imx_clk_gate2("esai_gate",   "ipg", base + MX35_CCM_CGR0, 24);
-        clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
-        clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
-        clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
-
-        clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1,  0);
-        clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1,  2);
-        clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1,  4);
-        clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1,  6);
-        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1,  8);
-        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
-        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
-        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
-        clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
-        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
-        clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
-        clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
-        clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
-        clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
-        clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
-        clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
-
-        clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2,  0);
-        clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2,  2);
-        clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2,  4);
-        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2,  6);
-        clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2,  8);
-        clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
-        clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
-        clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
-        clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
-        clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
-        clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
-        clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
-        clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
-        clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
-        clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
-
-        clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3,  0);
-        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
-        clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX35 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
-        clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
-        clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
-        clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
-        clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
-        clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
-        clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
-        clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
-        clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
-        clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
-        clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
-        clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
-        clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
-        clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
-        clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
-        clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
-        clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
-        clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
-        /* i.mx35 has the i.mx27 type fec */
-        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
-        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
-        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
-        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-        clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
-        /* i.mx35 has the i.mx21 type uart */
-        clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
-        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
-        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
-        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
-
-        clk_prepare_enable(clk[spba_gate]);
-        clk_prepare_enable(clk[gpio1_gate]);
-        clk_prepare_enable(clk[gpio2_gate]);
-        clk_prepare_enable(clk[gpio3_gate]);
-        clk_prepare_enable(clk[iim_gate]);
-        clk_prepare_enable(clk[emi_gate]);
-
-        /*
-         * SCC is needed to boot via mmc after a watchdog reset. The clock code
-         * before conversion to common clk also enabled UART1 (which isn't
-         * handled here and not needed for mmc) and IIM (which is enabled
-         * unconditionally above).
-         */
-        clk_prepare_enable(clk[scc_gate]);
-
-        imx_print_silicon_rev("i.MX35", mx35_revision());
-
-#ifdef CONFIG_MXC_USE_EPIT
-        epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
-#else
-        mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
-#endif
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
deleted file mode 100644
index 579023f59dc..00000000000
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-#include <linux/err.h>
-
-#include "crm-regs-imx5.h"
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-
-/* Low-power Audio Playback Mode clock */
-static const char *lp_apm_sel[] = { "osc", };
-
-/* This is used multiple times */
-static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
-static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
-static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
-static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
-static const char *per_root_sel[] = { "per_podf", "ipg", };
-static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
-static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
-static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
-static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
-static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
-static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
-static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
-static const char *emi_slow_sel[] = { "main_bus", "ahb", };
-static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
-static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
-static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
-static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
-static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
-static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
-static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
-static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
-static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
-static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
-static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
-static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
-static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
-
-enum imx5_clks {
-        dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
-        uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
-        emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
-        usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
-        tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
-        uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
-        gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
-        gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
-        esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
-        ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
-        ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
-        ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
-        vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
-        uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
-        esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
-        mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
-        ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
-        ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
-        periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
-        tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
-        esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
-        usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
-        pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
-        ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
-        usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
-        ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
-        ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
-        ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
-        ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
-        ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
-        epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
-        can_sel, can1_serial_gate, can1_ipg_gate,
-        clk_max
-};
-
-static struct clk *clk[clk_max];
-static struct clk_onecell_data clk_data;
-
-static void __init mx5_clocks_common_init(unsigned long rate_ckil,
-                unsigned long rate_osc, unsigned long rate_ckih1,
-                unsigned long rate_ckih2)
-{
-        int i;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
-        clk[osc] = imx_clk_fixed("osc", rate_osc);
-        clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
-        clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
-
-        clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
-                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
-        clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
-                                periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
-        clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
-                                main_bus_sel, ARRAY_SIZE(main_bus_sel));
-        clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
-                                per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
-        clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
-        clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
-        clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
-        clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
-                                per_root_sel, ARRAY_SIZE(per_root_sel));
-        clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
-        clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
-        clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
-        clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
-        clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
-        clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
-        clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
-        clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
-        clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
-        clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
-        clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
-        clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
-        clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
-
-        clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
-        clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
-        clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
-        clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
-        clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
-        clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
-
-        clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
-                                emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
-        clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
-        clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
-        clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
-        clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
-        clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
-        clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
-        clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
-        clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
-        clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
-                                usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
-        clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
-        clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
-        clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
-        clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
-        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
-        clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
-        clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
-        clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
-        clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
-        clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
-        clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
-        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
-        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
-        clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
-        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
-        clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
-        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
-        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
-        clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
-        clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
-        clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
-        clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
-        clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
-        clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
-        clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
-        clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
-        clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
-        clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
-        clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
-        clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
-        clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
-        clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
-        clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
-        clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
-        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
-        clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
-        clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
-        clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
-        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
-        clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
-        clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
-        clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
-        clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
-        clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
-        clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
-        clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
-        clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
-        clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
-        clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
-        clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
-
-        clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
-        clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
-        clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
-        clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
-        clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
-        clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
-        clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
-        clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
-        clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
-        clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
-        clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
-        clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
-        clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
-        clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
-        clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
-        clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
-        clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
-        clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
-        clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
-        clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
-        clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX5 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-        
-        clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
-        clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
-        clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
-        clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
-        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
-        clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
-        clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
-        clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
-        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-        clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
-        clk_register_clkdev(clk[iim_gate], "iim", NULL);
-        clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
-        clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
-        clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
-        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
-        clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
-        clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
-        clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
-        clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
-
-        /* Set SDHC parents to be PLL2 */
-        clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
-        clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
-
-        /* move usb phy clk to 24MHz */
-        clk_set_parent(clk[usb_phy_sel], clk[osc]);
-
-        clk_prepare_enable(clk[gpc_dvfs]);
-        clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
-        clk_prepare_enable(clk[aips_tz1]);
-        clk_prepare_enable(clk[aips_tz2]); /* fec */
-        clk_prepare_enable(clk[spba]);
-        clk_prepare_enable(clk[emi_fast_gate]); /* fec */
-        clk_prepare_enable(clk[emi_slow_gate]); /* eim */
-        clk_prepare_enable(clk[mipi_hsc1_gate]);
-        clk_prepare_enable(clk[mipi_hsc2_gate]);
-        clk_prepare_enable(clk[mipi_esc_gate]);
-        clk_prepare_enable(clk[mipi_hsp_gate]);
-        clk_prepare_enable(clk[tmax1]);
-        clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
-        clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
-}
-
-int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
-                        unsigned long rate_ckih1, unsigned long rate_ckih2)
-{
-        int i;
-        u32 val;
-        struct device_node *np;
-
-        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
-        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
-        clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
-        clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
-                                mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
-        clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
-                                mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
-        clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
-                                mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
-        clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
-        clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
-        clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
-        clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
-        clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
-        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
-        clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
-        clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
-        clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
-        clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
-        clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
-        clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX51 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
-        clk_data.clks = clk;
-        clk_data.clk_num = ARRAY_SIZE(clk);
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
-        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
-
-        clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
-        clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
-        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
-        clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
-        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
-
-        /* set the usboh3 parent to pll2_sw */
-        clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
-
-        /* set SDHC root clock to 166.25MHZ*/
-        clk_set_rate(clk[esdhc_a_podf], 166250000);
-        clk_set_rate(clk[esdhc_b_podf], 166250000);
-
-        /* System timer */
-        mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
-
-        clk_prepare_enable(clk[iim_gate]);
-        imx_print_silicon_rev("i.MX51", mx51_revision());
-        clk_disable_unprepare(clk[iim_gate]);
-
-        /*
-         * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
-         * longer supported. Set to one for better power saving.
-         *
-         * The effect of not setting these bits is that MIPI clocks can't be
-         * enabled without the IPU clock being enabled aswell.
-         */
-        val = readl(MXC_CCM_CCDR);
-        val |= 1 << 18;
-        writel(val, MXC_CCM_CCDR);
-
-        val = readl(MXC_CCM_CLPCR);
-        val |= 1 << 23;
-        writel(val, MXC_CCM_CLPCR);
-
-        return 0;
-}
-
-int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
-                        unsigned long rate_ckih1, unsigned long rate_ckih2)
-{
-        int i;
-        unsigned long r;
-        struct device_node *np;
-
-        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
-        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
-        clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
-        clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
-
-        clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
-                                mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
-        clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
-        clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
-        clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
-        clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
-                                mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
-        clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
-        clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
-        clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
-        clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
-        clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
-                                mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
-        clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
-                                mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
-        clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
-                                mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
-        clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
-        clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
-        clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
-        clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
-        clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
-        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
-        clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
-        clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
-        clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
-                                mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
-        clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
-        clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
-        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
-        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
-        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX53 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
-        clk_data.clks = clk;
-        clk_data.clk_num = ARRAY_SIZE(clk);
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
-        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
-
-        clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
-        clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
-        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
-
-        /* set SDHC root clock to 200MHZ*/
-        clk_set_rate(clk[esdhc_a_podf], 200000000);
-        clk_set_rate(clk[esdhc_b_podf], 200000000);
-
-        /* System timer */
-        mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
-
-        clk_prepare_enable(clk[iim_gate]);
-        imx_print_silicon_rev("i.MX53", mx53_revision());
-        clk_disable_unprepare(clk[iim_gate]);
-
-        r = clk_round_rate(clk[usboh3_per_gate], 54000000);
-        clk_set_rate(clk[usboh3_per_gate], r);
-
-        return 0;
-}
-
-#ifdef CONFIG_OF
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                   unsigned long *ckih1, unsigned long *ckih2)
-{
-        struct device_node *np;
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        *ckil = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        *osc = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        *ckih1 = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                        *ckih2 = rate;
-        }
-}
-
-int __init mx51_clocks_init_dt(void)
-{
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
-}
-
-int __init mx53_clocks_init_dt(void)
-{
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
-}
-#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
deleted file mode 100644
index 7f2c10c7413..00000000000
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include "clk.h"
-#include "common.h"
-
-#define CCGR0                           0x68
-#define CCGR1                           0x6c
-#define CCGR2                           0x70
-#define CCGR3                           0x74
-#define CCGR4                           0x78
-#define CCGR5                           0x7c
-#define CCGR6                           0x80
-#define CCGR7                           0x84
-
-#define CLPCR                           0x54
-#define BP_CLPCR_LPM                    0
-#define BM_CLPCR_LPM                    (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
-#define BM_CLPCR_SBYOS                  (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
-#define BM_CLPCR_VSTBY                  (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT             9
-#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
-
-static void __iomem *ccm_base;
-
-void __init imx6q_clock_map_io(void) { }
-
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-        u32 val = readl_relaxed(ccm_base + CLPCR);
-
-        val &= ~BM_CLPCR_LPM;
-        switch (mode) {
-        case WAIT_CLOCKED:
-                break;
-        case WAIT_UNCLOCKED:
-                val |= 0x1 << BP_CLPCR_LPM;
-                break;
-        case STOP_POWER_ON:
-                val |= 0x2 << BP_CLPCR_LPM;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val &= ~BM_CLPCR_VSTBY;
-                val &= ~BM_CLPCR_SBYOS;
-                break;
-        case STOP_POWER_OFF:
-                val |= 0x2 << BP_CLPCR_LPM;
-                val |= 0x3 << BP_CLPCR_STBY_COUNT;
-                val |= BM_CLPCR_VSTBY;
-                val |= BM_CLPCR_SBYOS;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        writel_relaxed(val, ccm_base + CLPCR);
-
-        return 0;
-}
-
-static const char *step_sels[]  = { "osc", "pll2_pfd2_396m", };
-static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
-static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
-static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", };
-static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
-static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
-static const char *axi_sels[]           = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
-static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
-static const char *gpu_axi_sels[]       = { "axi", "ahb", };
-static const char *gpu2d_core_sels[]    = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
-static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
-static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
-static const char *ipu_sels[]           = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
-static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", };
-static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
-static const char *ipu1_di0_sels[]      = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
-static const char *ipu1_di1_sels[]      = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
-static const char *ipu2_di0_sels[]      = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
-static const char *ipu2_di1_sels[]      = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
-static const char *hsi_tx_sels[]        = { "pll3_120m", "pll2_pfd2_396m", };
-static const char *pcie_axi_sels[]      = { "axi", "ahb", };
-static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", };
-static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
-static const char *enfc_sels[]  = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
-static const char *emi_sels[]           = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
-static const char *vdo_axi_sels[]       = { "axi", "ahb", };
-static const char *vpu_axi_sels[]       = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
-static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video",
-                                    "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
-                                    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
-
-enum mx6q_clks {
-        dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
-        pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
-        pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
-        periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
-        esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
-        gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
-        ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
-        ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
-        ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
-        usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
-        emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
-        periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
-        asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
-        gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
-        ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
-        ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
-        ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
-        usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
-        emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
-        mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
-        can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
-        esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
-        hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
-        ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
-        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
-        gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
-        ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
-        usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
-        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
-        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
-        clk_max
-};
-
-static struct clk *clk[clk_max];
-static struct clk_onecell_data clk_data;
-
-static enum mx6q_clks const clks_init_on[] __initconst = {
-        mmdc_ch0_axi, rom,
-};
-
-static struct clk_div_table clk_enet_ref_table[] = {
-        { .val = 0, .div = 20, },
-        { .val = 1, .div = 10, },
-        { .val = 2, .div = 5, },
-        { .val = 3, .div = 4, },
-};
-
-int __init mx6q_clocks_init(void)
-{
-        struct device_node *np;
-        void __iomem *base;
-        int i, irq;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        clk[ckil] = imx_clk_fixed("ckil", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        clk[ckih] = imx_clk_fixed("ckih", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        clk[osc] = imx_clk_fixed("osc", rate);
-        }
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-
-        /*                   type                               name         parent_name  base     div_mask */
-        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f);
-        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1);
-        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3);
-        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f);
-        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
-        clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
-        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
-        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
-
-        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
-        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
-
-        clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
-        clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
-
-        clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
-        clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
-
-        clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
-                        base + 0xe0, 0, 2, 0, clk_enet_ref_table,
-                        &imx_ccm_lock);
-
-        /*                                name              parent_name        reg       idx */
-        clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
-        clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
-        clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
-        clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
-        clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
-        clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
-        clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
-
-        /*                                    name         parent_name     mult div */
-        clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
-        clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
-        clk[pll3_80m]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
-        clk[pll3_60m]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
-        clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        ccm_base = base;
-
-        /*                                  name                reg       shift width parent_names     num_parents */
-        clk[step]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
-        clk[pll1_sw]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
-        clk[periph_pre]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
-        clk[periph2_pre]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
-        clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
-        clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
-        clk[axi_sel]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
-        clk[esai_sel]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[asrc_sel]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[spdif_sel]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[gpu2d_axi]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[gpu3d_axi]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[gpu2d_core_sel]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
-        clk[gpu3d_core_sel]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
-        clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
-        clk[ipu1_sel]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-        clk[ipu2_sel]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-        clk[ldb_di0_sel]      = imx_clk_mux("ldb_di0_sel",      base + 0x2c, 9,  3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
-        clk[ldb_di1_sel]      = imx_clk_mux("ldb_di1_sel",      base + 0x2c, 12, 3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
-        clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
-        clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
-        clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
-        clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
-        clk[ipu1_di0_sel]     = imx_clk_mux("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels));
-        clk[ipu1_di1_sel]     = imx_clk_mux("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels));
-        clk[ipu2_di0_sel]     = imx_clk_mux("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels));
-        clk[ipu2_di1_sel]     = imx_clk_mux("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels));
-        clk[hsi_tx_sel]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
-        clk[pcie_axi_sel]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
-        clk[ssi1_sel]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clk[ssi2_sel]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clk[ssi3_sel]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clk[usdhc1_sel]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[usdhc2_sel]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[usdhc3_sel]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[usdhc4_sel]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
-        clk[emi_sel]          = imx_clk_mux("emi_sel",          base + 0x1c, 27, 2, emi_sels,          ARRAY_SIZE(emi_sels));
-        clk[emi_slow_sel]     = imx_clk_mux("emi_slow_sel",     base + 0x1c, 29, 2, emi_sels,          ARRAY_SIZE(emi_sels));
-        clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
-        clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
-        clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
-
-        /*                              name         reg      shift width busy: reg, shift parent_names  num_parents */
-        clk[periph]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
-        clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
-
-        /*                                      name                parent_name          reg       shift width */
-        clk[periph_clk2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
-        clk[periph2_clk2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
-        clk[ipg]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
-        clk[ipg_per]          = imx_clk_divider("ipg_per",          "ipg",               base + 0x1c, 0,  6);
-        clk[esai_pred]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
-        clk[esai_podf]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
-        clk[asrc_pred]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
-        clk[asrc_podf]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
-        clk[spdif_pred]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
-        clk[spdif_podf]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
-        clk[can_root]         = imx_clk_divider("can_root",         "pll3_usb_otg",      base + 0x20, 2,  6);
-        clk[ecspi_root]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
-        clk[gpu2d_core_podf]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
-        clk[gpu3d_core_podf]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
-        clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
-        clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
-        clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
-        clk[ldb_di0_div_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
-        clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_div_3_5",       base + 0x20, 10, 1);
-        clk[ldb_di1_div_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
-        clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_div_3_5",   base + 0x20, 11, 1);
-        clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
-        clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
-        clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
-        clk[ipu2_di1_pre]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
-        clk[hsi_tx_podf]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
-        clk[ssi1_pred]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
-        clk[ssi1_podf]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
-        clk[ssi2_pred]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
-        clk[ssi2_podf]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
-        clk[ssi3_pred]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
-        clk[ssi3_podf]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
-        clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
-        clk[usdhc1_podf]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
-        clk[usdhc2_podf]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
-        clk[usdhc3_podf]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
-        clk[usdhc4_podf]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
-        clk[enfc_pred]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
-        clk[enfc_podf]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
-        clk[emi_podf]         = imx_clk_divider("emi_podf",         "emi_sel",           base + 0x1c, 20, 3);
-        clk[emi_slow_podf]    = imx_clk_divider("emi_slow_podf",    "emi_slow_sel",      base + 0x1c, 23, 3);
-        clk[vpu_axi_podf]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
-        clk[cko1_podf]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
-
-        /*                                            name                 parent_name    reg        shift width busy: reg, shift */
-        clk[axi]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
-        clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
-        clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
-        clk[arm]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
-        clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
-
-        /*                                name             parent_name          reg         shift */
-        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
-        clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
-        clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
-        clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
-        clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
-        clk[can2_serial]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
-        clk[ecspi1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
-        clk[ecspi2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
-        clk[ecspi3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
-        clk[ecspi4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
-        clk[ecspi5]       = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
-        clk[enet]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
-        clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
-        clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
-        clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
-        clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
-        clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
-        clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
-        clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
-        clk[i2c1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
-        clk[i2c2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
-        clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
-        clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
-        clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
-        clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
-        clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
-        clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
-        clk[ipu2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
-        clk[ipu2_di0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
-        clk[ldb_di0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
-        clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
-        clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
-        clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "pll8_mlb",          base + 0x74, 18);
-        clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
-        clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
-        clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
-        clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
-        clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
-        clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
-        clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
-        clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
-        clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
-        clk[pwm4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
-        clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
-        clk[gpmi_bch]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
-        clk[gpmi_io]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
-        clk[gpmi_apb]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
-        clk[rom]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);
-        clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
-        clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
-        clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-        clk[ssi1_ipg]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
-        clk[ssi2_ipg]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
-        clk[ssi3_ipg]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
-        clk[uart_ipg]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
-        clk[uart_serial]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
-        clk[usboh3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
-        clk[usdhc1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
-        clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
-        clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
-        clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
-        clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
-        clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
-        clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX6q clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_data.clks = clk;
-        clk_data.clk_num = ARRAY_SIZE(clk);
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
-        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[twd], NULL, "smp_twd");
-        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
-        clk_register_clkdev(clk[ahb], "ahb", NULL);
-        clk_register_clkdev(clk[cko1], "cko1", NULL);
-        clk_register_clkdev(clk[arm], NULL, "cpu0");
-
-        /*
-         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
-         * We can not get the 100MHz from the pll2_pfd0_352m.
-         * So choose pll2_pfd2_396m as enfc_sel's parent.
-         */
-        clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
-
-        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-                clk_prepare_enable(clk[clks_init_on[i]]);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(base, irq);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
deleted file mode 100644
index e2ed4160f32..00000000000
--- a/arch/arm/mach-imx/clk-pfd.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include "clk.h"
-
-/**
- * struct clk_pfd - IMX PFD clock
- * @clk_hw:     clock source
- * @reg:        PFD register address
- * @idx:        the index of PFD encoded in the register
- *
- * PFD clock found on i.MX6 series.  Each register for PFD has 4 clk_pfd
- * data encoded, and member idx is used to specify the one.  And each
- * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
- */
-struct clk_pfd {
-        struct clk_hw   hw;
-        void __iomem    *reg;
-        u8              idx;
-};
-
-#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
-
-#define SET     0x4
-#define CLR     0x8
-#define OTG     0xc
-
-static int clk_pfd_enable(struct clk_hw *hw)
-{
-        struct clk_pfd *pfd = to_clk_pfd(hw);
-
-        writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
-
-        return 0;
-}
-
-static void clk_pfd_disable(struct clk_hw *hw)
-{
-        struct clk_pfd *pfd = to_clk_pfd(hw);
-
-        writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
-}
-
-static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
-                                         unsigned long parent_rate)
-{
-        struct clk_pfd *pfd = to_clk_pfd(hw);
-        u64 tmp = parent_rate;
-        u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
-
-        tmp *= 18;
-        do_div(tmp, frac);
-
-        return tmp;
-}
-
-static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
-                               unsigned long *prate)
-{
-        u64 tmp = *prate;
-        u8 frac;
-
-        tmp = tmp * 18 + rate / 2;
-        do_div(tmp, rate);
-        frac = tmp;
-        if (frac < 12)
-                frac = 12;
-        else if (frac > 35)
-                frac = 35;
-        tmp = *prate;
-        tmp *= 18;
-        do_div(tmp, frac);
-
-        return tmp;
-}
-
-static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pfd *pfd = to_clk_pfd(hw);
-        u64 tmp = parent_rate;
-        u8 frac;
-
-        tmp = tmp * 18 + rate / 2;
-        do_div(tmp, rate);
-        frac = tmp;
-        if (frac < 12)
-                frac = 12;
-        else if (frac > 35)
-                frac = 35;
-
-        writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
-        writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
-
-        return 0;
-}
-
-static const struct clk_ops clk_pfd_ops = {
-        .enable         = clk_pfd_enable,
-        .disable        = clk_pfd_disable,
-        .recalc_rate    = clk_pfd_recalc_rate,
-        .round_rate     = clk_pfd_round_rate,
-        .set_rate       = clk_pfd_set_rate,
-};
-
-struct clk *imx_clk_pfd(const char *name, const char *parent_name,
-                        void __iomem *reg, u8 idx)
-{
-        struct clk_pfd *pfd;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
-        if (!pfd)
-                return ERR_PTR(-ENOMEM);
-
-        pfd->reg = reg;
-        pfd->idx = idx;
-
-        init.name = name;
-        init.ops = &clk_pfd_ops;
-        init.flags = 0;
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-
-        pfd->hw.init = &init;
-
-        clk = clk_register(NULL, &pfd->hw);
-        if (IS_ERR(clk))
-                kfree(pfd);
-
-        return clk;
-}
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
deleted file mode 100644
index abff350ba24..00000000000
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ /dev/null
@@ -1,111 +0,0 @@
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-
-#include "clk.h"
-#include "common.h"
-#include "hardware.h"
-
-/**
- * pll v1
- *
- * @clk_hw      clock source
- * @parent      the parent clock name
- * @base        base address of pll registers
- *
- * PLL clock version 1, found on i.MX1/21/25/27/31/35
- */
-struct clk_pllv1 {
-        struct clk_hw   hw;
-        void __iomem    *base;
-};
-
-#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
-
-static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_pllv1 *pll = to_clk_pllv1(hw);
-        long long ll;
-        int mfn_abs;
-        unsigned int mfi, mfn, mfd, pd;
-        u32 reg;
-        unsigned long rate;
-
-        reg = readl(pll->base);
-
-        /*
-         * Get the resulting clock rate from a PLL register value and the input
-         * frequency. PLLs with this register layout can be found on i.MX1,
-         * i.MX21, i.MX27 and i,MX31
-         *
-         *                  mfi + mfn / (mfd + 1)
-         *  f = 2 * f_ref * --------------------
-         *                        pd + 1
-         */
-
-        mfi = (reg >> 10) & 0xf;
-        mfn = reg & 0x3ff;
-        mfd = (reg >> 16) & 0x3ff;
-        pd =  (reg >> 26) & 0xf;
-
-        mfi = mfi <= 5 ? 5 : mfi;
-
-        mfn_abs = mfn;
-
-        /*
-         * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-         * 2's complements number
-         */
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                mfn_abs = 0x400 - mfn;
-
-        rate = parent_rate * 2;
-        rate /= pd + 1;
-
-        ll = (unsigned long long)rate * mfn_abs;
-
-        do_div(ll, mfd + 1);
-
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                ll = -ll;
-
-        ll = (rate * mfi) + ll;
-
-        return ll;
-}
-
-struct clk_ops clk_pllv1_ops = {
-        .recalc_rate = clk_pllv1_recalc_rate,
-};
-
-struct clk *imx_clk_pllv1(const char *name, const char *parent,
-                void __iomem *base)
-{
-        struct clk_pllv1 *pll;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        pll = kmalloc(sizeof(*pll), GFP_KERNEL);
-        if (!pll)
-                return ERR_PTR(-ENOMEM);
-
-        pll->base = base;
-
-        init.name = name;
-        init.ops = &clk_pllv1_ops;
-        init.flags = 0;
-        init.parent_names = &parent;
-        init.num_parents = 1;
-
-        pll->hw.init = &init;
-
-        clk = clk_register(NULL, &pll->hw);
-        if (IS_ERR(clk))
-                kfree(pll);
-
-        return clk;
-}
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
deleted file mode 100644
index 0440379e362..00000000000
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ /dev/null
@@ -1,266 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-
-#include <asm/div64.h>
-
-#include "clk.h"
-
-#define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL                  0x00
-#define MXC_PLL_DP_CONFIG               0x04
-#define MXC_PLL_DP_OP                   0x08
-#define MXC_PLL_DP_MFD                  0x0C
-#define MXC_PLL_DP_MFN                  0x10
-#define MXC_PLL_DP_MFNMINUS             0x14
-#define MXC_PLL_DP_MFNPLUS              0x18
-#define MXC_PLL_DP_HFS_OP               0x1C
-#define MXC_PLL_DP_HFS_MFD              0x20
-#define MXC_PLL_DP_HFS_MFN              0x24
-#define MXC_PLL_DP_MFN_TOGC             0x28
-#define MXC_PLL_DP_DESTAT               0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL         0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET  12
-#define MXC_PLL_DP_CTL_ADE              0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET       8
-#define MXC_PLL_DP_CTL_HFSM             0x80
-#define MXC_PLL_DP_CTL_PRE              0x40
-#define MXC_PLL_DP_CTL_UPEN             0x20
-#define MXC_PLL_DP_CTL_RST              0x10
-#define MXC_PLL_DP_CTL_RCP              0x8
-#define MXC_PLL_DP_CTL_PLM              0x4
-#define MXC_PLL_DP_CTL_BRM0             0x2
-#define MXC_PLL_DP_CTL_LRF              0x1
-
-#define MXC_PLL_DP_CONFIG_BIST          0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE        0x4
-#define MXC_PLL_DP_CONFIG_AREN          0x2
-#define MXC_PLL_DP_CONFIG_LDREQ         0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET        4
-#define MXC_PLL_DP_OP_MFI_MASK          (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET        0
-#define MXC_PLL_DP_OP_PDF_MASK          0xF
-
-#define MXC_PLL_DP_MFD_OFFSET           0
-#define MXC_PLL_DP_MFD_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET           0x0
-#define MXC_PLL_DP_MFN_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS     (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN      (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET  0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK    0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL       (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN           0x07FFFFFF
-
-#define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
-
-struct clk_pllv2 {
-        struct clk_hw   hw;
-        void __iomem    *base;
-};
-
-static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
-                u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
-{
-        long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
-        unsigned long dbl;
-        s64 temp;
-
-        dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
-        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
-        mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
-        mfi = (mfi <= 5) ? 5 : mfi;
-        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
-        mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
-        /* Sign extend to 32-bits */
-        if (mfn >= 0x04000000) {
-                mfn |= 0xFC000000;
-                mfn_abs = -mfn;
-        }
-
-        ref_clk = 2 * parent_rate;
-        if (dbl != 0)
-                ref_clk *= 2;
-
-        ref_clk /= (pdf + 1);
-        temp = (u64) ref_clk * mfn_abs;
-        do_div(temp, mfd + 1);
-        if (mfn < 0)
-                temp = -temp;
-        temp = (ref_clk * mfi) + temp;
-
-        return temp;
-}
-
-static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
-        void __iomem *pllbase;
-        struct clk_pllv2 *pll = to_clk_pllv2(hw);
-
-        pllbase = pll->base;
-
-        dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-        dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
-        dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
-        dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
-
-        return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
-}
-
-static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
-                u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
-{
-        u32 reg;
-        long mfi, pdf, mfn, mfd = 999999;
-        s64 temp64;
-        unsigned long quad_parent_rate;
-
-        quad_parent_rate = 4 * parent_rate;
-        pdf = mfi = -1;
-        while (++pdf < 16 && mfi < 5)
-                mfi = rate * (pdf+1) / quad_parent_rate;
-        if (mfi > 15)
-                return -EINVAL;
-        pdf--;
-
-        temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
-        do_div(temp64, quad_parent_rate / 1000000);
-        mfn = (long)temp64;
-
-        reg = mfi << 4 | pdf;
-
-        *dp_op = reg;
-        *dp_mfd = mfd;
-        *dp_mfn = mfn;
-
-        return 0;
-}
-
-static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv2 *pll = to_clk_pllv2(hw);
-        void __iomem *pllbase;
-        u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
-        int ret;
-
-        pllbase = pll->base;
-
-
-        ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
-        if (ret)
-                return ret;
-
-        dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-        /* use dpdck0_2 */
-        __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
-
-        __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
-        __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
-        __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
-
-        return 0;
-}
-
-static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *prate)
-{
-        u32 dp_op, dp_mfd, dp_mfn;
-
-        __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
-        return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
-                        dp_op, dp_mfd, dp_mfn);
-}
-
-static int clk_pllv2_prepare(struct clk_hw *hw)
-{
-        struct clk_pllv2 *pll = to_clk_pllv2(hw);
-        u32 reg;
-        void __iomem *pllbase;
-        int i = 0;
-
-        pllbase = pll->base;
-        reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
-        __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-
-        /* Wait for lock */
-        do {
-                reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-                if (reg & MXC_PLL_DP_CTL_LRF)
-                        break;
-
-                udelay(1);
-        } while (++i < MAX_DPLL_WAIT_TRIES);
-
-        if (i == MAX_DPLL_WAIT_TRIES) {
-                pr_err("MX5: pll locking failed\n");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static void clk_pllv2_unprepare(struct clk_hw *hw)
-{
-        struct clk_pllv2 *pll = to_clk_pllv2(hw);
-        u32 reg;
-        void __iomem *pllbase;
-
-        pllbase = pll->base;
-        reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
-        __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-}
-
-struct clk_ops clk_pllv2_ops = {
-        .prepare = clk_pllv2_prepare,
-        .unprepare = clk_pllv2_unprepare,
-        .recalc_rate = clk_pllv2_recalc_rate,
-        .round_rate = clk_pllv2_round_rate,
-        .set_rate = clk_pllv2_set_rate,
-};
-
-struct clk *imx_clk_pllv2(const char *name, const char *parent,
-                void __iomem *base)
-{
-        struct clk_pllv2 *pll;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-        if (!pll)
-                return ERR_PTR(-ENOMEM);
-
-        pll->base = base;
-
-        init.name = name;
-        init.ops = &clk_pllv2_ops;
-        init.flags = 0;
-        init.parent_names = &parent;
-        init.num_parents = 1;
-
-        pll->hw.init = &init;
-
-        clk = clk_register(NULL, &pll->hw);
-        if (IS_ERR(clk))
-                kfree(pll);
-
-        return clk;
-}
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
deleted file mode 100644
index d09bc3df9a7..00000000000
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/jiffies.h>
-#include <linux/err.h>
-#include "clk.h"
-
-#define PLL_NUM_OFFSET          0x10
-#define PLL_DENOM_OFFSET        0x20
-
-#define BM_PLL_POWER            (0x1 << 12)
-#define BM_PLL_ENABLE           (0x1 << 13)
-#define BM_PLL_BYPASS           (0x1 << 16)
-#define BM_PLL_LOCK             (0x1 << 31)
-
-/**
- * struct clk_pllv3 - IMX PLL clock version 3
- * @clk_hw:      clock source
- * @base:        base address of PLL registers
- * @powerup_set: set POWER bit to power up the PLL
- * @div_mask:    mask of divider bits
- *
- * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
- * is actually a multiplier, and always sits at bit 0.
- */
-struct clk_pllv3 {
-        struct clk_hw   hw;
-        void __iomem    *base;
-        bool            powerup_set;
-        u32             div_mask;
-};
-
-#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
-
-static int clk_pllv3_prepare(struct clk_hw *hw)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        unsigned long timeout = jiffies + msecs_to_jiffies(10);
-        u32 val;
-
-        val = readl_relaxed(pll->base);
-        val &= ~BM_PLL_BYPASS;
-        if (pll->powerup_set)
-                val |= BM_PLL_POWER;
-        else
-                val &= ~BM_PLL_POWER;
-        writel_relaxed(val, pll->base);
-
-        /* Wait for PLL to lock */
-        while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
-                if (time_after(jiffies, timeout))
-                        return -ETIMEDOUT;
-
-        return 0;
-}
-
-static void clk_pllv3_unprepare(struct clk_hw *hw)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val;
-
-        val = readl_relaxed(pll->base);
-        val |= BM_PLL_BYPASS;
-        if (pll->powerup_set)
-                val &= ~BM_PLL_POWER;
-        else
-                val |= BM_PLL_POWER;
-        writel_relaxed(val, pll->base);
-}
-
-static int clk_pllv3_enable(struct clk_hw *hw)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val;
-
-        val = readl_relaxed(pll->base);
-        val |= BM_PLL_ENABLE;
-        writel_relaxed(val, pll->base);
-
-        return 0;
-}
-
-static void clk_pllv3_disable(struct clk_hw *hw)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val;
-
-        val = readl_relaxed(pll->base);
-        val &= ~BM_PLL_ENABLE;
-        writel_relaxed(val, pll->base);
-}
-
-static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
-                                           unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 div = readl_relaxed(pll->base)  & pll->div_mask;
-
-        return (div == 1) ? parent_rate * 22 : parent_rate * 20;
-}
-
-static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
-                                 unsigned long *prate)
-{
-        unsigned long parent_rate = *prate;
-
-        return (rate >= parent_rate * 22) ? parent_rate * 22 :
-                                            parent_rate * 20;
-}
-
-static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val, div;
-
-        if (rate == parent_rate * 22)
-                div = 1;
-        else if (rate == parent_rate * 20)
-                div = 0;
-        else
-                return -EINVAL;
-
-        val = readl_relaxed(pll->base);
-        val &= ~pll->div_mask;
-        val |= div;
-        writel_relaxed(val, pll->base);
-
-        return 0;
-}
-
-static const struct clk_ops clk_pllv3_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-        .recalc_rate    = clk_pllv3_recalc_rate,
-        .round_rate     = clk_pllv3_round_rate,
-        .set_rate       = clk_pllv3_set_rate,
-};
-
-static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
-                                               unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 div = readl_relaxed(pll->base) & pll->div_mask;
-
-        return parent_rate * div / 2;
-}
-
-static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
-                                     unsigned long *prate)
-{
-        unsigned long parent_rate = *prate;
-        unsigned long min_rate = parent_rate * 54 / 2;
-        unsigned long max_rate = parent_rate * 108 / 2;
-        u32 div;
-
-        if (rate > max_rate)
-                rate = max_rate;
-        else if (rate < min_rate)
-                rate = min_rate;
-        div = rate * 2 / parent_rate;
-
-        return parent_rate * div / 2;
-}
-
-static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        unsigned long min_rate = parent_rate * 54 / 2;
-        unsigned long max_rate = parent_rate * 108 / 2;
-        u32 val, div;
-
-        if (rate < min_rate || rate > max_rate)
-                return -EINVAL;
-
-        div = rate * 2 / parent_rate;
-        val = readl_relaxed(pll->base);
-        val &= ~pll->div_mask;
-        val |= div;
-        writel_relaxed(val, pll->base);
-
-        return 0;
-}
-
-static const struct clk_ops clk_pllv3_sys_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-        .recalc_rate    = clk_pllv3_sys_recalc_rate,
-        .round_rate     = clk_pllv3_sys_round_rate,
-        .set_rate       = clk_pllv3_sys_set_rate,
-};
-
-static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
-                                              unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
-        u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
-        u32 div = readl_relaxed(pll->base) & pll->div_mask;
-
-        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
-}
-
-static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
-                                    unsigned long *prate)
-{
-        unsigned long parent_rate = *prate;
-        unsigned long min_rate = parent_rate * 27;
-        unsigned long max_rate = parent_rate * 54;
-        u32 div;
-        u32 mfn, mfd = 1000000;
-        s64 temp64;
-
-        if (rate > max_rate)
-                rate = max_rate;
-        else if (rate < min_rate)
-                rate = min_rate;
-
-        div = rate / parent_rate;
-        temp64 = (u64) (rate - div * parent_rate);
-        temp64 *= mfd;
-        do_div(temp64, parent_rate);
-        mfn = temp64;
-
-        return parent_rate * div + parent_rate / mfd * mfn;
-}
-
-static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        unsigned long min_rate = parent_rate * 27;
-        unsigned long max_rate = parent_rate * 54;
-        u32 val, div;
-        u32 mfn, mfd = 1000000;
-        s64 temp64;
-
-        if (rate < min_rate || rate > max_rate)
-                return -EINVAL;
-
-        div = rate / parent_rate;
-        temp64 = (u64) (rate - div * parent_rate);
-        temp64 *= mfd;
-        do_div(temp64, parent_rate);
-        mfn = temp64;
-
-        val = readl_relaxed(pll->base);
-        val &= ~pll->div_mask;
-        val |= div;
-        writel_relaxed(val, pll->base);
-        writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
-        writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
-
-        return 0;
-}
-
-static const struct clk_ops clk_pllv3_av_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-        .recalc_rate    = clk_pllv3_av_recalc_rate,
-        .round_rate     = clk_pllv3_av_round_rate,
-        .set_rate       = clk_pllv3_av_set_rate,
-};
-
-static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
-                                                unsigned long parent_rate)
-{
-        return 500000000;
-}
-
-static const struct clk_ops clk_pllv3_enet_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-        .recalc_rate    = clk_pllv3_enet_recalc_rate,
-};
-
-static const struct clk_ops clk_pllv3_mlb_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-};
-
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-                          const char *parent_name, void __iomem *base,
-                          u32 div_mask)
-{
-        struct clk_pllv3 *pll;
-        const struct clk_ops *ops;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-        if (!pll)
-                return ERR_PTR(-ENOMEM);
-
-        switch (type) {
-        case IMX_PLLV3_SYS:
-                ops = &clk_pllv3_sys_ops;
-                break;
-        case IMX_PLLV3_USB:
-                ops = &clk_pllv3_ops;
-                pll->powerup_set = true;
-                break;
-        case IMX_PLLV3_AV:
-                ops = &clk_pllv3_av_ops;
-                break;
-        case IMX_PLLV3_ENET:
-                ops = &clk_pllv3_enet_ops;
-                break;
-        case IMX_PLLV3_MLB:
-                ops = &clk_pllv3_mlb_ops;
-                break;
-        default:
-                ops = &clk_pllv3_ops;
-        }
-        pll->base = base;
-        pll->div_mask = div_mask;
-
-        init.name = name;
-        init.ops = ops;
-        init.flags = 0;
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-
-        pll->hw.init = &init;
-
-        clk = clk_register(NULL, &pll->hw);
-        if (IS_ERR(clk))
-                kfree(pll);
-
-        return clk;
-}
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
deleted file mode 100644
index f5e8be8e7f1..00000000000
--- a/arch/arm/mach-imx/clk.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#include <linux/spinlock.h>
-
-DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
deleted file mode 100644
index 9d1f3b99d1d..00000000000
--- a/arch/arm/mach-imx/clk.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef __MACH_IMX_CLK_H
-#define __MACH_IMX_CLK_H
-
-#include <linux/spinlock.h>
-#include <linux/clk-provider.h>
-
-extern spinlock_t imx_ccm_lock;
-
-struct clk *imx_clk_pllv1(const char *name, const char *parent,
-                void __iomem *base);
-
-struct clk *imx_clk_pllv2(const char *name, const char *parent,
-                void __iomem *base);
-
-enum imx_pllv3_type {
-        IMX_PLLV3_GENERIC,
-        IMX_PLLV3_SYS,
-        IMX_PLLV3_USB,
-        IMX_PLLV3_AV,
-        IMX_PLLV3_ENET,
-        IMX_PLLV3_MLB,
-};
-
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-                const char *parent_name, void __iomem *base, u32 div_mask);
-
-struct clk *clk_register_gate2(struct device *dev, const char *name,
-                const char *parent_name, unsigned long flags,
-                void __iomem *reg, u8 bit_idx,
-                u8 clk_gate_flags, spinlock_t *lock);
-
-static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
-                void __iomem *reg, u8 shift)
-{
-        return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
-                        shift, 0, &imx_ccm_lock);
-}
-
-struct clk *imx_clk_pfd(const char *name, const char *parent_name,
-                void __iomem *reg, u8 idx);
-
-struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
-                                 void __iomem *reg, u8 shift, u8 width,
-                                 void __iomem *busy_reg, u8 busy_shift);
-
-struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
-                             u8 width, void __iomem *busy_reg, u8 busy_shift,
-                             const char **parent_names, int num_parents);
-
-static inline struct clk *imx_clk_fixed(const char *name, int rate)
-{
-        return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
-}
-
-static inline struct clk *imx_clk_divider(const char *name, const char *parent,
-                void __iomem *reg, u8 shift, u8 width)
-{
-        return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
-                        reg, shift, width, 0, &imx_ccm_lock);
-}
-
-static inline struct clk *imx_clk_gate(const char *name, const char *parent,
-                void __iomem *reg, u8 shift)
-{
-        return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
-                        shift, 0, &imx_ccm_lock);
-}
-
-static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
-                u8 shift, u8 width, const char **parents, int num_parents)
-{
-        return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
-                        width, 0, &imx_ccm_lock);
-}
-
-static inline struct clk *imx_clk_fixed_factor(const char *name,
-                const char *parent, unsigned int mult, unsigned int div)
-{
-        return clk_register_fixed_factor(NULL, name, parent,
-                        CLK_SET_RATE_PARENT, mult, div);
-}
-
-#endif
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
deleted file mode 100644
index 7191ab4434e..00000000000
--- a/arch/arm/mach-imx/common.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_COMMON_H__
-#define __ASM_ARCH_MXC_COMMON_H__
-
-struct platform_device;
-struct clk;
-enum mxc_cpu_pwr_mode;
-
-extern void mx1_map_io(void);
-extern void mx21_map_io(void);
-extern void mx25_map_io(void);
-extern void mx27_map_io(void);
-extern void mx31_map_io(void);
-extern void mx35_map_io(void);
-extern void mx50_map_io(void);
-extern void mx51_map_io(void);
-extern void mx53_map_io(void);
-extern void imx1_init_early(void);
-extern void imx21_init_early(void);
-extern void imx25_init_early(void);
-extern void imx27_init_early(void);
-extern void imx31_init_early(void);
-extern void imx35_init_early(void);
-extern void imx50_init_early(void);
-extern void imx51_init_early(void);
-extern void imx53_init_early(void);
-extern void mxc_init_irq(void __iomem *);
-extern void tzic_init_irq(void __iomem *);
-extern void mx1_init_irq(void);
-extern void mx21_init_irq(void);
-extern void mx25_init_irq(void);
-extern void mx27_init_irq(void);
-extern void mx31_init_irq(void);
-extern void mx35_init_irq(void);
-extern void mx50_init_irq(void);
-extern void mx51_init_irq(void);
-extern void mx53_init_irq(void);
-extern void imx1_soc_init(void);
-extern void imx21_soc_init(void);
-extern void imx25_soc_init(void);
-extern void imx27_soc_init(void);
-extern void imx31_soc_init(void);
-extern void imx35_soc_init(void);
-extern void imx50_soc_init(void);
-extern void imx51_soc_init(void);
-extern void imx51_init_late(void);
-extern void imx53_init_late(void);
-extern void epit_timer_init(void __iomem *base, int irq);
-extern void mxc_timer_init(void __iomem *, int);
-extern int mx1_clocks_init(unsigned long fref);
-extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
-extern int mx25_clocks_init(void);
-extern int mx27_clocks_init(unsigned long fref);
-extern int mx31_clocks_init(unsigned long fref);
-extern int mx35_clocks_init(void);
-extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
-                        unsigned long ckih1, unsigned long ckih2);
-extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
-                        unsigned long ckih1, unsigned long ckih2);
-extern int mx25_clocks_init_dt(void);
-extern int mx27_clocks_init_dt(void);
-extern int mx31_clocks_init_dt(void);
-extern int mx51_clocks_init_dt(void);
-extern int mx53_clocks_init_dt(void);
-extern int mx6q_clocks_init(void);
-extern struct platform_device *mxc_register_gpio(char *name, int id,
-        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
-extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
-extern void mxc_arch_reset_init(void __iomem *);
-extern int mx53_revision(void);
-extern int mx53_display_revision(void);
-extern void imx_set_aips(void __iomem *);
-extern int mxc_device_init(void);
-
-enum mxc_cpu_pwr_mode {
-        WAIT_CLOCKED,           /* wfi only */
-        WAIT_UNCLOCKED,         /* WAIT */
-        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
-        STOP_POWER_ON,          /* just STOP */
-        STOP_POWER_OFF,         /* STOP + SRPG */
-};
-
-enum mx3_cpu_pwr_mode {
-        MX3_RUN,
-        MX3_WAIT,
-        MX3_DOZE,
-        MX3_SLEEP,
-};
-
-extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
-extern void imx_print_silicon_rev(const char *cpu, int srev);
-
-void avic_handle_irq(struct pt_regs *);
-void tzic_handle_irq(struct pt_regs *);
-
-#define imx1_handle_irq avic_handle_irq
-#define imx21_handle_irq avic_handle_irq
-#define imx25_handle_irq avic_handle_irq
-#define imx27_handle_irq avic_handle_irq
-#define imx31_handle_irq avic_handle_irq
-#define imx35_handle_irq avic_handle_irq
-#define imx50_handle_irq tzic_handle_irq
-#define imx51_handle_irq tzic_handle_irq
-#define imx53_handle_irq tzic_handle_irq
-#define imx6q_handle_irq gic_handle_irq
-
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
-#ifdef CONFIG_DEBUG_LL
-extern void imx_lluart_map_io(void);
-#else
-static inline void imx_lluart_map_io(void) {}
-#endif
-extern void v7_cpu_resume(void);
-extern u32 *pl310_get_save_ptr(void);
-#ifdef CONFIG_SMP
-extern void v7_secondary_startup(void);
-extern void imx_scu_map_io(void);
-extern void imx_smp_prepare(void);
-#else
-static inline void imx_scu_map_io(void) {}
-static inline void imx_smp_prepare(void) {}
-#endif
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
-extern void imx_src_init(void);
-extern void imx_src_prepare_restart(void);
-extern void imx_gpc_init(void);
-extern void imx_gpc_pre_suspend(void);
-extern void imx_gpc_post_resume(void);
-extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-extern void imx6q_clock_map_io(void);
-
-extern void imx_cpu_die(unsigned int cpu);
-
-#ifdef CONFIG_PM
-extern void imx6q_pm_init(void);
-extern void imx51_pm_init(void);
-extern void imx53_pm_init(void);
-#else
-static inline void imx6q_pm_init(void) {}
-static inline void imx51_pm_init(void) {}
-static inline void imx53_pm_init(void) {}
-#endif
-
-#ifdef CONFIG_NEON
-extern int mx51_neon_fixup(void);
-#else
-static inline int mx51_neon_fixup(void) { return 0; }
-#endif
-
-extern struct smp_operations imx_smp_ops;
-
-#endif
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
deleted file mode 100644
index 96ec64b5ff7..00000000000
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * MX25 CPU type detection
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include "iim.h"
-#include "hardware.h"
-
-static int mx25_cpu_rev = -1;
-
-static int mx25_read_cpu_rev(void)
-{
-        u32 rev;
-
-        rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
-        switch (rev) {
-        case 0x00:
-                return IMX_CHIP_REVISION_1_0;
-        case 0x01:
-                return IMX_CHIP_REVISION_1_1;
-        default:
-                return IMX_CHIP_REVISION_UNKNOWN;
-        }
-}
-
-int mx25_revision(void)
-{
-        if (mx25_cpu_rev == -1)
-                mx25_cpu_rev = mx25_read_cpu_rev();
-
-        return mx25_cpu_rev;
-}
-EXPORT_SYMBOL(mx25_revision);
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index fe8d36f7e30..3b117be37bd 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -24,14 +24,14 @@
 #include <linux/io.h>
 #include <linux/module.h>
 
-#include "hardware.h"
+#include <mach/hardware.h>
 
-static int mx27_cpu_rev = -1;
-static int mx27_cpu_partnumber;
+static int cpu_silicon_rev = -1;
+static int cpu_partnumber;
 
 #define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
 
-static int mx27_read_cpu_rev(void)
+static void query_silicon_parameter(void)
 {
         u32 val;
         /*
@@ -42,18 +42,20 @@ static int mx27_read_cpu_rev(void)
         val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
                                 + SYS_CHIP_ID));
 
-        mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
-
         switch (val >> 28) {
         case 0:
-                return IMX_CHIP_REVISION_1_0;
+                cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
+                break;
         case 1:
-                return IMX_CHIP_REVISION_2_0;
+                cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
+                break;
         case 2:
-                return IMX_CHIP_REVISION_2_1;
+                cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
+                break;
         default:
-                return IMX_CHIP_REVISION_UNKNOWN;
+                cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
         }
+        cpu_partnumber = (int)((val >> 12) & 0xFFFF);
 }
 
 /*
@@ -63,12 +65,12 @@ static int mx27_read_cpu_rev(void)
  */
 int mx27_revision(void)
 {
-        if (mx27_cpu_rev == -1)
-                mx27_cpu_rev = mx27_read_cpu_rev();
+        if (cpu_silicon_rev == -1)
+                query_silicon_parameter();
 
-        if (mx27_cpu_partnumber != 0x8821)
+        if (cpu_partnumber != 0x8821)
                 return -EINVAL;
 
-        return mx27_cpu_rev;
+        return cpu_silicon_rev;
 }
 EXPORT_SYMBOL(mx27_revision);
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index fde1860a252..a3780700a88 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -11,53 +11,47 @@
 
 #include <linux/module.h>
 #include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
 
-#include "common.h"
-#include "hardware.h"
-#include "iim.h"
-
-static int mx31_cpu_rev = -1;
+unsigned int mx31_cpu_rev;
+EXPORT_SYMBOL(mx31_cpu_rev);
 
 static struct {
         u8 srev;
         const char *name;
+        const char *v;
         unsigned int rev;
-} mx31_cpu_type[] = {
-        { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
-        { .srev = 0x10, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x11, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x12, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x13, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
-        { .srev = 0x14, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_2 },
-        { .srev = 0x15, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_2 },
-        { .srev = 0x28, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_2_0 },
-        { .srev = 0x29, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_2_0 },
+} mx31_cpu_type[] __initdata = {
+        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0  },
+        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
+        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
 };
 
-static int mx31_read_cpu_rev(void)
+void __init mx31_read_cpu_rev(void)
 {
         u32 i, srev;
 
         /* read SREV register from IIM module */
         srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
-        srev &= 0xff;
 
         for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
                 if (srev == mx31_cpu_type[i].srev) {
-                        imx_print_silicon_rev(mx31_cpu_type[i].name,
-                                                mx31_cpu_type[i].rev);
-                        return mx31_cpu_type[i].rev;
-                }
+                        printk(KERN_INFO
+                                "CPU identified as %s, silicon rev %s\n",
+                                mx31_cpu_type[i].name, mx31_cpu_type[i].v);
 
-        imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
-        return IMX_CHIP_REVISION_UNKNOWN;
-}
+                        mx31_cpu_rev = mx31_cpu_type[i].rev;
+                        return;
+                }
 
-int mx31_revision(void)
-{
-        if (mx31_cpu_rev == -1)
-                mx31_cpu_rev = mx31_read_cpu_rev();
+        mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
 
-        return mx31_cpu_rev;
+        printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
-EXPORT_SYMBOL(mx31_revision);
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index ec3aaa098c1..6637cd819ec 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -10,34 +10,35 @@
  */
 #include <linux/module.h>
 #include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
 
-#include "hardware.h"
-#include "iim.h"
+unsigned int mx35_cpu_rev;
+EXPORT_SYMBOL(mx35_cpu_rev);
 
-static int mx35_cpu_rev = -1;
-
-static int mx35_read_cpu_rev(void)
+void __init mx35_read_cpu_rev(void)
 {
         u32 rev;
+        char *srev;
 
         rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
         switch (rev) {
         case 0x00:
-                return IMX_CHIP_REVISION_1_0;
+                mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
+                srev = "1.0";
+                break;
         case 0x10:
-                return IMX_CHIP_REVISION_2_0;
+                mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
+                srev = "2.0";
+                break;
         case 0x11:
-                return IMX_CHIP_REVISION_2_1;
+                mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
+                srev = "2.1";
+                break;
         default:
-                return IMX_CHIP_REVISION_UNKNOWN;
+                mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+                srev = "unknown";
         }
-}
-
-int mx35_revision(void)
-{
-        if (mx35_cpu_rev == -1)
-                mx35_cpu_rev = mx35_read_cpu_rev();
 
-        return mx35_cpu_rev;
+        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
 }
-EXPORT_SYMBOL(mx35_revision);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
deleted file mode 100644
index d88760014ff..00000000000
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * This file contains the CPU initialization code.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include "hardware.h"
-
-static int mx5_cpu_rev = -1;
-
-#define IIM_SREV 0x24
-#define MX50_HW_ADADIG_DIGPROG  0xB0
-
-static int get_mx51_srev(void)
-{
-        void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
-        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
-
-        switch (rev) {
-        case 0x0:
-                return IMX_CHIP_REVISION_2_0;
-        case 0x10:
-                return IMX_CHIP_REVISION_3_0;
-        default:
-                return IMX_CHIP_REVISION_UNKNOWN;
-        }
-}
-
-/*
- * Returns:
- *      the silicon revision of the cpu
- *      -EINVAL - not a mx51
- */
-int mx51_revision(void)
-{
-        if (!cpu_is_mx51())
-                return -EINVAL;
-
-        if (mx5_cpu_rev == -1)
-                mx5_cpu_rev = get_mx51_srev();
-
-        return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx51_revision);
-
-#ifdef CONFIG_NEON
-
-/*
- * All versions of the silicon before Rev. 3 have broken NEON implementations.
- * Dependent on link order - so the assumption is that vfp_init is called
- * before us.
- */
-int __init mx51_neon_fixup(void)
-{
-        if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
-                        (elf_hwcap & HWCAP_NEON)) {
-                elf_hwcap &= ~HWCAP_NEON;
-                pr_info("Turning off NEON support, detected broken NEON implementation\n");
-        }
-        return 0;
-}
-
-#endif
-
-static int get_mx53_srev(void)
-{
-        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
-        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
-
-        switch (rev) {
-        case 0x0:
-                return IMX_CHIP_REVISION_1_0;
-        case 0x2:
-                return IMX_CHIP_REVISION_2_0;
-        case 0x3:
-                return IMX_CHIP_REVISION_2_1;
-        default:
-                return IMX_CHIP_REVISION_UNKNOWN;
-        }
-}
-
-/*
- * Returns:
- *      the silicon revision of the cpu
- *      -EINVAL - not a mx53
- */
-int mx53_revision(void)
-{
-        if (!cpu_is_mx53())
-                return -EINVAL;
-
-        if (mx5_cpu_rev == -1)
-                mx5_cpu_rev = get_mx53_srev();
-
-        return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx53_revision);
-
-static int get_mx50_srev(void)
-{
-        void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
-        u32 rev;
-
-        if (!anatop) {
-                mx5_cpu_rev = -EINVAL;
-                return 0;
-        }
-
-        rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
-        rev &= 0xff;
-
-        iounmap(anatop);
-        if (rev == 0x0)
-                return IMX_CHIP_REVISION_1_0;
-        else if (rev == 0x1)
-                return IMX_CHIP_REVISION_1_1;
-        return 0;
-}
-
-/*
- * Returns:
- *      the silicon revision of the cpu
- *      -EINVAL - not a mx50
- */
-int mx50_revision(void)
-{
-        if (!cpu_is_mx50())
-                return -EINVAL;
-
-        if (mx5_cpu_rev == -1)
-                mx5_cpu_rev = get_mx50_srev();
-
-        return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx50_revision);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
deleted file mode 100644
index 03fcbd08259..00000000000
--- a/arch/arm/mach-imx/cpu.c
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include "hardware.h"
-
-unsigned int __mxc_cpu_type;
-EXPORT_SYMBOL(__mxc_cpu_type);
-
-void mxc_set_cpu_type(unsigned int type)
-{
-        __mxc_cpu_type = type;
-}
-
-void imx_print_silicon_rev(const char *cpu, int srev)
-{
-        if (srev == IMX_CHIP_REVISION_UNKNOWN)
-                pr_info("CPU identified as %s, unknown revision\n", cpu);
-        else
-                pr_info("CPU identified as %s, silicon rev %d.%d\n",
-                                cpu, (srev >> 4) & 0xf, srev & 0xf);
-}
-
-void __init imx_set_aips(void __iomem *base)
-{
-        unsigned int reg;
-/*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
-        __raw_writel(0x77777777, base + 0x0);
-        __raw_writel(0x77777777, base + 0x4);
-
-/*
- * Set all OPACRx to be non-bufferable, to not require
- * supervisor privilege level for access, allow for
- * write access and untrusted master access.
- */
-        __raw_writel(0x0, base + 0x40);
-        __raw_writel(0x0, base + 0x44);
-        __raw_writel(0x0, base + 0x48);
-        __raw_writel(0x0, base + 0x4C);
-        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-        __raw_writel(reg, base + 0x50);
-}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
deleted file mode 100644
index b9ef692b61a..00000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/bug.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include "hardware.h"
-
-static struct cpu_op mx51_cpu_op[] = {
-        {
-        .cpu_rate = 160000000,},
-        {
-        .cpu_rate = 800000000,},
-};
-
-struct cpu_op *mx51_get_cpu_op(int *op)
-{
-        *op = ARRAY_SIZE(mx51_cpu_op);
-        return mx51_cpu_op;
-}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
deleted file mode 100644
index 97477fecb46..00000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
deleted file mode 100644
index d8c75c3c925..00000000000
--- a/arch/arm/mach-imx/cpufreq.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*
- * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
- * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
- * the CPU clock speed on the fly.
- */
-
-#include <linux/module.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include "hardware.h"
-
-#define CLK32_FREQ      32768
-#define NANOSECOND      (1000 * 1000 * 1000)
-
-struct cpu_op *(*get_cpu_op)(int *op);
-
-static int cpu_freq_khz_min;
-static int cpu_freq_khz_max;
-
-static struct clk *cpu_clk;
-static struct cpufreq_frequency_table *imx_freq_table;
-
-static int cpu_op_nr;
-static struct cpu_op *cpu_op_tbl;
-
-static int set_cpu_freq(int freq)
-{
-        int ret = 0;
-        int org_cpu_rate;
-
-        org_cpu_rate = clk_get_rate(cpu_clk);
-        if (org_cpu_rate == freq)
-                return ret;
-
-        ret = clk_set_rate(cpu_clk, freq);
-        if (ret != 0) {
-                printk(KERN_DEBUG "cannot set CPU clock rate\n");
-                return ret;
-        }
-
-        return ret;
-}
-
-static int mxc_verify_speed(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        return cpufreq_frequency_table_verify(policy, imx_freq_table);
-}
-
-static unsigned int mxc_get_speed(unsigned int cpu)
-{
-        if (cpu)
-                return 0;
-
-        return clk_get_rate(cpu_clk) / 1000;
-}
-
-static int mxc_set_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq, unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        int freq_Hz;
-        int ret = 0;
-        unsigned int index;
-
-        cpufreq_frequency_table_target(policy, imx_freq_table,
-                        target_freq, relation, &index);
-        freq_Hz = imx_freq_table[index].frequency * 1000;
-
-        freqs.old = clk_get_rate(cpu_clk) / 1000;
-        freqs.new = freq_Hz / 1000;
-        freqs.cpu = 0;
-        freqs.flags = 0;
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        ret = set_cpu_freq(freq_Hz);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return ret;
-}
-
-static int mxc_cpufreq_init(struct cpufreq_policy *policy)
-{
-        int ret;
-        int i;
-
-        printk(KERN_INFO "i.MXC CPU frequency driver\n");
-
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        if (!get_cpu_op)
-                return -EINVAL;
-
-        cpu_clk = clk_get(NULL, "cpu_clk");
-        if (IS_ERR(cpu_clk)) {
-                printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
-                return PTR_ERR(cpu_clk);
-        }
-
-        cpu_op_tbl = get_cpu_op(&cpu_op_nr);
-
-        cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
-        cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
-
-        imx_freq_table = kmalloc(
-                sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
-                        GFP_KERNEL);
-        if (!imx_freq_table) {
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        for (i = 0; i < cpu_op_nr; i++) {
-                imx_freq_table[i].index = i;
-                imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
-
-                if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
-                        cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
-
-                if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
-                        cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
-        }
-
-        imx_freq_table[i].index = i;
-        imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        policy->cur = clk_get_rate(cpu_clk) / 1000;
-        policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
-        policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
-
-        /* Manual states, that PLL stabilizes in two CLK32 periods */
-        policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
-
-        ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
-
-        if (ret < 0) {
-                printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
-                       __func__, ret);
-                goto err;
-        }
-
-        cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
-        return 0;
-err:
-        kfree(imx_freq_table);
-err1:
-        clk_put(cpu_clk);
-        return ret;
-}
-
-static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-
-        set_cpu_freq(cpu_freq_khz_max * 1000);
-        clk_put(cpu_clk);
-        kfree(imx_freq_table);
-        return 0;
-}
-
-static struct cpufreq_driver mxc_driver = {
-        .flags = CPUFREQ_STICKY,
-        .verify = mxc_verify_speed,
-        .target = mxc_set_target,
-        .get = mxc_get_speed,
-        .init = mxc_cpufreq_init,
-        .exit = mxc_cpufreq_exit,
-        .name = "imx",
-};
-
-static int mxc_cpufreq_driver_init(void)
-{
-        return cpufreq_register_driver(&mxc_driver);
-}
-
-static void mxc_cpufreq_driver_exit(void)
-{
-        cpufreq_unregister_driver(&mxc_driver);
-}
-
-module_init(mxc_cpufreq_driver_init);
-module_exit(mxc_cpufreq_driver_exit);
-
-MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
-MODULE_DESCRIPTION("CPUfreq driver for i.MX");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-imx/cpuidle.c b/arch/arm/mach-imx/cpuidle.c
deleted file mode 100644
index d4cb511a44a..00000000000
--- a/arch/arm/mach-imx/cpuidle.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/cpuidle.h>
-#include <linux/err.h>
-#include <linux/hrtimer.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-static struct cpuidle_device __percpu * imx_cpuidle_devices;
-
-static void __init imx_cpuidle_devices_uninit(void)
-{
-        int cpu_id;
-        struct cpuidle_device *dev;
-
-        for_each_possible_cpu(cpu_id) {
-                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
-                cpuidle_unregister_device(dev);
-        }
-
-        free_percpu(imx_cpuidle_devices);
-}
-
-int __init imx_cpuidle_init(struct cpuidle_driver *drv)
-{
-        struct cpuidle_device *dev;
-        int cpu_id, ret;
-
-        if (drv->state_count > CPUIDLE_STATE_MAX) {
-                pr_err("%s: state_count exceeds maximum\n", __func__);
-                return -EINVAL;
-        }
-
-        ret = cpuidle_register_driver(drv);
-        if (ret) {
-                pr_err("%s: Failed to register cpuidle driver with error: %d\n",
-                         __func__, ret);
-                return ret;
-        }
-
-        imx_cpuidle_devices = alloc_percpu(struct cpuidle_device);
-        if (imx_cpuidle_devices == NULL) {
-                ret = -ENOMEM;
-                goto unregister_drv;
-        }
-
-        /* initialize state data for each cpuidle_device */
-        for_each_possible_cpu(cpu_id) {
-                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
-                dev->cpu = cpu_id;
-                dev->state_count = drv->state_count;
-
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("%s: Failed to register cpu %u, error: %d\n",
-                                __func__, cpu_id, ret);
-                        goto uninit;
-                }
-        }
-
-        return 0;
-
-uninit:
-        imx_cpuidle_devices_uninit();
-
-unregister_drv:
-        cpuidle_unregister_driver(drv);
-        return ret;
-}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
deleted file mode 100644
index bc932d1af37..00000000000
--- a/arch/arm/mach-imx/cpuidle.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/cpuidle.h>
-
-#ifdef CONFIG_CPU_IDLE
-extern int imx_cpuidle_init(struct cpuidle_driver *drv);
-#else
-static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
-{
-        return -ENODEV;
-}
-#endif
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h
deleted file mode 100644
index 5e3f1f0f4ca..00000000000
--- a/arch/arm/mach-imx/crm-regs-imx5.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MX51_CCM_BASE           MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
-#define MX51_DPLL1_BASE         MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
-#define MX51_DPLL2_BASE         MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
-#define MX51_DPLL3_BASE         MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE      MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE           MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
-
-/*MX53*/
-#define MX53_CCM_BASE           MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
-#define MX53_DPLL1_BASE         MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
-#define MX53_DPLL2_BASE         MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
-#define MX53_DPLL3_BASE         MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE         MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL                  0x00
-#define MXC_PLL_DP_CONFIG               0x04
-#define MXC_PLL_DP_OP                   0x08
-#define MXC_PLL_DP_MFD                  0x0C
-#define MXC_PLL_DP_MFN                  0x10
-#define MXC_PLL_DP_MFNMINUS             0x14
-#define MXC_PLL_DP_MFNPLUS              0x18
-#define MXC_PLL_DP_HFS_OP               0x1C
-#define MXC_PLL_DP_HFS_MFD              0x20
-#define MXC_PLL_DP_HFS_MFN              0x24
-#define MXC_PLL_DP_MFN_TOGC             0x28
-#define MXC_PLL_DP_DESTAT               0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL         0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET  12
-#define MXC_PLL_DP_CTL_ADE              0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET       8
-#define MXC_PLL_DP_CTL_HFSM             0x80
-#define MXC_PLL_DP_CTL_PRE              0x40
-#define MXC_PLL_DP_CTL_UPEN             0x20
-#define MXC_PLL_DP_CTL_RST              0x10
-#define MXC_PLL_DP_CTL_RCP              0x8
-#define MXC_PLL_DP_CTL_PLM              0x4
-#define MXC_PLL_DP_CTL_BRM0             0x2
-#define MXC_PLL_DP_CTL_LRF              0x1
-
-#define MXC_PLL_DP_CONFIG_BIST          0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE        0x4
-#define MXC_PLL_DP_CONFIG_AREN          0x2
-#define MXC_PLL_DP_CONFIG_LDREQ         0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET        4
-#define MXC_PLL_DP_OP_MFI_MASK          (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET        0
-#define MXC_PLL_DP_OP_PDF_MASK          0xF
-
-#define MXC_PLL_DP_MFD_OFFSET           0
-#define MXC_PLL_DP_MFD_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET           0x0
-#define MXC_PLL_DP_MFN_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS     (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN      (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET  0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK    0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL       (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN           0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR             (MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR            (MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR             (MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR            (MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR           (MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR           (MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR           (MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1          (MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2          (MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1          (MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR          (MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR          (MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR           (MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR          (MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2          (MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3          (MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4          (MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR            (MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR          (MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR            (MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR            (MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR           (MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR            (MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR            (MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR           (MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR            (MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0           (MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1           (MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2           (MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3           (MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4           (MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5           (MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6           (MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7           (MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR           (MX51_CCM_BASE + 0x84)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN             (1 << 12)
-#define MXC_CCM_CCR_FPM_MULT_MASK       (1 << 11)
-#define MXC_CCM_CCR_CAMP2_EN            (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN            (1 << 9)
-#define MXC_CCM_CCR_FPM_EN              (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET        (0)
-#define MXC_CCM_CCR_OSCNT_MASK  (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_HSC_HS_MASK        (0x1 << 18)
-#define MXC_CCM_CCDR_IPU_HS_MASK        (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK        (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY  (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE   (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_FPM_READY   (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B    (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL         (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET    (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK      (0x3 << 7)
-#define MXC_CCM_CCSR_STEP_SEL_LP_APM       0
-#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
-#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
-#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET   (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK     (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET   (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK     (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL    (1 << 2) /* 0: pll1_main_clk,
-                                                    1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL    (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL    (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET   (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK     (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL               (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL            (0x1 << 25)
-#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET         (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL                (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_OFFSET           (27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK             (0x7 << 27)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET           (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK             (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET         (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK           (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET         (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET           (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK             (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET           (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK             (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET           (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK             (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET       (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK         (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET       (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK         (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET        (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK          (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET    (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK      (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET     (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK       (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET        (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK          (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET    (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK      (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET    (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK      (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET        (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK          (0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET      (14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK        (0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL     (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL        (0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET          (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK            (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET          (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK            (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET           (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL                  (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET              (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK                (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET            (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK              (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET      (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK        (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                   (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL        (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                   (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET      (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK        (0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET       (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK         (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK                (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL                     (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL                     (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET           (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK             (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL                      (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL                  (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET              (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK                (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET             (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK               (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL             (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL             (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)             (26+n*3)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)               (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET         (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK           (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET         (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK           (0x3 << 22)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET               (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK                 (0x3 << 20)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET              (18)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK                (0x3 << 18)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET              (16)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK                (0x3 << 16)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET             (14)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK               (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET              (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK                (0x3 << 12)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET               (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK                 (0x3 << 10)
-#define MXC_CCM_CSCMR2_SLIMBUS_COM                      (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET           (6)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK             (0x7 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM                       (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM                       (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET            (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK              (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET            (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK              (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET     (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK       (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET     (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK       (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET      (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK        (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET      (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK        (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET     (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK       (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET              (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK                (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET     (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK       (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET           (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK             (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET           (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK             (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET             (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK               (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET         (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK           (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET         (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK               (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET         (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK           (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET         (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK               (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET               (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                 (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET            (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK              (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET            (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK              (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET            (16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK              (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET            (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK              (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET                (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK                  (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET               (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                 (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET               (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                 (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET             (12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK               (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET             (6)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK               (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET            (3)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK              (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK              (0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET             (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK               (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET             (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK               (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET              (16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK                (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET              (9)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK                (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET          (6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK                (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET              (0)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK                (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET            (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK              (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET            (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK              (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK               (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET        (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK          (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET        (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK          (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET        (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK          (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET        (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK          (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                    (1 << 16)
-#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY              (1 << 8)
-#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                    (1 << 7)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                 (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY              (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY        (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                    (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                    (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                  (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                  (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER             (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET        (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK          (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS         (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS         (0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS        (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS         (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS         (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS        (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS        (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN              (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET         (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK           (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY                     (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC               (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS                     (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM        (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET       (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK         (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET                (0)
-#define MXC_CCM_CLPCR_LPM_MASK                  (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED                    (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED        (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED                    (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED                    (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED                  (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED                  (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED                     (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY                         (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY                        (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY                         (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY                          (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3                           (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2                           (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1                           (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED               (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED   (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED               (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED             (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED             (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED             (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED                (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY                    (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CKIH_READY                    (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_FPM_READY                     (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3                      (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2                      (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1                      (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                    (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                   (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK                     (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                   (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK                     (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN                           (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                   (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK                     (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                   (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK                     (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE             (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL                            (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET            (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK              (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGRx_CG_MASK                           0x3
-#define MXC_CCM_CCGRx_MOD_OFF                           0x0
-#define MXC_CCM_CCGRx_MOD_ON                            0x3
-#define MXC_CCM_CCGRx_MOD_IDLE                          0x1
-
-#define MXC_CCM_CCGRx_CG15_MASK                         (0x3 << 30)
-#define MXC_CCM_CCGRx_CG14_MASK                         (0x3 << 28)
-#define MXC_CCM_CCGRx_CG13_MASK                         (0x3 << 26)
-#define MXC_CCM_CCGRx_CG12_MASK                         (0x3 << 24)
-#define MXC_CCM_CCGRx_CG11_MASK                         (0x3 << 22)
-#define MXC_CCM_CCGRx_CG10_MASK                         (0x3 << 20)
-#define MXC_CCM_CCGRx_CG9_MASK                          (0x3 << 18)
-#define MXC_CCM_CCGRx_CG8_MASK                          (0x3 << 16)
-#define MXC_CCM_CCGRx_CG5_MASK                          (0x3 << 10)
-#define MXC_CCM_CCGRx_CG4_MASK                          (0x3 << 8)
-#define MXC_CCM_CCGRx_CG3_MASK                          (0x3 << 6)
-#define MXC_CCM_CCGRx_CG2_MASK                          (0x3 << 4)
-#define MXC_CCM_CCGRx_CG1_MASK                          (0x3 << 2)
-#define MXC_CCM_CCGRx_CG0_MASK                          (0x3 << 0)
-
-#define MXC_CCM_CCGRx_CG15_OFFSET                       30
-#define MXC_CCM_CCGRx_CG14_OFFSET                       28
-#define MXC_CCM_CCGRx_CG13_OFFSET                       26
-#define MXC_CCM_CCGRx_CG12_OFFSET                       24
-#define MXC_CCM_CCGRx_CG11_OFFSET                       22
-#define MXC_CCM_CCGRx_CG10_OFFSET                       20
-#define MXC_CCM_CCGRx_CG9_OFFSET                        18
-#define MXC_CCM_CCGRx_CG8_OFFSET                        16
-#define MXC_CCM_CCGRx_CG7_OFFSET                        14
-#define MXC_CCM_CCGRx_CG6_OFFSET                        12
-#define MXC_CCM_CCGRx_CG5_OFFSET                        10
-#define MXC_CCM_CCGRx_CG4_OFFSET                        8
-#define MXC_CCM_CCGRx_CG3_OFFSET                        6
-#define MXC_CCM_CCGRx_CG2_OFFSET                        4
-#define MXC_CCM_CCGRx_CG1_OFFSET                        2
-#define MXC_CCM_CCGRx_CG0_OFFSET                        0
-
-#define MXC_DPTC_LP_BASE        (MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE        (MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE      (MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE       (MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE        (MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE        (MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE        (MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE      (MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE       (MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE    (MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE    (MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE   (MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE       (MX51_GPC_BASE + 0x300)
-
-/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID          (MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC           (MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC           (MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC           (MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC      (MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC          (MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC           (MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC           (MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS           (MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS            (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN            (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1            (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0            (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0            (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1            (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT            (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC            (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR            (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0          (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1          (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0          (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1          (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0             (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1             (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2             (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3             (MXC_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MXC_GPC_CNTR            (MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR             (MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR             (MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU          (MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON            (MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET        8
-#define MXC_GPC_PGR_ARMPG_MASK          (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR        (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR        (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR        (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR        (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR        (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR        (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR            1
-#define MXC_SRPGCR_PCR          1
-#define MXC_EMPGCR_PCR          1
-#define MXC_PGSR_PSR            1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM       (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM   (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR    (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR    (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR    (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR     (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR     (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR     (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR  (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR  (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR  (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR  (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR  (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR  (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR         (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR         (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR         (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR    (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR    (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR    (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif                          /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/crmregs-imx3.h b/arch/arm/mach-imx/crmregs-imx3.h
deleted file mode 100644
index a1dfde53e33..00000000000
--- a/arch/arm/mach-imx/crmregs-imx3.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
-
-#define CKIH_CLK_FREQ           26000000
-#define CKIH_CLK_FREQ_27MHZ     27000000
-#define CKIL_CLK_FREQ           32768
-
-extern void __iomem *mx3_ccm_base;
-
-/* Register addresses */
-#define MXC_CCM_CCMR            0x00
-#define MXC_CCM_PDR0            0x04
-#define MXC_CCM_PDR1            0x08
-#define MX35_CCM_PDR2           0x0C
-#define MXC_CCM_RCSR            0x0C
-#define MX35_CCM_PDR3           0x10
-#define MXC_CCM_MPCTL           0x10
-#define MX35_CCM_PDR4           0x14
-#define MXC_CCM_UPCTL           0x14
-#define MX35_CCM_RCSR           0x18
-#define MXC_CCM_SRPCTL          0x18
-#define MX35_CCM_MPCTL          0x1C
-#define MXC_CCM_COSR            0x1C
-#define MX35_CCM_PPCTL          0x20
-#define MXC_CCM_CGR0            0x20
-#define MX35_CCM_ACMR           0x24
-#define MXC_CCM_CGR1            0x24
-#define MX35_CCM_COSR           0x28
-#define MXC_CCM_CGR2            0x28
-#define MX35_CCM_CGR0           0x2C
-#define MXC_CCM_WIMR            0x2C
-#define MX35_CCM_CGR1           0x30
-#define MXC_CCM_LDC             0x30
-#define MX35_CCM_CGR2           0x34
-#define MXC_CCM_DCVR0           0x34
-#define MX35_CCM_CGR3           0x38
-#define MXC_CCM_DCVR1           0x38
-#define MXC_CCM_DCVR2           0x3C
-#define MXC_CCM_DCVR3           0x40
-#define MXC_CCM_LTR0            0x44
-#define MXC_CCM_LTR1            0x48
-#define MXC_CCM_LTR2            0x4C
-#define MXC_CCM_LTR3            0x50
-#define MXC_CCM_LTBR0           0x54
-#define MXC_CCM_LTBR1           0x58
-#define MXC_CCM_PMCR0           0x5C
-#define MXC_CCM_PMCR1           0x60
-#define MXC_CCM_PDR2            0x64
-
-/* Register bit definitions */
-#define MXC_CCM_CCMR_WBEN                       (1 << 27)
-#define MXC_CCM_CCMR_CSCS                       (1 << 25)
-#define MXC_CCM_CCMR_PERCS                      (1 << 24)
-#define MXC_CCM_CCMR_SSI1S_OFFSET               18
-#define MXC_CCM_CCMR_SSI1S_MASK                 (0x3 << 18)
-#define MXC_CCM_CCMR_SSI2S_OFFSET               21
-#define MXC_CCM_CCMR_SSI2S_MASK                 (0x3 << 21)
-#define MXC_CCM_CCMR_LPM_OFFSET                 14
-#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
-#define MXC_CCM_CCMR_LPM_WAIT_MX35              (0x1 << 14)
-#define MXC_CCM_CCMR_FIRS_OFFSET                11
-#define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
-#define MXC_CCM_CCMR_UPE                        (1 << 9)
-#define MXC_CCM_CCMR_SPE                        (1 << 8)
-#define MXC_CCM_CCMR_MDS                        (1 << 7)
-#define MXC_CCM_CCMR_SBYCS                      (1 << 4)
-#define MXC_CCM_CCMR_MPE                        (1 << 3)
-#define MXC_CCM_CCMR_PRCS_OFFSET                1
-#define MXC_CCM_CCMR_PRCS_MASK                  (0x3 << 1)
-
-#define MXC_CCM_PDR0_CSI_PODF_OFFSET            26
-#define MXC_CCM_PDR0_CSI_PODF_MASK              (0x3F << 26)
-#define MXC_CCM_PDR0_CSI_PRDF_OFFSET            23
-#define MXC_CCM_PDR0_CSI_PRDF_MASK              (0x7 << 23)
-#define MXC_CCM_PDR0_PER_PODF_OFFSET            16
-#define MXC_CCM_PDR0_PER_PODF_MASK              (0x1F << 16)
-#define MXC_CCM_PDR0_HSP_PODF_OFFSET            11
-#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x7 << 11)
-#define MXC_CCM_PDR0_NFC_PODF_OFFSET            8
-#define MXC_CCM_PDR0_NFC_PODF_MASK              (0x7 << 8)
-#define MXC_CCM_PDR0_IPG_PODF_OFFSET            6
-#define MXC_CCM_PDR0_IPG_PODF_MASK              (0x3 << 6)
-#define MXC_CCM_PDR0_MAX_PODF_OFFSET            3
-#define MXC_CCM_PDR0_MAX_PODF_MASK              (0x7 << 3)
-#define MXC_CCM_PDR0_MCU_PODF_OFFSET            0
-#define MXC_CCM_PDR0_MCU_PODF_MASK              0x7
-
-#define MXC_CCM_PDR1_USB_PRDF_OFFSET            30
-#define MXC_CCM_PDR1_USB_PRDF_MASK              (0x3 << 30)
-#define MXC_CCM_PDR1_USB_PODF_OFFSET            27
-#define MXC_CCM_PDR1_USB_PODF_MASK              (0x7 << 27)
-#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET       24
-#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK         (0x7 << 24)
-#define MXC_CCM_PDR1_FIRI_PODF_OFFSET           18
-#define MXC_CCM_PDR1_FIRI_PODF_MASK             (0x3F << 18)
-#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET       15
-#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK         (0x7 << 15)
-#define MXC_CCM_PDR1_SSI2_PODF_OFFSET           9
-#define MXC_CCM_PDR1_SSI2_PODF_MASK             (0x3F << 9)
-#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET       6
-#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK         (0x7 << 6)
-#define MXC_CCM_PDR1_SSI1_PODF_OFFSET           0
-#define MXC_CCM_PDR1_SSI1_PODF_MASK             0x3F
-
-/* Bit definitions for RCSR */
-#define MXC_CCM_RCSR_NF16B                      0x80000000
-
-/*
- * LTR0 register offsets
- */
-#define MXC_CCM_LTR0_DIV3CK_OFFSET              1
-#define MXC_CCM_LTR0_DIV3CK_MASK                (0x3 << 1)
-#define MXC_CCM_LTR0_DNTHR_OFFSET               16
-#define MXC_CCM_LTR0_DNTHR_MASK                 (0x3F << 16)
-#define MXC_CCM_LTR0_UPTHR_OFFSET               22
-#define MXC_CCM_LTR0_UPTHR_MASK                 (0x3F << 22)
-
-/*
- * LTR1 register offsets
- */
-#define MXC_CCM_LTR1_PNCTHR_OFFSET              0
-#define MXC_CCM_LTR1_PNCTHR_MASK                0x3F
-#define MXC_CCM_LTR1_UPCNT_OFFSET               6
-#define MXC_CCM_LTR1_UPCNT_MASK                 (0xFF << 6)
-#define MXC_CCM_LTR1_DNCNT_OFFSET               14
-#define MXC_CCM_LTR1_DNCNT_MASK                 (0xFF << 14)
-#define MXC_CCM_LTR1_LTBRSR_MASK                0x400000
-#define MXC_CCM_LTR1_LTBRSR_OFFSET              22
-#define MXC_CCM_LTR1_LTBRSR                     0x400000
-#define MXC_CCM_LTR1_LTBRSH                     0x800000
-
-/*
- * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
- */
-#define MXC_CCM_LTR2_WSW_OFFSET(x)              (11 + (x) * 3)
-#define MXC_CCM_LTR2_WSW_MASK(x)                (0x7 << \
-                                        MXC_CCM_LTR2_WSW_OFFSET((x)))
-#define MXC_CCM_LTR2_EMAC_OFFSET                0
-#define MXC_CCM_LTR2_EMAC_MASK                  0x1FF
-
-/*
- * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
- */
-#define MXC_CCM_LTR3_WSW_OFFSET(x)              (5 + (x) * 3)
-#define MXC_CCM_LTR3_WSW_MASK(x)                (0x7 << \
-                                        MXC_CCM_LTR3_WSW_OFFSET((x)))
-
-#define MXC_CCM_PMCR0_DFSUP1                    0x80000000
-#define MXC_CCM_PMCR0_DFSUP1_SPLL               (0 << 31)
-#define MXC_CCM_PMCR0_DFSUP1_MPLL               (1 << 31)
-#define MXC_CCM_PMCR0_DFSUP0                    0x40000000
-#define MXC_CCM_PMCR0_DFSUP0_PLL                (0 << 30)
-#define MXC_CCM_PMCR0_DFSUP0_PDR                (1 << 30)
-#define MXC_CCM_PMCR0_DFSUP_MASK                (0x3 << 30)
-
-#define DVSUP_TURBO                             0
-#define DVSUP_HIGH                              1
-#define DVSUP_MEDIUM                            2
-#define DVSUP_LOW                               3
-#define MXC_CCM_PMCR0_DVSUP_TURBO               (DVSUP_TURBO << 28)
-#define MXC_CCM_PMCR0_DVSUP_HIGH                (DVSUP_HIGH << 28)
-#define MXC_CCM_PMCR0_DVSUP_MEDIUM              (DVSUP_MEDIUM << 28)
-#define MXC_CCM_PMCR0_DVSUP_LOW                 (DVSUP_LOW << 28)
-#define MXC_CCM_PMCR0_DVSUP_OFFSET              28
-#define MXC_CCM_PMCR0_DVSUP_MASK                (0x3 << 28)
-#define MXC_CCM_PMCR0_UDSC                      0x08000000
-#define MXC_CCM_PMCR0_UDSC_MASK                 (1 << 27)
-#define MXC_CCM_PMCR0_UDSC_UP                   (1 << 27)
-#define MXC_CCM_PMCR0_UDSC_DOWN                 (0 << 27)
-
-#define MXC_CCM_PMCR0_VSCNT_1                   (0x0 << 24)
-#define MXC_CCM_PMCR0_VSCNT_2                   (0x1 << 24)
-#define MXC_CCM_PMCR0_VSCNT_3                   (0x2 << 24)
-#define MXC_CCM_PMCR0_VSCNT_4                   (0x3 << 24)
-#define MXC_CCM_PMCR0_VSCNT_5                   (0x4 << 24)
-#define MXC_CCM_PMCR0_VSCNT_6                   (0x5 << 24)
-#define MXC_CCM_PMCR0_VSCNT_7                   (0x6 << 24)
-#define MXC_CCM_PMCR0_VSCNT_8                   (0x7 << 24)
-#define MXC_CCM_PMCR0_VSCNT_OFFSET              24
-#define MXC_CCM_PMCR0_VSCNT_MASK                (0x7 << 24)
-#define MXC_CCM_PMCR0_DVFEV                     0x00800000
-#define MXC_CCM_PMCR0_DVFIS                     0x00400000
-#define MXC_CCM_PMCR0_LBMI                      0x00200000
-#define MXC_CCM_PMCR0_LBFL                      0x00100000
-#define MXC_CCM_PMCR0_LBCF_4                    (0x0 << 18)
-#define MXC_CCM_PMCR0_LBCF_8                    (0x1 << 18)
-#define MXC_CCM_PMCR0_LBCF_12                   (0x2 << 18)
-#define MXC_CCM_PMCR0_LBCF_16                   (0x3 << 18)
-#define MXC_CCM_PMCR0_LBCF_OFFSET               18
-#define MXC_CCM_PMCR0_LBCF_MASK                 (0x3 << 18)
-#define MXC_CCM_PMCR0_PTVIS                     0x00020000
-#define MXC_CCM_PMCR0_UPDTEN                    0x00010000
-#define MXC_CCM_PMCR0_UPDTEN_MASK               (0x1 << 16)
-#define MXC_CCM_PMCR0_FSVAIM                    0x00008000
-#define MXC_CCM_PMCR0_FSVAI_OFFSET              13
-#define MXC_CCM_PMCR0_FSVAI_MASK                (0x3 << 13)
-#define MXC_CCM_PMCR0_DPVCR                     0x00001000
-#define MXC_CCM_PMCR0_DPVV                      0x00000800
-#define MXC_CCM_PMCR0_WFIM                      0x00000400
-#define MXC_CCM_PMCR0_DRCE3                     0x00000200
-#define MXC_CCM_PMCR0_DRCE2                     0x00000100
-#define MXC_CCM_PMCR0_DRCE1                     0x00000080
-#define MXC_CCM_PMCR0_DRCE0                     0x00000040
-#define MXC_CCM_PMCR0_DCR                       0x00000020
-#define MXC_CCM_PMCR0_DVFEN                     0x00000010
-#define MXC_CCM_PMCR0_PTVAIM                    0x00000008
-#define MXC_CCM_PMCR0_PTVAI_OFFSET              1
-#define MXC_CCM_PMCR0_PTVAI_MASK                (0x3 << 1)
-#define MXC_CCM_PMCR0_DPTEN                     0x00000001
-
-#define MXC_CCM_PMCR1_DVGP_OFFSET               0
-#define MXC_CCM_PMCR1_DVGP_MASK                 (0xF)
-
-#define MXC_CCM_PMCR1_PLLRDIS                      (0x1 << 7)
-#define MXC_CCM_PMCR1_EMIRQ_EN                      (0x1 << 8)
-
-#define MXC_CCM_DCVR_ULV_MASK                   (0x3FF << 22)
-#define MXC_CCM_DCVR_ULV_OFFSET                 22
-#define MXC_CCM_DCVR_LLV_MASK                   (0x3FF << 12)
-#define MXC_CCM_DCVR_LLV_OFFSET                 12
-#define MXC_CCM_DCVR_ELV_MASK                   (0x3FF << 2)
-#define MXC_CCM_DCVR_ELV_OFFSET                 2
-
-#define MXC_CCM_PDR2_MST2_PDF_MASK              (0x3F << 7)
-#define MXC_CCM_PDR2_MST2_PDF_OFFSET            7
-#define MXC_CCM_PDR2_MST1_PDF_MASK              0x3F
-#define MXC_CCM_PDR2_MST1_PDF_OFFSET            0
-
-#define MXC_CCM_COSR_CLKOSEL_MASK               0x0F
-#define MXC_CCM_COSR_CLKOSEL_OFFSET             0
-#define MXC_CCM_COSR_CLKOUTDIV_MASK             (0x07 << 6)
-#define MXC_CCM_COSR_CLKOUTDIV_OFFSET           6
-#define MXC_CCM_COSR_CLKOEN                     (1 << 9)
-
-/*
- * PMCR0 register offsets
- */
-#define MXC_CCM_PMCR0_LBFL_OFFSET   20
-#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
-#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
-
-#endif                          /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index f9b5afc6bcd..3aad1e70de9 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -6,7 +6,8 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include "devices/devices-common.h"
+#include <mach/mx1.h>
+#include <mach/devices-common.h>
 
 extern const struct imx_imx_fb_data imx1_imx_fb_data;
 #define imx1_add_imx_fb(pdata) \
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index bd939328015..2628e0c474d 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -6,14 +6,15 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include "devices/devices-common.h"
+#include <mach/mx21.h>
+#include <mach/devices-common.h>
 
 extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
 #define imx21_add_imx21_hcd(pdata)      \
         imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
-#define imx21_add_imx2_wdt()    \
+#define imx21_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx21_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx21_imx_fb_data;
@@ -49,7 +50,7 @@ extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
         imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
-#define imx21_add_mxc_w1()      \
+#define imx21_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx21_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx21_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index 0d2922bc575..efa0761c508 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -6,7 +6,8 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include "devices/devices-common.h"
+#include <mach/mx25.h>
+#include <mach/devices-common.h>
 
 extern const struct imx_fec_data imx25_fec_data;
 #define imx25_add_fec(pdata)    \
@@ -23,11 +24,11 @@ extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
 
 extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
-#define imx25_add_imxdi_rtc()   \
+#define imx25_add_imxdi_rtc(pdata)      \
         imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
 
 extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
-#define imx25_add_imx2_wdt()    \
+#define imx25_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx25_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx25_imx_fb_data;
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 13096251975..7f97a3cdd41 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -6,7 +6,8 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include "devices/devices-common.h"
+#include <mach/mx27.h>
+#include <mach/devices-common.h>
 
 extern const struct imx_fec_data imx27_fec_data;
 #define imx27_add_fec(pdata)    \
@@ -16,12 +17,8 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
 #define imx27_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
 
-extern const struct imx_imx27_coda_data imx27_coda_data;
-#define imx27_add_coda()        \
-        imx_add_imx27_coda(&imx27_coda_data)
-
 extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
-#define imx27_add_imx2_wdt()    \
+#define imx27_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx27_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx27_imx_fb_data;
@@ -54,10 +51,6 @@ extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
 
-extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data;
-#define imx27_add_mx2_emmaprp() \
-        imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data)
-
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
 #define imx27_add_mxc_ehci_otg(pdata)   \
         imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
@@ -74,7 +67,7 @@ extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
         imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
-#define imx27_add_mxc_w1()      \
+#define imx27_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx27_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx27_cspi_data[];
@@ -83,7 +76,3 @@ extern const struct imx_spi_imx_data imx27_cspi_data[];
 #define imx27_add_spi_imx0(pdata)       imx27_add_cspi(0, pdata)
 #define imx27_add_spi_imx1(pdata)       imx27_add_cspi(1, pdata)
 #define imx27_add_spi_imx2(pdata)       imx27_add_cspi(2, pdata)
-
-extern const struct imx_pata_imx_data imx27_pata_imx_data;
-#define imx27_add_pata_imx() \
-        imx_add_pata_imx(&imx27_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index e8d1611bbc8..dbe940d9c53 100644
--- a/arch/arm/mach-imx/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -6,14 +6,15 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include "devices/devices-common.h"
+#include <mach/mx31.h>
+#include <mach/devices-common.h>
 
 extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
 #define imx31_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
-#define imx31_add_imx2_wdt()       \
+#define imx31_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx31_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
@@ -41,8 +42,8 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
 #define imx31_add_imx_uart4(pdata)      imx31_add_imx_uart(4, pdata)
 
 extern const struct imx_ipu_core_data imx31_ipu_core_data;
-#define imx31_add_ipu_core()            \
-        imx_add_ipu_core(&imx31_ipu_core_data)
+#define imx31_add_ipu_core(pdata)       \
+        imx_add_ipu_core(&imx31_ipu_core_data, pdata)
 #define imx31_alloc_mx3_camera(pdata)   \
         imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
 #define imx31_add_mx3_sdc_fb(pdata)     \
@@ -64,11 +65,11 @@ extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
         imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
-#define imx31_add_mxc_rtc()     \
+#define imx31_add_mxc_rtc(pdata)        \
         imx_add_mxc_rtc(&imx31_mxc_rtc_data)
 
 extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
-#define imx31_add_mxc_w1()      \
+#define imx31_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx31_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx31_cspi_data[];
@@ -77,7 +78,3 @@ extern const struct imx_spi_imx_data imx31_cspi_data[];
 #define imx31_add_spi_imx0(pdata)       imx31_add_cspi(0, pdata)
 #define imx31_add_spi_imx1(pdata)       imx31_add_cspi(1, pdata)
 #define imx31_add_spi_imx2(pdata)       imx31_add_cspi(2, pdata)
-
-extern const struct imx_pata_imx_data imx31_pata_imx_data;
-#define imx31_add_pata_imx() \
-        imx_add_pata_imx(&imx31_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index e2675f1b141..234cbd3c18a 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -6,7 +6,8 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include "devices/devices-common.h"
+#include <mach/mx35.h>
+#include <mach/devices-common.h>
 
 extern const struct imx_fec_data imx35_fec_data;
 #define imx35_add_fec(pdata)    \
@@ -23,7 +24,7 @@ extern const struct imx_flexcan_data imx35_flexcan_data[];
 #define imx35_add_flexcan1(pdata)       imx35_add_flexcan(1, pdata)
 
 extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
-#define imx35_add_imx2_wdt()       \
+#define imx35_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx35_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
@@ -49,8 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
 #define imx35_add_imx_uart2(pdata)      imx35_add_imx_uart(2, pdata)
 
 extern const struct imx_ipu_core_data imx35_ipu_core_data;
-#define imx35_add_ipu_core()            \
-        imx_add_ipu_core(&imx35_ipu_core_data)
+#define imx35_add_ipu_core(pdata)       \
+        imx_add_ipu_core(&imx35_ipu_core_data, pdata)
 #define imx35_alloc_mx3_camera(pdata)   \
         imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
 #define imx35_add_mx3_sdc_fb(pdata)     \
@@ -67,12 +68,8 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
 #define imx35_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
 
-extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;
-#define imx35_add_mxc_rtc()     \
-        imx_add_mxc_rtc(&imx35_mxc_rtc_data)
-
 extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
-#define imx35_add_mxc_w1()      \
+#define imx35_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx35_mxc_w1_data)
 
 extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
@@ -84,7 +81,3 @@ extern const struct imx_spi_imx_data imx35_cspi_data[];
         imx_add_spi_imx(&imx35_cspi_data[id], pdata)
 #define imx35_add_spi_imx0(pdata)       imx35_add_cspi(0, pdata)
 #define imx35_add_spi_imx1(pdata)       imx35_add_cspi(1, pdata)
-
-extern const struct imx_pata_imx_data imx35_pata_imx_data;
-#define imx35_add_pata_imx() \
-        imx_add_pata_imx(&imx35_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h
deleted file mode 100644
index 2c290391f29..00000000000
--- a/arch/arm/mach-imx/devices-imx50.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include "devices/devices-common.h"
-
-extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
-#define imx50_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
-
-extern const struct imx_fec_data imx50_fec_data;
-#define imx50_add_fec(pdata)    \
-        imx_add_fec(&imx50_fec_data, pdata)
-
-extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
-#define imx50_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
deleted file mode 100644
index deee5baee88..00000000000
--- a/arch/arm/mach-imx/devices-imx51.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fec_data imx51_fec_data;
-#define imx51_add_fec(pdata)    \
-        imx_add_fec(&imx51_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
-#define imx51_add_fsl_usb2_udc(pdata)   \
-        imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
-#define imx51_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
-#define imx51_add_hsi2c(pdata)  \
-        imx51_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
-#define imx51_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
-#define imx51_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
-
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
-#define imx51_add_mxc_ehci_otg(pdata)   \
-        imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
-#define imx51_add_mxc_ehci_hs(id, pdata)        \
-        imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
-#define imx51_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
-#define imx51_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx51_cspi_data;
-#define imx51_add_cspi(pdata)   \
-        imx_add_spi_imx(&imx51_cspi_data, pdata)
-
-extern const struct imx_spi_imx_data imx51_ecspi_data[];
-#define imx51_add_ecspi(id, pdata)      \
-        imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
-#define imx51_add_imx2_wdt(id)  \
-        imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
-#define imx51_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
-
-extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
-#define imx51_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx51_pata_imx_data;
-#define imx51_add_pata_imx() \
-        imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
deleted file mode 100644
index 9a8f1ca7bcb..00000000000
--- a/arch/arm/mach-imx/devices/Kconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-config IMX_HAVE_PLATFORM_FEC
-        bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
-
-config IMX_HAVE_PLATFORM_FLEXCAN
-        bool
-        select HAVE_CAN_FLEXCAN if CAN
-
-config IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        bool
-
-config IMX_HAVE_PLATFORM_GPIO_KEYS
-        bool
-        default y if SOC_IMX51
-
-config IMX_HAVE_PLATFORM_IMX21_HCD
-        bool
-
-config IMX_HAVE_PLATFORM_IMX27_CODA
-        bool
-        default y if SOC_IMX27
-
-config IMX_HAVE_PLATFORM_IMX2_WDT
-        bool
-
-config IMX_HAVE_PLATFORM_IMXDI_RTC
-        bool
-
-config IMX_HAVE_PLATFORM_IMX_FB
-        bool
-
-config IMX_HAVE_PLATFORM_IMX_I2C
-        bool
-
-config IMX_HAVE_PLATFORM_IMX_KEYPAD
-        bool
-
-config IMX_HAVE_PLATFORM_PATA_IMX
-        bool
-
-config IMX_HAVE_PLATFORM_IMX_SSI
-        bool
-
-config IMX_HAVE_PLATFORM_IMX_UART
-        bool
-
-config IMX_HAVE_PLATFORM_IMX_UDC
-        bool
-
-config IMX_HAVE_PLATFORM_IPU_CORE
-        bool
-
-config IMX_HAVE_PLATFORM_MX1_CAMERA
-        bool
-
-config IMX_HAVE_PLATFORM_MX2_CAMERA
-        bool
-
-config IMX_HAVE_PLATFORM_MX2_EMMA
-        bool
-
-config IMX_HAVE_PLATFORM_MXC_EHCI
-        bool
-
-config IMX_HAVE_PLATFORM_MXC_MMC
-        bool
-
-config IMX_HAVE_PLATFORM_MXC_NAND
-        bool
-
-config IMX_HAVE_PLATFORM_MXC_PWM
-        bool
-
-config IMX_HAVE_PLATFORM_MXC_RNGA
-        bool
-        select ARCH_HAS_RNGA
-
-config IMX_HAVE_PLATFORM_MXC_RTC
-        bool
-
-config IMX_HAVE_PLATFORM_MXC_W1
-        bool
-
-config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        bool
-
-config IMX_HAVE_PLATFORM_SPI_IMX
-        bool
-
-config IMX_HAVE_PLATFORM_AHCI
-        bool
-        default y if ARCH_MX53
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
deleted file mode 100644
index 6acf37e0c11..00000000000
--- a/arch/arm/mach-imx/devices/Makefile
+++ /dev/null
@@ -1,33 +0,0 @@
-obj-y := devices.o
-
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
-obj-y += platform-gpio-mxc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
-obj-y += platform-imx-dma.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
deleted file mode 100644
index 6277baf1b7b..00000000000
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/platform_data/dma-imx-sdma.h>
-
-extern struct device mxc_aips_bus;
-extern struct device mxc_ahb_bus;
-
-static inline struct platform_device *imx_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask)
-{
-        struct platform_device_info pdevinfo = {
-                .name = name,
-                .id = id,
-                .res = res,
-                .num_res = num_resources,
-                .data = data,
-                .size_data = size_data,
-                .dma_mask = dmamask,
-        };
-        return platform_device_register_full(&pdevinfo);
-}
-
-static inline struct platform_device *imx_add_platform_device(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data)
-{
-        return imx_add_platform_device_dmamask(
-                        name, id, res, num_resources, data, size_data, 0);
-}
-
-#include <linux/fec.h>
-struct imx_fec_data {
-        const char *devid;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_fec(
-                const struct imx_fec_data *data,
-                const struct fec_platform_data *pdata);
-
-#include <linux/can/platform/flexcan.h>
-struct imx_flexcan_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_flexcan(
-                const struct imx_flexcan_data *data,
-                const struct flexcan_platform_data *pdata);
-
-#include <linux/fsl_devices.h>
-struct imx_fsl_usb2_udc_data {
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_fsl_usb2_udc(
-                const struct imx_fsl_usb2_udc_data *data,
-                const struct fsl_usb2_platform_data *pdata);
-
-#include <linux/gpio_keys.h>
-struct platform_device *__init imx_add_gpio_keys(
-                const struct gpio_keys_platform_data *pdata);
-
-#include <linux/platform_data/usb-mx2.h>
-struct imx_imx21_hcd_data {
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx21_hcd(
-                const struct imx_imx21_hcd_data *data,
-                const struct mx21_usbh_platform_data *pdata);
-
-struct imx_imx27_coda_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx27_coda(
-                const struct imx_imx27_coda_data *data);
-
-struct imx_imx2_wdt_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-};
-struct platform_device *__init imx_add_imx2_wdt(
-                const struct imx_imx2_wdt_data *data);
-
-struct imx_imxdi_rtc_data {
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imxdi_rtc(
-                const struct imx_imxdi_rtc_data *data);
-
-#include <linux/platform_data/video-imxfb.h>
-struct imx_imx_fb_data {
-        const char *devid;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_fb(
-                const struct imx_imx_fb_data *data,
-                const struct imx_fb_platform_data *pdata);
-
-#include <linux/platform_data/i2c-imx.h>
-struct imx_imx_i2c_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_i2c(
-                const struct imx_imx_i2c_data *data,
-                const struct imxi2c_platform_data *pdata);
-
-#include <linux/input/matrix_keypad.h>
-struct imx_imx_keypad_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_keypad(
-                const struct imx_imx_keypad_data *data,
-                const struct matrix_keymap_data *pdata);
-
-#include <linux/platform_data/asoc-imx-ssi.h>
-struct imx_imx_ssi_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-        resource_size_t dmatx0;
-        resource_size_t dmarx0;
-        resource_size_t dmatx1;
-        resource_size_t dmarx1;
-};
-struct platform_device *__init imx_add_imx_ssi(
-                const struct imx_imx_ssi_data *data,
-                const struct imx_ssi_platform_data *pdata);
-
-#include <linux/platform_data/serial-imx.h>
-struct imx_imx_uart_3irq_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irqrx;
-        resource_size_t irqtx;
-        resource_size_t irqrts;
-};
-struct platform_device *__init imx_add_imx_uart_3irq(
-                const struct imx_imx_uart_3irq_data *data,
-                const struct imxuart_platform_data *pdata);
-
-struct imx_imx_uart_1irq_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_uart_1irq(
-                const struct imx_imx_uart_1irq_data *data,
-                const struct imxuart_platform_data *pdata);
-
-#include <linux/platform_data/usb-imx_udc.h>
-struct imx_imx_udc_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq0;
-        resource_size_t irq1;
-        resource_size_t irq2;
-        resource_size_t irq3;
-        resource_size_t irq4;
-        resource_size_t irq5;
-        resource_size_t irq6;
-};
-struct platform_device *__init imx_add_imx_udc(
-                const struct imx_imx_udc_data *data,
-                const struct imxusb_platform_data *pdata);
-
-#include <linux/platform_data/video-mx3fb.h>
-#include <linux/platform_data/camera-mx3.h>
-struct imx_ipu_core_data {
-        resource_size_t iobase;
-        resource_size_t synirq;
-        resource_size_t errirq;
-};
-struct platform_device *__init imx_add_ipu_core(
-                const struct imx_ipu_core_data *data);
-struct platform_device *__init imx_alloc_mx3_camera(
-                const struct imx_ipu_core_data *data,
-                const struct mx3_camera_pdata *pdata);
-struct platform_device *__init imx_add_mx3_sdc_fb(
-                const struct imx_ipu_core_data *data,
-                struct mx3fb_platform_data *pdata);
-
-#include <linux/platform_data/camera-mx1.h>
-struct imx_mx1_camera_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mx1_camera(
-                const struct imx_mx1_camera_data *data,
-                const struct mx1_camera_pdata *pdata);
-
-#include <linux/platform_data/camera-mx2.h>
-struct imx_mx2_camera_data {
-        const char *devid;
-        resource_size_t iobasecsi;
-        resource_size_t iosizecsi;
-        resource_size_t irqcsi;
-        resource_size_t iobaseemmaprp;
-        resource_size_t iosizeemmaprp;
-        resource_size_t irqemmaprp;
-};
-struct platform_device *__init imx_add_mx2_camera(
-                const struct imx_mx2_camera_data *data,
-                const struct mx2_camera_platform_data *pdata);
-
-
-struct imx_mx2_emma_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mx2_emmaprp(
-                const struct imx_mx2_emma_data *data);
-
-#include <linux/platform_data/usb-ehci-mxc.h>
-struct imx_mxc_ehci_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_ehci(
-                const struct imx_mxc_ehci_data *data,
-                const struct mxc_usbh_platform_data *pdata);
-
-#include <linux/platform_data/mmc-mxcmmc.h>
-struct imx_mxc_mmc_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-        resource_size_t dmareq;
-};
-struct platform_device *__init imx_add_mxc_mmc(
-                const struct imx_mxc_mmc_data *data,
-                const struct imxmmc_platform_data *pdata);
-
-#include <linux/platform_data/mtd-mxc_nand.h>
-struct imx_mxc_nand_data {
-        const char *devid;
-        /*
-         * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
-         * machines but don't change existing devices as the nand device usually
-         * appears in the kernel command line to pass its partitioning.
-         */
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t axibase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_nand(
-                const struct imx_mxc_nand_data *data,
-                const struct mxc_nand_platform_data *pdata);
-
-struct imx_pata_imx_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_pata_imx(
-                const struct imx_pata_imx_data *data);
-
-struct imx_mxc_pwm_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data);
-
-/* mxc_rtc */
-struct imx_mxc_rtc_data {
-        const char *devid;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_rtc(
-                const struct imx_mxc_rtc_data *data);
-
-/* mxc_w1 */
-struct imx_mxc_w1_data {
-        resource_size_t iobase;
-};
-struct platform_device *__init imx_add_mxc_w1(
-                const struct imx_mxc_w1_data *data);
-
-#include <linux/platform_data/mmc-esdhc-imx.h>
-struct imx_sdhci_esdhc_imx_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_sdhci_esdhc_imx(
-                const struct imx_sdhci_esdhc_imx_data *data,
-                const struct esdhc_platform_data *pdata);
-
-#include <linux/platform_data/spi-imx.h>
-struct imx_spi_imx_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        int irq;
-};
-struct platform_device *__init imx_add_spi_imx(
-                const struct imx_spi_imx_data *data,
-                const struct spi_imx_master *pdata);
-
-struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
-                                        int irq, int irq_err);
-struct platform_device *imx_add_imx_sdma(char *name,
-        resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
-
-#include <linux/ahci_platform.h>
-struct imx_ahci_imx_data {
-        const char *devid;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_ahci_imx(
-                const struct imx_ahci_imx_data *data,
-                const struct ahci_platform_data *pdata);
diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c
deleted file mode 100644
index 1b37482407f..00000000000
--- a/arch/arm/mach-imx/devices/devices.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-
-struct device mxc_aips_bus = {
-        .init_name      = "mxc_aips",
-        .parent         = &platform_bus,
-};
-
-struct device mxc_ahb_bus = {
-        .init_name      = "mxc_ahb",
-        .parent         = &platform_bus,
-};
-
-int __init mxc_device_init(void)
-{
-        int ret;
-
-        ret = device_register(&mxc_aips_bus);
-        if (IS_ERR_VALUE(ret))
-                goto done;
-
-        ret = device_register(&mxc_ahb_bus);
-
-done:
-        return ret;
-}
diff --git a/arch/arm/mach-imx/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c
deleted file mode 100644
index 3d87dd9c284..00000000000
--- a/arch/arm/mach-imx/devices/platform-ahci-imx.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_ahci_imx_data_entry_single(soc, _devid)             \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _SATA_BASE_ADDR,                       \
-                .irq = soc ## _INT_SATA,                                \
-        }
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
-        imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
-#endif
-
-enum {
-        HOST_CAP = 0x00,
-        HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
-        HOST_PORTS_IMPL = 0x0c,
-        HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
-};
-
-static struct clk *sata_clk, *sata_ref_clk;
-
-/* AHCI module Initialization, if return 0, initialization is successful. */
-static int imx_sata_init(struct device *dev, void __iomem *addr)
-{
-        u32 tmpdata;
-        int ret = 0;
-        struct clk *clk;
-
-        sata_clk = clk_get(dev, "ahci");
-        if (IS_ERR(sata_clk)) {
-                dev_err(dev, "no sata clock.\n");
-                return PTR_ERR(sata_clk);
-        }
-        ret = clk_prepare_enable(sata_clk);
-        if (ret) {
-                dev_err(dev, "can't prepare/enable sata clock.\n");
-                goto put_sata_clk;
-        }
-
-        /* Get the AHCI SATA PHY CLK */
-        sata_ref_clk = clk_get(dev, "ahci_phy");
-        if (IS_ERR(sata_ref_clk)) {
-                dev_err(dev, "no sata ref clock.\n");
-                ret = PTR_ERR(sata_ref_clk);
-                goto release_sata_clk;
-        }
-        ret = clk_prepare_enable(sata_ref_clk);
-        if (ret) {
-                dev_err(dev, "can't prepare/enable sata ref clock.\n");
-                goto put_sata_ref_clk;
-        }
-
-        /* Get the AHB clock rate, and configure the TIMER1MS reg later */
-        clk = clk_get(dev, "ahci_dma");
-        if (IS_ERR(clk)) {
-                dev_err(dev, "no dma clock.\n");
-                ret = PTR_ERR(clk);
-                goto release_sata_ref_clk;
-        }
-        tmpdata = clk_get_rate(clk) / 1000;
-        clk_put(clk);
-
-        writel(tmpdata, addr + HOST_TIMER1MS);
-
-        tmpdata = readl(addr + HOST_CAP);
-        if (!(tmpdata & HOST_CAP_SSS)) {
-                tmpdata |= HOST_CAP_SSS;
-                writel(tmpdata, addr + HOST_CAP);
-        }
-
-        if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
-                writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
-                        addr + HOST_PORTS_IMPL);
-
-        return 0;
-
-release_sata_ref_clk:
-        clk_disable_unprepare(sata_ref_clk);
-put_sata_ref_clk:
-        clk_put(sata_ref_clk);
-release_sata_clk:
-        clk_disable_unprepare(sata_clk);
-put_sata_clk:
-        clk_put(sata_clk);
-
-        return ret;
-}
-
-static void imx_sata_exit(struct device *dev)
-{
-        clk_disable_unprepare(sata_ref_clk);
-        clk_put(sata_ref_clk);
-
-        clk_disable_unprepare(sata_clk);
-        clk_put(sata_clk);
-
-}
-struct platform_device *__init imx_add_ahci_imx(
-                const struct imx_ahci_imx_data *data,
-                const struct ahci_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device_dmamask(data->devid, 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata),  DMA_BIT_MASK(32));
-}
-
-struct platform_device *__init imx53_add_ahci_imx(void)
-{
-        struct ahci_platform_data pdata = {
-                .init = imx_sata_init,
-                .exit = imx_sata_exit,
-        };
-
-        return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
-}
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
deleted file mode 100644
index 2cb188ad9a0..00000000000
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_fec_data_entry_single(soc, _devid)                          \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _FEC_BASE_ADDR,                        \
-                .irq = soc ## _INT_FEC,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_fec_data imx25_fec_data __initconst =
-        imx_fec_data_entry_single(MX25, "imx25-fec");
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_fec_data imx27_fec_data __initconst =
-        imx_fec_data_entry_single(MX27, "imx27-fec");
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX35
-/* i.mx35 has the i.mx27 type fec */
-const struct imx_fec_data imx35_fec_data __initconst =
-        imx_fec_data_entry_single(MX35, "imx27-fec");
-#endif
-
-#ifdef CONFIG_SOC_IMX50
-/* i.mx50 has the i.mx25 type fec */
-const struct imx_fec_data imx50_fec_data __initconst =
-        imx_fec_data_entry_single(MX50, "imx25-fec");
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-/* i.mx51 has the i.mx27 type fec */
-const struct imx_fec_data imx51_fec_data __initconst =
-        imx_fec_data_entry_single(MX51, "imx27-fec");
-#endif
-
-#ifdef CONFIG_SOC_IMX53
-/* i.mx53 has the i.mx25 type fec */
-const struct imx_fec_data imx53_fec_data __initconst =
-        imx_fec_data_entry_single(MX53, "imx25-fec");
-#endif
-
-struct platform_device *__init imx_add_fec(
-                const struct imx_fec_data *data,
-                const struct fec_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device_dmamask(data->devid, 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c
deleted file mode 100644
index 1078bf0a94e..00000000000
--- a/arch/arm/mach-imx/devices/platform-flexcan.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CAN ## _hwid,                        \
-        }
-
-#define imx_flexcan_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_flexcan_data imx25_flexcan_data[] __initconst = {
-#define imx25_flexcan_data_entry(_id, _hwid)                            \
-        imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_flexcan_data_entry(0, 1),
-        imx25_flexcan_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
-#define imx35_flexcan_data_entry(_id, _hwid)                            \
-        imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K)
-        imx35_flexcan_data_entry(0, 1),
-        imx35_flexcan_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_flexcan(
-                const struct imx_flexcan_data *data,
-                const struct flexcan_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("flexcan", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
deleted file mode 100644
index 37e44398197..00000000000
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_fsl_usb2_udc_data_entry_single(soc)                         \
-        {                                                               \
-                .iobase = soc ## _USB_OTG_BASE_ADDR,                    \
-                .irq = soc ## _INT_USB_OTG,                             \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX25);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX27);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX31);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX35);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX51);
-#endif
-
-struct platform_device *__init imx_add_fsl_usb2_udc(
-                const struct imx_fsl_usb2_udc_data *data,
-                const struct fsl_usb2_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_512 - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c
deleted file mode 100644
index 26483fa94b7..00000000000
--- a/arch/arm/mach-imx/devices/platform-gpio-mxc.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices-common.h"
-
-struct platform_device *__init mxc_register_gpio(char *name, int id,
-        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
-{
-        struct resource res[] = {
-                {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = irq,
-                        .end = irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = irq_high,
-                        .end = irq_high,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return platform_device_register_resndata(&mxc_aips_bus,
-                        name, id, res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-gpio_keys.c b/arch/arm/mach-imx/devices/platform-gpio_keys.c
deleted file mode 100644
index 486282539c7..00000000000
--- a/arch/arm/mach-imx/devices/platform-gpio_keys.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-struct platform_device *__init imx_add_gpio_keys(
-                const struct gpio_keys_platform_data *pdata)
-{
-        return imx_add_platform_device("gpio-keys", -1, NULL,
-                 0, pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-dma.c b/arch/arm/mach-imx/devices/platform-imx-dma.c
deleted file mode 100644
index ccdb5dc4ddb..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx-dma.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices-common.h"
-
-struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name,
-        resource_size_t iobase, int irq, int irq_err)
-{
-        struct resource res[] = {
-                {
-                        .start = iobase,
-                        .end = iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = irq,
-                        .end = irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = irq_err,
-                        .end = irq_err,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return platform_device_register_resndata(&mxc_ahb_bus,
-                        name, -1, res, ARRAY_SIZE(res), NULL, 0);
-}
-
-struct platform_device __init __maybe_unused *imx_add_imx_sdma(char *name,
-        resource_size_t iobase, int irq, struct sdma_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = iobase,
-                        .end = iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = irq,
-                        .end = irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return platform_device_register_resndata(&mxc_ahb_bus, name,
-                        -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
deleted file mode 100644
index 10b0ed39f07..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_fb_data_entry_single(soc, _devid, _size)                \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _LCDC_BASE_ADDR,                       \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_LCDC,                                \
-        }
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX1, "imx1-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-struct platform_device *__init imx_add_imx_fb(
-                const struct imx_imx_fb_data *data,
-                const struct imx_fb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("imx-fb", 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
deleted file mode 100644
index 8e30e5703cd..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)   \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_I2C ## _hwid,                        \
-        }
-
-#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size)          \
-        [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
-        imx_imx_i2c_data_entry_single(MX1, "imx1-i2c", 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
-        imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
-#define imx25_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
-        imx25_imx_i2c_data_entry(0, 1),
-        imx25_imx_i2c_data_entry(1, 2),
-        imx25_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
-#define imx27_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx27_imx_i2c_data_entry(0, 1),
-        imx27_imx_i2c_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
-#define imx31_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx31_imx_i2c_data_entry(0, 1),
-        imx31_imx_i2c_data_entry(1, 2),
-        imx31_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
-#define imx35_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx35_imx_i2c_data_entry(0, 1),
-        imx35_imx_i2c_data_entry(1, 2),
-        imx35_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX50
-const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
-#define imx50_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx50_imx_i2c_data_entry(0, 1),
-        imx50_imx_i2c_data_entry(1, 2),
-        imx50_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
-#define imx51_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx51_imx_i2c_data_entry(0, 1),
-        imx51_imx_i2c_data_entry(1, 2),
-        {
-                .devid = "imx21-i2c",
-                .id = 2,
-                .iobase = MX51_HSI2C_DMA_BASE_ADDR,
-                .iosize = SZ_16K,
-                .irq = MX51_INT_HS_I2C,
-        },
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
-#define imx53_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx53_imx_i2c_data_entry(0, 1),
-        imx53_imx_i2c_data_entry(1, 2),
-        imx53_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_imx_i2c(
-                const struct imx_imx_i2c_data *data,
-                const struct imxi2c_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device(data->devid, data->id,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
deleted file mode 100644
index 8f22a4c98a4..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_keypad_data_entry_single(soc, _size)                    \
-        {                                                               \
-                .iobase = soc ## _KPP_BASE_ADDR,                        \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_KPP,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX21, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX25, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX27, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX31, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX35, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX51, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX53, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_imx_keypad(
-                const struct imx_imx_keypad_data *data,
-                const struct matrix_keymap_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imx-keypad", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
deleted file mode 100644
index bfcb8f3dfa8..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = {                                                       \
-                .id = _id,                                              \
-                .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_SSI ## _hwid,                        \
-                .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0,         \
-                .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0,         \
-                .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1,         \
-                .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1,         \
-        }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
-#define imx21_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
-        imx21_imx_ssi_data_entry(0, 1),
-        imx21_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
-#define imx25_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
-        imx25_imx_ssi_data_entry(0, 1),
-        imx25_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
-#define imx27_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K)
-        imx27_imx_ssi_data_entry(0, 1),
-        imx27_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
-#define imx31_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
-        imx31_imx_ssi_data_entry(0, 1),
-        imx31_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
-#define imx35_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
-        imx35_imx_ssi_data_entry(0, 1),
-        imx35_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
-#define imx51_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_imx_ssi_data_entry(0, 1),
-        imx51_imx_ssi_data_entry(1, 2),
-        imx51_imx_ssi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
-#define imx53_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
-        imx53_imx_ssi_data_entry(0, 1),
-        imx53_imx_ssi_data_entry(1, 2),
-        imx53_imx_ssi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_imx_ssi(
-                const struct imx_imx_ssi_data *data,
-                const struct imx_ssi_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-#define DMARES(_name) {                                                 \
-        .name = #_name,                                                 \
-        .start = data->dma ## _name,                                    \
-        .end = data->dma ## _name,                                      \
-        .flags = IORESOURCE_DMA,                                        \
-}
-                DMARES(tx0),
-                DMARES(rx0),
-                DMARES(tx1),
-                DMARES(rx1),
-        };
-
-        return imx_add_platform_device("imx-ssi", data->id,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
deleted file mode 100644
index 67bf866a2cb..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size)            \
-        [_id] = {                                                       \
-                .id = _id,                                              \
-                .iobase = soc ## _UART ## _hwid ## _BASE_ADDR,          \
-                .iosize = _size,                                        \
-                .irqrx = soc ## _INT_UART ## _hwid ## RX,               \
-                .irqtx = soc ## _INT_UART ## _hwid ## TX,               \
-                .irqrts = soc ## _INT_UART ## _hwid ## RTS,             \
-        }
-
-#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size)            \
-        [_id] = {                                                       \
-                .id = _id,                                              \
-                .iobase = soc ## _UART ## _hwid ## _BASE_ADDR,          \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_UART ## _hwid,                       \
-        }
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
-#define imx1_imx_uart_data_entry(_id, _hwid)                            \
-        imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
-        imx1_imx_uart_data_entry(0, 1),
-        imx1_imx_uart_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
-#define imx21_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
-        imx21_imx_uart_data_entry(0, 1),
-        imx21_imx_uart_data_entry(1, 2),
-        imx21_imx_uart_data_entry(2, 3),
-        imx21_imx_uart_data_entry(3, 4),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
-#define imx25_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_imx_uart_data_entry(0, 1),
-        imx25_imx_uart_data_entry(1, 2),
-        imx25_imx_uart_data_entry(2, 3),
-        imx25_imx_uart_data_entry(3, 4),
-        imx25_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
-#define imx27_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K)
-        imx27_imx_uart_data_entry(0, 1),
-        imx27_imx_uart_data_entry(1, 2),
-        imx27_imx_uart_data_entry(2, 3),
-        imx27_imx_uart_data_entry(3, 4),
-        imx27_imx_uart_data_entry(4, 5),
-        imx27_imx_uart_data_entry(5, 6),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
-#define imx31_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
-        imx31_imx_uart_data_entry(0, 1),
-        imx31_imx_uart_data_entry(1, 2),
-        imx31_imx_uart_data_entry(2, 3),
-        imx31_imx_uart_data_entry(3, 4),
-        imx31_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
-#define imx35_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
-        imx35_imx_uart_data_entry(0, 1),
-        imx35_imx_uart_data_entry(1, 2),
-        imx35_imx_uart_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX50
-const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
-#define imx50_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
-        imx50_imx_uart_data_entry(0, 1),
-        imx50_imx_uart_data_entry(1, 2),
-        imx50_imx_uart_data_entry(2, 3),
-        imx50_imx_uart_data_entry(3, 4),
-        imx50_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX50 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
-#define imx51_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
-        imx51_imx_uart_data_entry(0, 1),
-        imx51_imx_uart_data_entry(1, 2),
-        imx51_imx_uart_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
-#define imx53_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
-        imx53_imx_uart_data_entry(0, 1),
-        imx53_imx_uart_data_entry(1, 2),
-        imx53_imx_uart_data_entry(2, 3),
-        imx53_imx_uart_data_entry(3, 4),
-        imx53_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_imx_uart_3irq(
-                const struct imx_imx_uart_3irq_data *data,
-                const struct imxuart_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irqrx,
-                        .end = data->irqrx,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irqtx,
-                        .end = data->irqtx,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irqrts,
-                        .end = data->irqrx,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imx1-uart", data->id, res,
-                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
-
-struct platform_device *__init imx_add_imx_uart_1irq(
-                const struct imx_imx_uart_1irq_data *data,
-                const struct imxuart_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        /* i.mx21 type uart runs on all i.mx except i.mx1 */
-        return imx_add_platform_device("imx21-uart", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
deleted file mode 100644
index ec75d641368..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)          \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR,          \
-                .iosize = _size,                                        \
-        }
-#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size)                 \
-        [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
-#define imx51_imx2_wdt_data_entry(_id, _hwid)                           \
-        imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_imx2_wdt_data_entry(0, 1),
-        imx51_imx2_wdt_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
-#define imx53_imx2_wdt_data_entry(_id, _hwid)                           \
-        imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
-        imx53_imx2_wdt_data_entry(0, 1),
-        imx53_imx2_wdt_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_imx2_wdt(
-                const struct imx_imx2_wdt_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-        return imx_add_platform_device("imx2-wdt", data->id,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
deleted file mode 100644
index 30c81616a9a..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx21-hcd.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx21_hcd_data_entry_single(soc)                            \
-        {                                                               \
-                .iobase = soc ## _USBOTG_BASE_ADDR,                     \
-                .irq = soc ## _INT_USBHOST,                             \
-        }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
-        imx_imx21_hcd_data_entry_single(MX21);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-struct platform_device *__init imx_add_imx21_hcd(
-                const struct imx_imx21_hcd_data *data,
-                const struct mx21_usbh_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("imx21-hcd", 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx27-coda.c b/arch/arm/mach-imx/devices/platform-imx27-coda.c
deleted file mode 100644
index 25bebc29e54..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx27-coda.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2012 Vista Silicon
- * Javier Martin <javier.martin@vista-silicon.com>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx27_coda_data imx27_coda_data __initconst = {
-        .iobase = MX27_VPU_BASE_ADDR,
-        .iosize = SZ_512,
-        .irq = MX27_INT_VPU,
-};
-#endif
-
-struct platform_device *__init imx_add_imx27_coda(
-                const struct imx_imx27_coda_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL,
-                                        0, DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c
deleted file mode 100644
index 5ced7e4e2c7..00000000000
--- a/arch/arm/mach-imx/devices/platform-imx_udc.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_udc_data_entry_single(soc, _size)                       \
-        {                                                               \
-                .iobase = soc ## _USBD_BASE_ADDR,                       \
-                .iosize = _size,                                        \
-                .irq0 = soc ## _INT_USBD0,                              \
-                .irq1 = soc ## _INT_USBD1,                              \
-                .irq2 = soc ## _INT_USBD2,                              \
-                .irq3 = soc ## _INT_USBD3,                              \
-                .irq4 = soc ## _INT_USBD4,                              \
-                .irq5 = soc ## _INT_USBD5,                              \
-                .irq6 = soc ## _INT_USBD6,                              \
-        }
-
-#define imx_imx_udc_data_entry(soc, _size)                              \
-        [_id] = imx_imx_udc_data_entry_single(soc, _size)
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
-        imx_imx_udc_data_entry_single(MX1, SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-struct platform_device *__init imx_add_imx_udc(
-                const struct imx_imx_udc_data *data,
-                const struct imxusb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq0,
-                        .end = data->irq0,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq1,
-                        .end = data->irq1,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq2,
-                        .end = data->irq2,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq3,
-                        .end = data->irq3,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq4,
-                        .end = data->irq4,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq5,
-                        .end = data->irq5,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq6,
-                        .end = data->irq6,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imx_udc", 0,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
deleted file mode 100644
index 5bb490d556e..00000000000
--- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imxdi_rtc_data_entry_single(soc)                            \
-        {                                                               \
-                .iobase = soc ## _DRYICE_BASE_ADDR,                     \
-                .irq = soc ## _INT_DRYICE,                              \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
-        imx_imxdi_rtc_data_entry_single(MX25);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-struct platform_device *__init imx_add_imxdi_rtc(
-                const struct imx_imxdi_rtc_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imxdi_rtc", 0,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c
deleted file mode 100644
index fc4dd7cedc1..00000000000
--- a/arch/arm/mach-imx/devices/platform-ipu-core.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_ipu_core_entry_single(soc)                                  \
-{                                                                       \
-        .iobase = soc ## _IPU_CTRL_BASE_ADDR,                           \
-        .synirq = soc ## _INT_IPU_SYN,                                  \
-        .errirq = soc ## _INT_IPU_ERR,                                  \
-}
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_ipu_core_data imx31_ipu_core_data __initconst =
-        imx_ipu_core_entry_single(MX31);
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
-        imx_ipu_core_entry_single(MX35);
-#endif
-
-static struct platform_device *imx_ipu_coredev __initdata;
-
-struct platform_device *__init imx_add_ipu_core(
-                const struct imx_ipu_core_data *data)
-{
-        /* The resource order is important! */
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + 0x5f,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->iobase + 0x88,
-                        .end = data->iobase + 0xb3,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->synirq,
-                        .end = data->synirq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->errirq,
-                        .end = data->errirq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
-
-struct platform_device *__init imx_alloc_mx3_camera(
-                const struct imx_ipu_core_data *data,
-                const struct mx3_camera_pdata *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase + 0x60,
-                        .end = data->iobase + 0x87,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-        int ret = -ENOMEM;
-        struct platform_device *pdev;
-
-        if (IS_ERR_OR_NULL(imx_ipu_coredev))
-                return ERR_PTR(-ENODEV);
-
-        pdev = platform_device_alloc("mx3-camera", 0);
-        if (!pdev)
-                goto err;
-
-        pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-        if (!pdev->dev.dma_mask)
-                goto err;
-
-        *pdev->dev.dma_mask = DMA_BIT_MASK(32);
-        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
-        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
-        if (ret)
-                goto err;
-
-        if (pdata) {
-                struct mx3_camera_pdata *copied_pdata;
-
-                ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
-                if (ret) {
-err:
-                        kfree(pdev->dev.dma_mask);
-                        platform_device_put(pdev);
-                        return ERR_PTR(-ENODEV);
-                }
-                copied_pdata = dev_get_platdata(&pdev->dev);
-                copied_pdata->dma_dev = &imx_ipu_coredev->dev;
-        }
-
-        return pdev;
-}
-
-struct platform_device *__init imx_add_mx3_sdc_fb(
-                const struct imx_ipu_core_data *data,
-                struct mx3fb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase + 0xb4,
-                        .end = data->iobase + 0x1bf,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-
-        if (IS_ERR_OR_NULL(imx_ipu_coredev))
-                return ERR_PTR(-ENODEV);
-
-        pdata->dma_dev = &imx_ipu_coredev->dev;
-
-        return imx_add_platform_device_dmamask("mx3_sdc_fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
-                        DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c
deleted file mode 100644
index 2c678813108..00000000000
--- a/arch/arm/mach-imx/devices/platform-mx1-camera.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx1_camera_data_entry_single(soc, _size)                    \
-        {                                                               \
-                .iobase = soc ## _CSI ## _BASE_ADDR,                    \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CSI,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
-        imx_mx1_camera_data_entry_single(MX1, 10);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-struct platform_device *__init imx_add_mx1_camera(
-                const struct imx_mx1_camera_data *data,
-                const struct mx1_camera_pdata *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("mx1-camera", 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
deleted file mode 100644
index b53e1f348f5..00000000000
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx2_camera_data_entry_single(soc, _devid)                   \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobasecsi = soc ## _CSI_BASE_ADDR,                     \
-                .iosizecsi = SZ_4K,                                     \
-                .irqcsi = soc ## _INT_CSI,                              \
-        }
-#define imx_mx2_camera_data_entry_single_emma(soc, _devid)              \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobasecsi = soc ## _CSI_BASE_ADDR,                     \
-                .iosizecsi = SZ_32,                                     \
-                .irqcsi = soc ## _INT_CSI,                              \
-                .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR,             \
-                .iosizeemmaprp = SZ_32,                                 \
-                .irqemmaprp = soc ## _INT_EMMAPRP,                      \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
-        imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
-        imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-struct platform_device *__init imx_add_mx2_camera(
-                const struct imx_mx2_camera_data *data,
-                const struct mx2_camera_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobasecsi,
-                        .end = data->iobasecsi + data->iosizecsi - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irqcsi,
-                        .end = data->irqcsi,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->iobaseemmaprp,
-                        .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irqemmaprp,
-                        .end = data->irqemmaprp,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask(data->devid, 0,
-                        res, data->iobaseemmaprp ? 4 : 2,
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-
diff --git a/arch/arm/mach-imx/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c
deleted file mode 100644
index 11bd01d402f..00000000000
--- a/arch/arm/mach-imx/devices/platform-mx2-emma.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx2_emmaprp_data_entry_single(soc)                          \
-        {                                                               \
-                .iobase = soc ## _EMMAPRP_BASE_ADDR,                    \
-                .iosize = SZ_32,                                        \
-                .irq = soc ## _INT_EMMAPRP,                             \
-        }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mx2_emma_data imx27_mx2_emmaprp_data __initconst =
-        imx_mx2_emmaprp_data_entry_single(MX27);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-struct platform_device *__init imx_add_mx2_emmaprp(
-                const struct imx_mx2_emma_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
-                        res, 2, NULL, 0, DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
deleted file mode 100644
index 5d4bbbfde64..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_ehci_data_entry_single(soc, _id, hs)                    \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _USB_ ## hs ## _BASE_ADDR,             \
-                .irq = soc ## _INT_USB_ ## hs,                          \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
-const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX25, 1, HS);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
-const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = {
-        imx_mxc_ehci_data_entry_single(MX27, 1, HS1),
-        imx_mxc_ehci_data_entry_single(MX27, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX31, 0, OTG);
-const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = {
-        imx_mxc_ehci_data_entry_single(MX31, 1, HS1),
-        imx_mxc_ehci_data_entry_single(MX31, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX35, 0, OTG);
-const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX35, 1, HS);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
-const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
-        imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
-        imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-struct platform_device *__init imx_add_mxc_ehci(
-                const struct imx_mxc_ehci_data *data,
-                const struct mxc_usbh_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_512 - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("mxc-ehci", data->id,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
deleted file mode 100644
index b8203c760c8..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc-mmc.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size)   \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR,          \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_SDHC ## _hwid,                       \
-                .dmareq = soc ## _DMA_REQ_SDHC ## _hwid,                \
-        }
-#define imx_mxc_mmc_data_entry(soc, _devid, _id, _hwid, _size)          \
-        [_id] = imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
-#define imx21_mxc_mmc_data_entry(_id, _hwid)                            \
-        imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K)
-        imx21_mxc_mmc_data_entry(0, 1),
-        imx21_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
-#define imx27_mxc_mmc_data_entry(_id, _hwid)                            \
-        imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K)
-        imx27_mxc_mmc_data_entry(0, 1),
-        imx27_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
-#define imx31_mxc_mmc_data_entry(_id, _hwid)                            \
-        imx_mxc_mmc_data_entry(MX31, "imx31-mmc", _id, _hwid, SZ_16K)
-        imx31_mxc_mmc_data_entry(0, 1),
-        imx31_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-struct platform_device *__init imx_add_mxc_mmc(
-                const struct imx_mxc_mmc_data *data,
-                const struct imxmmc_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dmareq,
-                        .end = data->dmareq,
-                        .flags = IORESOURCE_DMA,
-                },
-        };
-        return imx_add_platform_device_dmamask(data->devid, data->id,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
deleted file mode 100644
index 7af1c53e42b..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_nand_data_entry_single(soc, _devid, _size)              \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _NFC_BASE_ADDR,                        \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_NFC                                  \
-        }
-
-#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size)            \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = -1,                                               \
-                .iobase = soc ## _NFC_BASE_ADDR,                        \
-                .iosize = _size,                                        \
-                .axibase = soc ## _NFC_AXI_BASE_ADDR,                   \
-                .irq = soc ## _INT_NFC                                  \
-        }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K);
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
-        imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
-#endif
-
-struct platform_device *__init imx_add_mxc_nand(
-                const struct imx_mxc_nand_data *data,
-                const struct mxc_nand_platform_data *pdata)
-{
-        /* AXI has to come first, that's how the mxc_nand driver expect it */
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->axibase,
-                        .end = data->axibase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-        return imx_add_platform_device(data->devid, data->id,
-                        res, ARRAY_SIZE(res) - !data->axibase,
-                        pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
deleted file mode 100644
index dcd28977768..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_PWM ## _hwid,                        \
-        }
-#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
-#define imx25_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_mxc_pwm_data_entry(0, 1),
-        imx25_mxc_pwm_data_entry(1, 2),
-        imx25_mxc_pwm_data_entry(2, 3),
-        imx25_mxc_pwm_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
-#define imx51_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_mxc_pwm_data_entry(0, 1),
-        imx51_mxc_pwm_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("mxc_pwm", data->id,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
deleted file mode 100644
index c58404badb5..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-struct imx_mxc_rnga_data {
-        resource_size_t iobase;
-};
-
-#define imx_mxc_rnga_data_entry_single(soc)                             \
-        {                                                               \
-                .iobase = soc ## _RNGA_BASE_ADDR,                       \
-        }
-
-#ifdef CONFIG_SOC_IMX31
-static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
-        imx_mxc_rnga_data_entry_single(MX31);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-static struct platform_device *__init imx_add_mxc_rnga(
-                const struct imx_mxc_rnga_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-        return imx_add_platform_device("mxc_rnga", -1,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
-
-static int __init imxXX_add_mxc_rnga(void)
-{
-        struct platform_device *ret;
-
-#if defined(CONFIG_SOC_IMX31)
-        if (cpu_is_mx31())
-                ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
-        else
-#endif /* if defined(CONFIG_SOC_IMX31) */
-                ret = ERR_PTR(-ENODEV);
-
-        if (IS_ERR(ret))
-                return PTR_ERR(ret);
-
-        return 0;
-}
-arch_initcall(imxXX_add_mxc_rnga);
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rtc.c b/arch/arm/mach-imx/devices/platform-mxc_rtc.c
deleted file mode 100644
index c7fffaadf84..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_rtc.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_rtc_data_entry_single(soc, _devid)                      \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _RTC_BASE_ADDR,                        \
-                .irq = soc ## _INT_RTC,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
-        imx_mxc_rtc_data_entry_single(MX31, "imx21-rtc");
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst =
-        imx_mxc_rtc_data_entry_single(MX35, "imx21-rtc");
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_mxc_rtc(
-                const struct imx_mxc_rtc_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device(data->devid, -1,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c
deleted file mode 100644
index 88c18b720d6..00000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_w1.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_w1_data_entry_single(soc)                               \
-        {                                                               \
-                .iobase = soc ## _OWIRE_BASE_ADDR,                      \
-        }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
-        imx_mxc_w1_data_entry_single(MX21);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
-        imx_mxc_w1_data_entry_single(MX27);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst =
-        imx_mxc_w1_data_entry_single(MX31);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst =
-        imx_mxc_w1_data_entry_single(MX35);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_mxc_w1(
-                const struct imx_mxc_w1_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-
-        return imx_add_platform_device("mxc_w1", 0,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c
deleted file mode 100644
index e4ec11c8ce5..00000000000
--- a/arch/arm/mach-imx/devices/platform-pata_imx.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_pata_imx_data_entry_single(soc, _size)                      \
-        {                                                               \
-                .iobase = soc ## _ATA_BASE_ADDR,                        \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_ATA,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_pata_imx_data imx27_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX27, SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_pata_imx_data imx31_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX31, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX35, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_pata_imx_data imx51_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX51, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_pata_imx_data imx53_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX53, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_pata_imx(
-                const struct imx_pata_imx_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-                {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device("pata_imx", -1,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
-
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
deleted file mode 100644
index e66a4e31631..00000000000
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/platform_data/mmc-esdhc-imx.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR,  \
-                .irq = soc ## _INT_ESDHC ## hwid,                       \
-        }
-
-#define imx_sdhci_esdhc_imx_data_entry(soc, devid, id, hwid)    \
-        [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, devid, id, hwid)
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_sdhci_esdhc_imx_data
-imx25_sdhci_esdhc_imx_data[] __initconst = {
-#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX25, "sdhci-esdhc-imx25", _id, _hwid)
-        imx25_sdhci_esdhc_imx_data_entry(0, 1),
-        imx25_sdhci_esdhc_imx_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_sdhci_esdhc_imx_data
-imx35_sdhci_esdhc_imx_data[] __initconst = {
-#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX35, "sdhci-esdhc-imx35", _id, _hwid)
-        imx35_sdhci_esdhc_imx_data_entry(0, 1),
-        imx35_sdhci_esdhc_imx_data_entry(1, 2),
-        imx35_sdhci_esdhc_imx_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_sdhci_esdhc_imx_data
-imx51_sdhci_esdhc_imx_data[] __initconst = {
-#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid)
-        imx51_sdhci_esdhc_imx_data_entry(0, 1),
-        imx51_sdhci_esdhc_imx_data_entry(1, 2),
-        imx51_sdhci_esdhc_imx_data_entry(2, 3),
-        imx51_sdhci_esdhc_imx_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_sdhci_esdhc_imx_data
-imx53_sdhci_esdhc_imx_data[] __initconst = {
-#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid)
-        imx53_sdhci_esdhc_imx_data_entry(0, 1),
-        imx53_sdhci_esdhc_imx_data_entry(1, 2),
-        imx53_sdhci_esdhc_imx_data_entry(2, 3),
-        imx53_sdhci_esdhc_imx_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-static const struct esdhc_platform_data default_esdhc_pdata __initconst = {
-        .wp_type = ESDHC_WP_NONE,
-        .cd_type = ESDHC_CD_NONE,
-};
-
-struct platform_device *__init imx_add_sdhci_esdhc_imx(
-                const struct imx_sdhci_esdhc_imx_data *data,
-                const struct esdhc_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        /*
-         * If machine does not provide pdata, use the default one
-         * which means no WP/CD support
-         */
-        if (!pdata)
-                pdata = &default_esdhc_pdata;
-
-        return imx_add_platform_device(data->devid, data->id, res,
-                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
deleted file mode 100644
index 8880bcb11e0..00000000000
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR,       \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_ ## type ## hwid,                    \
-        }
-
-#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)        \
-        [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
-#define imx1_cspi_data_entry(_id, _hwid) \
-        imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
-        imx1_cspi_data_entry(0, 1),
-        imx1_cspi_data_entry(1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
-#define imx21_cspi_data_entry(_id, _hwid)                            \
-        imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
-        imx21_cspi_data_entry(0, 1),
-        imx21_cspi_data_entry(1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX25
-/* i.mx25 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
-#define imx25_cspi_data_entry(_id, _hwid)                               \
-        imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
-        imx25_cspi_data_entry(0, 1),
-        imx25_cspi_data_entry(1, 2),
-        imx25_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
-#define imx27_cspi_data_entry(_id, _hwid)                               \
-        imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
-        imx27_cspi_data_entry(0, 1),
-        imx27_cspi_data_entry(1, 2),
-        imx27_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
-#define imx31_cspi_data_entry(_id, _hwid)                               \
-        imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
-        imx31_cspi_data_entry(0, 1),
-        imx31_cspi_data_entry(1, 2),
-        imx31_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
-#define imx35_cspi_data_entry(_id, _hwid)                           \
-        imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
-        imx35_cspi_data_entry(0, 1),
-        imx35_cspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-/* i.mx51 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx51_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K);
-
-const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
-#define imx51_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
-        imx51_ecspi_data_entry(0, 1),
-        imx51_ecspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-/* i.mx53 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx53_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
-
-/* i.mx53 has the i.mx51 type ecspi */
-const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
-#define imx53_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
-        imx53_ecspi_data_entry(0, 1),
-        imx53_ecspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
-struct platform_device *__init imx_add_spi_imx(
-                const struct imx_spi_imx_data *data,
-                const struct spi_imx_master *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device(data->devid, data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 134c190e300..865daf0b09e 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -15,27 +15,23 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
 
-#include "hardware.h"
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
 #define MX25_OTG_SIC_SHIFT      29
 #define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
 #define MX25_OTG_PM_BIT         (1 << 24)
-#define MX25_OTG_PP_BIT         (1 << 11)
-#define MX25_OTG_OCPOL_BIT      (1 << 3)
 
 #define MX25_H1_SIC_SHIFT       21
 #define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
-#define MX25_H1_PP_BIT          (1 << 18)
-#define MX25_H1_PM_BIT          (1 << 16)
+#define MX25_H1_PM_BIT          (1 << 8)
 #define MX25_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX25_H1_TLL_BIT         (1 << 5)
 #define MX25_H1_USBTE_BIT       (1 << 4)
-#define MX25_H1_OCPOL_BIT       (1 << 2)
 
 int mx25_initialize_usb_hw(int port, unsigned int flags)
 {
@@ -45,35 +41,21 @@ int mx25_initialize_usb_hw(int port, unsigned int flags)
 
         switch (port) {
         case 0: /* OTG port */
-                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
-                        MX25_OTG_OCPOL_BIT);
+                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX25_OTG_PM_BIT;
 
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX25_OTG_PP_BIT;
-
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX25_OTG_OCPOL_BIT;
-
                 break;
         case 1: /* H1 port */
-                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
-                        MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
-                        MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
+                        MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX25_H1_PM_BIT;
 
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX25_H1_PP_BIT;
-
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX25_H1_OCPOL_BIT;
-
                 if (!(flags & MXC_EHCI_TTL_ENABLED))
                         v |= MX25_H1_TLL_BIT;
 
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index 448d9115539..fa69419eabd 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -15,9 +15,9 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
 
-#include "hardware.h"
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 05de4e1e39d..faad0f15ac7 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -15,9 +15,9 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
 
-#include "hardware.h"
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 554e7cccff5..001ec3971f5 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -15,27 +15,23 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
 
-#include "hardware.h"
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
 #define MX35_OTG_SIC_SHIFT      29
 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
 #define MX35_OTG_PM_BIT         (1 << 24)
-#define MX35_OTG_PP_BIT         (1 << 11)
-#define MX35_OTG_OCPOL_BIT      (1 << 3)
 
 #define MX35_H1_SIC_SHIFT       21
 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PP_BIT          (1 << 18)
-#define MX35_H1_PM_BIT          (1 << 16)
+#define MX35_H1_PM_BIT          (1 << 8)
 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX35_H1_TLL_BIT         (1 << 5)
 #define MX35_H1_USBTE_BIT       (1 << 4)
-#define MX35_H1_OCPOL_BIT       (1 << 2)
 
 int mx35_initialize_usb_hw(int port, unsigned int flags)
 {
@@ -45,35 +41,21 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
 
         switch (port) {
         case 0: /* OTG port */
-                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
-                        MX35_OTG_OCPOL_BIT);
+                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX35_OTG_PM_BIT;
 
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX35_OTG_PP_BIT;
-
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX35_OTG_OCPOL_BIT;
-
                 break;
         case 1: /* H1 port */
-                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
-                        MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
-                        MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                        MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX35_H1_PM_BIT;
 
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX35_H1_PP_BIT;
-
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX35_H1_OCPOL_BIT;
-
                 if (!(flags & MXC_EHCI_TTL_ENABLED))
                         v |= MX35_H1_TLL_BIT;
 
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
deleted file mode 100644
index e49710b10c6..00000000000
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "hardware.h"
-
-#define MXC_OTG_OFFSET                  0
-#define MXC_H1_OFFSET                   0x200
-#define MXC_H2_OFFSET                   0x400
-
-/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)       /* HOST1 power mask */
-
-/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_POL_BIT      (1 << 9)        /* OTG Polarity of Overcurrent */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_POL_BIT               (1 << 6)        /* UH1 Polarity of Overcurrent */
-#define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
-#define MXC_OTG_PHYCTRL_PWR_POL_BIT     (1 << 3)        /* OTG Power Pin Polarity */
-
-/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
-
-#define MXC_USBCMD_OFFSET               0x140
-
-/* USBCMD */
-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
-
-int mx51_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-        void __iomem *usb_base;
-        void __iomem *usbotg_base;
-        void __iomem *usbother_base;
-        int ret = 0;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base) {
-                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
-                return -ENOMEM;
-        }
-
-        switch (port) {
-        case 0: /* OTG port */
-                usbotg_base = usb_base + MXC_OTG_OFFSET;
-                break;
-        case 1: /* Host 1 port */
-                usbotg_base = usb_base + MXC_H1_OFFSET;
-                break;
-        case 2: /* Host 2 port */
-                usbotg_base = usb_base + MXC_H2_OFFSET;
-                break;
-        default:
-                printk(KERN_ERR"%s no such port %d\n", __func__, port);
-                ret = -ENOENT;
-                goto error;
-        }
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        switch (port) {
-        case 0: /*OTG port */
-                if (flags & MXC_EHCI_INTERNAL_PHY) {
-                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
-                                v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
-                        else
-                                v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                /* OC/USBPWR is used */
-                                v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        } else {
-                                /* OC/USBPWR is not used */
-                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        }
-                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
-                        else
-                                v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
-                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                                v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
-                        else
-                                v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
-                        else
-                                v |= MXC_OTG_UCTRL_OPM_BIT;
-                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-                }
-                break;
-        case 1: /* Host 1 */
-                /*Host ULPI */
-                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                        /* HOST1 wakeup/ULPI intr enable */
-                        v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                } else {
-                        /* HOST1 wakeup/ULPI intr disable */
-                        v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                }
-
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
-                else
-                        v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-
-                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
-                        v |= MXC_H1_OC_POL_BIT;
-                else
-                        v &= ~MXC_H1_OC_POL_BIT;
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
-                else
-                        v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
-                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
-                if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
-                        /* Interrupt Threshold Control:Immediate (no threshold) */
-                        v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
-                __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
-                break;
-        case 2: /* Host 2 ULPI */
-                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
-                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                        /* HOST1 wakeup/ULPI intr enable */
-                        v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                } else {
-                        /* HOST1 wakeup/ULPI intr disable */
-                        v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                }
-
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
-                else
-                        v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
-                break;
-        }
-
-error:
-        iounmap(usb_base);
-        return ret;
-}
-
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
deleted file mode 100644
index 04a5961beea..00000000000
--- a/arch/arm/mach-imx/epit.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/epit.c
- *
- *  Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#define EPITCR          0x00
-#define EPITSR          0x04
-#define EPITLR          0x08
-#define EPITCMPR        0x0c
-#define EPITCNR         0x10
-
-#define EPITCR_EN                       (1 << 0)
-#define EPITCR_ENMOD                    (1 << 1)
-#define EPITCR_OCIEN                    (1 << 2)
-#define EPITCR_RLD                      (1 << 3)
-#define EPITCR_PRESC(x)                 (((x) & 0xfff) << 4)
-#define EPITCR_SWR                      (1 << 16)
-#define EPITCR_IOVW                     (1 << 17)
-#define EPITCR_DBGEN                    (1 << 18)
-#define EPITCR_WAITEN                   (1 << 19)
-#define EPITCR_RES                      (1 << 20)
-#define EPITCR_STOPEN                   (1 << 21)
-#define EPITCR_OM_DISCON                (0 << 22)
-#define EPITCR_OM_TOGGLE                (1 << 22)
-#define EPITCR_OM_CLEAR                 (2 << 22)
-#define EPITCR_OM_SET                   (3 << 22)
-#define EPITCR_CLKSRC_OFF               (0 << 24)
-#define EPITCR_CLKSRC_PERIPHERAL        (1 << 24)
-#define EPITCR_CLKSRC_REF_HIGH          (1 << 24)
-#define EPITCR_CLKSRC_REF_LOW           (3 << 24)
-
-#define EPITSR_OCIF                     (1 << 0)
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "hardware.h"
-
-static struct clock_event_device clockevent_epit;
-static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
-
-static void __iomem *timer_base;
-
-static inline void epit_irq_disable(void)
-{
-        u32 val;
-
-        val = __raw_readl(timer_base + EPITCR);
-        val &= ~EPITCR_OCIEN;
-        __raw_writel(val, timer_base + EPITCR);
-}
-
-static inline void epit_irq_enable(void)
-{
-        u32 val;
-
-        val = __raw_readl(timer_base + EPITCR);
-        val |= EPITCR_OCIEN;
-        __raw_writel(val, timer_base + EPITCR);
-}
-
-static void epit_irq_acknowledge(void)
-{
-        __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
-}
-
-static int __init epit_clocksource_init(struct clk *timer_clk)
-{
-        unsigned int c = clk_get_rate(timer_clk);
-
-        return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32,
-                        clocksource_mmio_readl_down);
-}
-
-/* clock event */
-
-static int epit_set_next_event(unsigned long evt,
-                              struct clock_event_device *unused)
-{
-        unsigned long tcmp;
-
-        tcmp = __raw_readl(timer_base + EPITCNR);
-
-        __raw_writel(tcmp - evt, timer_base + EPITCMPR);
-
-        return 0;
-}
-
-static void epit_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *evt)
-{
-        unsigned long flags;
-
-        /*
-         * The timer interrupt generation is disabled at least
-         * for enough time to call epit_set_next_event()
-         */
-        local_irq_save(flags);
-
-        /* Disable interrupt in GPT module */
-        epit_irq_disable();
-
-        if (mode != clockevent_mode) {
-                /* Set event time into far-far future */
-
-                /* Clear pending interrupt */
-                epit_irq_acknowledge();
-        }
-
-        /* Remember timer mode */
-        clockevent_mode = mode;
-        local_irq_restore(flags);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                printk(KERN_ERR "epit_set_mode: Periodic mode is not "
-                                "supported for i.MX EPIT\n");
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        /*
-         * Do not put overhead of interrupt enable/disable into
-         * epit_set_next_event(), the core has about 4 minutes
-         * to call epit_set_next_event() or shutdown clock after
-         * mode switching
-         */
-                local_irq_save(flags);
-                epit_irq_enable();
-                local_irq_restore(flags);
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                /* Left event sources disabled, no more interrupts appear */
-                break;
-        }
-}
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = &clockevent_epit;
-
-        epit_irq_acknowledge();
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction epit_timer_irq = {
-        .name           = "i.MX EPIT Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = epit_timer_interrupt,
-};
-
-static struct clock_event_device clockevent_epit = {
-        .name           = "epit",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
-        .set_mode       = epit_set_mode,
-        .set_next_event = epit_set_next_event,
-        .rating         = 200,
-};
-
-static int __init epit_clockevent_init(struct clk *timer_clk)
-{
-        unsigned int c = clk_get_rate(timer_clk);
-
-        clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
-                                        clockevent_epit.shift);
-        clockevent_epit.max_delta_ns =
-                        clockevent_delta2ns(0xfffffffe, &clockevent_epit);
-        clockevent_epit.min_delta_ns =
-                        clockevent_delta2ns(0x800, &clockevent_epit);
-
-        clockevent_epit.cpumask = cpumask_of(0);
-
-        clockevents_register_device(&clockevent_epit);
-
-        return 0;
-}
-
-void __init epit_timer_init(void __iomem *base, int irq)
-{
-        struct clk *timer_clk;
-
-        timer_clk = clk_get_sys("imx-epit.0", NULL);
-        if (IS_ERR(timer_clk)) {
-                pr_err("i.MX epit: unable to get clk\n");
-                return;
-        }
-
-        clk_prepare_enable(timer_clk);
-
-        timer_base = base;
-
-        /*
-         * Initialise to a known state (all timers off, and timing reset)
-         */
-        __raw_writel(0x0, timer_base + EPITCR);
-
-        __raw_writel(0xffffffff, timer_base + EPITLR);
-        __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
-                        timer_base + EPITCR);
-
-        /* init and register the timer to the framework */
-        epit_clocksource_init(timer_clk);
-        epit_clockevent_init(timer_clk);
-
-        /* Make irqs happen */
-        setup_irq(irq, &epit_timer_irq);
-}
diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h
deleted file mode 100644
index a21d3313f99..00000000000
--- a/arch/arm/mach-imx/eukrea-baseboards.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on board-pcm038.h which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_EUKREA_BASEBOARDS_H__
-#define __MACH_EUKREA_BASEBOARDS_H__
-
-#ifndef __ASSEMBLY__
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
- * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
- * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
- * or eukrea_cpuimx51sd_init().
- *
- * This example here is for the development board. Refer
- * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
- * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
- * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
- * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
- * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
- */
-
-extern void eukrea_mbimxsd25_baseboard_init(void);
-extern void eukrea_mbimx27_baseboard_init(void);
-extern void eukrea_mbimxsd35_baseboard_init(void);
-extern void eukrea_mbimx51_baseboard_init(void);
-extern void eukrea_mbimxsd51_baseboard_init(void);
-
-#endif
-
-#endif /* __MACH_EUKREA_BASEBOARDS_H__ */
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index b4c70028d35..5db3e1463af 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -29,10 +29,12 @@
 
 #include <asm/mach/arch.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+#include <mach/hardware.h>
+#include <mach/audmux.h>
+
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
 
 static const int eukrea_mbimx27_pins[] __initconst = {
         /* UART2 */
@@ -242,7 +244,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 static void __maybe_unused ads7846_dev_init(void)
 {
         if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
-                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
+                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
                 return;
         }
         gpio_direction_input(ADS7846_PENDOWN);
@@ -265,7 +267,7 @@ static struct spi_board_info __maybe_unused
                 .bus_num        = 0,
                 .chip_select    = 0,
                 .max_speed_hz   = 1500000,
-                /* irq number is run-time assigned */
+                .irq            = IRQ_GPIOD(25),
                 .platform_data  = &ads7846_config,
                 .mode           = SPI_MODE_2,
         },
@@ -304,6 +306,25 @@ void __init eukrea_mbimx27_baseboard_init(void)
         mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
                 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+        /* SSI unit master I2S codec connected to SSI_PINS_4*/
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_TFSDIR |
+                        MXC_AUDMUX_V1_PCR_TCLKDIR |
+                        MXC_AUDMUX_V1_PCR_RFSDIR |
+                        MXC_AUDMUX_V1_PCR_RCLKDIR |
+                        MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                        MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+        );
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+        );
+#endif
+
         imx27_add_imx_uart1(&uart_pdata);
         imx27_add_imx_uart2(&uart_pdata);
 #if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
@@ -328,7 +349,6 @@ void __init eukrea_mbimx27_baseboard_init(void)
         /* SPI_CS0 init */
         mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
         imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
-        eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
         spi_register_board_info(eukrea_mbimx27_spi_board_info,
                         ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
 
@@ -347,5 +367,4 @@ void __init eukrea_mbimx27_baseboard_init(void)
         imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
 
         gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index e2b70f4c1a2..66e8726253f 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -23,17 +23,17 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
-#include <linux/spi/spi.h>
 #include <video/platform_lcd.h>
 
+#include <mach/hardware.h>
+#include <mach/iomux-mx25.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/mx25.h>
+#include <mach/audmux.h>
 
-#include "common.h"
 #include "devices-imx25.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
 
 static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         /* LCD */
@@ -88,22 +88,12 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         /* CAN */
         MX25_PAD_GPIO_D__CAN2_RX,
         MX25_PAD_GPIO_C__CAN2_TX,
-        /* SPI1 */
-        MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
-        MX25_PAD_CSPI1_MISO__CSPI1_MISO,
-        MX25_PAD_CSPI1_SS0__GPIO_1_16,
-        MX25_PAD_CSPI1_SS1__GPIO_1_17,
-        MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
-        MX25_PAD_CSPI1_RDY__GPIO_2_22,
 };
 
-#define GPIO_LED1               IMX_GPIO_NR(3, 19)
-#define GPIO_SWITCH1    IMX_GPIO_NR(3, 18)
-#define GPIO_SD1CD              IMX_GPIO_NR(2, 20)
-#define GPIO_LCDPWR             IMX_GPIO_NR(1, 26)
-#define GPIO_SPI1_SS0   IMX_GPIO_NR(1, 16)
-#define GPIO_SPI1_SS1   IMX_GPIO_NR(1, 17)
-#define GPIO_SPI1_IRQ   IMX_GPIO_NR(2, 22)
+#define GPIO_LED1       83
+#define GPIO_SWITCH1    82
+#define GPIO_SD1CD      52
+#define GPIO_LCDPWR     26
 
 static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
         {
@@ -239,30 +229,6 @@ static struct esdhc_platform_data sd1_pdata = {
         .wp_type = ESDHC_WP_NONE,
 };
 
-static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .mode = SPI_MODE_0,
-        },
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-        },
-};
-
-static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
-
-static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
-        .chipselect     = eukrea_mbimxsd25_spi_cs,
-        .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
-};
-
 /*
  * system init for baseboard usage. Will be called by cpuimx25 init.
  *
@@ -275,6 +241,22 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
                         ARRAY_SIZE(eukrea_mbimxsd_pads)))
                 printk(KERN_ERR "error setting mbimxsd pads !\n");
 
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+        /* SSI unit master I2S codec connected to SSI_AUD5*/
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR |
+                        MXC_AUDMUX_V2_PTCR_TFSEL(4) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                        MXC_AUDMUX_V2_PTCR_TCSEL(4),
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(4)
+        );
+        mxc_audmux_v2_configure_port(4,
+                        MXC_AUDMUX_V2_PTCR_SYN,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+        );
+#endif
+
         imx25_add_imx_uart1(&uart_pdata);
         imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
         imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
@@ -292,19 +274,12 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 
         gpio_request(GPIO_LCDPWR, "LCDPWR");
         gpio_direction_output(GPIO_LCDPWR, 1);
+        gpio_free(GPIO_SWITCH1);
 
         i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
                                 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
 
-        gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
-        gpio_direction_input(GPIO_SPI1_IRQ);
-        gpio_free(GPIO_SPI1_IRQ);
-        imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
-        spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
-                ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
-
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
         gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
         imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 5a2d5ef12dd..0f0af02b318 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -27,7 +27,6 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
-#include <linux/spi/spi.h>
 #include <video/platform_lcd.h>
 #include <linux/i2c.h>
 
@@ -36,10 +35,12 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/audmux.h>
+
 #include "devices-imx35.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
 
 static const struct fb_videomode fb_modedb[] = {
         {
@@ -94,6 +95,10 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "CMO-QVGA",
         .mode           = fb_modedb,
@@ -154,22 +159,12 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
         /* SD1 CD */
         MX35_PAD_LD18__GPIO3_24,
-        /* SPI */
-        MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
-        MX35_PAD_CSPI1_MISO__CSPI1_MISO,
-        MX35_PAD_CSPI1_SS0__GPIO1_18,
-        MX35_PAD_CSPI1_SS1__GPIO1_19,
-        MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
-        MX35_PAD_CSPI1_SPI_RDY__GPIO3_5,
 };
 
 #define GPIO_LED1       IMX_GPIO_NR(3, 29)
 #define GPIO_SWITCH1    IMX_GPIO_NR(3, 25)
 #define GPIO_LCDPWR     IMX_GPIO_NR(1, 4)
 #define GPIO_SD1CD      IMX_GPIO_NR(3, 24)
-#define GPIO_SPI1_SS0   IMX_GPIO_NR(1, 18)
-#define GPIO_SPI1_SS1   IMX_GPIO_NR(1, 19)
-#define GPIO_SPI1_IRQ   IMX_GPIO_NR(3, 5)
 
 static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
                                    unsigned int power)
@@ -245,30 +240,6 @@ static struct esdhc_platform_data sd1_pdata = {
         .wp_type = ESDHC_WP_NONE,
 };
 
-static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .mode = SPI_MODE_0,
-        },
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-        },
-};
-
-static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
-
-static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = {
-        .chipselect     = eukrea_mbimxsd35_spi_cs,
-        .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs),
-};
-
 /*
  * system init for baseboard usage. Will be called by cpuimx35 init.
  *
@@ -281,8 +252,24 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
                         ARRAY_SIZE(eukrea_mbimxsd_pads)))
                 printk(KERN_ERR "error setting mbimxsd pads !\n");
 
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+        /* SSI unit master I2S codec connected to SSI_AUD4 */
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR |
+                        MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                        MXC_AUDMUX_V2_PTCR_TCSEL(3),
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+        );
+        mxc_audmux_v2_configure_port(3,
+                        MXC_AUDMUX_V2_PTCR_SYN,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+        );
+#endif
+
         imx35_add_imx_uart1(&uart_pdata);
-        imx35_add_ipu_core();
+        imx35_add_ipu_core(&mx3_ipu_data);
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
@@ -304,15 +291,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
         i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
                                 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
 
-        gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
-        gpio_direction_input(GPIO_SPI1_IRQ);
-        gpio_free(GPIO_SPI1_IRQ);
-        imx35_add_spi_imx0(&eukrea_mbimxsd35_spi0_data);
-        spi_register_board_info(eukrea_mbimxsd35_spi_board_info,
-                ARRAY_SIZE(eukrea_mbimxsd35_spi_board_info));
-
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
         gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
         imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
deleted file mode 100644
index 9be6c1e69d6..00000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <video/platform_lcd.h>
-#include <linux/backlight.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx51.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-
-static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
-        /* LED */
-        MX51_PAD_NANDF_D10__GPIO3_30,
-        /* SWITCH */
-        NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-        /* UART 3 */
-        MX51_PAD_UART3_RXD__UART3_RXD,
-        MX51_PAD_UART3_TXD__UART3_TXD,
-        MX51_PAD_KEY_COL4__UART3_RTS,
-        MX51_PAD_KEY_COL5__UART3_CTS,
-        /* SD */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD1 CD */
-        NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-        /* SSI */
-        MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
-        MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
-        MX51_PAD_AUD3_BB_CK__AUD3_TXC,
-        MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
-        /* LCD Backlight */
-        MX51_PAD_DI1_D1_CS__GPIO3_4,
-        /* LCD RST */
-        MX51_PAD_CSI1_D9__GPIO3_13,
-};
-
-#define GPIO_LED1       IMX_GPIO_NR(3, 30)
-#define GPIO_SWITCH1    IMX_GPIO_NR(3, 31)
-#define GPIO_LCDRST     IMX_GPIO_NR(3, 13)
-#define GPIO_LCDBL      IMX_GPIO_NR(3, 4)
-
-static void eukrea_mbimxsd51_lcd_power_set(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power)
-                gpio_direction_output(GPIO_LCDRST, 1);
-        else
-                gpio_direction_output(GPIO_LCDRST, 0);
-}
-
-static struct plat_lcd_data eukrea_mbimxsd51_lcd_power_data = {
-        .set_power              = eukrea_mbimxsd51_lcd_power_set,
-};
-
-static struct platform_device eukrea_mbimxsd51_lcd_powerdev = {
-        .name                   = "platform-lcd",
-        .dev.platform_data      = &eukrea_mbimxsd51_lcd_power_data,
-};
-
-static void eukrea_mbimxsd51_bl_set_intensity(int intensity)
-{
-        if (intensity)
-                gpio_direction_output(GPIO_LCDBL, 1);
-        else
-                gpio_direction_output(GPIO_LCDBL, 0);
-}
-
-static struct generic_bl_info eukrea_mbimxsd51_bl_info = {
-        .name                   = "eukrea_mbimxsd51-bl",
-        .max_intensity          = 0xff,
-        .default_intensity      = 0xff,
-        .set_bl_intensity       = eukrea_mbimxsd51_bl_set_intensity,
-};
-
-static struct platform_device eukrea_mbimxsd51_bl_dev = {
-        .name                   = "generic-bl",
-        .id                     = 1,
-        .dev = {
-                .platform_data  = &eukrea_mbimxsd51_bl_info,
-        },
-};
-
-static const struct gpio_led eukrea_mbimxsd51_leds[] __initconst = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = GPIO_LED1,
-        },
-};
-
-static const struct gpio_led_platform_data
-                eukrea_mbimxsd51_led_info __initconst = {
-        .leds           = eukrea_mbimxsd51_leds,
-        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd51_leds),
-};
-
-static struct gpio_keys_button eukrea_mbimxsd51_gpio_buttons[] = {
-        {
-                .gpio           = GPIO_SWITCH1,
-                .code           = BTN_0,
-                .desc           = "BP1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-
-static const struct gpio_keys_platform_data
-                eukrea_mbimxsd51_button_data __initconst = {
-        .buttons        = eukrea_mbimxsd51_gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd51_gpio_buttons),
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct i2c_board_info eukrea_mbimxsd51_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-
-static const
-struct imx_ssi_platform_data eukrea_mbimxsd51_ssi_pdata __initconst = {
-        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
-};
-
-static int screen_type;
-
-static int __init eukrea_mbimxsd51_screen_type(char *options)
-{
-        if (!strcmp(options, "dvi"))
-                screen_type = 1;
-        else if (!strcmp(options, "tft"))
-                screen_type = 0;
-
-        return 0;
-}
-__setup("screen_type=", eukrea_mbimxsd51_screen_type);
-
-/*
- * system init for baseboard usage. Will be called by cpuimx51sd init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd51_baseboard_init(void)
-{
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd51_pads,
-                        ARRAY_SIZE(eukrea_mbimxsd51_pads)))
-                printk(KERN_ERR "error setting mbimxsd pads !\n");
-
-        imx51_add_imx_uart(1, NULL);
-        imx51_add_imx_uart(2, &uart_pdata);
-
-        imx51_add_sdhci_esdhc_imx(0, NULL);
-
-        imx51_add_imx_ssi(0, &eukrea_mbimxsd51_ssi_pdata);
-
-        gpio_request(GPIO_LED1, "LED1");
-        gpio_direction_output(GPIO_LED1, 1);
-        gpio_free(GPIO_LED1);
-
-        gpio_request(GPIO_SWITCH1, "SWITCH1");
-        gpio_direction_input(GPIO_SWITCH1);
-        gpio_free(GPIO_SWITCH1);
-
-        gpio_request(GPIO_LCDRST, "LCDRST");
-        gpio_direction_output(GPIO_LCDRST, 0);
-        gpio_request(GPIO_LCDBL, "LCDBL");
-        gpio_direction_output(GPIO_LCDBL, 0);
-        if (!screen_type) {
-                platform_device_register(&eukrea_mbimxsd51_bl_dev);
-                platform_device_register(&eukrea_mbimxsd51_lcd_powerdev);
-        } else {
-                gpio_free(GPIO_LCDRST);
-                gpio_free(GPIO_LCDBL);
-        }
-
-        i2c_register_board_info(0, eukrea_mbimxsd51_i2c_devices,
-                                ARRAY_SIZE(eukrea_mbimxsd51_i2c_devices));
-
-        gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info);
-        imx_add_gpio_keys(&eukrea_mbimxsd51_button_data);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
-}
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
deleted file mode 100644
index e1537f9e45b..00000000000
--- a/arch/arm/mach-imx/gpc.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/hardware/gic.h>
-
-#define GPC_IMR1                0x008
-#define GPC_PGC_CPU_PDN         0x2a0
-
-#define IMR_NUM                 4
-
-static void __iomem *gpc_base;
-static u32 gpc_wake_irqs[IMR_NUM];
-static u32 gpc_saved_imrs[IMR_NUM];
-
-void imx_gpc_pre_suspend(void)
-{
-        void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
-        int i;
-
-        /* Tell GPC to power off ARM core when suspend */
-        writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
-
-        for (i = 0; i < IMR_NUM; i++) {
-                gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
-                writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
-        }
-}
-
-void imx_gpc_post_resume(void)
-{
-        void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
-        int i;
-
-        /* Keep ARM core powered on for other low-power modes */
-        writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
-
-        for (i = 0; i < IMR_NUM; i++)
-                writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
-}
-
-static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        unsigned int idx = d->irq / 32 - 1;
-        u32 mask;
-
-        /* Sanity check for SPI irq */
-        if (d->irq < 32)
-                return -EINVAL;
-
-        mask = 1 << d->irq % 32;
-        gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
-                                  gpc_wake_irqs[idx] & ~mask;
-
-        return 0;
-}
-
-static void imx_gpc_irq_unmask(struct irq_data *d)
-{
-        void __iomem *reg;
-        u32 val;
-
-        /* Sanity check for SPI irq */
-        if (d->irq < 32)
-                return;
-
-        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
-        val = readl_relaxed(reg);
-        val &= ~(1 << d->irq % 32);
-        writel_relaxed(val, reg);
-}
-
-static void imx_gpc_irq_mask(struct irq_data *d)
-{
-        void __iomem *reg;
-        u32 val;
-
-        /* Sanity check for SPI irq */
-        if (d->irq < 32)
-                return;
-
-        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
-        val = readl_relaxed(reg);
-        val |= 1 << (d->irq % 32);
-        writel_relaxed(val, reg);
-}
-
-void __init imx_gpc_init(void)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
-        gpc_base = of_iomap(np, 0);
-        WARN_ON(!gpc_base);
-
-        /* Register GPC as the secondary interrupt controller behind GIC */
-        gic_arch_extn.irq_mask = imx_gpc_irq_mask;
-        gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
-        gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
-}
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
deleted file mode 100644
index 3ce7fa3bd43..00000000000
--- a/arch/arm/mach-imx/hardware.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#define __ASM_ARCH_MXC_HARDWARE_H__
-
-#include <asm/sizes.h>
-
-#define addr_in_module(addr, mod) \
-        ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
-
-#define IMX_IO_P2V_MODULE(addr, module)                                 \
-        (((addr) - module ## _BASE_ADDR) < module ## _SIZE ?            \
-         (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
-
-/*
- * This is rather complicated for humans and ugly to verify, but for a machine
- * it's OK.  Still more as it is usually only applied to constants.  The upsides
- * on using this approach are:
- *
- *  - same mapping on all i.MX machines
- *  - works for assembler, too
- *  - no need to nurture #defines for virtual addresses
- *
- * The downside it, it's hard to verify (but I have a script for that).
- *
- * Obviously this needs to be injective for each SoC.  In general it maps the
- * whole address space to [0xf4000000, 0xf5ffffff].  So [0xf6000000,0xfeffffff]
- * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
- *
- * It applies the following mappings for the different SoCs:
- *
- * mx1:
- *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
- * mx21:
- *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
- *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
- * mx25:
- *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
- *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
- *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- * mx27:
- *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
- *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
- * mx31:
- *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
- *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
- *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- * mx35:
- *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
- *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
- *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- * mx50:
- *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
- * mx51:
- *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
- *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
- *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
- *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
- *      AIPS2   0x83f00000+0x100000     ->      0xf5300000+0x100000
- * mx53:
- *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      DEBUG   0x40000000+0x100000     ->      0xf5000000+0x100000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
- *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
- * mx6q:
- *      SCU     0x00a00000+0x004000     ->      0xf4000000+0x004000
- *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
- *      ANATOP  0x020c8000+0x004000     ->      0xf42c8000+0x004000
- *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
- */
-#define IMX_IO_P2V(x)   (                                               \
-                        (((x) & 0x80000000) >> 7) |                     \
-                        (0xf4000000 +                                   \
-                        (((x) & 0x50000000) >> 6) +                     \
-                        (((x) & 0x0b000000) >> 4) +                     \
-                        (((x) & 0x000fffff))))
-
-#define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
-
-#include "mxc.h"
-
-#include "mx6q.h"
-#include "mx50.h"
-#include "mx51.h"
-#include "mx53.h"
-#include "mx3x.h"
-#include "mx31.h"
-#include "mx35.h"
-#include "mx2x.h"
-#include "mx21.h"
-#include "mx27.h"
-#include "mx1.h"
-#include "mx25.h"
-
-#define imx_map_entry(soc, name, _type) {                               \
-        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
-        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
-        .length = soc ## _ ## name ## _SIZE,                            \
-        .type = _type,                                                  \
-}
-
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
-
-#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
deleted file mode 100644
index 7e49deb128a..00000000000
--- a/arch/arm/mach-imx/headsmp.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-
-        .section ".text.head", "ax"
-
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-
-        ldr     r1, =0x3ff
-
-        and     r3, r1, r0, lsr #3      @ NumWays - 1
-        add     r2, r2, #1              @ NumSets
-
-        and     r0, r0, #0x7
-        add     r0, r0, #4      @ SetShift
-
-        clz     r1, r3          @ WayShift
-        add     r4, r3, #1      @ NumWays
-1:      sub     r2, r2, #1      @ NumSets--
-        mov     r3, r4          @ Temp = NumWays
-2:      subs    r3, r3, #1      @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
-
-#ifdef CONFIG_SMP
-ENTRY(v7_secondary_startup)
-        bl      v7_invalidate_l1
-        b       secondary_startup
-ENDPROC(v7_secondary_startup)
-#endif
-
-#ifdef CONFIG_PM
-/*
- * The following code is located into the .data section.  This is to
- * allow phys_l2x0_saved_regs to be accessed with a relative load
- * as we are running on physical address here.
- */
-        .data
-        .align
-
-#ifdef CONFIG_CACHE_L2X0
-        .macro  pl310_resume
-        ldr     r2, phys_l2x0_saved_regs
-        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
-        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
-        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
-        mov     r1, #0x1
-        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
-        .endm
-
-        .globl  phys_l2x0_saved_regs
-phys_l2x0_saved_regs:
-        .long   0
-#else
-        .macro  pl310_resume
-        .endm
-#endif
-
-ENTRY(v7_cpu_resume)
-        bl      v7_invalidate_l1
-        pl310_resume
-        b       cpu_resume
-ENDPROC(v7_cpu_resume)
-#endif
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
deleted file mode 100644
index 3dec962b077..00000000000
--- a/arch/arm/mach-imx/hotplug.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/errno.h>
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-
-#include "common.h"
-
-static inline void cpu_enter_lowpower(void)
-{
-        unsigned int v;
-
-        flush_cache_all();
-        asm volatile(
-                "mcr    p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, %3\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-          : "cc");
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void imx_cpu_die(unsigned int cpu)
-{
-        cpu_enter_lowpower();
-        imx_enable_cpu(cpu, false);
-
-        /* spin here until hardware takes it down */
-        while (1)
-                ;
-}
diff --git a/arch/arm/mach-imx/iim.h b/arch/arm/mach-imx/iim.h
deleted file mode 100644
index 315bffadafd..00000000000
--- a/arch/arm/mach-imx/iim.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_IIM_H__
-#define __ASM_ARCH_MXC_IIM_H__
-
-/* Register offsets */
-#define MXC_IIMSTAT             0x0000
-#define MXC_IIMSTATM            0x0004
-#define MXC_IIMERR              0x0008
-#define MXC_IIMEMASK            0x000C
-#define MXC_IIMFCTL             0x0010
-#define MXC_IIMUA               0x0014
-#define MXC_IIMLA               0x0018
-#define MXC_IIMSDAT             0x001C
-#define MXC_IIMPREV             0x0020
-#define MXC_IIMSREV             0x0024
-#define MXC_IIMPRG_P            0x0028
-#define MXC_IIMSCS0             0x002C
-#define MXC_IIMSCS1             0x0030
-#define MXC_IIMSCS2             0x0034
-#define MXC_IIMSCS3             0x0038
-#define MXC_IIMFBAC0            0x0800
-#define MXC_IIMJAC              0x0804
-#define MXC_IIMHWV1             0x0808
-#define MXC_IIMHWV2             0x080C
-#define MXC_IIMHAB0             0x0810
-#define MXC_IIMHAB1             0x0814
-/* Definitions for i.MX27 TO2 */
-#define MXC_IIMMAC              0x0814
-#define MXC_IIMPREV_FUSE        0x0818
-#define MXC_IIMSREV_FUSE        0x081C
-#define MXC_IIMSJC_CHALL_0      0x0820
-#define MXC_IIMSJC_CHALL_7      0x083C
-#define MXC_IIMFB0UC17          0x0840
-#define MXC_IIMFB0UC255         0x0BFC
-#define MXC_IIMFBAC1            0x0C00
-/* Definitions for i.MX27 TO2 */
-#define MXC_IIMSUID             0x0C04
-#define MXC_IIMKEY0             0x0C04
-#define MXC_IIMKEY20            0x0C54
-#define MXC_IIMSJC_RESP_0       0x0C58
-#define MXC_IIMSJC_RESP_7       0x0C74
-#define MXC_IIMFB1UC30          0x0C78
-#define MXC_IIMFB1UC255         0x0FFC
-
-/* Bit definitions */
-
-#define MXC_IIMHWV1_WLOCK               (0x1 << 7)
-#define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
-#define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
-#define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
-#define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
-#define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
-#define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
-
-#define MXC_IIMHWV2_WLOCK               (0x1 << 7)
-#define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
-#define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
-
-#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
deleted file mode 100644
index e17dfbc4219..00000000000
--- a/arch/arm/mach-imx/imx25-dt.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "common.h"
-#include "mx25.h"
-
-static void __init imx25_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static void __init imx25_timer_init(void)
-{
-        mx25_clocks_init_dt();
-}
-
-static struct sys_timer imx25_timer = {
-        .init = imx25_timer_init,
-};
-
-static const char * const imx25_dt_board_compat[] __initconst = {
-        "fsl,imx25",
-        NULL
-};
-
-DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
-        .map_io         = mx25_map_io,
-        .init_early     = imx25_init_early,
-        .init_irq       = mx25_init_irq,
-        .handle_irq     = imx25_handle_irq,
-        .timer          = &imx25_timer,
-        .init_machine   = imx25_dt_init,
-        .dt_compat      = imx25_dt_board_compat,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
deleted file mode 100644
index ebfae96543c..00000000000
--- a/arch/arm/mach-imx/imx27-dt.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "mx27.h"
-
-static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
-        { /* sentinel */ }
-};
-
-static void __init imx27_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             imx27_auxdata_lookup, NULL);
-}
-
-static void __init imx27_timer_init(void)
-{
-        mx27_clocks_init_dt();
-}
-
-static struct sys_timer imx27_timer = {
-        .init = imx27_timer_init,
-};
-
-static const char * const imx27_dt_board_compat[] __initconst = {
-        "fsl,imx27",
-        NULL
-};
-
-DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
-        .map_io         = mx27_map_io,
-        .init_early     = imx27_init_early,
-        .init_irq       = mx27_init_irq,
-        .handle_irq     = imx27_handle_irq,
-        .timer          = &imx27_timer,
-        .init_machine   = imx27_dt_init,
-        .dt_compat      = imx27_dt_board_compat,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
deleted file mode 100644
index af476de2570..00000000000
--- a/arch/arm/mach-imx/imx31-dt.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "mx31.h"
-
-static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
-                        "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
-                        "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
-                        "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
-                        "imx21-uart.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
-                        "imx21-uart.4", NULL),
-        { /* sentinel */ }
-};
-
-static void __init imx31_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             imx31_auxdata_lookup, NULL);
-}
-
-static void __init imx31_timer_init(void)
-{
-        mx31_clocks_init_dt();
-}
-
-static struct sys_timer imx31_timer = {
-        .init = imx31_timer_init,
-};
-
-static const char *imx31_dt_board_compat[] __initdata = {
-        "fsl,imx31",
-        NULL
-};
-
-DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
-        .map_io         = mx31_map_io,
-        .init_early     = imx31_init_early,
-        .init_irq       = mx31_init_irq,
-        .handle_irq     = imx31_handle_irq,
-        .timer          = &imx31_timer,
-        .init_machine   = imx31_dt_init,
-        .dt_compat      = imx31_dt_board_compat,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
deleted file mode 100644
index 5ffa40c673f..00000000000
--- a/arch/arm/mach-imx/imx51-dt.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "mx51.h"
-
-static void __init imx51_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static void __init imx51_timer_init(void)
-{
-        mx51_clocks_init_dt();
-}
-
-static struct sys_timer imx51_timer = {
-        .init = imx51_timer_init,
-};
-
-static const char *imx51_dt_board_compat[] __initdata = {
-        "fsl,imx51",
-        NULL
-};
-
-DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
-        .map_io         = mx51_map_io,
-        .init_early     = imx51_init_early,
-        .init_irq       = mx51_init_irq,
-        .handle_irq     = imx51_handle_irq,
-        .timer          = &imx51_timer,
-        .init_machine   = imx51_dt_init,
-        .init_late      = imx51_init_late,
-        .dt_compat      = imx51_dt_board_compat,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index cabefbc5e7c..cf8f8099ebd 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -17,14 +17,14 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  * MA 02110-1301, USA.
  */
-#include <linux/gpio.h>
+
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
-
-#include "hardware.h"
-#include "iomux-mx3.h"
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/iomux-mx3.h>
 
 /*
  * IOMUX register (base) addresses
diff --git a/arch/arm/mach-imx/iomux-mx1.h b/arch/arm/mach-imx/iomux-mx1.h
deleted file mode 100644
index 95f4681d85d..00000000000
--- a/arch/arm/mach-imx/iomux-mx1.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX1_H__
-#define __MACH_IOMUX_MX1_H__
-
-#include "iomux-v1.h"
-
-#define PA0_AIN_SPI2_CLK        (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
-#define PA0_AF_ETMTRACESYNC     (GPIO_PORTA | GPIO_AF | 0)
-#define PA1_AOUT_SPI2_RXD       (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
-#define PA1_PF_TIN              (GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_PWM0             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
-#define PA3_PF_CSI_MCLK         (GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_CSI_D0           (GPIO_PORTA | GPIO_PF | 4)
-#define PA5_PF_CSI_D1           (GPIO_PORTA | GPIO_PF | 5)
-#define PA6_PF_CSI_D2           (GPIO_PORTA | GPIO_PF | 6)
-#define PA7_PF_CSI_D3           (GPIO_PORTA | GPIO_PF | 7)
-#define PA8_PF_CSI_D4           (GPIO_PORTA | GPIO_PF | 8)
-#define PA9_PF_CSI_D5           (GPIO_PORTA | GPIO_PF | 9)
-#define PA10_PF_CSI_D6          (GPIO_PORTA | GPIO_PF | 10)
-#define PA11_PF_CSI_D7          (GPIO_PORTA | GPIO_PF | 11)
-#define PA12_PF_CSI_VSYNC       (GPIO_PORTA | GPIO_PF | 12)
-#define PA13_PF_CSI_HSYNC       (GPIO_PORTA | GPIO_PF | 13)
-#define PA14_PF_CSI_PIXCLK      (GPIO_PORTA | GPIO_PF | 14)
-#define PA15_PF_I2C_SDA         (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
-#define PA16_PF_I2C_SCL         (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
-#define PA17_AF_ETMTRACEPKT4    (GPIO_PORTA | GPIO_AF | 17)
-#define PA17_AIN_SPI2_SS        (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
-#define PA18_AF_ETMTRACEPKT5    (GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_ETMTRACEPKT6    (GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_ETMTRACEPKT7    (GPIO_PORTA | GPIO_AF | 20)
-#define PA21_PF_A0              (GPIO_PORTA | GPIO_PF | 21)
-#define PA22_PF_CS4             (GPIO_PORTA | GPIO_PF | 22)
-#define PA23_PF_CS5             (GPIO_PORTA | GPIO_PF | 23)
-#define PA24_PF_A16             (GPIO_PORTA | GPIO_PF | 24)
-#define PA24_AF_ETMTRACEPKT0    (GPIO_PORTA | GPIO_AF | 24)
-#define PA25_PF_A17             (GPIO_PORTA | GPIO_PF | 25)
-#define PA25_AF_ETMTRACEPKT1    (GPIO_PORTA | GPIO_AF | 25)
-#define PA26_PF_A18             (GPIO_PORTA | GPIO_PF | 26)
-#define PA26_AF_ETMTRACEPKT2    (GPIO_PORTA | GPIO_AF | 26)
-#define PA27_PF_A19             (GPIO_PORTA | GPIO_PF | 27)
-#define PA27_AF_ETMTRACEPKT3    (GPIO_PORTA | GPIO_AF | 27)
-#define PA28_PF_A20             (GPIO_PORTA | GPIO_PF | 28)
-#define PA28_AF_ETMPIPESTAT0    (GPIO_PORTA | GPIO_AF | 28)
-#define PA29_PF_A21             (GPIO_PORTA | GPIO_PF | 29)
-#define PA29_AF_ETMPIPESTAT1    (GPIO_PORTA | GPIO_AF | 29)
-#define PA30_PF_A22             (GPIO_PORTA | GPIO_PF | 30)
-#define PA30_AF_ETMPIPESTAT2    (GPIO_PORTA | GPIO_AF | 30)
-#define PA31_PF_A23             (GPIO_PORTA | GPIO_PF | 31)
-#define PA31_AF_ETMTRACECLK     (GPIO_PORTA | GPIO_AF | 31)
-#define PB8_PF_SD_DAT0          (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
-#define PB8_AF_MS_PIO           (GPIO_PORTB | GPIO_AF | 8)
-#define PB9_PF_SD_DAT1          (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
-#define PB9_AF_MS_PI1           (GPIO_PORTB | GPIO_AF | 9)
-#define PB10_PF_SD_DAT2         (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
-#define PB10_AF_MS_SCLKI        (GPIO_PORTB | GPIO_AF | 10)
-#define PB11_PF_SD_DAT3         (GPIO_PORTB | GPIO_PF | 11)
-#define PB11_AF_MS_SDIO         (GPIO_PORTB | GPIO_AF | 11)
-#define PB12_PF_SD_CLK          (GPIO_PORTB | GPIO_PF | 12)
-#define PB12_AF_MS_SCLK0        (GPIO_PORTB | GPIO_AF | 12)
-#define PB13_PF_SD_CMD          (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
-#define PB13_AF_MS_BS           (GPIO_PORTB | GPIO_AF | 13)
-#define PB14_AF_SSI_RXFS        (GPIO_PORTB | GPIO_AF | 14)
-#define PB15_AF_SSI_RXCLK       (GPIO_PORTB | GPIO_AF | 15)
-#define PB16_AF_SSI_RXDAT       (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
-#define PB17_AF_SSI_TXDAT       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
-#define PB18_AF_SSI_TXFS        (GPIO_PORTB | GPIO_AF | 18)
-#define PB19_AF_SSI_TXCLK       (GPIO_PORTB | GPIO_AF | 19)
-#define PB20_PF_USBD_AFE        (GPIO_PORTB | GPIO_PF | 20)
-#define PB21_PF_USBD_OE         (GPIO_PORTB | GPIO_PF | 21)
-#define PB22_PF_USBD_RCV        (GPIO_PORTB | GPIO_PF | 22)
-#define PB23_PF_USBD_SUSPND     (GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USBD_VP         (GPIO_PORTB | GPIO_PF | 24)
-#define PB25_PF_USBD_VM         (GPIO_PORTB | GPIO_PF | 25)
-#define PB26_PF_USBD_VPO        (GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBD_VMO        (GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_UART2_CTS       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
-#define PB29_PF_UART2_RTS       (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
-#define PB30_PF_UART2_TXD       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
-#define PB31_PF_UART2_RXD       (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
-#define PC3_PF_SSI_RXFS         (GPIO_PORTC | GPIO_PF | 3)
-#define PC4_PF_SSI_RXCLK        (GPIO_PORTC | GPIO_PF | 4)
-#define PC5_PF_SSI_RXDAT        (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
-#define PC6_PF_SSI_TXDAT        (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
-#define PC7_PF_SSI_TXFS         (GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_SSI_TXCLK        (GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_UART1_CTS        (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_UART1_RTS       (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
-#define PC11_PF_UART1_TXD       (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_UART1_RXD       (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
-#define PC13_PF_SPI1_SPI_RDY    (GPIO_PORTC | GPIO_PF | 13)
-#define PC14_PF_SPI1_SCLK       (GPIO_PORTC | GPIO_PF | 14)
-#define PC15_PF_SPI1_SS         (GPIO_PORTC | GPIO_PF | 15)
-#define PC16_PF_SPI1_MISO       (GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SPI1_MOSI       (GPIO_PORTC | GPIO_PF | 17)
-#define PC24_BIN_UART3_RI       (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
-#define PC25_BIN_UART3_DSR      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
-#define PC26_AOUT_UART3_DTR     (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
-#define PC27_BIN_UART3_DCD      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
-#define PC28_BIN_UART3_CTS      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
-#define PC29_AOUT_UART3_RTS     (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
-#define PC30_BIN_UART3_TX       (GPIO_PORTC | GPIO_BIN | 30)
-#define PC31_AOUT_UART3_RX      (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
-#define PD6_PF_LSCLK            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
-#define PD7_PF_REV              (GPIO_PORTD | GPIO_PF | 7)
-#define PD7_AF_UART2_DTR        (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
-#define PD7_AIN_SPI2_SCLK       (GPIO_PORTD | GPIO_AIN | 7)
-#define PD8_PF_CLS              (GPIO_PORTD | GPIO_PF | 8)
-#define PD8_AF_UART2_DCD        (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
-#define PD8_AIN_SPI2_SS         (GPIO_PORTD | GPIO_AIN | 8)
-#define PD9_PF_PS               (GPIO_PORTD | GPIO_PF | 9)
-#define PD9_AF_UART2_RI         (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
-#define PD9_AOUT_SPI2_RXD       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
-#define PD10_PF_SPL_SPR         (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
-#define PD10_AF_UART2_DSR       (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
-#define PD10_AIN_SPI2_TXD       (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
-#define PD11_PF_CONTRAST        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
-#define PD12_PF_ACD_OE          (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
-#define PD13_PF_LP_HSYNC        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
-#define PD14_PF_FLM_VSYNC       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
-#define PD15_PF_LD0             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
-#define PD16_PF_LD1             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
-#define PD17_PF_LD2             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
-#define PD18_PF_LD3             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
-#define PD19_PF_LD4             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
-#define PD20_PF_LD5             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
-#define PD21_PF_LD6             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
-#define PD22_PF_LD7             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
-#define PD23_PF_LD8             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
-#define PD24_PF_LD9             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
-#define PD25_PF_LD10            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
-#define PD26_PF_LD11            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
-#define PD27_PF_LD12            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
-#define PD28_PF_LD13            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
-#define PD29_PF_LD14            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
-#define PD30_PF_LD15            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
-#define PD31_PF_TMR2OUT         (GPIO_PORTD | GPIO_PF | 31)
-#define PD31_BIN_SPI2_TXD       (GPIO_PORTD | GPIO_BIN | 31)
-
-#endif /* ifndef __MACH_IOMUX_MX1_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx21.h b/arch/arm/mach-imx/iomux-mx21.h
deleted file mode 100644
index a70cffceb08..00000000000
--- a/arch/arm/mach-imx/iomux-mx21.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX21_H__
-#define __MACH_IOMUX_MX21_H__
-
-#include "iomux-mx2x.h"
-#include "iomux-v1.h"
-
-/* Primary GPIO pin functions */
-
-#define PB22_PF_USBH1_BYP       (GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_ON        (GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_USBOTG_SDA       (GPIO_PORTC | GPIO_PF | 5)
-#define PC6_PF_USBOTG_SCL       (GPIO_PORTC | GPIO_PF | 6)
-#define PC7_PF_USBOTG_ON        (GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_USBOTG_FS        (GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_USBOTG_OE        (GPIO_PORTC | GPIO_PF | 9)
-#define PC10_PF_USBOTG_TXDM     (GPIO_PORTC | GPIO_PF | 10)
-#define PC11_PF_USBOTG_TXDP     (GPIO_PORTC | GPIO_PF | 11)
-#define PC12_PF_USBOTG_RXDM     (GPIO_PORTC | GPIO_PF | 12)
-#define PC13_PF_USBOTG_RXDP     (GPIO_PORTC | GPIO_PF | 13)
-#define PC16_PF_SAP_FS          (GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SAP_RXD         (GPIO_PORTC | GPIO_PF | 17)
-#define PC18_PF_SAP_TXD         (GPIO_PORTC | GPIO_PF | 18)
-#define PC19_PF_SAP_CLK         (GPIO_PORTC | GPIO_PF | 19)
-#define PE0_PF_TEST_WB2         (GPIO_PORTE | GPIO_PF | 0)
-#define PE1_PF_TEST_WB1         (GPIO_PORTE | GPIO_PF | 1)
-#define PE2_PF_TEST_WB0         (GPIO_PORTE | GPIO_PF | 2)
-#define PF1_PF_NFCE             (GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCLE            (GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_NFIO0            (GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_NFIO1            (GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_NFIO2            (GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_NFIO3           (GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_NFIO4           (GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_NFIO5           (GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_NFIO6           (GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_NFIO7           (GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_RES             (GPIO_PORTF | GPIO_PF | 16)
-
-/* Alternate GPIO pin functions */
-
-#define PA5_AF_BMI_CLK_CS       (GPIO_PORTA | GPIO_AF | 5)
-#define PA6_AF_BMI_D0           (GPIO_PORTA | GPIO_AF | 6)
-#define PA7_AF_BMI_D1           (GPIO_PORTA | GPIO_AF | 7)
-#define PA8_AF_BMI_D2           (GPIO_PORTA | GPIO_AF | 8)
-#define PA9_AF_BMI_D3           (GPIO_PORTA | GPIO_AF | 9)
-#define PA10_AF_BMI_D4          (GPIO_PORTA | GPIO_AF | 10)
-#define PA11_AF_BMI_D5          (GPIO_PORTA | GPIO_AF | 11)
-#define PA12_AF_BMI_D6          (GPIO_PORTA | GPIO_AF | 12)
-#define PA13_AF_BMI_D7          (GPIO_PORTA | GPIO_AF | 13)
-#define PA14_AF_BMI_D8          (GPIO_PORTA | GPIO_AF | 14)
-#define PA15_AF_BMI_D9          (GPIO_PORTA | GPIO_AF | 15)
-#define PA16_AF_BMI_D10         (GPIO_PORTA | GPIO_AF | 16)
-#define PA17_AF_BMI_D11         (GPIO_PORTA | GPIO_AF | 17)
-#define PA18_AF_BMI_D12         (GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_BMI_D13         (GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_BMI_D14         (GPIO_PORTA | GPIO_AF | 20)
-#define PA21_AF_BMI_D15         (GPIO_PORTA | GPIO_AF | 21)
-#define PA22_AF_BMI_READ_REQ    (GPIO_PORTA | GPIO_AF | 22)
-#define PA23_AF_BMI_WRITE       (GPIO_PORTA | GPIO_AF | 23)
-#define PA29_AF_BMI_RX_FULL     (GPIO_PORTA | GPIO_AF | 29)
-#define PA30_AF_BMI_READ        (GPIO_PORTA | GPIO_AF | 30)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SYS_CLK        (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PD21_AIN_USBH2_FS       (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
-#define PD22_AIN_USBH2_OE       (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
-#define PD23_AIN_USBH2_TXDM     (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
-#define PD24_AIN_USBH2_TXDP     (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
-#define PE8_AIN_IR_TXD          (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
-#define PF0_AIN_PC_RST          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
-#define PF1_AIN_PC_CE1          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
-#define PF2_AIN_PC_CE2          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
-#define PF3_AIN_PC_POE          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
-#define PF4_AIN_PC_OE           (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
-#define PF5_AIN_PC_RW           (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SYS_CLK        (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-#define PD27_BIN_EXT_DMA_GRANT  (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
-
-/* CIN GPIO pin functions */
-
-#define PB26_CIN_USBH1_RXDAT    (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
-
-/* AOUT GPIO pin functions */
-
-#define PA29_AOUT_BMI_WAIT      (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
-#define PD19_AOUT_USBH2_RXDM    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
-#define PD20_AOUT_USBH2_RXDP    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
-#define PD25_AOUT_EXT_DMAREQ    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
-#define PD26_AOUT_USBOTG_RXDAT  (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
-#define PE9_AOUT_IR_RXD         (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
-#define PF6_AOUT_PC_BVD2        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
-#define PF7_AOUT_PC_BVD1        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
-#define PF8_AOUT_PC_VS2         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
-#define PF9_AOUT_PC_VS1         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
-#define PF10_AOUT_PC_WP         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
-#define PF11_AOUT_PC_READY      (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
-#define PF12_AOUT_PC_WAIT       (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
-#define PF13_AOUT_PC_CD2        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
-#define PF14_AOUT_PC_CD1        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
-
-#endif /* ifndef __MACH_IOMUX_MX21_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx25.h b/arch/arm/mach-imx/iomux-mx25.h
deleted file mode 100644
index be51e838375..00000000000
--- a/arch/arm/mach-imx/iomux-mx25.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * arch/arm/plat-mxc/include/mach/iomux-mx25.h
- *
- * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
- *
- * based on arch/arm/mach-mx25/mx25_pins.h
- *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * and
- * arch/arm/plat-mxc/include/mach/iomux-mx35.h
- *    Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_IOMUX_MX25_H__
-#define __MACH_IOMUX_MX25_H__
-
-#include "iomux-v3.h"
-
-/*
- * IOMUX/PAD Bit field definitions
- */
-
-#define MX25_PAD_A10__A10               IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A10__GPIO_4_0          IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A13__A13               IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A13__GPIO_4_1          IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A14__A14               IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A14__GPIO_2_0          IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A15__A15               IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A15__GPIO_2_1          IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A16__A16               IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A16__GPIO_2_2          IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A17__A17               IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A17__GPIO_2_3          IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A23__A23               IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A23__GPIO_2_9          IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__GPIO_2_12         IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EB1__EB1               IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__AUD4_RXD          IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__GPIO_2_13         IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_OE__OE                 IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__AUD4_TXC           IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__GPIO_2_14          IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS0__CS0               IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__NF_CE3            IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__NF_CE1            IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__NF_CE2            IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__UART5_TXD_MUX     IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__GPIO_3_23         IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LBA__LBA               IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__UART5_RXD_MUX     IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__GPIO_3_24         IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_BCLK__BCLK             IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BCLK__GPIO_4_4         IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_RW__RW                 IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__AUD4_TXFS          IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__GPIO_3_25          IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFWE_B__NFWE_B         IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWE_B__GPIO_3_26      IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFRE_B__NFRE_B         IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFRE_B__GPIO_3_27      IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFALE__NFALE           IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFALE__GPIO_3_28       IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFCLE__NFCLE           IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFCLE__GPIO_3_29       IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFWP_B__NFWP_B         IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWP_B__GPIO_3_30      IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFRB__NFRB             IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D12__GPIO_4_8          IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D11__D11               IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D11__GPIO_4_9          IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D10__D10               IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__GPIO_4_10         IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__USBOTG_OC         IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_D9__D9                 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__GPIO_4_11          IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__USBH2_PWR          IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
-
-#define MX25_PAD_D8__D8                 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__GPIO_4_12          IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__USBH2_OC           IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_D7__D7                 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D7__GPIO_4_13          IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D6__D6                 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D6__GPIO_4_14          IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D5__D5                 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D5__GPIO_4_15          IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D4__D4                 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D4__GPIO_4_16          IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D3__D3                 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D3__GPIO_4_17          IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D2__D2                 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D2__GPIO_4_18          IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D1__D1                 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D1__GPIO_4_19          IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_VSYNC__VSYNC           IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSYNC__GPIO_1_23       IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LSCLK__LSCLK           IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LSCLK__GPIO_1_24       IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_OE_ACD__OE_ACD         IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__PWM4_PWMO    IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__USBH2_OC          IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__CSPI3_MOSI     IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__CSPI3_MISO     IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__CSPI3_SCLK     IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__CSPI3_RDY      IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D7__CSI_D7         IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D7__GPIO_1_6       IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D8__CSI_D8         IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D8__GPIO_1_7       IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D9__CSI_D9         IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D9__GPIO_4_21      IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_MCLK__CSI_MCLK     IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_MCLK__GPIO_1_8     IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC   IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_VSYNC__GPIO_1_9    IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC   IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_HSYNC__GPIO_1_10   IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11  IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_I2C1_CLK__I2C1_CLK     IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_CLK__GPIO_1_12    IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_I2C1_DAT__I2C1_DAT     IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_DAT__GPIO_1_13    IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14  IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MISO__GPIO_1_15  IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0   IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS0__GPIO_1_16   IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1   IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS1__GPIO_1_17   IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18  IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY   IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_CSPI1_RDY__GPIO_2_22   IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_UART1_RXD__GPIO_4_22   IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_TXD__GPIO_4_23   IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_RTS__CSI_D0      IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_RTS__GPIO_4_24   IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_CTS__CSI_D1      IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_CTS__GPIO_4_25   IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RXD__GPIO_4_26   IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA0__GPIO_2_25   IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA1__AUD7_RXD    IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define KPP_CTL_ROW     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define KPP_CTL_COL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL0__AUD5_TXD     IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL1__AUD5_RXD     IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL2__UART4_RTS    IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL2__AUD5_TXC     IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL3__UART4_CTS    IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL3__AUD5_TXFS    IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_MDIO__FEC_MDIO     IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13  IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_RTCK__RTCK             IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__OWIRE            IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__GPIO_3_14        IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_DE_B__DE_B             IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_DE_B__GPIO_2_20        IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_TDO__TDO               IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_GPIO_A__GPIO_A         IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_A__CAN1_TX        IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_A__USBOTG_PWR     IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
-
-#define MX25_PAD_GPIO_B__GPIO_B         IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_B__CAN1_RX        IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_B__USBOTG_OC      IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_GPIO_C__GPIO_C         IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-
-#define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
-
-#define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__AUD7_TXC       IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15  IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ   IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS   IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__GPIO_3_17   IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK   IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__GPIO_3_18   IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__AUD7_RXD   IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__GPIO_3_19  IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CLKO__CLKO             IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CLKO__GPIO_2_21        IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE0__GPIO_4_30  IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__GPIO_4_31  IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CTL_GRP_DVS_MISC       IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_FEC        IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_JTAG       IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_NFC        IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSI        IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_WEIM       IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_DDR        IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CRM        IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_KPP        IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_SDHC1      IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_LCD        IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_UART       IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_NFC        IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CSI        IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSPI1      IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DDRTYPE        IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_SDHC1      IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_LCD        IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX25_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx27.h b/arch/arm/mach-imx/iomux-mx27.h
deleted file mode 100644
index 218e99e89e8..00000000000
--- a/arch/arm/mach-imx/iomux-mx27.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX27_H__
-#define __MACH_IOMUX_MX27_H__
-
-#include "iomux-mx2x.h"
-#include "iomux-v1.h"
-
-/* Primary GPIO pin functions */
-
-#define PA0_PF_USBH2_CLK        (GPIO_PORTA | GPIO_PF | 0)
-#define PA1_PF_USBH2_DIR        (GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_USBH2_DATA7      (GPIO_PORTA | GPIO_PF | 2)
-#define PA3_PF_USBH2_NXT        (GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_USBH2_STP        (GPIO_PORTA | GPIO_PF | 4)
-#define PB22_PF_USBH1_SUSP      (GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_RCV       (GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
-#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
-#define PC7_PF_USBOTG_DATA5     (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
-#define PC8_PF_USBOTG_DATA6     (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
-#define PC9_PF_USBOTG_DATA0     (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_USBOTG_DATA2    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
-#define PC11_PF_USBOTG_DATA1    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_USBOTG_DATA4    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
-#define PC13_PF_USBOTG_DATA3    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
-#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
-#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
-#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
-#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
-#define PD0_PF_SD3_CMD          (GPIO_PORTD | GPIO_PF | 0)
-#define PD1_PF_SD3_CLK          (GPIO_PORTD | GPIO_PF | 1)
-#define PD2_PF_ATA_DATA0        (GPIO_PORTD | GPIO_PF | 2)
-#define PD3_PF_ATA_DATA1        (GPIO_PORTD | GPIO_PF | 3)
-#define PD4_PF_ATA_DATA2        (GPIO_PORTD | GPIO_PF | 4)
-#define PD5_PF_ATA_DATA3        (GPIO_PORTD | GPIO_PF | 5)
-#define PD6_PF_ATA_DATA4        (GPIO_PORTD | GPIO_PF | 6)
-#define PD7_PF_ATA_DATA5        (GPIO_PORTD | GPIO_PF | 7)
-#define PD8_PF_ATA_DATA6        (GPIO_PORTD | GPIO_PF | 8)
-#define PD9_PF_ATA_DATA7        (GPIO_PORTD | GPIO_PF | 9)
-#define PD10_PF_ATA_DATA8       (GPIO_PORTD | GPIO_PF | 10)
-#define PD11_PF_ATA_DATA9       (GPIO_PORTD | GPIO_PF | 11)
-#define PD12_PF_ATA_DATA10      (GPIO_PORTD | GPIO_PF | 12)
-#define PD13_PF_ATA_DATA11      (GPIO_PORTD | GPIO_PF | 13)
-#define PD14_PF_ATA_DATA12      (GPIO_PORTD | GPIO_PF | 14)
-#define PD15_PF_ATA_DATA13      (GPIO_PORTD | GPIO_PF | 15)
-#define PD16_PF_ATA_DATA14      (GPIO_PORTD | GPIO_PF | 16)
-#define PE0_PF_USBOTG_NXT       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
-#define PE1_PF_USBOTG_STP       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
-#define PE2_PF_USBOTG_DIR       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
-#define PE24_PF_USBOTG_CLK      (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
-#define PE25_PF_USBOTG_DATA7    (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
-#define PF1_PF_NFCLE            (GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCE             (GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_PC_POE           (GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_PC_RW            (GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_PC_IOIS16        (GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_PC_RST          (GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_PC_BVD2         (GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_PC_BVD1         (GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_PC_VS2          (GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_PC_VS1          (GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_PC_PWRON        (GPIO_PORTF | GPIO_PF | 16)
-#define PF17_PF_PC_READY        (GPIO_PORTF | GPIO_PF | 17)
-#define PF18_PF_PC_WAIT         (GPIO_PORTF | GPIO_PF | 18)
-#define PF19_PF_PC_CD2          (GPIO_PORTF | GPIO_PF | 19)
-#define PF20_PF_PC_CD1          (GPIO_PORTF | GPIO_PF | 20)
-#define PF23_PF_ATA_DATA15      (GPIO_PORTF | GPIO_PF | 23)
-
-/* Alternate GPIO pin functions */
-
-#define PB4_AF_MSHC_DATA0       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
-#define PB5_AF_MSHC_DATA1       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
-#define PB6_AF_MSHC_DATA2       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
-#define PB7_AF_MSHC_DATA4       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
-#define PB8_AF_MSHC_BS          (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
-#define PB9_AF_MSHC_SCLK        (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
-#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
-#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
-#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
-#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
-#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
-#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
-#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
-#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
-#define PC8_AF_FEC_MDIO         (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
-#define PC24_AF_GPT5_TOUT       (GPIO_PORTC | GPIO_AF | 24)
-#define PC25_AF_GPT5_TIN        (GPIO_PORTC | GPIO_AF | 25)
-#define PC26_AF_GPT4_TOUT       (GPIO_PORTC | GPIO_AF | 26)
-#define PC27_AF_GPT4_TIN        (GPIO_PORTC | GPIO_AF | 27)
-#define PD1_AF_ETMTRACE_PKT15   (GPIO_PORTD | GPIO_AF | 1)
-#define PD6_AF_ETMTRACE_PKT14   (GPIO_PORTD | GPIO_AF | 6)
-#define PD7_AF_ETMTRACE_PKT13   (GPIO_PORTD | GPIO_AF | 7)
-#define PD9_AF_ETMTRACE_PKT12   (GPIO_PORTD | GPIO_AF | 9)
-#define PD2_AF_SD3_D0           (GPIO_PORTD | GPIO_AF | 2)
-#define PD3_AF_SD3_D1           (GPIO_PORTD | GPIO_AF | 3)
-#define PD4_AF_SD3_D2           (GPIO_PORTD | GPIO_AF | 4)
-#define PD5_AF_SD3_D3           (GPIO_PORTD | GPIO_AF | 5)
-#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
-#define PD10_AF_ETMTRACE_PKT11  (GPIO_PORTD | GPIO_AF | 10)
-#define PD11_AF_ETMTRACE_PKT10  (GPIO_PORTD | GPIO_AF | 11)
-#define PD12_AF_ETMTRACE_PKT9   (GPIO_PORTD | GPIO_AF | 12)
-#define PD13_AF_ETMTRACE_PKT8   (GPIO_PORTD | GPIO_AF | 13)
-#define PD14_AF_ETMTRACE_PKT7   (GPIO_PORTD | GPIO_AF | 14)
-#define PD15_AF_ETMTRACE_PKT6   (GPIO_PORTD | GPIO_AF | 15)
-#define PD16_AF_ETMTRACE_PKT5   (GPIO_PORTD | GPIO_AF | 16)
-#define PF1_AF_ETMTRACE_PKT0    (GPIO_PORTF | GPIO_AF | 1)
-#define PF3_AF_ETMTRACE_PKT2    (GPIO_PORTF | GPIO_AF | 3)
-#define PF5_AF_ETMPIPESTAT11    (GPIO_PORTF | GPIO_AF | 5)
-#define PF7_AF_ATA_BUFFER_EN    (GPIO_PORTF | GPIO_AF | 7)
-#define PF8_AF_ATA_IORDY        (GPIO_PORTF | GPIO_AF | 8)
-#define PF9_AF_ATA_INTRQ        (GPIO_PORTF | GPIO_AF | 9)
-#define PF10_AF_ATA_RESET       (GPIO_PORTF | GPIO_AF | 10)
-#define PF11_AF_ATA_DMACK       (GPIO_PORTF | GPIO_AF | 11)
-#define PF12_AF_ATA_DMAREQ      (GPIO_PORTF | GPIO_AF | 12)
-#define PF13_AF_ATA_DA0         (GPIO_PORTF | GPIO_AF | 13)
-#define PF14_AF_ATA_DA1         (GPIO_PORTF | GPIO_AF | 14)
-#define PF15_AF_ETMTRACE_SYNC   (GPIO_PORTF | GPIO_AF | 15)
-#define PF16_AF_ATA_DA2         (GPIO_PORTF | GPIO_AF | 16)
-#define PF17_AF_ATA_CS0         (GPIO_PORTF | GPIO_AF | 17)
-#define PF18_AF_ATA_CS1         (GPIO_PORTF | GPIO_AF | 18)
-#define PF19_AF_ATA_DIOW        (GPIO_PORTF | GPIO_AF | 19)
-#define PF20_AF_ATA_DIOR        (GPIO_PORTF | GPIO_AF | 20)
-#define PF22_AF_ETMTRACE_CLK    (GPIO_PORTF | GPIO_AF | 22)
-#define PF23_AF_ETMTRACE_PKT4   (GPIO_PORTF | GPIO_AF | 23)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SSI1_MCLK      (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PC15_AIN_GPT6_TOUT      (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
-#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
-#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
-#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
-#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
-#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
-#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
-#define PD27_AIN_EXT_DMA_GRANT  (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
-#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SSI2_MCLK      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-
-/* CIN GPIO pin functions */
-
-#define PD2_CIN_SLCDC1_DAT0     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
-#define PD3_CIN_SLCDC1_DAT1     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
-#define PD4_CIN_SLCDC1_DAT2     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
-#define PD5_CIN_SLCDC1_DAT3     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
-#define PD6_CIN_SLCDC1_DAT4     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
-#define PD7_CIN_SLCDC1_DAT5     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
-#define PD8_CIN_SLCDC1_DAT6     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
-#define PD9_CIN_SLCDC1_DAT7     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
-#define PD10_CIN_SLCDC1_DAT8    (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
-#define PD11_CIN_SLCDC1_DAT9    (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
-#define PD12_CIN_SLCDC1_DAT10   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
-#define PD13_CIN_SLCDC1_DAT11   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
-#define PD14_CIN_SLCDC1_DAT12   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
-#define PD15_CIN_SLCDC1_DAT13   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
-#define PD16_CIN_SLCDC1_DAT14   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
-#define PD23_CIN_SLCDC1_DAT15   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
-#define PF27_CIN_EXT_DMA_GRANT  (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
-/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
-
-/* AOUT GPIO pin functions */
-
-#define PC14_AOUT_GPT6_TIN      (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
-#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
-#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
-#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
-#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
-#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
-#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
-#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
-#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
-#define PD14_AOUT_FEC_RX_CLK    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
-#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
-
-/* BOUT GPIO pin functions */
-
-#define PC17_BOUT_PC_IOIS16     (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
-#define PC18_BOUT_PC_BVD2       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
-#define PC19_BOUT_PC_BVD1       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
-#define PC28_BOUT_PC_BVD2       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
-#define PC29_BOUT_PC_VS1        (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
-#define PC30_BOUT_PC_READY      (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
-#define PC31_BOUT_PC_WAIT       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
-
-#endif /* __MACH_IOMUX_MX27_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx2x.h b/arch/arm/mach-imx/iomux-mx2x.h
deleted file mode 100644
index 7a9b20abda0..00000000000
--- a/arch/arm/mach-imx/iomux-mx2x.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX2x_H__
-#define __MACH_IOMUX_MX2x_H__
-
-/* Primary GPIO pin functions */
-
-#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
-#define PA6_PF_LD0              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
-#define PA7_PF_LD1              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
-#define PA8_PF_LD2              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
-#define PA9_PF_LD3              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
-#define PA10_PF_LD4             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
-#define PA11_PF_LD5             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
-#define PA12_PF_LD6             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
-#define PA13_PF_LD7             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
-#define PA14_PF_LD8             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
-#define PA15_PF_LD9             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
-#define PA16_PF_LD10            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
-#define PA17_PF_LD11            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
-#define PA18_PF_LD12            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
-#define PA19_PF_LD13            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
-#define PA20_PF_LD14            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
-#define PA21_PF_LD15            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
-#define PA22_PF_LD16            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
-#define PA23_PF_LD17            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
-#define PA24_PF_REV             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
-#define PA25_PF_CLS             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
-#define PA26_PF_PS              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
-#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
-#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
-#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
-#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
-#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
-#define PB4_PF_SD2_D0           (GPIO_PORTB | GPIO_PF | 4)
-#define PB5_PF_SD2_D1           (GPIO_PORTB | GPIO_PF | 5)
-#define PB6_PF_SD2_D2           (GPIO_PORTB | GPIO_PF | 6)
-#define PB7_PF_SD2_D3           (GPIO_PORTB | GPIO_PF | 7)
-#define PB8_PF_SD2_CMD          (GPIO_PORTB | GPIO_PF | 8)
-#define PB9_PF_SD2_CLK          (GPIO_PORTB | GPIO_PF | 9)
-#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
-#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
-#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
-#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
-#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
-#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
-#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
-#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
-#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
-#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
-#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
-#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
-#define PB23_PF_USB_PWR         (GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USB_OC          (GPIO_PORTB | GPIO_PF | 24)
-#define PB26_PF_USBH1_FS        (GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBH1_OE        (GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_USBH1_TXDM      (GPIO_PORTB | GPIO_PF | 28)
-#define PB29_PF_USBH1_TXDP      (GPIO_PORTB | GPIO_PF | 29)
-#define PB30_PF_USBH1_RXDM      (GPIO_PORTB | GPIO_PF | 30)
-#define PB31_PF_USBH1_RXDP      (GPIO_PORTB | GPIO_PF | 31)
-#define PC14_PF_TOUT            (GPIO_PORTC | GPIO_PF | 14)
-#define PC15_PF_TIN             (GPIO_PORTC | GPIO_PF | 15)
-#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
-#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
-#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
-#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
-#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
-#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
-#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
-#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
-#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
-#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
-#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
-#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
-#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
-#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
-#define PD19_PF_CSPI2_SS2       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
-#define PD20_PF_CSPI2_SS1       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
-#define PD21_PF_CSPI2_SS0       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
-#define PD22_PF_CSPI2_SCLK      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
-#define PD23_PF_CSPI2_MISO      (GPIO_PORTD | GPIO_PF | GPIO_IN | 23)
-#define PD24_PF_CSPI2_MOSI      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
-#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
-#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
-#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
-#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
-#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
-#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
-#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
-#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
-#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
-#define PE5_PF_PWMO             (GPIO_PORTE | GPIO_PF | 5)
-#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
-#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
-#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
-#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
-#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
-#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
-#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
-#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
-#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
-#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
-#define PE16_PF_RTCK            (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
-#define PE17_PF_RESET_OUT       (GPIO_PORTE | GPIO_PF | 17)
-#define PE18_PF_SD1_D0          (GPIO_PORTE | GPIO_PF | 18)
-#define PE19_PF_SD1_D1          (GPIO_PORTE | GPIO_PF | 19)
-#define PE20_PF_SD1_D2          (GPIO_PORTE | GPIO_PF | 20)
-#define PE21_PF_SD1_D3          (GPIO_PORTE | GPIO_PF | 21)
-#define PE22_PF_SD1_CMD         (GPIO_PORTE | GPIO_PF | 22)
-#define PE23_PF_SD1_CLK         (GPIO_PORTE | GPIO_PF | 23)
-#define PF0_PF_NRFB             (GPIO_PORTF | GPIO_PF | 0)
-#define PF2_PF_NFWP             (GPIO_PORTF | GPIO_PF | 2)
-#define PF4_PF_NFALE            (GPIO_PORTF | GPIO_PF | 4)
-#define PF5_PF_NFRE             (GPIO_PORTF | GPIO_PF | 5)
-#define PF6_PF_NFWE             (GPIO_PORTF | GPIO_PF | 6)
-#define PF15_PF_CLKO            (GPIO_PORTF | GPIO_PF | 15)
-#define PF21_PF_CS4             (GPIO_PORTF | GPIO_PF | 21)
-#define PF22_PF_CS5             (GPIO_PORTF | GPIO_PF | 22)
-
-/* Alternate GPIO pin functions */
-
-#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
-#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
-#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
-#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
-#define PC28_AF_SLCDC2_D0       (GPIO_PORTC | GPIO_AF | 28)
-#define PC29_AF_SLCDC2_RS       (GPIO_PORTC | GPIO_AF | 29)
-#define PC30_AF_SLCDC2_CS       (GPIO_PORTC | GPIO_AF | 30)
-#define PC31_AF_SLCDC2_CLK      (GPIO_PORTC | GPIO_AF | 31)
-#define PD19_AF_USBH2_DATA4     (GPIO_PORTD | GPIO_AF | 19)
-#define PD20_AF_USBH2_DATA3     (GPIO_PORTD | GPIO_AF | 20)
-#define PD21_AF_USBH2_DATA6     (GPIO_PORTD | GPIO_AF | 21)
-#define PD22_AF_USBH2_DATA0     (GPIO_PORTD | GPIO_AF | 22)
-#define PD23_AF_USBH2_DATA2     (GPIO_PORTD | GPIO_AF | 23)
-#define PD24_AF_USBH2_DATA1     (GPIO_PORTD | GPIO_AF | 24)
-#define PD26_AF_USBH2_DATA5     (GPIO_PORTD | GPIO_AF | 26)
-#define PE0_AF_KP_COL6          (GPIO_PORTE | GPIO_AF | 0)
-#define PE1_AF_KP_ROW6          (GPIO_PORTE | GPIO_AF | 1)
-#define PE2_AF_KP_ROW7          (GPIO_PORTE | GPIO_AF | 2)
-#define PE3_AF_KP_COL7          (GPIO_PORTE | GPIO_AF | 3)
-#define PE4_AF_KP_ROW7          (GPIO_PORTE | GPIO_AF | 4)
-#define PE6_AF_KP_COL6          (GPIO_PORTE | GPIO_AF | 6)
-#define PE7_AF_KP_ROW6          (GPIO_PORTE | GPIO_AF | 7)
-#define PE16_AF_OWIRE           (GPIO_PORTE | GPIO_AF | 16)
-#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
-#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
-#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
-#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
-
-/* AIN GPIO pin functions */
-
-#define PA6_AIN_SLCDC1_DAT0     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
-#define PA7_AIN_SLCDC1_DAT1     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
-#define PA8_AIN_SLCDC1_DAT2     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
-#define PA0_AIN_SLCDC1_DAT3     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
-#define PA11_AIN_SLCDC1_DAT5    (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
-#define PA13_AIN_SLCDC1_DAT7    (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
-#define PA15_AIN_SLCDC1_DAT9    (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
-#define PA17_AIN_SLCDC1_DAT11   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
-#define PA19_AIN_SLCDC1_DAT13   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
-#define PA21_AIN_SLCDC1_DAT15   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
-#define PA22_AIN_EXT_DMAGRANT   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
-#define PA24_AIN_SLCDC1_D0      (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
-#define PA25_AIN_SLCDC1_RS      (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
-#define PA26_AIN_SLCDC1_CS      (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
-#define PA27_AIN_SLCDC1_CLK     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
-#define PB6_AIN_SLCDC1_D0       (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
-#define PB7_AIN_SLCDC1_RS       (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
-#define PB8_AIN_SLCDC1_CS       (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
-#define PB9_AIN_SLCDC1_CLK      (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
-#define PB25_AIN_SLCDC1_DAT0    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
-#define PB26_AIN_SLCDC1_DAT1    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
-#define PB27_AIN_SLCDC1_DAT2    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
-#define PB28_AIN_SLCDC1_DAT3    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
-#define PB29_AIN_SLCDC1_DAT4    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
-#define PB30_AIN_SLCDC1_DAT5    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
-#define PB31_AIN_SLCDC1_DAT6    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
-#define PC5_AIN_SLCDC1_DAT7     (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
-#define PC6_AIN_SLCDC1_DAT8     (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
-#define PC7_AIN_SLCDC1_DAT9     (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
-#define PC8_AIN_SLCDC1_DAT10    (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
-#define PC9_AIN_SLCDC1_DAT11    (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
-#define PC10_AIN_SLCDC1_DAT12   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
-#define PC11_AIN_SLCDC1_DAT13   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
-#define PC12_AIN_SLCDC1_DAT14   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
-#define PC13_AIN_SLCDC1_DAT15   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
-#define PE5_AIN_PC_SPKOUT       (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PE5_BIN_TOUT2           (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
-
-/* CIN GPIO pin functions */
-
-#define PA14_CIN_SLCDC1_DAT0    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
-#define PA15_CIN_SLCDC1_DAT1    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
-#define PA16_CIN_SLCDC1_DAT2    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
-#define PA17_CIN_SLCDC1_DAT3    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
-#define PA18_CIN_SLCDC1_DAT4    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
-#define PA19_CIN_SLCDC1_DAT5    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
-#define PA20_CIN_SLCDC1_DAT6    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
-#define PA21_CIN_SLCDC1_DAT7    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
-#define PB30_CIN_UART4_CTS      (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
-#define PE5_CIN_TOUT3           (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
-
-/* AOUT GPIO pin functions */
-
-#define PB29_AOUT_UART4_RXD     (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
-#define PB31_AOUT_UART4_RTS     (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
-#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
-#define PC15_AOUT_WKGD          (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
-#define PF21_AOUT_DTACK         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
-
-#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
deleted file mode 100644
index f79f78a1c0e..00000000000
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ /dev/null
@@ -1,753 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX3_H__
-#define __MACH_IOMUX_MX3_H__
-
-#include <linux/types.h>
-/*
- * various IOMUX output functions
- */
-
-#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
-#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
-#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
-#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
-#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
-#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
-#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
-#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
-#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
-#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
-#define IOMUX_ICONFIG_FUNC  2           /* used as function */
-#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
-#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
-
-#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
-#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
-#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
-#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
-
-/*
- * various IOMUX pad functions
- */
-enum iomux_pad_config {
-        PAD_CTL_NOLOOPBACK      = 0x0 << 9,
-        PAD_CTL_LOOPBACK        = 0x1 << 9,
-        PAD_CTL_PKE_NONE        = 0x0 << 8,
-        PAD_CTL_PKE_ENABLE      = 0x1 << 8,
-        PAD_CTL_PUE_KEEPER      = 0x0 << 7,
-        PAD_CTL_PUE_PUD         = 0x1 << 7,
-        PAD_CTL_100K_PD         = 0x0 << 5,
-        PAD_CTL_100K_PU         = 0x1 << 5,
-        PAD_CTL_47K_PU          = 0x2 << 5,
-        PAD_CTL_22K_PU          = 0x3 << 5,
-        PAD_CTL_HYS_CMOS        = 0x0 << 4,
-        PAD_CTL_HYS_SCHMITZ     = 0x1 << 4,
-        PAD_CTL_ODE_CMOS        = 0x0 << 3,
-        PAD_CTL_ODE_OpenDrain   = 0x1 << 3,
-        PAD_CTL_DRV_NORMAL      = 0x0 << 1,
-        PAD_CTL_DRV_HIGH        = 0x1 << 1,
-        PAD_CTL_DRV_MAX         = 0x2 << 1,
-        PAD_CTL_SRE_SLOW        = 0x0 << 0,
-        PAD_CTL_SRE_FAST        = 0x1 << 0
-};
-
-/*
- * various IOMUX general purpose functions
- */
-enum iomux_gp_func {
-        MUX_PGP_FIRI                    = 1 << 0,
-        MUX_DDR_MODE                    = 1 << 1,
-        MUX_PGP_CSPI_BB                 = 1 << 2,
-        MUX_PGP_ATA_1                   = 1 << 3,
-        MUX_PGP_ATA_2                   = 1 << 4,
-        MUX_PGP_ATA_3                   = 1 << 5,
-        MUX_PGP_ATA_4                   = 1 << 6,
-        MUX_PGP_ATA_5                   = 1 << 7,
-        MUX_PGP_ATA_6                   = 1 << 8,
-        MUX_PGP_ATA_7                   = 1 << 9,
-        MUX_PGP_ATA_8                   = 1 << 10,
-        MUX_PGP_UH2                     = 1 << 11,
-        MUX_SDCTL_CSD0_SEL              = 1 << 12,
-        MUX_SDCTL_CSD1_SEL              = 1 << 13,
-        MUX_CSPI1_UART3                 = 1 << 14,
-        MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
-        MUX_TAMPER_DETECT_EN            = 1 << 16,
-        MUX_PGP_USB_4WIRE               = 1 << 17,
-        MUX_PGP_USB_COMMON              = 1 << 18,
-        MUX_SDHC_MEMSTICK1              = 1 << 19,
-        MUX_SDHC_MEMSTICK2              = 1 << 20,
-        MUX_PGP_SPLL_BYP                = 1 << 21,
-        MUX_PGP_UPLL_BYP                = 1 << 22,
-        MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
-        MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
-        MUX_CSPI3_UART5_SEL             = 1 << 25,
-        MUX_PGP_ATA_9                   = 1 << 26,
-        MUX_PGP_USB_SUSPEND             = 1 << 27,
-        MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
-        MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
-        MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
-        MUX_CLKO_DDR_MODE               = 1 << 31,
-};
-
-/*
- * setups a single pin:
- *      - reserves the pin so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
- *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
- */
-int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
-/*
- * setups mutliple pins
- * convenient way to call the above function with tables
- */
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
-                const char *label);
-
-/*
- * releases a single pin:
- *      - make it available for a future use by another driver
- *      - frees the GPIO if the pin was configured as GPIO
- *      - DOES NOT reconfigure the IOMUX in its reset state
- */
-void mxc_iomux_release_pin(unsigned int pin);
-/*
- * releases multiple pins
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- */
-void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
-
-/*
- * This function only configures the iomux hardware.
- * It is called by the setup functions and should not be called directly anymore.
- * It is here visible for backward compatibility
- */
-int mxc_iomux_mode(unsigned int pin_mode);
-
-#define IOMUX_PADNUM_MASK       0x1ff
-#define IOMUX_GPIONUM_SHIFT     9
-#define IOMUX_GPIONUM_MASK      (0xff << IOMUX_GPIONUM_SHIFT)
-#define IOMUX_MODE_SHIFT        17
-#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
-
-#define IOMUX_PIN(gpionum, padnum) \
-        (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
-         (padnum & IOMUX_PADNUM_MASK))
-
-#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
-
-#define IOMUX_TO_GPIO(iomux_pin) \
-        ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-
-enum iomux_pins {
-        MX31_PIN_TTM_PAD        = IOMUX_PIN(0xff,   0),
-        MX31_PIN_CSPI3_SPI_RDY  = IOMUX_PIN(0xff,   1),
-        MX31_PIN_CSPI3_SCLK     = IOMUX_PIN(0xff,   2),
-        MX31_PIN_CSPI3_MISO     = IOMUX_PIN(0xff,   3),
-        MX31_PIN_CSPI3_MOSI     = IOMUX_PIN(0xff,   4),
-        MX31_PIN_CLKSS          = IOMUX_PIN(0xff,   5),
-        MX31_PIN_CE_CONTROL     = IOMUX_PIN(0xff,   6),
-        MX31_PIN_ATA_RESET_B    = IOMUX_PIN(95,     7),
-        MX31_PIN_ATA_DMACK      = IOMUX_PIN(94,     8),
-        MX31_PIN_ATA_DIOW       = IOMUX_PIN(93,     9),
-        MX31_PIN_ATA_DIOR       = IOMUX_PIN(92,    10),
-        MX31_PIN_ATA_CS1        = IOMUX_PIN(91,    11),
-        MX31_PIN_ATA_CS0        = IOMUX_PIN(90,    12),
-        MX31_PIN_SD1_DATA3      = IOMUX_PIN(63,    13),
-        MX31_PIN_SD1_DATA2      = IOMUX_PIN(62,    14),
-        MX31_PIN_SD1_DATA1      = IOMUX_PIN(61,    15),
-        MX31_PIN_SD1_DATA0      = IOMUX_PIN(60,    16),
-        MX31_PIN_SD1_CLK        = IOMUX_PIN(59,    17),
-        MX31_PIN_SD1_CMD        = IOMUX_PIN(58,    18),
-        MX31_PIN_D3_SPL         = IOMUX_PIN(0xff,  19),
-        MX31_PIN_D3_CLS         = IOMUX_PIN(0xff,  20),
-        MX31_PIN_D3_REV         = IOMUX_PIN(0xff,  21),
-        MX31_PIN_CONTRAST       = IOMUX_PIN(0xff,  22),
-        MX31_PIN_VSYNC3         = IOMUX_PIN(0xff,  23),
-        MX31_PIN_READ           = IOMUX_PIN(0xff,  24),
-        MX31_PIN_WRITE          = IOMUX_PIN(0xff,  25),
-        MX31_PIN_PAR_RS         = IOMUX_PIN(0xff,  26),
-        MX31_PIN_SER_RS         = IOMUX_PIN(89,    27),
-        MX31_PIN_LCS1           = IOMUX_PIN(88,    28),
-        MX31_PIN_LCS0           = IOMUX_PIN(87,    29),
-        MX31_PIN_SD_D_CLK       = IOMUX_PIN(86,    30),
-        MX31_PIN_SD_D_IO        = IOMUX_PIN(85,    31),
-        MX31_PIN_SD_D_I         = IOMUX_PIN(84,    32),
-        MX31_PIN_DRDY0          = IOMUX_PIN(0xff,  33),
-        MX31_PIN_FPSHIFT        = IOMUX_PIN(0xff,  34),
-        MX31_PIN_HSYNC          = IOMUX_PIN(0xff,  35),
-        MX31_PIN_VSYNC0         = IOMUX_PIN(0xff,  36),
-        MX31_PIN_LD17           = IOMUX_PIN(0xff,  37),
-        MX31_PIN_LD16           = IOMUX_PIN(0xff,  38),
-        MX31_PIN_LD15           = IOMUX_PIN(0xff,  39),
-        MX31_PIN_LD14           = IOMUX_PIN(0xff,  40),
-        MX31_PIN_LD13           = IOMUX_PIN(0xff,  41),
-        MX31_PIN_LD12           = IOMUX_PIN(0xff,  42),
-        MX31_PIN_LD11           = IOMUX_PIN(0xff,  43),
-        MX31_PIN_LD10           = IOMUX_PIN(0xff,  44),
-        MX31_PIN_LD9            = IOMUX_PIN(0xff,  45),
-        MX31_PIN_LD8            = IOMUX_PIN(0xff,  46),
-        MX31_PIN_LD7            = IOMUX_PIN(0xff,  47),
-        MX31_PIN_LD6            = IOMUX_PIN(0xff,  48),
-        MX31_PIN_LD5            = IOMUX_PIN(0xff,  49),
-        MX31_PIN_LD4            = IOMUX_PIN(0xff,  50),
-        MX31_PIN_LD3            = IOMUX_PIN(0xff,  51),
-        MX31_PIN_LD2            = IOMUX_PIN(0xff,  52),
-        MX31_PIN_LD1            = IOMUX_PIN(0xff,  53),
-        MX31_PIN_LD0            = IOMUX_PIN(0xff,  54),
-        MX31_PIN_USBH2_DATA1    = IOMUX_PIN(0xff,  55),
-        MX31_PIN_USBH2_DATA0    = IOMUX_PIN(0xff,  56),
-        MX31_PIN_USBH2_NXT      = IOMUX_PIN(0xff,  57),
-        MX31_PIN_USBH2_STP      = IOMUX_PIN(0xff,  58),
-        MX31_PIN_USBH2_DIR      = IOMUX_PIN(0xff,  59),
-        MX31_PIN_USBH2_CLK      = IOMUX_PIN(0xff,  60),
-        MX31_PIN_USBOTG_DATA7   = IOMUX_PIN(0xff,  61),
-        MX31_PIN_USBOTG_DATA6   = IOMUX_PIN(0xff,  62),
-        MX31_PIN_USBOTG_DATA5   = IOMUX_PIN(0xff,  63),
-        MX31_PIN_USBOTG_DATA4   = IOMUX_PIN(0xff,  64),
-        MX31_PIN_USBOTG_DATA3   = IOMUX_PIN(0xff,  65),
-        MX31_PIN_USBOTG_DATA2   = IOMUX_PIN(0xff,  66),
-        MX31_PIN_USBOTG_DATA1   = IOMUX_PIN(0xff,  67),
-        MX31_PIN_USBOTG_DATA0   = IOMUX_PIN(0xff,  68),
-        MX31_PIN_USBOTG_NXT     = IOMUX_PIN(0xff,  69),
-        MX31_PIN_USBOTG_STP     = IOMUX_PIN(0xff,  70),
-        MX31_PIN_USBOTG_DIR     = IOMUX_PIN(0xff,  71),
-        MX31_PIN_USBOTG_CLK     = IOMUX_PIN(0xff,  72),
-        MX31_PIN_USB_BYP        = IOMUX_PIN(31,    73),
-        MX31_PIN_USB_OC         = IOMUX_PIN(30,    74),
-        MX31_PIN_USB_PWR        = IOMUX_PIN(29,    75),
-        MX31_PIN_SJC_MOD        = IOMUX_PIN(0xff,  76),
-        MX31_PIN_DE_B           = IOMUX_PIN(0xff,  77),
-        MX31_PIN_TRSTB          = IOMUX_PIN(0xff,  78),
-        MX31_PIN_TDO            = IOMUX_PIN(0xff,  79),
-        MX31_PIN_TDI            = IOMUX_PIN(0xff,  80),
-        MX31_PIN_TMS            = IOMUX_PIN(0xff,  81),
-        MX31_PIN_TCK            = IOMUX_PIN(0xff,  82),
-        MX31_PIN_RTCK           = IOMUX_PIN(0xff,  83),
-        MX31_PIN_KEY_COL7       = IOMUX_PIN(57,    84),
-        MX31_PIN_KEY_COL6       = IOMUX_PIN(56,    85),
-        MX31_PIN_KEY_COL5       = IOMUX_PIN(55,    86),
-        MX31_PIN_KEY_COL4       = IOMUX_PIN(54,    87),
-        MX31_PIN_KEY_COL3       = IOMUX_PIN(0xff,  88),
-        MX31_PIN_KEY_COL2       = IOMUX_PIN(0xff,  89),
-        MX31_PIN_KEY_COL1       = IOMUX_PIN(0xff,  90),
-        MX31_PIN_KEY_COL0       = IOMUX_PIN(0xff,  91),
-        MX31_PIN_KEY_ROW7       = IOMUX_PIN(53,    92),
-        MX31_PIN_KEY_ROW6       = IOMUX_PIN(52,    93),
-        MX31_PIN_KEY_ROW5       = IOMUX_PIN(51,    94),
-        MX31_PIN_KEY_ROW4       = IOMUX_PIN(50,    95),
-        MX31_PIN_KEY_ROW3       = IOMUX_PIN(0xff,  96),
-        MX31_PIN_KEY_ROW2       = IOMUX_PIN(0xff,  97),
-        MX31_PIN_KEY_ROW1       = IOMUX_PIN(0xff,  98),
-        MX31_PIN_KEY_ROW0       = IOMUX_PIN(0xff,  99),
-        MX31_PIN_BATT_LINE      = IOMUX_PIN(49,   100),
-        MX31_PIN_CTS2           = IOMUX_PIN(0xff, 101),
-        MX31_PIN_RTS2           = IOMUX_PIN(0xff, 102),
-        MX31_PIN_TXD2           = IOMUX_PIN(28,   103),
-        MX31_PIN_RXD2           = IOMUX_PIN(27,   104),
-        MX31_PIN_DTR_DCE2       = IOMUX_PIN(48,   105),
-        MX31_PIN_DCD_DTE1       = IOMUX_PIN(47,   106),
-        MX31_PIN_RI_DTE1        = IOMUX_PIN(46,   107),
-        MX31_PIN_DSR_DTE1       = IOMUX_PIN(45,   108),
-        MX31_PIN_DTR_DTE1       = IOMUX_PIN(44,   109),
-        MX31_PIN_DCD_DCE1       = IOMUX_PIN(43,   110),
-        MX31_PIN_RI_DCE1        = IOMUX_PIN(42,   111),
-        MX31_PIN_DSR_DCE1       = IOMUX_PIN(41,   112),
-        MX31_PIN_DTR_DCE1       = IOMUX_PIN(40,   113),
-        MX31_PIN_CTS1           = IOMUX_PIN(39,   114),
-        MX31_PIN_RTS1           = IOMUX_PIN(38,   115),
-        MX31_PIN_TXD1           = IOMUX_PIN(37,   116),
-        MX31_PIN_RXD1           = IOMUX_PIN(36,   117),
-        MX31_PIN_CSPI2_SPI_RDY  = IOMUX_PIN(0xff, 118),
-        MX31_PIN_CSPI2_SCLK     = IOMUX_PIN(0xff, 119),
-        MX31_PIN_CSPI2_SS2      = IOMUX_PIN(0xff, 120),
-        MX31_PIN_CSPI2_SS1      = IOMUX_PIN(0xff, 121),
-        MX31_PIN_CSPI2_SS0      = IOMUX_PIN(0xff, 122),
-        MX31_PIN_CSPI2_MISO     = IOMUX_PIN(0xff, 123),
-        MX31_PIN_CSPI2_MOSI     = IOMUX_PIN(0xff, 124),
-        MX31_PIN_CSPI1_SPI_RDY  = IOMUX_PIN(0xff, 125),
-        MX31_PIN_CSPI1_SCLK     = IOMUX_PIN(0xff, 126),
-        MX31_PIN_CSPI1_SS2      = IOMUX_PIN(0xff, 127),
-        MX31_PIN_CSPI1_SS1      = IOMUX_PIN(0xff, 128),
-        MX31_PIN_CSPI1_SS0      = IOMUX_PIN(0xff, 129),
-        MX31_PIN_CSPI1_MISO     = IOMUX_PIN(0xff, 130),
-        MX31_PIN_CSPI1_MOSI     = IOMUX_PIN(0xff, 131),
-        MX31_PIN_SFS6           = IOMUX_PIN(26,   132),
-        MX31_PIN_SCK6           = IOMUX_PIN(25,   133),
-        MX31_PIN_SRXD6          = IOMUX_PIN(24,   134),
-        MX31_PIN_STXD6          = IOMUX_PIN(23,   135),
-        MX31_PIN_SFS5           = IOMUX_PIN(0xff, 136),
-        MX31_PIN_SCK5           = IOMUX_PIN(0xff, 137),
-        MX31_PIN_SRXD5          = IOMUX_PIN(22,   138),
-        MX31_PIN_STXD5          = IOMUX_PIN(21,   139),
-        MX31_PIN_SFS4           = IOMUX_PIN(0xff, 140),
-        MX31_PIN_SCK4           = IOMUX_PIN(0xff, 141),
-        MX31_PIN_SRXD4          = IOMUX_PIN(20,   142),
-        MX31_PIN_STXD4          = IOMUX_PIN(19,   143),
-        MX31_PIN_SFS3           = IOMUX_PIN(0xff, 144),
-        MX31_PIN_SCK3           = IOMUX_PIN(0xff, 145),
-        MX31_PIN_SRXD3          = IOMUX_PIN(18,   146),
-        MX31_PIN_STXD3          = IOMUX_PIN(17,   147),
-        MX31_PIN_I2C_DAT        = IOMUX_PIN(0xff, 148),
-        MX31_PIN_I2C_CLK        = IOMUX_PIN(0xff, 149),
-        MX31_PIN_CSI_PIXCLK     = IOMUX_PIN(83,   150),
-        MX31_PIN_CSI_HSYNC      = IOMUX_PIN(82,   151),
-        MX31_PIN_CSI_VSYNC      = IOMUX_PIN(81,   152),
-        MX31_PIN_CSI_MCLK       = IOMUX_PIN(80,   153),
-        MX31_PIN_CSI_D15        = IOMUX_PIN(79,   154),
-        MX31_PIN_CSI_D14        = IOMUX_PIN(78,   155),
-        MX31_PIN_CSI_D13        = IOMUX_PIN(77,   156),
-        MX31_PIN_CSI_D12        = IOMUX_PIN(76,   157),
-        MX31_PIN_CSI_D11        = IOMUX_PIN(75,   158),
-        MX31_PIN_CSI_D10        = IOMUX_PIN(74,   159),
-        MX31_PIN_CSI_D9         = IOMUX_PIN(73,   160),
-        MX31_PIN_CSI_D8         = IOMUX_PIN(72,   161),
-        MX31_PIN_CSI_D7         = IOMUX_PIN(71,   162),
-        MX31_PIN_CSI_D6         = IOMUX_PIN(70,   163),
-        MX31_PIN_CSI_D5         = IOMUX_PIN(69,   164),
-        MX31_PIN_CSI_D4         = IOMUX_PIN(68,   165),
-        MX31_PIN_M_GRANT        = IOMUX_PIN(0xff, 166),
-        MX31_PIN_M_REQUEST      = IOMUX_PIN(0xff, 167),
-        MX31_PIN_PC_POE         = IOMUX_PIN(0xff, 168),
-        MX31_PIN_PC_RW_B        = IOMUX_PIN(0xff, 169),
-        MX31_PIN_IOIS16         = IOMUX_PIN(0xff, 170),
-        MX31_PIN_PC_RST         = IOMUX_PIN(0xff, 171),
-        MX31_PIN_PC_BVD2        = IOMUX_PIN(0xff, 172),
-        MX31_PIN_PC_BVD1        = IOMUX_PIN(0xff, 173),
-        MX31_PIN_PC_VS2         = IOMUX_PIN(0xff, 174),
-        MX31_PIN_PC_VS1         = IOMUX_PIN(0xff, 175),
-        MX31_PIN_PC_PWRON       = IOMUX_PIN(0xff, 176),
-        MX31_PIN_PC_READY       = IOMUX_PIN(0xff, 177),
-        MX31_PIN_PC_WAIT_B      = IOMUX_PIN(0xff, 178),
-        MX31_PIN_PC_CD2_B       = IOMUX_PIN(0xff, 179),
-        MX31_PIN_PC_CD1_B       = IOMUX_PIN(0xff, 180),
-        MX31_PIN_D0             = IOMUX_PIN(0xff, 181),
-        MX31_PIN_D1             = IOMUX_PIN(0xff, 182),
-        MX31_PIN_D2             = IOMUX_PIN(0xff, 183),
-        MX31_PIN_D3             = IOMUX_PIN(0xff, 184),
-        MX31_PIN_D4             = IOMUX_PIN(0xff, 185),
-        MX31_PIN_D5             = IOMUX_PIN(0xff, 186),
-        MX31_PIN_D6             = IOMUX_PIN(0xff, 187),
-        MX31_PIN_D7             = IOMUX_PIN(0xff, 188),
-        MX31_PIN_D8             = IOMUX_PIN(0xff, 189),
-        MX31_PIN_D9             = IOMUX_PIN(0xff, 190),
-        MX31_PIN_D10            = IOMUX_PIN(0xff, 191),
-        MX31_PIN_D11            = IOMUX_PIN(0xff, 192),
-        MX31_PIN_D12            = IOMUX_PIN(0xff, 193),
-        MX31_PIN_D13            = IOMUX_PIN(0xff, 194),
-        MX31_PIN_D14            = IOMUX_PIN(0xff, 195),
-        MX31_PIN_D15            = IOMUX_PIN(0xff, 196),
-        MX31_PIN_NFRB           = IOMUX_PIN(16,   197),
-        MX31_PIN_NFCE_B         = IOMUX_PIN(15,   198),
-        MX31_PIN_NFWP_B         = IOMUX_PIN(14,   199),
-        MX31_PIN_NFCLE          = IOMUX_PIN(13,   200),
-        MX31_PIN_NFALE          = IOMUX_PIN(12,   201),
-        MX31_PIN_NFRE_B         = IOMUX_PIN(11,   202),
-        MX31_PIN_NFWE_B         = IOMUX_PIN(10,   203),
-        MX31_PIN_SDQS3          = IOMUX_PIN(0xff, 204),
-        MX31_PIN_SDQS2          = IOMUX_PIN(0xff, 205),
-        MX31_PIN_SDQS1          = IOMUX_PIN(0xff, 206),
-        MX31_PIN_SDQS0          = IOMUX_PIN(0xff, 207),
-        MX31_PIN_SDCLK_B        = IOMUX_PIN(0xff, 208),
-        MX31_PIN_SDCLK          = IOMUX_PIN(0xff, 209),
-        MX31_PIN_SDCKE1         = IOMUX_PIN(0xff, 210),
-        MX31_PIN_SDCKE0         = IOMUX_PIN(0xff, 211),
-        MX31_PIN_SDWE           = IOMUX_PIN(0xff, 212),
-        MX31_PIN_CAS            = IOMUX_PIN(0xff, 213),
-        MX31_PIN_RAS            = IOMUX_PIN(0xff, 214),
-        MX31_PIN_RW             = IOMUX_PIN(0xff, 215),
-        MX31_PIN_BCLK           = IOMUX_PIN(0xff, 216),
-        MX31_PIN_LBA            = IOMUX_PIN(0xff, 217),
-        MX31_PIN_ECB            = IOMUX_PIN(0xff, 218),
-        MX31_PIN_CS5            = IOMUX_PIN(0xff, 219),
-        MX31_PIN_CS4            = IOMUX_PIN(0xff, 220),
-        MX31_PIN_CS3            = IOMUX_PIN(0xff, 221),
-        MX31_PIN_CS2            = IOMUX_PIN(0xff, 222),
-        MX31_PIN_CS1            = IOMUX_PIN(0xff, 223),
-        MX31_PIN_CS0            = IOMUX_PIN(0xff, 224),
-        MX31_PIN_OE             = IOMUX_PIN(0xff, 225),
-        MX31_PIN_EB1            = IOMUX_PIN(0xff, 226),
-        MX31_PIN_EB0            = IOMUX_PIN(0xff, 227),
-        MX31_PIN_DQM3           = IOMUX_PIN(0xff, 228),
-        MX31_PIN_DQM2           = IOMUX_PIN(0xff, 229),
-        MX31_PIN_DQM1           = IOMUX_PIN(0xff, 230),
-        MX31_PIN_DQM0           = IOMUX_PIN(0xff, 231),
-        MX31_PIN_SD31           = IOMUX_PIN(0xff, 232),
-        MX31_PIN_SD30           = IOMUX_PIN(0xff, 233),
-        MX31_PIN_SD29           = IOMUX_PIN(0xff, 234),
-        MX31_PIN_SD28           = IOMUX_PIN(0xff, 235),
-        MX31_PIN_SD27           = IOMUX_PIN(0xff, 236),
-        MX31_PIN_SD26           = IOMUX_PIN(0xff, 237),
-        MX31_PIN_SD25           = IOMUX_PIN(0xff, 238),
-        MX31_PIN_SD24           = IOMUX_PIN(0xff, 239),
-        MX31_PIN_SD23           = IOMUX_PIN(0xff, 240),
-        MX31_PIN_SD22           = IOMUX_PIN(0xff, 241),
-        MX31_PIN_SD21           = IOMUX_PIN(0xff, 242),
-        MX31_PIN_SD20           = IOMUX_PIN(0xff, 243),
-        MX31_PIN_SD19           = IOMUX_PIN(0xff, 244),
-        MX31_PIN_SD18           = IOMUX_PIN(0xff, 245),
-        MX31_PIN_SD17           = IOMUX_PIN(0xff, 246),
-        MX31_PIN_SD16           = IOMUX_PIN(0xff, 247),
-        MX31_PIN_SD15           = IOMUX_PIN(0xff, 248),
-        MX31_PIN_SD14           = IOMUX_PIN(0xff, 249),
-        MX31_PIN_SD13           = IOMUX_PIN(0xff, 250),
-        MX31_PIN_SD12           = IOMUX_PIN(0xff, 251),
-        MX31_PIN_SD11           = IOMUX_PIN(0xff, 252),
-        MX31_PIN_SD10           = IOMUX_PIN(0xff, 253),
-        MX31_PIN_SD9            = IOMUX_PIN(0xff, 254),
-        MX31_PIN_SD8            = IOMUX_PIN(0xff, 255),
-        MX31_PIN_SD7            = IOMUX_PIN(0xff, 256),
-        MX31_PIN_SD6            = IOMUX_PIN(0xff, 257),
-        MX31_PIN_SD5            = IOMUX_PIN(0xff, 258),
-        MX31_PIN_SD4            = IOMUX_PIN(0xff, 259),
-        MX31_PIN_SD3            = IOMUX_PIN(0xff, 260),
-        MX31_PIN_SD2            = IOMUX_PIN(0xff, 261),
-        MX31_PIN_SD1            = IOMUX_PIN(0xff, 262),
-        MX31_PIN_SD0            = IOMUX_PIN(0xff, 263),
-        MX31_PIN_SDBA0          = IOMUX_PIN(0xff, 264),
-        MX31_PIN_SDBA1          = IOMUX_PIN(0xff, 265),
-        MX31_PIN_A25            = IOMUX_PIN(0xff, 266),
-        MX31_PIN_A24            = IOMUX_PIN(0xff, 267),
-        MX31_PIN_A23            = IOMUX_PIN(0xff, 268),
-        MX31_PIN_A22            = IOMUX_PIN(0xff, 269),
-        MX31_PIN_A21            = IOMUX_PIN(0xff, 270),
-        MX31_PIN_A20            = IOMUX_PIN(0xff, 271),
-        MX31_PIN_A19            = IOMUX_PIN(0xff, 272),
-        MX31_PIN_A18            = IOMUX_PIN(0xff, 273),
-        MX31_PIN_A17            = IOMUX_PIN(0xff, 274),
-        MX31_PIN_A16            = IOMUX_PIN(0xff, 275),
-        MX31_PIN_A14            = IOMUX_PIN(0xff, 276),
-        MX31_PIN_A15            = IOMUX_PIN(0xff, 277),
-        MX31_PIN_A13            = IOMUX_PIN(0xff, 278),
-        MX31_PIN_A12            = IOMUX_PIN(0xff, 279),
-        MX31_PIN_A11            = IOMUX_PIN(0xff, 280),
-        MX31_PIN_MA10           = IOMUX_PIN(0xff, 281),
-        MX31_PIN_A10            = IOMUX_PIN(0xff, 282),
-        MX31_PIN_A9             = IOMUX_PIN(0xff, 283),
-        MX31_PIN_A8             = IOMUX_PIN(0xff, 284),
-        MX31_PIN_A7             = IOMUX_PIN(0xff, 285),
-        MX31_PIN_A6             = IOMUX_PIN(0xff, 286),
-        MX31_PIN_A5             = IOMUX_PIN(0xff, 287),
-        MX31_PIN_A4             = IOMUX_PIN(0xff, 288),
-        MX31_PIN_A3             = IOMUX_PIN(0xff, 289),
-        MX31_PIN_A2             = IOMUX_PIN(0xff, 290),
-        MX31_PIN_A1             = IOMUX_PIN(0xff, 291),
-        MX31_PIN_A0             = IOMUX_PIN(0xff, 292),
-        MX31_PIN_VPG1           = IOMUX_PIN(0xff, 293),
-        MX31_PIN_VPG0           = IOMUX_PIN(0xff, 294),
-        MX31_PIN_DVFS1          = IOMUX_PIN(0xff, 295),
-        MX31_PIN_DVFS0          = IOMUX_PIN(0xff, 296),
-        MX31_PIN_VSTBY          = IOMUX_PIN(0xff, 297),
-        MX31_PIN_POWER_FAIL     = IOMUX_PIN(0xff, 298),
-        MX31_PIN_CKIL           = IOMUX_PIN(0xff, 299),
-        MX31_PIN_BOOT_MODE4     = IOMUX_PIN(0xff, 300),
-        MX31_PIN_BOOT_MODE3     = IOMUX_PIN(0xff, 301),
-        MX31_PIN_BOOT_MODE2     = IOMUX_PIN(0xff, 302),
-        MX31_PIN_BOOT_MODE1     = IOMUX_PIN(0xff, 303),
-        MX31_PIN_BOOT_MODE0     = IOMUX_PIN(0xff, 304),
-        MX31_PIN_CLKO           = IOMUX_PIN(0xff, 305),
-        MX31_PIN_POR_B          = IOMUX_PIN(0xff, 306),
-        MX31_PIN_RESET_IN_B     = IOMUX_PIN(0xff, 307),
-        MX31_PIN_CKIH           = IOMUX_PIN(0xff, 308),
-        MX31_PIN_SIMPD0         = IOMUX_PIN(35,   309),
-        MX31_PIN_SRX0           = IOMUX_PIN(34,   310),
-        MX31_PIN_STX0           = IOMUX_PIN(33,   311),
-        MX31_PIN_SVEN0          = IOMUX_PIN(32,   312),
-        MX31_PIN_SRST0          = IOMUX_PIN(67,   313),
-        MX31_PIN_SCLK0          = IOMUX_PIN(66,   314),
-        MX31_PIN_GPIO3_1        = IOMUX_PIN(65,   315),
-        MX31_PIN_GPIO3_0        = IOMUX_PIN(64,   316),
-        MX31_PIN_GPIO1_6        = IOMUX_PIN( 6,   317),
-        MX31_PIN_GPIO1_5        = IOMUX_PIN( 5,   318),
-        MX31_PIN_GPIO1_4        = IOMUX_PIN( 4,   319),
-        MX31_PIN_GPIO1_3        = IOMUX_PIN( 3,   320),
-        MX31_PIN_GPIO1_2        = IOMUX_PIN( 2,   321),
-        MX31_PIN_GPIO1_1        = IOMUX_PIN( 1,   322),
-        MX31_PIN_GPIO1_0        = IOMUX_PIN( 0,   323),
-        MX31_PIN_PWMO           = IOMUX_PIN( 9,   324),
-        MX31_PIN_WATCHDOG_RST   = IOMUX_PIN(0xff, 325),
-        MX31_PIN_COMPARE        = IOMUX_PIN( 8,   326),
-        MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
-};
-
-#define PIN_MAX 327
-#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
-
-/*
- * Convenience values for use with mxc_iomux_mode()
- *
- * Format here is MX31_PIN_(pin name)__(function)
- */
-#define MX31_PIN_CSPI3_MOSI__RXD3       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_MISO__TXD3       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_SCLK__RTS3       IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_SPI_RDY__CTS3    IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS1__SFS              IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_TXD1__SCK              IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RXD1__STXDA            IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_DCD_DCE1__DCD_DCE1     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RI_DCE1__RI_DCE1       IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DSR_DCE1__DSR_DCE1     IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DTR_DCE1__DTR_DCE1     IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DTR_DCE1__SRXDA        IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CTS2__CTS2             IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS2__RTS2             IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_TXD2__TXD2             IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RXD2__RXD2             IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__DCD_DTE2     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_RI_DTE1__RI_DTE2       IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_DSR_DTE1__DSR_DTE2     IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_DTR_DTE1__DTR_DTE2     IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
-#define MX31_PIN_PC_RST__CTS5           IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_VS2__RTS5           IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_BVD2__TXD5          IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_BVD1__RXD5          IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CSPI1_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MOSI__SCL        IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MISO__SDA        IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_BATT_LINE__OWIRE       IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CS4__CS4               IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA3__SD1_DATA3   IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA2__SD1_DATA2   IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA1__SD1_DATA1   IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA0__SD1_DATA0   IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_CLK__SD1_CLK       IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_CMD__SD1_CMD       IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_ATA_CS0__GPIO3_26      IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_CS1__GPIO3_27      IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_PC_PWRON__SD2_DATA3    IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_VS1__SD2_DATA2      IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_READY__SD2_DATA1    IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_WAIT_B__SD2_DATA0   IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD2_B__SD2_CLK      IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD1_B__SD2_CMD      IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_ATA_DIOR__GPIO3_28     IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_DIOW__GPIO3_29     IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_LD0__LD0               IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD1__LD1               IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD2__LD2               IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD3__LD3               IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD4__LD4               IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD5__LD5               IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD6__LD6               IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD7__LD7               IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD8__LD8               IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD9__LD9               IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD10__LD10             IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD11__LD11             IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD12__LD12             IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD13__LD13             IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD14__LD14             IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD15__LD15             IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD16__LD16             IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD17__LD17             IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_VSYNC3__VSYNC3         IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_HSYNC__HSYNC           IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_FPSHIFT__FPSHIFT       IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DRDY0__DRDY0           IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_REV__D3_REV         IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CONTRAST__CONTRAST     IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_SPL__D3_SPL         IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_CLS__D3_CLS         IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LCS0__GPI03_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO1_1__GPIO          IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_I2C_CLK__SCL           IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_I2C_DAT__SDA           IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__I2C2_SDA     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RI_DTE1__I2C2_SCL      IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CSPI2_SS2__I2C3_SDA    IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_SCLK__I2C3_SCL   IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSI_D4__CSI_D4         IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D5__CSI_D5         IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D6__CSI_D6         IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D7__CSI_D7         IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D8__CSI_D8         IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D9__CSI_D9         IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D10__CSI_D10       IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D11__CSI_D11       IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D12__CSI_D12       IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D13__CSI_D13       IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D14__CSI_D14       IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D15__CSI_D15       IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_HSYNC__CSI_HSYNC   IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_MCLK__CSI_MCLK     IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_VSYNC__CSI_VSYNC   IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D4__GPIO3_4        IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D5__GPIO3_5        IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0     IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1     IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2     IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3     IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4     IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5     IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6     IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7     IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_CLK__USBOTG_CLK         IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DIR__USBOTG_DIR         IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_NXT__USBOTG_NXT         IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_STP__USBOTG_STP         IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM         IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_MISO__USBH1_RXDP         IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS0__USBH1_TXDM          IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS1__USBH1_TXDP          IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS2__USBH1_RCV           IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SCLK__USBH1_OEB          IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS        IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_SFS6__USBH1_SUSPEND    IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_NFRE_B__GPIO1_11       IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_NFALE__GPIO1_12        IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USBH2_DATA0__USBH2_DATA0       IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_DATA1__USBH2_DATA1       IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD3__USBH2_DATA2     IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD3__USBH2_DATA3     IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK3__USBH2_DATA4      IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS3__USBH2_DATA5      IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD6__USBH2_DATA6     IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD6__USBH2_DATA7     IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_CLK__USBH2_CLK           IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_DIR__USBH2_DIR           IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_NXT__USBH2_NXT           IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_STP__USBH2_STP           IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK6__GPIO1_25         IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__I2C2_SDA     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RI_DTE1__I2C2_SCL      IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_ATA_CS0__GPIO3_26      IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_CS1__GPIO3_27      IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_PC_PWRON__SD2_DATA3    IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_VS1__SD2_DATA2      IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_READY__SD2_DATA1    IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_WAIT_B__SD2_DATA0   IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD2_B__SD2_CLK      IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD1_B__SD2_CMD      IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_ATA_DIOR__GPIO3_28     IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_DIOW__GPIO3_29     IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D4__CSI_D4         IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D5__CSI_D5         IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D6__CSI_D6         IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D7__CSI_D7         IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D8__CSI_D8         IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D9__CSI_D9         IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D10__CSI_D10       IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D11__CSI_D11       IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D12__CSI_D12       IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D13__CSI_D13       IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D14__CSI_D14       IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D15__CSI_D15       IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_HSYNC__CSI_HSYNC   IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_MCLK__CSI_MCLK     IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_VSYNC__CSI_VSYNC   IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO1_0__GPIO1_0       IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SVEN0__GPIO2_0         IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STX0__GPIO2_1          IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SRX0__GPIO2_2          IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SIMPD0__GPIO2_3        IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DTR_DCE1__GPIO2_8      IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DSR_DCE1__GPIO2_9      IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_RI_DCE1__GPIO2_10      IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STXD5__GPIO1_21        IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SRXD5__GPIO1_22        IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO1_3__GPIO1_3       IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSPI2_SS1__CSPI3_SS1   IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_RTS1__GPIO2_6          IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CTS1__GPIO2_7          IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_LCS0__GPIO3_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STXD4__STXD4           IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD4__SRXD4           IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK4__SCK4             IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS4__SFS4             IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD5__STXD5           IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD5__SRXD5           IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK5__SCK5             IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS5__SFS5             IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW0_KEY_ROW0      IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW1_KEY_ROW1      IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW2_KEY_ROW2      IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW3_KEY_ROW3      IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW4_KEY_ROW4      IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW4_GPIO          IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_KEY_ROW5_KEY_ROW5      IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW6_KEY_ROW6      IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW7_KEY_ROW7      IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL0_KEY_COL0      IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL1_KEY_COL1      IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL2_KEY_COL2      IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL3_KEY_COL3      IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL4_KEY_COL4      IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL5_KEY_COL5      IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL6_KEY_COL6      IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL7_KEY_COL7      IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST     IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
-
-
-/*
- * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
- * cspi2_ss1, cspi1_ss0 cspi1_ss1
- */
-
-/*
- * This function configures the pad value for a IOMUX pin.
- */
-void mxc_iomux_set_pad(enum iomux_pins, u32);
-
-#endif /* ifndef __MACH_IOMUX_MX3_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx35.h b/arch/arm/mach-imx/iomux-mx35.h
deleted file mode 100644
index 90bfa6b5be6..00000000000
--- a/arch/arm/mach-imx/iomux-mx35.h
+++ /dev/null
@@ -1,1267 +0,0 @@
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option, NO_PAD_CTRL) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IOMUX_MX35_H__
-#define __MACH_IOMUX_MX35_H__
-
-#include "iomux-v3.h"
-
-/*
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
- */
-
-/*                                                                        PAD    MUX   ALT INPSE PATH */
-#define MX35_PAD_CAPTURE__GPT_CAPIN1                            IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__GPT_CMPOUT2                           IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__CSPI2_SS1                             IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__EPIT1_EPITO                           IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__CCM_CLK32K                            IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__GPIO1_4                               IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_COMPARE__GPT_CMPOUT1                           IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPT_CAPIN2                            IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPT_CMPOUT3                           IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__EPIT2_EPITO                           IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPIO1_5                               IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__SDMA_EXTDMA_2                         IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_WDOG_RST__WDOG_WDOG_B                          IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE                     IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_WDOG_RST__GPIO1_6                              IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO1_0__GPIO1_0                               IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY                          IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__OWIRE_LINE                            IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0                         IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO1_1__GPIO1_1                               IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__PWM_PWMO                              IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__CSPI1_SS2                             IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT                     IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1                         IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO2_0__GPIO2_0                               IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK                    IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO3_0__GPIO3_0                               IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK                     IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B                     IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_POR_B__CCM_POR_B                               IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLKO__CCM_CLKO                                 IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CLKO__GPIO1_8                                  IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0                    IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1                    IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0                      IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1                      IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26              IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_VSTBY__CCM_VSTBY                               IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_VSTBY__GPIO1_7                                 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A0__EMI_EIM_DA_L_0                             IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A1__EMI_EIM_DA_L_1                             IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A2__EMI_EIM_DA_L_2                             IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A3__EMI_EIM_DA_L_3                             IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A4__EMI_EIM_DA_L_4                             IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A5__EMI_EIM_DA_L_5                             IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A6__EMI_EIM_DA_L_6                             IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A7__EMI_EIM_DA_L_7                             IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A8__EMI_EIM_DA_H_8                             IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A9__EMI_EIM_DA_H_9                             IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A10__EMI_EIM_DA_H_10                           IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_MA10__EMI_MA10                                 IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A11__EMI_EIM_DA_H_11                           IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A12__EMI_EIM_DA_H_12                           IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A13__EMI_EIM_DA_H_13                           IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A14__EMI_EIM_DA_H2_14                          IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A15__EMI_EIM_DA_H2_15                          IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A16__EMI_EIM_A_16                              IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A17__EMI_EIM_A_17                              IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A18__EMI_EIM_A_18                              IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A19__EMI_EIM_A_19                              IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A20__EMI_EIM_A_20                              IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A21__EMI_EIM_A_21                              IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A22__EMI_EIM_A_22                              IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A23__EMI_EIM_A_23                              IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A24__EMI_EIM_A_24                              IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A25__EMI_EIM_A_25                              IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDBA1__EMI_EIM_SDBA1                           IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDBA0__EMI_EIM_SDBA0                           IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD0__EMI_DRAM_D_0                              IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1__EMI_DRAM_D_1                              IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2__EMI_DRAM_D_2                              IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD3__EMI_DRAM_D_3                              IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD4__EMI_DRAM_D_4                              IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD5__EMI_DRAM_D_5                              IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD6__EMI_DRAM_D_6                              IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD7__EMI_DRAM_D_7                              IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD8__EMI_DRAM_D_8                              IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD9__EMI_DRAM_D_9                              IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD10__EMI_DRAM_D_10                            IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD11__EMI_DRAM_D_11                            IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD12__EMI_DRAM_D_12                            IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD13__EMI_DRAM_D_13                            IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD14__EMI_DRAM_D_14                            IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD15__EMI_DRAM_D_15                            IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD16__EMI_DRAM_D_16                            IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD17__EMI_DRAM_D_17                            IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD18__EMI_DRAM_D_18                            IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD19__EMI_DRAM_D_19                            IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD20__EMI_DRAM_D_20                            IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD21__EMI_DRAM_D_21                            IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD22__EMI_DRAM_D_22                            IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD23__EMI_DRAM_D_23                            IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD24__EMI_DRAM_D_24                            IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD25__EMI_DRAM_D_25                            IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD26__EMI_DRAM_D_26                            IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD27__EMI_DRAM_D_27                            IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD28__EMI_DRAM_D_28                            IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD29__EMI_DRAM_D_29                            IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD30__EMI_DRAM_D_30                            IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD31__EMI_DRAM_D_31                            IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM0__EMI_DRAM_DQM_0                           IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM1__EMI_DRAM_DQM_1                           IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM2__EMI_DRAM_DQM_2                           IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM3__EMI_DRAM_DQM_3                           IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_EB0__EMI_EIM_EB0_B                             IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_EB1__EMI_EIM_EB1_B                             IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_OE__EMI_EIM_OE                                 IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS0__EMI_EIM_CS0                               IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS1__EMI_EIM_CS1                               IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS1__EMI_NANDF_CE3                             IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS2__EMI_EIM_CS2                               IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS3__EMI_EIM_CS3                               IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS4__EMI_EIM_CS4                               IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__EMI_DTACK_B                               IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__EMI_NANDF_CE1                             IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__GPIO1_20                                  IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS5__EMI_EIM_CS5                               IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__CSPI2_SS2                                 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__CSPI1_SS2                                 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_CS5__EMI_NANDF_CE2                             IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__GPIO1_21                                  IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NF_CE0__EMI_NANDF_CE0                          IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NF_CE0__GPIO1_22                               IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ECB__EMI_EIM_ECB                               IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LBA__EMI_EIM_LBA                               IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_BCLK__EMI_EIM_BCLK                             IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RW__EMI_EIM_RW                                 IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RAS__EMI_DRAM_RAS                              IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CAS__EMI_DRAM_CAS                              IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDWE__EMI_DRAM_SDWE                            IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0                       IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1                       IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK                          IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0                         IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1                         IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2                         IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3                         IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B                         IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3                   IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC                     IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__GPIO2_18                               IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0                     IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B                         IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR                      IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK                         IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__GPIO2_19                               IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1                     IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFALE__EMI_NANDF_ALE                           IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__USB_TOP_USBH2_STP                       IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__IPU_DISPB_CS0                           IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__GPIO2_20                                IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2                      IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFCLE__EMI_NANDF_CLE                           IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT                       IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS                        IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__GPIO2_21                                IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3                      IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B                         IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7                   IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__IPU_DISPB_WR                           IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__GPIO2_22                               IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL                       IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFRB__EMI_NANDF_RB                             IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__IPU_DISPB_RD                             IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__GPIO2_23                                 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK                         IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D15__EMI_EIM_D_15                              IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D14__EMI_EIM_D_14                              IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D13__EMI_EIM_D_13                              IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D12__EMI_EIM_D_12                              IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D11__EMI_EIM_D_11                              IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D10__EMI_EIM_D_10                              IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D9__EMI_EIM_D_9                                IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D8__EMI_EIM_D_8                                IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D7__EMI_EIM_D_7                                IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D6__EMI_EIM_D_6                                IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D5__EMI_EIM_D_5                                IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D4__EMI_EIM_D_4                                IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3__EMI_EIM_D_3                                IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D2__EMI_EIM_D_2                                IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D1__EMI_EIM_D_1                                IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D0__EMI_EIM_D_0                                IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D8__IPU_CSI_D_8                            IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__KPP_COL_0                              IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__GPIO1_20                               IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13                  IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D9__IPU_CSI_D_9                            IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__KPP_COL_1                              IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__GPIO1_21                               IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14                  IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D10__IPU_CSI_D_10                          IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__KPP_COL_2                             IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__GPIO1_22                              IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15                 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D11__IPU_CSI_D_11                          IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D11__KPP_COL_3                             IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D11__GPIO1_23                              IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D12__IPU_CSI_D_12                          IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D12__KPP_ROW_0                             IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D12__GPIO1_24                              IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D13__IPU_CSI_D_13                          IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D13__KPP_ROW_1                             IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D13__GPIO1_25                              IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D14__IPU_CSI_D_14                          IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D14__KPP_ROW_2                             IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D14__GPIO1_26                              IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D15__IPU_CSI_D_15                          IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D15__KPP_ROW_3                             IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D15__GPIO1_27                              IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK                         IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_MCLK__GPIO1_28                             IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC                       IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_VSYNC__GPIO1_29                            IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC                       IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_HSYNC__GPIO1_30                            IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK                     IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_PIXCLK__GPIO1_31                           IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C1_CLK__I2C1_SCL                             IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_CLK__GPIO2_24                             IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK                      IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C1_DAT__I2C1_SDA                             IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_DAT__GPIO2_25                             IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C2_CLK__I2C2_SCL                             IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__CAN1_TXCAN                           IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR                    IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__GPIO2_26                             IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2              IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C2_DAT__I2C2_SDA                             IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__CAN1_RXCAN                           IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC                     IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__GPIO2_27                             IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3              IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD                         IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXD4__GPIO2_28                                IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0                IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD                         IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD4__GPIO2_29                                IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1                IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC                          IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCK4__GPIO2_30                                 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2                 IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS                       IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS4__GPIO2_31                               IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3               IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD                         IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1                        IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__CSPI2_MOSI                              IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__GPIO1_0                                 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4                IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD                         IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1                         IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__CSPI2_MISO                              IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__GPIO1_1                                 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5                IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC                          IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK                       IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__CSPI2_SCLK                               IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__GPIO1_2                                  IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6                 IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS                       IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__CSPI2_RDY                              IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__GPIO1_3                                IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7               IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCKR__ESAI_SCKR                                IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCKR__GPIO1_4                                  IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL)
-#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10                    IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FSR__ESAI_FSR                                  IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FSR__GPIO1_5                                   IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL)
-#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11                     IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_HCKR__ESAI_HCKR                                IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS                         IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__CSPI2_SS0                                IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__IPU_FLASH_STROBE                         IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__GPIO1_6                                  IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12                    IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCKT__ESAI_SCKT                                IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__GPIO1_7                                  IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__IPU_CSI_D_0                              IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__KPP_ROW_2                                IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_FST__ESAI_FST                                  IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FST__GPIO1_8                                   IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL)
-#define MX35_PAD_FST__IPU_CSI_D_1                               IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL)
-#define MX35_PAD_FST__KPP_ROW_3                                 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_HCKT__ESAI_HCKT                                IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC                          IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__GPIO1_9                                  IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__IPU_CSI_D_2                              IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__KPP_COL_3                                IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0                          IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC                       IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__CSPI2_SS2                             IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__CAN2_TXCAN                            IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__UART2_DTR                             IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__GPIO1_10                              IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0              IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1                          IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS                      IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__CSPI2_SS3                             IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__CAN2_RXCAN                            IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__UART2_DSR                             IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__GPIO1_11                              IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__IPU_CSI_D_3                           IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__KPP_ROW_0                             IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2                          IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__I2C3_SCL                              IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1                         IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__GPIO1_12                              IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__IPU_CSI_D_4                           IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__KPP_ROW_1                             IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3                          IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__I2C3_SDA                              IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2                         IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__GPIO1_13                              IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__IPU_CSI_D_5                           IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__KPP_COL_0                             IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX1__ESAI_TX1                                  IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__CCM_PMIC_RDY                              IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX1__CSPI1_SS2                                 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL)
-#define MX35_PAD_TX1__EMI_NANDF_CE3                             IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__UART2_RI                                  IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__GPIO1_14                                  IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__IPU_CSI_D_6                               IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__KPP_COL_1                                 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX0__ESAI_TX0                                  IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK                        IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX0__CSPI1_SS3                                 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__EMI_DTACK_B                               IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX0__UART2_DCD                                 IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__GPIO1_15                                  IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__IPU_CSI_D_7                               IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__KPP_COL_2                                 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI                         IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MOSI__GPIO1_16                           IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2                IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_MISO__CSPI1_MISO                         IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MISO__GPIO1_17                           IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3                IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SS0__CSPI1_SS0                           IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__OWIRE_LINE                          IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__CSPI2_SS3                           IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__GPIO1_18                            IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4                 IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SS1__CSPI1_SS1                           IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__PWM_PWMO                            IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__CCM_CLK32K                          IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__GPIO1_19                            IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29                        IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5                 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK                         IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__GPIO3_4                            IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30                       IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1           IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY                       IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5                         IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31                    IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2        IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RXD1__UART1_RXD_MUX                            IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__CSPI2_MOSI                               IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__KPP_COL_4                                IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__GPIO3_6                                  IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16                    IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TXD1__UART1_TXD_MUX                            IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__CSPI2_MISO                               IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__KPP_COL_5                                IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__GPIO3_7                                  IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17                    IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTS1__UART1_RTS                                IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__CSPI2_SCLK                               IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__I2C3_SCL                                 IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__IPU_CSI_D_0                              IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__KPP_COL_6                                IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__GPIO3_8                                  IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__EMI_NANDF_CE1                            IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18                    IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CTS1__UART1_CTS                                IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__CSPI2_RDY                                IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__I2C3_SDA                                 IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__IPU_CSI_D_1                              IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__KPP_COL_7                                IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__GPIO3_9                                  IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__EMI_NANDF_CE2                            IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19                    IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RXD2__UART2_RXD_MUX                            IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RXD2__KPP_ROW_4                                IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD2__GPIO3_10                                 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TXD2__UART2_TXD_MUX                            IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK                       IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__KPP_ROW_5                                IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__GPIO3_11                                 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTS2__UART2_RTS                                IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1                          IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__CAN2_RXCAN                               IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__IPU_CSI_D_2                              IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__KPP_ROW_6                                IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__GPIO3_12                                 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC                          IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__UART3_RXD_MUX                            IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CTS2__UART2_CTS                                IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1                         IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__CAN2_TXCAN                               IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__IPU_CSI_D_3                              IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__KPP_ROW_7                                IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__GPIO3_13                                 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS                         IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__UART3_TXD_MUX                            IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTCK__ARM11P_TOP_RTCK                          IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TCK__SJC_TCK                                   IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TMS__SJC_TMS                                   IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TDI__SJC_TDI                                   IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TDO__SJC_TDO                                   IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TRSTB__SJC_TRSTB                               IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DE_B__SJC_DE_B                                 IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SJC_MOD__SJC_MOD                               IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR                 IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR                  IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_PWR__GPIO3_14                           IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC                   IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC                    IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_OC__GPIO3_15                            IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD0__IPU_DISPB_DAT_0                           IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD0__GPIO2_0                                   IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0                      IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD1__IPU_DISPB_DAT_1                           IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD1__GPIO2_1                                   IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1                      IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD2__IPU_DISPB_DAT_2                           IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD2__GPIO2_2                                   IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2                      IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD3__IPU_DISPB_DAT_3                           IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD3__GPIO2_3                                   IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3                      IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD4__IPU_DISPB_DAT_4                           IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD4__GPIO2_4                                   IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4                      IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD5__IPU_DISPB_DAT_5                           IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD5__GPIO2_5                                   IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5                      IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD6__IPU_DISPB_DAT_6                           IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD6__GPIO2_6                                   IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6                      IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD7__IPU_DISPB_DAT_7                           IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD7__GPIO2_7                                   IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7                      IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD8__IPU_DISPB_DAT_8                           IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD8__GPIO2_8                                   IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8                      IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD9__IPU_DISPB_DAT_9                           IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__GPIO2_9                                   IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9                      IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD10__IPU_DISPB_DAT_10                         IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD10__GPIO2_10                                 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10                    IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD11__IPU_DISPB_DAT_11                         IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__GPIO2_11                                 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11                    IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4                       IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD12__IPU_DISPB_DAT_12                         IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__GPIO2_12                                 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12                    IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5                       IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD13__IPU_DISPB_DAT_13                         IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__GPIO2_13                                 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13                    IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6                       IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD14__IPU_DISPB_DAT_14                         IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__GPIO2_14                                 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0          IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7                       IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD15__IPU_DISPB_DAT_15                         IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__GPIO2_15                                 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1          IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8                       IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD16__IPU_DISPB_DAT_16                         IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC                      IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__GPIO2_16                                 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2          IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9                       IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD17__IPU_DISPB_DAT_17                         IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__IPU_DISPB_CS2                            IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__GPIO2_17                                 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3          IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10                      IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD18__IPU_DISPB_DAT_18                         IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC                       IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC                      IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD18__ESDHC3_CMD                               IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3                    IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__GPIO3_24                                 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4          IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11                      IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD19__IPU_DISPB_DAT_19                         IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__IPU_DISPB_BCLK                           IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__IPU_DISPB_CS1                            IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__ESDHC3_CLK                               IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR                       IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__GPIO3_25                                 IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5          IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12                      IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD20__IPU_DISPB_DAT_20                         IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__IPU_DISPB_CS0                            IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__IPU_DISPB_SD_CLK                         IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__ESDHC3_DAT0                              IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__GPIO3_26                                 IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3            IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13                      IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD21__IPU_DISPB_DAT_21                         IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__IPU_DISPB_PAR_RS                         IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__IPU_DISPB_SER_RS                         IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__ESDHC3_DAT1                              IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__USB_TOP_USBOTG_STP                       IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__GPIO3_27                                 IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL             IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14                      IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD22__IPU_DISPB_DAT_22                         IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__IPU_DISPB_WR                             IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__IPU_DISPB_SD_D_I                         IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__ESDHC3_DAT2                              IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT                       IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__GPIO3_28                                 IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR                     IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__ARM11P_TOP_TRCTL                         IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD23__IPU_DISPB_DAT_23                         IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__IPU_DISPB_RD                             IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO                        IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD23__ESDHC3_DAT3                              IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7                    IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__GPIO3_29                                 IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS                 IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__ARM11P_TOP_TRCLK                         IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC                   IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO                    IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__GPIO3_30                             IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE            IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15                  IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK                   IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK                   IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__GPIO3_31                           IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0      IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16                IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY                     IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O                      IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__GPIO1_0                               IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1         IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17                   IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR                      IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__GPIO1_1                              IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2        IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18                  IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC                   IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1                        IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__GPIO1_2                              IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD                     IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19                  IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV                       IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS                       IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__GPIO1_3                                IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB                     IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20                    IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS                       IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__IPU_DISPB_CS2                          IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__GPIO1_4                                IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0                IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21                    IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL                       IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC                    IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__GPIO1_5                                IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1                IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22                    IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_CMD__ESDHC1_CMD                            IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__MSHC_SCLK                             IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC                    IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4                 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__GPIO1_6                               IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL                      IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_CLK__ESDHC1_CLK                            IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__MSHC_BS                               IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK                        IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5                 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__GPIO1_7                               IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK                      IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0                         IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__MSHC_DATA_0                         IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0                       IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6               IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__GPIO1_8                             IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23                 IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1                         IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__MSHC_DATA_1                         IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS                    IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0               IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__GPIO1_9                             IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24                 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2                         IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__MSHC_DATA_2                         IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR                        IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1               IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__GPIO1_10                            IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25                 IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3                         IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__MSHC_DATA_3                         IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD                        IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2               IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__GPIO1_11                            IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26                 IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_CMD__ESDHC2_CMD                            IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__I2C3_SCL                              IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__ESDHC1_DAT4                           IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__IPU_CSI_D_2                           IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4                  IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__GPIO2_0                               IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1                      IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC                   IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_CLK__ESDHC2_CLK                            IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__I2C3_SDA                              IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__ESDHC1_DAT5                           IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__IPU_CSI_D_3                           IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5                  IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__GPIO2_1                               IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1                       IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2                         IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0                         IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX                       IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6                         IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4                         IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6                IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__GPIO2_2                             IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK                  IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1                         IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX                       IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7                         IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5                         IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0                IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__GPIO2_3                             IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2                         IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__UART3_RTS                           IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__CAN1_RXCAN                          IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6                         IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1                IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__GPIO2_4                             IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3                         IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__UART3_CTS                           IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__CAN1_TXCAN                          IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7                         IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2                IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__GPIO2_5                             IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_CS0__ATA_CS0                               IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__CSPI1_SS3                             IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1                         IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__GPIO2_6                               IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__IPU_DIAGB_0                           IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0             IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_CS1__ATA_CS1                               IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2                         IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__CSPI2_SS0                             IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__GPIO2_7                               IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__IPU_DIAGB_1                           IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1             IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DIOR__ATA_DIOR                             IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0                          IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR                   IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0                        IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__CSPI2_SS1                            IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__GPIO2_8                              IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2                          IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2            IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DIOW__ATA_DIOW                             IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1                          IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP                   IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1                        IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__CSPI2_MOSI                           IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__GPIO2_9                              IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3                          IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3            IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DMACK__ATA_DMACK                           IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2                         IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT                  IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__CSPI2_MISO                          IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__GPIO2_10                            IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4                         IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0           IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_RESET_B__ATA_RESET_B                       IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3                       IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0             IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O                  IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__CSPI2_RDY                         IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__GPIO2_11                          IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5                       IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1         IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_IORDY__ATA_IORDY                           IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4                         IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1               IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO                   IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4                         IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__GPIO2_12                            IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6                         IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2           IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA0__ATA_DATA_0                          IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5                         IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2               IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC                 IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5                         IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__GPIO2_13                            IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7                         IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3           IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA1__ATA_DATA_1                          IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6                         IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3               IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK                    IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6                         IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__GPIO2_14                            IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8                         IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27                 IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA2__ATA_DATA_2                          IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7                         IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4               IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS                    IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7                         IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__GPIO2_15                            IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9                         IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28                 IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__GPIO2_16                            IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA4__ATA_DATA_4                          IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__ESDHC3_CMD                          IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6               IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__GPIO2_17                            IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11                        IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30                 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA5__ATA_DATA_5                          IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7               IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__GPIO2_18                            IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12                        IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31                 IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA6__ATA_DATA_6                          IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__CAN1_TXCAN                          IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__UART1_DTR                           IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD                     IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__GPIO2_19                            IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13                        IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA7__ATA_DATA_7                          IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__CAN1_RXCAN                          IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__UART1_DSR                           IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD                     IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__GPIO2_20                            IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14                        IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA8__ATA_DATA_8                          IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__UART3_RTS                           IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__UART1_RI                            IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC                     IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__GPIO2_21                            IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15                        IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA9__ATA_DATA_9                          IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__UART3_CTS                           IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__UART1_DCD                           IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS                    IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__GPIO2_22                            IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16                        IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA10__ATA_DATA_10                        IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX                      IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC                    IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__GPIO2_23                           IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17                       IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA11__ATA_DATA_11                        IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX                      IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS                   IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__GPIO2_24                           IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18                       IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA12__ATA_DATA_12                        IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__I2C3_SCL                           IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__GPIO2_25                           IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19                       IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA13__ATA_DATA_13                        IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__I2C3_SDA                           IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__GPIO2_26                           IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20                       IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA14__ATA_DATA_14                        IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0                        IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__KPP_ROW_0                          IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__GPIO2_27                           IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21                       IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA15__ATA_DATA_15                        IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1                        IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__KPP_ROW_1                          IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__GPIO2_28                           IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22                       IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_INTRQ__ATA_INTRQ                           IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2                         IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__KPP_ROW_2                           IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__GPIO2_29                            IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23                        IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN                     IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3                       IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3                         IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__GPIO2_30                          IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24                      IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DMARQ__ATA_DMARQ                           IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4                         IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__KPP_COL_0                           IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__GPIO2_31                            IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25                        IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4                  IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA0__ATA_DA_0                              IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__IPU_CSI_D_5                           IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__KPP_COL_1                             IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__GPIO3_0                               IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__IPU_DIAGB_26                          IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5                    IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA1__ATA_DA_1                              IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__IPU_CSI_D_6                           IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__KPP_COL_2                             IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__GPIO3_1                               IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__IPU_DIAGB_27                          IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6                    IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA2__ATA_DA_2                              IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__IPU_CSI_D_7                           IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__KPP_COL_3                             IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__GPIO3_2                               IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__IPU_DIAGB_28                          IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7                    IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_CLK__MLB_MLBCLK                            IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_CLK__GPIO3_3                               IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_DAT__MLB_MLBDAT                            IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_DAT__GPIO3_4                               IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_SIG__MLB_MLBSIG                            IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_SIG__GPIO3_5                               IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK                         IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4                        IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX                      IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR                  IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI                         IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__GPIO3_6                            IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC                IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0               IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK                         IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5                        IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX                      IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP                  IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO                         IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__GPIO3_7                            IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I                   IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1               IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_DV__FEC_RX_DV                           IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6                         IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__UART3_RTS                           IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT                   IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK                          IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__GPIO3_8                             IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK                    IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2                IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_COL__FEC_COL                               IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__ESDHC1_DAT7                           IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__UART3_CTS                             IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0                  IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__CSPI2_RDY                             IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__GPIO3_9                               IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS                      IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3                  IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0                        IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__PWM_PWMO                           IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__UART3_DTR                          IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1               IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__CSPI2_SS0                          IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__GPIO3_10                           IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1                      IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4               IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0                        IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1                   IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__UART3_DSR                          IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2               IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__CSPI2_SS1                          IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__GPIO3_11                           IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0                      IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5               IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_EN__FEC_TX_EN                           IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1                     IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__UART3_RI                            IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3                IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__GPIO3_12                            IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS                    IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6                IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_MDC__FEC_MDC                               IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__CAN2_TXCAN                            IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__UART3_DCD                             IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4                  IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__GPIO3_13                              IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__IPU_DISPB_WR                          IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7                  IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_MDIO__FEC_MDIO                             IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__CAN2_RXCAN                           IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5                 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__GPIO3_14                             IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD                         IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8                 IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR                         IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE                         IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK                 IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6               IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__GPIO3_15                           IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC                 IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9               IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR                         IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0                        IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7               IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__KPP_COL_4                          IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__GPIO3_16                           IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO                  IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_CRS__FEC_CRS                               IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__IPU_CSI_D_1                           IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR                     IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__KPP_COL_5                             IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__GPIO3_17                              IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE                      IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1                        IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2                        IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC                    IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC                   IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__KPP_COL_6                          IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__GPIO3_18                           IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0                      IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1                        IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3                        IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS                   IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__KPP_COL_7                          IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__GPIO3_19                           IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1                      IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2                        IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4                        IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD                    IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__KPP_ROW_4                          IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__GPIO3_20                           IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2                        IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5                        IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD                    IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__KPP_ROW_5                          IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__GPIO3_21                           IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3                        IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6                        IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC                    IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__KPP_ROW_6                          IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__GPIO3_22                           IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3                        IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7                        IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS                   IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__KPP_ROW_7                          IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__GPIO3_23                           IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK                     IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TEST_MODE__TCU_TEST_MODE                       IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-
-#endif /* __MACH_IOMUX_MX35_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx50.h b/arch/arm/mach-imx/iomux-mx50.h
deleted file mode 100644
index 00f56e0e800..00000000000
--- a/arch/arm/mach-imx/iomux-mx50.h
+++ /dev/null
@@ -1,977 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_IOMUX_MX50_H__
-#define __MACH_IOMUX_MX50_H__
-
-#include "iomux-v3.h"
-
-#define MX50_ELCDIF_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-
-#define MX50_SD_PAD_CTRL        (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
-
-#define MX50_UART_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
-
-#define MX50_I2C_PAD_CTRL       (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
-                                        PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
-
-#define MX50_USB_PAD_CTRL       (PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
-
-#define MX50_FEC_PAD_CTRL       (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
-                                        PAD_CTL_DSE_HIGH)
-
-#define MX50_OWIRE_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
-                                        PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-
-#define MX50_KEYPAD_CTRL        (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
-
-#define MX50_CSPI_SS_PAD        (PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_COL0__KEY_COL0     IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__GPIO_4_0     IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__NANDF_CLE    IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_ROW0__KEY_ROW0     IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW0__GPIO_4_1     IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__NANDF_ALE    IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_COL1__KEY_COL1     IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__GPIO_4_2     IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__NANDF_CE0    IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_ROW1__KEY_ROW1     IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW1__GPIO_4_3     IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__NANDF_CE1    IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_COL2__KEY_COL2     IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_COL2__GPIO_4_4     IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__NANDF_CE2    IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_ROW2__KEY_ROW2     IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW2__GPIO_4_5     IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__NANDF_CE3    IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_COL3__KEY_COL3     IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__GPIO_4_6     IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__NANDF_READY  IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
-                                                        PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_KEY_COL3__SDMA_EXT0    IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_KEY_ROW3__KEY_ROW3     IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW3__GPIO_4_7     IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__NANDF_DQS    IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_ROW3__SDMA_EXT1    IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_I2C1_SCL__I2C1_SCL     IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__GPIO_6_18    IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-
-#define MX50_PAD_I2C1_SDA__I2C1_SDA     IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__GPIO_6_19    IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__UART2_RXD    IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
-
-#define MX50_PAD_I2C2_SCL__I2C2_SCL     IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__GPIO_6_20    IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__DCDC_OK      IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_I2C2_SDA__I2C2_SDA     IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__GPIO_6_21    IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__UART2_RTS    IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__PWRSTABLE    IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_I2C3_SCL__I2C3_SCL     IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPIO_6_22    IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__FEC_MDC      IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_I2C3_SCL__PMIC_RDY     IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPT_CAPIN1   IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__USBOTG_OC    IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
-
-#define MX50_PAD_I2C3_SDA__I2C3_SDA     IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                                MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__GPIO_6_23    IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__FEC_MDIO     IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__PWRFAIL_INT  IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__ALARM_DEB    IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__GPT_CAPIN1   IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__USBOTG_PWR   IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
-                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_PWM1__PWM1_PWMO        IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__GPIO_6_24        IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__USBOTG_OC        IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
-#define MX50_PAD_PWM1__GPT_CMPOUT1      IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PWM2__PWM2_PWMO        IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__GPIO_6_25        IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__USBOTG_PWR       IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
-                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-#define MX50_PAD_PWM2__DCDC_PWM         IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__GPT_CMPOUT2      IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__ANY_PU_RST       IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_OWIRE__OWIRE           IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
-#define MX50_PAD_OWIRE__GPIO_6_26       IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__USBH1_OC        IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
-#define MX50_PAD_OWIRE__SSI_EXT1_CLK    IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__EPDC_PWRIRQ     IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__GPT_CMPOUT3     IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPITO__EPITO           IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__GPIO_6_27       IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__USBH1_PWR       IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
-                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EPITO__SSI_EXT2_CLK    IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__TOG_EN          IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__GPT_CLKIN       IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_WDOG__WDOG             IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__GPIO_6_28        IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__WDOG_RST         IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__XTAL32K          IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SSI_TXFS__SSI_TXFS     IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__GPIO_6_0     IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SSI_TXC__SSI_TXC       IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__GPIO_6_1      IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SSI_TXD__SSI_TXD       IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__GPIO_6_2      IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__CSPI_RDY      IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SSI_RXD__SSI_RXD       IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__GPIO_6_3      IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__CSPI_SS3      IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
-
-#define MX50_PAD_SSI_RXFS__AUD3_RXFS    IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__GPIO_6_4     IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__WEIM_D6      IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__CSPI_SS2     IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_SSI_RXFS__FEC_COL      IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SSI_RXFS__FEC_MDC      IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_SSI_RXC__AUD3_RXC      IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__GPIO_6_5      IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__UART5_RXD     IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__WEIM_D7       IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__CSPI_SS1      IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_SSI_RXC__FEC_RX_CLK    IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__FEC_MDIO      IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
-
-#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__GPIO_6_6    IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RXD__GPIO_6_7    IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__GPIO_6_8    IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__SD4_D4      IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__SD4_CMD     IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__GPIO_6_9    IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__UART5_RXD   IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__GPIO_6_10   IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__SD4_D6      IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__SD4_D4      IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__GPIO_6_11   IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__SD4_D7      IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__SD4_D5      IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__GPIO_6_12   IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__SD4_CMD     IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__SD4_D6      IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__GPIO_6_13   IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__SD4_CLK     IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__SD4_D7      IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__GPIO_6_14   IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__SD1_D4      IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__SD4_D0      IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__SD2_WP      IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__WEIM_D12    IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_UART3_RXD__UART3_RXD   IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__GPIO_6_15   IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__SD1_D5      IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__SD4_D1      IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__SD2_CD      IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__WEIM_D13    IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__GPIO_6_16   IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__SD1_D6      IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__SD4_D2      IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__SD2_LCTL    IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__WEIM_D14    IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_UART4_RXD__UART4_RXD   IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__GPIO_6_17   IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__UART3_RTS   IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__SD1_D7      IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__SD4_D3      IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__SD1_LCTL    IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__WEIM_D15    IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_CSPI_SCLK__CSPI_SCLK   IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SCLK__GPIO_4_8    IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_CSPI_MOSI__CSPI_MOSI   IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MOSI__GPIO_4_9    IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_CSPI_MISO__CSPI_MISO   IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MISO__GPIO_4_10   IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_CSPI_SS0__CSPI_SS0     IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_CSPI_SS0__GPIO_4_11    IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK       IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12         IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY          IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY        IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__UART3_RTS         IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6        IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__WEIM_D8           IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI       IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13         IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1          IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1        IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7        IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__WEIM_D9           IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO       IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__GPIO_4_14         IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__CSPI_SS2          IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2        IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MISO__UART4_RTS         IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8        IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__WEIM_D10          IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0         IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__GPIO_4_15          IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_ECSPI1_SS0__CSPI_SS3           IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3         IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9         IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__WEIM_D11           IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK       IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16         IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR         IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY        IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__UART5_RTS         IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK     IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4        IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__WEIM_D8           IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI       IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17         IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD         IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1        IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN         IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5        IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__WEIM_D9           IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__GPIO_4_18         IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS         IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2        IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6        IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__WEIM_D10          IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0         IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_SS0__GPIO_4_19          IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS          IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3         IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_SS0__UART5_RXD          IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC       IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7         IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__WEIM_D11           IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__GPIO_5_0      IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__CLKO          IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__GPIO_5_1      IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__CLKO2         IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD1_D0__SD1_D0         IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D0__GPIO_5_2       IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D0__PLL1_BYP       IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD1_D1__SD1_D1         IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D1__GPIO_5_3       IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D1__PLL2_BYP       IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD1_D2__SD1_D2         IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D2__GPIO_5_4       IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D2__PLL3_BYP       IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD1_D3__SD1_D3         IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D3__GPIO_5_5       IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_CLK__SD2_CLK       IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__GPIO_5_6      IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__MSHC_SCLK     IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_SD2_CMD__SD2_CMD       IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__GPIO_5_7      IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__MSHC_BS       IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-
-#define MX50_PAD_SD2_D0__SD2_D0         IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D0__GPIO_5_8       IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D0__MSHC_D0        IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D0__KEY_COL4       IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D1__SD2_D1         IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D1__GPIO_5_9       IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D1__MSHC_D1        IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D1__KEY_ROW4       IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D2__SD2_D2         IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D2__GPIO_5_10      IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D2__MSHC_D2        IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D2__KEY_COL5       IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D3__SD2_D3         IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D3__GPIO_5_11      IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D3__MSHC_D3        IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D3__KEY_ROW5       IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D4__SD2_D4         IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D4__GPIO_5_12      IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__AUD4_RXFS      IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__KEY_COL6       IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__WEIM_D0        IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__CCM_OUT0       IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D5__SD2_D5         IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D5__GPIO_5_13      IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__AUD4_RXC       IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__KEY_ROW6       IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__WEIM_D1        IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__CCM_OUT1       IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D6__SD2_D6         IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D6__GPIO_5_14      IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__AUD4_RXD       IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__KEY_COL7       IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__WEIM_D2        IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__CCM_OUT2       IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_D7__SD2_D7         IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D7__GPIO_5_15      IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__AUD4_TXFS      IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__KEY_ROW7       IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__WEIM_D3        IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__CCM_STOP       IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_WP__SD2_WP         IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_WP__GPIO_5_16      IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__AUD4_TXD       IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__WEIM_D4        IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__CCM_WAIT       IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD2_CD__SD2_CD         IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CD__GPIO_5_17      IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__AUD4_TXC       IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__WEIM_D5        IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__CCM_REF_EN     IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ       IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ   IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B       IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1       IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B       IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0       IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS   IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD   IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB       IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI   IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK   IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO   IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D0__DISP_D0       IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D0__GPIO_2_0      IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__FEC_TXCLK     IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-
-#define MX50_PAD_DISP_D1__DISP_D1       IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D1__GPIO_2_1      IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__FEC_RX_ER     IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D1__WEIM_A17      IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D2__DISP_D2       IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D2__GPIO_2_2      IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__FEC_RX_DV     IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D2__WEIM_A18      IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D3__DISP_D3       IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D3__GPIO_2_3      IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__FEC_RXD1      IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D3__WEIM_A19      IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__FEC_COL       IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D4__DISP_D4       IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D4__GPIO_2_4      IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__FEC_RXD0      IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D4__WEIM_A20      IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D5__DISP_D5       IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D5__GPIO_2_5      IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__FEC_TX_EN     IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_DISP_D5__WEIM_A21      IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D6__DISP_D6       IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D6__GPIO_2_6      IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__FEC_TXD1      IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_DISP_D6__WEIM_A22      IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__FEC_RX_CLK    IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D7__DISP_D7       IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D7__GPIO_2_7      IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__FEC_TXD0      IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_DISP_D7__WEIM_A23      IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-
-
-#define MX50_PAD_DISP_WR__ELCDIF_WR     IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_WR__GPIO_2_16     IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_WR__WEIM_A24      IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_RD__ELCDIF_RD     IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RD__GPIO_2_19     IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__ELCDIF_EN     IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RD__WEIM_A25      IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RS__GPIO_2_17     IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__ELCDIF_VSYNC  IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RS__WEIM_A26      IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_CS__ELCDIF_CS     IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_CS__GPIO_2_21     IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__ELCDIF_HSYNC  IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_CS__WEIM_A27      IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__WEIM_CS3      IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC        IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__GPIO_2_18           IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__WEIM_CS3            IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__GPIO_2_20  IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__WEIM_CS3   IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_CMD__SD3_CMD       IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__GPIO_5_18     IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_CMD__NANDF_WRN     IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_CMD__SSP_CMD       IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_CLK__SD3_CLK       IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__GPIO_5_19     IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_CLK__NANDF_RDN     IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_CLK__SSP_CLK       IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D0__SD3_D0         IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D0__GPIO_5_20      IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D0__NANDF_D4       IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D0__SSP_D0         IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__PLL1_BYP       IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D1__SD3_D1         IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D1__GPIO_5_21      IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D1__NANDF_D5       IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D1__PLL2_BYP       IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D2__SD3_D2         IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D2__GPIO_5_22      IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D2__NANDF_D6       IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D2__SSP_D2         IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__PLL3_BYP       IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D3__SD3_D3         IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D3__GPIO_5_23      IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D3__NANDF_D7       IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D3__SSP_D3         IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D4__SD3_D4         IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D4__GPIO_5_24      IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D4__NANDF_D0       IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D4__SSP_D4         IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D5__SD3_D5         IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D5__GPIO_5_25      IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D5__NANDF_D1       IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D5__SSP_D5         IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D6__SD3_D6         IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D6__GPIO_5_26      IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D6__NANDF_D2       IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D6__SSP_D6         IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_D7__SD3_D7         IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D7__GPIO_5_27      IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D7__NANDF_D3       IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D7__SSP_D7         IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_SD3_WP__SD3_WP         IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_WP__GPIO_5_28      IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_WP__NANDF_RESETN   IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_WP__SSP_CD         IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__SD4_LCTL       IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_WP__WEIM_CS3       IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D8__DISP_D8       IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D8__GPIO_2_8      IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__NANDF_CLE     IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__SD1_LCTL      IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D8__SD4_CMD       IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D8__KEY_COL4      IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__FEC_TX_CLK    IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D9__DISP_D9       IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D9__GPIO_2_9      IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__NANDF_ALE     IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__SD2_LCTL      IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D9__SD4_CLK       IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D9__KEY_ROW4      IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__FEC_RX_ER     IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D10__DISP_D10     IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D10__GPIO_2_10    IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__NANDF_CEN0   IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__SD3_LCTL     IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D10__SD4_D0       IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D10__KEY_COL5     IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__FEC_RX_DV    IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D11__DISP_D11     IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D11__GPIO_2_11    IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__NANDF_CEN1   IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__SD4_D1       IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D11__KEY_ROW5     IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__FEC_RDAT1    IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D12__DISP_D12     IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D12__GPIO_2_12    IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__NANDF_CEN2   IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__SD1_CD       IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D12__SD4_D2       IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D12__KEY_COL6     IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__FEC_RDAT0    IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D13__DISP_D13     IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D13__GPIO_2_13    IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__NANDF_CEN3   IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__SD3_CD       IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D13__SD4_D3       IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D13__KEY_ROW6     IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__FEC_TX_EN    IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D14__DISP_D14     IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D14__GPIO_2_14    IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__NANDF_RDY0   IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__SD1_WP       IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D14__SD4_WP       IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D14__KEY_COL7     IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__FEC_TDAT1    IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_DISP_D15__DISP_D15     IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D15__GPIO_2_15    IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__NANDF_DQS    IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__SD3_RST      IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D15__SD4_CD       IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D15__KEY_ROW7     IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__FEC_TDAT0    IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D0__EPDC_D0       IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__GPIO_3_0      IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__WEIM_D0       IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__ELCDIF_RS     IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D1__EPDC_D1       IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__GPIO_3_1      IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__WEIM_D1       IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__ELCDIF_CS     IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__ELCDIF_EN     IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D2__EPDC_D2       IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__GPIO_3_2      IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__WEIM_D2       IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__ELCDIF_WR     IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC  IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D3__EPDC_D3       IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__GPIO_3_3      IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__WEIM_D3       IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__ELCDIF_RD     IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC  IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D4__EPDC_D4       IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__GPIO_3_4      IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__WEIM_D4       IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D5__EPDC_D5       IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__GPIO_3_5      IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__WEIM_D5       IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D6__EPDC_D6       IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__GPIO_3_6      IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__WEIM_D6       IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D7__EPDC_D7       IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__GPIO_3_7      IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__WEIM_D7       IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D8__EPDC_D8       IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__GPIO_3_8      IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__WEIM_D8       IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__ELCDIF_D24    IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D9__EPDC_D9       IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__GPIO_3_9      IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D10__EPDC_D10     IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__GPIO_3_10    IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__WEIM_D10     IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__ELCDIF_D26   IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D11__EPDC_D11     IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__GPIO_3_11    IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__WEIM_D11     IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__ELCDIF_D27   IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D12__EPDC_D12     IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__GPIO_3_12    IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__WEIM_D12     IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__ELCDIF_D28   IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D13__EPDC_D13     IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__GPIO_3_13    IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__WEIM_D13     IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__ELCDIF_D29   IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D14__EPDC_D14     IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__GPIO_3_14    IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__WEIM_D14     IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__ELCDIF_D30   IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__AUD6_TXD     IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_D15__EPDC_D15     IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__GPIO_3_15    IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__WEIM_D15     IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__ELCDIF_D31   IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__AUD6_TXC     IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__GPIO_3_16  IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__WEIM_D16   IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS  IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_GDSP__EPDC_GDSP   IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__GPIO_3_17   IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__WEIM_D17    IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__ELCDIF_D17  IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__AUD6_RXD    IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_GDOE__EPDC_GDOE   IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__GPIO_3_18   IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__WEIM_D18    IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__ELCDIF_D18  IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__AUD6_RXC    IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_GDRL__EPDC_GDRL   IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__GPIO_3_19   IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__WEIM_D19    IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__ELCDIF_D19  IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__AUD6_RXFS   IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__GPIO_3_20  IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__WEIM_D20   IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__AUD5_TXD   IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21  IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__WEIM_D21   IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC   IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__GPIO_3_22  IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__WEIM_D22   IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__AUD5_TXFS  IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDOE__EPDC_SDOE   IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__GPIO_3_23   IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__WEIM_D23    IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__ELCDIF_D23  IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__AUD5_RXD    IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDLE__EPDC_SDLE   IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__GPIO_3_24   IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__WEIM_D24    IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__ELCDIF_D8   IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__AUD5_RXC    IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN       IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25         IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__WEIM_D25          IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9         IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS         IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__GPIO_3_26  IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__WEIM_D26   IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__AUD4_TXD   IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM       IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27         IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__WEIM_D27          IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11        IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC          IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT     IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28        IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28         IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12       IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS        IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0   IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29       IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29        IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13      IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD        IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1   IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30       IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30        IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14      IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC        IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2   IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31       IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31        IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15      IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS       IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0       IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3        IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20       IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2        IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1       IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__GPIO_4_21  IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__WEIM_EB3   IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__GPIO_4_22  IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__WEIM_CS3   IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EPDC_BDR0__EPDC_BDR0   IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__GPIO_4_23   IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__ELCDIF_D7   IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_BDR1__EPDC_BDR1   IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__GPIO_4_24   IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__ELCDIF_D6   IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__GPIO_4_25  IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5  IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__GPIO_4_26  IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4  IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2         IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__GPIO_4_27          IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3        IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__GPIO_4_28  IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2  IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__GPIO_4_29  IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1  IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__GPIO_4_30  IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0  IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA0__WEIM_A0       IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__GPIO_1_0      IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__KEY_COL4      IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA1__WEIM_A1       IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__GPIO_1_1      IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__KEY_ROW4      IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
-
-#define MX50_PAD_EIM_DA2__WEIM_A2       IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__GPIO_1_2      IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__KEY_COL5      IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA3__WEIM_A3       IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__GPIO_1_3      IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__KEY_ROW5      IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
-
-#define MX50_PAD_EIM_DA4__WEIM_A4       IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__GPIO_1_4      IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__KEY_COL6      IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA5__WEIM_A5       IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__GPIO_1_5      IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__KEY_ROW6      IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
-
-#define MX50_PAD_EIM_DA6__WEIM_A6       IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__GPIO_1_6      IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__KEY_COL7      IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA7__WEIM_A7       IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__GPIO_1_7      IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__KEY_ROW7      IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
-
-#define MX50_PAD_EIM_DA8__WEIM_A8       IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__GPIO_1_8      IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA8__NANDF_CLE     IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_EIM_DA9__WEIM_A9       IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__GPIO_1_9      IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA9__NANDF_ALE     IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_EIM_DA10__WEIM_A10     IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__GPIO_1_10    IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA10__NANDF_CE0    IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_EIM_DA11__WEIM_A11     IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__GPIO_1_11    IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA11__NANDF_CE1    IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_EIM_DA12__WEIM_A12     IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__GPIO_1_12    IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA12__NANDF_CE2    IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA12__EPDC_SDCE6   IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA13__WEIM_A13     IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__GPIO_1_13    IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA13__NANDF_CE3    IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PIN_EIM_DA13__EPDC_SDCE7   IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA14__WEIM_A14     IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__GPIO_1_14    IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__NANDF_READY  IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
-                                                        PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_EIM_DA14__EPDC_SDCE8   IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_DA15__WEIM_A15     IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__GPIO_1_15    IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA15__NANDF_DQS    IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA15__EPDC_SDCE9   IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_CS2__WEIM_CS2      IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__GPIO_1_16     IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__WEIM_A27      IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_CS1__WEIM_CS1      IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__GPIO_1_17     IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_CS0__WEIM_CS0      IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS0__GPIO_1_18     IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_EB0__WEIM_EB0      IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB0__GPIO_1_19     IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_EB1__WEIM_EB1      IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB1__GPIO_1_20     IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_WAIT__WEIM_WAIT    IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__GPIO_1_21    IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_BCLK__WEIM_BCLK    IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_BCLK__GPIO_1_22    IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_RDY__WEIM_RDY      IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RDY__GPIO_1_23     IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_OE__WEIM_OE        IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_OE__GPIO_1_24      IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_RW__WEIM_RW        IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RW__GPIO_1_25      IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_LBA__WEIM_LBA      IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_LBA__GPIO_1_26     IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX50_PAD_EIM_CRE__WEIM_CRE      IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CRE__GPIO_1_27     IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
deleted file mode 100644
index 75bbcc4aa2d..00000000000
--- a/arch/arm/mach-imx/iomux-mx51.h
+++ /dev/null
@@ -1,827 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX51_H__
-#define __MACH_IOMUX_MX51_H__
-
-#include "iomux-v3.h"
-#define __NA_   0x000
-
-
-/* Pad control groupings */
-#define MX51_UART_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-#define MX51_I2C_PAD_CTRL       (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS)
-#define MX51_ESDHC_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS | PAD_CTL_PUE)
-#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_HYS | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
-                                PAD_CTL_SRE_FAST | PAD_CTL_DVS)
-#define MX51_GPIO_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-
-#define MX51_PAD_CTRL_2         (PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_3         (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_CTRL_4         (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_5         (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
-/*
- * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
- * See also iomux-v3.h
- */
-
-/* Raw pin modes without pad control */
-/*                                                        PAD    MUX ALT INPSE PATH PADCTRL */
-
-/* The same pins as above but with the default pad control values applied */
-#define MX51_PAD_EIM_D16__AUD4_RXFS             IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__AUD5_TXD              IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__EIM_D16               IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__GPIO2_0               IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D16__UART2_CTS             IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D16__USBH2_DATA0           IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__AUD5_RXD              IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__EIM_D17               IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__GPIO2_1               IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART2_RXD             IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART3_CTS             IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__USBH2_DATA1           IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__AUD5_TXC              IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__EIM_D18               IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__GPIO2_2               IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART2_TXD             IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART3_RTS             IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__USBH2_DATA2           IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD4_RXC              IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD5_TXFS             IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__EIM_D19               IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__GPIO2_3               IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D19__UART2_RTS             IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D19__USBH2_DATA3           IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__AUD4_TXD              IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__EIM_D20               IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__GPIO2_4               IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__USBH2_DATA4           IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__AUD4_RXD              IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__EIM_D21               IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO2_5               IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__USBH2_DATA5           IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__AUD4_TXC              IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__EIM_D22               IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__GPIO2_6               IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__USBH2_DATA6           IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__AUD4_TXFS             IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__EIM_D23               IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__GPIO2_7               IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__SPDIF_OUT1            IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__USBH2_DATA7           IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__AUD6_RXFS             IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__EIM_D24               IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__GPIO2_8               IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__I2C2_SDA              IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D24__USBOTG_DATA0          IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__EIM_D25               IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__KEY_COL6              IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__GPT_CMPOUT1           IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__GPT_CMPOUT2           IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__I2C2_SCL              IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D27__USBOTG_DATA3          IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__AUD6_TXD              IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__KEY_ROW4              IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__USBOTG_DATA4          IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__AUD6_RXD              IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__KEY_ROW5              IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__USBOTG_DATA5          IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__AUD6_TXC              IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__KEY_ROW6              IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__USBOTG_DATA6          IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__AUD6_TXFS             IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__KEY_ROW7              IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__USBOTG_DATA7          IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__EIM_A16               IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__GPIO2_10              IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__EIM_A17               IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__GPIO2_11              IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__BOOT_LPB0             IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__EIM_A18               IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__GPIO2_12              IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__BOOT_LPB1             IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__EIM_A19               IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__GPIO2_13              IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__EIM_A20               IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO2_14              IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__EIM_A21               IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__GPIO2_15              IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__EIM_A22               IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__GPIO2_16              IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__BOOT_HPN_EN           IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__EIM_A23               IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__GPIO2_17              IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__EIM_A24               IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__GPIO2_18              IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__USBH2_CLK             IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__DISP1_PIN4            IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__EIM_A25               IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__GPIO2_19              IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__USBH2_DIR             IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__CSI1_DATA_EN          IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__EIM_A26               IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__GPIO2_20              IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__USBH2_STP             IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__CSI2_DATA_EN          IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__DISP1_PIN1            IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__EIM_A27               IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__GPIO2_21              IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__USBH2_NXT             IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__AUD5_RXFS             IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__CSI1_D2               IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__EIM_EB2               IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO              (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
-                MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
-#define MX51_PAD_EIM_EB2__GPIO2_22              IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__AUD5_RXC              IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__CSI1_D3               IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__EIM_EB3               IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDATA1            IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPIO2_23              IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__EIM_OE                 IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__GPIO2_24               IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__EIM_CS0               IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__GPIO2_25              IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__EIM_CS1               IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__GPIO2_26              IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__AUD5_TXD              IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__CSI1_D4               IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__EIM_CS2               IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDATA2            IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__GPIO2_27              IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__USBOTG_STP            IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__AUD5_RXD              IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__CSI1_D5               IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__EIM_CS3               IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDATA3            IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__GPIO2_28              IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__USBOTG_NXT            IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__AUD5_TXC              IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__CSI1_D6               IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__EIM_CS4               IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS4__GPIO2_29              IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__USBOTG_CLK            IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__AUD5_TXFS             IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__CSI1_D7               IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__EIM_CS5               IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS5__GPIO2_30              IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__USBOTG_DIR            IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__EIM_DTACK           IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__GPIO2_31            IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__EIM_LBA               IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__GPIO3_1               IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__CCM_CLKO             IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__GPIO3_4            IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__PATA_DIOR          IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__GPIO3_5             IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__NANDF_ALE           IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__GPIO3_6             IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__NANDF_CLE           IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__PATA_RESET_B        IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__GPIO3_7            IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__PATA_DMACK         IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__GPIO3_8             IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__NANDF_RB0           IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__PATA_DMARQ          IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__CSPI_MOSI           IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2         IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3         IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB3__GPIO3_11            IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__NANDF_RB3           IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_CLK           IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__GPIO_NAND           IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__PATA_INTRQ          IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__GPIO3_16            IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__NANDF_CS0           IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__GPIO3_17            IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__NANDF_CS1           IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__CSPI_SCLK           IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS2__GPIO3_18            IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__NANDF_CS2           IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__PATA_CS_0           IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__SD4_CLK             IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS3__GPIO3_19            IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__NANDF_CS3           IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__PATA_CS_1           IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1          IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS4__GPIO3_20            IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__NANDF_CS4           IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__PATA_DA_0           IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__USBH3_STP           IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2          IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS5__GPIO3_21            IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__NANDF_CS5           IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__PATA_DA_1           IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__USBH3_DIR           IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__CSPI_SS3            IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3          IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS6__GPIO3_22            IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__NANDF_CS6           IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__PATA_DA_2           IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS7__GPIO3_23            IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__NANDF_CS7           IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__SD3_CLK             IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__GPIO3_25            IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__NANDF_D15           IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__PATA_DATA15         IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__SD3_DAT7            IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__ECSPI2_SS3          IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__GPIO3_26            IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__NANDF_D14           IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__PATA_DATA14         IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__SD3_DAT6            IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__ECSPI2_SS2          IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__GPIO3_27            IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__NANDF_D13           IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__PATA_DATA13         IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__SD3_DAT5            IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__ECSPI2_SS1          IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__GPIO3_28            IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__NANDF_D12           IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__PATA_DATA12         IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__SD3_DAT4            IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__FEC_RX_DV           IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__GPIO3_29            IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__NANDF_D11           IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__PATA_DATA11         IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__SD3_DATA3           IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__GPIO3_30            IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__NANDF_D10           IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__PATA_DATA10         IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__SD3_DATA2           IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__FEC_RDATA0           IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_D9__GPIO3_31             IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__NANDF_D9             IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__PATA_DATA9           IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__SD3_DATA1            IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__FEC_TDATA0           IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_D8__GPIO4_0              IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__NANDF_D8             IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__PATA_DATA8           IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__SD3_DATA0            IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__GPIO4_1              IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__NANDF_D7             IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__PATA_DATA7           IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__USBH3_DATA0          IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__GPIO4_2              IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__NANDF_D6             IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__PATA_DATA6           IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__SD4_LCTL             IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__USBH3_DATA1          IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__GPIO4_3              IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__NANDF_D5             IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__PATA_DATA5           IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__SD4_WP               IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__USBH3_DATA2          IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__GPIO4_4              IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__NANDF_D4             IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__PATA_DATA4           IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__SD4_CD               IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__USBH3_DATA3          IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__GPIO4_5              IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__NANDF_D3             IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__PATA_DATA3           IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__SD4_DAT4             IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__USBH3_DATA4          IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__GPIO4_6              IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__NANDF_D2             IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__PATA_DATA2           IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__SD4_DAT5             IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__USBH3_DATA5          IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__GPIO4_7              IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__NANDF_D1             IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__PATA_DATA1           IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__SD4_DAT6             IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__USBH3_DATA6          IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__GPIO4_8              IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__NANDF_D0             IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__PATA_DATA0           IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__SD4_DAT7             IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__USBH3_DATA7          IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__CSI1_D8               IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__GPIO3_12              IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__CSI1_D9               IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__GPIO3_13              IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__GPIO3_14           IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__GPIO3_15           IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__CSI2_D12             IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__GPIO4_9              IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__CSI2_D13             IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__GPIO4_10             IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__CSI2_D14             IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__CSI2_D15             IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__CSI2_D16             IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__CSI2_D17             IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__CSI2_D18             IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__GPIO4_11             IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__CSI2_D19             IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__GPIO4_12             IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__GPIO4_13           IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__GPIO4_14           IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__GPIO4_16             IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__I2C1_CLK             IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__GPIO4_17             IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__I2C1_DAT             IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__GPIO4_20           IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__GPIO4_21           IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__UART3_TXD          IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__GPIO4_22           IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__AUD4_RXD           IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__GPIO4_23           IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__AUD4_TXC            IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__GPIO4_24            IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__AUD4_TXD            IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__GPIO4_25            IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__GPIO4_26            IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__GPIO4_27           IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__GPIO4_28            IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__GPIO4_29            IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__PWM2_PWMO           IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__GPIO4_30            IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__GPIO4_31            IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__FIRI_TXD            IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__GPIO1_20            IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__FIRI_RXD            IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__GPIO1_21            IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__CSI1_D0             IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO1_22            IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART1_DTR           IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__CSI1_D1             IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO1_23            IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART1_DSR           IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__GPIO1_24           IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__PLL1_BYP             IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__PLL2_BYP             IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__PLL3_BYP             IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__SPDIF_OUT1           IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART1_RI             IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART1_DCD            IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__CSPI_SCLK           IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__GPIO1_25            IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__I2C2_SCL            IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__CSPI_MOSI           IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__GPIO1_26            IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__I2C2_SDA            IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__CSPI_RDY            IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO1_27            IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__UART3_RXD           IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__CSPI_MISO           IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__GPIO1_28            IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__UART3_TXD           IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__GPIO1_11          IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__UART2_CTS         IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__GPIO1_12          IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__UART2_RXD         IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__GPIO1_13          IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__UART2_TXD         IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__GPIO1_14          IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__UART2_RTS         IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__CSPI_SS0          IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__GPIO1_15          IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__CSPI_SS1          IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__GPIO1_16          IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__CSPI_SS3          IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__GPIO1_17          IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__GPIO1_18          IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__DI1_PIN11           IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__GPIO3_0             IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__DI1_PIN12           IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO3_1             IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__DI1_PIN13           IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO3_2             IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO3_3             IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO3_4             IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK     IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN15__DI1_PIN15           IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DISP1_SER_DIO          IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__FEC_TX_ER              IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__FEC_CRS              IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__FEC_MDC              IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__FEC_MDIO             IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI2_PIN15              IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP1_SER_DIN          IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP2_PIN1             IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__FEC_RDATA2             IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__KEY_COL6           IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__UART3_RXD          IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__USBH3_CLK          IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__KEY_COL7           IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__UART3_TXD          IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__USBH3_DIR          IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__KEY_ROW4           IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__USBH3_STP          IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__KEY_ROW5           IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__USBH3_NXT          IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__KEY_ROW6           IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__AUD6_RXC           IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__FEC_COL           IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__KEY_ROW7          IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__AUD6_TXD          IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__AUD6_RXD          IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__AUD6_TXC          IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__CSPI_MOSI             IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__CSPI_SCLK             IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__CSPI_MISO           IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__CSPI_SS1            IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__CSPI_SS2              IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__SD1_CD                IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__CSPI_MISO             IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__SD1_WP                IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__I2C1_SCL              IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__CSPI_SCLK             IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__I2C1_SDA              IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD2_DATA0__CSPI_MISO           IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD1_DAT4            IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD1_DAT5            IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD1_DAT6            IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__CSPI_SS2            IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD1_DAT7            IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__CCM_OUT_2             IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__I2C2_SCL              IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PLL1_BYP              IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__CCM_CLKO2             IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPT_CLKIN             IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPT_CAPIN1            IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CCM_CLKO              IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPT_CAPIN2            IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SPDIF_OUT1            IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CCM_CLKO2             IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_CLKO              IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
deleted file mode 100644
index 2b156d1d9e2..00000000000
--- a/arch/arm/mach-imx/iomux-v1.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * arch/arm/plat-mxc/iomux-v1.c
- *
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
- *
- * Common code for i.MX1, i.MX21 and i.MX27
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include "hardware.h"
-#include "iomux-v1.h"
-
-static void __iomem *imx_iomuxv1_baseaddr;
-static unsigned imx_iomuxv1_numports;
-
-static inline unsigned long imx_iomuxv1_readl(unsigned offset)
-{
-        return __raw_readl(imx_iomuxv1_baseaddr + offset);
-}
-
-static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
-{
-        __raw_writel(val, imx_iomuxv1_baseaddr + offset);
-}
-
-static inline void imx_iomuxv1_rmwl(unsigned offset,
-                unsigned long mask, unsigned long value)
-{
-        unsigned long reg = imx_iomuxv1_readl(offset);
-
-        reg &= ~mask;
-        reg |= value;
-
-        imx_iomuxv1_writel(reg, offset);
-}
-
-static inline void imx_iomuxv1_set_puen(
-                unsigned int port, unsigned int pin, int on)
-{
-        unsigned long mask = 1 << pin;
-
-        imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_ddir(
-                unsigned int port, unsigned int pin, int out)
-{
-        unsigned long mask = 1 << pin;
-
-        imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_gpr(
-                unsigned int port, unsigned int pin, int af)
-{
-        unsigned long mask = 1 << pin;
-
-        imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_gius(
-                unsigned int port, unsigned int pin, int inuse)
-{
-        unsigned long mask = 1 << pin;
-
-        imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_ocr(
-                unsigned int port, unsigned int pin, unsigned int ocr)
-{
-        unsigned long shift = (pin & 0xf) << 1;
-        unsigned long mask = 3 << shift;
-        unsigned long value = ocr << shift;
-        unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port);
-
-        imx_iomuxv1_rmwl(offset, mask, value);
-}
-
-static inline void imx_iomuxv1_set_iconfa(
-                unsigned int port, unsigned int pin, unsigned int aout)
-{
-        unsigned long shift = (pin & 0xf) << 1;
-        unsigned long mask = 3 << shift;
-        unsigned long value = aout << shift;
-        unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port);
-
-        imx_iomuxv1_rmwl(offset, mask, value);
-}
-
-static inline void imx_iomuxv1_set_iconfb(
-                unsigned int port, unsigned int pin, unsigned int bout)
-{
-        unsigned long shift = (pin & 0xf) << 1;
-        unsigned long mask = 3 << shift;
-        unsigned long value = bout << shift;
-        unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port);
-
-        imx_iomuxv1_rmwl(offset, mask, value);
-}
-
-int mxc_gpio_mode(int gpio_mode)
-{
-        unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-        unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-        unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
-        unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3;
-        unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3;
-
-        if (port >= imx_iomuxv1_numports)
-                return -EINVAL;
-
-        /* Pullup enable */
-        imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN);
-
-        /* Data direction */
-        imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT);
-
-        /* Primary / alternate function */
-        imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF);
-
-        /* use as gpio? */
-        imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF)));
-
-        imx_iomuxv1_set_ocr(port, pin, ocr);
-
-        imx_iomuxv1_set_iconfa(port, pin, aout);
-
-        imx_iomuxv1_set_iconfb(port, pin, bout);
-
-        return 0;
-}
-EXPORT_SYMBOL(mxc_gpio_mode);
-
-static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
-{
-        size_t i;
-        int ret = 0;
-
-        for (i = 0; i < count; ++i) {
-                ret = mxc_gpio_mode(list[i]);
-
-                if (ret)
-                        return ret;
-        }
-
-        return ret;
-}
-
-int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
-                const char *label)
-{
-        int ret;
-
-        ret = imx_iomuxv1_setup_multiple(pin_list, count);
-        return ret;
-}
-EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
-
-int __init imx_iomuxv1_init(void __iomem *base, int numports)
-{
-        imx_iomuxv1_baseaddr = base;
-        imx_iomuxv1_numports = numports;
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/iomux-v1.h b/arch/arm/mach-imx/iomux-v1.h
deleted file mode 100644
index 02651a40fe2..00000000000
--- a/arch/arm/mach-imx/iomux-v1.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_V1_H__
-#define __MACH_IOMUX_V1_H__
-
-/*
-*  GPIO Module and I/O Multiplexer
-*  x = 0..3 for reg_A, reg_B, reg_C, reg_D
-*/
-#define MXC_DDIR(x)     (0x00 + ((x) << 8))
-#define MXC_OCR1(x)     (0x04 + ((x) << 8))
-#define MXC_OCR2(x)     (0x08 + ((x) << 8))
-#define MXC_ICONFA1(x)  (0x0c + ((x) << 8))
-#define MXC_ICONFA2(x)  (0x10 + ((x) << 8))
-#define MXC_ICONFB1(x)  (0x14 + ((x) << 8))
-#define MXC_ICONFB2(x)  (0x18 + ((x) << 8))
-#define MXC_DR(x)       (0x1c + ((x) << 8))
-#define MXC_GIUS(x)     (0x20 + ((x) << 8))
-#define MXC_SSR(x)      (0x24 + ((x) << 8))
-#define MXC_ICR1(x)     (0x28 + ((x) << 8))
-#define MXC_ICR2(x)     (0x2c + ((x) << 8))
-#define MXC_IMR(x)      (0x30 + ((x) << 8))
-#define MXC_ISR(x)      (0x34 + ((x) << 8))
-#define MXC_GPR(x)      (0x38 + ((x) << 8))
-#define MXC_SWR(x)      (0x3c + ((x) << 8))
-#define MXC_PUEN(x)     (0x40 + ((x) << 8))
-
-#define MX1_NUM_GPIO_PORT       4
-#define MX21_NUM_GPIO_PORT      6
-#define MX27_NUM_GPIO_PORT      6
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA      (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB      (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC      (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD      (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE      (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF      (5 << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT        (1 << 8)
-#define GPIO_IN         (0 << 8)
-#define GPIO_PUEN       (1 << 9)
-
-#define GPIO_PF         (1 << 10)
-#define GPIO_AF         (1 << 11)
-
-#define GPIO_OCR_SHIFT 12
-#define GPIO_OCR_MASK   (3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN        (0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN        (1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN        (2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO       (3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT 14
-#define GPIO_AOUT_MASK  (3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT       (0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR   (1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0     (2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1     (3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT 16
-#define GPIO_BOUT_MASK  (3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT       (0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR   (1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0     (2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1     (3 << GPIO_BOUT_SHIFT)
-
-extern int mxc_gpio_mode(int gpio_mode);
-extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
-                const char *label);
-
-extern int imx_iomuxv1_init(void __iomem *base, int numports);
-
-#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
deleted file mode 100644
index 9dae74bf47f..00000000000
--- a/arch/arm/mach-imx/iomux-v3.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                       <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include "hardware.h"
-#include "iomux-v3.h"
-
-static void __iomem *base;
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
-{
-        u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
-        u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
-        u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
-        u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
-        u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
-        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
-        if (mux_ctrl_ofs)
-                __raw_writel(mux_mode, base + mux_ctrl_ofs);
-
-        if (sel_input_ofs)
-                __raw_writel(sel_input, base + sel_input_ofs);
-
-        if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
-                __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
-        return 0;
-}
-EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
-
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
-{
-        iomux_v3_cfg_t *p = pad_list;
-        int i;
-        int ret;
-
-        for (i = 0; i < count; i++) {
-                ret = mxc_iomux_v3_setup_pad(*p);
-                if (ret)
-                        return ret;
-                p++;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
-
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
-{
-        base = iomux_v3_base;
-}
diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h
deleted file mode 100644
index 2fa3b543010..00000000000
--- a/arch/arm/mach-imx/iomux-v3.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                      <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
-
-/*
- *      build IOMUX_PAD structure
- *
- * This iomux scheme is based around pads, which are the physical balls
- * on the processor.
- *
- * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
- *   things like driving strength and pullup/pulldown.
- * - Each pad can have but not necessarily does have an output routing register
- *   (IOMUXC_SW_MUX_CTL_PAD_x).
- * - Each pad can have but not necessarily does have an input routing register
- *   (IOMUXC_x_SELECT_INPUT)
- *
- * The three register sets do not have a fixed offset to each other,
- * hence we order this table by pad control registers (which all pads
- * have) and put the optional i/o routing registers into additional
- * fields.
- *
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num>
- *
- * IOMUX/PAD Bit field definitions
- *
- * MUX_CTRL_OFS:            0..11 (12)
- * PAD_CTRL_OFS:           12..23 (12)
- * SEL_INPUT_OFS:          24..35 (12)
- * MUX_MODE + SION:        36..40  (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
- * SEL_INP:                58..61  (4)
- * reserved:                 63    (1)
-*/
-
-typedef u64 iomux_v3_cfg_t;
-
-#define MUX_CTRL_OFS_SHIFT      0
-#define MUX_CTRL_OFS_MASK       ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
-#define MUX_PAD_CTRL_OFS_SHIFT  12
-#define MUX_PAD_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
-#define MUX_SEL_INPUT_OFS_SHIFT 24
-#define MUX_SEL_INPUT_OFS_MASK  ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
-
-#define MUX_MODE_SHIFT          36
-#define MUX_MODE_MASK           ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT      41
-#define MUX_PAD_CTRL_MASK       ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT     58
-#define MUX_SEL_INPUT_MASK      ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-
-#define MUX_PAD_CTRL(x)         ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
-
-#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
-                _sel_input, _pad_ctrl)                                  \
-        (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) |      \
-                ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) |       \
-                ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
-                ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) |   \
-                ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
-                ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
-
-#define NEW_PAD_CTRL(cfg, pad)  (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
-/*
- * Use to set PAD control
- */
-
-#define NO_PAD_CTRL                     (1 << 16)
-#define PAD_CTL_DVS                     (1 << 13)
-#define PAD_CTL_HYS                     (1 << 8)
-
-#define PAD_CTL_PKE                     (1 << 7)
-#define PAD_CTL_PUE                     (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN           (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP              (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP             (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP              (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE                     (1 << 3)
-
-#define PAD_CTL_DSE_LOW                 (0 << 1)
-#define PAD_CTL_DSE_MED                 (1 << 1)
-#define PAD_CTL_DSE_HIGH                (2 << 1)
-#define PAD_CTL_DSE_MAX                 (3 << 1)
-
-#define PAD_CTL_SRE_FAST                (1 << 0)
-#define PAD_CTL_SRE_SLOW                (0 << 0)
-
-#define IOMUX_CONFIG_SION               (0x1 << 4)
-
-#define MX51_NUM_GPIO_PORT      4
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA      (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB      (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC      (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD      (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE      (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF      (5 << GPIO_PORT_SHIFT)
-
-/*
- * setups a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-
-/*
- * setups mutliple pads
- * convenient way to call the above function with tables
- */
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
-
-/*
- * Initialise the iomux controller
- */
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
-
-#endif /* __MACH_IOMUX_V3_H__*/
-
diff --git a/arch/arm/mach-imx/iram.h b/arch/arm/mach-imx/iram.h
deleted file mode 100644
index 022690c3370..00000000000
--- a/arch/arm/mach-imx/iram.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/errno.h>
-
-#ifdef CONFIG_IRAM_ALLOC
-
-int __init iram_init(unsigned long base, unsigned long size);
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
-void iram_free(unsigned long dma_addr, unsigned int size);
-
-#else
-
-static inline int __init iram_init(unsigned long base, unsigned long size)
-{
-        return -ENOMEM;
-}
-
-static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-        return NULL;
-}
-
-static inline void iram_free(unsigned long base, unsigned long size) {}
-
-#endif
diff --git a/arch/arm/mach-imx/iram_alloc.c b/arch/arm/mach-imx/iram_alloc.c
deleted file mode 100644
index 6c80424f678..00000000000
--- a/arch/arm/mach-imx/iram_alloc.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/genalloc.h>
-
-#include "iram.h"
-
-static unsigned long iram_phys_base;
-static void __iomem *iram_virt_base;
-static struct gen_pool *iram_pool;
-
-static inline void __iomem *iram_phys_to_virt(unsigned long p)
-{
-        return iram_virt_base + (p - iram_phys_base);
-}
-
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-        if (!iram_pool)
-                return NULL;
-
-        *dma_addr = gen_pool_alloc(iram_pool, size);
-        pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr);
-        if (!*dma_addr)
-                return NULL;
-        return iram_phys_to_virt(*dma_addr);
-}
-EXPORT_SYMBOL(iram_alloc);
-
-void iram_free(unsigned long addr, unsigned int size)
-{
-        if (!iram_pool)
-                return;
-
-        gen_pool_free(iram_pool, addr, size);
-}
-EXPORT_SYMBOL(iram_free);
-
-int __init iram_init(unsigned long base, unsigned long size)
-{
-        iram_phys_base = base;
-
-        iram_pool = gen_pool_create(PAGE_SHIFT, -1);
-        if (!iram_pool)
-                return -ENOMEM;
-
-        gen_pool_add(iram_pool, base, size, -1);
-        iram_virt_base = ioremap(iram_phys_base, size);
-        if (!iram_virt_base)
-                return -EIO;
-
-        pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base);
-        return 0;
-}
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
deleted file mode 100644
index b6e11458e5a..00000000000
--- a/arch/arm/mach-imx/irq-common.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) BitBox Ltd 2010
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-
-#include "irq-common.h"
-
-int imx_irq_set_priority(unsigned char irq, unsigned char prio)
-{
-        struct irq_chip_generic *gc;
-        struct mxc_extra_irq *exirq;
-        int ret;
-
-        ret = -ENOSYS;
-
-        gc = irq_get_chip_data(irq);
-        if (gc && gc->private) {
-                exirq = gc->private;
-                if (exirq->set_priority)
-                        ret = exirq->set_priority(irq, prio);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(imx_irq_set_priority);
-
-int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
-{
-        struct irq_chip_generic *gc;
-        struct mxc_extra_irq *exirq;
-        int ret;
-
-        ret = -ENOSYS;
-
-        gc = irq_get_chip_data(irq);
-        if (gc && gc->private) {
-                exirq = gc->private;
-                if (exirq->set_irq_fiq)
-                        ret = exirq->set_irq_fiq(irq, type);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(mxc_set_irq_fiq);
diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h
deleted file mode 100644
index 5b2dabba330..00000000000
--- a/arch/arm/mach-imx/irq-common.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) BitBox Ltd 2010
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __PLAT_MXC_IRQ_COMMON_H__
-#define __PLAT_MXC_IRQ_COMMON_H__
-
-/* all normal IRQs can be FIQs */
-#define FIQ_START       0
-
-struct mxc_extra_irq
-{
-        int (*set_priority)(unsigned char irq, unsigned char prio);
-        int (*set_irq_fiq)(unsigned int irq, unsigned int type);
-};
-
-#endif
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
deleted file mode 100644
index 2fdc9bf2fb5..00000000000
--- a/arch/arm/mach-imx/lluart.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <asm/mach/map.h>
-
-#include "hardware.h"
-
-#define IMX6Q_UART1_BASE_ADDR   0x02020000
-#define IMX6Q_UART2_BASE_ADDR   0x021e8000
-#define IMX6Q_UART3_BASE_ADDR   0x021ec000
-#define IMX6Q_UART4_BASE_ADDR   0x021f0000
-#define IMX6Q_UART5_BASE_ADDR   0x021f4000
-
-/*
- * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
- * of IMX6Q_UART##n##_BASE_ADDR.
- */
-#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
-#define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
-#define IMX6Q_DEBUG_UART_BASE   IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
-
-static struct map_desc imx_lluart_desc = {
-#ifdef CONFIG_DEBUG_IMX6Q_UART
-        .virtual        = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
-        .pfn            = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
-        .length         = 0x4000,
-        .type           = MT_DEVICE,
-#endif
-};
-
-void __init imx_lluart_map_io(void)
-{
-        if (imx_lluart_desc.virtual)
-                iotable_init(&imx_lluart_desc, 1);
-}
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 5c9bd2c66e6..a404c89485c 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -18,17 +18,17 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/dm9000.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/iomux-mx1.h>
+
 #include "devices-imx1.h"
-#include "hardware.h"
-#include "iomux-mx1.h"
 
 static const int apf9328_pins[] __initconst = {
         /* UART1 */
@@ -41,9 +41,6 @@ static const int apf9328_pins[] __initconst = {
         PB29_PF_UART2_RTS,
         PB30_PF_UART2_TXD,
         PB31_PF_UART2_RXD,
-        /* I2C */
-        PA15_PF_I2C_SDA,
-        PA16_PF_I2C_SCL,
 };
 
 /*
@@ -86,7 +83,8 @@ static struct resource dm9000_resources[] = {
                 .end    = MX1_CS4_PHYS + 0x00C00003,
                 .flags  = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start  = IRQ_GPIOB(14),
+                .end    = IRQ_GPIOB(14),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -105,10 +103,6 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
 static struct platform_device *devices[] __initdata = {
         &apf9328_flash_device,
         &dm9000x_device,
@@ -125,10 +119,6 @@ static void __init apf9328_init(void)
         imx1_add_imx_uart0(NULL);
         imx1_add_imx_uart1(&uart1_pdata);
 
-        imx1_add_imx_i2c(&apf9328_i2c_data);
-
-        dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14));
-        dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14));
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
@@ -146,8 +136,6 @@ MACHINE_START(APF9328, "Armadeus APF9328")
         .map_io       = mx1_map_io,
         .init_early   = imx1_init_early,
         .init_irq     = mx1_init_irq,
-        .handle_irq   = imx1_handle_irq,
         .timer        = &apf9328_timer,
         .init_machine = apf9328_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 59bd6b06a6b..ede2710f8b7 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -38,21 +38,20 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/delay.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
+
 #include "devices-imx31.h"
-#include "crmregs-imx3.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
+#include "crmregs-imx31.h"
 
 static int armadillo5x0_pins[] = {
         /* UART1 */
@@ -315,19 +314,25 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
         },
 };
 
-static const struct physmap_flash_data
-                armadillo5x0_nor_flash_pdata __initconst = {
+static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
         .width          = 2,
         .parts          = armadillo5x0_nor_flash_partitions,
         .nr_parts       = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
 };
 
-static const struct resource armadillo5x0_nor_flash_resource __initconst = {
+static struct resource armadillo5x0_nor_flash_resource = {
         .flags          = IORESOURCE_MEM,
         .start          = MX31_CS0_BASE_ADDR,
         .end            = MX31_CS0_BASE_ADDR + SZ_64M - 1,
 };
 
+static struct platform_device armadillo5x0_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = -1,
+        .num_resources          = 1,
+        .resource               = &armadillo5x0_nor_flash_resource,
+};
+
 /*
  * FB support
  */
@@ -366,6 +371,10 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "CRT-VGA",
         .mode           = fb_modedb,
@@ -403,8 +412,7 @@ static int armadillo5x0_sdhc1_init(struct device *dev,
         gpio_direction_input(gpio_wp);
 
         /* When supported the trigger type have to be BOTH */
-        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
-                          detect_irq,
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
                           IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                           "sdhc-detect", data);
 
@@ -425,7 +433,7 @@ err_gpio_free:
 
 static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
         gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
         gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
 }
@@ -446,7 +454,8 @@ static struct resource armadillo5x0_smc911x_resources[] = {
                 .end    = MX31_CS3_BASE_ADDR + SZ_32M - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -476,11 +485,6 @@ static struct platform_device *devices[] __initdata = {
         &armadillo5x0_smc911x_device,
 };
 
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
 /*
  * Perform board specific initializations
  */
@@ -491,12 +495,6 @@ static void __init armadillo5x0_init(void)
         mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
                         ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        armadillo5x0_smc911x_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
-        armadillo5x0_smc911x_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
         platform_add_devices(devices, ARRAY_SIZE(devices));
         imx_add_gpio_keys(&armadillo5x0_button_data);
         imx31_add_imx_i2c1(NULL);
@@ -512,21 +510,18 @@ static void __init armadillo5x0_init(void)
         imx31_add_mxc_mmc(0, &sdhc_pdata);
 
         /* Register FB */
-        imx31_add_ipu_core();
+        imx31_add_ipu_core(&mx3_ipu_data);
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* Register NOR Flash */
-        platform_device_register_resndata(NULL, "physmap-flash", -1,
-                        &armadillo5x0_nor_flash_resource, 1,
-                        &armadillo5x0_nor_flash_pdata,
-                        sizeof(armadillo5x0_nor_flash_pdata));
+        mxc_register_device(&armadillo5x0_nor_flash,
+                            &armadillo5x0_nor_flash_pdata);
 
         /* Register NAND Flash */
         imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
 
         /* set NAND page size to 2k if not configured via boot mode pins */
-        __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) |
-                                        (1 << 30), mx3_ccm_base + MXC_CCM_RCSR);
+        __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
 
         /* RTC */
         /* Get RTC IRQ and register the chip */
@@ -563,12 +558,10 @@ static struct sys_timer armadillo5x0_timer = {
 
 MACHINE_START(ARMADILLO5X0, "Armadillo-500")
         /* Maintainer: Alberto Panizzo  */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &armadillo5x0_timer,
         .init_machine = armadillo5x0_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 3a39d5aec07..f49470553bd 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -19,14 +19,15 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
+#include <mach/iomux-mx3.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
 #include <asm/mach/time.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
@@ -61,8 +62,6 @@ MACHINE_START(BUG, "BugLabs BUGBase")
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &bug_timer,
         .init_machine = bug_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 12a370646b4..f851fe90368 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -34,12 +34,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx27.h>
+#include <mach/ulpi.h>
+
 #include "devices-imx27.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
 
 static const int eukrea_cpuimx27_pins[] __initconst = {
         /* UART1 */
@@ -168,28 +169,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
-                /* irq number is run-time assigned */
+                .irq = IRQ_GPIOB(23),
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
-                /* irq number is run-time assigned */
+                .irq = IRQ_GPIOB(22),
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
-                /* irq number is run-time assigned */
+                .irq = IRQ_GPIOB(27),
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
-                /* irq number is run-time assigned */
+                .irq = IRQ_GPIOB(30),
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
@@ -232,18 +233,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init eukrea_cpuimx27_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", eukrea_cpuimx27_otg_mode);
 
@@ -265,8 +266,8 @@ static void __init eukrea_cpuimx27_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt();
-        imx27_add_mxc_w1();
+        imx27_add_imx2_wdt(NULL);
+        imx27_add_mxc_w1(NULL);
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         /* SDHC2 can be used for Wifi */
@@ -278,10 +279,6 @@ static void __init eukrea_cpuimx27_init(void)
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-        serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
-        serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
-        serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
-        serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
         platform_device_register(&serial_device);
 #endif
 
@@ -314,12 +311,10 @@ static struct sys_timer eukrea_cpuimx27_timer = {
 };
 
 MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &eukrea_cpuimx27_timer,
         .init_machine = eukrea_cpuimx27_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 5a31bf8c8f4..4bd083ba9af 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -37,11 +37,12 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+
 #include "devices-imx35.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
@@ -52,25 +53,20 @@ static const struct imxi2c_platform_data
         .bitrate =              100000,
 };
 
-#define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 2)
-static int tsc2007_get_pendown_state(void)
-{
-        return !gpio_get_value(TSC2007_IRQGPIO);
-}
-
 static struct tsc2007_platform_data tsc2007_info = {
         .model                  = 2007,
         .x_plate_ohms           = 180,
-        .get_pendown_state = tsc2007_get_pendown_state,
 };
 
+#define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 2)
 static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8563", 0x51),
         }, {
                 I2C_BOARD_INFO("tsc2007", 0x48),
+                .type           = "tsc2007",
                 .platform_data  = &tsc2007_info,
-                /* irq number is run-time assigned */
+                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
         },
 };
 
@@ -140,18 +136,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init eukrea_cpuimx35_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
 
@@ -166,12 +162,11 @@ static void __init eukrea_cpuimx35_init(void)
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt();
+        imx35_add_imx2_wdt(NULL);
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
 
-        eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
         i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
                         ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
         imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
@@ -193,18 +188,16 @@ static void __init eukrea_cpuimx35_timer_init(void)
         mx35_clocks_init();
 }
 
-static struct sys_timer eukrea_cpuimx35_timer = {
+struct sys_timer eukrea_cpuimx35_timer = {
         .init   = eukrea_cpuimx35_timer_init,
 };
 
 MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
         /* Maintainer: Eukrea Electromatique */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
         .timer = &eukrea_cpuimx35_timer,
         .init_machine = eukrea_cpuimx35_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
deleted file mode 100644
index b727de029c8..00000000000
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * based on board-mx51_babbage.c which is
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/i2c-gpio.h>
-#include <linux/spi/spi.h>
-#include <linux/can/platform/mcp251x.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx51.h"
-#include "cpu_op-mx51.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-
-#define USBH1_RST               IMX_GPIO_NR(2, 28)
-#define ETH_RST                 IMX_GPIO_NR(2, 31)
-#define TSC2007_IRQGPIO_REV2    IMX_GPIO_NR(3, 12)
-#define TSC2007_IRQGPIO_REV3    IMX_GPIO_NR(4, 0)
-#define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
-#define CAN_RST                 IMX_GPIO_NR(4, 15)
-#define CAN_NCS                 IMX_GPIO_NR(4, 24)
-#define CAN_RXOBF_REV2          IMX_GPIO_NR(1, 4)
-#define CAN_RXOBF_REV3          IMX_GPIO_NR(3, 12)
-#define CAN_RX1BF               IMX_GPIO_NR(1, 6)
-#define CAN_TXORTS              IMX_GPIO_NR(1, 7)
-#define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
-#define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
-#define I2C_SCL                 IMX_GPIO_NR(4, 16)
-#define I2C_SDA                 IMX_GPIO_NR(4, 17)
-
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-
-#define MX51_USB_PLLDIV_12_MHZ          0x00
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define MX51_USB_PLL_DIV_24_MHZ         0x02
-
-static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-        MX51_PAD_USBH1_STP__USBH1_STP,
-        MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
-
-        /* FEC */
-        MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
-
-        /* HSI2C */
-        MX51_PAD_I2C1_CLK__GPIO4_16,
-        MX51_PAD_I2C1_DAT__GPIO4_17,
-
-        /* I2C1 */
-        MX51_PAD_SD2_CMD__I2C1_SCL,
-        MX51_PAD_SD2_CLK__I2C1_SDA,
-
-        /* CAN */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
-        MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
-        MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
-        MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
-        MX51_PAD_GPIO1_6__GPIO1_6,
-        MX51_PAD_GPIO1_7__GPIO1_7,
-        MX51_PAD_GPIO1_8__GPIO1_8,
-        MX51_PAD_GPIO1_9__GPIO1_9,
-
-        /* Touchscreen */
-        /* IRQ */
-        NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-        NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static int tsc2007_get_pendown_state(void)
-{
-        if (mx51_revision() < IMX_CHIP_REVISION_3_0)
-                return !gpio_get_value(TSC2007_IRQGPIO_REV2);
-        else
-                return !gpio_get_value(TSC2007_IRQGPIO_REV3);
-}
-
-static struct tsc2007_platform_data tsc2007_info = {
-        .model                  = 2007,
-        .x_plate_ohms           = 180,
-        .get_pendown_state      = tsc2007_get_pendown_state,
-};
-
-static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        }, {
-                I2C_BOARD_INFO("tsc2007", 0x49),
-                .platform_data  = &tsc2007_info,
-        },
-};
-
-static const struct mxc_nand_platform_data
-                eukrea_cpuimx51sd_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        /* The clock for the USBH1 ULPI port will come from the PHY. */
-        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                        usbother_base + MX51_USB_CTRL_1_OFFSET);
-        iounmap(usb_base);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                        MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init           = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-        .init           = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init eukrea_cpuimx51sd_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
-
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = I2C_SDA,
-        .sda_is_open_drain      = 0,
-        .scl_pin                = I2C_SCL,
-        .scl_is_open_drain      = 0,
-        .udelay                 = 2,
-};
-
-static struct platform_device hsi2c_gpio_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-
-static struct mcp251x_platform_data mcp251x_info = {
-        .oscillator_frequency = 24E6,
-};
-
-static struct spi_board_info cpuimx51sd_spi_device[] = {
-        {
-                .modalias        = "mcp2515",
-                .max_speed_hz    = 10000000,
-                .bus_num         = 0,
-                .mode           = SPI_MODE_0,
-                .chip_select     = 0,
-                .platform_data   = &mcp251x_info,
-                /* irq number is run-time assigned */
-        },
-};
-
-static int cpuimx51sd_spi1_cs[] = {
-        CAN_NCS,
-};
-
-static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
-        .chipselect     = cpuimx51sd_spi1_cs,
-        .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
-};
-
-static struct platform_device *rev2_platform_devices[] __initdata = {
-        &hsi2c_gpio_device,
-};
-
-static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static void __init eukrea_cpuimx51sd_init(void)
-{
-        imx51_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
-                                        ARRAY_SIZE(eukrea_cpuimx51sd_pads));
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
-        imx51_add_imx2_wdt(0);
-
-        gpio_request(ETH_RST, "eth_rst");
-        gpio_set_value(ETH_RST, 1);
-        imx51_add_fec(NULL);
-
-        gpio_request(CAN_IRQGPIO, "can_irq");
-        gpio_direction_input(CAN_IRQGPIO);
-        gpio_free(CAN_IRQGPIO);
-        gpio_request(CAN_NCS, "can_ncs");
-        gpio_direction_output(CAN_NCS, 1);
-        gpio_free(CAN_NCS);
-        gpio_request(CAN_RST, "can_rst");
-        gpio_direction_output(CAN_RST, 0);
-        msleep(20);
-        gpio_set_value(CAN_RST, 1);
-        imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
-        cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
-        spi_register_board_info(cpuimx51sd_spi_device,
-                                ARRAY_SIZE(cpuimx51sd_spi_device));
-
-        if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
-                eukrea_cpuimx51sd_i2c_devices[1].irq =
-                        gpio_to_irq(TSC2007_IRQGPIO_REV2),
-                platform_add_devices(rev2_platform_devices,
-                        ARRAY_SIZE(rev2_platform_devices));
-                gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
-                gpio_direction_input(TSC2007_IRQGPIO_REV2);
-                gpio_free(TSC2007_IRQGPIO_REV2);
-        } else {
-                eukrea_cpuimx51sd_i2c_devices[1].irq =
-                        gpio_to_irq(TSC2007_IRQGPIO_REV3),
-                imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
-                gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
-                gpio_direction_input(TSC2007_IRQGPIO_REV3);
-                gpio_free(TSC2007_IRQGPIO_REV3);
-        }
-
-        i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
-                        ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
-
-        if (otg_mode_host)
-                imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        else {
-                initialize_otg_port(NULL);
-                imx51_add_fsl_usb2_udc(&usb_pdata);
-        }
-
-        gpio_request(USBH1_RST, "usb_rst");
-        gpio_direction_output(USBH1_RST, 0);
-        msleep(20);
-        gpio_set_value(USBH1_RST, 1);
-        imx51_add_mxc_ehci_hs(1, &usbh1_config);
-
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
-        eukrea_mbimxsd51_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx51sd_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mxc_timer = {
-        .init   = eukrea_cpuimx51sd_timer_init,
-};
-
-MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
-        /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mxc_timer,
-        .init_machine = eukrea_cpuimx51sd_init,
-        .init_late      = imx51_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 75027a5ad8b..2442d5da883 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -27,18 +27,18 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include <mach/iomux-mx25.h>
 
-#include "common.h"
 #include "devices-imx25.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
@@ -106,21 +106,20 @@ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI,
-        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init eukrea_cpuimx25_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", eukrea_cpuimx25_otg_mode);
 
@@ -134,9 +133,8 @@ static void __init eukrea_cpuimx25_init(void)
 
         imx25_add_imx_uart0(&uart_pdata);
         imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
-        imx25_add_imxdi_rtc();
+        imx25_add_imxdi_rtc(NULL);
         imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx2_wdt();
 
         i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
@@ -165,12 +163,10 @@ static struct sys_timer eukrea_cpuimx25_timer = {
 
 MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
         /* Maintainer: Eukrea Electromatique */
-        .atag_offset = 0x100,
+        .boot_params = MX25_PHYS_OFFSET + 0x100,
         .map_io = mx25_map_io,
         .init_early = imx25_init_early,
         .init_irq = mx25_init_irq,
-        .handle_irq = imx25_handle_irq,
         .timer = &eukrea_cpuimx25_timer,
         .init_machine = eukrea_cpuimx25_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 318bd8df7fc..6778f8193bc 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,43 +30,17 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/leds.h>
-#include <linux/platform_data/asoc-mx27vis.h>
-#include <media/soc_camera.h>
 #include <sound/tlv320aic32x4.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <asm/system_info.h>
-#include <asm/memblock.h>
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
 
-#include "common.h"
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
 
-#define TVP5150_RSTN (GPIO_PORTC + 18)
-#define TVP5150_PWDN (GPIO_PORTC + 19)
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
-#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25)
-
-#define VERSION_MASK            0x7
-#define MOTHERBOARD_SHIFT       4
-#define EXPBOARD_SHIFT          0
-
-#define MOTHERBOARD_BIT2        (GPIO_PORTD + 31)
-#define MOTHERBOARD_BIT1        (GPIO_PORTD + 30)
-#define MOTHERBOARD_BIT0        (GPIO_PORTD + 29)
-
-#define EXPBOARD_BIT2           (GPIO_PORTD + 25)
-#define EXPBOARD_BIT1           (GPIO_PORTD + 27)
-#define EXPBOARD_BIT0           (GPIO_PORTD + 28)
-
-#define AMP_GAIN_0              (GPIO_PORTF + 9)
-#define AMP_GAIN_1              (GPIO_PORTF + 8)
-#define AMP_MUTE_SDL            (GPIO_PORTE + 5)
-#define AMP_MUTE_SDR            (GPIO_PORTF + 7)
+#define SDHC1_IRQ IRQ_GPIOB(25)
 
 static const int visstrim_m10_pins[] __initconst = {
         /* UART1 (console) */
@@ -126,152 +100,8 @@ static const int visstrim_m10_pins[] __initconst = {
         PE1_PF_USBOTG_STP,
         PB23_PF_USB_PWR,
         PB24_PF_USB_OC,
-        /* CSI */
-        TVP5150_RSTN | GPIO_GPIO | GPIO_OUT,
-        TVP5150_PWDN | GPIO_GPIO | GPIO_OUT,
-        PB10_PF_CSI_D0,
-        PB11_PF_CSI_D1,
-        PB12_PF_CSI_D2,
-        PB13_PF_CSI_D3,
-        PB14_PF_CSI_D4,
-        PB15_PF_CSI_MCLK,
-        PB16_PF_CSI_PIXCLK,
-        PB17_PF_CSI_D5,
-        PB18_PF_CSI_D6,
-        PB19_PF_CSI_D7,
-        PB20_PF_CSI_VSYNC,
-        PB21_PF_CSI_HSYNC,
-        /* mother board version */
-        MOTHERBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
-        MOTHERBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
-        MOTHERBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
-        /* expansion board version */
-        EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
-        EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
-        EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
-        /* Audio AMP control */
-        AMP_GAIN_0 | GPIO_GPIO | GPIO_OUT,
-        AMP_GAIN_1 | GPIO_GPIO | GPIO_OUT,
-        AMP_MUTE_SDL | GPIO_GPIO | GPIO_OUT,
-        AMP_MUTE_SDR | GPIO_GPIO | GPIO_OUT,
-};
-
-static struct gpio visstrim_m10_version_gpios[] = {
-        { EXPBOARD_BIT0, GPIOF_IN, "exp-version-0" },
-        { EXPBOARD_BIT1, GPIOF_IN, "exp-version-1" },
-        { EXPBOARD_BIT2, GPIOF_IN, "exp-version-2" },
-        { MOTHERBOARD_BIT0, GPIOF_IN, "mother-version-0" },
-        { MOTHERBOARD_BIT1, GPIOF_IN, "mother-version-1" },
-        { MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" },
-};
-
-static const struct gpio visstrim_m10_gpios[] __initconst = {
-        {
-                .gpio = TVP5150_RSTN,
-                .flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
-                .label = "tvp5150_rstn",
-        },
-        {
-                .gpio = TVP5150_PWDN,
-                .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
-                .label = "tvp5150_pwdn",
-        },
-        {
-                .gpio = OTG_PHY_CS_GPIO,
-                .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
-                .label = "usbotg_cs",
-        },
-        {
-                .gpio = AMP_GAIN_0,
-                .flags = GPIOF_DIR_OUT,
-                .label = "amp-gain-0",
-        },
-        {
-                .gpio = AMP_GAIN_1,
-                .flags = GPIOF_DIR_OUT,
-                .label = "amp-gain-1",
-        },
-        {
-                .gpio = AMP_MUTE_SDL,
-                .flags = GPIOF_DIR_OUT,
-                .label = "amp-mute-sdl",
-        },
-        {
-                .gpio = AMP_MUTE_SDR,
-                .flags = GPIOF_DIR_OUT,
-                .label = "amp-mute-sdr",
-        },
-};
-
-/* Camera */
-static int visstrim_camera_power(struct device *dev, int on)
-{
-        gpio_set_value(TVP5150_PWDN, on);
-
-        return 0;
-};
-
-static int visstrim_camera_reset(struct device *dev)
-{
-        gpio_set_value(TVP5150_RSTN, 0);
-        ndelay(500);
-        gpio_set_value(TVP5150_RSTN, 1);
-
-        return 0;
-};
-
-static struct i2c_board_info visstrim_i2c_camera =  {
-        I2C_BOARD_INFO("tvp5150", 0x5d),
 };
 
-static struct soc_camera_link iclink_tvp5150 = {
-        .bus_id         = 0,
-        .board_info     = &visstrim_i2c_camera,
-        .i2c_adapter_id = 0,
-        .power = visstrim_camera_power,
-        .reset = visstrim_camera_reset,
-};
-
-static struct mx2_camera_platform_data visstrim_camera = {
-        .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE |
-                 MX2_CAMERA_PCLK_SAMPLE_RISING,
-        .clk = 100000,
-};
-
-static phys_addr_t mx2_camera_base __initdata;
-#define MX2_CAMERA_BUF_SIZE SZ_8M
-
-static void __init visstrim_analog_camera_init(void)
-{
-        struct platform_device *pdev;
-        int dma;
-
-        gpio_set_value(TVP5150_PWDN, 1);
-        ndelay(1);
-        gpio_set_value(TVP5150_RSTN, 0);
-        ndelay(500);
-        gpio_set_value(TVP5150_RSTN, 1);
-        ndelay(200000);
-
-        pdev = imx27_add_mx2_camera(&visstrim_camera);
-        if (IS_ERR(pdev))
-                return;
-
-        dma = dma_declare_coherent_memory(&pdev->dev,
-                                mx2_camera_base, mx2_camera_base,
-                                MX2_CAMERA_BUF_SIZE,
-                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-        if (!(dma & DMA_MEMORY_MAP))
-                return;
-}
-
-static void __init visstrim_reserve(void)
-{
-        /* reserve 4 MiB for mx2-camera */
-        mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE,
-                        MX2_CAMERA_BUF_SIZE);
-}
-
 /* GPIOs used as events for applications */
 static struct gpio_keys_button visstrim_gpio_keys[] = {
         {
@@ -306,49 +136,20 @@ static const struct gpio_keys_platform_data
         .nbuttons       = ARRAY_SIZE(visstrim_gpio_keys),
 };
 
-/* led */
-static const struct gpio_led visstrim_m10_leds[] __initconst = {
-        {
-                .name = "visstrim:ld0",
-                .default_trigger = "nand-disk",
-                .gpio = (GPIO_PORTC + 29),
-        },
-        {
-                .name = "visstrim:ld1",
-                .default_trigger = "nand-disk",
-                .gpio = (GPIO_PORTC + 24),
-        },
-        {
-                .name = "visstrim:ld2",
-                .default_trigger = "nand-disk",
-                .gpio = (GPIO_PORTC + 28),
-        },
-        {
-                .name = "visstrim:ld3",
-                .default_trigger = "nand-disk",
-                .gpio = (GPIO_PORTC + 25),
-        },
-};
-
-static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = {
-        .leds = visstrim_m10_leds,
-        .num_leds = ARRAY_SIZE(visstrim_m10_leds),
-};
-
 /* Visstrim_SM10 has a microSD slot connected to sdhc1 */
 static int visstrim_m10_sdhc1_init(struct device *dev,
                 irq_handler_t detect_irq, void *data)
 {
         int ret;
 
-        ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq,
-                          IRQF_TRIGGER_FALLING, "mmc-detect", data);
+        ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
+                                "mmc-detect", data);
         return ret;
 }
 
 static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data);
+        free_irq(SDHC1_IRQ, data);
 }
 
 static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
@@ -415,15 +216,16 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("tlv320aic32x4", 0x18),
                 .platform_data = &visstrim_m10_aic32x4_pdata,
-        },
-        {
-                 I2C_BOARD_INFO("m41t00", 0x68),
         }
 };
 
 /* USB OTG */
 static int otg_phy_init(struct platform_device *pdev)
 {
+        gpio_set_value(OTG_PHY_CS_GPIO, 0);
+
+        mdelay(10);
+
         return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 
@@ -438,159 +240,29 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
         .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
 
-/* coda */
-
-static void __init visstrim_coda_init(void)
-{
-        struct platform_device *pdev;
-        int dma;
-
-        pdev = imx27_add_coda();
-        dma = dma_declare_coherent_memory(&pdev->dev,
-                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
-                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
-                                          MX2_CAMERA_BUF_SIZE,
-                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-        if (!(dma & DMA_MEMORY_MAP))
-                return;
-}
-
-/* DMA deinterlace */
-static struct platform_device visstrim_deinterlace = {
-        .name = "m2m-deinterlace",
-        .id = 0,
-};
-
-static void __init visstrim_deinterlace_init(void)
-{
-        int ret = -ENOMEM;
-        struct platform_device *pdev = &visstrim_deinterlace;
-        int dma;
-
-        ret = platform_device_register(pdev);
-
-        dma = dma_declare_coherent_memory(&pdev->dev,
-                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
-                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
-                                          MX2_CAMERA_BUF_SIZE,
-                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-        if (!(dma & DMA_MEMORY_MAP))
-                return;
-}
-
-/* Emma-PrP for format conversion */
-static void __init visstrim_emmaprp_init(void)
-{
-        struct platform_device *pdev;
-        int dma;
-
-        pdev = imx27_add_mx2_emmaprp();
-        if (IS_ERR(pdev))
-                return;
-
-        /*
-         * Use the same memory area as the analog camera since both
-         * devices are, by nature, exclusive.
-         */
-        dma = dma_declare_coherent_memory(&pdev->dev,
-                                mx2_camera_base, mx2_camera_base,
-                                MX2_CAMERA_BUF_SIZE,
-                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-        if (!(dma & DMA_MEMORY_MAP))
-                pr_err("Failed to declare memory for emmaprp\n");
-}
-
-/* Audio */
-static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = {
-        .amp_gain0_gpio = AMP_GAIN_0,
-        .amp_gain1_gpio = AMP_GAIN_1,
-        .amp_mutel_gpio = AMP_MUTE_SDL,
-        .amp_muter_gpio = AMP_MUTE_SDR,
-};
-
-static void __init visstrim_m10_revision(void)
-{
-        int exp_version = 0;
-        int mo_version = 0;
-        int ret;
-
-        ret = gpio_request_array(visstrim_m10_version_gpios,
-                                 ARRAY_SIZE(visstrim_m10_version_gpios));
-        if (ret) {
-                pr_err("Failed to request version gpios");
-                return;
-        }
-
-        /* Get expansion board version (negative logic) */
-        exp_version |= !gpio_get_value(EXPBOARD_BIT2) << 2;
-        exp_version |= !gpio_get_value(EXPBOARD_BIT1) << 1;
-        exp_version |= !gpio_get_value(EXPBOARD_BIT0);
-
-        /* Get mother board version (negative logic) */
-        mo_version |= !gpio_get_value(MOTHERBOARD_BIT2) << 2;
-        mo_version |= !gpio_get_value(MOTHERBOARD_BIT1) << 1;
-        mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
-
-        system_rev = 0x27000;
-        system_rev |= (mo_version << MOTHERBOARD_SHIFT);
-        system_rev |= (exp_version << EXPBOARD_SHIFT);
-}
-
 static void __init visstrim_m10_board_init(void)
 {
         int ret;
-        int mo_version;
 
         imx27_soc_init();
-        visstrim_m10_revision();
 
         ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
                         ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
         if (ret)
                 pr_err("Failed to setup pins (%d)\n", ret);
 
-        ret = gpio_request_array(visstrim_m10_gpios,
-                                ARRAY_SIZE(visstrim_m10_gpios));
-        if (ret)
-                pr_err("Failed to request gpios (%d)\n", ret);
-
         imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
         imx27_add_imx_uart0(&uart_pdata);
 
-        imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
-        imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
         i2c_register_board_info(0, visstrim_m10_i2c_devices,
                                 ARRAY_SIZE(visstrim_m10_i2c_devices));
-
+        imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
+        imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
         imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
         imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
         imx27_add_fec(NULL);
         imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata,
-                                sizeof(snd_mx27vis_pdata));
-        platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
-                                      &iclink_tvp5150, sizeof(iclink_tvp5150));
-        gpio_led_register_device(0, &visstrim_m10_led_data);
-
-        /* Use mother board version to decide what video devices we shall use */
-        mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
-        if (mo_version & 0x1) {
-                visstrim_emmaprp_init();
-
-                /*
-                 * Despite not being used, tvp5150 must be
-                 * powered on to avoid I2C problems. To minimize
-                 * power consupmtion keep reset enabled.
-                 */
-                gpio_set_value(TVP5150_PWDN, 1);
-                ndelay(1);
-                gpio_set_value(TVP5150_RSTN, 0);
-        } else {
-                visstrim_deinterlace_init();
-                visstrim_analog_camera_init();
-        }
-        visstrim_coda_init();
 }
 
 static void __init visstrim_m10_timer_init(void)
@@ -603,13 +275,10 @@ static struct sys_timer visstrim_m10_timer = {
 };
 
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
-        .atag_offset = 0x100,
-        .reserve = visstrim_reserve,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &visstrim_m10_timer,
         .init_machine = visstrim_m10_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 53a86011293..272f793e924 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -17,11 +17,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
 
-#include "hardware.h"
-#include "common.h"
 #include "devices-imx27.h"
-#include "iomux-mx27.h"
 
 static const int mx27ipcam_pins[] __initconst = {
         /* UART1 */
@@ -57,7 +57,7 @@ static void __init mx27ipcam_init(void)
 
         imx27_add_imx_uart0(NULL);
         imx27_add_fec(NULL);
-        imx27_add_imx2_wdt();
+        imx27_add_imx2_wdt(NULL);
 }
 
 static void __init mx27ipcam_timer_init(void)
@@ -71,12 +71,10 @@ static struct sys_timer mx27ipcam_timer = {
 
 MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &mx27ipcam_timer,
         .init_machine = mx27ipcam_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index fc8dce93137..d81a769fe89 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -20,11 +20,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
 
-#include "common.h"
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
 
 static const int mx27lite_pins[] __initconst = {
         /* UART1 */
@@ -77,12 +77,10 @@ static struct sys_timer mx27lite_timer = {
 };
 
 MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &mx27lite_timer,
         .init_machine = mx27lite_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
deleted file mode 100644
index 860284dea0e..00000000000
--- a/arch/arm/mach-imx/mach-imx53.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "mx53.h"
-
-static void __init imx53_qsb_init(void)
-{
-        struct clk *clk;
-
-        clk = clk_get_sys(NULL, "ssi_ext1");
-        if (IS_ERR(clk)) {
-                pr_err("failed to get clk ssi_ext1\n");
-                return;
-        }
-
-        clk_register_clkdev(clk, NULL, "0-000a");
-}
-
-static void __init imx53_dt_init(void)
-{
-        if (of_machine_is_compatible("fsl,imx53-qsb"))
-                imx53_qsb_init();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static void __init imx53_timer_init(void)
-{
-        mx53_clocks_init_dt();
-}
-
-static struct sys_timer imx53_timer = {
-        .init = imx53_timer_init,
-};
-
-static const char *imx53_dt_board_compat[] __initdata = {
-        "fsl,imx53",
-        NULL
-};
-
-DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
-        .map_io         = mx53_map_io,
-        .init_early     = imx53_init_early,
-        .init_irq       = mx53_init_irq,
-        .handle_irq     = imx53_handle_irq,
-        .timer          = &imx53_timer,
-        .init_machine   = imx53_dt_init,
-        .init_late      = imx53_init_late,
-        .dt_compat      = imx53_dt_board_compat,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
deleted file mode 100644
index 4eb1b3ac794..00000000000
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/cpuidle.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/phy.h>
-#include <linux/regmap.h>
-#include <linux/micrel_phy.h>
-#include <linux/mfd/syscon.h>
-#include <asm/cpuidle.h>
-#include <asm/smp_twd.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/system_misc.h>
-
-#include "common.h"
-#include "cpuidle.h"
-#include "hardware.h"
-
-#define IMX6Q_ANALOG_DIGPROG    0x260
-
-static int imx6q_revision(void)
-{
-        struct device_node *np;
-        void __iomem *base;
-        static u32 rev;
-
-        if (!rev) {
-                np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-                if (!np)
-                        return IMX_CHIP_REVISION_UNKNOWN;
-                base = of_iomap(np, 0);
-                if (!base) {
-                        of_node_put(np);
-                        return IMX_CHIP_REVISION_UNKNOWN;
-                }
-                rev =  readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
-                iounmap(base);
-                of_node_put(np);
-        }
-
-        switch (rev & 0xff) {
-        case 0:
-                return IMX_CHIP_REVISION_1_0;
-        case 1:
-                return IMX_CHIP_REVISION_1_1;
-        case 2:
-                return IMX_CHIP_REVISION_1_2;
-        default:
-                return IMX_CHIP_REVISION_UNKNOWN;
-        }
-}
-
-void imx6q_restart(char mode, const char *cmd)
-{
-        struct device_node *np;
-        void __iomem *wdog_base;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
-        wdog_base = of_iomap(np, 0);
-        if (!wdog_base)
-                goto soft;
-
-        imx_src_prepare_restart();
-
-        /* enable wdog */
-        writew_relaxed(1 << 2, wdog_base);
-        /* write twice to ensure the request will not get ignored */
-        writew_relaxed(1 << 2, wdog_base);
-
-        /* wait for reset to assert ... */
-        mdelay(500);
-
-        pr_err("Watchdog reset failed to assert reset\n");
-
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-
-soft:
-        /* we'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
-
-/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
-static int ksz9021rn_phy_fixup(struct phy_device *phydev)
-{
-        if (IS_BUILTIN(CONFIG_PHYLIB)) {
-                /* min rx data delay */
-                phy_write(phydev, 0x0b, 0x8105);
-                phy_write(phydev, 0x0c, 0x0000);
-
-                /* max rx/tx clock delay, min rx/tx control delay */
-                phy_write(phydev, 0x0b, 0x8104);
-                phy_write(phydev, 0x0c, 0xf0f0);
-                phy_write(phydev, 0x0b, 0x104);
-        }
-
-        return 0;
-}
-
-static void __init imx6q_sabrelite_cko1_setup(void)
-{
-        struct clk *cko1_sel, *ahb, *cko1;
-        unsigned long rate;
-
-        cko1_sel = clk_get_sys(NULL, "cko1_sel");
-        ahb = clk_get_sys(NULL, "ahb");
-        cko1 = clk_get_sys(NULL, "cko1");
-        if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
-                pr_err("cko1 setup failed!\n");
-                goto put_clk;
-        }
-        clk_set_parent(cko1_sel, ahb);
-        rate = clk_round_rate(cko1, 16000000);
-        clk_set_rate(cko1, rate);
-put_clk:
-        if (!IS_ERR(cko1_sel))
-                clk_put(cko1_sel);
-        if (!IS_ERR(ahb))
-                clk_put(ahb);
-        if (!IS_ERR(cko1))
-                clk_put(cko1);
-}
-
-static void __init imx6q_sabrelite_init(void)
-{
-        if (IS_BUILTIN(CONFIG_PHYLIB))
-                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-                                ksz9021rn_phy_fixup);
-        imx6q_sabrelite_cko1_setup();
-}
-
-static void __init imx6q_1588_init(void)
-{
-        struct regmap *gpr;
-
-        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-        if (!IS_ERR(gpr))
-                regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
-        else
-                pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
-
-}
-static void __init imx6q_usb_init(void)
-{
-        struct regmap *anatop;
-
-#define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
-#define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
-
-#define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
-#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
-
-        anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
-        if (!IS_ERR(anatop)) {
-                /*
-                 * The external charger detector needs to be disabled,
-                 * or the signal at DP will be poor
-                 */
-                regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
-                                BM_ANADIG_USB_CHRG_DETECT_EN_B
-                                | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
-                regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
-                                BM_ANADIG_USB_CHRG_DETECT_EN_B |
-                                BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
-        } else {
-                pr_warn("failed to find fsl,imx6q-anatop regmap\n");
-        }
-}
-
-static void __init imx6q_init_machine(void)
-{
-        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
-                imx6q_sabrelite_init();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-
-        imx6q_pm_init();
-        imx6q_usb_init();
-        imx6q_1588_init();
-}
-
-static struct cpuidle_driver imx6q_cpuidle_driver = {
-        .name                   = "imx6q_cpuidle",
-        .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
-        .states[0]              = ARM_CPUIDLE_WFI_STATE,
-        .state_count            = 1,
-};
-
-static void __init imx6q_init_late(void)
-{
-        imx_cpuidle_init(&imx6q_cpuidle_driver);
-}
-
-static void __init imx6q_map_io(void)
-{
-        imx_lluart_map_io();
-        imx_scu_map_io();
-        imx6q_clock_map_io();
-}
-
-static const struct of_device_id imx6q_irq_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { /* sentinel */ }
-};
-
-static void __init imx6q_init_irq(void)
-{
-        l2x0_of_init(0, ~0UL);
-        imx_src_init();
-        imx_gpc_init();
-        of_irq_init(imx6q_irq_match);
-}
-
-static void __init imx6q_timer_init(void)
-{
-        mx6q_clocks_init();
-        twd_local_timer_of_register();
-        imx_print_silicon_rev("i.MX6Q", imx6q_revision());
-}
-
-static struct sys_timer imx6q_timer = {
-        .init = imx6q_timer_init,
-};
-
-static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q",
-        NULL,
-};
-
-DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
-        .smp            = smp_ops(imx_smp_ops),
-        .map_io         = imx6q_map_io,
-        .init_irq       = imx6q_init_irq,
-        .handle_irq     = imx6q_handle_irq,
-        .timer          = &imx6q_timer,
-        .init_machine   = imx6q_init_machine,
-        .init_late      = imx6q_init_late,
-        .dt_compat      = imx6q_dt_compat,
-        .restart        = imx6q_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 2e536ea5344..e472a1d8805 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -24,8 +24,6 @@
 #include <linux/serial_8250.h>
 #include <linux/smsc911x.h>
 #include <linux/types.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -36,10 +34,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include "common.h"
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
 
 #define KZM_ARM11_IO_ADDRESS(x) (IOMEM(                                 \
         IMX_IO_P2V_MODULE(x, MX31_CS4) ?:                               \
@@ -71,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .membase        = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
                 .mapbase        = KZM_ARM11_16550,
-                /* irq number is run-time assigned */
+                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
                 .irqflags       = IRQ_TYPE_EDGE_RISING,
                 .uartclk        = 14745600,
                 .regshift       = 0,
@@ -89,7 +88,8 @@ static struct resource serial8250_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                /* irq number is run-time assigned */
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -122,13 +122,6 @@ static int __init kzm_init_ext_uart(void)
         tmp |= 0x2;
         __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
 
-        serial_platform_data[0].irq =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-        serial8250_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-        serial8250_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
         return platform_device_register(&serial_device);
 }
 #else
@@ -156,7 +149,8 @@ static struct resource kzm_smsc9118_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                /* irq number is run-time assigned */
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         },
 };
@@ -171,11 +165,6 @@ static struct platform_device kzm_smsc9118_device = {
                           },
 };
 
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
 static int __init kzm_init_smsc9118(void)
 {
         /*
@@ -185,13 +174,6 @@ static int __init kzm_init_smsc9118(void)
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
 
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        kzm_smsc9118_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
-        kzm_smsc9118_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
-
         return platform_device_register(&kzm_smsc9118_device);
 }
 #else
@@ -257,13 +239,13 @@ static void __init kzm_board_init(void)
  */
 static struct map_desc kzm_io_desc[] __initdata = {
         {
-                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length         = MX31_CS4_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
+                .virtual        = MX31_CS5_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS5_BASE_ADDR),
                 .length         = MX31_CS5_SIZE,
                 .type           = MT_DEVICE
@@ -289,12 +271,10 @@ static struct sys_timer kzm_timer = {
 };
 
 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = kzm_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &kzm_timer,
         .init_machine = kzm_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 06b483783e6..5cd8bee4696 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -23,10 +23,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx1.h>
+#include <mach/irqs.h>
+
 #include "devices-imx1.h"
-#include "hardware.h"
-#include "iomux-mx1.h"
 
 static const int mx1ads_pins[] __initconst = {
         /* UART1 */
@@ -66,16 +68,23 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
  * Physmap flash
  */
 
-static const struct physmap_flash_data mx1ads_flash_data __initconst = {
+static struct physmap_flash_data mx1ads_flash_data = {
         .width          = 4,            /* bankwidth in bytes */
 };
 
-static const struct resource flash_resource __initconst = {
+static struct resource flash_resource = {
         .start  = MX1_CS0_PHYS,
         .end    = MX1_CS0_PHYS + SZ_32M - 1,
         .flags  = IORESOURCE_MEM,
 };
 
+static struct platform_device flash_device = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .resource = &flash_resource,
+        .num_resources = 1,
+};
+
 /*
  * I2C
  */
@@ -116,9 +125,7 @@ static void __init mx1ads_init(void)
         imx1_add_imx_uart1(&uart1_pdata);
 
         /* Physmap flash */
-        platform_device_register_resndata(NULL, "physmap-flash", 0,
-                        &flash_resource, 1,
-                        &mx1ads_flash_data, sizeof(mx1ads_flash_data));
+        mxc_register_device(&flash_device, &mx1ads_flash_data);
 
         /* I2C */
         i2c_register_board_info(0, mx1ads_i2c_devices,
@@ -132,29 +139,25 @@ static void __init mx1ads_timer_init(void)
         mx1_clocks_init(32000);
 }
 
-static struct sys_timer mx1ads_timer = {
+struct sys_timer mx1ads_timer = {
         .init   = mx1ads_timer_init,
 };
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
         /* Maintainer: Sascha Hauer, Pengutronix */
-        .atag_offset = 0x100,
+        .boot_params = MX1_PHYS_OFFSET + 0x100,
         .map_io = mx1_map_io,
         .init_early = imx1_init_early,
         .init_irq = mx1_init_irq,
-        .handle_irq = imx1_handle_irq,
         .timer = &mx1ads_timer,
         .init_machine = mx1ads_init,
-        .restart        = mxc_restart,
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .atag_offset = 0x100,
+        .boot_params = MX1_PHYS_OFFSET + 0x100,
         .map_io = mx1_map_io,
         .init_early = imx1_init_early,
         .init_irq = mx1_init_irq,
-        .handle_irq = imx1_handle_irq,
         .timer = &mx1ads_timer,
         .init_machine = mx1ads_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 6adb3136bb0..d389ecf9b5a 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -18,27 +18,27 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <mach/iomux-mx21.h>
 
-#include "common.h"
 #include "devices-imx21.h"
-#include "hardware.h"
-#include "iomux-mx21.h"
 
 /*
  * Memory-mapped I/O on MX21ADS base board
  */
 #define MX21ADS_MMIO_BASE_ADDR   0xf5000000
-#define MX21ADS_MMIO_SIZE        0xc00000
+#define MX21ADS_MMIO_SIZE        SZ_16M
 
 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
                 (MX21ADS_MMIO_BASE_ADDR + (offset))
 
-#define MX21ADS_CS8900A_MMIO_SIZE   0x200000
-#define MX21ADS_CS8900A_IRQ_GPIO    IMX_GPIO_NR(5, 11)
+#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
@@ -159,19 +159,6 @@ static struct platform_device mx21ads_nor_mtd_device = {
         .resource = &mx21ads_flash_resource,
 };
 
-static struct resource mx21ads_cs8900_resources[] __initdata = {
-        DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
-        /* irq number is run-time assigned */
-        DEFINE_RES_IRQ(-1),
-};
-
-static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
-        .name = "cs89x0",
-        .id = 0,
-        .res = mx21ads_cs8900_resources,
-        .num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
-};
-
 static const struct imxuart_platform_data uart_pdata_rts __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -242,13 +229,13 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
         void *data)
 {
-        return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
+        return request_irq(IRQ_GPIOD(25), detect_irq,
                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
 }
 
 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
+        free_irq(IRQ_GPIOD(25), data);
 }
 
 static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
@@ -305,12 +292,6 @@ static void __init mx21ads_board_init(void)
         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-        mx21ads_cs8900_resources[1].start =
-                        gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
-        mx21ads_cs8900_resources[1].end =
-                        gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
-        platform_device_register_full(&mx21ads_cs8900_devinfo);
 }
 
 static void __init mx21ads_timer_init(void)
@@ -324,12 +305,10 @@ static struct sys_timer mx21ads_timer = {
 
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX21_PHYS_OFFSET + 0x100,
         .map_io = mx21ads_map_io,
         .init_early = imx21_init_early,
         .init_irq = mx21_init_irq,
-        .handle_irq = imx21_handle_irq,
         .timer = &mx21ads_timer,
         .init_machine = mx21ads_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index b1b03aa55bb..7f66a91df36 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -31,19 +31,17 @@
 #include <linux/platform_device.h>
 #include <linux/usb/otg.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include <mach/iomux-mx25.h>
 
-#include "common.h"
 #include "devices-imx25.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-
-#define MX25PDK_CAN_PWDN        IMX_GPIO_NR(4, 6)
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
@@ -110,11 +108,6 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
         /* I2C1 */
         MX25_PAD_I2C1_CLK__I2C1_CLK,
         MX25_PAD_I2C1_DAT__I2C1_DAT,
-
-        /* CAN1 */
-        MX25_PAD_GPIO_A__CAN1_TX,
-        MX25_PAD_GPIO_B__CAN1_RX,
-        MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
 };
 
 static const struct fec_platform_data mx25_fec_pdata __initconst = {
@@ -237,9 +230,9 @@ static void __init mx25pdk_init(void)
         imx25_add_fsl_usb2_udc(&otg_device_pdata);
         imx25_add_mxc_ehci_hs(&usbh2_pdata);
         imx25_add_mxc_nand(&mx25pdk_nand_board_info);
-        imx25_add_imxdi_rtc();
+        imx25_add_imxdi_rtc(NULL);
         imx25_add_imx_fb(&mx25pdk_fb_pdata);
-        imx25_add_imx2_wdt();
+        imx25_add_imx2_wdt(NULL);
 
         mx25pdk_fec_reset();
         imx25_add_fec(&mx25_fec_pdata);
@@ -247,9 +240,6 @@ static void __init mx25pdk_init(void)
 
         imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
         imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
-
-        gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
-        imx25_add_flexcan0(NULL);
 }
 
 static void __init mx25pdk_timer_init(void)
@@ -263,12 +253,10 @@ static struct sys_timer mx25pdk_timer = {
 
 MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX25_PHYS_OFFSET + 0x100,
         .map_io = mx25_map_io,
         .init_early = imx25_init_early,
         .init_irq = mx25_init_irq,
-        .handle_irq = imx25_handle_irq,
         .timer = &mx25pdk_timer,
         .init_machine = mx25pdk_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index d0e547fa925..6fa6934ab15 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -31,29 +31,27 @@
 #include <linux/regulator/machine.h>
 #include <linux/spi/l4f00242t03.h>
 
-#include <media/soc_camera.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+#include <mach/ulpi.h>
+#include <mach/irqs.h>
+#include <mach/3ds_debugboard.h>
 
-#include "3ds_debugboard.h"
-#include "common.h"
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
 
 #define SD1_EN_GPIO             IMX_GPIO_NR(2, 25)
 #define OTG_PHY_RESET_GPIO      IMX_GPIO_NR(2, 23)
 #define SPI2_SS0                IMX_GPIO_NR(4, 21)
+#define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(3, 28))
 #define PMIC_INT                IMX_GPIO_NR(3, 14)
 #define SPI1_SS0                IMX_GPIO_NR(4, 28)
 #define SD1_CD                  IMX_GPIO_NR(2, 26)
 #define LCD_RESET               IMX_GPIO_NR(1, 3)
 #define LCD_ENABLE              IMX_GPIO_NR(1, 31)
-#define CSI_PWRDWN              IMX_GPIO_NR(4, 19)
-#define CSI_RESET               IMX_GPIO_NR(3, 6)
 
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
@@ -143,31 +141,6 @@ static const int mx27pdk_pins[] __initconst = {
         PA30_PF_CONTRAST,
         LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
         LCD_RESET | GPIO_GPIO | GPIO_OUT,
-        /* CSI */
-        PB10_PF_CSI_D0,
-        PB11_PF_CSI_D1,
-        PB12_PF_CSI_D2,
-        PB13_PF_CSI_D3,
-        PB14_PF_CSI_D4,
-        PB15_PF_CSI_MCLK,
-        PB16_PF_CSI_PIXCLK,
-        PB17_PF_CSI_D5,
-        PB18_PF_CSI_D6,
-        PB19_PF_CSI_D7,
-        PB20_PF_CSI_VSYNC,
-        PB21_PF_CSI_HSYNC,
-        CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
-        CSI_RESET | GPIO_GPIO | GPIO_OUT,
-        /* SSI4 */
-        PC16_PF_SSI4_FS,
-        PC17_PF_SSI4_RXD,
-        PC18_PF_SSI4_TXD,
-        PC19_PF_SSI4_CLK,
-};
-
-static struct gpio mx27_3ds_camera_gpios[] = {
-        { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" },
-        { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" },
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -244,18 +217,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init mx27_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", mx27_3ds_otg_mode);
 
@@ -268,8 +241,7 @@ static struct regulator_init_data gpo_init = {
 };
 
 static struct regulator_consumer_supply vmmc1_consumers[] = {
-        REGULATOR_SUPPLY("vcore", "spi0.0"),
-        REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
+        REGULATOR_SUPPLY("lcd_2v8", NULL),
 };
 
 static struct regulator_init_data vmmc1_init = {
@@ -285,7 +257,7 @@ static struct regulator_init_data vmmc1_init = {
 };
 
 static struct regulator_consumer_supply vgen_consumers[] = {
-        REGULATOR_SUPPLY("vdd", "spi0.0"),
+        REGULATOR_SUPPLY("vdd_lcdio", NULL),
 };
 
 static struct regulator_init_data vgen_init = {
@@ -298,22 +270,6 @@ static struct regulator_init_data vgen_init = {
         .consumer_supplies = vgen_consumers,
 };
 
-static struct regulator_consumer_supply vvib_consumers[] = {
-        REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
-};
-
-static struct regulator_init_data vvib_init = {
-        .constraints = {
-                .min_uV = 1300000,
-                .max_uV = 1300000,
-                .apply_uV = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
-        .consumer_supplies = vvib_consumers,
-};
-
 static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         {
                 .id = MC13783_REG_VMMC1,
@@ -327,31 +283,18 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         }, {
                 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
                 .init_data = &gpo_init,
-        }, {
-                .id = MC13783_REG_VVIB,  /* Power OV2640 */
-                .init_data = &vvib_init,
         },
 };
 
 /* MC13783 */
-static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
-        .dac_ssi_port = MC13783_SSI1_PORT,
-        .adc_ssi_port = MC13783_SSI1_PORT,
-};
-
 static struct mc13xxx_platform_data mc13783_pdata = {
         .regulators = {
                 .regulators = mx27_3ds_regulators,
                 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
 
         },
-        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
-                                                MC13XXX_USE_CODEC,
-        .codec = &mx27_3ds_codec,
-};
-
-static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
-        .flags = IMX_SSI_DMA | IMX_SSI_NET,
+        .flags  = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN |
+        MC13783_USE_RTC,
 };
 
 /* SPI */
@@ -369,51 +312,6 @@ static const struct spi_imx_master spi2_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(spi2_chipselect),
 };
 
-static int mx27_3ds_camera_power(struct device *dev, int on)
-{
-        /* enable or disable the camera */
-        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
-        gpio_set_value(CSI_PWRDWN, on ? 0 : 1);
-
-        if (!on)
-                goto out;
-
-        /* If enabled, give a reset impulse */
-        gpio_set_value(CSI_RESET, 0);
-        msleep(20);
-        gpio_set_value(CSI_RESET, 1);
-        msleep(100);
-
-out:
-        return 0;
-}
-
-static struct i2c_board_info mx27_3ds_i2c_camera = {
-        I2C_BOARD_INFO("ov2640", 0x30),
-};
-
-static struct regulator_bulk_data mx27_3ds_camera_regs[] = {
-        { .supply = "cmos_vcore" },
-        { .supply = "cmos_2v8" },
-};
-
-static struct soc_camera_link iclink_ov2640 = {
-        .bus_id         = 0,
-        .board_info     = &mx27_3ds_i2c_camera,
-        .i2c_adapter_id = 0,
-        .power          = mx27_3ds_camera_power,
-        .regulators     = mx27_3ds_camera_regs,
-        .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs),
-};
-
-static struct platform_device mx27_3ds_ov2640 = {
-        .name   = "soc-camera-pdrv",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &iclink_ov2640,
-        },
-};
-
 static struct imx_fb_videomode mx27_3ds_modes[] = {
         {       /* 480x640 @ 60 Hz */
                 .mode = {
@@ -450,6 +348,8 @@ static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
 static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
         .reset_gpio             = LCD_RESET,
         .data_enable_gpio       = LCD_ENABLE,
+        .core_supply            = "lcd_2v8",
+        .io_supply              = "vdd_lcdio",
 };
 
 static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
@@ -459,7 +359,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
                 .bus_num        = 1,
                 .chip_select    = 0, /* SS0 */
                 .platform_data  = &mc13783_pdata,
-                /* irq number is run-time assigned */
+                .irq = gpio_to_irq(PMIC_INT),
                 .mode = SPI_CS_HIGH,
         }, {
                 .modalias       = "l4f00242t03",
@@ -470,21 +370,12 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
         },
 };
 
-static struct platform_device *devices[] __initdata = {
-        &mx27_3ds_ov2640,
-};
-
-static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = {
-        .clk = 26000000,
-};
-
 static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
         .bitrate = 100000,
 };
 
 static void __init mx27pdk_init(void)
 {
-        int ret;
         imx27_soc_init();
 
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@@ -494,7 +385,7 @@ static void __init mx27pdk_init(void)
         imx27_add_fec(NULL);
         imx27_add_imx_keypad(&mx27_3ds_keymap_data);
         imx27_add_mxc_mmc(0, &sdhc1_pdata);
-        imx27_add_imx2_wdt();
+        imx27_add_imx2_wdt(NULL);
         otg_phy_init();
 
         if (otg_mode_host) {
@@ -510,27 +401,13 @@ static void __init mx27pdk_init(void)
 
         imx27_add_spi_imx1(&spi2_pdata);
         imx27_add_spi_imx0(&spi1_pdata);
-        mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
         spi_register_board_info(mx27_3ds_spi_devs,
                                                 ARRAY_SIZE(mx27_3ds_spi_devs));
 
-        if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
+        if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
         imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
         imx27_add_imx_fb(&mx27_3ds_fb_data);
-
-        ret = gpio_request_array(mx27_3ds_camera_gpios,
-                                 ARRAY_SIZE(mx27_3ds_camera_gpios));
-        if (ret) {
-                pr_err("Failed to request camera gpios");
-                iclink_ov2640.power = NULL;
-        }
-
-        imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
-        imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
-
-        imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
 }
 
 static void __init mx27pdk_timer_init(void)
@@ -544,12 +421,10 @@ static struct sys_timer mx27pdk_timer = {
 
 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &mx27pdk_timer,
         .init_machine = mx27pdk_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 3d036f57f0e..fc26ed71b9e 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -13,7 +13,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#include <linux/gpio.h>
+
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
@@ -21,15 +21,16 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/iomux-mx27.h>
 
-#include "common.h"
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
 
 /*
  * Base address of PBC controller, CS4
@@ -246,25 +247,25 @@ static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
                               void *data)
 {
-        return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
-                           IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
+        return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
+                           "sdhc1-card-detect", data);
 }
 
 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
                               void *data)
 {
-        return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
-                           IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
+        return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
+                           "sdhc2-card-detect", data);
 }
 
 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
+        free_irq(IRQ_GPIOE(21), data);
 }
 
 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
+        free_irq(IRQ_GPIOB(7), data);
 }
 
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
@@ -310,7 +311,7 @@ static void __init mx27ads_board_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_mxc_w1();
+        imx27_add_mxc_w1(NULL);
 }
 
 static void __init mx27ads_timer_init(void)
@@ -344,12 +345,10 @@ static void __init mx27ads_map_io(void)
 
 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27ads_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &mx27ads_timer,
         .init_machine = mx27ads_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index bc301befdd0..c20be753092 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -30,19 +30,21 @@
 
 #include <media/soc_camera.h>
 
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/memblock.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/3ds_debugboard.h>
+#include <mach/ulpi.h>
 
-#include "3ds_debugboard.h"
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
+
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
 static int mx31_3ds_pins[] = {
         /* UART1 */
@@ -153,11 +155,6 @@ static int mx31_3ds_pins[] = {
         MX31_PIN_CSI_VSYNC__CSI_VSYNC,
         MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
         IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
-        /* SSI */
-        MX31_PIN_STXD4__STXD4,
-        MX31_PIN_SRXD4__SRXD4,
-        MX31_PIN_SCK4__SCK4,
-        MX31_PIN_SFS4__SFS4,
 };
 
 /*
@@ -274,6 +271,10 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "Epson-VGA",
         .mode           = fb_modedb,
@@ -284,6 +285,8 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
 static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
         .reset_gpio             = IOMUX_TO_GPIO(MX31_PIN_LCS1),
         .data_enable_gpio       = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
+        .core_supply            = "lcd_2v8",
+        .io_supply              = "vdd_lcdio",
 };
 
 /*
@@ -310,7 +313,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
                 return ret;
         }
 
-        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                           detect_irq, IRQF_DISABLED |
                           IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
                           "sdhc1-detect", data);
@@ -329,7 +332,7 @@ gpio_free:
 
 static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
         gpio_free_array(mx31_3ds_sdhc1_gpios,
                          ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
 }
@@ -393,7 +396,7 @@ static struct regulator_init_data gpo_init = {
 };
 
 static struct regulator_consumer_supply vmmc2_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"),
+        REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
 };
 
 static struct regulator_init_data vmmc2_init = {
@@ -408,7 +411,7 @@ static struct regulator_init_data vmmc2_init = {
 };
 
 static struct regulator_consumer_supply vmmc1_consumers[] = {
-        REGULATOR_SUPPLY("vcore", "spi0.0"),
+        REGULATOR_SUPPLY("lcd_2v8", NULL),
         REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
 };
 
@@ -425,7 +428,7 @@ static struct regulator_init_data vmmc1_init = {
 };
 
 static struct regulator_consumer_supply vgen_consumers[] = {
-        REGULATOR_SUPPLY("vdd", "spi0.0"),
+        REGULATOR_SUPPLY("vdd_lcdio", NULL),
 };
 
 static struct regulator_init_data vgen_init = {
@@ -486,23 +489,12 @@ static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
 };
 
 /* MC13783 */
-static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
-        .dac_ssi_port = MC13783_SSI1_PORT,
-        .adc_ssi_port = MC13783_SSI1_PORT,
-};
-
 static struct mc13xxx_platform_data mc13783_pdata = {
         .regulators = {
                 .regulators = mx31_3ds_regulators,
                 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
         },
-        .codec = &mx31_3ds_codec,
-        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
-
-};
-
-static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
-        .flags = IMX_SSI_DMA | IMX_SSI_NET,
+        .flags  = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
 };
 
 /* SPI */
@@ -532,7 +524,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
                 .bus_num        = 1,
                 .chip_select    = 1, /* SS2 */
                 .platform_data  = &mc13783_pdata,
-                /* irq number is run-time assigned */
+                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
                 .mode = SPI_CS_HIGH,
         }, {
                 .modalias       = "l4f00242t03",
@@ -550,7 +542,7 @@ static const struct mxc_nand_platform_data
 mx31_3ds_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
-#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
+#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
         .flash_bbt      = 1,
 #endif
 };
@@ -664,18 +656,18 @@ static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init mx31_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", mx31_3ds_otg_mode);
 
@@ -707,7 +699,6 @@ static void __init mx31_3ds_init(void)
         imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
         imx31_add_spi_imx1(&spi1_pdata);
-        mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
@@ -730,15 +721,15 @@ static void __init mx31_3ds_init(void)
         if (!otg_mode_host)
                 imx31_add_fsl_usb2_udc(&usbotg_pdata);
 
-        if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
+        if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 printk(KERN_WARNING "Init of the debug board failed, all "
                                     "devices on the debug board are unusable.\n");
-        imx31_add_imx2_wdt();
+        imx31_add_imx2_wdt(NULL);
         imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
         imx31_add_mxc_mmc(0, &sdhc1_pdata);
 
         imx31_add_spi_imx0(&spi0_pdata);
-        imx31_add_ipu_core();
+        imx31_add_ipu_core(&mx3_ipu_data);
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* CSI */
@@ -751,10 +742,6 @@ static void __init mx31_3ds_init(void)
         }
 
         mx31_3ds_init_camera();
-
-        imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
-
-        imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
 }
 
 static void __init mx31_3ds_timer_init(void)
@@ -769,19 +756,19 @@ static struct sys_timer mx31_3ds_timer = {
 static void __init mx31_3ds_reserve(void)
 {
         /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
-        mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
+        mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
                                          MX31_3DS_CAMERA_BUF_SIZE);
+        memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
 }
 
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &mx31_3ds_timer,
         .init_machine = mx31_3ds_init,
         .reserve = mx31_3ds_reserve,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 8b56f8883f3..29ca8907a78 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -21,13 +21,15 @@
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/board-mx31ads.h>
+#include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 #include <linux/mfd/wm8350/audio.h>
@@ -35,13 +37,7 @@
 #include <linux/mfd/wm8350/pmic.h>
 #endif
 
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
 
 /* PBC Board interrupt status register */
 #define PBC_INTSTATUS           0x000016
@@ -64,17 +60,14 @@
 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
-#define EXPIO_INT_XUART_INTA    10
-#define EXPIO_INT_XUART_INTB    11
-
-#define MXC_MAX_EXP_IO_LINES    16
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
 
-/* CS8900 */
-#define EXPIO_INT_ENET_INT      8
-#define CS4_CS8900_MMIO_START   0x20000
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
 
-static struct irq_domain *domain;
+#define MXC_MAX_EXP_IO_LINES    16
 
 /*
  * The serial port definition structure.
@@ -83,6 +76,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
+                .irq      = EXPIO_INT_XUART_INTA,
                 .uartclk  = 14745600,
                 .regshift = 0,
                 .iotype   = UPIO_MEM,
@@ -90,6 +84,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         }, {
                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
+                .irq      = EXPIO_INT_XUART_INTB,
                 .uartclk  = 14745600,
                 .regshift = 0,
                 .iotype   = UPIO_MEM,
@@ -106,37 +101,11 @@ static struct platform_device serial_device = {
         },
 };
 
-static struct resource mx31ads_cs8900_resources[] __initdata = {
-        DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
-        DEFINE_RES_IRQ(-1),
-};
-
-static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
-        .name = "cs89x0",
-        .id = 0,
-        .res = mx31ads_cs8900_resources,
-        .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
-};
-
 static int __init mxc_init_extuart(void)
 {
-        serial_platform_data[0].irq = irq_find_mapping(domain,
-                                                       EXPIO_INT_XUART_INTA);
-        serial_platform_data[1].irq = irq_find_mapping(domain,
-                                                       EXPIO_INT_XUART_INTB);
         return platform_device_register(&serial_device);
 }
 
-static void __init mxc_init_ext_ethernet(void)
-{
-        mx31ads_cs8900_resources[1].start =
-                        irq_find_mapping(domain, EXPIO_INT_ENET_INT);
-        mx31ads_cs8900_resources[1].end =
-                        irq_find_mapping(domain, EXPIO_INT_ENET_INT);
-        platform_device_register_full(
-                (struct platform_device_info *)&mx31ads_cs8900_devinfo);
-}
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -163,12 +132,12 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
         imr_val = __raw_readw(PBC_INTMASK_SET_REG);
         int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
 
-        expio_irq = 0;
+        expio_irq = MXC_EXP_IO_BASE;
         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
                 if ((int_valid & 1) == 0)
                         continue;
 
-                generic_handle_irq(irq_find_mapping(domain, expio_irq));
+                generic_handle_irq(expio_irq);
         }
 }
 
@@ -178,7 +147,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
  */
 static void expio_mask_irq(struct irq_data *d)
 {
-        u32 expio = d->hwirq;
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
         /* mask the interrupt */
         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
         __raw_readw(PBC_INTMASK_CLEAR_REG);
@@ -190,7 +159,7 @@ static void expio_mask_irq(struct irq_data *d)
  */
 static void expio_ack_irq(struct irq_data *d)
 {
-        u32 expio = d->hwirq;
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
         /* clear the interrupt status */
         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 }
@@ -201,7 +170,7 @@ static void expio_ack_irq(struct irq_data *d)
  */
 static void expio_unmask_irq(struct irq_data *d)
 {
-        u32 expio = d->hwirq;
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
         /* unmask the interrupt */
         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 }
@@ -215,8 +184,7 @@ static struct irq_chip expio_irq_chip = {
 
 static void __init mx31ads_init_expio(void)
 {
-        int irq_base;
-        int i, irq;
+        int i;
 
         printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
 
@@ -228,21 +196,13 @@ static void __init mx31ads_init_expio(void)
         /* disable the interrupt and clear the status */
         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
-
-        irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
-        WARN_ON(irq_base < 0);
-
-        domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
-                                       &irq_domain_simple_ops, NULL);
-        WARN_ON(!domain);
-
-        for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
+        for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
+             i++) {
                 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
-        irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
-        irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
+        irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
 }
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -494,6 +454,7 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
 
 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
         .init = mx31_wm8350_init,
+        .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
 };
 #endif
 
@@ -502,17 +463,13 @@ static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("wm8350", 0x1a),
                 .platform_data = &mx31_wm8350_pdata,
-                /* irq number is run-time assigned */
+                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
         },
 #endif
 };
 
 static void __init mxc_init_i2c(void)
 {
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-        mx31ads_i2c1_devices[0].irq =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
-#endif
         i2c_register_board_info(1, mx31ads_i2c1_devices,
                                 ARRAY_SIZE(mx31ads_i2c1_devices));
 
@@ -535,15 +492,12 @@ static void __init mxc_init_audio(void)
         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
 
-/*
- * Static mappings, starting from the CS4 start address up to the start address
- * of the CS8900.
- */
+/* static mappings */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
-                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
-                .length         = CS4_CS8900_MMIO_START,
+                .length         = MX31_CS4_SIZE / 2,
                 .type           = MT_DEVICE
         },
 };
@@ -568,7 +522,6 @@ static void __init mx31ads_init(void)
         mxc_init_imx_uart();
         mxc_init_i2c();
         mxc_init_audio();
-        mxc_init_ext_ethernet();
 }
 
 static void __init mx31ads_timer_init(void)
@@ -582,12 +535,10 @@ static struct sys_timer mx31ads_timer = {
 
 MACHINE_START(MX31ADS, "Freescale MX31ADS")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx31ads_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31ads_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &mx31ads_timer,
         .init_machine = mx31ads_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 08b9965c8b3..126913ad106 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -27,27 +27,25 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <linux/moduleparam.h>
 #include <linux/smsc911x.h>
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include "board-mx31lilly.h"
-#include "common.h"
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lilly.h>
+#include <mach/ulpi.h>
+
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
 
 /*
  * This file contains module-specific initialization routines for LILLY-1131.
@@ -64,7 +62,8 @@ static struct resource smsc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                /* irq number is run-time assigned */
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
         }
 };
@@ -231,7 +230,7 @@ static struct spi_board_info mc13783_dev __initdata = {
         .bus_num        = 1,
         .chip_select    = 0,
         .platform_data  = &mc13783_pdata,
-        /* irq number is run-time assigned */
+        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -242,11 +241,6 @@ static struct platform_device *devices[] __initdata = {
 static int mx31lilly_baseboard;
 core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
 
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
 static void __init mx31lilly_board_init(void)
 {
         imx31_soc_init();
@@ -283,15 +277,8 @@ static void __init mx31lilly_board_init(void)
 
         imx31_add_spi_imx0(&spi0_pdata);
         imx31_add_spi_imx1(&spi1_pdata);
-        mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(&mc13783_dev, 1);
 
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        smsc91x_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
-        smsc91x_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         /* USB */
@@ -308,12 +295,10 @@ static struct sys_timer mx31lilly_timer = {
 };
 
 MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &mx31lilly_timer,
         .init_machine = mx31lilly_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index bdcd92e5951..4b47fd9fdd8 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -21,7 +21,6 @@
 #include <linux/memory.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/moduleparam.h>
 #include <linux/smsc911x.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -29,8 +28,6 @@
 #include <linux/usb/ulpi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/delay.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,12 +36,14 @@
 #include <asm/page.h>
 #include <asm/setup.h>
 
-#include "board-mx31lite.h"
-#include "common.h"
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/board-mx31lite.h>
+#include <mach/iomux-mx3.h>
+#include <mach/irqs.h>
+#include <mach/ulpi.h>
+
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
 
 /*
  * This file contains the module-specific initialization routines.
@@ -81,7 +80,8 @@ static struct resource smsc911x_resources[] = {
                 .end            = MX31_CS4_BASE_ADDR + 0x100,
                 .flags          = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start          = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+                .end            = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -112,7 +112,8 @@ static const struct spi_imx_master spi1_pdata __initconst = {
 };
 
 static struct mc13xxx_platform_data mc13783_pdata __initdata = {
-        .flags = MC13XXX_USE_RTC,
+        .flags  = MC13XXX_USE_RTC |
+                  MC13XXX_USE_REGULATOR,
 };
 
 static struct spi_board_info mc13783_spi_dev __initdata = {
@@ -121,7 +122,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
         .bus_num        = 1,
         .chip_select    = 0,
         .platform_data  = &mc13783_pdata,
-        /* irq number is run-time assigned */
+        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 };
 
 /*
@@ -206,7 +207,7 @@ static struct platform_device physmap_flash_device = {
  */
 static struct map_desc mx31lite_io_desc[] __initdata = {
         {
-                .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
+                .virtual = MX31_CS4_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length = MX31_CS4_SIZE,
                 .type = MT_DEVICE
@@ -225,11 +226,6 @@ void __init mx31lite_map_io(void)
 static int mx31lite_baseboard;
 core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
 
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
 static void __init mx31lite_init(void)
 {
         int ret;
@@ -255,7 +251,6 @@ static void __init mx31lite_init(void)
         imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
         imx31_add_spi_imx1(&spi1_pdata);
-        mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(&mc13783_spi_dev, 1);
 
         /* USB */
@@ -264,18 +259,12 @@ static void __init mx31lite_init(void)
         if (usbh2_pdata.otg)
                 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
         /* SMSC9117 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
         if (ret)
                 pr_warning("could not get LAN irq gpio\n");
         else {
                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
-                smsc911x_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
-                smsc911x_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
                 platform_device_register(&smsc911x_device);
         }
 }
@@ -285,18 +274,16 @@ static void __init mx31lite_timer_init(void)
         mx31_clocks_init(26000000);
 }
 
-static struct sys_timer mx31lite_timer = {
+struct sys_timer mx31lite_timer = {
         .init   = mx31lite_timer_init,
 };
 
 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx31lite_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &mx31lite_timer,
         .init_machine = mx31lite_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 2517cfa9f26..b358383120e 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -18,7 +18,6 @@
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/moduleparam.h>
 #include <linux/leds.h>
 #include <linux/memory.h>
 #include <linux/mtd/physmap.h>
@@ -29,10 +28,6 @@
 #include <linux/spi/spi.h>
 #include <linux/types.h>
 #include <linux/memblock.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/input.h>
 
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -41,15 +36,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <asm/memblock.h>
-#include <linux/platform_data/asoc-imx-ssi.h>
+#include <mach/board-mx31moboard.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
 
-#include "board-mx31moboard.h"
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
 
 static unsigned int moboard_pins[] = {
         /* UART0 */
@@ -103,9 +96,6 @@ static unsigned int moboard_pins[] = {
         MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
         MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
         MX31_PIN_CSPI2_SS1__CSPI3_SS1,
-        /* SSI */
-        MX31_PIN_STXD4__STXD4, MX31_PIN_SRXD4__SRXD4,
-        MX31_PIN_SCK4__SCK4, MX31_PIN_SFS4__SFS4,
 };
 
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -175,11 +165,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = {
 
 static struct regulator_consumer_supply sdhc_consumers[] = {
         {
-                .dev_name = "imx31-mmc.0",
+                .dev_name = "mxc-mmc.0",
                 .supply = "sdhc0_vcc",
         },
         {
-                .dev_name = "imx31-mmc.1",
+                .dev_name = "mxc-mmc.1",
                 .supply = "sdhc1_vcc",
         },
 };
@@ -232,7 +222,7 @@ static struct mc13xxx_regulator_init_data moboard_regulators[] = {
         },
 };
 
-static struct mc13xxx_led_platform_data moboard_led[] = {
+static struct mc13783_led_platform_data moboard_led[] = {
         {
                 .id = MC13783_LED_R1,
                 .name = "coreboard-led-4:red",
@@ -265,7 +255,7 @@ static struct mc13xxx_led_platform_data moboard_led[] = {
         },
 };
 
-static struct mc13xxx_leds_platform_data moboard_leds = {
+static struct mc13783_leds_platform_data moboard_leds = {
         .num_leds = ARRAY_SIZE(moboard_led),
         .led = moboard_led,
         .flags = MC13783_LED_SLEWLIMTC,
@@ -274,36 +264,20 @@ static struct mc13xxx_leds_platform_data moboard_leds = {
         .tc2_period = MC13783_LED_PERIOD_10MS,
 };
 
-static struct mc13xxx_buttons_platform_data moboard_buttons = {
-        .b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE |
-                        MC13783_BUTTON_POL_INVERT,
-        .b1on_key = KEY_POWER,
-};
-
-static struct mc13xxx_codec_platform_data moboard_codec = {
-        .dac_ssi_port = MC13783_SSI1_PORT,
-        .adc_ssi_port = MC13783_SSI1_PORT,
-};
-
 static struct mc13xxx_platform_data moboard_pmic = {
         .regulators = {
                 .regulators = moboard_regulators,
                 .num_regulators = ARRAY_SIZE(moboard_regulators),
         },
         .leds = &moboard_leds,
-        .buttons = &moboard_buttons,
-        .codec = &moboard_codec,
-        .flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC | MC13XXX_USE_CODEC,
-};
-
-static struct imx_ssi_platform_data moboard_ssi_pdata = {
-        .flags = IMX_SSI_DMA | IMX_SSI_NET,
+        .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
+                MC13XXX_USE_ADC | MC13XXX_USE_LED,
 };
 
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
         {
                 .modalias = "mc13783",
-                /* irq number is run-time assigned */
+                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
                 .max_speed_hz = 300000,
                 .bus_num = 1,
                 .chip_select = 0,
@@ -473,6 +447,10 @@ static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
         .leds           = mx31moboard_leds,
 };
 
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static struct platform_device *devices[] __initdata = {
         &mx31moboard_flash,
 };
@@ -490,7 +468,7 @@ static int __init mx31moboard_init_cam(void)
         int dma, ret = -ENOMEM;
         struct platform_device *pdev;
 
-        imx31_add_ipu_core();
+        imx31_add_ipu_core(&mx3_ipu_data);
 
         pdev = imx31_alloc_mx3_camera(&camera_pdata);
         if (IS_ERR(pdev))
@@ -512,18 +490,6 @@ err:
 
 }
 
-static void mx31moboard_poweroff(void)
-{
-        struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
-
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-
-        mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
-
-        __raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-}
-
 static int mx31moboard_baseboard;
 core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
 
@@ -540,8 +506,6 @@ static void __init mx31moboard_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
         gpio_led_register_device(-1, &mx31moboard_led_pdata);
 
-        imx31_add_imx2_wdt();
-
         imx31_add_imx_uart0(&uart0_pdata);
         imx31_add_imx_uart4(&uart4_pdata);
 
@@ -553,8 +517,6 @@ static void __init mx31moboard_init(void)
 
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
-        moboard_spi_board_info[0].irq =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(moboard_spi_board_info,
                 ARRAY_SIZE(moboard_spi_board_info));
 
@@ -566,12 +528,6 @@ static void __init mx31moboard_init(void)
 
         moboard_usbh2_init();
 
-        imx31_add_imx_ssi(0, &moboard_ssi_pdata);
-
-        imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
-
-        pm_power_off = mx31moboard_poweroff;
-
         switch (mx31moboard_baseboard) {
         case MX31NOBOARD:
                 break;
@@ -596,26 +552,26 @@ static void __init mx31moboard_timer_init(void)
         mx31_clocks_init(26000000);
 }
 
-static struct sys_timer mx31moboard_timer = {
+struct sys_timer mx31moboard_timer = {
         .init   = mx31moboard_timer_init,
 };
 
 static void __init mx31moboard_reserve(void)
 {
         /* reserve 4 MiB for mx3-camera */
-        mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
+        mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
                         MX3_CAMERA_BUF_SIZE);
+        memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
 }
 
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
-        /* Maintainer: Philippe Retornaz, EPFL Mobots group */
-        .atag_offset = 0x100,
+        /* Maintainer: Valentin Longchamp, EPFL Mobots group */
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .reserve = mx31moboard_reserve,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &mx31moboard_timer,
         .init_machine = mx31moboard_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 5277da45d60..b3b9bd8ac2a 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -4,11 +4,6 @@
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
- * Copyright (C) 2011 Meprolight, Ltd.
- * Alex Gershgorin <alexg@meprolight.com>
- *
- * Modified from i.MX31 3-Stack Development System
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -34,102 +29,21 @@
 #include <linux/usb/otg.h>
 
 #include <linux/mtd/physmap.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <asm/memblock.h>
 
-#include <video/platform_lcd.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+#include <mach/3ds_debugboard.h>
 
-#include <media/soc_camera.h>
-
-#include "3ds_debugboard.h"
-#include "common.h"
 #include "devices-imx35.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
-
-#define GPIO_MC9S08DZ60_GPS_ENABLE 0
-#define GPIO_MC9S08DZ60_HDD_ENABLE 4
-#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
-#define GPIO_MC9S08DZ60_LCD_ENABLE 6
-#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
-
-static const struct fb_videomode fb_modedb[] = {
-        {
-                 /* 800x480 @ 55 Hz */
-                .name = "Ceramate-CLAA070VC01",
-                .refresh = 55,
-                .xres = 800,
-                .yres = 480,
-                .pixclock = 40000,
-                .left_margin = 40,
-                .right_margin = 40,
-                .upper_margin = 5,
-                .lower_margin = 5,
-                .hsync_len = 20,
-                .vsync_len = 10,
-                .sync = FB_SYNC_OE_ACT_HIGH,
-                .vmode = FB_VMODE_NONINTERLACED,
-                .flag = 0,
-         },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata __initdata = {
-        .name = "Ceramate-CLAA070VC01",
-        .mode = fb_modedb,
-        .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct i2c_board_info __initdata i2c_devices_3ds[] = {
-        {
-                I2C_BOARD_INFO("mc9s08dz60", 0x69),
-        },
-};
-
-static int lcd_power_gpio = -ENXIO;
-
-static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, void *data)
-{
-        return !strcmp(chip->label, data);
-}
 
-static void mx35_3ds_lcd_set_power(
-                                struct plat_lcd_data *pd, unsigned int power)
-{
-        struct gpio_chip *chip;
-
-        if (!gpio_is_valid(lcd_power_gpio)) {
-                chip = gpiochip_find(
-                                "mc9s08dz60", mc9s08dz60_gpiochip_match);
-                if (chip) {
-                        lcd_power_gpio =
-                                chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
-                        if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
-                                pr_err("error: gpio already requested!\n");
-                                lcd_power_gpio = -ENXIO;
-                        }
-                } else {
-                        pr_err("error: didn't find mc9s08dz60 gpio chip\n");
-                }
-        }
-
-        if (gpio_is_valid(lcd_power_gpio))
-                gpio_set_value_cansleep(lcd_power_gpio, power);
-}
-
-static struct plat_lcd_data mx35_3ds_lcd_data = {
-        .set_power = mx35_3ds_lcd_set_power,
-};
-
-static struct platform_device mx35_3ds_lcd = {
-        .name = "platform-lcd",
-        .dev.platform_data = &mx35_3ds_lcd_data,
-};
+#define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
@@ -206,297 +120,8 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
         /* I2C1 */
         MX35_PAD_I2C1_CLK__I2C1_SCL,
         MX35_PAD_I2C1_DAT__I2C1_SDA,
-        /* Display */
-        MX35_PAD_LD0__IPU_DISPB_DAT_0,
-        MX35_PAD_LD1__IPU_DISPB_DAT_1,
-        MX35_PAD_LD2__IPU_DISPB_DAT_2,
-        MX35_PAD_LD3__IPU_DISPB_DAT_3,
-        MX35_PAD_LD4__IPU_DISPB_DAT_4,
-        MX35_PAD_LD5__IPU_DISPB_DAT_5,
-        MX35_PAD_LD6__IPU_DISPB_DAT_6,
-        MX35_PAD_LD7__IPU_DISPB_DAT_7,
-        MX35_PAD_LD8__IPU_DISPB_DAT_8,
-        MX35_PAD_LD9__IPU_DISPB_DAT_9,
-        MX35_PAD_LD10__IPU_DISPB_DAT_10,
-        MX35_PAD_LD11__IPU_DISPB_DAT_11,
-        MX35_PAD_LD12__IPU_DISPB_DAT_12,
-        MX35_PAD_LD13__IPU_DISPB_DAT_13,
-        MX35_PAD_LD14__IPU_DISPB_DAT_14,
-        MX35_PAD_LD15__IPU_DISPB_DAT_15,
-        MX35_PAD_LD16__IPU_DISPB_DAT_16,
-        MX35_PAD_LD17__IPU_DISPB_DAT_17,
-        MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
-        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
-        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
-        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
-        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
-        MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
-        MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
-        /* CSI */
-        MX35_PAD_TX1__IPU_CSI_D_6,
-        MX35_PAD_TX0__IPU_CSI_D_7,
-        MX35_PAD_CSI_D8__IPU_CSI_D_8,
-        MX35_PAD_CSI_D9__IPU_CSI_D_9,
-        MX35_PAD_CSI_D10__IPU_CSI_D_10,
-        MX35_PAD_CSI_D11__IPU_CSI_D_11,
-        MX35_PAD_CSI_D12__IPU_CSI_D_12,
-        MX35_PAD_CSI_D13__IPU_CSI_D_13,
-        MX35_PAD_CSI_D14__IPU_CSI_D_14,
-        MX35_PAD_CSI_D15__IPU_CSI_D_15,
-        MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
-        MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
-        MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
-        MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
-        /*PMIC IRQ*/
-        MX35_PAD_GPIO2_0__GPIO2_0,
-};
-
-/*
- * Camera support
-*/
-static phys_addr_t mx3_camera_base __initdata;
-#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
-
-static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
-        .flags = MX3_CAMERA_DATAWIDTH_8,
-        .mclk_10khz = 2000,
-};
-
-static int __init imx35_3ds_init_camera(void)
-{
-        int dma, ret = -ENOMEM;
-        struct platform_device *pdev =
-                imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
-
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
-
-        if (!mx3_camera_base)
-                goto err;
-
-        dma = dma_declare_coherent_memory(&pdev->dev,
-                                        mx3_camera_base, mx3_camera_base,
-                                        MX35_3DS_CAMERA_BUF_SIZE,
-                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-
-        if (!(dma & DMA_MEMORY_MAP))
-                goto err;
-
-        ret = platform_device_add(pdev);
-        if (ret)
-err:
-                platform_device_put(pdev);
-
-        return ret;
-}
-
-static struct i2c_board_info mx35_3ds_i2c_camera = {
-        I2C_BOARD_INFO("ov2640", 0x30),
-};
-
-static struct soc_camera_link iclink_ov2640 = {
-        .bus_id         = 0,
-        .board_info     = &mx35_3ds_i2c_camera,
-        .i2c_adapter_id = 0,
-        .power          = NULL,
-};
-
-static struct platform_device mx35_3ds_ov2640 = {
-        .name   = "soc-camera-pdrv",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &iclink_ov2640,
-        },
-};
-
-static struct regulator_consumer_supply sw1_consumers[] = {
-        {
-                .supply = "cpu_vcc",
-        }
-};
-
-static struct regulator_consumer_supply vcam_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-};
-
-static struct regulator_consumer_supply vaudio_consumers[] = {
-        REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"),
-};
-
-static struct regulator_init_data sw1_init = {
-        .constraints = {
-                .name = "SW1",
-                .min_uV = 600000,
-                .max_uV = 1375000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .valid_modes_mask = 0,
-                .always_on = 1,
-                .boot_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
-        .consumer_supplies = sw1_consumers,
-};
-
-static struct regulator_init_data sw2_init = {
-        .constraints = {
-                .name = "SW2",
-                .always_on = 1,
-                .boot_on = 1,
-        }
 };
 
-static struct regulator_init_data sw3_init = {
-        .constraints = {
-                .name = "SW3",
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data sw4_init = {
-        .constraints = {
-                .name = "SW4",
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data viohi_init = {
-        .constraints = {
-                .name = "VIOHI",
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vusb_init = {
-        .constraints = {
-                .name = "VUSB",
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vdig_init = {
-        .constraints = {
-                .name = "VDIG",
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vpll_init = {
-        .constraints = {
-                .name = "VPLL",
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vusb2_init = {
-        .constraints = {
-                .name = "VUSB2",
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vvideo_init = {
-        .constraints = {
-                .name = "VVIDEO",
-                .boot_on = 1
-        }
-};
-
-static struct regulator_init_data vaudio_init = {
-        .constraints = {
-                .name = "VAUDIO",
-                .min_uV = 2300000,
-                .max_uV = 3000000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vaudio_consumers),
-        .consumer_supplies = vaudio_consumers,
-};
-
-static struct regulator_init_data vcam_init = {
-        .constraints = {
-                .name = "VCAM",
-                .min_uV = 2500000,
-                .max_uV = 3000000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                        REGULATOR_CHANGE_MODE,
-                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-                .boot_on = 1
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vcam_consumers),
-        .consumer_supplies = vcam_consumers,
-};
-
-static struct regulator_init_data vgen1_init = {
-        .constraints = {
-                .name = "VGEN1",
-        }
-};
-
-static struct regulator_init_data vgen2_init = {
-        .constraints = {
-                .name = "VGEN2",
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen3_init = {
-        .constraints = {
-                .name = "VGEN3",
-        }
-};
-
-static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
-        { .id = MC13892_SW1, .init_data = &sw1_init },
-        { .id = MC13892_SW2, .init_data = &sw2_init },
-        { .id = MC13892_SW3, .init_data = &sw3_init },
-        { .id = MC13892_SW4, .init_data = &sw4_init },
-        { .id = MC13892_VIOHI, .init_data = &viohi_init },
-        { .id = MC13892_VPLL, .init_data = &vpll_init },
-        { .id = MC13892_VDIG, .init_data = &vdig_init },
-        { .id = MC13892_VUSB2, .init_data = &vusb2_init },
-        { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
-        { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
-        { .id = MC13892_VCAM, .init_data = &vcam_init },
-        { .id = MC13892_VGEN1, .init_data = &vgen1_init },
-        { .id = MC13892_VGEN2, .init_data = &vgen2_init },
-        { .id = MC13892_VGEN3, .init_data = &vgen3_init },
-        { .id = MC13892_VUSB, .init_data = &vusb_init },
-};
-
-static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
-        .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
-        .regulators = {
-                .num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
-                .regulators = mx35_3ds_regulators,
-        },
-};
-
-#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
-
-static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
-
-        I2C_BOARD_INFO("mc13892", 0x08),
-        .platform_data = &mx35_3ds_mc13892_data,
-        /* irq number is run-time assigned */
-};
-
-static void __init imx35_3ds_init_mc13892(void)
-{
-        int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
-
-        if (ret) {
-                pr_err("failed to get pmic irq: %d\n", ret);
-                return;
-        }
-
-        mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT);
-        i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
-}
-
 static int mx35_3ds_otg_init(struct platform_device *pdev)
 {
         return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
@@ -530,18 +155,18 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
         .portsc         = MXC_EHCI_MODE_SERIAL,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init mx35_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", mx35_3ds_otg_mode);
 
@@ -554,15 +179,12 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
-        struct platform_device *imx35_fb_pdev;
-
         imx35_soc_init();
 
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt();
-        imx35_add_mxc_rtc();
+        imx35_add_imx2_wdt(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
@@ -578,23 +200,10 @@ static void __init mx35_3ds_init(void)
         imx35_add_mxc_nand(&mx35pdk_nand_board_info);
         imx35_add_sdhci_esdhc_imx(0, NULL);
 
-        if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1)))
+        if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all "
                                 "devices on the debugboard are unusable.\n");
         imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
-
-        i2c_register_board_info(
-                0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
-
-        imx35_add_ipu_core();
-        platform_device_register(&mx35_3ds_ov2640);
-        imx35_3ds_init_camera();
-
-        imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
-        mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
-        platform_device_register(&mx35_3ds_lcd);
-
-        imx35_3ds_init_mc13892();
 }
 
 static void __init mx35pdk_timer_init(void)
@@ -602,26 +211,16 @@ static void __init mx35pdk_timer_init(void)
         mx35_clocks_init();
 }
 
-static struct sys_timer mx35pdk_timer = {
+struct sys_timer mx35pdk_timer = {
         .init   = mx35pdk_timer_init,
 };
 
-static void __init mx35_3ds_reserve(void)
-{
-        /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
-        mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
-                                         MX35_3DS_CAMERA_BUF_SIZE);
-}
-
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         /* Maintainer: Freescale Semiconductor, Inc */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
         .timer = &mx35pdk_timer,
         .init_machine = mx35_3ds_init,
-        .reserve = mx35_3ds_reserve,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
deleted file mode 100644
index 0c1f88a80bd..00000000000
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx50.h"
-#include "hardware.h"
-#include "iomux-mx50.h"
-
-#define FEC_EN          IMX_GPIO_NR(6, 23)
-#define FEC_RESET_B     IMX_GPIO_NR(4, 12)
-
-static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
-        /* SD1 */
-        MX50_PAD_ECSPI2_SS0__GPIO_4_19,
-        MX50_PAD_EIM_CRE__GPIO_1_27,
-        MX50_PAD_SD1_CMD__SD1_CMD,
-
-        MX50_PAD_SD1_CLK__SD1_CLK,
-        MX50_PAD_SD1_D0__SD1_D0,
-        MX50_PAD_SD1_D1__SD1_D1,
-        MX50_PAD_SD1_D2__SD1_D2,
-        MX50_PAD_SD1_D3__SD1_D3,
-
-        /* SD2 */
-        MX50_PAD_SD2_CD__GPIO_5_17,
-        MX50_PAD_SD2_WP__GPIO_5_16,
-        MX50_PAD_SD2_CMD__SD2_CMD,
-        MX50_PAD_SD2_CLK__SD2_CLK,
-        MX50_PAD_SD2_D0__SD2_D0,
-        MX50_PAD_SD2_D1__SD2_D1,
-        MX50_PAD_SD2_D2__SD2_D2,
-        MX50_PAD_SD2_D3__SD2_D3,
-        MX50_PAD_SD2_D4__SD2_D4,
-        MX50_PAD_SD2_D5__SD2_D5,
-        MX50_PAD_SD2_D6__SD2_D6,
-        MX50_PAD_SD2_D7__SD2_D7,
-
-        /* SD3 */
-        MX50_PAD_SD3_CMD__SD3_CMD,
-        MX50_PAD_SD3_CLK__SD3_CLK,
-        MX50_PAD_SD3_D0__SD3_D0,
-        MX50_PAD_SD3_D1__SD3_D1,
-        MX50_PAD_SD3_D2__SD3_D2,
-        MX50_PAD_SD3_D3__SD3_D3,
-        MX50_PAD_SD3_D4__SD3_D4,
-        MX50_PAD_SD3_D5__SD3_D5,
-        MX50_PAD_SD3_D6__SD3_D6,
-        MX50_PAD_SD3_D7__SD3_D7,
-
-        /* PWR_INT */
-        MX50_PAD_ECSPI2_MISO__GPIO_4_18,
-
-        /* UART pad setting */
-        MX50_PAD_UART1_TXD__UART1_TXD,
-        MX50_PAD_UART1_RXD__UART1_RXD,
-        MX50_PAD_UART1_RTS__UART1_RTS,
-        MX50_PAD_UART2_TXD__UART2_TXD,
-        MX50_PAD_UART2_RXD__UART2_RXD,
-        MX50_PAD_UART2_CTS__UART2_CTS,
-        MX50_PAD_UART2_RTS__UART2_RTS,
-
-        MX50_PAD_I2C1_SCL__I2C1_SCL,
-        MX50_PAD_I2C1_SDA__I2C1_SDA,
-        MX50_PAD_I2C2_SCL__I2C2_SCL,
-        MX50_PAD_I2C2_SDA__I2C2_SDA,
-
-        MX50_PAD_EPITO__USBH1_PWR,
-        /* Need to comment below line if
-         * one needs to debug owire.
-         */
-        MX50_PAD_OWIRE__USBH1_OC,
-        /* using gpio to control otg pwr */
-        MX50_PAD_PWM2__GPIO_6_25,
-        MX50_PAD_I2C3_SCL__USBOTG_OC,
-
-        MX50_PAD_SSI_RXC__FEC_MDIO,
-        MX50_PAD_SSI_RXFS__FEC_MDC,
-        MX50_PAD_DISP_D0__FEC_TXCLK,
-        MX50_PAD_DISP_D1__FEC_RX_ER,
-        MX50_PAD_DISP_D2__FEC_RX_DV,
-        MX50_PAD_DISP_D3__FEC_RXD1,
-        MX50_PAD_DISP_D4__FEC_RXD0,
-        MX50_PAD_DISP_D5__FEC_TX_EN,
-        MX50_PAD_DISP_D6__FEC_TXD1,
-        MX50_PAD_DISP_D7__FEC_TXD0,
-        MX50_PAD_I2C3_SDA__GPIO_6_23,
-        MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
-
-        MX50_PAD_CSPI_SS0__CSPI_SS0,
-        MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
-        MX50_PAD_CSPI_MOSI__CSPI_MOSI,
-        MX50_PAD_CSPI_MISO__CSPI_MISO,
-
-        /* SGTL500_OSC_EN */
-        MX50_PAD_UART1_CTS__GPIO_6_8,
-
-        /* SGTL_AMP_SHDN */
-        MX50_PAD_UART3_RXD__GPIO_6_15,
-
-        /* Keypad */
-        MX50_PAD_KEY_COL0__KEY_COL0,
-        MX50_PAD_KEY_ROW0__KEY_ROW0,
-        MX50_PAD_KEY_COL1__KEY_COL1,
-        MX50_PAD_KEY_ROW1__KEY_ROW1,
-        MX50_PAD_KEY_COL2__KEY_COL2,
-        MX50_PAD_KEY_ROW2__KEY_ROW2,
-        MX50_PAD_KEY_COL3__KEY_COL3,
-        MX50_PAD_KEY_ROW3__KEY_ROW3,
-        MX50_PAD_EIM_DA0__KEY_COL4,
-        MX50_PAD_EIM_DA1__KEY_ROW4,
-        MX50_PAD_EIM_DA2__KEY_COL5,
-        MX50_PAD_EIM_DA3__KEY_ROW5,
-        MX50_PAD_EIM_DA4__KEY_COL6,
-        MX50_PAD_EIM_DA5__KEY_ROW6,
-        MX50_PAD_EIM_DA6__KEY_COL7,
-        MX50_PAD_EIM_DA7__KEY_ROW7,
-        /*EIM pads */
-        MX50_PAD_EIM_DA8__GPIO_1_8,
-        MX50_PAD_EIM_DA9__GPIO_1_9,
-        MX50_PAD_EIM_DA10__GPIO_1_10,
-        MX50_PAD_EIM_DA11__GPIO_1_11,
-        MX50_PAD_EIM_DA12__GPIO_1_12,
-        MX50_PAD_EIM_DA13__GPIO_1_13,
-        MX50_PAD_EIM_DA14__GPIO_1_14,
-        MX50_PAD_EIM_DA15__GPIO_1_15,
-        MX50_PAD_EIM_CS2__GPIO_1_16,
-        MX50_PAD_EIM_CS1__GPIO_1_17,
-        MX50_PAD_EIM_CS0__GPIO_1_18,
-        MX50_PAD_EIM_EB0__GPIO_1_19,
-        MX50_PAD_EIM_EB1__GPIO_1_20,
-        MX50_PAD_EIM_WAIT__GPIO_1_21,
-        MX50_PAD_EIM_BCLK__GPIO_1_22,
-        MX50_PAD_EIM_RDY__GPIO_1_23,
-        MX50_PAD_EIM_OE__GPIO_1_24,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct fec_platform_data fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static inline void mx50_rdp_fec_reset(void)
-{
-        gpio_request(FEC_EN, "fec-en");
-        gpio_direction_output(FEC_EN, 0);
-        gpio_request(FEC_RESET_B, "fec-reset_b");
-        gpio_direction_output(FEC_RESET_B, 0);
-        msleep(1);
-        gpio_set_value(FEC_RESET_B, 1);
-}
-
-static const struct imxi2c_platform_data i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mx50_rdp_board_init(void)
-{
-        imx50_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
-                                        ARRAY_SIZE(mx50_rdp_pads));
-
-        imx50_add_imx_uart(0, &uart_pdata);
-        imx50_add_imx_uart(1, &uart_pdata);
-        mx50_rdp_fec_reset();
-        imx50_add_fec(&fec_data);
-        imx50_add_imx_i2c(0, &i2c_data);
-        imx50_add_imx_i2c(1, &i2c_data);
-        imx50_add_imx_i2c(2, &i2c_data);
-}
-
-static void __init mx50_rdp_timer_init(void)
-{
-        mx50_clocks_init(32768, 24000000, 22579200);
-}
-
-static struct sys_timer mx50_rdp_timer = {
-        .init   = mx50_rdp_timer_init,
-};
-
-MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
-        .map_io = mx50_map_io,
-        .init_early = imx50_init_early,
-        .init_irq = mx50_init_irq,
-        .handle_irq = imx50_handle_irq,
-        .timer = &mx50_rdp_timer,
-        .init_machine = mx50_rdp_board_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
deleted file mode 100644
index abc25bd1107..00000000000
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "3ds_debugboard.h"
-#include "common.h"
-#include "devices-imx51.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-
-#define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
-
-static iomux_v3_cfg_t mx51_3ds_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-        MX51_PAD_EIM_D25__UART2_CTS,
-        MX51_PAD_EIM_D26__UART2_RTS,
-
-        /* UART3 */
-        MX51_PAD_UART3_RXD__UART3_RXD,
-        MX51_PAD_UART3_TXD__UART3_TXD,
-        MX51_PAD_EIM_D24__UART3_CTS,
-        MX51_PAD_EIM_D27__UART3_RTS,
-
-        /* CPLD PARENT IRQ PIN */
-        MX51_PAD_GPIO1_6__GPIO1_6,
-
-        /* KPP */
-        MX51_PAD_KEY_ROW0__KEY_ROW0,
-        MX51_PAD_KEY_ROW1__KEY_ROW1,
-        MX51_PAD_KEY_ROW2__KEY_ROW2,
-        MX51_PAD_KEY_ROW3__KEY_ROW3,
-        MX51_PAD_KEY_COL0__KEY_COL0,
-        MX51_PAD_KEY_COL1__KEY_COL1,
-        MX51_PAD_KEY_COL2__KEY_COL2,
-        MX51_PAD_KEY_COL3__KEY_COL3,
-        MX51_PAD_KEY_COL4__KEY_COL4,
-        MX51_PAD_KEY_COL5__KEY_COL5,
-
-        /* eCSPI2 */
-        MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
-        MX51_PAD_NANDF_RB3__ECSPI2_MISO,
-        MX51_PAD_NANDF_D15__ECSPI2_MOSI,
-        MX51_PAD_NANDF_D12__GPIO3_28,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static int mx51_3ds_board_keymap[] = {
-        KEY(0, 0, KEY_1),
-        KEY(0, 1, KEY_2),
-        KEY(0, 2, KEY_3),
-        KEY(0, 3, KEY_F1),
-        KEY(0, 4, KEY_UP),
-        KEY(0, 5, KEY_F2),
-
-        KEY(1, 0, KEY_4),
-        KEY(1, 1, KEY_5),
-        KEY(1, 2, KEY_6),
-        KEY(1, 3, KEY_LEFT),
-        KEY(1, 4, KEY_SELECT),
-        KEY(1, 5, KEY_RIGHT),
-
-        KEY(2, 0, KEY_7),
-        KEY(2, 1, KEY_8),
-        KEY(2, 2, KEY_9),
-        KEY(2, 3, KEY_F3),
-        KEY(2, 4, KEY_DOWN),
-        KEY(2, 5, KEY_F4),
-
-        KEY(3, 0, KEY_0),
-        KEY(3, 1, KEY_OK),
-        KEY(3, 2, KEY_ESC),
-        KEY(3, 3, KEY_ENTER),
-        KEY(3, 4, KEY_MENU),
-        KEY(3, 5, KEY_BACK)
-};
-
-static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
-        .keymap         = mx51_3ds_board_keymap,
-        .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
-};
-
-static int mx51_3ds_spi2_cs[] = {
-        MXC_SPI_CS(0),
-        MX51_3DS_ECSPI2_CS,
-};
-
-static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
-        .chipselect     = mx51_3ds_spi2_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
-};
-
-static struct spi_board_info mx51_3ds_spi_nor_device[] = {
-        {
-         .modalias = "m25p80",
-         .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
-         .bus_num = 1,
-         .chip_select = 1,
-         .mode = SPI_MODE_0,
-         .platform_data = NULL,},
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mx51_3ds_init(void)
-{
-        imx51_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
-                                        ARRAY_SIZE(mx51_3ds_pads));
-
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-
-        imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
-        spi_register_board_info(mx51_3ds_spi_nor_device,
-                                ARRAY_SIZE(mx51_3ds_spi_nor_device));
-
-        if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
-                printk(KERN_WARNING "Init of the debugboard failed, all "
-                                    "devices on the board are unusable.\n");
-
-        imx51_add_sdhci_esdhc_imx(0, NULL);
-        imx51_add_imx_keypad(&mx51_3ds_map_data);
-        imx51_add_imx2_wdt(0);
-}
-
-static void __init mx51_3ds_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx51_3ds_timer = {
-        .init = mx51_3ds_timer_init,
-};
-
-MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_3ds_timer,
-        .init_machine = mx51_3ds_init,
-        .init_late      = imx51_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
deleted file mode 100644
index d9a84ca2199..00000000000
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx51.h"
-#include "cpu_op-mx51.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-
-#define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
-#define BABBAGE_USBH1_STP       IMX_GPIO_NR(1, 27)
-#define BABBAGE_USB_PHY_RESET   IMX_GPIO_NR(2, 5)
-#define BABBAGE_FEC_PHY_RESET   IMX_GPIO_NR(2, 14)
-#define BABBAGE_POWER_KEY       IMX_GPIO_NR(2, 21)
-#define BABBAGE_ECSPI1_CS0      IMX_GPIO_NR(4, 24)
-#define BABBAGE_ECSPI1_CS1      IMX_GPIO_NR(4, 25)
-#define BABBAGE_SD2_CD          IMX_GPIO_NR(1, 6)
-#define BABBAGE_SD2_WP          IMX_GPIO_NR(1, 5)
-
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET                  0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
-
-#define MX51_USB_PLLDIV_12_MHZ          0x00
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define MX51_USB_PLL_DIV_24_MHZ 0x02
-
-static struct gpio_keys_button babbage_buttons[] = {
-        {
-                .gpio           = BABBAGE_POWER_KEY,
-                .code           = BTN_0,
-                .desc           = "PWR",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-
-static const struct gpio_keys_platform_data imx_button_data __initconst = {
-        .buttons        = babbage_buttons,
-        .nbuttons       = ARRAY_SIZE(babbage_buttons),
-};
-
-static iomux_v3_cfg_t mx51babbage_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-
-        /* UART3 */
-        MX51_PAD_EIM_D25__UART3_RXD,
-        MX51_PAD_EIM_D26__UART3_TXD,
-        MX51_PAD_EIM_D27__UART3_RTS,
-        MX51_PAD_EIM_D24__UART3_CTS,
-
-        /* I2C1 */
-        MX51_PAD_EIM_D16__I2C1_SDA,
-        MX51_PAD_EIM_D19__I2C1_SCL,
-
-        /* I2C2 */
-        MX51_PAD_KEY_COL4__I2C2_SCL,
-        MX51_PAD_KEY_COL5__I2C2_SDA,
-
-        /* HSI2C */
-        MX51_PAD_I2C1_CLK__I2C1_CLK,
-        MX51_PAD_I2C1_DAT__I2C1_DAT,
-
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-        /* USB HUB reset line*/
-        MX51_PAD_GPIO1_7__GPIO1_7,
-
-        /* USB PHY reset line */
-        MX51_PAD_EIM_D21__GPIO2_5,
-
-        /* FEC */
-        MX51_PAD_EIM_EB2__FEC_MDIO,
-        MX51_PAD_EIM_EB3__FEC_RDATA1,
-        MX51_PAD_EIM_CS2__FEC_RDATA2,
-        MX51_PAD_EIM_CS3__FEC_RDATA3,
-        MX51_PAD_EIM_CS4__FEC_RX_ER,
-        MX51_PAD_EIM_CS5__FEC_CRS,
-        MX51_PAD_NANDF_RB2__FEC_COL,
-        MX51_PAD_NANDF_RB3__FEC_RX_CLK,
-        MX51_PAD_NANDF_D9__FEC_RDATA0,
-        MX51_PAD_NANDF_D8__FEC_TDATA0,
-        MX51_PAD_NANDF_CS2__FEC_TX_ER,
-        MX51_PAD_NANDF_CS3__FEC_MDC,
-        MX51_PAD_NANDF_CS4__FEC_TDATA1,
-        MX51_PAD_NANDF_CS5__FEC_TDATA2,
-        MX51_PAD_NANDF_CS6__FEC_TDATA3,
-        MX51_PAD_NANDF_CS7__FEC_TX_EN,
-        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
-
-        /* FEC PHY reset line */
-        MX51_PAD_EIM_A20__GPIO2_14,
-
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* CD/WP from controller */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-        /* CD/WP gpio */
-        MX51_PAD_GPIO1_6__GPIO1_6,
-        MX51_PAD_GPIO1_5__GPIO1_5,
-
-        /* eCSPI1 */
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-
-        /* Audio */
-        MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
-        MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
-        MX51_PAD_AUD3_BB_CK__AUD3_TXC,
-        MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
-        .bitrate = 400000,
-};
-
-static struct gpio mx51_babbage_usbh1_gpios[] = {
-        { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
-        { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
-};
-
-static int gpio_usbh1_active(void)
-{
-        iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-        int ret;
-
-        /* Set USBH1_STP to GPIO and toggle it */
-        mxc_iomux_v3_setup_pad(usbh1stp_gpio);
-        ret = gpio_request_array(mx51_babbage_usbh1_gpios,
-                                        ARRAY_SIZE(mx51_babbage_usbh1_gpios));
-
-        if (ret) {
-                pr_debug("failed to get USBH1 pins: %d\n", ret);
-                return ret;
-        }
-
-        msleep(100);
-        gpio_set_value(BABBAGE_USBH1_STP, 1);
-        gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
-        gpio_free_array(mx51_babbage_usbh1_gpios,
-                                        ARRAY_SIZE(mx51_babbage_usbh1_gpios));
-        return 0;
-}
-
-static inline void babbage_usbhub_reset(void)
-{
-        int ret;
-
-        /* Reset USB hub */
-        ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
-                                        GPIOF_OUT_INIT_LOW, "GPIO1_7");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
-                return;
-        }
-
-        msleep(2);
-        /* Deassert reset */
-        gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
-}
-
-static inline void babbage_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
-                                        GPIOF_OUT_INIT_LOW, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        msleep(1);
-        gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
-}
-
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        /* The clock for the USBH1 ULPI port will come externally from the PHY. */
-        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
-        iounmap(usb_base);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                        MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init           = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-        .init           = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init babbage_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", babbage_otg_mode);
-
-static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
-        {
-                .modalias = "mtd_dataflash",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-                .platform_data = NULL,
-        },
-};
-
-static int mx51_babbage_spi_cs[] = {
-        BABBAGE_ECSPI1_CS0,
-        BABBAGE_ECSPI1_CS1,
-};
-
-static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
-        .chipselect     = mx51_babbage_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
-};
-
-static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
-        .cd_gpio = BABBAGE_SD2_CD,
-        .wp_gpio = BABBAGE_SD2_WP,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_GPIO,
-};
-
-void __init imx51_babbage_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
-                                         ARRAY_SIZE(mx51babbage_pads));
-}
-
-/*
- * Board specific initialization.
- */
-static void __init mx51_babbage_init(void)
-{
-        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
-                PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
-
-        imx51_soc_init();
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-        imx51_babbage_common_init();
-
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, NULL);
-        imx51_add_imx_uart(2, &uart_pdata);
-
-        babbage_fec_reset();
-        imx51_add_fec(NULL);
-
-        /* Set the PAD settings for the pwr key. */
-        mxc_iomux_v3_setup_pad(power_key);
-        imx_add_gpio_keys(&imx_button_data);
-
-        imx51_add_imx_i2c(0, &babbage_i2c_data);
-        imx51_add_imx_i2c(1, &babbage_i2c_data);
-        imx51_add_hsi2c(&babbage_hsi2c_data);
-
-        if (otg_mode_host)
-                imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        else {
-                initialize_otg_port(NULL);
-                imx51_add_fsl_usb2_udc(&usb_pdata);
-        }
-
-        gpio_usbh1_active();
-        imx51_add_mxc_ehci_hs(1, &usbh1_config);
-        /* setback USBH1_STP to be function */
-        mxc_iomux_v3_setup_pad(usbh1stp);
-        babbage_usbhub_reset();
-
-        imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
-        imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
-
-        spi_register_board_info(mx51_babbage_spi_board_info,
-                ARRAY_SIZE(mx51_babbage_spi_board_info));
-        imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
-        imx51_add_imx2_wdt(0);
-}
-
-static void __init mx51_babbage_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx51_babbage_timer = {
-        .init = mx51_babbage_timer_init,
-};
-
-MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
-        /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_babbage_timer,
-        .init_machine = mx51_babbage_init,
-        .init_late      = imx51_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index f4a8c7e108e..c85876fed66 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -21,17 +21,17 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
+#include <mach/iomux-mx27.h>
 #include <linux/i2c/pca953x.h>
 
-#include "common.h"
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
 
 static const int mxt_td60_pins[] __initconst = {
         /* UART0 */
@@ -213,13 +213,13 @@ static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
 static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
                                 void *data)
 {
-        return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
-                           IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
+        return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
+                                "sdhc1-card-detect", data);
 }
 
 static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
+        free_irq(IRQ_GPIOF(8), data);
 }
 
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
@@ -267,12 +267,10 @@ static struct sys_timer mxt_td60_timer = {
 
 MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
         /* maintainer: Maxtrack Industrial */
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &mxt_td60_timer,
         .init_machine = mxt_td60_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index eee369fa94a..71083aa1603 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -32,13 +32,15 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
+#include <mach/audmux.h>
+#include <mach/irqs.h>
+#include <mach/ulpi.h>
 
-#include "common.h"
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
@@ -244,7 +246,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 {
         int ret;
 
-        ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
+        ret = request_irq(IRQ_GPIOC(29), detect_irq,
                           IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                           "imx-mmc-detect", data);
         if (ret)
@@ -256,7 +258,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 
 static void pca100_sdhc2_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
+        free_irq(IRQ_GPIOC(29), data);
 }
 
 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
@@ -297,18 +299,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init pca100_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", pca100_otg_mode);
 
@@ -357,6 +359,18 @@ static void __init pca100_init(void)
 
         imx27_soc_init();
 
+        /* SSI unit */
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+                                  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+                                  MXC_AUDMUX_V1_PCR_TFCSEL(3) |
+                                  MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+                                  MXC_AUDMUX_V1_PCR_RXDSEL(3));
+        mxc_audmux_v1_configure_port(3,
+                                  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+                                  MXC_AUDMUX_V1_PCR_TFCSEL(0) |
+                                  MXC_AUDMUX_V1_PCR_TFSDIR |
+                                  MXC_AUDMUX_V1_PCR_RXDSEL(0));
+
         ret = mxc_gpio_setup_multiple_pins(pca100_pins,
                         ARRAY_SIZE(pca100_pins), "PCA100");
         if (ret)
@@ -407,8 +421,8 @@ static void __init pca100_init(void)
         imx27_add_imx_fb(&pca100_fb_data);
 
         imx27_add_fec(NULL);
-        imx27_add_imx2_wdt();
-        imx27_add_mxc_w1();
+        imx27_add_imx2_wdt(NULL);
+        imx27_add_mxc_w1(NULL);
 }
 
 static void __init pca100_timer_init(void)
@@ -421,12 +435,10 @@ static struct sys_timer pca100_timer = {
 };
 
 MACHINE_START(PCA100, "phyCARD-i.MX27")
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .init_machine = pca100_init,
         .timer = &pca100_timer,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 547fef133f6..f45b7cd72c8 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -32,8 +32,6 @@
 #include <linux/usb/ulpi.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
 
 #include <media/soc_camera.h>
 
@@ -41,14 +39,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <asm/memblock.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
 
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
 #include "pcm037.h"
-#include "ulpi.h"
 
 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
 
@@ -225,7 +222,8 @@ static struct resource smsc911x_resources[] = {
                 .end            = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
                 .flags          = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start          = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+                .end            = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                 .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -370,7 +368,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
         gpio_direction_input(SDHC1_GPIO_WP);
 #endif
 
-        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
                         IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                                 "sdhc-detect", data);
         if (ret)
@@ -390,7 +388,7 @@ err_gpio_free:
 
 static void pcm970_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
         gpio_free(SDHC1_GPIO_DET);
         gpio_free(SDHC1_GPIO_WP);
 }
@@ -441,6 +439,10 @@ static struct platform_device *devices[] __initdata = {
         &pcm037_mt9v022,
 };
 
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static const struct fb_videomode fb_modedb[] = {
         {
                 /* 240x320 @ 60 Hz Sharp */
@@ -506,7 +508,8 @@ static struct resource pcm970_sja1000_resources[] = {
                 .end     = MX31_CS5_BASE_ADDR + 0x100 - 1,
                 .flags   = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
                 .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         },
 };
@@ -551,26 +554,21 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init pcm037_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", pcm037_otg_mode);
 
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
 /*
  * Board specific initialization.
  */
@@ -580,8 +578,6 @@ static void __init pcm037_init(void)
 
         imx31_soc_init();
 
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
         mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
         mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
@@ -613,13 +609,13 @@ static void __init pcm037_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        imx31_add_imx2_wdt();
+        imx31_add_imx2_wdt(NULL);
         imx31_add_imx_uart0(&uart_pdata);
         /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
         imx31_add_imx_uart1(&uart_pdata);
         imx31_add_imx_uart2(&uart_pdata);
 
-        imx31_add_mxc_w1();
+        imx31_add_mxc_w1(NULL);
 
         /* LAN9217 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
@@ -627,10 +623,6 @@ static void __init pcm037_init(void)
                 pr_warning("could not get LAN irq gpio\n");
         else {
                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
-                smsc911x_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
-                smsc911x_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
                 platform_device_register(&pcm037_eth);
         }
 
@@ -644,7 +636,7 @@ static void __init pcm037_init(void)
 
         imx31_add_mxc_nand(&pcm037_nand_board_info);
         imx31_add_mxc_mmc(0, &sdhc_pdata);
-        imx31_add_ipu_core();
+        imx31_add_ipu_core(&mx3_ipu_data);
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* CSI */
@@ -657,10 +649,6 @@ static void __init pcm037_init(void)
 
         pcm037_init_camera();
 
-        pcm970_sja1000_resources[1].start =
-                        gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
-        pcm970_sja1000_resources[1].end =
-                        gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
         platform_device_register(&pcm970_sja1000);
 
         if (otg_mode_host) {
@@ -685,32 +673,26 @@ static void __init pcm037_timer_init(void)
         mx31_clocks_init(26000000);
 }
 
-static struct sys_timer pcm037_timer = {
+struct sys_timer pcm037_timer = {
         .init   = pcm037_timer_init,
 };
 
 static void __init pcm037_reserve(void)
 {
         /* reserve 4 MiB for mx3-camera */
-        mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
+        mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
                         MX3_CAMERA_BUF_SIZE);
-}
-
-static void __init pcm037_init_late(void)
-{
-        pcm037_eet_init_devices();
+        memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
 }
 
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
         /* Maintainer: Pengutronix */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .reserve = pcm037_reserve,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &pcm037_timer,
         .init_machine = pcm037_init,
-        .init_late = pcm037_init_late,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index 8fd8255068e..1b7606bef8f 100644
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -11,12 +11,13 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+
 #include <asm/mach-types.h>
 
 #include "pcm037.h"
-#include "common.h"
 #include "devices-imx31.h"
-#include "iomux-mx3.h"
 
 static unsigned int pcm037_eet_pins[] = {
         /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
@@ -159,9 +160,9 @@ static const struct gpio_keys_platform_data
         .rep            = 0, /* No auto-repeat */
 };
 
-int __init pcm037_eet_init_devices(void)
+static int __init eet_init_devices(void)
 {
-        if (pcm037_variant() != PCM037_EET)
+        if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
                 return 0;
 
         mxc_iomux_setup_multiple_pins(pcm037_eet_pins,
@@ -175,3 +176,4 @@ int __init pcm037_eet_init_devices(void)
 
         return 0;
 }
+late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 4aa0d079860..2d6a64bbac4 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -27,18 +27,18 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
-#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "board-pcm038.h"
-#include "common.h"
+#include <mach/board-pcm038.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx27.h>
+#include <mach/ulpi.h>
+
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
 
 static const int pcm038_pins[] __initconst = {
         /* UART1 */
@@ -176,9 +176,7 @@ static struct platform_device *platform_devices[] __initdata = {
  * setup other stuffs to access the sram. */
 static void __init pcm038_init_sram(void)
 {
-        __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
-        __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
-        __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
+        mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
 }
 
 static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
@@ -211,7 +209,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
 
 static struct regulator_consumer_supply sdhc1_consumers[] = {
         {
-                .dev_name = "imx21-mmc.1",
+                .dev_name = "mxc-mmc.1",
                 .supply = "sdhc_vcc",
         },
 };
@@ -233,7 +231,7 @@ static struct regulator_init_data sdhc1_data = {
 
 static struct regulator_consumer_supply cam_consumers[] = {
         {
-                .dev_name = NULL,
+                .dev    = NULL,
                 .supply = "imx_cam_vcc",
         },
 };
@@ -268,13 +266,14 @@ static struct mc13xxx_platform_data pcm038_pmic = {
                 .regulators = pcm038_regulators,
                 .num_regulators = ARRAY_SIZE(pcm038_regulators),
         },
-        .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
+        .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR |
+                 MC13783_USE_TOUCHSCREEN,
 };
 
 static struct spi_board_info pcm038_spi_board_info[] __initdata = {
         {
                 .modalias = "mc13783",
-                /* irq number is run-time assigned */
+                .irq = IRQ_GPIOB(23),
                 .max_speed_hz = 300000,
                 .bus_num = 0,
                 .chip_select = 0,
@@ -325,7 +324,6 @@ static void __init pcm038_init(void)
         mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
         imx27_add_spi_imx0(&pcm038_spi0_data);
-        pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
         spi_register_board_info(pcm038_spi_board_info,
                                 ARRAY_SIZE(pcm038_spi_board_info));
 
@@ -333,8 +331,8 @@ static void __init pcm038_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt();
-        imx27_add_mxc_w1();
+        imx27_add_imx2_wdt(NULL);
+        imx27_add_mxc_w1(NULL);
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
         pcm970_baseboard_init();
@@ -351,12 +349,10 @@ static struct sys_timer pcm038_timer = {
 };
 
 MACHINE_START(PCM038, "phyCORE-i.MX27")
-        .atag_offset = 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
         .timer = &pcm038_timer,
         .init_machine = pcm038_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 92445440221..660ec3e80cf 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -33,11 +33,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ulpi.h>
+#include <mach/audmux.h>
+
 #include "devices-imx35.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
-#include "ulpi.h"
 
 static const struct fb_videomode fb_modedb[] = {
         {
@@ -75,6 +77,10 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "Sharp-LQ035Q7",
         .mode           = fb_modedb,
@@ -325,18 +331,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_UTMI,
 };
 
-static bool otg_mode_host __initdata;
+static int otg_mode_host;
 
 static int __init pcm043_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = true;
+                otg_mode_host = 1;
         else if (!strcmp(options, "device"))
-                otg_mode_host = false;
+                otg_mode_host = 0;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 1;
+        return 0;
 }
 __setup("otg_mode=", pcm043_otg_mode);
 
@@ -356,9 +362,21 @@ static void __init pcm043_init(void)
 
         mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
+        mxc_audmux_v2_configure_port(3,
+                        MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+                        MXC_AUDMUX_V2_PTCR_TFSEL(0) |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0));
+
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+                        MXC_AUDMUX_V2_PTCR_TCSEL(3) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(3));
+
         imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
-        imx35_add_imx2_wdt();
+        imx35_add_imx2_wdt(NULL);
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&pcm037_nand_board_info);
@@ -371,7 +389,7 @@ static void __init pcm043_init(void)
 
         imx35_add_imx_i2c0(&pcm043_i2c0_data);
 
-        imx35_add_ipu_core();
+        imx35_add_ipu_core(&mx3_ipu_data);
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         if (otg_mode_host) {
@@ -394,18 +412,16 @@ static void __init pcm043_timer_init(void)
         mx35_clocks_init();
 }
 
-static struct sys_timer pcm043_timer = {
+struct sys_timer pcm043_timer = {
         .init   = pcm043_timer_init,
 };
 
 MACHINE_START(PCM043, "Phytec Phycore pcm043")
         /* Maintainer: Pengutronix */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
         .timer = &pcm043_timer,
         .init_machine = pcm043_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 96d9a91f8a3..3626f486498 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -21,17 +21,18 @@
 #include <linux/mtd/nand.h>
 #include <linux/gpio.h>
 
+#include <mach/hardware.h>
+#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <mach/iomux-mx3.h>
 
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
 
 /* FPGA defines */
 #define QONG_FPGA_VERSION(major, minor, rev)    \
@@ -50,6 +51,8 @@
         (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
 #define QONG_DNET_SIZE          0x00001000
 
+#define QONG_FPGA_IRQ           IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
+
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -75,7 +78,8 @@ static struct resource dnet_resources[] = {
                 .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start  = QONG_FPGA_IRQ,
+                .end    = QONG_FPGA_IRQ,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -91,10 +95,6 @@ static int __init qong_init_dnet(void)
 {
         int ret;
 
-        dnet_resources[1].start =
-                gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
-        dnet_resources[1].end =
-                gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
         ret = platform_device_register(&dnet_device);
         return ret;
 }
@@ -190,10 +190,7 @@ static struct platform_device qong_nand_device = {
 static void __init qong_init_nand_mtd(void)
 {
         /* init CS */
-        __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
-        __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
-        __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
-
+        mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
         mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
 
         /* enable pin */
@@ -252,7 +249,6 @@ static void __init qong_init(void)
         mxc_init_imx_uart();
         qong_init_nor_mtd();
         qong_init_fpga();
-        imx31_add_imx2_wdt();
 }
 
 static void __init qong_timer_init(void)
@@ -266,12 +262,10 @@ static struct sys_timer qong_timer = {
 
 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
         /* Maintainer: DENX Software Engineering GmbH */
-        .atag_offset = 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
         .timer = &qong_timer,
         .init_machine = qong_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index fc970409dba..db2d60470e1 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -14,16 +14,17 @@
 #include <linux/mtd/physmap.h>
 #include <linux/interrupt.h>
 #include <linux/dm9000.h>
-#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/iomux-mx1.h>
+
 #include "devices-imx1.h"
-#include "hardware.h"
-#include "iomux-mx1.h"
 
 /*
  * This scb9328 has a 32MiB flash
@@ -77,7 +78,8 @@ static struct resource dm9000x_resources[] = {
                 .end    = MX1_CS5_PHYS + 5,
                 .flags  = IORESOURCE_MEM,       /* data access */
         }, {
-                /* irq number is run-time assigned */
+                .start  = IRQ_GPIOC(3),
+                .end    = IRQ_GPIOC(3),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -121,8 +123,6 @@ static void __init scb9328_init(void)
         imx1_add_imx_uart0(&uart_pdata);
 
         printk(KERN_INFO"Scb9328: Adding devices\n");
-        dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3));
-        dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3));
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
@@ -137,12 +137,10 @@ static struct sys_timer scb9328_timer = {
 
 MACHINE_START(SCB9328, "Synertronixx scb9328")
         /* Sascha Hauer */
-        .atag_offset = 100,
+        .boot_params = 0x08000100,
         .map_io = mx1_map_io,
         .init_early = imx1_init_early,
         .init_irq = mx1_init_irq,
-        .handle_irq = imx1_handle_irq,
         .timer = &scb9328_timer,
         .init_machine = scb9328_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 3aecf91e428..7d8e012a633 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -28,14 +28,16 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/mfd/mc13xxx.h>
 
-#include "common.h"
 #include "devices-imx35.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
 
 #define GPIO_LCDPWR     IMX_GPIO_NR(1, 2)
 #define GPIO_PMIC_INT   IMX_GPIO_NR(2, 0)
@@ -85,6 +87,10 @@ static const struct fb_videomode fb_modedb[] = {
         }
 };
 
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "PT0708048",
         .mode           = fb_modedb,
@@ -156,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
         }, {
                 I2C_BOARD_INFO("mc13892", 0x08),
                 .platform_data = &vpr200_pmic,
-                /* irq number is run-time assigned */
+                .irq = gpio_to_irq(GPIO_PMIC_INT),
         }
 };
 
@@ -266,7 +272,7 @@ static void __init vpr200_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt();
+        imx35_add_imx2_wdt(NULL);
         imx_add_gpio_keys(&vpr200_gpio_keys_data);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -284,7 +290,7 @@ static void __init vpr200_board_init(void)
         imx35_add_imx_uart0(NULL);
         imx35_add_imx_uart2(NULL);
 
-        imx35_add_ipu_core();
+        imx35_add_ipu_core(&mx3_ipu_data);
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         imx35_add_fsl_usb2_udc(&otg_device_pdata);
@@ -293,7 +299,6 @@ static void __init vpr200_board_init(void)
         imx35_add_mxc_nand(&vpr200_nand_board_info);
         imx35_add_sdhci_esdhc_imx(0, NULL);
 
-        vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
         i2c_register_board_info(0, vpr200_i2c_devices,
                         ARRAY_SIZE(vpr200_i2c_devices));
 
@@ -305,7 +310,7 @@ static void __init vpr200_timer_init(void)
         mx35_clocks_init();
 }
 
-static struct sys_timer vpr200_timer = {
+struct sys_timer vpr200_timer = {
         .init   = vpr200_timer_init,
 };
 
@@ -314,8 +319,6 @@ MACHINE_START(VPR200, "VPR200")
         .map_io = mx35_map_io,
         .init_early = imx35_init_early,
         .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
         .timer = &vpr200_timer,
         .init_machine = vpr200_board_init,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 7a146671e65..2bded591d5c 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -18,14 +18,13 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 
 static struct map_desc imx_io_desc[] __initdata = {
         imx_map_entry(MX1, IO, MT_DEVICE),
@@ -59,7 +58,4 @@ void __init imx1_soc_init(void)
                                                 MX1_GPIO_INT_PORTC, 0);
         mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
                                                 MX1_GPIO_INT_PORTD, 0);
-        imx_add_imx_dma("imx1-dma", MX1_DMA_BASE_ADDR,
-                        MX1_DMA_INT, MX1_DMA_ERR);
-        pinctrl_provide_dummies();
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a8ec5..3f05dfebacc 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -20,14 +20,13 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/pinctrl/machine.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 
 /* MX21 memory map definition */
 static struct map_desc imx21_io_desc[] __initdata = {
@@ -76,14 +75,8 @@ void __init mx21_init_irq(void)
         mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
 }
 
-static const struct resource imx21_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
-};
-
 void __init imx21_soc_init(void)
 {
-        mxc_device_init();
-
         mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
@@ -91,9 +84,5 @@ void __init imx21_soc_init(void)
         mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
 
-        pinctrl_provide_dummies();
-        imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR,
-                        MX21_INT_DMACH0, 0); /* No ERR irq */
-        platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
-                                        ARRAY_SIZE(imx21_audmux_res));
+        imx_add_imx_dma();
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707bb7a..cc4d152bd9b 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -19,16 +19,16 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
-#include <linux/pinctrl/machine.h>
 
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-#include "mx25.h"
+#include <mach/common.h>
+#include <mach/devices-common.h>
+#include <mach/hardware.h>
+#include <mach/mx25.h>
+#include <mach/iomux-v3.h>
+#include <mach/irqs.h>
 
 /*
  * This table defines static virtual address mappings for I/O regions.
@@ -83,24 +83,14 @@ static struct sdma_platform_data imx25_sdma_pdata __initdata = {
         .script_addrs = &imx25_sdma_script,
 };
 
-static const struct resource imx25_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
 void __init imx25_soc_init(void)
 {
-        mxc_device_init();
-
-        /* i.mx25 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
-        mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
-        mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
-        mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+        /* i.mx25 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
+        mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
 
-        pinctrl_provide_dummies();
         /* i.mx25 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
-        /* i.mx25 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
-                                        ARRAY_SIZE(imx25_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65a7b5..96dd1f5ea7b 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -20,14 +20,13 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/pinctrl/machine.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 
 /* MX27 memory map definition */
 static struct map_desc imx27_io_desc[] __initdata = {
@@ -76,14 +75,8 @@ void __init mx27_init_irq(void)
         mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
 }
 
-static const struct resource imx27_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
-};
-
 void __init imx27_soc_init(void)
 {
-        mxc_device_init();
-
         /* i.mx27 has the i.mx21 type gpio */
         mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
@@ -92,10 +85,5 @@ void __init imx27_soc_init(void)
         mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
 
-        pinctrl_provide_dummies();
-        imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR,
-                        MX27_INT_DMACH0, 0); /* No ERR irq */
-        /* imx27 has the imx21 type audmux */
-        platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
-                                        ARRAY_SIZE(imx27_audmux_res));
+        imx_add_imx_dma();
 }
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
deleted file mode 100644
index cefa047c405..00000000000
--- a/arch/arm/mach-imx/mm-imx3.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/pinctrl/machine.h>
-
-#include <asm/pgtable.h>
-#include <asm/system_misc.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "crmregs-imx3.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-
-void __iomem *mx3_ccm_base;
-
-static void imx3_idle(void)
-{
-        unsigned long reg = 0;
-
-        mx3_cpu_lp_set(MX3_WAIT);
-
-        __asm__ __volatile__(
-                /* disable I and D cache */
-                "mrc p15, 0, %0, c1, c0, 0\n"
-                "bic %0, %0, #0x00001000\n"
-                "bic %0, %0, #0x00000004\n"
-                "mcr p15, 0, %0, c1, c0, 0\n"
-                /* invalidate I cache */
-                "mov %0, #0\n"
-                "mcr p15, 0, %0, c7, c5, 0\n"
-                /* clear and invalidate D cache */
-                "mov %0, #0\n"
-                "mcr p15, 0, %0, c7, c14, 0\n"
-                /* WFI */
-                "mov %0, #0\n"
-                "mcr p15, 0, %0, c7, c0, 4\n"
-                "nop\n" "nop\n" "nop\n" "nop\n"
-                "nop\n" "nop\n" "nop\n"
-                /* enable I and D cache */
-                "mrc p15, 0, %0, c1, c0, 0\n"
-                "orr %0, %0, #0x00001000\n"
-                "orr %0, %0, #0x00000004\n"
-                "mcr p15, 0, %0, c1, c0, 0\n"
-                : "=r" (reg));
-}
-
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
-                                         unsigned int mtype, void *caller)
-{
-        if (mtype == MT_DEVICE) {
-                /*
-                 * Access all peripherals below 0x80000000 as nonshared device
-                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
-                 * can occur.
-                 */
-                if (phys_addr < 0x80000000 &&
-                                !addr_in_module(phys_addr, MX3x_L2CC))
-                        mtype = MT_DEVICE_NONSHARED;
-        }
-
-        return __arm_ioremap_caller(phys_addr, size, mtype, caller);
-}
-
-void __init imx3_init_l2x0(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base;
-        void __iomem *clkctl_base;
-
-/*
- * First of all, we must repair broken chip settings. There are some
- * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
- * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
- * Workaraound is to setup the correct register setting prior enabling the
- * L2 cache. This should not hurt already working CPUs, as they are using the
- * same value.
- */
-#define L2_MEM_VAL 0x10
-
-        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
-        if (clkctl_base != NULL) {
-                writel(0x00000515, clkctl_base + L2_MEM_VAL);
-                iounmap(clkctl_base);
-        } else {
-                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
-        }
-
-        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
-        if (!l2x0_base) {
-                printk(KERN_ERR "remapping L2 cache area failed\n");
-                return;
-        }
-
-        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
-#endif
-}
-
-#ifdef CONFIG_SOC_IMX31
-static struct map_desc mx31_io_desc[] __initdata = {
-        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
-        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-
-void __init imx31_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-        arch_ioremap_caller = imx3_ioremap_caller;
-        arm_pm_idle = imx3_idle;
-        mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
-}
-
-void __init mx31_init_irq(void)
-{
-        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-}
-
-static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
-        .per_2_per_addr = 1677,
-};
-
-static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
-        .ap_2_ap_addr = 423,
-        .ap_2_bp_addr = 829,
-        .bp_2_ap_addr = 1029,
-};
-
-static struct sdma_platform_data imx31_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx31-to2.bin",
-        .script_addrs = &imx31_to2_sdma_script,
-};
-
-static const struct resource imx31_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx31_soc_init(void)
-{
-        int to_version = mx31_revision() >> 4;
-
-        imx3_init_l2x0();
-
-        mxc_device_init();
-
-        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
-
-        pinctrl_provide_dummies();
-
-        if (to_version == 1) {
-                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
-                        strlen(imx31_sdma_pdata.fw_name));
-                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
-        }
-
-        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
-
-        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
-        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
-
-        platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
-                                        ARRAY_SIZE(imx31_audmux_res));
-}
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-static struct map_desc mx35_io_desc[] __initdata = {
-        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-void __init mx35_map_io(void)
-{
-        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
-}
-
-void __init imx35_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX35);
-        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-        arm_pm_idle = imx3_idle;
-        arch_ioremap_caller = imx3_ioremap_caller;
-        mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
-}
-
-void __init mx35_init_irq(void)
-{
-        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-}
-
-static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .uart_2_mcu_addr = 817,
-        .mcu_2_app_addr = 747,
-        .uartsh_2_mcu_addr = 1183,
-        .per_2_shp_addr = 1033,
-        .mcu_2_shp_addr = 961,
-        .ata_2_mcu_addr = 1333,
-        .mcu_2_ata_addr = 1252,
-        .app_2_mcu_addr = 683,
-        .shp_2_per_addr = 1111,
-        .shp_2_mcu_addr = 892,
-};
-
-static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
-        .ap_2_ap_addr = 729,
-        .uart_2_mcu_addr = 904,
-        .per_2_app_addr = 1597,
-        .mcu_2_app_addr = 834,
-        .uartsh_2_mcu_addr = 1270,
-        .per_2_shp_addr = 1120,
-        .mcu_2_shp_addr = 1048,
-        .ata_2_mcu_addr = 1429,
-        .mcu_2_ata_addr = 1339,
-        .app_2_per_addr = 1531,
-        .app_2_mcu_addr = 770,
-        .shp_2_per_addr = 1198,
-        .shp_2_mcu_addr = 979,
-};
-
-static struct sdma_platform_data imx35_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx35-to2.bin",
-        .script_addrs = &imx35_to2_sdma_script,
-};
-
-static const struct resource imx35_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx35_soc_init(void)
-{
-        int to_version = mx35_revision() >> 4;
-
-        imx3_init_l2x0();
-
-        mxc_device_init();
-
-        mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
-        mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
-        mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
-
-        pinctrl_provide_dummies();
-        if (to_version == 1) {
-                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
-                        strlen(imx35_sdma_pdata.fw_name));
-                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
-        }
-
-        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
-
-        /* Setup AIPS registers */
-        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
-        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
-
-        /* i.mx35 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
-                                        ARRAY_SIZE(imx35_audmux_res));
-}
-#endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
deleted file mode 100644
index 79d71cf23a1..00000000000
--- a/arch/arm/mach-imx/mm-imx5.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/pinctrl/machine.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-
-/*
- * Define the MX50 memory map.
- */
-static struct map_desc mx50_io_desc[] __initdata = {
-        imx_map_entry(MX50, TZIC, MT_DEVICE),
-        imx_map_entry(MX50, SPBA0, MT_DEVICE),
-        imx_map_entry(MX50, AIPS1, MT_DEVICE),
-        imx_map_entry(MX50, AIPS2, MT_DEVICE),
-};
-
-/*
- * Define the MX51 memory map.
- */
-static struct map_desc mx51_io_desc[] __initdata = {
-        imx_map_entry(MX51, TZIC, MT_DEVICE),
-        imx_map_entry(MX51, IRAM, MT_DEVICE),
-        imx_map_entry(MX51, AIPS1, MT_DEVICE),
-        imx_map_entry(MX51, SPBA0, MT_DEVICE),
-        imx_map_entry(MX51, AIPS2, MT_DEVICE),
-};
-
-/*
- * Define the MX53 memory map.
- */
-static struct map_desc mx53_io_desc[] __initdata = {
-        imx_map_entry(MX53, TZIC, MT_DEVICE),
-        imx_map_entry(MX53, AIPS1, MT_DEVICE),
-        imx_map_entry(MX53, SPBA0, MT_DEVICE),
-        imx_map_entry(MX53, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx50_map_io(void)
-{
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
-}
-
-void __init mx51_map_io(void)
-{
-        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
-}
-
-void __init mx53_map_io(void)
-{
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
-}
-
-void __init imx50_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX50);
-        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-}
-
-/*
- * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
- * the Freescale marketing division. However this did not remove the
- * hardware from the chip which still needs to be configured for proper
- * IPU support.
- */
-static void __init imx51_ipu_mipi_setup(void)
-{
-        void __iomem *hsc_addr;
-        hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
-
-        /* setup MIPI module to legacy mode */
-        __raw_writel(0xf00, hsc_addr);
-
-        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
-        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
-                hsc_addr + 0x800);
-}
-
-void __init imx51_init_early(void)
-{
-        imx51_ipu_mipi_setup();
-        mxc_set_cpu_type(MXC_CPU_MX51);
-        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-}
-
-void __init imx53_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX53);
-        mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
-}
-
-void __init mx50_init_irq(void)
-{
-        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-}
-
-void __init mx51_init_irq(void)
-{
-        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
-}
-
-void __init mx53_init_irq(void)
-{
-        tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
-}
-
-static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .uart_2_mcu_addr = 817,
-        .mcu_2_app_addr = 747,
-        .mcu_2_shp_addr = 961,
-        .ata_2_mcu_addr = 1473,
-        .mcu_2_ata_addr = 1392,
-        .app_2_per_addr = 1033,
-        .app_2_mcu_addr = 683,
-        .shp_2_per_addr = 1251,
-        .shp_2_mcu_addr = 892,
-};
-
-static struct sdma_platform_data imx51_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx51.bin",
-        .script_addrs = &imx51_sdma_script,
-};
-
-static const struct resource imx50_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-static const struct resource imx51_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx50_soc_init(void)
-{
-        mxc_device_init();
-
-        /* i.mx50 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
-
-        /* i.mx50 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
-                                        ARRAY_SIZE(imx50_audmux_res));
-}
-
-void __init imx51_soc_init(void)
-{
-        mxc_device_init();
-
-        /* i.mx51 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
-
-        pinctrl_provide_dummies();
-
-        /* i.mx51 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
-
-        /* Setup AIPS registers */
-        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
-        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
-
-        /* i.mx51 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
-                                        ARRAY_SIZE(imx51_audmux_res));
-}
-
-void __init imx51_init_late(void)
-{
-        mx51_neon_fixup();
-        imx51_pm_init();
-}
-
-void __init imx53_init_late(void)
-{
-        imx53_pm_init();
-}
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
deleted file mode 100644
index 7a9686ad994..00000000000
--- a/arch/arm/mach-imx/mmdc.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-
-#define MMDC_MAPSR              0x404
-#define BP_MMDC_MAPSR_PSD       0
-#define BP_MMDC_MAPSR_PSS       4
-
-static int imx_mmdc_probe(struct platform_device *pdev)
-{
-        struct device_node *np = pdev->dev.of_node;
-        void __iomem *mmdc_base, *reg;
-        u32 val;
-        int timeout = 0x400;
-
-        mmdc_base = of_iomap(np, 0);
-        WARN_ON(!mmdc_base);
-
-        reg = mmdc_base + MMDC_MAPSR;
-
-        /* Enable automatic power saving */
-        val = readl_relaxed(reg);
-        val &= ~(1 << BP_MMDC_MAPSR_PSD);
-        writel_relaxed(val, reg);
-
-        /* Ensure it's successfully enabled */
-        while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout)) {
-                pr_warn("%s: failed to enable automatic power saving\n",
-                        __func__);
-                return -EBUSY;
-        }
-
-        return 0;
-}
-
-static struct of_device_id imx_mmdc_dt_ids[] = {
-        { .compatible = "fsl,imx6q-mmdc", },
-        { /* sentinel */ }
-};
-
-static struct platform_driver imx_mmdc_driver = {
-        .driver         = {
-                .name   = "imx-mmdc",
-                .owner  = THIS_MODULE,
-                .of_match_table = imx_mmdc_dt_ids,
-        },
-        .probe          = imx_mmdc_probe,
-};
-
-static int __init imx_mmdc_init(void)
-{
-        return platform_driver_register(&imx_mmdc_driver);
-}
-postcore_initcall(imx_mmdc_init);
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
index fb38436ca67..b09ee12a4ff 100644
--- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
@@ -11,7 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 
-#include <linux/platform_data/camera-mx1.h>
+#include <mach/mx1_camera.h>
 
 /* IMX camera FIQ handler */
 EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
diff --git a/arch/arm/mach-imx/mx1.h b/arch/arm/mach-imx/mx1.h
deleted file mode 100644
index 45bd31cc34d..00000000000
--- a/arch/arm/mach-imx/mx1.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright (C) 1997,1998 Russell King
- * Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MX1_H__
-#define __MACH_MX1_H__
-
-/*
- * Memory map
- */
-#define MX1_IO_BASE_ADDR        0x00200000
-#define MX1_IO_SIZE             SZ_1M
-
-#define MX1_CS0_PHYS            0x10000000
-#define MX1_CS0_SIZE            0x02000000
-
-#define MX1_CS1_PHYS            0x12000000
-#define MX1_CS1_SIZE            0x01000000
-
-#define MX1_CS2_PHYS            0x13000000
-#define MX1_CS2_SIZE            0x01000000
-
-#define MX1_CS3_PHYS            0x14000000
-#define MX1_CS3_SIZE            0x01000000
-
-#define MX1_CS4_PHYS            0x15000000
-#define MX1_CS4_SIZE            0x01000000
-
-#define MX1_CS5_PHYS            0x16000000
-#define MX1_CS5_SIZE            0x01000000
-
-/*
- *  Register BASEs, based on OFFSETs
- */
-#define MX1_AIPI1_BASE_ADDR             (0x00000 + MX1_IO_BASE_ADDR)
-#define MX1_WDT_BASE_ADDR               (0x01000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM1_BASE_ADDR              (0x02000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM2_BASE_ADDR              (0x03000 + MX1_IO_BASE_ADDR)
-#define MX1_RTC_BASE_ADDR               (0x04000 + MX1_IO_BASE_ADDR)
-#define MX1_LCDC_BASE_ADDR              (0x05000 + MX1_IO_BASE_ADDR)
-#define MX1_UART1_BASE_ADDR             (0x06000 + MX1_IO_BASE_ADDR)
-#define MX1_UART2_BASE_ADDR             (0x07000 + MX1_IO_BASE_ADDR)
-#define MX1_PWM_BASE_ADDR               (0x08000 + MX1_IO_BASE_ADDR)
-#define MX1_DMA_BASE_ADDR               (0x09000 + MX1_IO_BASE_ADDR)
-#define MX1_AIPI2_BASE_ADDR             (0x10000 + MX1_IO_BASE_ADDR)
-#define MX1_SIM_BASE_ADDR               (0x11000 + MX1_IO_BASE_ADDR)
-#define MX1_USBD_BASE_ADDR              (0x12000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI1_BASE_ADDR             (0x13000 + MX1_IO_BASE_ADDR)
-#define MX1_MMC_BASE_ADDR               (0x14000 + MX1_IO_BASE_ADDR)
-#define MX1_ASP_BASE_ADDR               (0x15000 + MX1_IO_BASE_ADDR)
-#define MX1_BTA_BASE_ADDR               (0x16000 + MX1_IO_BASE_ADDR)
-#define MX1_I2C_BASE_ADDR               (0x17000 + MX1_IO_BASE_ADDR)
-#define MX1_SSI_BASE_ADDR               (0x18000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI2_BASE_ADDR             (0x19000 + MX1_IO_BASE_ADDR)
-#define MX1_MSHC_BASE_ADDR              (0x1A000 + MX1_IO_BASE_ADDR)
-#define MX1_CCM_BASE_ADDR               (0x1B000 + MX1_IO_BASE_ADDR)
-#define MX1_SCM_BASE_ADDR               (0x1B804 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO_BASE_ADDR              (0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO1_BASE_ADDR             (0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO2_BASE_ADDR             (0x1C100 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO3_BASE_ADDR             (0x1C200 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO4_BASE_ADDR             (0x1C300 + MX1_IO_BASE_ADDR)
-#define MX1_EIM_BASE_ADDR               (0x20000 + MX1_IO_BASE_ADDR)
-#define MX1_SDRAMC_BASE_ADDR            (0x21000 + MX1_IO_BASE_ADDR)
-#define MX1_MMA_BASE_ADDR               (0x22000 + MX1_IO_BASE_ADDR)
-#define MX1_AVIC_BASE_ADDR              (0x23000 + MX1_IO_BASE_ADDR)
-#define MX1_CSI_BASE_ADDR               (0x24000 + MX1_IO_BASE_ADDR)
-
-/* macro to get at IO space when running virtually */
-#define MX1_IO_P2V(x)                   IMX_IO_P2V(x)
-#define MX1_IO_ADDRESS(x)               IOMEM(MX1_IO_P2V(x))
-
-/* fixed interrput numbers */
-#include <asm/irq.h>
-#define MX1_INT_SOFTINT         (NR_IRQS_LEGACY + 0)
-#define MX1_INT_CSI             (NR_IRQS_LEGACY + 6)
-#define MX1_DSPA_MAC_INT        (NR_IRQS_LEGACY + 7)
-#define MX1_DSPA_INT            (NR_IRQS_LEGACY + 8)
-#define MX1_COMP_INT            (NR_IRQS_LEGACY + 9)
-#define MX1_MSHC_XINT           (NR_IRQS_LEGACY + 10)
-#define MX1_GPIO_INT_PORTA      (NR_IRQS_LEGACY + 11)
-#define MX1_GPIO_INT_PORTB      (NR_IRQS_LEGACY + 12)
-#define MX1_GPIO_INT_PORTC      (NR_IRQS_LEGACY + 13)
-#define MX1_INT_LCDC            (NR_IRQS_LEGACY + 14)
-#define MX1_SIM_INT             (NR_IRQS_LEGACY + 15)
-#define MX1_SIM_DATA_INT        (NR_IRQS_LEGACY + 16)
-#define MX1_RTC_INT             (NR_IRQS_LEGACY + 17)
-#define MX1_RTC_SAMINT          (NR_IRQS_LEGACY + 18)
-#define MX1_INT_UART2PFERR      (NR_IRQS_LEGACY + 19)
-#define MX1_INT_UART2RTS        (NR_IRQS_LEGACY + 20)
-#define MX1_INT_UART2DTR        (NR_IRQS_LEGACY + 21)
-#define MX1_INT_UART2UARTC      (NR_IRQS_LEGACY + 22)
-#define MX1_INT_UART2TX         (NR_IRQS_LEGACY + 23)
-#define MX1_INT_UART2RX         (NR_IRQS_LEGACY + 24)
-#define MX1_INT_UART1PFERR      (NR_IRQS_LEGACY + 25)
-#define MX1_INT_UART1RTS        (NR_IRQS_LEGACY + 26)
-#define MX1_INT_UART1DTR        (NR_IRQS_LEGACY + 27)
-#define MX1_INT_UART1UARTC      (NR_IRQS_LEGACY + 28)
-#define MX1_INT_UART1TX         (NR_IRQS_LEGACY + 29)
-#define MX1_INT_UART1RX         (NR_IRQS_LEGACY + 30)
-#define MX1_VOICE_DAC_INT       (NR_IRQS_LEGACY + 31)
-#define MX1_VOICE_ADC_INT       (NR_IRQS_LEGACY + 32)
-#define MX1_PEN_DATA_INT        (NR_IRQS_LEGACY + 33)
-#define MX1_PWM_INT             (NR_IRQS_LEGACY + 34)
-#define MX1_SDHC_INT            (NR_IRQS_LEGACY + 35)
-#define MX1_INT_I2C             (NR_IRQS_LEGACY + 39)
-#define MX1_INT_CSPI2           (NR_IRQS_LEGACY + 40)
-#define MX1_INT_CSPI1           (NR_IRQS_LEGACY + 41)
-#define MX1_SSI_TX_INT          (NR_IRQS_LEGACY + 42)
-#define MX1_SSI_TX_ERR_INT      (NR_IRQS_LEGACY + 43)
-#define MX1_SSI_RX_INT          (NR_IRQS_LEGACY + 44)
-#define MX1_SSI_RX_ERR_INT      (NR_IRQS_LEGACY + 45)
-#define MX1_TOUCH_INT           (NR_IRQS_LEGACY + 46)
-#define MX1_INT_USBD0           (NR_IRQS_LEGACY + 47)
-#define MX1_INT_USBD1           (NR_IRQS_LEGACY + 48)
-#define MX1_INT_USBD2           (NR_IRQS_LEGACY + 49)
-#define MX1_INT_USBD3           (NR_IRQS_LEGACY + 50)
-#define MX1_INT_USBD4           (NR_IRQS_LEGACY + 51)
-#define MX1_INT_USBD5           (NR_IRQS_LEGACY + 52)
-#define MX1_INT_USBD6           (NR_IRQS_LEGACY + 53)
-#define MX1_BTSYS_INT           (NR_IRQS_LEGACY + 55)
-#define MX1_BTTIM_INT           (NR_IRQS_LEGACY + 56)
-#define MX1_BTWUI_INT           (NR_IRQS_LEGACY + 57)
-#define MX1_TIM2_INT            (NR_IRQS_LEGACY + 58)
-#define MX1_TIM1_INT            (NR_IRQS_LEGACY + 59)
-#define MX1_DMA_ERR             (NR_IRQS_LEGACY + 60)
-#define MX1_DMA_INT             (NR_IRQS_LEGACY + 61)
-#define MX1_GPIO_INT_PORTD      (NR_IRQS_LEGACY + 62)
-#define MX1_WDT_INT             (NR_IRQS_LEGACY + 63)
-
-/* DMA */
-#define MX1_DMA_REQ_UART3_T             2
-#define MX1_DMA_REQ_UART3_R             3
-#define MX1_DMA_REQ_SSI2_T              4
-#define MX1_DMA_REQ_SSI2_R              5
-#define MX1_DMA_REQ_CSI_STAT            6
-#define MX1_DMA_REQ_CSI_R               7
-#define MX1_DMA_REQ_MSHC                8
-#define MX1_DMA_REQ_DSPA_DCT_DOUT       9
-#define MX1_DMA_REQ_DSPA_DCT_DIN        10
-#define MX1_DMA_REQ_DSPA_MAC            11
-#define MX1_DMA_REQ_EXT                 12
-#define MX1_DMA_REQ_SDHC                13
-#define MX1_DMA_REQ_SPI1_R              14
-#define MX1_DMA_REQ_SPI1_T              15
-#define MX1_DMA_REQ_SSI_T               16
-#define MX1_DMA_REQ_SSI_R               17
-#define MX1_DMA_REQ_ASP_DAC             18
-#define MX1_DMA_REQ_ASP_ADC             19
-#define MX1_DMA_REQ_USP_EP(x)           (20 + (x))
-#define MX1_DMA_REQ_SPI2_R              26
-#define MX1_DMA_REQ_SPI2_T              27
-#define MX1_DMA_REQ_UART2_T             28
-#define MX1_DMA_REQ_UART2_R             29
-#define MX1_DMA_REQ_UART1_T             30
-#define MX1_DMA_REQ_UART1_R             31
-
-/*
- * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
- * to not break drivers/usb/gadget/imx_udc.  Should go
- * away after this driver uses the new name.
- */
-#define USBD_INT0               MX1_INT_USBD0
-
-#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/mach-imx/mx21.h b/arch/arm/mach-imx/mx21.h
deleted file mode 100644
index 468738aa997..00000000000
--- a/arch/arm/mach-imx/mx21.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
- *
- * This contains i.MX21-specific hardware definitions. For those
- * hardware pieces that are common between i.MX21 and i.MX27, have a
- * look at mx2x.h.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MX21_H__
-#define __MACH_MX21_H__
-
-#define MX21_AIPI_BASE_ADDR             0x10000000
-#define MX21_AIPI_SIZE                  SZ_1M
-#define MX21_DMA_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x01000)
-#define MX21_WDOG_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x02000)
-#define MX21_GPT1_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x03000)
-#define MX21_GPT2_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x04000)
-#define MX21_GPT3_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x05000)
-#define MX21_PWM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x06000)
-#define MX21_RTC_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x07000)
-#define MX21_KPP_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x08000)
-#define MX21_OWIRE_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x09000)
-#define MX21_UART1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0a000)
-#define MX21_UART2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0b000)
-#define MX21_UART3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0c000)
-#define MX21_UART4_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0d000)
-#define MX21_CSPI1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0e000)
-#define MX21_CSPI2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0f000)
-#define MX21_SSI1_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x10000)
-#define MX21_SSI2_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x11000)
-#define MX21_I2C_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x12000)
-#define MX21_SDHC1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x13000)
-#define MX21_SDHC2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x14000)
-#define MX21_GPIO_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x15000)
-#define MX21_GPIO1_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x000)
-#define MX21_GPIO2_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x100)
-#define MX21_GPIO3_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x200)
-#define MX21_GPIO4_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x300)
-#define MX21_GPIO5_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x400)
-#define MX21_GPIO6_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x500)
-#define MX21_AUDMUX_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x16000)
-#define MX21_CSPI3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x17000)
-#define MX21_LCDC_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x21000)
-#define MX21_SLCDC_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x22000)
-#define MX21_USBOTG_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x24000)
-#define MX21_EMMA_PP_BASE_ADDR                  (MX21_AIPI_BASE_ADDR + 0x26000)
-#define MX21_EMMA_PRP_BASE_ADDR                 (MX21_AIPI_BASE_ADDR + 0x26400)
-#define MX21_CCM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x27000)
-#define MX21_SYSCTRL_BASE_ADDR                  (MX21_AIPI_BASE_ADDR + 0x27800)
-#define MX21_JAM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x3e000)
-#define MX21_MAX_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX21_AVIC_BASE_ADDR             0x10040000
-
-#define MX21_SAHB1_BASE_ADDR            0x80000000
-#define MX21_SAHB1_SIZE                 SZ_1M
-#define MX21_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* Memory regions and CS */
-#define MX21_SDRAM_BASE_ADDR            0xc0000000
-#define MX21_CSD1_BASE_ADDR             0xc4000000
-
-#define MX21_CS0_BASE_ADDR              0xc8000000
-#define MX21_CS1_BASE_ADDR              0xcc000000
-#define MX21_CS2_BASE_ADDR              0xd0000000
-#define MX21_CS3_BASE_ADDR              0xd1000000
-#define MX21_CS4_BASE_ADDR              0xd2000000
-#define MX21_PCMCIA_MEM_BASE_ADDR       0xd4000000
-#define MX21_CS5_BASE_ADDR              0xdd000000
-
-/* NAND, SDRAM, WEIM etc controllers */
-#define MX21_X_MEMC_BASE_ADDR           0xdf000000
-#define MX21_X_MEMC_SIZE                SZ_256K
-
-#define MX21_SDRAMC_BASE_ADDR           (MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define MX21_EIM_BASE_ADDR              (MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define MX21_PCMCIA_CTL_BASE_ADDR       (MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define MX21_NFC_BASE_ADDR              (MX21_X_MEMC_BASE_ADDR + 0x3000)
-
-#define MX21_IRAM_BASE_ADDR             0xffffe800      /* internal ram */
-
-#define MX21_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX21_IO_ADDRESS(x)              IOMEM(MX21_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX21_INT_CSPI3          (NR_IRQS_LEGACY + 6)
-#define MX21_INT_GPIO           (NR_IRQS_LEGACY + 8)
-#define MX21_INT_FIRI           (NR_IRQS_LEGACY + 9)
-#define MX21_INT_SDHC2          (NR_IRQS_LEGACY + 10)
-#define MX21_INT_SDHC1          (NR_IRQS_LEGACY + 11)
-#define MX21_INT_I2C            (NR_IRQS_LEGACY + 12)
-#define MX21_INT_SSI2           (NR_IRQS_LEGACY + 13)
-#define MX21_INT_SSI1           (NR_IRQS_LEGACY + 14)
-#define MX21_INT_CSPI2          (NR_IRQS_LEGACY + 15)
-#define MX21_INT_CSPI1          (NR_IRQS_LEGACY + 16)
-#define MX21_INT_UART4          (NR_IRQS_LEGACY + 17)
-#define MX21_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX21_INT_UART2          (NR_IRQS_LEGACY + 19)
-#define MX21_INT_UART1          (NR_IRQS_LEGACY + 20)
-#define MX21_INT_KPP            (NR_IRQS_LEGACY + 21)
-#define MX21_INT_RTC            (NR_IRQS_LEGACY + 22)
-#define MX21_INT_PWM            (NR_IRQS_LEGACY + 23)
-#define MX21_INT_GPT3           (NR_IRQS_LEGACY + 24)
-#define MX21_INT_GPT2           (NR_IRQS_LEGACY + 25)
-#define MX21_INT_GPT1           (NR_IRQS_LEGACY + 26)
-#define MX21_INT_WDOG           (NR_IRQS_LEGACY + 27)
-#define MX21_INT_PCMCIA         (NR_IRQS_LEGACY + 28)
-#define MX21_INT_NFC            (NR_IRQS_LEGACY + 29)
-#define MX21_INT_BMI            (NR_IRQS_LEGACY + 30)
-#define MX21_INT_CSI            (NR_IRQS_LEGACY + 31)
-#define MX21_INT_DMACH0         (NR_IRQS_LEGACY + 32)
-#define MX21_INT_DMACH1         (NR_IRQS_LEGACY + 33)
-#define MX21_INT_DMACH2         (NR_IRQS_LEGACY + 34)
-#define MX21_INT_DMACH3         (NR_IRQS_LEGACY + 35)
-#define MX21_INT_DMACH4         (NR_IRQS_LEGACY + 36)
-#define MX21_INT_DMACH5         (NR_IRQS_LEGACY + 37)
-#define MX21_INT_DMACH6         (NR_IRQS_LEGACY + 38)
-#define MX21_INT_DMACH7         (NR_IRQS_LEGACY + 39)
-#define MX21_INT_DMACH8         (NR_IRQS_LEGACY + 40)
-#define MX21_INT_DMACH9         (NR_IRQS_LEGACY + 41)
-#define MX21_INT_DMACH10        (NR_IRQS_LEGACY + 42)
-#define MX21_INT_DMACH11        (NR_IRQS_LEGACY + 43)
-#define MX21_INT_DMACH12        (NR_IRQS_LEGACY + 44)
-#define MX21_INT_DMACH13        (NR_IRQS_LEGACY + 45)
-#define MX21_INT_DMACH14        (NR_IRQS_LEGACY + 46)
-#define MX21_INT_DMACH15        (NR_IRQS_LEGACY + 47)
-#define MX21_INT_EMMAENC        (NR_IRQS_LEGACY + 49)
-#define MX21_INT_EMMADEC        (NR_IRQS_LEGACY + 50)
-#define MX21_INT_EMMAPRP        (NR_IRQS_LEGACY + 51)
-#define MX21_INT_EMMAPP         (NR_IRQS_LEGACY + 52)
-#define MX21_INT_USBWKUP        (NR_IRQS_LEGACY + 53)
-#define MX21_INT_USBDMA         (NR_IRQS_LEGACY + 54)
-#define MX21_INT_USBHOST        (NR_IRQS_LEGACY + 55)
-#define MX21_INT_USBFUNC        (NR_IRQS_LEGACY + 56)
-#define MX21_INT_USBMNP         (NR_IRQS_LEGACY + 57)
-#define MX21_INT_USBCTRL        (NR_IRQS_LEGACY + 58)
-#define MX21_INT_SLCDC          (NR_IRQS_LEGACY + 60)
-#define MX21_INT_LCDC           (NR_IRQS_LEGACY + 61)
-
-/* fixed DMA request numbers */
-#define MX21_DMA_REQ_CSPI3_RX   1
-#define MX21_DMA_REQ_CSPI3_TX   2
-#define MX21_DMA_REQ_EXT        3
-#define MX21_DMA_REQ_FIRI_RX    4
-#define MX21_DMA_REQ_SDHC2      6
-#define MX21_DMA_REQ_SDHC1      7
-#define MX21_DMA_REQ_SSI2_RX0   8
-#define MX21_DMA_REQ_SSI2_TX0   9
-#define MX21_DMA_REQ_SSI2_RX1   10
-#define MX21_DMA_REQ_SSI2_TX1   11
-#define MX21_DMA_REQ_SSI1_RX0   12
-#define MX21_DMA_REQ_SSI1_TX0   13
-#define MX21_DMA_REQ_SSI1_RX1   14
-#define MX21_DMA_REQ_SSI1_TX1   15
-#define MX21_DMA_REQ_CSPI2_RX   16
-#define MX21_DMA_REQ_CSPI2_TX   17
-#define MX21_DMA_REQ_CSPI1_RX   18
-#define MX21_DMA_REQ_CSPI1_TX   19
-#define MX21_DMA_REQ_UART4_RX   20
-#define MX21_DMA_REQ_UART4_TX   21
-#define MX21_DMA_REQ_UART3_RX   22
-#define MX21_DMA_REQ_UART3_TX   23
-#define MX21_DMA_REQ_UART2_RX   24
-#define MX21_DMA_REQ_UART2_TX   25
-#define MX21_DMA_REQ_UART1_RX   26
-#define MX21_DMA_REQ_UART1_TX   27
-#define MX21_DMA_REQ_BMI_TX     28
-#define MX21_DMA_REQ_BMI_RX     29
-#define MX21_DMA_REQ_CSI_STAT   30
-#define MX21_DMA_REQ_CSI_RX     31
-
-#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h
deleted file mode 100644
index ec466400a20..00000000000
--- a/arch/arm/mach-imx/mx25.h
+++ /dev/null
@@ -1,117 +0,0 @@
-#ifndef __MACH_MX25_H__
-#define __MACH_MX25_H__
-
-#define MX25_AIPS1_BASE_ADDR            0x43f00000
-#define MX25_AIPS1_SIZE                 SZ_1M
-#define MX25_AIPS2_BASE_ADDR            0x53f00000
-#define MX25_AIPS2_SIZE                 SZ_1M
-#define MX25_AVIC_BASE_ADDR             0x68000000
-#define MX25_AVIC_SIZE                  SZ_1M
-
-#define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
-#define MX25_I2C3_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x84000)
-#define MX25_CAN1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x88000)
-#define MX25_CAN2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x8c000)
-#define MX25_I2C2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x98000)
-#define MX25_CSPI1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0xa4000)
-#define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
-
-#define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
-#define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
-#define MX25_GPIO4_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0x9c000)
-#define MX25_PWM2_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa0000)
-#define MX25_GPIO3_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xa4000)
-#define MX25_PWM3_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa8000)
-#define MX25_PWM4_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xc8000)
-#define MX25_GPIO1_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xcc000)
-#define MX25_GPIO2_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xd0000)
-#define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
-#define MX25_PWM1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xe0000)
-
-#define MX25_UART1_BASE_ADDR            0x43f90000
-#define MX25_UART2_BASE_ADDR            0x43f94000
-#define MX25_AUDMUX_BASE_ADDR           0x43fb0000
-#define MX25_UART3_BASE_ADDR            0x5000c000
-#define MX25_UART4_BASE_ADDR            0x50008000
-#define MX25_UART5_BASE_ADDR            0x5002c000
-
-#define MX25_CSPI3_BASE_ADDR            0x50004000
-#define MX25_CSPI2_BASE_ADDR            0x50010000
-#define MX25_FEC_BASE_ADDR              0x50038000
-#define MX25_SSI2_BASE_ADDR             0x50014000
-#define MX25_SSI1_BASE_ADDR             0x50034000
-#define MX25_NFC_BASE_ADDR              0xbb000000
-#define MX25_IIM_BASE_ADDR              0x53ff0000
-#define MX25_DRYICE_BASE_ADDR           0x53ffc000
-#define MX25_ESDHC1_BASE_ADDR           0x53fb4000
-#define MX25_ESDHC2_BASE_ADDR           0x53fb8000
-#define MX25_LCDC_BASE_ADDR             0x53fbc000
-#define MX25_KPP_BASE_ADDR              0x43fa8000
-#define MX25_SDMA_BASE_ADDR             0x53fd4000
-#define MX25_USB_BASE_ADDR              0x53ff4000
-#define MX25_USB_OTG_BASE_ADDR                  (MX25_USB_BASE_ADDR + 0x0000)
-/*
- * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
- * for the host controller.  Early documentation drafts specified 0x400 and
- * Freescale internal sources confirm only the latter value to work.
- */
-#define MX25_USB_HS_BASE_ADDR                   (MX25_USB_BASE_ADDR + 0x0400)
-#define MX25_CSI_BASE_ADDR              0x53ff8000
-
-#define MX25_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX25_IO_ADDRESS(x)              IOMEM(MX25_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX25_INT_CSPI3          (NR_IRQS_LEGACY + 0)
-#define MX25_INT_I2C1           (NR_IRQS_LEGACY + 3)
-#define MX25_INT_I2C2           (NR_IRQS_LEGACY + 4)
-#define MX25_INT_UART4          (NR_IRQS_LEGACY + 5)
-#define MX25_INT_ESDHC2         (NR_IRQS_LEGACY + 8)
-#define MX25_INT_ESDHC1         (NR_IRQS_LEGACY + 9)
-#define MX25_INT_I2C3           (NR_IRQS_LEGACY + 10)
-#define MX25_INT_SSI2           (NR_IRQS_LEGACY + 11)
-#define MX25_INT_SSI1           (NR_IRQS_LEGACY + 12)
-#define MX25_INT_CSPI2          (NR_IRQS_LEGACY + 13)
-#define MX25_INT_CSPI1          (NR_IRQS_LEGACY + 14)
-#define MX25_INT_GPIO3          (NR_IRQS_LEGACY + 16)
-#define MX25_INT_CSI            (NR_IRQS_LEGACY + 17)
-#define MX25_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX25_INT_GPIO4          (NR_IRQS_LEGACY + 23)
-#define MX25_INT_KPP            (NR_IRQS_LEGACY + 24)
-#define MX25_INT_DRYICE         (NR_IRQS_LEGACY + 25)
-#define MX25_INT_PWM1           (NR_IRQS_LEGACY + 26)
-#define MX25_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX25_INT_NFC            (NR_IRQS_LEGACY + 33)
-#define MX25_INT_SDMA           (NR_IRQS_LEGACY + 34)
-#define MX25_INT_USB_HS         (NR_IRQS_LEGACY + 35)
-#define MX25_INT_PWM2           (NR_IRQS_LEGACY + 36)
-#define MX25_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
-#define MX25_INT_LCDC           (NR_IRQS_LEGACY + 39)
-#define MX25_INT_UART5          (NR_IRQS_LEGACY + 40)
-#define MX25_INT_PWM3           (NR_IRQS_LEGACY + 41)
-#define MX25_INT_PWM4           (NR_IRQS_LEGACY + 42)
-#define MX25_INT_CAN1           (NR_IRQS_LEGACY + 43)
-#define MX25_INT_CAN2           (NR_IRQS_LEGACY + 44)
-#define MX25_INT_UART1          (NR_IRQS_LEGACY + 45)
-#define MX25_INT_GPIO2          (NR_IRQS_LEGACY + 51)
-#define MX25_INT_GPIO1          (NR_IRQS_LEGACY + 52)
-#define MX25_INT_GPT1           (NR_IRQS_LEGACY + 54)
-#define MX25_INT_FEC            (NR_IRQS_LEGACY + 57)
-
-#define MX25_DMA_REQ_SSI2_RX1   22
-#define MX25_DMA_REQ_SSI2_TX1   23
-#define MX25_DMA_REQ_SSI2_RX0   24
-#define MX25_DMA_REQ_SSI2_TX0   25
-#define MX25_DMA_REQ_SSI1_RX1   26
-#define MX25_DMA_REQ_SSI1_TX1   27
-#define MX25_DMA_REQ_SSI1_RX0   28
-#define MX25_DMA_REQ_SSI1_TX0   29
-
-#ifndef __ASSEMBLY__
-extern int mx25_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h
deleted file mode 100644
index e074616d54c..00000000000
--- a/arch/arm/mach-imx/mx27.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This contains i.MX27-specific hardware definitions. For those
- * hardware pieces that are common between i.MX21 and i.MX27, have a
- * look at mx2x.h.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MX27_H__
-#define __MACH_MX27_H__
-
-#define MX27_AIPI_BASE_ADDR             0x10000000
-#define MX27_AIPI_SIZE                  SZ_1M
-#define MX27_DMA_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x01000)
-#define MX27_WDOG_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x02000)
-#define MX27_GPT1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x03000)
-#define MX27_GPT2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x04000)
-#define MX27_GPT3_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x05000)
-#define MX27_PWM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x06000)
-#define MX27_RTC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x07000)
-#define MX27_KPP_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x08000)
-#define MX27_OWIRE_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x09000)
-#define MX27_UART1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0a000)
-#define MX27_UART2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0b000)
-#define MX27_UART3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0c000)
-#define MX27_UART4_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0d000)
-#define MX27_CSPI1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0e000)
-#define MX27_CSPI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0f000)
-#define MX27_SSI1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x10000)
-#define MX27_SSI2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x12000)
-#define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
-#define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
-#define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
-#define MX27_GPIO1_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x000)
-#define MX27_GPIO2_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x100)
-#define MX27_GPIO3_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x200)
-#define MX27_GPIO4_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x300)
-#define MX27_GPIO5_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x400)
-#define MX27_GPIO6_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x500)
-#define MX27_AUDMUX_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x16000)
-#define MX27_CSPI3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x17000)
-#define MX27_MSHC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT4_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT5_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1a000)
-#define MX27_UART5_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1b000)
-#define MX27_UART6_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1c000)
-#define MX27_I2C2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1d000)
-#define MX27_SDHC3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1e000)
-#define MX27_GPT6_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1f000)
-#define MX27_LCDC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x21000)
-#define MX27_SLCDC_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x22000)
-#define MX27_VPU_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x23000)
-#define MX27_USB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x24000)
-#define MX27_USB_OTG_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0000)
-#define MX27_USB_HS1_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0200)
-#define MX27_USB_HS2_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0400)
-#define MX27_SAHARA_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x25000)
-#define MX27_EMMAPP_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x26000)
-#define MX27_EMMAPRP_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x26400)
-#define MX27_CCM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x27000)
-#define MX27_SYSCTRL_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x27800)
-#define MX27_IIM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x28000)
-#define MX27_RTIC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x2a000)
-#define MX27_FEC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2b000)
-#define MX27_SCC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2c000)
-#define MX27_ETB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3b000)
-#define MX27_ETB_RAM_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x3c000)
-#define MX27_JAM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3e000)
-#define MX27_MAX_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX27_AVIC_BASE_ADDR             0x10040000
-
-/* ROM patch */
-#define MX27_ROMP_BASE_ADDR             0x10041000
-
-#define MX27_SAHB1_BASE_ADDR            0x80000000
-#define MX27_SAHB1_SIZE                 SZ_1M
-#define MX27_CSI_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x0000)
-#define MX27_ATA_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x1000)
-
-/* Memory regions and CS */
-#define MX27_SDRAM_BASE_ADDR            0xa0000000
-#define MX27_CSD1_BASE_ADDR             0xb0000000
-
-#define MX27_CS0_BASE_ADDR              0xc0000000
-#define MX27_CS1_BASE_ADDR              0xc8000000
-#define MX27_CS2_BASE_ADDR              0xd0000000
-#define MX27_CS3_BASE_ADDR              0xd2000000
-#define MX27_CS4_BASE_ADDR              0xd4000000
-#define MX27_CS5_BASE_ADDR              0xd6000000
-
-/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define MX27_X_MEMC_BASE_ADDR           0xd8000000
-#define MX27_X_MEMC_SIZE                SZ_1M
-#define MX27_NFC_BASE_ADDR                      (MX27_X_MEMC_BASE_ADDR)
-#define MX27_SDRAMC_BASE_ADDR                   (MX27_X_MEMC_BASE_ADDR + 0x1000)
-#define MX27_WEIM_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x2000)
-#define MX27_M3IF_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x3000)
-#define MX27_PCMCIA_CTL_BASE_ADDR               (MX27_X_MEMC_BASE_ADDR + 0x4000)
-
-#define MX27_WEIM_CSCRx_BASE_ADDR(cs)   (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX27_WEIM_CSCRxU(cs)                    (MX27_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX27_WEIM_CSCRxL(cs)                    (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX27_WEIM_CSCRxA(cs)                    (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX27_PCMCIA_MEM_BASE_ADDR       0xdc000000
-
-/* IRAM */
-#define MX27_IRAM_BASE_ADDR             0xffff4c00      /* internal ram */
-
-#define MX27_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX27_IO_ADDRESS(x)              IOMEM(MX27_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX27_INT_I2C2           (NR_IRQS_LEGACY + 1)
-#define MX27_INT_GPT6           (NR_IRQS_LEGACY + 2)
-#define MX27_INT_GPT5           (NR_IRQS_LEGACY + 3)
-#define MX27_INT_GPT4           (NR_IRQS_LEGACY + 4)
-#define MX27_INT_RTIC           (NR_IRQS_LEGACY + 5)
-#define MX27_INT_CSPI3          (NR_IRQS_LEGACY + 6)
-#define MX27_INT_SDHC           (NR_IRQS_LEGACY + 7)
-#define MX27_INT_GPIO           (NR_IRQS_LEGACY + 8)
-#define MX27_INT_SDHC3          (NR_IRQS_LEGACY + 9)
-#define MX27_INT_SDHC2          (NR_IRQS_LEGACY + 10)
-#define MX27_INT_SDHC1          (NR_IRQS_LEGACY + 11)
-#define MX27_INT_I2C1           (NR_IRQS_LEGACY + 12)
-#define MX27_INT_SSI2           (NR_IRQS_LEGACY + 13)
-#define MX27_INT_SSI1           (NR_IRQS_LEGACY + 14)
-#define MX27_INT_CSPI2          (NR_IRQS_LEGACY + 15)
-#define MX27_INT_CSPI1          (NR_IRQS_LEGACY + 16)
-#define MX27_INT_UART4          (NR_IRQS_LEGACY + 17)
-#define MX27_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX27_INT_UART2          (NR_IRQS_LEGACY + 19)
-#define MX27_INT_UART1          (NR_IRQS_LEGACY + 20)
-#define MX27_INT_KPP            (NR_IRQS_LEGACY + 21)
-#define MX27_INT_RTC            (NR_IRQS_LEGACY + 22)
-#define MX27_INT_PWM            (NR_IRQS_LEGACY + 23)
-#define MX27_INT_GPT3           (NR_IRQS_LEGACY + 24)
-#define MX27_INT_GPT2           (NR_IRQS_LEGACY + 25)
-#define MX27_INT_GPT1           (NR_IRQS_LEGACY + 26)
-#define MX27_INT_WDOG           (NR_IRQS_LEGACY + 27)
-#define MX27_INT_PCMCIA         (NR_IRQS_LEGACY + 28)
-#define MX27_INT_NFC            (NR_IRQS_LEGACY + 29)
-#define MX27_INT_ATA            (NR_IRQS_LEGACY + 30)
-#define MX27_INT_CSI            (NR_IRQS_LEGACY + 31)
-#define MX27_INT_DMACH0         (NR_IRQS_LEGACY + 32)
-#define MX27_INT_DMACH1         (NR_IRQS_LEGACY + 33)
-#define MX27_INT_DMACH2         (NR_IRQS_LEGACY + 34)
-#define MX27_INT_DMACH3         (NR_IRQS_LEGACY + 35)
-#define MX27_INT_DMACH4         (NR_IRQS_LEGACY + 36)
-#define MX27_INT_DMACH5         (NR_IRQS_LEGACY + 37)
-#define MX27_INT_DMACH6         (NR_IRQS_LEGACY + 38)
-#define MX27_INT_DMACH7         (NR_IRQS_LEGACY + 39)
-#define MX27_INT_DMACH8         (NR_IRQS_LEGACY + 40)
-#define MX27_INT_DMACH9         (NR_IRQS_LEGACY + 41)
-#define MX27_INT_DMACH10        (NR_IRQS_LEGACY + 42)
-#define MX27_INT_DMACH11        (NR_IRQS_LEGACY + 43)
-#define MX27_INT_DMACH12        (NR_IRQS_LEGACY + 44)
-#define MX27_INT_DMACH13        (NR_IRQS_LEGACY + 45)
-#define MX27_INT_DMACH14        (NR_IRQS_LEGACY + 46)
-#define MX27_INT_DMACH15        (NR_IRQS_LEGACY + 47)
-#define MX27_INT_UART6          (NR_IRQS_LEGACY + 48)
-#define MX27_INT_UART5          (NR_IRQS_LEGACY + 49)
-#define MX27_INT_FEC            (NR_IRQS_LEGACY + 50)
-#define MX27_INT_EMMAPRP        (NR_IRQS_LEGACY + 51)
-#define MX27_INT_EMMAPP         (NR_IRQS_LEGACY + 52)
-#define MX27_INT_VPU            (NR_IRQS_LEGACY + 53)
-#define MX27_INT_USB_HS1        (NR_IRQS_LEGACY + 54)
-#define MX27_INT_USB_HS2        (NR_IRQS_LEGACY + 55)
-#define MX27_INT_USB_OTG        (NR_IRQS_LEGACY + 56)
-#define MX27_INT_SCC_SMN        (NR_IRQS_LEGACY + 57)
-#define MX27_INT_SCC_SCM        (NR_IRQS_LEGACY + 58)
-#define MX27_INT_SAHARA         (NR_IRQS_LEGACY + 59)
-#define MX27_INT_SLCDC          (NR_IRQS_LEGACY + 60)
-#define MX27_INT_LCDC           (NR_IRQS_LEGACY + 61)
-#define MX27_INT_IIM            (NR_IRQS_LEGACY + 62)
-#define MX27_INT_CCM            (NR_IRQS_LEGACY + 63)
-
-/* fixed DMA request numbers */
-#define MX27_DMA_REQ_CSPI3_RX   1
-#define MX27_DMA_REQ_CSPI3_TX   2
-#define MX27_DMA_REQ_EXT        3
-#define MX27_DMA_REQ_MSHC       4
-#define MX27_DMA_REQ_SDHC2      6
-#define MX27_DMA_REQ_SDHC1      7
-#define MX27_DMA_REQ_SSI2_RX0   8
-#define MX27_DMA_REQ_SSI2_TX0   9
-#define MX27_DMA_REQ_SSI2_RX1   10
-#define MX27_DMA_REQ_SSI2_TX1   11
-#define MX27_DMA_REQ_SSI1_RX0   12
-#define MX27_DMA_REQ_SSI1_TX0   13
-#define MX27_DMA_REQ_SSI1_RX1   14
-#define MX27_DMA_REQ_SSI1_TX1   15
-#define MX27_DMA_REQ_CSPI2_RX   16
-#define MX27_DMA_REQ_CSPI2_TX   17
-#define MX27_DMA_REQ_CSPI1_RX   18
-#define MX27_DMA_REQ_CSPI1_TX   19
-#define MX27_DMA_REQ_UART4_RX   20
-#define MX27_DMA_REQ_UART4_TX   21
-#define MX27_DMA_REQ_UART3_RX   22
-#define MX27_DMA_REQ_UART3_TX   23
-#define MX27_DMA_REQ_UART2_RX   24
-#define MX27_DMA_REQ_UART2_TX   25
-#define MX27_DMA_REQ_UART1_RX   26
-#define MX27_DMA_REQ_UART1_TX   27
-#define MX27_DMA_REQ_ATA_TX     28
-#define MX27_DMA_REQ_ATA_RCV    29
-#define MX27_DMA_REQ_CSI_STAT   30
-#define MX27_DMA_REQ_CSI_RX     31
-#define MX27_DMA_REQ_UART5_TX   32
-#define MX27_DMA_REQ_UART5_RX   33
-#define MX27_DMA_REQ_UART6_TX   34
-#define MX27_DMA_REQ_UART6_RX   35
-#define MX27_DMA_REQ_SDHC3      36
-#define MX27_DMA_REQ_NFC        37
-
-#ifndef __ASSEMBLY__
-extern int mx27_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/mx2x.h b/arch/arm/mach-imx/mx2x.h
deleted file mode 100644
index 11642f5b224..00000000000
--- a/arch/arm/mach-imx/mx2x.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This contains hardware definitions that are common between i.MX21 and
- * i.MX27.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MX2x_H__
-#define __MACH_MX2x_H__
-
-/* The following addresses are common between i.MX21 and i.MX27 */
-
-/* Register offsets */
-#define MX2x_AIPI_BASE_ADDR             0x10000000
-#define MX2x_AIPI_SIZE                  SZ_1M
-#define MX2x_DMA_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x01000)
-#define MX2x_WDOG_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x02000)
-#define MX2x_GPT1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x03000)
-#define MX2x_GPT2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x04000)
-#define MX2x_GPT3_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x05000)
-#define MX2x_PWM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x06000)
-#define MX2x_RTC_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x07000)
-#define MX2x_KPP_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x08000)
-#define MX2x_OWIRE_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x09000)
-#define MX2x_UART1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0a000)
-#define MX2x_UART2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0b000)
-#define MX2x_UART3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0c000)
-#define MX2x_UART4_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0d000)
-#define MX2x_CSPI1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0e000)
-#define MX2x_CSPI2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0f000)
-#define MX2x_SSI1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x10000)
-#define MX2x_SSI2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x11000)
-#define MX2x_I2C_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x12000)
-#define MX2x_SDHC1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x13000)
-#define MX2x_SDHC2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x14000)
-#define MX2x_GPIO_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x15000)
-#define MX2x_AUDMUX_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x16000)
-#define MX2x_CSPI3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x17000)
-#define MX2x_LCDC_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x21000)
-#define MX2x_SLCDC_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x22000)
-#define MX2x_USBOTG_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x24000)
-#define MX2x_EMMA_PP_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x26000)
-#define MX2x_EMMA_PRP_BASE_ADDR                 (MX2x_AIPI_BASE_ADDR + 0x26400)
-#define MX2x_CCM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x27000)
-#define MX2x_SYSCTRL_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x27800)
-#define MX2x_JAM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3e000)
-#define MX2x_MAX_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX2x_AVIC_BASE_ADDR             0x10040000
-
-#define MX2x_SAHB1_BASE_ADDR            0x80000000
-#define MX2x_SAHB1_SIZE                 SZ_1M
-#define MX2x_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX2x_INT_CSPI3          (NR_IRQS_LEGACY + 6)
-#define MX2x_INT_GPIO           (NR_IRQS_LEGACY + 8)
-#define MX2x_INT_SDHC2          (NR_IRQS_LEGACY + 10)
-#define MX2x_INT_SDHC1          (NR_IRQS_LEGACY + 11)
-#define MX2x_INT_I2C            (NR_IRQS_LEGACY + 12)
-#define MX2x_INT_SSI2           (NR_IRQS_LEGACY + 13)
-#define MX2x_INT_SSI1           (NR_IRQS_LEGACY + 14)
-#define MX2x_INT_CSPI2          (NR_IRQS_LEGACY + 15)
-#define MX2x_INT_CSPI1          (NR_IRQS_LEGACY + 16)
-#define MX2x_INT_UART4          (NR_IRQS_LEGACY + 17)
-#define MX2x_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX2x_INT_UART2          (NR_IRQS_LEGACY + 19)
-#define MX2x_INT_UART1          (NR_IRQS_LEGACY + 20)
-#define MX2x_INT_KPP            (NR_IRQS_LEGACY + 21)
-#define MX2x_INT_RTC            (NR_IRQS_LEGACY + 22)
-#define MX2x_INT_PWM            (NR_IRQS_LEGACY + 23)
-#define MX2x_INT_GPT3           (NR_IRQS_LEGACY + 24)
-#define MX2x_INT_GPT2           (NR_IRQS_LEGACY + 25)
-#define MX2x_INT_GPT1           (NR_IRQS_LEGACY + 26)
-#define MX2x_INT_WDOG           (NR_IRQS_LEGACY + 27)
-#define MX2x_INT_PCMCIA         (NR_IRQS_LEGACY + 28)
-#define MX2x_INT_NANDFC         (NR_IRQS_LEGACY + 29)
-#define MX2x_INT_CSI            (NR_IRQS_LEGACY + 31)
-#define MX2x_INT_DMACH0         (NR_IRQS_LEGACY + 32)
-#define MX2x_INT_DMACH1         (NR_IRQS_LEGACY + 33)
-#define MX2x_INT_DMACH2         (NR_IRQS_LEGACY + 34)
-#define MX2x_INT_DMACH3         (NR_IRQS_LEGACY + 35)
-#define MX2x_INT_DMACH4         (NR_IRQS_LEGACY + 36)
-#define MX2x_INT_DMACH5         (NR_IRQS_LEGACY + 37)
-#define MX2x_INT_DMACH6         (NR_IRQS_LEGACY + 38)
-#define MX2x_INT_DMACH7         (NR_IRQS_LEGACY + 39)
-#define MX2x_INT_DMACH8         (NR_IRQS_LEGACY + 40)
-#define MX2x_INT_DMACH9         (NR_IRQS_LEGACY + 41)
-#define MX2x_INT_DMACH10        (NR_IRQS_LEGACY + 42)
-#define MX2x_INT_DMACH11        (NR_IRQS_LEGACY + 43)
-#define MX2x_INT_DMACH12        (NR_IRQS_LEGACY + 44)
-#define MX2x_INT_DMACH13        (NR_IRQS_LEGACY + 45)
-#define MX2x_INT_DMACH14        (NR_IRQS_LEGACY + 46)
-#define MX2x_INT_DMACH15        (NR_IRQS_LEGACY + 47)
-#define MX2x_INT_EMMAPRP        (NR_IRQS_LEGACY + 51)
-#define MX2x_INT_EMMAPP         (NR_IRQS_LEGACY + 52)
-#define MX2x_INT_SLCDC          (NR_IRQS_LEGACY + 60)
-#define MX2x_INT_LCDC           (NR_IRQS_LEGACY + 61)
-
-/* fixed DMA request numbers */
-#define MX2x_DMA_REQ_CSPI3_RX   1
-#define MX2x_DMA_REQ_CSPI3_TX   2
-#define MX2x_DMA_REQ_EXT        3
-#define MX2x_DMA_REQ_SDHC2      6
-#define MX2x_DMA_REQ_SDHC1      7
-#define MX2x_DMA_REQ_SSI2_RX0   8
-#define MX2x_DMA_REQ_SSI2_TX0   9
-#define MX2x_DMA_REQ_SSI2_RX1   10
-#define MX2x_DMA_REQ_SSI2_TX1   11
-#define MX2x_DMA_REQ_SSI1_RX0   12
-#define MX2x_DMA_REQ_SSI1_TX0   13
-#define MX2x_DMA_REQ_SSI1_RX1   14
-#define MX2x_DMA_REQ_SSI1_TX1   15
-#define MX2x_DMA_REQ_CSPI2_RX   16
-#define MX2x_DMA_REQ_CSPI2_TX   17
-#define MX2x_DMA_REQ_CSPI1_RX   18
-#define MX2x_DMA_REQ_CSPI1_TX   19
-#define MX2x_DMA_REQ_UART4_RX   20
-#define MX2x_DMA_REQ_UART4_TX   21
-#define MX2x_DMA_REQ_UART3_RX   22
-#define MX2x_DMA_REQ_UART3_TX   23
-#define MX2x_DMA_REQ_UART2_RX   24
-#define MX2x_DMA_REQ_UART2_TX   25
-#define MX2x_DMA_REQ_UART1_RX   26
-#define MX2x_DMA_REQ_UART1_TX   27
-#define MX2x_DMA_REQ_CSI_STAT   30
-#define MX2x_DMA_REQ_CSI_RX     31
-
-#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h
deleted file mode 100644
index ee9b1f9215d..00000000000
--- a/arch/arm/mach-imx/mx31.h
+++ /dev/null
@@ -1,196 +0,0 @@
-#ifndef __MACH_MX31_H__
-#define __MACH_MX31_H__
-
-/*
- * IRAM
- */
-#define MX31_IRAM_BASE_ADDR             0x1ffc0000      /* internal ram */
-#define MX31_IRAM_SIZE                  SZ_16K
-
-#define MX31_L2CC_BASE_ADDR             0x30000000
-#define MX31_L2CC_SIZE                  SZ_1M
-
-#define MX31_AIPS1_BASE_ADDR            0x43f00000
-#define MX31_AIPS1_SIZE                 SZ_1M
-#define MX31_MAX_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x04000)
-#define MX31_EVTMON_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x08000)
-#define MX31_CLKCTL_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x0c000)
-#define MX31_ETB_SLOT4_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x10000)
-#define MX31_ETB_SLOT5_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x14000)
-#define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
-#define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_USB_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
-#define MX31_USB_OTG_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0000)
-#define MX31_USB_HS1_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0200)
-#define MX31_USB_HS2_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0400)
-#define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
-#define MX31_UART1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x90000)
-#define MX31_UART2_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x94000)
-#define MX31_I2C2_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x98000)
-#define MX31_OWIRE_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x9c000)
-#define MX31_SSI1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0xa0000)
-#define MX31_CSPI1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xa4000)
-#define MX31_KPP_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0xa8000)
-#define MX31_IOMUXC_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0xac000)
-#define MX31_UART4_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb0000)
-#define MX31_UART5_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb4000)
-#define MX31_ECT_IP1_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xb8000)
-#define MX31_ECT_IP2_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xbc000)
-
-#define MX31_SPBA0_BASE_ADDR            0x50000000
-#define MX31_SPBA0_SIZE                 SZ_1M
-#define MX31_SDHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_SDHC2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x08000)
-#define MX31_UART3_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x0c000)
-#define MX31_CSPI2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x10000)
-#define MX31_SSI2_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x14000)
-#define MX31_SIM1_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x18000)
-#define MX31_IIM_BASE_ADDR                      (MX31_SPBA0_BASE_ADDR + 0x1c000)
-#define MX31_ATA_DMA_BASE_ADDR                  (MX31_SPBA0_BASE_ADDR + 0x20000)
-#define MX31_MSHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x24000)
-#define MX31_SPBA_CTRL_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x3c000)
-
-#define MX31_AIPS2_BASE_ADDR            0x53f00000
-#define MX31_AIPS2_SIZE                 SZ_1M
-#define MX31_CCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0x80000)
-#define MX31_CSPI3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x84000)
-#define MX31_FIRI_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x8c000)
-#define MX31_GPT1_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x90000)
-#define MX31_EPIT1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x94000)
-#define MX31_EPIT2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x98000)
-#define MX31_GPIO3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xa4000)
-#define MX31_SCC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xac000)
-#define MX31_SCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xae000)
-#define MX31_SMN_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xaf000)
-#define MX31_RNGA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xb0000)
-#define MX31_IPU_CTRL_BASE_ADDR                 (MX31_AIPS2_BASE_ADDR + 0xc0000)
-#define MX31_AUDMUX_BASE_ADDR                   (MX31_AIPS2_BASE_ADDR + 0xc4000)
-#define MX31_MPEG4_ENC_BASE_ADDR                (MX31_AIPS2_BASE_ADDR + 0xc8000)
-#define MX31_GPIO1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xcc000)
-#define MX31_GPIO2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xd0000)
-#define MX31_SDMA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xd4000)
-#define MX31_RTC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xd8000)
-#define MX31_WDOG_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xdc000)
-#define MX31_PWM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xe0000)
-#define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
-
-#define MX31_ROMP_BASE_ADDR             0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT        IOMEM(0xfc500000)
-#define MX31_ROMP_SIZE                  SZ_1M
-
-#define MX31_AVIC_BASE_ADDR             0x68000000
-#define MX31_AVIC_SIZE                  SZ_1M
-
-#define MX31_IPU_MEM_BASE_ADDR          0x70000000
-#define MX31_CSD0_BASE_ADDR             0x80000000
-#define MX31_CSD1_BASE_ADDR             0x90000000
-
-#define MX31_CS0_BASE_ADDR              0xa0000000
-#define MX31_CS1_BASE_ADDR              0xa8000000
-#define MX31_CS2_BASE_ADDR              0xb0000000
-#define MX31_CS3_BASE_ADDR              0xb2000000
-
-#define MX31_CS4_BASE_ADDR              0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT         IOMEM(0xf6000000)
-#define MX31_CS4_SIZE                   SZ_32M
-
-#define MX31_CS5_BASE_ADDR              0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT         IOMEM(0xf8000000)
-#define MX31_CS5_SIZE                   SZ_32M
-
-#define MX31_X_MEMC_BASE_ADDR           0xb8000000
-#define MX31_X_MEMC_SIZE                SZ_64K
-#define MX31_NFC_BASE_ADDR                      (MX31_X_MEMC_BASE_ADDR + 0x0000)
-#define MX31_ESDCTL_BASE_ADDR                   (MX31_X_MEMC_BASE_ADDR + 0x1000)
-#define MX31_WEIM_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x2000)
-#define MX31_M3IF_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x3000)
-#define MX31_EMI_CTL_BASE_ADDR                  (MX31_X_MEMC_BASE_ADDR + 0x4000)
-#define MX31_PCMCIA_CTL_BASE_ADDR               MX31_EMI_CTL_BASE_ADDR
-
-#define MX31_WEIM_CSCRx_BASE_ADDR(cs)   (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX31_WEIM_CSCRxU(cs)                    (MX31_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX31_WEIM_CSCRxL(cs)                    (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX31_WEIM_CSCRxA(cs)                    (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX31_PCMCIA_MEM_BASE_ADDR       0xbc000000
-
-#define MX31_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX31_IO_ADDRESS(x)              IOMEM(MX31_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX31_INT_I2C3           (NR_IRQS_LEGACY + 3)
-#define MX31_INT_I2C2           (NR_IRQS_LEGACY + 4)
-#define MX31_INT_MPEG4_ENCODER  (NR_IRQS_LEGACY + 5)
-#define MX31_INT_RTIC           (NR_IRQS_LEGACY + 6)
-#define MX31_INT_FIRI           (NR_IRQS_LEGACY + 7)
-#define MX31_INT_SDHC2          (NR_IRQS_LEGACY + 8)
-#define MX31_INT_SDHC1          (NR_IRQS_LEGACY + 9)
-#define MX31_INT_I2C1           (NR_IRQS_LEGACY + 10)
-#define MX31_INT_SSI2           (NR_IRQS_LEGACY + 11)
-#define MX31_INT_SSI1           (NR_IRQS_LEGACY + 12)
-#define MX31_INT_CSPI2          (NR_IRQS_LEGACY + 13)
-#define MX31_INT_CSPI1          (NR_IRQS_LEGACY + 14)
-#define MX31_INT_ATA            (NR_IRQS_LEGACY + 15)
-#define MX31_INT_MBX            (NR_IRQS_LEGACY + 16)
-#define MX31_INT_CSPI3          (NR_IRQS_LEGACY + 17)
-#define MX31_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX31_INT_IIM            (NR_IRQS_LEGACY + 19)
-#define MX31_INT_SIM2           (NR_IRQS_LEGACY + 20)
-#define MX31_INT_SIM1           (NR_IRQS_LEGACY + 21)
-#define MX31_INT_RNGA           (NR_IRQS_LEGACY + 22)
-#define MX31_INT_EVTMON         (NR_IRQS_LEGACY + 23)
-#define MX31_INT_KPP            (NR_IRQS_LEGACY + 24)
-#define MX31_INT_RTC            (NR_IRQS_LEGACY + 25)
-#define MX31_INT_PWM            (NR_IRQS_LEGACY + 26)
-#define MX31_INT_EPIT2          (NR_IRQS_LEGACY + 27)
-#define MX31_INT_EPIT1          (NR_IRQS_LEGACY + 28)
-#define MX31_INT_GPT            (NR_IRQS_LEGACY + 29)
-#define MX31_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
-#define MX31_INT_CCM_DVFS       (NR_IRQS_LEGACY + 31)
-#define MX31_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX31_INT_NFC            (NR_IRQS_LEGACY + 33)
-#define MX31_INT_SDMA           (NR_IRQS_LEGACY + 34)
-#define MX31_INT_USB_HS1        (NR_IRQS_LEGACY + 35)
-#define MX31_INT_USB_HS2        (NR_IRQS_LEGACY + 36)
-#define MX31_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
-#define MX31_INT_MSHC1          (NR_IRQS_LEGACY + 39)
-#define MX31_INT_MSHC2          (NR_IRQS_LEGACY + 40)
-#define MX31_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
-#define MX31_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
-#define MX31_INT_UART1          (NR_IRQS_LEGACY + 45)
-#define MX31_INT_UART4          (NR_IRQS_LEGACY + 46)
-#define MX31_INT_UART5          (NR_IRQS_LEGACY + 47)
-#define MX31_INT_ECT            (NR_IRQS_LEGACY + 48)
-#define MX31_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
-#define MX31_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
-#define MX31_INT_GPIO2          (NR_IRQS_LEGACY + 51)
-#define MX31_INT_GPIO1          (NR_IRQS_LEGACY + 52)
-#define MX31_INT_CCM            (NR_IRQS_LEGACY + 53)
-#define MX31_INT_PCMCIA         (NR_IRQS_LEGACY + 54)
-#define MX31_INT_WDOG           (NR_IRQS_LEGACY + 55)
-#define MX31_INT_GPIO3          (NR_IRQS_LEGACY + 56)
-#define MX31_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
-#define MX31_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
-#define MX31_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
-#define MX31_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
-#define MX31_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
-#define MX31_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
-
-#define MX31_DMA_REQ_SDHC1      20
-#define MX31_DMA_REQ_SDHC2      21
-#define MX31_DMA_REQ_SSI2_RX1   22
-#define MX31_DMA_REQ_SSI2_TX1   23
-#define MX31_DMA_REQ_SSI2_RX0   24
-#define MX31_DMA_REQ_SSI2_TX0   25
-#define MX31_DMA_REQ_SSI1_RX1   26
-#define MX31_DMA_REQ_SSI1_TX1   27
-#define MX31_DMA_REQ_SSI1_RX0   28
-#define MX31_DMA_REQ_SSI1_TX0   29
-
-#define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
-
-#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index d4361b80c5f..7d26f766a4e 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -30,11 +30,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "board-mx31lilly.h"
-#include "common.h"
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lilly.h>
+
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
 
 /*
  * This file contains board-specific initialization routines for the
@@ -129,8 +130,7 @@ static int mxc_mmc1_init(struct device *dev,
         gpio_direction_input(gpio_det);
         gpio_direction_input(gpio_wp);
 
-        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
-                          detect_irq,
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
                           IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                           "MMC detect", data);
         if (ret)
@@ -151,7 +151,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
 {
         gpio_free(gpio_det);
         gpio_free(gpio_wp);
-        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
 }
 
 static const struct imxmmc_platform_data mmc_pdata __initconst = {
@@ -161,6 +161,10 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
 };
 
 /* Framebuffer support */
+static const struct ipu_platform_data ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
 static const struct fb_videomode fb_modedb = {
         /* 640x480 TFT panel (IPS-056T) */
         .name           = "CRT-VGA",
@@ -194,7 +198,7 @@ static void __init mx31lilly_init_fb(void)
                 return;
         }
 
-        imx31_add_ipu_core();
+        imx31_add_ipu_core(&ipu_data);
         imx31_add_mx3_sdc_fb(&fb_pdata);
         gpio_direction_output(LCD_VCC_EN_GPIO, 1);
 }
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 5a160b7e4fc..bf0fb87946b 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -31,11 +31,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "board-mx31lite.h"
-#include "common.h"
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lite.h>
+
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
 
 /*
  * This file contains board-specific initialization routines for the
@@ -115,8 +116,7 @@ static int mxc_mmc1_init(struct device *dev,
         gpio_direction_input(gpio_det);
         gpio_direction_input(gpio_wp);
 
-        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
-                          detect_irq,
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
                           IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                           "MMC detect", data);
         if (ret)
@@ -137,7 +137,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
 {
         gpio_free(gpio_det);
         gpio_free(gpio_wp);
-        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
 }
 
 static const struct imxmmc_platform_data mmc_pdata __initconst = {
@@ -191,6 +191,6 @@ void __init mx31lite_db_init(void)
         imx31_add_mxc_mmc(0, &mmc_pdata);
         imx31_add_spi_imx0(&spi0_pdata);
         gpio_led_register_device(-1, &litekit_led_platform_data);
-        imx31_add_imx2_wdt();
-        imx31_add_mxc_rtc();
+        imx31_add_imx2_wdt(NULL);
+        imx31_add_mxc_rtc(NULL);
 }
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 52d5b157472..0aa25364360 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -22,11 +22,12 @@
 
 #include <linux/usb/otg.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/hardware.h>
+#include <mach/ulpi.h>
+
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
 
 static unsigned int devboard_pins[] = {
         /* UART1 */
@@ -157,7 +158,7 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev)
 #define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
 #define USBH1_MODE      IOMUX_TO_GPIO(MX31_PIN_NFALE)
 
-static int devboard_isp1105_init(struct usb_phy *otg)
+static int devboard_isp1105_init(struct otg_transceiver *otg)
 {
         int ret = gpio_request(USBH1_MODE, "usbh1-mode");
         if (ret)
@@ -176,7 +177,7 @@ static int devboard_isp1105_init(struct usb_phy *otg)
 }
 
 
-static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on)
+static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
 {
         if (on)
                 gpio_set_value(USBH1_VBUSEN_B, 0);
@@ -193,24 +194,18 @@ static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
 
 static int __init devboard_usbh1_init(void)
 {
-        struct usb_phy *phy;
+        struct otg_transceiver *otg;
         struct platform_device *pdev;
 
-        phy = kzalloc(sizeof(*phy), GFP_KERNEL);
-        if (!phy)
-                return -ENOMEM;
-
-        phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
-        if (!phy->otg) {
-                kfree(phy);
+        otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+        if (!otg)
                 return -ENOMEM;
-        }
 
-        phy->label      = "ISP1105";
-        phy->init       = devboard_isp1105_init;
-        phy->otg->set_vbus      = devboard_isp1105_set_vbus;
+        otg->label      = "ISP1105";
+        otg->init       = devboard_isp1105_init;
+        otg->set_vbus   = devboard_isp1105_set_vbus;
 
-        usbh1_pdata.otg = phy;
+        usbh1_pdata.otg = otg;
 
         pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
         if (IS_ERR(pdev))
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index a4f43e90f3c..bb639cbda4e 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -24,13 +24,14 @@
 
 #include <linux/usb/otg.h>
 
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
+
 #include <media/soc_camera.h>
 
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
 
 static unsigned int marxbot_pins[] = {
         /* SDHC2 */
@@ -271,7 +272,7 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev)
 #define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
 #define USBH1_MODE      IOMUX_TO_GPIO(MX31_PIN_NFALE)
 
-static int marxbot_isp1105_init(struct usb_phy *otg)
+static int marxbot_isp1105_init(struct otg_transceiver *otg)
 {
         int ret = gpio_request(USBH1_MODE, "usbh1-mode");
         if (ret)
@@ -290,7 +291,7 @@ static int marxbot_isp1105_init(struct usb_phy *otg)
 }
 
 
-static int marxbot_isp1105_set_vbus(struct usb_otg *otg, bool on)
+static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
 {
         if (on)
                 gpio_set_value(USBH1_VBUSEN_B, 0);
@@ -307,24 +308,18 @@ static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
 
 static int __init marxbot_usbh1_init(void)
 {
-        struct usb_phy *phy;
+        struct otg_transceiver *otg;
         struct platform_device *pdev;
 
-        phy = kzalloc(sizeof(*phy), GFP_KERNEL);
-        if (!phy)
-                return -ENOMEM;
-
-        phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
-        if (!phy->otg) {
-                kfree(phy);
+        otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+        if (!otg)
                 return -ENOMEM;
-        }
 
-        phy->label      = "ISP1105";
-        phy->init       = marxbot_isp1105_init;
-        phy->otg->set_vbus      = marxbot_isp1105_set_vbus;
+        otg->label      = "ISP1105";
+        otg->init       = marxbot_isp1105_init;
+        otg->set_vbus   = marxbot_isp1105_set_vbus;
 
-        usbh1_pdata.otg = phy;
+        usbh1_pdata.otg = otg;
 
         pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
         if (IS_ERR(pdev))
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 04ae45dbfaa..fabb801e799 100644
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -23,14 +23,15 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31moboard.h>
+#include <mach/ulpi.h>
+
 #include <media/soc_camera.h>
 
-#include "board-mx31moboard.h"
-#include "common.h"
 #include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
 
 static unsigned int smartbot_pins[] = {
         /* UART1 */
diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h
deleted file mode 100644
index 2af5d3a699c..00000000000
--- a/arch/arm/mach-imx/mx35.h
+++ /dev/null
@@ -1,190 +0,0 @@
-#ifndef __MACH_MX35_H__
-#define __MACH_MX35_H__
-
-/*
- * IRAM
- */
-#define MX35_IRAM_BASE_ADDR             0x10000000      /* internal ram */
-#define MX35_IRAM_SIZE                  SZ_128K
-
-#define MX35_L2CC_BASE_ADDR             0x30000000
-#define MX35_L2CC_SIZE                  SZ_1M
-
-#define MX35_AIPS1_BASE_ADDR            0x43f00000
-#define MX35_AIPS1_SIZE                 SZ_1M
-#define MX35_MAX_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x04000)
-#define MX35_EVTMON_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x08000)
-#define MX35_CLKCTL_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x0c000)
-#define MX35_ETB_SLOT4_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x10000)
-#define MX35_ETB_SLOT5_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x14000)
-#define MX35_ECT_CTIO_BASE_ADDR                 (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C1_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x80000)
-#define MX35_I2C3_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x84000)
-#define MX35_UART1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x90000)
-#define MX35_UART2_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x94000)
-#define MX35_I2C2_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x98000)
-#define MX35_OWIRE_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x9c000)
-#define MX35_SSI1_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0xa0000)
-#define MX35_CSPI1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0xa4000)
-#define MX35_KPP_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0xa8000)
-#define MX35_IOMUXC_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0xac000)
-#define MX35_ECT_IP1_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xb8000)
-#define MX35_ECT_IP2_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xbc000)
-
-#define MX35_SPBA0_BASE_ADDR            0x50000000
-#define MX35_SPBA0_SIZE                 SZ_1M
-#define MX35_UART3_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x0c000)
-#define MX35_CSPI2_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x10000)
-#define MX35_SSI2_BASE_ADDR                     (MX35_SPBA0_BASE_ADDR + 0x14000)
-#define MX35_ATA_BASE_ADDR                      (MX35_SPBA0_BASE_ADDR + 0x20000)
-#define MX35_MSHC1_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x24000)
-#define MX35_FEC_BASE_ADDR              0x50038000
-#define MX35_SPBA_CTRL_BASE_ADDR                (MX35_SPBA0_BASE_ADDR + 0x3c000)
-
-#define MX35_AIPS2_BASE_ADDR            0x53f00000
-#define MX35_AIPS2_SIZE                 SZ_1M
-#define MX35_CCM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0x80000)
-#define MX35_GPT1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0x90000)
-#define MX35_EPIT1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0x94000)
-#define MX35_EPIT2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0x98000)
-#define MX35_GPIO3_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xa4000)
-#define MX35_SCC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xac000)
-#define MX35_RNGA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xb0000)
-#define MX35_ESDHC1_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xb4000)
-#define MX35_ESDHC2_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xb8000)
-#define MX35_ESDHC3_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xbc000)
-#define MX35_IPU_CTRL_BASE_ADDR                 (MX35_AIPS2_BASE_ADDR + 0xc0000)
-#define MX35_AUDMUX_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xc4000)
-#define MX35_GPIO1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xcc000)
-#define MX35_GPIO2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xd0000)
-#define MX35_SDMA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xd4000)
-#define MX35_RTC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xd8000)
-#define MX35_WDOG_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xdc000)
-#define MX35_PWM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xe0000)
-#define MX35_CAN1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe4000)
-#define MX35_CAN2_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe8000)
-#define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
-#define MX35_IIM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xf0000)
-#define MX35_USB_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xf4000)
-#define MX35_USB_OTG_BASE_ADDR                  (MX35_USB_BASE_ADDR + 0x0000)
-/*
- * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
- * HS.  When host support was implemented only a preliminary document was
- * available, which told 0x400.  This works fine.
- */
-#define MX35_USB_HS_BASE_ADDR                   (MX35_USB_BASE_ADDR + 0x0400)
-
-#define MX35_ROMP_BASE_ADDR             0x60000000
-#define MX35_ROMP_SIZE                  SZ_1M
-
-#define MX35_AVIC_BASE_ADDR             0x68000000
-#define MX35_AVIC_SIZE                  SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX35_IPU_MEM_BASE_ADDR          0x70000000
-#define MX35_CSD0_BASE_ADDR             0x80000000
-#define MX35_CSD1_BASE_ADDR             0x90000000
-
-#define MX35_CS0_BASE_ADDR              0xa0000000
-#define MX35_CS1_BASE_ADDR              0xa8000000
-#define MX35_CS2_BASE_ADDR              0xb0000000
-#define MX35_CS3_BASE_ADDR              0xb2000000
-
-#define MX35_CS4_BASE_ADDR              0xb4000000
-#define MX35_CS4_BASE_ADDR_VIRT         0xf6000000
-#define MX35_CS4_SIZE                   SZ_32M
-
-#define MX35_CS5_BASE_ADDR              0xb6000000
-#define MX35_CS5_BASE_ADDR_VIRT         0xf8000000
-#define MX35_CS5_SIZE                   SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MX35_X_MEMC_BASE_ADDR           0xb8000000
-#define MX35_X_MEMC_SIZE                SZ_64K
-#define MX35_ESDCTL_BASE_ADDR                   (MX35_X_MEMC_BASE_ADDR + 0x1000)
-#define MX35_WEIM_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x2000)
-#define MX35_M3IF_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x3000)
-#define MX35_EMI_CTL_BASE_ADDR                  (MX35_X_MEMC_BASE_ADDR + 0x4000)
-#define MX35_PCMCIA_CTL_BASE_ADDR               MX35_EMI_CTL_BASE_ADDR
-
-#define MX35_NFC_BASE_ADDR              0xbb000000
-#define MX35_PCMCIA_MEM_BASE_ADDR       0xbc000000
-
-#define MX35_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX35_IO_ADDRESS(x)              IOMEM(MX35_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX35_INT_OWIRE          (NR_IRQS_LEGACY + 2)
-#define MX35_INT_I2C3           (NR_IRQS_LEGACY + 3)
-#define MX35_INT_I2C2           (NR_IRQS_LEGACY + 4)
-#define MX35_INT_RTIC           (NR_IRQS_LEGACY + 6)
-#define MX35_INT_ESDHC1         (NR_IRQS_LEGACY + 7)
-#define MX35_INT_ESDHC2         (NR_IRQS_LEGACY + 8)
-#define MX35_INT_ESDHC3         (NR_IRQS_LEGACY + 9)
-#define MX35_INT_I2C1           (NR_IRQS_LEGACY + 10)
-#define MX35_INT_SSI1           (NR_IRQS_LEGACY + 11)
-#define MX35_INT_SSI2           (NR_IRQS_LEGACY + 12)
-#define MX35_INT_CSPI2          (NR_IRQS_LEGACY + 13)
-#define MX35_INT_CSPI1          (NR_IRQS_LEGACY + 14)
-#define MX35_INT_ATA            (NR_IRQS_LEGACY + 15)
-#define MX35_INT_GPU2D          (NR_IRQS_LEGACY + 16)
-#define MX35_INT_ASRC           (NR_IRQS_LEGACY + 17)
-#define MX35_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX35_INT_IIM            (NR_IRQS_LEGACY + 19)
-#define MX35_INT_RNGA           (NR_IRQS_LEGACY + 22)
-#define MX35_INT_EVTMON         (NR_IRQS_LEGACY + 23)
-#define MX35_INT_KPP            (NR_IRQS_LEGACY + 24)
-#define MX35_INT_RTC            (NR_IRQS_LEGACY + 25)
-#define MX35_INT_PWM            (NR_IRQS_LEGACY + 26)
-#define MX35_INT_EPIT2          (NR_IRQS_LEGACY + 27)
-#define MX35_INT_EPIT1          (NR_IRQS_LEGACY + 28)
-#define MX35_INT_GPT            (NR_IRQS_LEGACY + 29)
-#define MX35_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
-#define MX35_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX35_INT_NFC            (NR_IRQS_LEGACY + 33)
-#define MX35_INT_SDMA           (NR_IRQS_LEGACY + 34)
-#define MX35_INT_USB_HS         (NR_IRQS_LEGACY + 35)
-#define MX35_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
-#define MX35_INT_MSHC1          (NR_IRQS_LEGACY + 39)
-#define MX35_INT_ESAI           (NR_IRQS_LEGACY + 40)
-#define MX35_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
-#define MX35_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
-#define MX35_INT_CAN1           (NR_IRQS_LEGACY + 43)
-#define MX35_INT_CAN2           (NR_IRQS_LEGACY + 44)
-#define MX35_INT_UART1          (NR_IRQS_LEGACY + 45)
-#define MX35_INT_MLB            (NR_IRQS_LEGACY + 46)
-#define MX35_INT_SPDIF          (NR_IRQS_LEGACY + 47)
-#define MX35_INT_ECT            (NR_IRQS_LEGACY + 48)
-#define MX35_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
-#define MX35_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
-#define MX35_INT_GPIO2          (NR_IRQS_LEGACY + 51)
-#define MX35_INT_GPIO1          (NR_IRQS_LEGACY + 52)
-#define MX35_INT_WDOG           (NR_IRQS_LEGACY + 55)
-#define MX35_INT_GPIO3          (NR_IRQS_LEGACY + 56)
-#define MX35_INT_FEC            (NR_IRQS_LEGACY + 57)
-#define MX35_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
-#define MX35_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
-#define MX35_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
-#define MX35_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
-#define MX35_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
-#define MX35_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
-
-#define MX35_DMA_REQ_SSI2_RX1   22
-#define MX35_DMA_REQ_SSI2_TX1   23
-#define MX35_DMA_REQ_SSI2_RX0   24
-#define MX35_DMA_REQ_SSI2_TX0   25
-#define MX35_DMA_REQ_SSI1_RX1   26
-#define MX35_DMA_REQ_SSI1_TX1   27
-#define MX35_DMA_REQ_SSI1_RX0   28
-#define MX35_DMA_REQ_SSI1_TX0   29
-
-#define MX35_PROD_SIGNATURE             0x1     /* For MX31 */
-
-#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/mach-imx/mx3x.h b/arch/arm/mach-imx/mx3x.h
deleted file mode 100644
index 96fb4fbc8ad..00000000000
--- a/arch/arm/mach-imx/mx3x.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MX3x_H__
-#define __MACH_MX3x_H__
-
-/*
- * MX31 memory map:
- *
- * Virt         Phys            Size    What
- * ---------------------------------------------------------------------------
- * FC000000     43F00000        1M      AIPS 1
- * FC100000     50000000        1M      SPBA
- * FC200000     53F00000        1M      AIPS 2
- * FC500000     60000000        128M    ROMPATCH
- * FC400000     68000000        128M    AVIC
- *              70000000        256M    IPU (MAX M2)
- *              80000000        256M    CSD0 SDRAM/DDR
- *              90000000        256M    CSD1 SDRAM/DDR
- *              A0000000        128M    CS0 Flash
- *              A8000000        128M    CS1 Flash
- *              B0000000        32M     CS2
- *              B2000000        32M     CS3
- * F4000000     B4000000        32M     CS4
- *              B6000000        32M     CS5
- * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
- *              C0000000        64M     PCMCIA/CF
- */
-
-/*
- * L2CC
- */
-#define MX3x_L2CC_BASE_ADDR             0x30000000
-#define MX3x_L2CC_SIZE                  SZ_1M
-
-/*
- * AIPS 1
- */
-#define MX3x_AIPS1_BASE_ADDR            0x43f00000
-#define MX3x_AIPS1_SIZE                 SZ_1M
-#define MX3x_MAX_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x04000)
-#define MX3x_EVTMON_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x08000)
-#define MX3x_CLKCTL_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x0c000)
-#define MX3x_ETB_SLOT4_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x10000)
-#define MX3x_ETB_SLOT5_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x14000)
-#define MX3x_ECT_CTIO_BASE_ADDR                 (MX3x_AIPS1_BASE_ADDR + 0x18000)
-#define MX3x_I2C_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x80000)
-#define MX3x_I2C3_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x84000)
-#define MX3x_UART1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x90000)
-#define MX3x_UART2_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x94000)
-#define MX3x_I2C2_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x98000)
-#define MX3x_OWIRE_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x9c000)
-#define MX3x_SSI1_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0xa0000)
-#define MX3x_CSPI1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0xa4000)
-#define MX3x_KPP_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0xa8000)
-#define MX3x_IOMUXC_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0xac000)
-#define MX3x_ECT_IP1_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xb8000)
-#define MX3x_ECT_IP2_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xbc000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX3x_SPBA0_BASE_ADDR            0x50000000
-#define MX3x_SPBA0_SIZE                 SZ_1M
-#define MX3x_UART3_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x0c000)
-#define MX3x_CSPI2_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x10000)
-#define MX3x_SSI2_BASE_ADDR                     (MX3x_SPBA0_BASE_ADDR + 0x14000)
-#define MX3x_ATA_DMA_BASE_ADDR                  (MX3x_SPBA0_BASE_ADDR + 0x20000)
-#define MX3x_MSHC1_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x24000)
-#define MX3x_SPBA_CTRL_BASE_ADDR                (MX3x_SPBA0_BASE_ADDR + 0x3c000)
-
-/*
- * AIPS 2
- */
-#define MX3x_AIPS2_BASE_ADDR            0x53f00000
-#define MX3x_AIPS2_SIZE                 SZ_1M
-#define MX3x_CCM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0x80000)
-#define MX3x_GPT1_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0x90000)
-#define MX3x_EPIT1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x94000)
-#define MX3x_EPIT2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x98000)
-#define MX3x_GPIO3_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xa4000)
-#define MX3x_SCC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xac000)
-#define MX3x_RNGA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xb0000)
-#define MX3x_IPU_CTRL_BASE_ADDR                 (MX3x_AIPS2_BASE_ADDR + 0xc0000)
-#define MX3x_AUDMUX_BASE_ADDR                   (MX3x_AIPS2_BASE_ADDR + 0xc4000)
-#define MX3x_GPIO1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xcc000)
-#define MX3x_GPIO2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xd0000)
-#define MX3x_SDMA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xd4000)
-#define MX3x_RTC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xd8000)
-#define MX3x_WDOG_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xdc000)
-#define MX3x_PWM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xe0000)
-#define MX3x_RTIC_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xec000)
-
-/*
- * ROMP and AVIC
- */
-#define MX3x_ROMP_BASE_ADDR             0x60000000
-#define MX3x_ROMP_SIZE                  SZ_1M
-
-#define MX3x_AVIC_BASE_ADDR             0x68000000
-#define MX3x_AVIC_SIZE                  SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX3x_IPU_MEM_BASE_ADDR          0x70000000
-#define MX3x_CSD0_BASE_ADDR             0x80000000
-#define MX3x_CSD1_BASE_ADDR             0x90000000
-
-#define MX3x_CS0_BASE_ADDR              0xa0000000
-#define MX3x_CS1_BASE_ADDR              0xa8000000
-#define MX3x_CS2_BASE_ADDR              0xb0000000
-#define MX3x_CS3_BASE_ADDR              0xb2000000
-
-#define MX3x_CS4_BASE_ADDR              0xb4000000
-#define MX3x_CS4_BASE_ADDR_VIRT         0xf6000000
-#define MX3x_CS4_SIZE                   SZ_32M
-
-#define MX3x_CS5_BASE_ADDR              0xb6000000
-#define MX3x_CS5_BASE_ADDR_VIRT         0xf8000000
-#define MX3x_CS5_SIZE                   SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MX3x_X_MEMC_BASE_ADDR           0xb8000000
-#define MX3x_X_MEMC_SIZE                SZ_64K
-#define MX3x_ESDCTL_BASE_ADDR                   (MX3x_X_MEMC_BASE_ADDR + 0x1000)
-#define MX3x_WEIM_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x2000)
-#define MX3x_M3IF_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x3000)
-#define MX3x_EMI_CTL_BASE_ADDR                  (MX3x_X_MEMC_BASE_ADDR + 0x4000)
-#define MX3x_PCMCIA_CTL_BASE_ADDR               MX3x_EMI_CTL_BASE_ADDR
-
-#define MX3x_PCMCIA_MEM_BASE_ADDR       0xbc000000
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX3x_INT_I2C3           (NR_IRQS_LEGACY + 3)
-#define MX3x_INT_I2C2           (NR_IRQS_LEGACY + 4)
-#define MX3x_INT_RTIC           (NR_IRQS_LEGACY + 6)
-#define MX3x_INT_I2C            (NR_IRQS_LEGACY + 10)
-#define MX3x_INT_CSPI2          (NR_IRQS_LEGACY + 13)
-#define MX3x_INT_CSPI1          (NR_IRQS_LEGACY + 14)
-#define MX3x_INT_ATA            (NR_IRQS_LEGACY + 15)
-#define MX3x_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX3x_INT_IIM            (NR_IRQS_LEGACY + 19)
-#define MX3x_INT_RNGA           (NR_IRQS_LEGACY + 22)
-#define MX3x_INT_EVTMON         (NR_IRQS_LEGACY + 23)
-#define MX3x_INT_KPP            (NR_IRQS_LEGACY + 24)
-#define MX3x_INT_RTC            (NR_IRQS_LEGACY + 25)
-#define MX3x_INT_PWM            (NR_IRQS_LEGACY + 26)
-#define MX3x_INT_EPIT2          (NR_IRQS_LEGACY + 27)
-#define MX3x_INT_EPIT1          (NR_IRQS_LEGACY + 28)
-#define MX3x_INT_GPT            (NR_IRQS_LEGACY + 29)
-#define MX3x_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
-#define MX3x_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX3x_INT_NANDFC         (NR_IRQS_LEGACY + 33)
-#define MX3x_INT_SDMA           (NR_IRQS_LEGACY + 34)
-#define MX3x_INT_MSHC1          (NR_IRQS_LEGACY + 39)
-#define MX3x_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
-#define MX3x_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
-#define MX3x_INT_UART1          (NR_IRQS_LEGACY + 45)
-#define MX3x_INT_ECT            (NR_IRQS_LEGACY + 48)
-#define MX3x_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
-#define MX3x_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
-#define MX3x_INT_GPIO2          (NR_IRQS_LEGACY + 51)
-#define MX3x_INT_GPIO1          (NR_IRQS_LEGACY + 52)
-#define MX3x_INT_WDOG           (NR_IRQS_LEGACY + 55)
-#define MX3x_INT_GPIO3          (NR_IRQS_LEGACY + 56)
-#define MX3x_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
-#define MX3x_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
-#define MX3x_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
-#define MX3x_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
-#define MX3x_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
-#define MX3x_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
-
-#define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
-
-/* Mandatory defines used globally */
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx35_revision(void);
-extern int mx31_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/mach-imx/mx50.h b/arch/arm/mach-imx/mx50.h
deleted file mode 100644
index 09ac19c1570..00000000000
--- a/arch/arm/mach-imx/mx50.h
+++ /dev/null
@@ -1,290 +0,0 @@
-#ifndef __MACH_MX50_H__
-#define __MACH_MX50_H__
-
-/*
- * IROM
- */
-#define MX50_IROM_BASE_ADDR             0x0
-#define MX50_IROM_SIZE                  SZ_64K
-
-/* TZIC */
-#define MX50_TZIC_BASE_ADDR             0x0fffc000
-#define MX50_TZIC_SIZE                  SZ_16K
-
-/*
- * IRAM
- */
-#define MX50_IRAM_BASE_ADDR     0xf8000000      /* internal ram */
-#define MX50_IRAM_PARTITIONS    16
-#define MX50_IRAM_SIZE          (MX50_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-/*
- * Databahn
- */
-#define MX50_DATABAHN_BASE_ADDR                 0x14000000
-
-/*
- * Graphics Memory of GPU
- */
-#define MX50_GPU2D_BASE_ADDR            0x20000000
-
-#define MX50_DEBUG_BASE_ADDR            0x40000000
-#define MX50_DEBUG_SIZE                 SZ_1M
-#define MX50_ETB_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00001000)
-#define MX50_ETM_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00002000)
-#define MX50_TPIU_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00003000)
-#define MX50_CTI0_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00004000)
-#define MX50_CTI1_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00005000)
-#define MX50_CTI2_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00006000)
-#define MX50_CTI3_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00007000)
-#define MX50_CORTEX_DBG_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x00008000)
-
-#define MX50_APBHDMA_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01000000)
-#define MX50_OCOTP_CTRL_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x01002000)
-#define MX50_DIGCTL_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01004000)
-#define MX50_GPMI_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01006000)
-#define MX50_BCH_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01008000)
-#define MX50_ELCDIF_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x0100a000)
-#define MX50_EPXP_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x0100c000)
-#define MX50_DCP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x0100e000)
-#define MX50_EPDC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01010000)
-#define MX50_QOSC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01012000)
-#define MX50_PERFMON_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01014000)
-#define MX50_SSP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01016000)
-#define MX50_ANATOP_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01018000)
-#define MX50_NIC_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x08000000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX50_SPBA0_BASE_ADDR            0x50000000
-#define MX50_SPBA0_SIZE                 SZ_1M
-
-#define MX50_MMC_SDHC1_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00004000)
-#define MX50_MMC_SDHC2_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00008000)
-#define MX50_UART3_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x0000c000)
-#define MX50_CSPI1_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x00010000)
-#define MX50_SSI2_BASE_ADDR             (MX50_SPBA0_BASE_ADDR + 0x00014000)
-#define MX50_MMC_SDHC3_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00020000)
-#define MX50_MMC_SDHC4_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00024000)
-
-/*
- * AIPS 1
- */
-#define MX50_AIPS1_BASE_ADDR    0x53f00000
-#define MX50_AIPS1_SIZE         SZ_1M
-
-#define MX50_OTG_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00080000)
-#define MX50_GPIO1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00084000)
-#define MX50_GPIO2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00088000)
-#define MX50_GPIO3_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x0008c000)
-#define MX50_GPIO4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00090000)
-#define MX50_KPP_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00094000)
-#define MX50_WDOG_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x00098000)
-#define MX50_GPT1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a0000)
-#define MX50_SRTC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a4000)
-#define MX50_IOMUXC_BASE_ADDR   (MX50_AIPS1_BASE_ADDR + 0x000a8000)
-#define MX50_EPIT1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000ac000)
-#define MX50_PWM1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b4000)
-#define MX50_PWM2_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b8000)
-#define MX50_UART1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000bc000)
-#define MX50_UART2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000c0000)
-#define MX50_SRC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d0000)
-#define MX50_CCM_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d4000)
-#define MX50_GPC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d8000)
-#define MX50_GPIO5_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000dc000)
-#define MX50_GPIO6_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000e0000)
-#define MX50_I2C3_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000ec000)
-#define MX50_UART4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000f0000)
-
-#define MX50_MSHC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f4000)
-#define MX50_RNGB_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f8000)
-
-/*
- * AIPS 2
- */
-#define MX50_AIPS2_BASE_ADDR    0x63f00000
-#define MX50_AIPS2_SIZE         SZ_1M
-
-#define MX50_PLL1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00080000)
-#define MX50_PLL2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00084000)
-#define MX50_PLL3_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00088000)
-#define MX50_UART5_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x00090000)
-#define MX50_AHBMAX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x00094000)
-#define MX50_ARM_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000a0000)
-#define MX50_OWIRE_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000a4000)
-#define MX50_CSPI2_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000ac000)
-#define MX50_SDMA_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000b0000)
-#define MX50_ROMCP_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000b8000)
-#define MX50_CSPI3_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000c0000)
-#define MX50_I2C2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c4000)
-#define MX50_I2C1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c8000)
-#define MX50_SSI1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000cc000)
-#define MX50_AUDMUX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x000d0000)
-#define MX50_WEIM_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000d8000)
-#define MX50_FEC_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000ec000)
-
-/*
- * Memory regions and CS
- */
-#define MX50_CSD0_BASE_ADDR             0x70000000
-#define MX50_CSD1_BASE_ADDR             0xb0000000
-#define MX50_CS0_BASE_ADDR              0xf0000000
-
-#define MX50_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX50_IO_ADDRESS(x)              IOMEM(MX50_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX50_SPBA_SDHC1         0x04
-#define MX50_SPBA_SDHC2         0x08
-#define MX50_SPBA_UART3         0x0c
-#define MX50_SPBA_CSPI1         0x10
-#define MX50_SPBA_SSI2          0x14
-#define MX50_SPBA_SDHC3         0x20
-#define MX50_SPBA_SDHC4         0x24
-#define MX50_SPBA_SPDIF         0x28
-#define MX50_SPBA_ATA           0x30
-#define MX50_SPBA_SLIM          0x34
-#define MX50_SPBA_HSI2C         0x38
-#define MX50_SPBA_CTRL          0x3c
-
-/*
- * DMA request assignments
- */
-#define MX50_DMA_REQ_GPC                1
-#define MX50_DMA_REQ_ATA_UART4_RX       2
-#define MX50_DMA_REQ_ATA_UART4_TX       3
-#define MX50_DMA_REQ_CSPI1_RX           6
-#define MX50_DMA_REQ_CSPI1_TX           7
-#define MX50_DMA_REQ_CSPI2_RX           8
-#define MX50_DMA_REQ_CSPI2_TX           9
-#define MX50_DMA_REQ_I2C3_SDHC3         10
-#define MX50_DMA_REQ_SDHC4              11
-#define MX50_DMA_REQ_UART2_FIRI_RX      12
-#define MX50_DMA_REQ_UART2_FIRI_TX      13
-#define MX50_DMA_REQ_EXT0               14
-#define MX50_DMA_REQ_EXT1               15
-#define MX50_DMA_REQ_UART5_RX           16
-#define MX50_DMA_REQ_UART5_TX           17
-#define MX50_DMA_REQ_UART1_RX           18
-#define MX50_DMA_REQ_UART1_TX           19
-#define MX50_DMA_REQ_I2C1_SDHC1         20
-#define MX50_DMA_REQ_I2C2_SDHC2         21
-#define MX50_DMA_REQ_SSI2_RX2           22
-#define MX50_DMA_REQ_SSI2_TX2           23
-#define MX50_DMA_REQ_SSI2_RX1           24
-#define MX50_DMA_REQ_SSI2_TX1           25
-#define MX50_DMA_REQ_SSI1_RX2           26
-#define MX50_DMA_REQ_SSI1_TX2           27
-#define MX50_DMA_REQ_SSI1_RX1           28
-#define MX50_DMA_REQ_SSI1_TX1           29
-#define MX50_DMA_REQ_CSPI_RX            38
-#define MX50_DMA_REQ_CSPI_TX            39
-#define MX50_DMA_REQ_UART3_RX           42
-#define MX50_DMA_REQ_UART3_TX           43
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX50_INT_MMC_SDHC1      (NR_IRQS_LEGACY + 1)
-#define MX50_INT_MMC_SDHC2      (NR_IRQS_LEGACY + 2)
-#define MX50_INT_MMC_SDHC3      (NR_IRQS_LEGACY + 3)
-#define MX50_INT_MMC_SDHC4      (NR_IRQS_LEGACY + 4)
-#define MX50_INT_DAP            (NR_IRQS_LEGACY + 5)
-#define MX50_INT_SDMA           (NR_IRQS_LEGACY + 6)
-#define MX50_INT_IOMUX          (NR_IRQS_LEGACY + 7)
-#define MX50_INT_UART4          (NR_IRQS_LEGACY + 13)
-#define MX50_INT_USB_H1         (NR_IRQS_LEGACY + 14)
-#define MX50_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
-#define MX50_INT_DATABAHN       (NR_IRQS_LEGACY + 19)
-#define MX50_INT_ELCDIF         (NR_IRQS_LEGACY + 20)
-#define MX50_INT_EPXP           (NR_IRQS_LEGACY + 21)
-#define MX50_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
-#define MX50_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
-#define MX50_INT_EPDC           (NR_IRQS_LEGACY + 27)
-#define MX50_INT_NIC            (NR_IRQS_LEGACY + 28)
-#define MX50_INT_SSI1           (NR_IRQS_LEGACY + 29)
-#define MX50_INT_SSI2           (NR_IRQS_LEGACY + 30)
-#define MX50_INT_UART1          (NR_IRQS_LEGACY + 31)
-#define MX50_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX50_INT_UART3          (NR_IRQS_LEGACY + 33)
-#define MX50_INT_RESV34         (NR_IRQS_LEGACY + 34)
-#define MX50_INT_RESV35         (NR_IRQS_LEGACY + 35)
-#define MX50_INT_CSPI1          (NR_IRQS_LEGACY + 36)
-#define MX50_INT_CSPI2          (NR_IRQS_LEGACY + 37)
-#define MX50_INT_CSPI           (NR_IRQS_LEGACY + 38)
-#define MX50_INT_GPT            (NR_IRQS_LEGACY + 39)
-#define MX50_INT_EPIT1          (NR_IRQS_LEGACY + 40)
-#define MX50_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
-#define MX50_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
-#define MX50_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
-#define MX50_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
-#define MX50_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
-#define MX50_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
-#define MX50_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
-#define MX50_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
-#define MX50_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
-#define MX50_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
-#define MX50_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
-#define MX50_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
-#define MX50_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
-#define MX50_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
-#define MX50_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
-#define MX50_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
-#define MX50_INT_WDOG1          (NR_IRQS_LEGACY + 58)
-#define MX50_INT_KPP            (NR_IRQS_LEGACY + 60)
-#define MX50_INT_PWM1           (NR_IRQS_LEGACY + 61)
-#define MX50_INT_I2C1           (NR_IRQS_LEGACY + 62)
-#define MX50_INT_I2C2           (NR_IRQS_LEGACY + 63)
-#define MX50_INT_I2C3           (NR_IRQS_LEGACY + 64)
-#define MX50_INT_RESV65         (NR_IRQS_LEGACY + 65)
-#define MX50_INT_DCDC           (NR_IRQS_LEGACY + 66)
-#define MX50_INT_THERMAL_ALARM  (NR_IRQS_LEGACY + 67)
-#define MX50_INT_ANA3           (NR_IRQS_LEGACY + 68)
-#define MX50_INT_ANA4           (NR_IRQS_LEGACY + 69)
-#define MX50_INT_CCM1           (NR_IRQS_LEGACY + 71)
-#define MX50_INT_CCM2           (NR_IRQS_LEGACY + 72)
-#define MX50_INT_GPC1           (NR_IRQS_LEGACY + 73)
-#define MX50_INT_GPC2           (NR_IRQS_LEGACY + 74)
-#define MX50_INT_SRC            (NR_IRQS_LEGACY + 75)
-#define MX50_INT_NM             (NR_IRQS_LEGACY + 76)
-#define MX50_INT_PMU            (NR_IRQS_LEGACY + 77)
-#define MX50_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
-#define MX50_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
-#define MX50_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
-#define MX50_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
-#define MX50_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
-#define MX50_INT_UART5          (NR_IRQS_LEGACY + 86)
-#define MX50_INT_FEC            (NR_IRQS_LEGACY + 87)
-#define MX50_INT_OWIRE          (NR_IRQS_LEGACY + 88)
-#define MX50_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
-#define MX50_INT_SJC            (NR_IRQS_LEGACY + 90)
-#define MX50_INT_DCP_CHAN1_3    (NR_IRQS_LEGACY + 91)
-#define MX50_INT_DCP_CHAN0      (NR_IRQS_LEGACY + 92)
-#define MX50_INT_PWM2           (NR_IRQS_LEGACY + 94)
-#define MX50_INT_RNGB           (NR_IRQS_LEGACY + 97)
-#define MX50_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
-#define MX50_INT_RAWNAND_BCH    (NR_IRQS_LEGACY + 100)
-#define MX50_INT_RAWNAND_GPMI   (NR_IRQS_LEGACY + 102)
-#define MX50_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
-#define MX50_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
-#define MX50_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
-#define MX50_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
-#define MX50_INT_MSHC           (NR_IRQS_LEGACY + 109)
-#define MX50_INT_APBHDMA_CHAN0  (NR_IRQS_LEGACY + 110)
-#define MX50_INT_APBHDMA_CHAN1  (NR_IRQS_LEGACY + 111)
-#define MX50_INT_APBHDMA_CHAN2  (NR_IRQS_LEGACY + 112)
-#define MX50_INT_APBHDMA_CHAN3  (NR_IRQS_LEGACY + 113)
-#define MX50_INT_APBHDMA_CHAN4  (NR_IRQS_LEGACY + 114)
-#define MX50_INT_APBHDMA_CHAN5  (NR_IRQS_LEGACY + 115)
-#define MX50_INT_APBHDMA_CHAN6  (NR_IRQS_LEGACY + 116)
-#define MX50_INT_APBHDMA_CHAN7  (NR_IRQS_LEGACY + 117)
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx50_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/mx51.h b/arch/arm/mach-imx/mx51.h
deleted file mode 100644
index af844f76261..00000000000
--- a/arch/arm/mach-imx/mx51.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef __MACH_MX51_H__
-#define __MACH_MX51_H__
-
-/*
- * IROM
- */
-#define MX51_IROM_BASE_ADDR             0x0
-#define MX51_IROM_SIZE                  SZ_64K
-
-/*
- * IRAM
- */
-#define MX51_IRAM_BASE_ADDR             0x1ffe0000      /* internal ram */
-#define MX51_IRAM_PARTITIONS            16
-#define MX51_IRAM_SIZE          (MX51_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-#define MX51_GPU_BASE_ADDR              0x20000000
-#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
-
-/*
- * SPBA global module enabled #0
- */
-#define MX51_SPBA0_BASE_ADDR            0x70000000
-#define MX51_SPBA0_SIZE                 SZ_1M
-
-#define MX51_ESDHC1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x04000)
-#define MX51_ESDHC2_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x08000)
-#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0c000)
-#define MX51_ECSPI1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x10000)
-#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x14000)
-#define MX51_ESDHC3_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x20000)
-#define MX51_ESDHC4_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x24000)
-#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x28000)
-#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x30000)
-#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x34000)
-#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x38000)
-#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x3c000)
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR            0x73f00000
-#define MX51_AIPS1_SIZE                 SZ_1M
-
-#define MX51_USB_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
-#define MX51_USB_OTG_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0000)
-#define MX51_USB_HS1_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0200)
-#define MX51_USB_HS2_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0400)
-#define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
-#define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
-#define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
-#define MX51_GPIO4_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x90000)
-#define MX51_KPP_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x94000)
-#define MX51_WDOG1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x98000)
-#define MX51_WDOG2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x9c000)
-#define MX51_GPT1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa0000)
-#define MX51_SRTC_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa4000)
-#define MX51_IOMUXC_BASE_ADDR           (MX51_AIPS1_BASE_ADDR + 0xa8000)
-#define MX51_EPIT1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xac000)
-#define MX51_EPIT2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xb0000)
-#define MX51_PWM1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb4000)
-#define MX51_PWM2_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb8000)
-#define MX51_UART1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xbc000)
-#define MX51_UART2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xc0000)
-#define MX51_SRC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd0000)
-#define MX51_CCM_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd4000)
-#define MX51_GPC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd8000)
-
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR            0x83f00000
-#define MX51_AIPS2_SIZE                 SZ_1M
-
-#define MX51_PLL1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x80000)
-#define MX51_PLL2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x84000)
-#define MX51_PLL3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x88000)
-#define MX51_AHBMAX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0x94000)
-#define MX51_IIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x98000)
-#define MX51_CSU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x9c000)
-#define MX51_ARM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xa0000)
-#define MX51_OWIRE_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xa4000)
-#define MX51_FIRI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xa8000)
-#define MX51_ECSPI2_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xac000)
-#define MX51_SDMA_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xb0000)
-#define MX51_SCC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xb4000)
-#define MX51_ROMCP_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xb8000)
-#define MX51_RTIC_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xbc000)
-#define MX51_CSPI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc0000)
-#define MX51_I2C2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc4000)
-#define MX51_I2C1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc8000)
-#define MX51_SSI1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xcc000)
-#define MX51_AUDMUX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd0000)
-#define MX51_M4IF_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xd8000)
-#define MX51_ESDCTL_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd9000)
-#define MX51_WEIM_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xda000)
-#define MX51_NFC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdb000)
-#define MX51_EMI_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdbf00)
-#define MX51_MIPI_HSC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xdc000)
-#define MX51_ATA_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe0000)
-#define MX51_SIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe4000)
-#define MX51_SSI3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe8000)
-#define MX51_FEC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xec000)
-#define MX51_TVE_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf0000)
-#define MX51_VPU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf4000)
-#define MX51_SAHARA_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xf8000)
-
-#define MX51_CSD0_BASE_ADDR             0x90000000
-#define MX51_CSD1_BASE_ADDR             0xa0000000
-#define MX51_CS0_BASE_ADDR              0xb0000000
-#define MX51_CS1_BASE_ADDR              0xb8000000
-#define MX51_CS2_BASE_ADDR              0xc0000000
-#define MX51_CS3_BASE_ADDR              0xc8000000
-#define MX51_CS4_BASE_ADDR              0xcc000000
-#define MX51_CS5_BASE_ADDR              0xce000000
-
-/*
- * NFC
- */
-#define MX51_NFC_AXI_BASE_ADDR          0xcfff0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE               SZ_64K
-
-#define MX51_GPU2D_BASE_ADDR            0xd0000000
-#define MX51_TZIC_BASE_ADDR             0xe0000000
-#define MX51_TZIC_SIZE                  SZ_16K
-
-#define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX51_SPBA_SDHC1 0x04
-#define MX51_SPBA_SDHC2 0x08
-#define MX51_SPBA_UART3 0x0c
-#define MX51_SPBA_CSPI1 0x10
-#define MX51_SPBA_SSI2  0x14
-#define MX51_SPBA_SDHC3 0x20
-#define MX51_SPBA_SDHC4 0x24
-#define MX51_SPBA_SPDIF 0x28
-#define MX51_SPBA_ATA   0x30
-#define MX51_SPBA_SLIM  0x34
-#define MX51_SPBA_HSI2C 0x38
-#define MX51_SPBA_CTRL  0x3c
-
-/*
- * Defines for modules using static and dynamic DMA channels
- */
-#define MX51_MXC_DMA_CHANNEL_IRAM       30
-#define MX51_MXC_DMA_CHANNEL_SPDIF_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC1       MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC2       MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_RX    MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_TX    MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI2_RX    MXC_DMA_DYNAMIC_CHANNEL
-#ifdef CONFIG_SDMA_IRAM
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX    (MX51_MXC_DMA_CHANNEL_IRAM + 1)
-#else                           /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX    MXC_DMA_DYNAMIC_CHANNEL
-#endif                          /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_CSPI1_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI1_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_RX     MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_TX     MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MEMORY     MXC_DMA_DYNAMIC_CHANNEL
-
-#define MX51_IS_MEM_DEVICE_NONSHARED(x)         0
-
-/*
- * DMA request assignments
- */
-#define MX51_DMA_REQ_VPU                0
-#define MX51_DMA_REQ_GPC                1
-#define MX51_DMA_REQ_ATA_RX             2
-#define MX51_DMA_REQ_ATA_TX             3
-#define MX51_DMA_REQ_ATA_TX_END         4
-#define MX51_DMA_REQ_SLIM_B             5
-#define MX51_DMA_REQ_CSPI1_RX           6
-#define MX51_DMA_REQ_CSPI1_TX           7
-#define MX51_DMA_REQ_CSPI2_RX           8
-#define MX51_DMA_REQ_CSPI2_TX           9
-#define MX51_DMA_REQ_HS_I2C_TX          10
-#define MX51_DMA_REQ_HS_I2C_RX          11
-#define MX51_DMA_REQ_FIRI_RX            12
-#define MX51_DMA_REQ_FIRI_TX            13
-#define MX51_DMA_REQ_EXTREQ1            14
-#define MX51_DMA_REQ_GPU                15
-#define MX51_DMA_REQ_UART2_RX           16
-#define MX51_DMA_REQ_UART2_TX           17
-#define MX51_DMA_REQ_UART1_RX           18
-#define MX51_DMA_REQ_UART1_TX           19
-#define MX51_DMA_REQ_SDHC1              20
-#define MX51_DMA_REQ_SDHC2              21
-#define MX51_DMA_REQ_SSI2_RX1           22
-#define MX51_DMA_REQ_SSI2_TX1           23
-#define MX51_DMA_REQ_SSI2_RX0           24
-#define MX51_DMA_REQ_SSI2_TX0           25
-#define MX51_DMA_REQ_SSI1_RX1           26
-#define MX51_DMA_REQ_SSI1_TX1           27
-#define MX51_DMA_REQ_SSI1_RX0           28
-#define MX51_DMA_REQ_SSI1_TX0           29
-#define MX51_DMA_REQ_EMI_RD             30
-#define MX51_DMA_REQ_CTI2_0             31
-#define MX51_DMA_REQ_EMI_WR             32
-#define MX51_DMA_REQ_CTI2_1             33
-#define MX51_DMA_REQ_EPIT2              34
-#define MX51_DMA_REQ_SSI3_RX1           35
-#define MX51_DMA_REQ_IPU                36
-#define MX51_DMA_REQ_SSI3_TX1           37
-#define MX51_DMA_REQ_CSPI_RX            38
-#define MX51_DMA_REQ_CSPI_TX            39
-#define MX51_DMA_REQ_SDHC3              40
-#define MX51_DMA_REQ_SDHC4              41
-#define MX51_DMA_REQ_SLIM_B_TX          42
-#define MX51_DMA_REQ_UART3_RX           43
-#define MX51_DMA_REQ_UART3_TX           44
-#define MX51_DMA_REQ_SPDIF              45
-#define MX51_DMA_REQ_SSI3_RX0           46
-#define MX51_DMA_REQ_SSI3_TX0           47
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX51_INT_BASE                   (NR_IRQS_LEGACY + 0)
-#define MX51_INT_RESV0                  (NR_IRQS_LEGACY + 0)
-#define MX51_INT_ESDHC1                 (NR_IRQS_LEGACY + 1)
-#define MX51_INT_ESDHC2                 (NR_IRQS_LEGACY + 2)
-#define MX51_INT_ESDHC3                 (NR_IRQS_LEGACY + 3)
-#define MX51_INT_ESDHC4                 (NR_IRQS_LEGACY + 4)
-#define MX51_INT_RESV5                  (NR_IRQS_LEGACY + 5)
-#define MX51_INT_SDMA                   (NR_IRQS_LEGACY + 6)
-#define MX51_INT_IOMUX                  (NR_IRQS_LEGACY + 7)
-#define MX51_INT_NFC                    (NR_IRQS_LEGACY + 8)
-#define MX51_INT_VPU                    (NR_IRQS_LEGACY + 9)
-#define MX51_INT_IPU_ERR                (NR_IRQS_LEGACY + 10)
-#define MX51_INT_IPU_SYN                (NR_IRQS_LEGACY + 11)
-#define MX51_INT_GPU                    (NR_IRQS_LEGACY + 12)
-#define MX51_INT_RESV13                 (NR_IRQS_LEGACY + 13)
-#define MX51_INT_USB_HS1                (NR_IRQS_LEGACY + 14)
-#define MX51_INT_EMI                    (NR_IRQS_LEGACY + 15)
-#define MX51_INT_USB_HS2                (NR_IRQS_LEGACY + 16)
-#define MX51_INT_USB_HS3                (NR_IRQS_LEGACY + 17)
-#define MX51_INT_USB_OTG                (NR_IRQS_LEGACY + 18)
-#define MX51_INT_SAHARA_H0              (NR_IRQS_LEGACY + 19)
-#define MX51_INT_SAHARA_H1              (NR_IRQS_LEGACY + 20)
-#define MX51_INT_SCC_SMN                (NR_IRQS_LEGACY + 21)
-#define MX51_INT_SCC_STZ                (NR_IRQS_LEGACY + 22)
-#define MX51_INT_SCC_SCM                (NR_IRQS_LEGACY + 23)
-#define MX51_INT_SRTC_NTZ               (NR_IRQS_LEGACY + 24)
-#define MX51_INT_SRTC_TZ                (NR_IRQS_LEGACY + 25)
-#define MX51_INT_RTIC                   (NR_IRQS_LEGACY + 26)
-#define MX51_INT_CSU                    (NR_IRQS_LEGACY + 27)
-#define MX51_INT_SLIM_B                 (NR_IRQS_LEGACY + 28)
-#define MX51_INT_SSI1                   (NR_IRQS_LEGACY + 29)
-#define MX51_INT_SSI2                   (NR_IRQS_LEGACY + 30)
-#define MX51_INT_UART1                  (NR_IRQS_LEGACY + 31)
-#define MX51_INT_UART2                  (NR_IRQS_LEGACY + 32)
-#define MX51_INT_UART3                  (NR_IRQS_LEGACY + 33)
-#define MX51_INT_RESV34                 (NR_IRQS_LEGACY + 34)
-#define MX51_INT_RESV35                 (NR_IRQS_LEGACY + 35)
-#define MX51_INT_ECSPI1                 (NR_IRQS_LEGACY + 36)
-#define MX51_INT_ECSPI2                 (NR_IRQS_LEGACY + 37)
-#define MX51_INT_CSPI                   (NR_IRQS_LEGACY + 38)
-#define MX51_INT_GPT                    (NR_IRQS_LEGACY + 39)
-#define MX51_INT_EPIT1                  (NR_IRQS_LEGACY + 40)
-#define MX51_INT_EPIT2                  (NR_IRQS_LEGACY + 41)
-#define MX51_INT_GPIO1_INT7             (NR_IRQS_LEGACY + 42)
-#define MX51_INT_GPIO1_INT6             (NR_IRQS_LEGACY + 43)
-#define MX51_INT_GPIO1_INT5             (NR_IRQS_LEGACY + 44)
-#define MX51_INT_GPIO1_INT4             (NR_IRQS_LEGACY + 45)
-#define MX51_INT_GPIO1_INT3             (NR_IRQS_LEGACY + 46)
-#define MX51_INT_GPIO1_INT2             (NR_IRQS_LEGACY + 47)
-#define MX51_INT_GPIO1_INT1             (NR_IRQS_LEGACY + 48)
-#define MX51_INT_GPIO1_INT0             (NR_IRQS_LEGACY + 49)
-#define MX51_INT_GPIO1_LOW              (NR_IRQS_LEGACY + 50)
-#define MX51_INT_GPIO1_HIGH             (NR_IRQS_LEGACY + 51)
-#define MX51_INT_GPIO2_LOW              (NR_IRQS_LEGACY + 52)
-#define MX51_INT_GPIO2_HIGH             (NR_IRQS_LEGACY + 53)
-#define MX51_INT_GPIO3_LOW              (NR_IRQS_LEGACY + 54)
-#define MX51_INT_GPIO3_HIGH             (NR_IRQS_LEGACY + 55)
-#define MX51_INT_GPIO4_LOW              (NR_IRQS_LEGACY + 56)
-#define MX51_INT_GPIO4_HIGH             (NR_IRQS_LEGACY + 57)
-#define MX51_INT_WDOG1                  (NR_IRQS_LEGACY + 58)
-#define MX51_INT_WDOG2                  (NR_IRQS_LEGACY + 59)
-#define MX51_INT_KPP                    (NR_IRQS_LEGACY + 60)
-#define MX51_INT_PWM1                   (NR_IRQS_LEGACY + 61)
-#define MX51_INT_I2C1                   (NR_IRQS_LEGACY + 62)
-#define MX51_INT_I2C2                   (NR_IRQS_LEGACY + 63)
-#define MX51_INT_HS_I2C                 (NR_IRQS_LEGACY + 64)
-#define MX51_INT_RESV65                 (NR_IRQS_LEGACY + 65)
-#define MX51_INT_RESV66                 (NR_IRQS_LEGACY + 66)
-#define MX51_INT_SIM_IPB                (NR_IRQS_LEGACY + 67)
-#define MX51_INT_SIM_DAT                (NR_IRQS_LEGACY + 68)
-#define MX51_INT_IIM                    (NR_IRQS_LEGACY + 69)
-#define MX51_INT_ATA                    (NR_IRQS_LEGACY + 70)
-#define MX51_INT_CCM1                   (NR_IRQS_LEGACY + 71)
-#define MX51_INT_CCM2                   (NR_IRQS_LEGACY + 72)
-#define MX51_INT_GPC1                   (NR_IRQS_LEGACY + 73)
-#define MX51_INT_GPC2                   (NR_IRQS_LEGACY + 74)
-#define MX51_INT_SRC                    (NR_IRQS_LEGACY + 75)
-#define MX51_INT_NM                     (NR_IRQS_LEGACY + 76)
-#define MX51_INT_PMU                    (NR_IRQS_LEGACY + 77)
-#define MX51_INT_CTI_IRQ                (NR_IRQS_LEGACY + 78)
-#define MX51_INT_CTI1_TG0               (NR_IRQS_LEGACY + 79)
-#define MX51_INT_CTI1_TG1               (NR_IRQS_LEGACY + 80)
-#define MX51_INT_MCG_ERR                (NR_IRQS_LEGACY + 81)
-#define MX51_INT_MCG_TMR                (NR_IRQS_LEGACY + 82)
-#define MX51_INT_MCG_FUNC               (NR_IRQS_LEGACY + 83)
-#define MX51_INT_GPU2_IRQ               (NR_IRQS_LEGACY + 84)
-#define MX51_INT_GPU2_BUSY              (NR_IRQS_LEGACY + 85)
-#define MX51_INT_RESV86                 (NR_IRQS_LEGACY + 86)
-#define MX51_INT_FEC                    (NR_IRQS_LEGACY + 87)
-#define MX51_INT_OWIRE                  (NR_IRQS_LEGACY + 88)
-#define MX51_INT_CTI1_TG2               (NR_IRQS_LEGACY + 89)
-#define MX51_INT_SJC                    (NR_IRQS_LEGACY + 90)
-#define MX51_INT_SPDIF                  (NR_IRQS_LEGACY + 91)
-#define MX51_INT_TVE                    (NR_IRQS_LEGACY + 92)
-#define MX51_INT_FIRI                   (NR_IRQS_LEGACY + 93)
-#define MX51_INT_PWM2                   (NR_IRQS_LEGACY + 94)
-#define MX51_INT_SLIM_EXP               (NR_IRQS_LEGACY + 95)
-#define MX51_INT_SSI3                   (NR_IRQS_LEGACY + 96)
-#define MX51_INT_EMI_BOOT               (NR_IRQS_LEGACY + 97)
-#define MX51_INT_CTI1_TG3               (NR_IRQS_LEGACY + 98)
-#define MX51_INT_SMC_RX                 (NR_IRQS_LEGACY + 99)
-#define MX51_INT_VPU_IDLE               (NR_IRQS_LEGACY + 100)
-#define MX51_INT_EMI_NFC                (NR_IRQS_LEGACY + 101)
-#define MX51_INT_GPU_IDLE               (NR_IRQS_LEGACY + 102)
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx51_revision(void);
-extern void mx51_display_revision(void);
-#endif
-
-#endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/mx53.h b/arch/arm/mach-imx/mx53.h
deleted file mode 100644
index f829d1c2250..00000000000
--- a/arch/arm/mach-imx/mx53.h
+++ /dev/null
@@ -1,342 +0,0 @@
-#ifndef __MACH_MX53_H__
-#define __MACH_MX53_H__
-
-/*
- * IROM
- */
-#define MX53_IROM_BASE_ADDR             0x0
-#define MX53_IROM_SIZE                  SZ_64K
-
-/* TZIC */
-#define MX53_TZIC_BASE_ADDR             0x0FFFC000
-#define MX53_TZIC_SIZE                  SZ_16K
-
-/*
- * AHCI SATA
- */
-#define MX53_SATA_BASE_ADDR             0x10000000
-
-/*
- * NFC
- */
-#define MX53_NFC_AXI_BASE_ADDR  0xF7FF0000      /* NAND flash AXI */
-#define MX53_NFC_AXI_SIZE               SZ_64K
-
-/*
- * IRAM
- */
-#define MX53_IRAM_BASE_ADDR     0xF8000000      /* internal ram */
-#define MX53_IRAM_PARTITIONS    16
-#define MX53_IRAM_SIZE          (MX53_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-/*
- * Graphics Memory of GPU
- */
-#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
-#define MX53_GPU2D_BASE_ADDR            0x20000000
-#define MX53_GPU_BASE_ADDR              0x30000000
-#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
-
-#define MX53_DEBUG_BASE_ADDR            0x40000000
-#define MX53_DEBUG_SIZE         SZ_1M
-#define MX53_ETB_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00001000)
-#define MX53_ETM_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00002000)
-#define MX53_TPIU_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00003000)
-#define MX53_CTI0_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00004000)
-#define MX53_CTI1_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00005000)
-#define MX53_CTI2_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00006000)
-#define MX53_CTI3_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00007000)
-#define MX53_CORTEX_DBG_BASE_ADDR       (MX53_DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX53_SPBA0_BASE_ADDR            0x50000000
-#define MX53_SPBA0_SIZE         SZ_1M
-
-#define MX53_ESDHC1_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00004000)
-#define MX53_ESDHC2_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00008000)
-#define MX53_UART3_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_ECSPI1_BASE_ADDR           (MX53_SPBA0_BASE_ADDR + 0x00010000)
-#define MX53_SSI2_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x00014000)
-#define MX53_ESDHC3_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00020000)
-#define MX53_ESDHC4_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00024000)
-#define MX53_SPDIF_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00028000)
-#define MX53_ASRC_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x0002C000)
-#define MX53_ATA_DMA_BASE_ADDR  (MX53_SPBA0_BASE_ADDR + 0x00030000)
-#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
-#define MX53_HSI2C_DMA_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00038000)
-#define MX53_SPBA_CTRL_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define MX53_AIPS1_BASE_ADDR    0x53F00000
-#define MX53_AIPS1_SIZE         SZ_1M
-
-#define MX53_OTG_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00080000)
-#define MX53_GPIO1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00084000)
-#define MX53_GPIO2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00088000)
-#define MX53_GPIO3_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX53_GPIO4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00090000)
-#define MX53_KPP_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00098000)
-#define MX53_WDOG2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX53_GPT1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX53_SRTC_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX53_IOMUXC_BASE_ADDR   (MX53_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX53_EPIT1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX53_EPIT2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX53_PWM1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX53_PWM2_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX53_UART1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX53_UART2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX53_SRC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX53_CCM_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX53_GPC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D8000)
-#define MX53_GPIO5_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000DC000)
-#define MX53_GPIO6_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E0000)
-#define MX53_GPIO7_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E4000)
-#define MX53_ATA_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000E8000)
-#define MX53_I2C3_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000EC000)
-#define MX53_UART4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define MX53_AIPS2_BASE_ADDR            0x63F00000
-#define MX53_AIPS2_SIZE                 SZ_1M
-
-#define MX53_PLL1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00080000)
-#define MX53_PLL2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00084000)
-#define MX53_PLL3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00088000)
-#define MX53_PLL4_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x0008C000)
-#define MX53_UART5_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x00090000)
-#define MX53_AHBMAX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x00094000)
-#define MX53_IIM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x00098000)
-#define MX53_CSU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX53_ARM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX53_OWIRE_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX53_FIRI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_ECSPI2_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX53_SDMA_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX53_SCC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX53_ROMCP_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX53_RTIC_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX53_I2C2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX53_I2C1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX53_SSI1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX53_AUDMUX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX53_RTC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000D4000)
-#define MX53_M4IF_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX53_ESDCTL_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX53_WEIM_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX53_NFC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX53_EMI_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX53_MLB_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX53_SSI3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX53_FEC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX53_TVE_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX53_VPU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX53_SAHARA_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000F8000)
-#define MX53_PTP_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000FC000)
-
-/*
- * Memory regions and CS
- */
-#define MX53_CSD0_BASE_ADDR             0x70000000
-#define MX53_CSD1_BASE_ADDR             0xB0000000
-#define MX53_CS0_BASE_ADDR              0xF0000000
-#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
-#define MX53_CS1_64MB_BASE_ADDR         0xF4000000
-#define MX53_CS2_64MB_BASE_ADDR         0xF4000000
-#define MX53_CS2_96MB_BASE_ADDR         0xF6000000
-#define MX53_CS3_BASE_ADDR              0xF6000000
-
-#define MX53_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX53_IO_ADDRESS(x)              IOMEM(MX53_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX53_SPBA_SDHC1 0x04
-#define MX53_SPBA_SDHC2 0x08
-#define MX53_SPBA_UART3 0x0C
-#define MX53_SPBA_CSPI1 0x10
-#define MX53_SPBA_SSI2          0x14
-#define MX53_SPBA_SDHC3 0x20
-#define MX53_SPBA_SDHC4 0x24
-#define MX53_SPBA_SPDIF 0x28
-#define MX53_SPBA_ATA           0x30
-#define MX53_SPBA_SLIM          0x34
-#define MX53_SPBA_HSI2C 0x38
-#define MX53_SPBA_CTRL          0x3C
-
-/*
- * DMA request assignments
- */
-#define MX53_DMA_REQ_SSI3_TX0           47
-#define MX53_DMA_REQ_SSI3_RX0           46
-#define MX53_DMA_REQ_SSI3_TX1           45
-#define MX53_DMA_REQ_SSI3_RX1           44
-#define MX53_DMA_REQ_UART3_TX   43
-#define MX53_DMA_REQ_UART3_RX   42
-#define MX53_DMA_REQ_ESAI_TX            41
-#define MX53_DMA_REQ_ESAI_RX            40
-#define MX53_DMA_REQ_CSPI_TX            39
-#define MX53_DMA_REQ_CSPI_RX            38
-#define MX53_DMA_REQ_ASRC_DMA6  37
-#define MX53_DMA_REQ_ASRC_DMA5  36
-#define MX53_DMA_REQ_ASRC_DMA4  35
-#define MX53_DMA_REQ_ASRC_DMA3  34
-#define MX53_DMA_REQ_ASRC_DMA2  33
-#define MX53_DMA_REQ_ASRC_DMA1  32
-#define MX53_DMA_REQ_EMI_WR             31
-#define MX53_DMA_REQ_EMI_RD             30
-#define MX53_DMA_REQ_SSI1_TX0           29
-#define MX53_DMA_REQ_SSI1_RX0           28
-#define MX53_DMA_REQ_SSI1_TX1           27
-#define MX53_DMA_REQ_SSI1_RX1           26
-#define MX53_DMA_REQ_SSI2_TX0           25
-#define MX53_DMA_REQ_SSI2_RX0           24
-#define MX53_DMA_REQ_SSI2_TX1           23
-#define MX53_DMA_REQ_SSI2_RX1           22
-#define MX53_DMA_REQ_I2C2_SDHC2 21
-#define MX53_DMA_REQ_I2C1_SDHC1 20
-#define MX53_DMA_REQ_UART1_TX   19
-#define MX53_DMA_REQ_UART1_RX   18
-#define MX53_DMA_REQ_UART5_TX   17
-#define MX53_DMA_REQ_UART5_RX   16
-#define MX53_DMA_REQ_SPDIF_TX           15
-#define MX53_DMA_REQ_SPDIF_RX           14
-#define MX53_DMA_REQ_UART2_FIRI_TX      13
-#define MX53_DMA_REQ_UART2_FIRI_RX      12
-#define MX53_DMA_REQ_SDHC4              11
-#define MX53_DMA_REQ_I2C3_SDHC3 10
-#define MX53_DMA_REQ_CSPI2_TX           9
-#define MX53_DMA_REQ_CSPI2_RX           8
-#define MX53_DMA_REQ_CSPI1_TX           7
-#define MX53_DMA_REQ_CSPI1_RX           6
-#define MX53_DMA_REQ_IPU                5
-#define MX53_DMA_REQ_ATA_TX_END 4
-#define MX53_DMA_REQ_ATA_UART4_TX       3
-#define MX53_DMA_REQ_ATA_UART4_RX       2
-#define MX53_DMA_REQ_GPC                1
-#define MX53_DMA_REQ_VPU                0
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX53_INT_RESV0          (NR_IRQS_LEGACY + 0)
-#define MX53_INT_ESDHC1         (NR_IRQS_LEGACY + 1)
-#define MX53_INT_ESDHC2         (NR_IRQS_LEGACY + 2)
-#define MX53_INT_ESDHC3         (NR_IRQS_LEGACY + 3)
-#define MX53_INT_ESDHC4         (NR_IRQS_LEGACY + 4)
-#define MX53_INT_DAP            (NR_IRQS_LEGACY + 5)
-#define MX53_INT_SDMA           (NR_IRQS_LEGACY + 6)
-#define MX53_INT_IOMUX          (NR_IRQS_LEGACY + 7)
-#define MX53_INT_NFC            (NR_IRQS_LEGACY + 8)
-#define MX53_INT_VPU            (NR_IRQS_LEGACY + 9)
-#define MX53_INT_IPU_ERR        (NR_IRQS_LEGACY + 10)
-#define MX53_INT_IPU_SYN        (NR_IRQS_LEGACY + 11)
-#define MX53_INT_GPU            (NR_IRQS_LEGACY + 12)
-#define MX53_INT_UART4          (NR_IRQS_LEGACY + 13)
-#define MX53_INT_USB_H1         (NR_IRQS_LEGACY + 14)
-#define MX53_INT_EMI            (NR_IRQS_LEGACY + 15)
-#define MX53_INT_USB_H2         (NR_IRQS_LEGACY + 16)
-#define MX53_INT_USB_H3         (NR_IRQS_LEGACY + 17)
-#define MX53_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
-#define MX53_INT_SAHARA_H0      (NR_IRQS_LEGACY + 19)
-#define MX53_INT_SAHARA_H1      (NR_IRQS_LEGACY + 20)
-#define MX53_INT_SCC_SMN        (NR_IRQS_LEGACY + 21)
-#define MX53_INT_SCC_STZ        (NR_IRQS_LEGACY + 22)
-#define MX53_INT_SCC_SCM        (NR_IRQS_LEGACY + 23)
-#define MX53_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
-#define MX53_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
-#define MX53_INT_RTIC           (NR_IRQS_LEGACY + 26)
-#define MX53_INT_CSU            (NR_IRQS_LEGACY + 27)
-#define MX53_INT_SATA           (NR_IRQS_LEGACY + 28)
-#define MX53_INT_SSI1           (NR_IRQS_LEGACY + 29)
-#define MX53_INT_SSI2           (NR_IRQS_LEGACY + 30)
-#define MX53_INT_UART1          (NR_IRQS_LEGACY + 31)
-#define MX53_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX53_INT_UART3          (NR_IRQS_LEGACY + 33)
-#define MX53_INT_RTC            (NR_IRQS_LEGACY + 34)
-#define MX53_INT_PTP            (NR_IRQS_LEGACY + 35)
-#define MX53_INT_ECSPI1         (NR_IRQS_LEGACY + 36)
-#define MX53_INT_ECSPI2         (NR_IRQS_LEGACY + 37)
-#define MX53_INT_CSPI           (NR_IRQS_LEGACY + 38)
-#define MX53_INT_GPT            (NR_IRQS_LEGACY + 39)
-#define MX53_INT_EPIT1          (NR_IRQS_LEGACY + 40)
-#define MX53_INT_EPIT2          (NR_IRQS_LEGACY + 41)
-#define MX53_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
-#define MX53_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
-#define MX53_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
-#define MX53_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
-#define MX53_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
-#define MX53_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
-#define MX53_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
-#define MX53_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
-#define MX53_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
-#define MX53_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
-#define MX53_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
-#define MX53_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
-#define MX53_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
-#define MX53_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
-#define MX53_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
-#define MX53_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
-#define MX53_INT_WDOG1          (NR_IRQS_LEGACY + 58)
-#define MX53_INT_WDOG2          (NR_IRQS_LEGACY + 59)
-#define MX53_INT_KPP            (NR_IRQS_LEGACY + 60)
-#define MX53_INT_PWM1           (NR_IRQS_LEGACY + 61)
-#define MX53_INT_I2C1           (NR_IRQS_LEGACY + 62)
-#define MX53_INT_I2C2           (NR_IRQS_LEGACY + 63)
-#define MX53_INT_I2C3           (NR_IRQS_LEGACY + 64)
-#define MX53_INT_MLB            (NR_IRQS_LEGACY + 65)
-#define MX53_INT_ASRC           (NR_IRQS_LEGACY + 66)
-#define MX53_INT_SPDIF          (NR_IRQS_LEGACY + 67)
-#define MX53_INT_SIM_DAT        (NR_IRQS_LEGACY + 68)
-#define MX53_INT_IIM            (NR_IRQS_LEGACY + 69)
-#define MX53_INT_ATA            (NR_IRQS_LEGACY + 70)
-#define MX53_INT_CCM1           (NR_IRQS_LEGACY + 71)
-#define MX53_INT_CCM2           (NR_IRQS_LEGACY + 72)
-#define MX53_INT_GPC1           (NR_IRQS_LEGACY + 73)
-#define MX53_INT_GPC2           (NR_IRQS_LEGACY + 74)
-#define MX53_INT_SRC            (NR_IRQS_LEGACY + 75)
-#define MX53_INT_NM             (NR_IRQS_LEGACY + 76)
-#define MX53_INT_PMU            (NR_IRQS_LEGACY + 77)
-#define MX53_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
-#define MX53_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
-#define MX53_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
-#define MX53_INT_ESAI           (NR_IRQS_LEGACY + 81)
-#define MX53_INT_CAN1           (NR_IRQS_LEGACY + 82)
-#define MX53_INT_CAN2           (NR_IRQS_LEGACY + 83)
-#define MX53_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
-#define MX53_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
-#define MX53_INT_UART5          (NR_IRQS_LEGACY + 86)
-#define MX53_INT_FEC            (NR_IRQS_LEGACY + 87)
-#define MX53_INT_OWIRE          (NR_IRQS_LEGACY + 88)
-#define MX53_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
-#define MX53_INT_SJC            (NR_IRQS_LEGACY + 90)
-#define MX53_INT_TVE            (NR_IRQS_LEGACY + 92)
-#define MX53_INT_FIRI           (NR_IRQS_LEGACY + 93)
-#define MX53_INT_PWM2           (NR_IRQS_LEGACY + 94)
-#define MX53_INT_SLIM_EXP       (NR_IRQS_LEGACY + 95)
-#define MX53_INT_SSI3           (NR_IRQS_LEGACY + 96)
-#define MX53_INT_EMI_BOOT       (NR_IRQS_LEGACY + 97)
-#define MX53_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
-#define MX53_INT_SMC_RX         (NR_IRQS_LEGACY + 99)
-#define MX53_INT_VPU_IDLE       (NR_IRQS_LEGACY + 100)
-#define MX53_INT_EMI_NFC        (NR_IRQS_LEGACY + 101)
-#define MX53_INT_GPU_IDLE       (NR_IRQS_LEGACY + 102)
-#define MX53_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
-#define MX53_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
-#define MX53_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
-#define MX53_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
-#define MX53_INT_GPIO7_LOW      (NR_IRQS_LEGACY + 107)
-#define MX53_INT_GPIO7_HIGH     (NR_IRQS_LEGACY + 108)
-
-#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h
deleted file mode 100644
index 19d3f54db5a..00000000000
--- a/arch/arm/mach-imx/mx6q.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_MX6Q_H__
-#define __MACH_MX6Q_H__
-
-#define MX6Q_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX6Q_IO_ADDRESS(x)              IOMEM(MX6Q_IO_P2V(x))
-
-/*
- * The following are the blocks that need to be statically mapped.
- * For other blocks, the base address really should be retrieved from
- * device tree.
- */
-#define MX6Q_SCU_BASE_ADDR              0x00a00000
-#define MX6Q_SCU_SIZE                   0x1000
-#define MX6Q_CCM_BASE_ADDR              0x020c4000
-#define MX6Q_CCM_SIZE                   0x4000
-#define MX6Q_ANATOP_BASE_ADDR           0x020c8000
-#define MX6Q_ANATOP_SIZE                0x1000
-
-#endif  /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
deleted file mode 100644
index d78298366a9..00000000000
--- a/arch/arm/mach-imx/mxc.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_H__
-#define __ASM_ARCH_MXC_H__
-
-#include <linux/types.h>
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
-#define MXC_CPU_MX1             1
-#define MXC_CPU_MX21            21
-#define MXC_CPU_MX25            25
-#define MXC_CPU_MX27            27
-#define MXC_CPU_MX31            31
-#define MXC_CPU_MX35            35
-#define MXC_CPU_MX50            50
-#define MXC_CPU_MX51            51
-#define MXC_CPU_MX53            53
-
-#define IMX_CHIP_REVISION_1_0           0x10
-#define IMX_CHIP_REVISION_1_1           0x11
-#define IMX_CHIP_REVISION_1_2           0x12
-#define IMX_CHIP_REVISION_1_3           0x13
-#define IMX_CHIP_REVISION_2_0           0x20
-#define IMX_CHIP_REVISION_2_1           0x21
-#define IMX_CHIP_REVISION_2_2           0x22
-#define IMX_CHIP_REVISION_2_3           0x23
-#define IMX_CHIP_REVISION_3_0           0x30
-#define IMX_CHIP_REVISION_3_1           0x31
-#define IMX_CHIP_REVISION_3_2           0x32
-#define IMX_CHIP_REVISION_3_3           0x33
-#define IMX_CHIP_REVISION_UNKNOWN       0xff
-
-#ifndef __ASSEMBLY__
-extern unsigned int __mxc_cpu_type;
-#endif
-
-#ifdef CONFIG_SOC_IMX1
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX1
-# endif
-# define cpu_is_mx1()           (mxc_cpu_type == MXC_CPU_MX1)
-#else
-# define cpu_is_mx1()           (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX21
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX21
-# endif
-# define cpu_is_mx21()          (mxc_cpu_type == MXC_CPU_MX21)
-#else
-# define cpu_is_mx21()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX25
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX25
-# endif
-# define cpu_is_mx25()          (mxc_cpu_type == MXC_CPU_MX25)
-#else
-# define cpu_is_mx25()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX27
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX27
-# endif
-# define cpu_is_mx27()          (mxc_cpu_type == MXC_CPU_MX27)
-#else
-# define cpu_is_mx27()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX31
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX31
-# endif
-# define cpu_is_mx31()          (mxc_cpu_type == MXC_CPU_MX31)
-#else
-# define cpu_is_mx31()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX35
-# endif
-# define cpu_is_mx35()          (mxc_cpu_type == MXC_CPU_MX35)
-#else
-# define cpu_is_mx35()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX50
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX50
-# endif
-# define cpu_is_mx50()          (mxc_cpu_type == MXC_CPU_MX50)
-#else
-# define cpu_is_mx50()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX51
-# endif
-# define cpu_is_mx51()          (mxc_cpu_type == MXC_CPU_MX51)
-#else
-# define cpu_is_mx51()          (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX53
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX53
-# endif
-# define cpu_is_mx53()          (mxc_cpu_type == MXC_CPU_MX53)
-#else
-# define cpu_is_mx53()          (0)
-#endif
-
-#ifndef __ASSEMBLY__
-
-struct cpu_op {
-        u32 cpu_rate;
-};
-
-int tzic_enable_wake(void);
-
-extern struct cpu_op *(*get_cpu_op)(int *op);
-#endif
-
-#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
-#define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
-
-#endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/mach-imx/pcm037.h b/arch/arm/mach-imx/pcm037.h
index 7d167690e17..d6929721a5f 100644
--- a/arch/arm/mach-imx/pcm037.h
+++ b/arch/arm/mach-imx/pcm037.h
@@ -8,10 +8,4 @@ enum pcm037_board_variant {
 
 extern enum pcm037_board_variant pcm037_variant(void);
 
-#ifdef CONFIG_MACH_PCM037_EET
-int pcm037_eet_init_devices(void);
-#else
-static inline int pcm037_eet_init_devices(void) { return 0; }
-#endif
-
 #endif
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 51c60823408..99afbc3f43a 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -23,10 +23,11 @@
 
 #include <asm/mach/arch.h>
 
-#include "common.h"
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+#include <mach/hardware.h>
+
 #include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
 
 static const int pcm970_pins[] __initconst = {
         /* SDHC */
@@ -94,14 +95,14 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
 {
         int ret;
 
-        ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
-                          IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
+        ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
+                                "imx-mmc-detect", data);
         if (ret)
                 return ret;
 
         ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
         if (ret) {
-                free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
+                free_irq(IRQ_GPIOC(29), data);
                 return ret;
         }
 
@@ -112,7 +113,7 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
 
 static void pcm970_sdhc2_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
+        free_irq(IRQ_GPIOC(29), data);
         gpio_free(GPIO_PORTC + 28);
 }
 
@@ -191,7 +192,8 @@ static struct resource pcm970_sja1000_resources[] = {
                 .end     = MX27_CS4_BASE_ADDR + 0x100 - 1,
                 .flags   = IORESOURCE_MEM,
         }, {
-                /* irq number is run-time assigned */
+                .start   = IRQ_GPIOE(19),
+                .end     = IRQ_GPIOE(19),
                 .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         },
 };
@@ -225,7 +227,5 @@ void __init pcm970_baseboard_init(void)
         imx27_add_imx_fb(&pcm038_fb_data);
         mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
         imx27_add_mxc_mmc(1, &sdhc_pdata);
-        pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
-        pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
         platform_device_register(&pcm970_sja1000);
 }
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
deleted file mode 100644
index 3777b805b76..00000000000
--- a/arch/arm/mach-imx/platsmp.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <asm/page.h>
-#include <asm/smp_scu.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "hardware.h"
-
-static void __iomem *scu_base;
-
-static struct map_desc scu_io_desc __initdata = {
-        /* .virtual and .pfn are run-time assigned */
-        .length         = SZ_4K,
-        .type           = MT_DEVICE,
-};
-
-void __init imx_scu_map_io(void)
-{
-        unsigned long base;
-
-        /* Get SCU base */
-        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
-
-        scu_io_desc.virtual = IMX_IO_P2V(base);
-        scu_io_desc.pfn = __phys_to_pfn(base);
-        iotable_init(&scu_io_desc, 1);
-
-        scu_base = IMX_IO_ADDRESS(base);
-}
-
-static void __cpuinit imx_secondary_init(unsigned int cpu)
-{
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-}
-
-static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        imx_set_cpu_jump(cpu, v7_secondary_startup);
-        imx_enable_cpu(cpu, true);
-        return 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init imx_smp_init_cpus(void)
-{
-        int i, ncores;
-
-        ncores = scu_get_core_count(scu_base);
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-
-        set_smp_cross_call(gic_raise_softirq);
-}
-
-void imx_smp_prepare(void)
-{
-        scu_enable(scu_base);
-}
-
-static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
-{
-        imx_smp_prepare();
-}
-
-struct smp_operations  imx_smp_ops __initdata = {
-        .smp_init_cpus          = imx_smp_init_cpus,
-        .smp_prepare_cpus       = imx_smp_prepare_cpus,
-        .smp_secondary_init     = imx_secondary_init,
-        .smp_boot_secondary     = imx_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = imx_cpu_die,
-#endif
-};
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index 56d02d064fb..acf17691d2c 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -10,8 +10,8 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
-
-#include "hardware.h"
+#include <mach/system.h>
+#include <mach/mx27.h>
 
 static int mx27_suspend_enter(suspend_state_t state)
 {
@@ -23,7 +23,7 @@ static int mx27_suspend_enter(suspend_state_t state)
                 cscr &= 0xFFFFFFFC;
                 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
                 /* Executes WFI */
-                cpu_do_idle();
+                arch_idle();
                 break;
 
         default:
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
deleted file mode 100644
index 6a07006ff0f..00000000000
--- a/arch/arm/mach-imx/pm-imx3.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/io.h>
-
-#include "common.h"
-#include "crmregs-imx3.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-
-/*
- * Set cpu low power mode before WFI instruction. This function is called
- * mx3 because it can be used for mx31 and mx35.
- * Currently only WAIT_MODE is supported.
- */
-void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
-{
-        int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR);
-        reg &= ~MXC_CCM_CCMR_LPM_MASK;
-
-        switch (mode) {
-        case MX3_WAIT:
-                if (cpu_is_mx35())
-                        reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
-                __raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
-                break;
-        default:
-                pr_err("Unknown cpu power mode: %d\n", mode);
-                return;
-        }
-}
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
deleted file mode 100644
index 2e063c2deb9..00000000000
--- a/arch/arm/mach-imx/pm-imx5.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/suspend.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/export.h>
-#include <asm/cacheflush.h>
-#include <asm/system_misc.h>
-#include <asm/tlbflush.h>
-
-#include "common.h"
-#include "cpuidle.h"
-#include "crm-regs-imx5.h"
-#include "hardware.h"
-
-/*
- * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
- * This is also the lowest power state possible without affecting
- * non-cpu parts of the system.  For these reasons, imx5 should default
- * to always using this state for cpu idling.  The PM_SUSPEND_STANDBY also
- * uses this state and needs to take no action when registers remain confgiured
- * for this state.
- */
-#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
-
-/*
- * set cpu low power mode before WFI instruction. This function is called
- * mx5 because it can be used for mx50, mx51, and mx53.
- */
-static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
-{
-        u32 plat_lpc, arm_srpgcr, ccm_clpcr;
-        u32 empgc0, empgc1;
-        int stop_mode = 0;
-
-        /* always allow platform to issue a deep sleep mode request */
-        plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
-            ~(MXC_CORTEXA8_PLAT_LPC_DSM);
-        ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
-        arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
-        empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
-        empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
-
-        switch (mode) {
-        case WAIT_CLOCKED:
-                break;
-        case WAIT_UNCLOCKED:
-                ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-        case STOP_POWER_OFF:
-                plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
-                            | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
-                if (mode == WAIT_UNCLOCKED_POWER_OFF) {
-                        ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
-                        ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
-                        ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
-                        stop_mode = 0;
-                } else {
-                        ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
-                        ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
-                        ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
-                        ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
-                        stop_mode = 1;
-                }
-                arm_srpgcr |= MXC_SRPGCR_PCR;
-                break;
-        case STOP_POWER_ON:
-                ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
-                break;
-        default:
-                printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
-                return;
-        }
-
-        __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
-        __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
-        __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
-
-        /* Enable NEON SRPG for all but MX50TO1.0. */
-        if (mx50_revision() != IMX_CHIP_REVISION_1_0)
-                __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
-
-        if (stop_mode) {
-                empgc0 |= MXC_SRPGCR_PCR;
-                empgc1 |= MXC_SRPGCR_PCR;
-
-                __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
-                __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
-        }
-}
-
-static int mx5_suspend_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_MEM:
-                mx5_cpu_lp_set(STOP_POWER_OFF);
-                break;
-        case PM_SUSPEND_STANDBY:
-                /* DEFAULT_IDLE_STATE already configured */
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        if (state == PM_SUSPEND_MEM) {
-                local_flush_tlb_all();
-                flush_cache_all();
-
-                /*clear the EMPGC0/1 bits */
-                __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-                __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
-        }
-        cpu_do_idle();
-
-        /* return registers to default idle state */
-        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
-        return 0;
-}
-
-static int mx5_pm_valid(suspend_state_t state)
-{
-        return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
-}
-
-static const struct platform_suspend_ops mx5_suspend_ops = {
-        .valid = mx5_pm_valid,
-        .enter = mx5_suspend_enter,
-};
-
-static inline int imx5_cpu_do_idle(void)
-{
-        int ret = tzic_enable_wake();
-
-        if (likely(!ret))
-                cpu_do_idle();
-
-        return ret;
-}
-
-static void imx5_pm_idle(void)
-{
-        imx5_cpu_do_idle();
-}
-
-static int imx5_cpuidle_enter(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv, int idx)
-{
-        int ret;
-
-        ret = imx5_cpu_do_idle();
-        if (ret < 0)
-                return ret;
-
-        return idx;
-}
-
-static struct cpuidle_driver imx5_cpuidle_driver = {
-        .name                   = "imx5_cpuidle",
-        .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
-        .states[0]      = {
-                .enter                  = imx5_cpuidle_enter,
-                .exit_latency           = 2,
-                .target_residency       = 1,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "IMX5 SRPG",
-                .desc                   = "CPU state retained,powered off",
-        },
-        .state_count            = 1,
-};
-
-static int __init imx5_pm_common_init(void)
-{
-        int ret;
-        struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-
-        if (IS_ERR(gpc_dvfs_clk))
-                return PTR_ERR(gpc_dvfs_clk);
-
-        ret = clk_prepare_enable(gpc_dvfs_clk);
-        if (ret)
-                return ret;
-
-        arm_pm_idle = imx5_pm_idle;
-
-        /* Set the registers to the default cpu idle state. */
-        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
-
-        imx_cpuidle_init(&imx5_cpuidle_driver);
-        return 0;
-}
-
-void __init imx51_pm_init(void)
-{
-        int ret = imx5_pm_common_init();
-        if (!ret)
-                suspend_set_ops(&mx5_suspend_ops);
-}
-
-void __init imx53_pm_init(void)
-{
-        imx5_pm_common_init();
-}
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
deleted file mode 100644
index a17543da602..00000000000
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/suspend.h>
-#include <asm/cacheflush.h>
-#include <asm/proc-fns.h>
-#include <asm/suspend.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include "common.h"
-#include "hardware.h"
-
-extern unsigned long phys_l2x0_saved_regs;
-
-static int imx6q_suspend_finish(unsigned long val)
-{
-        cpu_do_idle();
-        return 0;
-}
-
-static int imx6q_pm_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_MEM:
-                imx6q_set_lpm(STOP_POWER_OFF);
-                imx_gpc_pre_suspend();
-                imx_set_cpu_jump(0, v7_cpu_resume);
-                /* Zzz ... */
-                cpu_suspend(0, imx6q_suspend_finish);
-                imx_smp_prepare();
-                imx_gpc_post_resume();
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static const struct platform_suspend_ops imx6q_pm_ops = {
-        .enter = imx6q_pm_enter,
-        .valid = suspend_valid_only_mem,
-};
-
-void __init imx6q_pm_init(void)
-{
-        /*
-         * The l2x0 core code provides an infrastucture to save and restore
-         * l2x0 registers across suspend/resume cycle.  But because imx6q
-         * retains L2 content during suspend and needs to resume L2 before
-         * MMU is enabled, it can only utilize register saving support and
-         * have to take care of restoring on its own.  So we save physical
-         * address of the data structure used by l2x0 core to save registers,
-         * and later restore the necessary ones in imx6q resume entry.
-         */
-#ifdef CONFIG_CACHE_L2X0
-        phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
-#endif
-
-        suspend_set_ops(&imx6q_pm_ops);
-}
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
deleted file mode 100644
index e15f1555c59..00000000000
--- a/arch/arm/mach-imx/src.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/smp.h>
-#include <asm/smp_plat.h>
-
-#define SRC_SCR                         0x000
-#define SRC_GPR1                        0x020
-#define BP_SRC_SCR_WARM_RESET_ENABLE    0
-#define BP_SRC_SCR_CORE1_RST            14
-#define BP_SRC_SCR_CORE1_ENABLE         22
-
-static void __iomem *src_base;
-
-void imx_enable_cpu(int cpu, bool enable)
-{
-        u32 mask, val;
-
-        cpu = cpu_logical_map(cpu);
-        mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
-        val = readl_relaxed(src_base + SRC_SCR);
-        val = enable ? val | mask : val & ~mask;
-        writel_relaxed(val, src_base + SRC_SCR);
-}
-
-void imx_set_cpu_jump(int cpu, void *jump_addr)
-{
-        cpu = cpu_logical_map(cpu);
-        writel_relaxed(virt_to_phys(jump_addr),
-                       src_base + SRC_GPR1 + cpu * 8);
-}
-
-void imx_src_prepare_restart(void)
-{
-        u32 val;
-
-        /* clear enable bits of secondary cores */
-        val = readl_relaxed(src_base + SRC_SCR);
-        val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
-        writel_relaxed(val, src_base + SRC_SCR);
-
-        /* clear persistent entry register of primary core */
-        writel_relaxed(0, src_base + SRC_GPR1);
-}
-
-void __init imx_src_init(void)
-{
-        struct device_node *np;
-        u32 val;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
-        src_base = of_iomap(np, 0);
-        WARN_ON(!src_base);
-
-        /*
-         * force warm reset sources to generate cold reset
-         * for a more reliable restart
-         */
-        val = readl_relaxed(src_base + SRC_SCR);
-        val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
-        writel_relaxed(val, src_base + SRC_SCR);
-}
diff --git a/arch/arm/mach-imx/ssi-fiq-ksym.c b/arch/arm/mach-imx/ssi-fiq-ksym.c
deleted file mode 100644
index 792090f9a03..00000000000
--- a/arch/arm/mach-imx/ssi-fiq-ksym.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Exported ksyms for the SSI FIQ handler
- *
- * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-
-#include <linux/platform_data/asoc-imx-ssi.h>
-
-EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);
-EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);
-EXPORT_SYMBOL(imx_ssi_fiq_start);
-EXPORT_SYMBOL(imx_ssi_fiq_end);
-EXPORT_SYMBOL(imx_ssi_fiq_base);
-
diff --git a/arch/arm/mach-imx/ssi-fiq.S b/arch/arm/mach-imx/ssi-fiq.S
deleted file mode 100644
index a8b93c5f29b..00000000000
--- a/arch/arm/mach-imx/ssi-fiq.S
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- *  Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-/*
- * r8  = bit 0-15: tx offset, bit 16-31: tx buffer size
- * r9  = bit 0-15: rx offset, bit 16-31: rx buffer size
- */
-
-#define SSI_STX0        0x00
-#define SSI_SRX0        0x08
-#define SSI_SISR        0x14
-#define SSI_SIER        0x18
-#define SSI_SACNT       0x38
-
-#define SSI_SACNT_AC97EN        (1 << 0)
-
-#define SSI_SIER_TFE0_EN        (1 << 0)
-#define SSI_SISR_TFE0           (1 << 0)
-#define SSI_SISR_RFF0           (1 << 2)
-#define SSI_SIER_RFF0_EN        (1 << 2)
-
-                .text
-                .global imx_ssi_fiq_start
-                .global imx_ssi_fiq_end
-                .global imx_ssi_fiq_base
-                .global imx_ssi_fiq_rx_buffer
-                .global imx_ssi_fiq_tx_buffer
-
-/*
- * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
- * using ENDPROC().  imx_ssi_fiq_start and imx_ssi_fiq_end are used to
- * mark the function body so that it can be copied to the FIQ vector in
- * the vectors page.  imx_ssi_fiq_start should only be called as the result
- * of an FIQ: calling it directly will not work.
- */
-imx_ssi_fiq_start:
-                ldr r12, .L_imx_ssi_fiq_base
-
-                /* TX */
-                ldr r13, .L_imx_ssi_fiq_tx_buffer
-
-                /* shall we send? */
-                ldr r11, [r12, #SSI_SIER]
-                tst r11, #SSI_SIER_TFE0_EN
-                beq 1f
-
-                /* TX FIFO empty? */
-                ldr r11, [r12, #SSI_SISR]
-                tst r11, #SSI_SISR_TFE0
-                beq 1f
-
-                mov r10, #0x10000
-                sub r10, #1
-                and r10, r10, r8        /* r10: current buffer offset */
-
-                add r13, r13, r10
-
-                ldrh r11, [r13]
-                strh r11, [r12, #SSI_STX0]
-
-                ldrh r11, [r13, #2]
-                strh r11, [r12, #SSI_STX0]
-
-                ldrh r11, [r13, #4]
-                strh r11, [r12, #SSI_STX0]
-
-                ldrh r11, [r13, #6]
-                strh r11, [r12, #SSI_STX0]
-
-                add r10, #8
-                lsr r11, r8, #16        /* r11: buffer size */
-                cmp r10, r11
-                lslgt r8, r11, #16
-                addle r8, #8
-1:
-                /* RX */
-
-                /* shall we receive? */
-                ldr r11, [r12, #SSI_SIER]
-                tst r11, #SSI_SIER_RFF0_EN
-                beq 1f
-
-                /* RX FIFO full? */
-                ldr r11, [r12, #SSI_SISR]
-                tst r11, #SSI_SISR_RFF0
-                beq 1f
-
-                ldr r13, .L_imx_ssi_fiq_rx_buffer
-
-                mov r10, #0x10000
-                sub r10, #1
-                and r10, r10, r9        /* r10: current buffer offset */
-
-                add r13, r13, r10
-
-                ldr r11, [r12, #SSI_SACNT]
-                tst r11, #SSI_SACNT_AC97EN
-
-                ldr r11, [r12, #SSI_SRX0]
-                strh r11, [r13]
-
-                ldr r11, [r12, #SSI_SRX0]
-                strh r11, [r13, #2]
-
-                /* dummy read to skip slot 12 */
-                ldrne r11, [r12, #SSI_SRX0]
-
-                ldr r11, [r12, #SSI_SRX0]
-                strh r11, [r13, #4]
-
-                ldr r11, [r12, #SSI_SRX0]
-                strh r11, [r13, #6]
-
-                /* dummy read to skip slot 12 */
-                ldrne r11, [r12, #SSI_SRX0]
-
-                add r10, #8
-                lsr r11, r9, #16        /* r11: buffer size */
-                cmp r10, r11
-                lslgt r9, r11, #16
-                addle r9, #8
-
-1:
-                @ return from FIQ
-                subs    pc, lr, #4
-
-                .align
-.L_imx_ssi_fiq_base:
-imx_ssi_fiq_base:
-                .word 0x0
-.L_imx_ssi_fiq_rx_buffer:
-imx_ssi_fiq_rx_buffer:
-                .word 0x0
-.L_imx_ssi_fiq_tx_buffer:
-imx_ssi_fiq_tx_buffer:
-                .word 0x0
-.L_imx_ssi_fiq_end:
-imx_ssi_fiq_end:
-
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
deleted file mode 100644
index 695e0d73bf8..00000000000
--- a/arch/arm/mach-imx/system.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 1999 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-
-#include <asm/system_misc.h>
-#include <asm/proc-fns.h>
-#include <asm/mach-types.h>
-
-#include "common.h"
-#include "hardware.h"
-
-static void __iomem *wdog_base;
-
-/*
- * Reset the system. It is called by machine_restart().
- */
-void mxc_restart(char mode, const char *cmd)
-{
-        unsigned int wcr_enable;
-
-        if (cpu_is_mx1()) {
-                wcr_enable = (1 << 0);
-        } else {
-                struct clk *clk;
-
-                clk = clk_get_sys("imx2-wdt.0", NULL);
-                if (!IS_ERR(clk))
-                        clk_prepare_enable(clk);
-                wcr_enable = (1 << 2);
-        }
-
-        /* Assert SRS signal */
-        __raw_writew(wcr_enable, wdog_base);
-
-        /* wait for reset to assert... */
-        mdelay(500);
-
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-
-        /* we'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
-
-void mxc_arch_reset_init(void __iomem *base)
-{
-        wdog_base = base;
-}
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
deleted file mode 100644
index f017302f6d0..00000000000
--- a/arch/arm/mach-imx/time.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/time.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
- *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "hardware.h"
-
-/*
- * There are 2 versions of the timer hardware on Freescale MXC hardware.
- * Version 1: MX1/MXL, MX21, MX27.
- * Version 2: MX25, MX31, MX35, MX37, MX51
- */
-
-/* defines common for all i.MX */
-#define MXC_TCTL                0x00
-#define MXC_TCTL_TEN            (1 << 0) /* Enable module */
-#define MXC_TPRER               0x04
-
-/* MX1, MX21, MX27 */
-#define MX1_2_TCTL_CLK_PCLK1    (1 << 1)
-#define MX1_2_TCTL_IRQEN        (1 << 4)
-#define MX1_2_TCTL_FRR          (1 << 8)
-#define MX1_2_TCMP              0x08
-#define MX1_2_TCN               0x10
-#define MX1_2_TSTAT             0x14
-
-/* MX21, MX27 */
-#define MX2_TSTAT_CAPT          (1 << 1)
-#define MX2_TSTAT_COMP          (1 << 0)
-
-/* MX31, MX35, MX25, MX5 */
-#define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
-#define V2_TCTL_CLK_IPG         (1 << 6)
-#define V2_TCTL_CLK_PER         (2 << 6)
-#define V2_TCTL_FRR             (1 << 9)
-#define V2_IR                   0x0c
-#define V2_TSTAT                0x08
-#define V2_TSTAT_OF1            (1 << 0)
-#define V2_TCN                  0x24
-#define V2_TCMP                 0x10
-
-#define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-#define timer_is_v2()   (!timer_is_v1())
-
-static struct clock_event_device clockevent_mxc;
-static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
-
-static void __iomem *timer_base;
-
-static inline void gpt_irq_disable(void)
-{
-        unsigned int tmp;
-
-        if (timer_is_v2())
-                __raw_writel(0, timer_base + V2_IR);
-        else {
-                tmp = __raw_readl(timer_base + MXC_TCTL);
-                __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
-        }
-}
-
-static inline void gpt_irq_enable(void)
-{
-        if (timer_is_v2())
-                __raw_writel(1<<0, timer_base + V2_IR);
-        else {
-                __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
-                        timer_base + MXC_TCTL);
-        }
-}
-
-static void gpt_irq_acknowledge(void)
-{
-        if (timer_is_v1()) {
-                if (cpu_is_mx1())
-                        __raw_writel(0, timer_base + MX1_2_TSTAT);
-                else
-                        __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
-                                timer_base + MX1_2_TSTAT);
-        } else if (timer_is_v2())
-                __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
-}
-
-static void __iomem *sched_clock_reg;
-
-static u32 notrace mxc_read_sched_clock(void)
-{
-        return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
-}
-
-static int __init mxc_clocksource_init(struct clk *timer_clk)
-{
-        unsigned int c = clk_get_rate(timer_clk);
-        void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
-
-        sched_clock_reg = reg;
-
-        setup_sched_clock(mxc_read_sched_clock, 32, c);
-        return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
-                        clocksource_mmio_readl_up);
-}
-
-/* clock event */
-
-static int mx1_2_set_next_event(unsigned long evt,
-                              struct clock_event_device *unused)
-{
-        unsigned long tcmp;
-
-        tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
-
-        __raw_writel(tcmp, timer_base + MX1_2_TCMP);
-
-        return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
-                                -ETIME : 0;
-}
-
-static int v2_set_next_event(unsigned long evt,
-                              struct clock_event_device *unused)
-{
-        unsigned long tcmp;
-
-        tcmp = __raw_readl(timer_base + V2_TCN) + evt;
-
-        __raw_writel(tcmp, timer_base + V2_TCMP);
-
-        return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
-                                -ETIME : 0;
-}
-
-#ifdef DEBUG
-static const char *clock_event_mode_label[] = {
-        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
-        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
-        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
-        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
-        [CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
-};
-#endif /* DEBUG */
-
-static void mxc_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *evt)
-{
-        unsigned long flags;
-
-        /*
-         * The timer interrupt generation is disabled at least
-         * for enough time to call mxc_set_next_event()
-         */
-        local_irq_save(flags);
-
-        /* Disable interrupt in GPT module */
-        gpt_irq_disable();
-
-        if (mode != clockevent_mode) {
-                /* Set event time into far-far future */
-                if (timer_is_v2())
-                        __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
-                                        timer_base + V2_TCMP);
-                else
-                        __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
-                                        timer_base + MX1_2_TCMP);
-
-                /* Clear pending interrupt */
-                gpt_irq_acknowledge();
-        }
-
-#ifdef DEBUG
-        printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
-                clock_event_mode_label[clockevent_mode],
-                clock_event_mode_label[mode]);
-#endif /* DEBUG */
-
-        /* Remember timer mode */
-        clockevent_mode = mode;
-        local_irq_restore(flags);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
-                                "supported for i.MX\n");
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        /*
-         * Do not put overhead of interrupt enable/disable into
-         * mxc_set_next_event(), the core has about 4 minutes
-         * to call mxc_set_next_event() or shutdown clock after
-         * mode switching
-         */
-                local_irq_save(flags);
-                gpt_irq_enable();
-                local_irq_restore(flags);
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                /* Left event sources disabled, no more interrupts appear */
-                break;
-        }
-}
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = &clockevent_mxc;
-        uint32_t tstat;
-
-        if (timer_is_v2())
-                tstat = __raw_readl(timer_base + V2_TSTAT);
-        else
-                tstat = __raw_readl(timer_base + MX1_2_TSTAT);
-
-        gpt_irq_acknowledge();
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mxc_timer_irq = {
-        .name           = "i.MX Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = mxc_timer_interrupt,
-};
-
-static struct clock_event_device clockevent_mxc = {
-        .name           = "mxc_timer1",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
-        .set_mode       = mxc_set_mode,
-        .set_next_event = mx1_2_set_next_event,
-        .rating         = 200,
-};
-
-static int __init mxc_clockevent_init(struct clk *timer_clk)
-{
-        unsigned int c = clk_get_rate(timer_clk);
-
-        if (timer_is_v2())
-                clockevent_mxc.set_next_event = v2_set_next_event;
-
-        clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
-                                        clockevent_mxc.shift);
-        clockevent_mxc.max_delta_ns =
-                        clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
-        clockevent_mxc.min_delta_ns =
-                        clockevent_delta2ns(0xff, &clockevent_mxc);
-
-        clockevent_mxc.cpumask = cpumask_of(0);
-
-        clockevents_register_device(&clockevent_mxc);
-
-        return 0;
-}
-
-void __init mxc_timer_init(void __iomem *base, int irq)
-{
-        uint32_t tctl_val;
-        struct clk *timer_clk;
-        struct clk *timer_ipg_clk;
-
-        timer_clk = clk_get_sys("imx-gpt.0", "per");
-        if (IS_ERR(timer_clk)) {
-                pr_err("i.MX timer: unable to get clk\n");
-                return;
-        }
-
-        timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
-        if (!IS_ERR(timer_ipg_clk))
-                clk_prepare_enable(timer_ipg_clk);
-
-        clk_prepare_enable(timer_clk);
-
-        timer_base = base;
-
-        /*
-         * Initialise to a known state (all timers off, and timing reset)
-         */
-
-        __raw_writel(0, timer_base + MXC_TCTL);
-        __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
-
-        if (timer_is_v2())
-                tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
-        else
-                tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
-
-        __raw_writel(tctl_val, timer_base + MXC_TCTL);
-
-        /* init and register the timer to the framework */
-        mxc_clocksource_init(timer_clk);
-        mxc_clockevent_init(timer_clk);
-
-        /* Make irqs happen */
-        setup_irq(irq, &mxc_timer_irq);
-}
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
deleted file mode 100644
index 9721161f208..00000000000
--- a/arch/arm/mach-imx/tzic.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/irqdomain.h>
-#include <linux/of.h>
-
-#include <asm/mach/irq.h>
-#include <asm/exception.h>
-
-#include "common.h"
-#include "hardware.h"
-#include "irq-common.h"
-
-/*
- *****************************************
- * TZIC Registers                        *
- *****************************************
- */
-
-#define TZIC_INTCNTL    0x0000  /* Control register */
-#define TZIC_INTTYPE    0x0004  /* Controller Type register */
-#define TZIC_IMPID      0x0008  /* Distributor Implementer Identification */
-#define TZIC_PRIOMASK   0x000C  /* Priority Mask Reg */
-#define TZIC_SYNCCTRL   0x0010  /* Synchronizer Control register */
-#define TZIC_DSMINT     0x0014  /* DSM interrupt Holdoffregister */
-#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
-#define TZIC_ENSET0(i)  (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
-#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
-#define TZIC_SRCSET0    0x0200  /* Source Set Register 0 */
-#define TZIC_SRCCLAR0   0x0280  /* Source Clear Register 0 */
-#define TZIC_PRIORITY0  0x0400  /* Priority Register 0 */
-#define TZIC_PND0       0x0D00  /* Pending Register 0 */
-#define TZIC_HIPND(i)   (0x0D80+ ((i) << 2))    /* High Priority Pending Register */
-#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2))   /* Wakeup Config Register */
-#define TZIC_SWINT      0x0F00  /* Software Interrupt Rigger Register */
-#define TZIC_ID0        0x0FD0  /* Indentification Register 0 */
-
-void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
-static struct irq_domain *domain;
-
-#define TZIC_NUM_IRQS 128
-
-#ifdef CONFIG_FIQ
-static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
-{
-        unsigned int index, mask, value;
-
-        index = irq >> 5;
-        if (unlikely(index >= 4))
-                return -EINVAL;
-        mask = 1U << (irq & 0x1F);
-
-        value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
-        if (type)
-                value &= ~mask;
-        __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
-
-        return 0;
-}
-#else
-#define tzic_set_irq_fiq NULL
-#endif
-
-#ifdef CONFIG_PM
-static void tzic_irq_suspend(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        int idx = d->hwirq >> 5;
-
-        __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
-}
-
-static void tzic_irq_resume(struct irq_data *d)
-{
-        int idx = d->hwirq >> 5;
-
-        __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
-                     tzic_base + TZIC_WAKEUP0(idx));
-}
-
-#else
-#define tzic_irq_suspend NULL
-#define tzic_irq_resume NULL
-#endif
-
-static struct mxc_extra_irq tzic_extra_irq = {
-#ifdef CONFIG_FIQ
-        .set_irq_fiq = tzic_set_irq_fiq,
-#endif
-};
-
-static __init void tzic_init_gc(int idx, unsigned int irq_start)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
-                                    handle_level_irq);
-        gc->private = &tzic_extra_irq;
-        gc->wake_enabled = IRQ_MSK(32);
-
-        ct = gc->chip_types;
-        ct->chip.irq_mask = irq_gc_mask_disable_reg;
-        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
-        ct->chip.irq_set_wake = irq_gc_set_wake;
-        ct->chip.irq_suspend = tzic_irq_suspend;
-        ct->chip.irq_resume = tzic_irq_resume;
-        ct->regs.disable = TZIC_ENCLEAR0(idx);
-        ct->regs.enable = TZIC_ENSET0(idx);
-
-        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
-}
-
-asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
-{
-        u32 stat;
-        int i, irqofs, handled;
-
-        do {
-                handled = 0;
-
-                for (i = 0; i < 4; i++) {
-                        stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
-                                __raw_readl(tzic_base + TZIC_INTSEC0(i));
-
-                        while (stat) {
-                                handled = 1;
-                                irqofs = fls(stat) - 1;
-                                handle_IRQ(irq_find_mapping(domain,
-                                                irqofs + i * 32), regs);
-                                stat &= ~(1 << irqofs);
-                        }
-                }
-        } while (handled);
-}
-
-/*
- * This function initializes the TZIC hardware and disables all the
- * interrupts. It registers the interrupt enable and disable functions
- * to the kernel for each interrupt source.
- */
-void __init tzic_init_irq(void __iomem *irqbase)
-{
-        struct device_node *np;
-        int irq_base;
-        int i;
-
-        tzic_base = irqbase;
-        /* put the TZIC into the reset value with
-         * all interrupts disabled
-         */
-        i = __raw_readl(tzic_base + TZIC_INTCNTL);
-
-        __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
-        __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
-        __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
-
-        for (i = 0; i < 4; i++)
-                __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
-
-        /* disable all interrupts */
-        for (i = 0; i < 4; i++)
-                __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
-
-        /* all IRQ no FIQ Warning :: No selection */
-
-        irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
-        WARN_ON(irq_base < 0);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
-        domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
-                                       &irq_domain_simple_ops, NULL);
-        WARN_ON(!domain);
-
-        for (i = 0; i < 4; i++, irq_base += 32)
-                tzic_init_gc(i, irq_base);
-
-#ifdef CONFIG_FIQ
-        /* Initialize FIQ */
-        init_FIQ(FIQ_START);
-#endif
-
-        pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
-}
-
-/**
- * tzic_enable_wake() - enable wakeup interrupt
- *
- * @return                      0 if successful; non-zero otherwise
- *
- * This function provides an interrupt synchronization point that is required
- * by tzic enabled platforms before entering imx specific low power modes (ie,
- * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
- */
-int tzic_enable_wake(void)
-{
-        unsigned int i;
-
-        __raw_writel(1, tzic_base + TZIC_DSMINT);
-        if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
-                return -EAGAIN;
-
-        for (i = 0; i < 4; i++)
-                __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
-                             tzic_base + TZIC_WAKEUP0(i));
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f051957d10..00000000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- * Copyright 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include "ulpi.h"
-
-/* ULPIVIEW register bits */
-#define ULPIVW_WU               (1 << 31)       /* Wakeup */
-#define ULPIVW_RUN              (1 << 30)       /* read/write run */
-#define ULPIVW_WRITE            (1 << 29)       /* 0 = read  1 = write */
-#define ULPIVW_SS               (1 << 27)       /* SyncState */
-#define ULPIVW_PORT_MASK        0x07    /* Port field */
-#define ULPIVW_PORT_SHIFT       24
-#define ULPIVW_ADDR_MASK        0xff    /* data address field */
-#define ULPIVW_ADDR_SHIFT       16
-#define ULPIVW_RDATA_MASK       0xff    /* read data field */
-#define ULPIVW_RDATA_SHIFT      8
-#define ULPIVW_WDATA_MASK       0xff    /* write data field */
-#define ULPIVW_WDATA_SHIFT      0
-
-static int ulpi_poll(void __iomem *view, u32 bit)
-{
-        int timeout = 10000;
-
-        while (timeout--) {
-                u32 data = __raw_readl(view);
-
-                if (!(data & bit))
-                        return 0;
-
-                cpu_relax();
-        };
-
-        printk(KERN_WARNING "timeout polling for ULPI device\n");
-
-        return -ETIMEDOUT;
-}
-
-static int ulpi_read(struct usb_phy *otg, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-
-        /* make sure interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-
-        /* read the register */
-        __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
-
-        /* wait for completion */
-        ret = ulpi_poll(view, ULPIVW_RUN);
-        if (ret)
-                return ret;
-
-        return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
-}
-
-static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-
-        /* make sure the interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-
-        __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
-                      (reg << ULPIVW_ADDR_SHIFT) |
-                      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
-
-        /* wait for completion */
-        return ulpi_poll(view, ULPIVW_RUN);
-}
-
-struct usb_phy_io_ops mxc_ulpi_access_ops = {
-        .read   = ulpi_read,
-        .write  = ulpi_write,
-};
-EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
-
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
-        return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
-}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
deleted file mode 100644
index 42bdaca6d7d..00000000000
--- a/arch/arm/mach-imx/ulpi.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __MACH_ULPI_H
-#define __MACH_ULPI_H
-
-#ifdef CONFIG_USB_ULPI
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
-#else
-static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
-        return NULL;
-}
-#endif
-
-extern struct usb_phy_io_ops mxc_ulpi_access_ops;
-
-#endif /* __MACH_ULPI_H */
-