diff options
| author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
|---|---|---|
| committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
| commit | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch) | |
| tree | a8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h | |
| parent | 406089d01562f1e2bf9f089fd7637009ebaad589 (diff) | |
Patched in Tegra support.
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h deleted file mode 100644 index a606d396647..00000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Matrix-centric header file for the AT91SAM9x5 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2012 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Only EBI related registers. | ||
| 7 | * Write Protect register definitions may be useful. | ||
| 8 | * | ||
| 9 | * Licensed under GPLv2 or later. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef AT91SAM9X5_MATRIX_H | ||
| 13 | #define AT91SAM9X5_MATRIX_H | ||
| 14 | |||
| 15 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ | ||
| 16 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 17 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) | ||
| 18 | #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) | ||
| 19 | #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 20 | #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) | ||
| 21 | #define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) | ||
| 22 | #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 23 | #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) | ||
| 24 | #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) | ||
| 25 | #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 26 | #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) | ||
| 27 | #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) | ||
| 28 | #define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ | ||
| 29 | #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) | ||
| 30 | #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) | ||
| 31 | #define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ | ||
| 32 | #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) | ||
| 33 | #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) | ||
| 34 | #define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ | ||
| 35 | #define AT91_MATRIX_NFD0_ON_D0 (0 << 24) | ||
| 36 | #define AT91_MATRIX_NFD0_ON_D16 (1 << 24) | ||
| 37 | #define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ | ||
| 38 | #define AT91_MATRIX_MP_OFF (0 << 25) | ||
| 39 | #define AT91_MATRIX_MP_ON (1 << 25) | ||
| 40 | |||
| 41 | #define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ | ||
| 42 | #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ | ||
| 43 | #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) | ||
| 44 | #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) | ||
| 45 | #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ | ||
| 46 | |||
| 47 | #define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ | ||
| 48 | #define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ | ||
| 49 | #define AT91_MATRIX_WPSR_NO_WPV (0 << 0) | ||
| 50 | #define AT91_MATRIX_WPSR_WPV (1 << 0) | ||
| 51 | #define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ | ||
| 52 | |||
| 53 | #endif | ||