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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-at91
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/at91cap9.c397
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c1259
-rw-r--r--arch/arm/mach-at91/board-cap9adk.c398
-rw-r--r--arch/arm/mach-at91/board-usb-a9260.c230
-rw-r--r--arch/arm/mach-at91/board-usb-a9263.c246
-rw-r--r--arch/arm/mach-at91/include/mach/at91_aic.h53
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pit.h32
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h41
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rtc.h75
-rw-r--r--arch/arm/mach-at91/include/mach/at91_shdwc.h38
-rw-r--r--arch/arm/mach-at91/include/mach/at91_spi.h81
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ssc.h106
-rw-r--r--arch/arm/mach-at91/include/mach/at91_tc.h146
-rw-r--r--arch/arm/mach-at91/include/mach/at91_twi.h68
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h123
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h108
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_matrix.h137
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_emac.h138
-rw-r--r--arch/arm/mach-at91/include/mach/at_hdmac.h102
-rw-r--r--arch/arm/mach-at91/include/mach/board.h210
-rw-r--r--arch/arm/mach-at91/include/mach/entry-macro.S32
-rw-r--r--arch/arm/mach-at91/include/mach/gsia18s.h33
-rw-r--r--arch/arm/mach-at91/include/mach/irqs.h48
-rw-r--r--arch/arm/mach-at91/include/mach/stamp9g20.h7
-rw-r--r--arch/arm/mach-at91/include/mach/system.h59
-rw-r--r--arch/arm/mach-at91/include/mach/vmalloc.h26
26 files changed, 4193 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
new file mode 100644
index 00000000000..bfc684441ef
--- /dev/null
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -0,0 +1,397 @@
1/*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/pm.h>
17
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21
22#include <mach/cpu.h>
23#include <mach/at91cap9.h>
24#include <mach/at91_pmc.h>
25#include <mach/at91_rstc.h>
26#include <mach/at91_shdwc.h>
27
28#include "soc.h"
29#include "generic.h"
30#include "clock.h"
31
32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35
36/*
37 * The peripheral clocks.
38 */
39static struct clk pioABCD_clk = {
40 .name = "pioABCD_clk",
41 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
42 .type = CLK_TYPE_PERIPHERAL,
43};
44static struct clk mpb0_clk = {
45 .name = "mpb0_clk",
46 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk mpb1_clk = {
50 .name = "mpb1_clk",
51 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk mpb2_clk = {
55 .name = "mpb2_clk",
56 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk mpb3_clk = {
60 .name = "mpb3_clk",
61 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk mpb4_clk = {
65 .name = "mpb4_clk",
66 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart0_clk = {
70 .name = "usart0_clk",
71 .pmc_mask = 1 << AT91CAP9_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk usart1_clk = {
75 .name = "usart1_clk",
76 .pmc_mask = 1 << AT91CAP9_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk usart2_clk = {
80 .name = "usart2_clk",
81 .pmc_mask = 1 << AT91CAP9_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc0_clk = {
85 .name = "mci0_clk",
86 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk mmc1_clk = {
90 .name = "mci1_clk",
91 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk can_clk = {
95 .name = "can_clk",
96 .pmc_mask = 1 << AT91CAP9_ID_CAN,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk twi_clk = {
100 .name = "twi_clk",
101 .pmc_mask = 1 << AT91CAP9_ID_TWI,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk spi0_clk = {
105 .name = "spi0_clk",
106 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk spi1_clk = {
110 .name = "spi1_clk",
111 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk ssc0_clk = {
115 .name = "ssc0_clk",
116 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk ssc1_clk = {
120 .name = "ssc1_clk",
121 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk ac97_clk = {
125 .name = "ac97_clk",
126 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk tcb_clk = {
130 .name = "tcb_clk",
131 .pmc_mask = 1 << AT91CAP9_ID_TCB,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk pwm_clk = {
135 .name = "pwm_clk",
136 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk macb_clk = {
140 .name = "macb_clk",
141 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk aestdes_clk = {
145 .name = "aestdes_clk",
146 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149static struct clk adc_clk = {
150 .name = "adc_clk",
151 .pmc_mask = 1 << AT91CAP9_ID_ADC,
152 .type = CLK_TYPE_PERIPHERAL,
153};
154static struct clk isi_clk = {
155 .name = "isi_clk",
156 .pmc_mask = 1 << AT91CAP9_ID_ISI,
157 .type = CLK_TYPE_PERIPHERAL,
158};
159static struct clk lcdc_clk = {
160 .name = "lcdc_clk",
161 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
162 .type = CLK_TYPE_PERIPHERAL,
163};
164static struct clk dma_clk = {
165 .name = "dma_clk",
166 .pmc_mask = 1 << AT91CAP9_ID_DMA,
167 .type = CLK_TYPE_PERIPHERAL,
168};
169static struct clk udphs_clk = {
170 .name = "udphs_clk",
171 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
172 .type = CLK_TYPE_PERIPHERAL,
173};
174static struct clk ohci_clk = {
175 .name = "ohci_clk",
176 .pmc_mask = 1 << AT91CAP9_ID_UHP,
177 .type = CLK_TYPE_PERIPHERAL,
178};
179
180static struct clk *periph_clocks[] __initdata = {
181 &pioABCD_clk,
182 &mpb0_clk,
183 &mpb1_clk,
184 &mpb2_clk,
185 &mpb3_clk,
186 &mpb4_clk,
187 &usart0_clk,
188 &usart1_clk,
189 &usart2_clk,
190 &mmc0_clk,
191 &mmc1_clk,
192 &can_clk,
193 &twi_clk,
194 &spi0_clk,
195 &spi1_clk,
196 &ssc0_clk,
197 &ssc1_clk,
198 &ac97_clk,
199 &tcb_clk,
200 &pwm_clk,
201 &macb_clk,
202 &aestdes_clk,
203 &adc_clk,
204 &isi_clk,
205 &lcdc_clk,
206 &dma_clk,
207 &udphs_clk,
208 &ohci_clk,
209 // irq0 .. irq1
210};
211
212static struct clk_lookup periph_clocks_lookups[] = {
213 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
214 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
215 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
219 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
220 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
222};
223
224static struct clk_lookup usart_clocks_lookups[] = {
225 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
226 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
227 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
229};
230
231/*
232 * The four programmable clocks.
233 * You must configure pin multiplexing to bring these signals out.
234 */
235static struct clk pck0 = {
236 .name = "pck0",
237 .pmc_mask = AT91_PMC_PCK0,
238 .type = CLK_TYPE_PROGRAMMABLE,
239 .id = 0,
240};
241static struct clk pck1 = {
242 .name = "pck1",
243 .pmc_mask = AT91_PMC_PCK1,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 1,
246};
247static struct clk pck2 = {
248 .name = "pck2",
249 .pmc_mask = AT91_PMC_PCK2,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 2,
252};
253static struct clk pck3 = {
254 .name = "pck3",
255 .pmc_mask = AT91_PMC_PCK3,
256 .type = CLK_TYPE_PROGRAMMABLE,
257 .id = 3,
258};
259
260static void __init at91cap9_register_clocks(void)
261{
262 int i;
263
264 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
265 clk_register(periph_clocks[i]);
266
267 clkdev_add_table(periph_clocks_lookups,
268 ARRAY_SIZE(periph_clocks_lookups));
269 clkdev_add_table(usart_clocks_lookups,
270 ARRAY_SIZE(usart_clocks_lookups));
271
272 clk_register(&pck0);
273 clk_register(&pck1);
274 clk_register(&pck2);
275 clk_register(&pck3);
276}
277
278static struct clk_lookup console_clock_lookup;
279
280void __init at91cap9_set_console_clock(int id)
281{
282 if (id >= ARRAY_SIZE(usart_clocks_lookups))
283 return;
284
285 console_clock_lookup.con_id = "usart";
286 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
287 clkdev_add(&console_clock_lookup);
288}
289
290/* --------------------------------------------------------------------
291 * GPIO
292 * -------------------------------------------------------------------- */
293
294static struct at91_gpio_bank at91cap9_gpio[] = {
295 {
296 .id = AT91CAP9_ID_PIOABCD,
297 .offset = AT91_PIOA,
298 .clock = &pioABCD_clk,
299 }, {
300 .id = AT91CAP9_ID_PIOABCD,
301 .offset = AT91_PIOB,
302 .clock = &pioABCD_clk,
303 }, {
304 .id = AT91CAP9_ID_PIOABCD,
305 .offset = AT91_PIOC,
306 .clock = &pioABCD_clk,
307 }, {
308 .id = AT91CAP9_ID_PIOABCD,
309 .offset = AT91_PIOD,
310 .clock = &pioABCD_clk,
311 }
312};
313
314static void at91cap9_reset(void)
315{
316 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
317}
318
319static void at91cap9_poweroff(void)
320{
321 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
322}
323
324
325/* --------------------------------------------------------------------
326 * AT91CAP9 processor initialization
327 * -------------------------------------------------------------------- */
328
329static void __init at91cap9_map_io(void)
330{
331 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
332}
333
334static void __init at91cap9_initialize(void)
335{
336 at91_arch_reset = at91cap9_reset;
337 pm_power_off = at91cap9_poweroff;
338 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
339
340 /* Register GPIO subsystem */
341 at91_gpio_init(at91cap9_gpio, 4);
342
343 /* Remember the silicon revision */
344 if (cpu_is_at91cap9_revB())
345 system_rev = 0xB;
346 else if (cpu_is_at91cap9_revC())
347 system_rev = 0xC;
348}
349
350/* --------------------------------------------------------------------
351 * Interrupt initialization
352 * -------------------------------------------------------------------- */
353
354/*
355 * The default interrupt priority levels (0 = lowest, 7 = highest).
356 */
357static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
358 7, /* Advanced Interrupt Controller (FIQ) */
359 7, /* System Peripherals */
360 1, /* Parallel IO Controller A, B, C and D */
361 0, /* MP Block Peripheral 0 */
362 0, /* MP Block Peripheral 1 */
363 0, /* MP Block Peripheral 2 */
364 0, /* MP Block Peripheral 3 */
365 0, /* MP Block Peripheral 4 */
366 5, /* USART 0 */
367 5, /* USART 1 */
368 5, /* USART 2 */
369 0, /* Multimedia Card Interface 0 */
370 0, /* Multimedia Card Interface 1 */
371 3, /* CAN */
372 6, /* Two-Wire Interface */
373 5, /* Serial Peripheral Interface 0 */
374 5, /* Serial Peripheral Interface 1 */
375 4, /* Serial Synchronous Controller 0 */
376 4, /* Serial Synchronous Controller 1 */
377 5, /* AC97 Controller */
378 0, /* Timer Counter 0, 1 and 2 */
379 0, /* Pulse Width Modulation Controller */
380 3, /* Ethernet */
381 0, /* Advanced Encryption Standard, Triple DES*/
382 0, /* Analog-to-Digital Converter */
383 0, /* Image Sensor Interface */
384 3, /* LCD Controller */
385 0, /* DMA Controller */
386 2, /* USB Device Port */
387 2, /* USB Host port */
388 0, /* Advanced Interrupt Controller (IRQ0) */
389 0, /* Advanced Interrupt Controller (IRQ1) */
390};
391
392struct at91_init_soc __initdata at91cap9_soc = {
393 .map_io = at91cap9_map_io,
394 .default_irq_priority = at91cap9_default_irq_priority,
395 .register_clocks = at91cap9_register_clocks,
396 .init = at91cap9_initialize,
397};
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
new file mode 100644
index 00000000000..0512baf0a21
--- /dev/null
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -0,0 +1,1259 @@
1/*
2 * arch/arm/mach-at91/at91cap9_devices.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <asm/mach/irq.h>
17
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20#include <linux/i2c-gpio.h>
21
22#include <video/atmel_lcdc.h>
23
24#include <mach/board.h>
25#include <mach/cpu.h>
26#include <mach/gpio.h>
27#include <mach/at91cap9.h>
28#include <mach/at91cap9_matrix.h>
29#include <mach/at91sam9_smc.h>
30
31#include "generic.h"
32
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91CAP9_UHP_BASE,
45 .end = AT91CAP9_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = AT91CAP9_ID_UHP,
50 .end = AT91CAP9_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 if (cpu_is_at91cap9_revB())
75 irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
76
77 /* Enable VBus control for UHP ports */
78 for (i = 0; i < data->ports; i++) {
79 if (data->vbus_pin[i])
80 at91_set_gpio_output(data->vbus_pin[i], 0);
81 }
82
83 usbh_data = *data;
84 platform_device_register(&at91_usbh_device);
85}
86#else
87void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
88#endif
89
90
91/* --------------------------------------------------------------------
92 * USB HS Device (Gadget)
93 * -------------------------------------------------------------------- */
94
95#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
96
97static struct resource usba_udc_resources[] = {
98 [0] = {
99 .start = AT91CAP9_UDPHS_FIFO,
100 .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 [1] = {
104 .start = AT91CAP9_BASE_UDPHS,
105 .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 [2] = {
109 .start = AT91CAP9_ID_UDPHS,
110 .end = AT91CAP9_ID_UDPHS,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
116 [idx] = { \
117 .name = nam, \
118 .index = idx, \
119 .fifo_size = maxpkt, \
120 .nr_banks = maxbk, \
121 .can_dma = dma, \
122 .can_isoc = isoc, \
123 }
124
125static struct usba_ep_data usba_udc_ep[] = {
126 EP("ep0", 0, 64, 1, 0, 0),
127 EP("ep1", 1, 1024, 3, 1, 1),
128 EP("ep2", 2, 1024, 3, 1, 1),
129 EP("ep3", 3, 1024, 2, 1, 1),
130 EP("ep4", 4, 1024, 2, 1, 1),
131 EP("ep5", 5, 1024, 2, 1, 0),
132 EP("ep6", 6, 1024, 2, 1, 0),
133 EP("ep7", 7, 1024, 2, 0, 0),
134};
135
136#undef EP
137
138/*
139 * pdata doesn't have room for any endpoints, so we need to
140 * append room for the ones we need right after it.
141 */
142static struct {
143 struct usba_platform_data pdata;
144 struct usba_ep_data ep[8];
145} usba_udc_data;
146
147static struct platform_device at91_usba_udc_device = {
148 .name = "atmel_usba_udc",
149 .id = -1,
150 .dev = {
151 .platform_data = &usba_udc_data.pdata,
152 },
153 .resource = usba_udc_resources,
154 .num_resources = ARRAY_SIZE(usba_udc_resources),
155};
156
157void __init at91_add_device_usba(struct usba_platform_data *data)
158{
159 if (cpu_is_at91cap9_revB()) {
160 irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
161 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
162 AT91_MATRIX_UDPHS_BYPASS_LOCK);
163 }
164 else
165 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
166
167 /*
168 * Invalid pins are 0 on AT91, but the usba driver is shared
169 * with AVR32, which use negative values instead. Once/if
170 * gpio_is_valid() is ported to AT91, revisit this code.
171 */
172 usba_udc_data.pdata.vbus_pin = -EINVAL;
173 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
174 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
175
176 if (data && data->vbus_pin > 0) {
177 at91_set_gpio_input(data->vbus_pin, 0);
178 at91_set_deglitch(data->vbus_pin, 1);
179 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
180 }
181
182 /* Pullup pin is handled internally by USB device peripheral */
183
184 platform_device_register(&at91_usba_udc_device);
185}
186#else
187void __init at91_add_device_usba(struct usba_platform_data *data) {}
188#endif
189
190
191/* --------------------------------------------------------------------
192 * Ethernet
193 * -------------------------------------------------------------------- */
194
195#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
196static u64 eth_dmamask = DMA_BIT_MASK(32);
197static struct at91_eth_data eth_data;
198
199static struct resource eth_resources[] = {
200 [0] = {
201 .start = AT91CAP9_BASE_EMAC,
202 .end = AT91CAP9_BASE_EMAC + SZ_16K - 1,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = AT91CAP9_ID_EMAC,
207 .end = AT91CAP9_ID_EMAC,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct platform_device at91cap9_eth_device = {
213 .name = "macb",
214 .id = -1,
215 .dev = {
216 .dma_mask = &eth_dmamask,
217 .coherent_dma_mask = DMA_BIT_MASK(32),
218 .platform_data = &eth_data,
219 },
220 .resource = eth_resources,
221 .num_resources = ARRAY_SIZE(eth_resources),
222};
223
224void __init at91_add_device_eth(struct at91_eth_data *data)
225{
226 if (!data)
227 return;
228
229 if (data->phy_irq_pin) {
230 at91_set_gpio_input(data->phy_irq_pin, 0);
231 at91_set_deglitch(data->phy_irq_pin, 1);
232 }
233
234 /* Pins used for MII and RMII */
235 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
236 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
237 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
238 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
239 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
240 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
241 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
242 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
243 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
244 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
245
246 if (!data->is_rmii) {
247 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
248 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
249 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
250 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
251 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
252 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
253 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
254 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
255 }
256
257 eth_data = *data;
258 platform_device_register(&at91cap9_eth_device);
259}
260#else
261void __init at91_add_device_eth(struct at91_eth_data *data) {}
262#endif
263
264
265/* --------------------------------------------------------------------
266 * MMC / SD
267 * -------------------------------------------------------------------- */
268
269#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
270static u64 mmc_dmamask = DMA_BIT_MASK(32);
271static struct at91_mmc_data mmc0_data, mmc1_data;
272
273static struct resource mmc0_resources[] = {
274 [0] = {
275 .start = AT91CAP9_BASE_MCI0,
276 .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
277 .flags = IORESOURCE_MEM,
278 },
279 [1] = {
280 .start = AT91CAP9_ID_MCI0,
281 .end = AT91CAP9_ID_MCI0,
282 .flags = IORESOURCE_IRQ,
283 },
284};
285
286static struct platform_device at91cap9_mmc0_device = {
287 .name = "at91_mci",
288 .id = 0,
289 .dev = {
290 .dma_mask = &mmc_dmamask,
291 .coherent_dma_mask = DMA_BIT_MASK(32),
292 .platform_data = &mmc0_data,
293 },
294 .resource = mmc0_resources,
295 .num_resources = ARRAY_SIZE(mmc0_resources),
296};
297
298static struct resource mmc1_resources[] = {
299 [0] = {
300 .start = AT91CAP9_BASE_MCI1,
301 .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 [1] = {
305 .start = AT91CAP9_ID_MCI1,
306 .end = AT91CAP9_ID_MCI1,
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311static struct platform_device at91cap9_mmc1_device = {
312 .name = "at91_mci",
313 .id = 1,
314 .dev = {
315 .dma_mask = &mmc_dmamask,
316 .coherent_dma_mask = DMA_BIT_MASK(32),
317 .platform_data = &mmc1_data,
318 },
319 .resource = mmc1_resources,
320 .num_resources = ARRAY_SIZE(mmc1_resources),
321};
322
323void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
324{
325 if (!data)
326 return;
327
328 /* input/irq */
329 if (data->det_pin) {
330 at91_set_gpio_input(data->det_pin, 1);
331 at91_set_deglitch(data->det_pin, 1);
332 }
333 if (data->wp_pin)
334 at91_set_gpio_input(data->wp_pin, 1);
335 if (data->vcc_pin)
336 at91_set_gpio_output(data->vcc_pin, 0);
337
338 if (mmc_id == 0) { /* MCI0 */
339 /* CLK */
340 at91_set_A_periph(AT91_PIN_PA2, 0);
341
342 /* CMD */
343 at91_set_A_periph(AT91_PIN_PA1, 1);
344
345 /* DAT0, maybe DAT1..DAT3 */
346 at91_set_A_periph(AT91_PIN_PA0, 1);
347 if (data->wire4) {
348 at91_set_A_periph(AT91_PIN_PA3, 1);
349 at91_set_A_periph(AT91_PIN_PA4, 1);
350 at91_set_A_periph(AT91_PIN_PA5, 1);
351 }
352
353 mmc0_data = *data;
354 platform_device_register(&at91cap9_mmc0_device);
355 } else { /* MCI1 */
356 /* CLK */
357 at91_set_A_periph(AT91_PIN_PA16, 0);
358
359 /* CMD */
360 at91_set_A_periph(AT91_PIN_PA17, 1);
361
362 /* DAT0, maybe DAT1..DAT3 */
363 at91_set_A_periph(AT91_PIN_PA18, 1);
364 if (data->wire4) {
365 at91_set_A_periph(AT91_PIN_PA19, 1);
366 at91_set_A_periph(AT91_PIN_PA20, 1);
367 at91_set_A_periph(AT91_PIN_PA21, 1);
368 }
369
370 mmc1_data = *data;
371 platform_device_register(&at91cap9_mmc1_device);
372 }
373}
374#else
375void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
376#endif
377
378
379/* --------------------------------------------------------------------
380 * NAND / SmartMedia
381 * -------------------------------------------------------------------- */
382
383#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
384static struct atmel_nand_data nand_data;
385
386#define NAND_BASE AT91_CHIPSELECT_3
387
388static struct resource nand_resources[] = {
389 [0] = {
390 .start = NAND_BASE,
391 .end = NAND_BASE + SZ_256M - 1,
392 .flags = IORESOURCE_MEM,
393 },
394 [1] = {
395 .start = AT91_BASE_SYS + AT91_ECC,
396 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
397 .flags = IORESOURCE_MEM,
398 }
399};
400
401static struct platform_device at91cap9_nand_device = {
402 .name = "atmel_nand",
403 .id = -1,
404 .dev = {
405 .platform_data = &nand_data,
406 },
407 .resource = nand_resources,
408 .num_resources = ARRAY_SIZE(nand_resources),
409};
410
411void __init at91_add_device_nand(struct atmel_nand_data *data)
412{
413 unsigned long csa;
414
415 if (!data)
416 return;
417
418 csa = at91_sys_read(AT91_MATRIX_EBICSA);
419 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
420
421 /* enable pin */
422 if (data->enable_pin)
423 at91_set_gpio_output(data->enable_pin, 1);
424
425 /* ready/busy pin */
426 if (data->rdy_pin)
427 at91_set_gpio_input(data->rdy_pin, 1);
428
429 /* card detect pin */
430 if (data->det_pin)
431 at91_set_gpio_input(data->det_pin, 1);
432
433 nand_data = *data;
434 platform_device_register(&at91cap9_nand_device);
435}
436#else
437void __init at91_add_device_nand(struct atmel_nand_data *data) {}
438#endif
439
440
441/* --------------------------------------------------------------------
442 * TWI (i2c)
443 * -------------------------------------------------------------------- */
444
445/*
446 * Prefer the GPIO code since the TWI controller isn't robust
447 * (gets overruns and underruns under load) and can only issue
448 * repeated STARTs in one scenario (the driver doesn't yet handle them).
449 */
450#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
451
452static struct i2c_gpio_platform_data pdata = {
453 .sda_pin = AT91_PIN_PB4,
454 .sda_is_open_drain = 1,
455 .scl_pin = AT91_PIN_PB5,
456 .scl_is_open_drain = 1,
457 .udelay = 2, /* ~100 kHz */
458};
459
460static struct platform_device at91cap9_twi_device = {
461 .name = "i2c-gpio",
462 .id = -1,
463 .dev.platform_data = &pdata,
464};
465
466void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
467{
468 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
469 at91_set_multi_drive(AT91_PIN_PB4, 1);
470
471 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
472 at91_set_multi_drive(AT91_PIN_PB5, 1);
473
474 i2c_register_board_info(0, devices, nr_devices);
475 platform_device_register(&at91cap9_twi_device);
476}
477
478#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
479
480static struct resource twi_resources[] = {
481 [0] = {
482 .start = AT91CAP9_BASE_TWI,
483 .end = AT91CAP9_BASE_TWI + SZ_16K - 1,
484 .flags = IORESOURCE_MEM,
485 },
486 [1] = {
487 .start = AT91CAP9_ID_TWI,
488 .end = AT91CAP9_ID_TWI,
489 .flags = IORESOURCE_IRQ,
490 },
491};
492
493static struct platform_device at91cap9_twi_device = {
494 .name = "at91_i2c",
495 .id = -1,
496 .resource = twi_resources,
497 .num_resources = ARRAY_SIZE(twi_resources),
498};
499
500void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
501{
502 /* pins used for TWI interface */
503 at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */
504 at91_set_multi_drive(AT91_PIN_PB4, 1);
505
506 at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */
507 at91_set_multi_drive(AT91_PIN_PB5, 1);
508
509 i2c_register_board_info(0, devices, nr_devices);
510 platform_device_register(&at91cap9_twi_device);
511}
512#else
513void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
514#endif
515
516/* --------------------------------------------------------------------
517 * SPI
518 * -------------------------------------------------------------------- */
519
520#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
521static u64 spi_dmamask = DMA_BIT_MASK(32);
522
523static struct resource spi0_resources[] = {
524 [0] = {
525 .start = AT91CAP9_BASE_SPI0,
526 .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
527 .flags = IORESOURCE_MEM,
528 },
529 [1] = {
530 .start = AT91CAP9_ID_SPI0,
531 .end = AT91CAP9_ID_SPI0,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
536static struct platform_device at91cap9_spi0_device = {
537 .name = "atmel_spi",
538 .id = 0,
539 .dev = {
540 .dma_mask = &spi_dmamask,
541 .coherent_dma_mask = DMA_BIT_MASK(32),
542 },
543 .resource = spi0_resources,
544 .num_resources = ARRAY_SIZE(spi0_resources),
545};
546
547static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
548
549static struct resource spi1_resources[] = {
550 [0] = {
551 .start = AT91CAP9_BASE_SPI1,
552 .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
553 .flags = IORESOURCE_MEM,
554 },
555 [1] = {
556 .start = AT91CAP9_ID_SPI1,
557 .end = AT91CAP9_ID_SPI1,
558 .flags = IORESOURCE_IRQ,
559 },
560};
561
562static struct platform_device at91cap9_spi1_device = {
563 .name = "atmel_spi",
564 .id = 1,
565 .dev = {
566 .dma_mask = &spi_dmamask,
567 .coherent_dma_mask = DMA_BIT_MASK(32),
568 },
569 .resource = spi1_resources,
570 .num_resources = ARRAY_SIZE(spi1_resources),
571};
572
573static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
574
575void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
576{
577 int i;
578 unsigned long cs_pin;
579 short enable_spi0 = 0;
580 short enable_spi1 = 0;
581
582 /* Choose SPI chip-selects */
583 for (i = 0; i < nr_devices; i++) {
584 if (devices[i].controller_data)
585 cs_pin = (unsigned long) devices[i].controller_data;
586 else if (devices[i].bus_num == 0)
587 cs_pin = spi0_standard_cs[devices[i].chip_select];
588 else
589 cs_pin = spi1_standard_cs[devices[i].chip_select];
590
591 if (devices[i].bus_num == 0)
592 enable_spi0 = 1;
593 else
594 enable_spi1 = 1;
595
596 /* enable chip-select pin */
597 at91_set_gpio_output(cs_pin, 1);
598
599 /* pass chip-select pin to driver */
600 devices[i].controller_data = (void *) cs_pin;
601 }
602
603 spi_register_board_info(devices, nr_devices);
604
605 /* Configure SPI bus(es) */
606 if (enable_spi0) {
607 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
608 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
609 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
610
611 platform_device_register(&at91cap9_spi0_device);
612 }
613 if (enable_spi1) {
614 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
615 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
616 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
617
618 platform_device_register(&at91cap9_spi1_device);
619 }
620}
621#else
622void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
623#endif
624
625
626/* --------------------------------------------------------------------
627 * Timer/Counter block
628 * -------------------------------------------------------------------- */
629
630#ifdef CONFIG_ATMEL_TCLIB
631
632static struct resource tcb_resources[] = {
633 [0] = {
634 .start = AT91CAP9_BASE_TCB0,
635 .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
636 .flags = IORESOURCE_MEM,
637 },
638 [1] = {
639 .start = AT91CAP9_ID_TCB,
640 .end = AT91CAP9_ID_TCB,
641 .flags = IORESOURCE_IRQ,
642 },
643};
644
645static struct platform_device at91cap9_tcb_device = {
646 .name = "atmel_tcb",
647 .id = 0,
648 .resource = tcb_resources,
649 .num_resources = ARRAY_SIZE(tcb_resources),
650};
651
652static void __init at91_add_device_tc(void)
653{
654 platform_device_register(&at91cap9_tcb_device);
655}
656#else
657static void __init at91_add_device_tc(void) { }
658#endif
659
660
661/* --------------------------------------------------------------------
662 * RTT
663 * -------------------------------------------------------------------- */
664
665static struct resource rtt_resources[] = {
666 {
667 .start = AT91_BASE_SYS + AT91_RTT,
668 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
669 .flags = IORESOURCE_MEM,
670 }
671};
672
673static struct platform_device at91cap9_rtt_device = {
674 .name = "at91_rtt",
675 .id = 0,
676 .resource = rtt_resources,
677 .num_resources = ARRAY_SIZE(rtt_resources),
678};
679
680static void __init at91_add_device_rtt(void)
681{
682 platform_device_register(&at91cap9_rtt_device);
683}
684
685
686/* --------------------------------------------------------------------
687 * Watchdog
688 * -------------------------------------------------------------------- */
689
690#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
691static struct platform_device at91cap9_wdt_device = {
692 .name = "at91_wdt",
693 .id = -1,
694 .num_resources = 0,
695};
696
697static void __init at91_add_device_watchdog(void)
698{
699 platform_device_register(&at91cap9_wdt_device);
700}
701#else
702static void __init at91_add_device_watchdog(void) {}
703#endif
704
705
706/* --------------------------------------------------------------------
707 * PWM
708 * --------------------------------------------------------------------*/
709
710#if defined(CONFIG_ATMEL_PWM)
711static u32 pwm_mask;
712
713static struct resource pwm_resources[] = {
714 [0] = {
715 .start = AT91CAP9_BASE_PWMC,
716 .end = AT91CAP9_BASE_PWMC + SZ_16K - 1,
717 .flags = IORESOURCE_MEM,
718 },
719 [1] = {
720 .start = AT91CAP9_ID_PWMC,
721 .end = AT91CAP9_ID_PWMC,
722 .flags = IORESOURCE_IRQ,
723 },
724};
725
726static struct platform_device at91cap9_pwm0_device = {
727 .name = "atmel_pwm",
728 .id = -1,
729 .dev = {
730 .platform_data = &pwm_mask,
731 },
732 .resource = pwm_resources,
733 .num_resources = ARRAY_SIZE(pwm_resources),
734};
735
736void __init at91_add_device_pwm(u32 mask)
737{
738 if (mask & (1 << AT91_PWM0))
739 at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */
740
741 if (mask & (1 << AT91_PWM1))
742 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
743
744 if (mask & (1 << AT91_PWM2))
745 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
746
747 if (mask & (1 << AT91_PWM3))
748 at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */
749
750 pwm_mask = mask;
751
752 platform_device_register(&at91cap9_pwm0_device);
753}
754#else
755void __init at91_add_device_pwm(u32 mask) {}
756#endif
757
758
759
760/* --------------------------------------------------------------------
761 * AC97
762 * -------------------------------------------------------------------- */
763
764#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
765static u64 ac97_dmamask = DMA_BIT_MASK(32);
766static struct ac97c_platform_data ac97_data;
767
768static struct resource ac97_resources[] = {
769 [0] = {
770 .start = AT91CAP9_BASE_AC97C,
771 .end = AT91CAP9_BASE_AC97C + SZ_16K - 1,
772 .flags = IORESOURCE_MEM,
773 },
774 [1] = {
775 .start = AT91CAP9_ID_AC97C,
776 .end = AT91CAP9_ID_AC97C,
777 .flags = IORESOURCE_IRQ,
778 },
779};
780
781static struct platform_device at91cap9_ac97_device = {
782 .name = "atmel_ac97c",
783 .id = 1,
784 .dev = {
785 .dma_mask = &ac97_dmamask,
786 .coherent_dma_mask = DMA_BIT_MASK(32),
787 .platform_data = &ac97_data,
788 },
789 .resource = ac97_resources,
790 .num_resources = ARRAY_SIZE(ac97_resources),
791};
792
793void __init at91_add_device_ac97(struct ac97c_platform_data *data)
794{
795 if (!data)
796 return;
797
798 at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */
799 at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */
800 at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */
801 at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */
802
803 /* reset */
804 if (data->reset_pin)
805 at91_set_gpio_output(data->reset_pin, 0);
806
807 ac97_data = *data;
808 platform_device_register(&at91cap9_ac97_device);
809}
810#else
811void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
812#endif
813
814
815/* --------------------------------------------------------------------
816 * LCD Controller
817 * -------------------------------------------------------------------- */
818
819#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
820static u64 lcdc_dmamask = DMA_BIT_MASK(32);
821static struct atmel_lcdfb_info lcdc_data;
822
823static struct resource lcdc_resources[] = {
824 [0] = {
825 .start = AT91CAP9_LCDC_BASE,
826 .end = AT91CAP9_LCDC_BASE + SZ_4K - 1,
827 .flags = IORESOURCE_MEM,
828 },
829 [1] = {
830 .start = AT91CAP9_ID_LCDC,
831 .end = AT91CAP9_ID_LCDC,
832 .flags = IORESOURCE_IRQ,
833 },
834};
835
836static struct platform_device at91_lcdc_device = {
837 .name = "atmel_lcdfb",
838 .id = 0,
839 .dev = {
840 .dma_mask = &lcdc_dmamask,
841 .coherent_dma_mask = DMA_BIT_MASK(32),
842 .platform_data = &lcdc_data,
843 },
844 .resource = lcdc_resources,
845 .num_resources = ARRAY_SIZE(lcdc_resources),
846};
847
848void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
849{
850 if (!data)
851 return;
852
853 if (cpu_is_at91cap9_revB())
854 irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
855
856 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
857 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
858 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
859 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
860 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
861 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
862 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
863 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
864 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
865 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
866 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
867 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
868 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
869 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
870 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
871 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
872 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
873 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
874 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
875 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
876 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
877 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
878
879 lcdc_data = *data;
880 platform_device_register(&at91_lcdc_device);
881}
882#else
883void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
884#endif
885
886
887/* --------------------------------------------------------------------
888 * SSC -- Synchronous Serial Controller
889 * -------------------------------------------------------------------- */
890
891#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
892static u64 ssc0_dmamask = DMA_BIT_MASK(32);
893
894static struct resource ssc0_resources[] = {
895 [0] = {
896 .start = AT91CAP9_BASE_SSC0,
897 .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
898 .flags = IORESOURCE_MEM,
899 },
900 [1] = {
901 .start = AT91CAP9_ID_SSC0,
902 .end = AT91CAP9_ID_SSC0,
903 .flags = IORESOURCE_IRQ,
904 },
905};
906
907static struct platform_device at91cap9_ssc0_device = {
908 .name = "ssc",
909 .id = 0,
910 .dev = {
911 .dma_mask = &ssc0_dmamask,
912 .coherent_dma_mask = DMA_BIT_MASK(32),
913 },
914 .resource = ssc0_resources,
915 .num_resources = ARRAY_SIZE(ssc0_resources),
916};
917
918static inline void configure_ssc0_pins(unsigned pins)
919{
920 if (pins & ATMEL_SSC_TF)
921 at91_set_A_periph(AT91_PIN_PB0, 1);
922 if (pins & ATMEL_SSC_TK)
923 at91_set_A_periph(AT91_PIN_PB1, 1);
924 if (pins & ATMEL_SSC_TD)
925 at91_set_A_periph(AT91_PIN_PB2, 1);
926 if (pins & ATMEL_SSC_RD)
927 at91_set_A_periph(AT91_PIN_PB3, 1);
928 if (pins & ATMEL_SSC_RK)
929 at91_set_A_periph(AT91_PIN_PB4, 1);
930 if (pins & ATMEL_SSC_RF)
931 at91_set_A_periph(AT91_PIN_PB5, 1);
932}
933
934static u64 ssc1_dmamask = DMA_BIT_MASK(32);
935
936static struct resource ssc1_resources[] = {
937 [0] = {
938 .start = AT91CAP9_BASE_SSC1,
939 .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
940 .flags = IORESOURCE_MEM,
941 },
942 [1] = {
943 .start = AT91CAP9_ID_SSC1,
944 .end = AT91CAP9_ID_SSC1,
945 .flags = IORESOURCE_IRQ,
946 },
947};
948
949static struct platform_device at91cap9_ssc1_device = {
950 .name = "ssc",
951 .id = 1,
952 .dev = {
953 .dma_mask = &ssc1_dmamask,
954 .coherent_dma_mask = DMA_BIT_MASK(32),
955 },
956 .resource = ssc1_resources,
957 .num_resources = ARRAY_SIZE(ssc1_resources),
958};
959
960static inline void configure_ssc1_pins(unsigned pins)
961{
962 if (pins & ATMEL_SSC_TF)
963 at91_set_A_periph(AT91_PIN_PB6, 1);
964 if (pins & ATMEL_SSC_TK)
965 at91_set_A_periph(AT91_PIN_PB7, 1);
966 if (pins & ATMEL_SSC_TD)
967 at91_set_A_periph(AT91_PIN_PB8, 1);
968 if (pins & ATMEL_SSC_RD)
969 at91_set_A_periph(AT91_PIN_PB9, 1);
970 if (pins & ATMEL_SSC_RK)
971 at91_set_A_periph(AT91_PIN_PB10, 1);
972 if (pins & ATMEL_SSC_RF)
973 at91_set_A_periph(AT91_PIN_PB11, 1);
974}
975
976/*
977 * SSC controllers are accessed through library code, instead of any
978 * kind of all-singing/all-dancing driver. For example one could be
979 * used by a particular I2S audio codec's driver, while another one
980 * on the same system might be used by a custom data capture driver.
981 */
982void __init at91_add_device_ssc(unsigned id, unsigned pins)
983{
984 struct platform_device *pdev;
985
986 /*
987 * NOTE: caller is responsible for passing information matching
988 * "pins" to whatever will be using each particular controller.
989 */
990 switch (id) {
991 case AT91CAP9_ID_SSC0:
992 pdev = &at91cap9_ssc0_device;
993 configure_ssc0_pins(pins);
994 break;
995 case AT91CAP9_ID_SSC1:
996 pdev = &at91cap9_ssc1_device;
997 configure_ssc1_pins(pins);
998 break;
999 default:
1000 return;
1001 }
1002
1003 platform_device_register(pdev);
1004}
1005
1006#else
1007void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1008#endif
1009
1010
1011/* --------------------------------------------------------------------
1012 * UART
1013 * -------------------------------------------------------------------- */
1014
1015#if defined(CONFIG_SERIAL_ATMEL)
1016static struct resource dbgu_resources[] = {
1017 [0] = {
1018 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1019 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1020 .flags = IORESOURCE_MEM,
1021 },
1022 [1] = {
1023 .start = AT91_ID_SYS,
1024 .end = AT91_ID_SYS,
1025 .flags = IORESOURCE_IRQ,
1026 },
1027};
1028
1029static struct atmel_uart_data dbgu_data = {
1030 .use_dma_tx = 0,
1031 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1032 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1033};
1034
1035static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1036
1037static struct platform_device at91cap9_dbgu_device = {
1038 .name = "atmel_usart",
1039 .id = 0,
1040 .dev = {
1041 .dma_mask = &dbgu_dmamask,
1042 .coherent_dma_mask = DMA_BIT_MASK(32),
1043 .platform_data = &dbgu_data,
1044 },
1045 .resource = dbgu_resources,
1046 .num_resources = ARRAY_SIZE(dbgu_resources),
1047};
1048
1049static inline void configure_dbgu_pins(void)
1050{
1051 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1052 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1053}
1054
1055static struct resource uart0_resources[] = {
1056 [0] = {
1057 .start = AT91CAP9_BASE_US0,
1058 .end = AT91CAP9_BASE_US0 + SZ_16K - 1,
1059 .flags = IORESOURCE_MEM,
1060 },
1061 [1] = {
1062 .start = AT91CAP9_ID_US0,
1063 .end = AT91CAP9_ID_US0,
1064 .flags = IORESOURCE_IRQ,
1065 },
1066};
1067
1068static struct atmel_uart_data uart0_data = {
1069 .use_dma_tx = 1,
1070 .use_dma_rx = 1,
1071};
1072
1073static u64 uart0_dmamask = DMA_BIT_MASK(32);
1074
1075static struct platform_device at91cap9_uart0_device = {
1076 .name = "atmel_usart",
1077 .id = 1,
1078 .dev = {
1079 .dma_mask = &uart0_dmamask,
1080 .coherent_dma_mask = DMA_BIT_MASK(32),
1081 .platform_data = &uart0_data,
1082 },
1083 .resource = uart0_resources,
1084 .num_resources = ARRAY_SIZE(uart0_resources),
1085};
1086
1087static inline void configure_usart0_pins(unsigned pins)
1088{
1089 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
1090 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
1091
1092 if (pins & ATMEL_UART_RTS)
1093 at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */
1094 if (pins & ATMEL_UART_CTS)
1095 at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */
1096}
1097
1098static struct resource uart1_resources[] = {
1099 [0] = {
1100 .start = AT91CAP9_BASE_US1,
1101 .end = AT91CAP9_BASE_US1 + SZ_16K - 1,
1102 .flags = IORESOURCE_MEM,
1103 },
1104 [1] = {
1105 .start = AT91CAP9_ID_US1,
1106 .end = AT91CAP9_ID_US1,
1107 .flags = IORESOURCE_IRQ,
1108 },
1109};
1110
1111static struct atmel_uart_data uart1_data = {
1112 .use_dma_tx = 1,
1113 .use_dma_rx = 1,
1114};
1115
1116static u64 uart1_dmamask = DMA_BIT_MASK(32);
1117
1118static struct platform_device at91cap9_uart1_device = {
1119 .name = "atmel_usart",
1120 .id = 2,
1121 .dev = {
1122 .dma_mask = &uart1_dmamask,
1123 .coherent_dma_mask = DMA_BIT_MASK(32),
1124 .platform_data = &uart1_data,
1125 },
1126 .resource = uart1_resources,
1127 .num_resources = ARRAY_SIZE(uart1_resources),
1128};
1129
1130static inline void configure_usart1_pins(unsigned pins)
1131{
1132 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1133 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1134
1135 if (pins & ATMEL_UART_RTS)
1136 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1137 if (pins & ATMEL_UART_CTS)
1138 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1139}
1140
1141static struct resource uart2_resources[] = {
1142 [0] = {
1143 .start = AT91CAP9_BASE_US2,
1144 .end = AT91CAP9_BASE_US2 + SZ_16K - 1,
1145 .flags = IORESOURCE_MEM,
1146 },
1147 [1] = {
1148 .start = AT91CAP9_ID_US2,
1149 .end = AT91CAP9_ID_US2,
1150 .flags = IORESOURCE_IRQ,
1151 },
1152};
1153
1154static struct atmel_uart_data uart2_data = {
1155 .use_dma_tx = 1,
1156 .use_dma_rx = 1,
1157};
1158
1159static u64 uart2_dmamask = DMA_BIT_MASK(32);
1160
1161static struct platform_device at91cap9_uart2_device = {
1162 .name = "atmel_usart",
1163 .id = 3,
1164 .dev = {
1165 .dma_mask = &uart2_dmamask,
1166 .coherent_dma_mask = DMA_BIT_MASK(32),
1167 .platform_data = &uart2_data,
1168 },
1169 .resource = uart2_resources,
1170 .num_resources = ARRAY_SIZE(uart2_resources),
1171};
1172
1173static inline void configure_usart2_pins(unsigned pins)
1174{
1175 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1176 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1177
1178 if (pins & ATMEL_UART_RTS)
1179 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1180 if (pins & ATMEL_UART_CTS)
1181 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1182}
1183
1184static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1185struct platform_device *atmel_default_console_device; /* the serial console device */
1186
1187void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1188{
1189 struct platform_device *pdev;
1190 struct atmel_uart_data *pdata;
1191
1192 switch (id) {
1193 case 0: /* DBGU */
1194 pdev = &at91cap9_dbgu_device;
1195 configure_dbgu_pins();
1196 break;
1197 case AT91CAP9_ID_US0:
1198 pdev = &at91cap9_uart0_device;
1199 configure_usart0_pins(pins);
1200 break;
1201 case AT91CAP9_ID_US1:
1202 pdev = &at91cap9_uart1_device;
1203 configure_usart1_pins(pins);
1204 break;
1205 case AT91CAP9_ID_US2:
1206 pdev = &at91cap9_uart2_device;
1207 configure_usart2_pins(pins);
1208 break;
1209 default:
1210 return;
1211 }
1212 pdata = pdev->dev.platform_data;
1213 pdata->num = portnr; /* update to mapped ID */
1214
1215 if (portnr < ATMEL_MAX_UART)
1216 at91_uarts[portnr] = pdev;
1217}
1218
1219void __init at91_set_serial_console(unsigned portnr)
1220{
1221 if (portnr < ATMEL_MAX_UART) {
1222 atmel_default_console_device = at91_uarts[portnr];
1223 at91cap9_set_console_clock(at91_uarts[portnr]->id);
1224 }
1225}
1226
1227void __init at91_add_device_serial(void)
1228{
1229 int i;
1230
1231 for (i = 0; i < ATMEL_MAX_UART; i++) {
1232 if (at91_uarts[i])
1233 platform_device_register(at91_uarts[i]);
1234 }
1235
1236 if (!atmel_default_console_device)
1237 printk(KERN_INFO "AT91: No default serial console defined.\n");
1238}
1239#else
1240void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1241void __init at91_set_serial_console(unsigned portnr) {}
1242void __init at91_add_device_serial(void) {}
1243#endif
1244
1245
1246/* -------------------------------------------------------------------- */
1247/*
1248 * These devices are always present and don't need any board-specific
1249 * setup.
1250 */
1251static int __init at91_add_standard_devices(void)
1252{
1253 at91_add_device_rtt();
1254 at91_add_device_watchdog();
1255 at91_add_device_tc();
1256 return 0;
1257}
1258
1259arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
new file mode 100644
index 00000000000..679b0b743e9
--- /dev/null
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -0,0 +1,398 @@
1/*
2 * linux/arch/arm/mach-at91/board-cap9adk.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2005 SAN People
7 * Copyright (C) 2007 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/spi/spi.h>
30#include <linux/spi/ads7846.h>
31#include <linux/fb.h>
32#include <linux/mtd/physmap.h>
33
34#include <video/atmel_lcdc.h>
35
36#include <mach/hardware.h>
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42
43#include <mach/board.h>
44#include <mach/gpio.h>
45#include <mach/at91cap9_matrix.h>
46#include <mach/at91sam9_smc.h>
47#include <mach/system_rev.h>
48
49#include "sam9_smc.h"
50#include "generic.h"
51
52
53static void __init cap9adk_init_early(void)
54{
55 /* Initialize processor: 12 MHz crystal */
56 at91_initialize(12000000);
57
58 /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
59 at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
60 /* ... POWER LED always on */
61 at91_set_gpio_output(AT91_PIN_PC29, 1);
62
63 /* Setup the serial ports and console */
64 at91_register_uart(0, 0, 0); /* DBGU = ttyS0 */
65 at91_set_serial_console(0);
66}
67
68/*
69 * USB Host port
70 */
71static struct at91_usbh_data __initdata cap9adk_usbh_data = {
72 .ports = 2,
73};
74
75/*
76 * USB HS Device port
77 */
78static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
79 .vbus_pin = AT91_PIN_PB31,
80};
81
82/*
83 * ADS7846 Touchscreen
84 */
85#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
86static int ads7843_pendown_state(void)
87{
88 return !at91_get_gpio_value(AT91_PIN_PC4); /* Touchscreen PENIRQ */
89}
90
91static struct ads7846_platform_data ads_info = {
92 .model = 7843,
93 .x_min = 150,
94 .x_max = 3830,
95 .y_min = 190,
96 .y_max = 3830,
97 .vref_delay_usecs = 100,
98 .x_plate_ohms = 450,
99 .y_plate_ohms = 250,
100 .pressure_max = 15000,
101 .debounce_max = 1,
102 .debounce_rep = 0,
103 .debounce_tol = (~0),
104 .get_pendown_state = ads7843_pendown_state,
105};
106
107static void __init cap9adk_add_device_ts(void)
108{
109 at91_set_gpio_input(AT91_PIN_PC4, 1); /* Touchscreen PENIRQ */
110 at91_set_gpio_input(AT91_PIN_PC5, 1); /* Touchscreen BUSY */
111}
112#else
113static void __init cap9adk_add_device_ts(void) {}
114#endif
115
116
117/*
118 * SPI devices.
119 */
120static struct spi_board_info cap9adk_spi_devices[] = {
121#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
122 { /* DataFlash card */
123 .modalias = "mtd_dataflash",
124 .chip_select = 0,
125 .max_speed_hz = 15 * 1000 * 1000,
126 .bus_num = 0,
127 },
128#endif
129#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
130 {
131 .modalias = "ads7846",
132 .chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
133 .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
134 .bus_num = 0,
135 .platform_data = &ads_info,
136 .irq = AT91_PIN_PC4,
137 },
138#endif
139};
140
141
142/*
143 * MCI (SD/MMC)
144 */
145static struct at91_mmc_data __initdata cap9adk_mmc_data = {
146 .wire4 = 1,
147// .det_pin = ... not connected
148// .wp_pin = ... not connected
149// .vcc_pin = ... not connected
150};
151
152
153/*
154 * MACB Ethernet device
155 */
156static struct at91_eth_data __initdata cap9adk_macb_data = {
157 .is_rmii = 1,
158};
159
160
161/*
162 * NAND flash
163 */
164static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
165 {
166 .name = "NAND partition",
167 .offset = 0,
168 .size = MTDPART_SIZ_FULL,
169 },
170};
171
172static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
173{
174 *num_partitions = ARRAY_SIZE(cap9adk_nand_partitions);
175 return cap9adk_nand_partitions;
176}
177
178static struct atmel_nand_data __initdata cap9adk_nand_data = {
179 .ale = 21,
180 .cle = 22,
181// .det_pin = ... not connected
182// .rdy_pin = ... not connected
183 .enable_pin = AT91_PIN_PD15,
184 .partition_info = nand_partitions,
185};
186
187static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
188 .ncs_read_setup = 1,
189 .nrd_setup = 2,
190 .ncs_write_setup = 1,
191 .nwe_setup = 2,
192
193 .ncs_read_pulse = 6,
194 .nrd_pulse = 4,
195 .ncs_write_pulse = 6,
196 .nwe_pulse = 4,
197
198 .read_cycle = 8,
199 .write_cycle = 8,
200
201 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
202 .tdf_cycles = 1,
203};
204
205static void __init cap9adk_add_device_nand(void)
206{
207 unsigned long csa;
208
209 csa = at91_sys_read(AT91_MATRIX_EBICSA);
210 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
211
212 cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
213 /* setup bus-width (8 or 16) */
214 if (cap9adk_nand_data.bus_width_16)
215 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
216 else
217 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
218
219 /* configure chip-select 3 (NAND) */
220 sam9_smc_configure(3, &cap9adk_nand_smc_config);
221
222 at91_add_device_nand(&cap9adk_nand_data);
223}
224
225
226/*
227 * NOR flash
228 */
229static struct mtd_partition cap9adk_nor_partitions[] = {
230 {
231 .name = "NOR partition",
232 .offset = 0,
233 .size = MTDPART_SIZ_FULL,
234 },
235};
236
237static struct physmap_flash_data cap9adk_nor_data = {
238 .width = 2,
239 .parts = cap9adk_nor_partitions,
240 .nr_parts = ARRAY_SIZE(cap9adk_nor_partitions),
241};
242
243#define NOR_BASE AT91_CHIPSELECT_0
244#define NOR_SIZE SZ_8M
245
246static struct resource nor_flash_resources[] = {
247 {
248 .start = NOR_BASE,
249 .end = NOR_BASE + NOR_SIZE - 1,
250 .flags = IORESOURCE_MEM,
251 }
252};
253
254static struct platform_device cap9adk_nor_flash = {
255 .name = "physmap-flash",
256 .id = 0,
257 .dev = {
258 .platform_data = &cap9adk_nor_data,
259 },
260 .resource = nor_flash_resources,
261 .num_resources = ARRAY_SIZE(nor_flash_resources),
262};
263
264static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
265 .ncs_read_setup = 2,
266 .nrd_setup = 4,
267 .ncs_write_setup = 2,
268 .nwe_setup = 4,
269
270 .ncs_read_pulse = 10,
271 .nrd_pulse = 8,
272 .ncs_write_pulse = 10,
273 .nwe_pulse = 8,
274
275 .read_cycle = 16,
276 .write_cycle = 16,
277
278 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
279 .tdf_cycles = 1,
280};
281
282static __init void cap9adk_add_device_nor(void)
283{
284 unsigned long csa;
285
286 csa = at91_sys_read(AT91_MATRIX_EBICSA);
287 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
288
289 /* configure chip-select 0 (NOR) */
290 sam9_smc_configure(0, &cap9adk_nor_smc_config);
291
292 platform_device_register(&cap9adk_nor_flash);
293}
294
295
296/*
297 * LCD Controller
298 */
299#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
300static struct fb_videomode at91_tft_vga_modes[] = {
301 {
302 .name = "TX09D50VM1CCA @ 60",
303 .refresh = 60,
304 .xres = 240, .yres = 320,
305 .pixclock = KHZ2PICOS(4965),
306
307 .left_margin = 1, .right_margin = 33,
308 .upper_margin = 1, .lower_margin = 0,
309 .hsync_len = 5, .vsync_len = 1,
310
311 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
312 .vmode = FB_VMODE_NONINTERLACED,
313 },
314};
315
316static struct fb_monspecs at91fb_default_monspecs = {
317 .manufacturer = "HIT",
318 .monitor = "TX09D70VM1CCA",
319
320 .modedb = at91_tft_vga_modes,
321 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
322 .hfmin = 15000,
323 .hfmax = 64000,
324 .vfmin = 50,
325 .vfmax = 150,
326};
327
328#define AT91CAP9_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
329 | ATMEL_LCDC_DISTYPE_TFT \
330 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
331
332static void at91_lcdc_power_control(int on)
333{
334 if (on)
335 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
336 else
337 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
338}
339
340/* Driver datas */
341static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
342 .default_bpp = 16,
343 .default_dmacon = ATMEL_LCDC_DMAEN,
344 .default_lcdcon2 = AT91CAP9_DEFAULT_LCDCON2,
345 .default_monspecs = &at91fb_default_monspecs,
346 .atmel_lcdfb_power_control = at91_lcdc_power_control,
347 .guard_time = 1,
348};
349
350#else
351static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
352#endif
353
354
355/*
356 * AC97
357 */
358static struct ac97c_platform_data cap9adk_ac97_data = {
359// .reset_pin = ... not connected
360};
361
362
363static void __init cap9adk_board_init(void)
364{
365 /* Serial */
366 at91_add_device_serial();
367 /* USB Host */
368 at91_add_device_usbh(&cap9adk_usbh_data);
369 /* USB HS */
370 at91_add_device_usba(&cap9adk_usba_udc_data);
371 /* SPI */
372 at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
373 /* Touchscreen */
374 cap9adk_add_device_ts();
375 /* MMC */
376 at91_add_device_mmc(1, &cap9adk_mmc_data);
377 /* Ethernet */
378 at91_add_device_eth(&cap9adk_macb_data);
379 /* NAND */
380 cap9adk_add_device_nand();
381 /* NOR Flash */
382 cap9adk_add_device_nor();
383 /* I2C */
384 at91_add_device_i2c(NULL, 0);
385 /* LCD Controller */
386 at91_add_device_lcdc(&cap9adk_lcdc_data);
387 /* AC97 */
388 at91_add_device_ac97(&cap9adk_ac97_data);
389}
390
391MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
392 /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
393 .timer = &at91sam926x_timer,
394 .map_io = at91_map_io,
395 .init_early = cap9adk_init_early,
396 .init_irq = at91_init_irq_default,
397 .init_machine = cap9adk_board_init,
398MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
new file mode 100644
index 00000000000..8c4c1a02c4b
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -0,0 +1,230 @@
1/*
2 * linux/arch/arm/mach-at91/board-usb-a9260.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2007 Calao-systems
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <linux/clk.h>
32
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
42#include <mach/board.h>
43#include <mach/gpio.h>
44#include <mach/at91sam9_smc.h>
45#include <mach/at91_shdwc.h>
46
47#include "sam9_smc.h"
48#include "generic.h"
49
50
51static void __init ek_init_early(void)
52{
53 /* Initialize processor: 12.000 MHz crystal */
54 at91_initialize(12000000);
55
56 /* DBGU on ttyS0. (Rx & Tx only) */
57 at91_register_uart(0, 0, 0);
58
59 /* set serial console to ttyS0 (ie, DBGU) */
60 at91_set_serial_console(0);
61}
62
63/*
64 * USB Host port
65 */
66static struct at91_usbh_data __initdata ek_usbh_data = {
67 .ports = 2,
68};
69
70/*
71 * USB Device port
72 */
73static struct at91_udc_data __initdata ek_udc_data = {
74 .vbus_pin = AT91_PIN_PC5,
75 .pullup_pin = 0, /* pull-up driven by UDC */
76};
77
78/*
79 * MACB Ethernet device
80 */
81static struct at91_eth_data __initdata ek_macb_data = {
82 .phy_irq_pin = AT91_PIN_PA31,
83 .is_rmii = 1,
84};
85
86/*
87 * NAND flash
88 */
89static struct mtd_partition __initdata ek_nand_partition[] = {
90 {
91 .name = "Uboot & Kernel",
92 .offset = 0,
93 .size = SZ_16M,
94 },
95 {
96 .name = "Root FS",
97 .offset = MTDPART_OFS_NXTBLK,
98 .size = 120 * SZ_1M,
99 },
100 {
101 .name = "FS",
102 .offset = MTDPART_OFS_NXTBLK,
103 .size = 120 * SZ_1M,
104 }
105};
106
107static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
108{
109 *num_partitions = ARRAY_SIZE(ek_nand_partition);
110 return ek_nand_partition;
111}
112
113static struct atmel_nand_data __initdata ek_nand_data = {
114 .ale = 21,
115 .cle = 22,
116// .det_pin = ... not connected
117 .rdy_pin = AT91_PIN_PC13,
118 .enable_pin = AT91_PIN_PC14,
119 .partition_info = nand_partitions,
120};
121
122static struct sam9_smc_config __initdata ek_nand_smc_config = {
123 .ncs_read_setup = 0,
124 .nrd_setup = 1,
125 .ncs_write_setup = 0,
126 .nwe_setup = 1,
127
128 .ncs_read_pulse = 3,
129 .nrd_pulse = 3,
130 .ncs_write_pulse = 3,
131 .nwe_pulse = 3,
132
133 .read_cycle = 5,
134 .write_cycle = 5,
135
136 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
137 .tdf_cycles = 2,
138};
139
140static void __init ek_add_device_nand(void)
141{
142 /* configure chip-select 3 (NAND) */
143 sam9_smc_configure(3, &ek_nand_smc_config);
144
145 at91_add_device_nand(&ek_nand_data);
146}
147
148/*
149 * GPIO Buttons
150 */
151
152#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
153static struct gpio_keys_button ek_buttons[] = {
154 { /* USER PUSH BUTTON */
155 .code = KEY_ENTER,
156 .gpio = AT91_PIN_PB10,
157 .active_low = 1,
158 .desc = "user_pb",
159 .wakeup = 1,
160 }
161};
162
163static struct gpio_keys_platform_data ek_button_data = {
164 .buttons = ek_buttons,
165 .nbuttons = ARRAY_SIZE(ek_buttons),
166};
167
168static struct platform_device ek_button_device = {
169 .name = "gpio-keys",
170 .id = -1,
171 .num_resources = 0,
172 .dev = {
173 .platform_data = &ek_button_data,
174 }
175};
176
177static void __init ek_add_device_buttons(void)
178{
179 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
180 at91_set_deglitch(AT91_PIN_PB10, 1);
181
182 platform_device_register(&ek_button_device);
183}
184#else
185static void __init ek_add_device_buttons(void) {}
186#endif
187
188/*
189 * LEDs
190 */
191static struct gpio_led ek_leds[] = {
192 { /* user_led (green) */
193 .name = "user_led",
194 .gpio = AT91_PIN_PB21,
195 .active_low = 0,
196 .default_trigger = "heartbeat",
197 }
198};
199
200static void __init ek_board_init(void)
201{
202 /* Serial */
203 at91_add_device_serial();
204 /* USB Host */
205 at91_add_device_usbh(&ek_usbh_data);
206 /* USB Device */
207 at91_add_device_udc(&ek_udc_data);
208 /* NAND */
209 ek_add_device_nand();
210 /* I2C */
211 at91_add_device_i2c(NULL, 0);
212 /* Ethernet */
213 at91_add_device_eth(&ek_macb_data);
214 /* Push Buttons */
215 ek_add_device_buttons();
216 /* LEDs */
217 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
218 /* shutdown controller, wakeup button (5 msec low) */
219 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
220 | AT91_SHDW_RTTWKEN);
221}
222
223MACHINE_START(USB_A9260, "CALAO USB_A9260")
224 /* Maintainer: calao-systems */
225 .timer = &at91sam926x_timer,
226 .map_io = at91_map_io,
227 .init_early = ek_init_early,
228 .init_irq = at91_init_irq_default,
229 .init_machine = ek_board_init,
230MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
new file mode 100644
index 00000000000..25e793782a4
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -0,0 +1,246 @@
1/*
2 * linux/arch/arm/mach-at91/board-usb-a9263.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation.
6 * Copyright (C) 2007 Calao-systems
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/hardware.h>
41#include <mach/board.h>
42#include <mach/gpio.h>
43#include <mach/at91sam9_smc.h>
44#include <mach/at91_shdwc.h>
45
46#include "sam9_smc.h"
47#include "generic.h"
48
49
50static void __init ek_init_early(void)
51{
52 /* Initialize processor: 12.00 MHz crystal */
53 at91_initialize(12000000);
54
55 /* DBGU on ttyS0. (Rx & Tx only) */
56 at91_register_uart(0, 0, 0);
57
58 /* set serial console to ttyS0 (ie, DBGU) */
59 at91_set_serial_console(0);
60}
61
62/*
63 * USB Host port
64 */
65static struct at91_usbh_data __initdata ek_usbh_data = {
66 .ports = 2,
67};
68
69/*
70 * USB Device port
71 */
72static struct at91_udc_data __initdata ek_udc_data = {
73 .vbus_pin = AT91_PIN_PB11,
74 .pullup_pin = 0, /* pull-up driven by UDC */
75};
76
77/*
78 * SPI devices.
79 */
80static struct spi_board_info ek_spi_devices[] = {
81#if !defined(CONFIG_MMC_AT91)
82 { /* DataFlash chip */
83 .modalias = "mtd_dataflash",
84 .chip_select = 0,
85 .max_speed_hz = 15 * 1000 * 1000,
86 .bus_num = 0,
87 }
88#endif
89};
90
91/*
92 * MACB Ethernet device
93 */
94static struct at91_eth_data __initdata ek_macb_data = {
95 .phy_irq_pin = AT91_PIN_PE31,
96 .is_rmii = 1,
97};
98
99/*
100 * NAND flash
101 */
102static struct mtd_partition __initdata ek_nand_partition[] = {
103 {
104 .name = "Linux Kernel",
105 .offset = 0,
106 .size = SZ_16M,
107 },
108 {
109 .name = "Root FS",
110 .offset = MTDPART_OFS_NXTBLK,
111 .size = 120 * SZ_1M,
112 },
113 {
114 .name = "FS",
115 .offset = MTDPART_OFS_NXTBLK,
116 .size = 120 * SZ_1M,
117 }
118};
119
120static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
121{
122 *num_partitions = ARRAY_SIZE(ek_nand_partition);
123 return ek_nand_partition;
124}
125
126static struct atmel_nand_data __initdata ek_nand_data = {
127 .ale = 21,
128 .cle = 22,
129// .det_pin = ... not connected
130 .rdy_pin = AT91_PIN_PA22,
131 .enable_pin = AT91_PIN_PD15,
132 .partition_info = nand_partitions,
133};
134
135static struct sam9_smc_config __initdata ek_nand_smc_config = {
136 .ncs_read_setup = 0,
137 .nrd_setup = 1,
138 .ncs_write_setup = 0,
139 .nwe_setup = 1,
140
141 .ncs_read_pulse = 3,
142 .nrd_pulse = 3,
143 .ncs_write_pulse = 3,
144 .nwe_pulse = 3,
145
146 .read_cycle = 5,
147 .write_cycle = 5,
148
149 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
150 .tdf_cycles = 2,
151};
152
153static void __init ek_add_device_nand(void)
154{
155 /* configure chip-select 3 (NAND) */
156 sam9_smc_configure(3, &ek_nand_smc_config);
157
158 at91_add_device_nand(&ek_nand_data);
159}
160
161
162/*
163 * GPIO Buttons
164 */
165#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
166static struct gpio_keys_button ek_buttons[] = {
167 { /* USER PUSH BUTTON */
168 .code = KEY_ENTER,
169 .gpio = AT91_PIN_PB10,
170 .active_low = 1,
171 .desc = "user_pb",
172 .wakeup = 1,
173 }
174};
175
176static struct gpio_keys_platform_data ek_button_data = {
177 .buttons = ek_buttons,
178 .nbuttons = ARRAY_SIZE(ek_buttons),
179};
180
181static struct platform_device ek_button_device = {
182 .name = "gpio-keys",
183 .id = -1,
184 .num_resources = 0,
185 .dev = {
186 .platform_data = &ek_button_data,
187 }
188};
189
190static void __init ek_add_device_buttons(void)
191{
192 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
193 at91_set_deglitch(AT91_PIN_PB10, 1);
194
195 platform_device_register(&ek_button_device);
196}
197#else
198static void __init ek_add_device_buttons(void) {}
199#endif
200
201/*
202 * LEDs
203 */
204static struct gpio_led ek_leds[] = {
205 { /* user_led (green) */
206 .name = "user_led",
207 .gpio = AT91_PIN_PB21,
208 .active_low = 1,
209 .default_trigger = "heartbeat",
210 }
211};
212
213
214static void __init ek_board_init(void)
215{
216 /* Serial */
217 at91_add_device_serial();
218 /* USB Host */
219 at91_add_device_usbh(&ek_usbh_data);
220 /* USB Device */
221 at91_add_device_udc(&ek_udc_data);
222 /* SPI */
223 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
224 /* Ethernet */
225 at91_add_device_eth(&ek_macb_data);
226 /* NAND */
227 ek_add_device_nand();
228 /* I2C */
229 at91_add_device_i2c(NULL, 0);
230 /* Push Buttons */
231 ek_add_device_buttons();
232 /* LEDs */
233 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
234 /* shutdown controller, wakeup button (5 msec low) */
235 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
236 | AT91_SHDW_RTTWKEN);
237}
238
239MACHINE_START(USB_A9263, "CALAO USB_A9263")
240 /* Maintainer: calao-systems */
241 .timer = &at91sam926x_timer,
242 .map_io = at91_map_io,
243 .init_early = ek_init_early,
244 .init_irq = at91_init_irq_default,
245 .init_machine = ek_board_init,
246MACHINE_END
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
new file mode 100644
index 00000000000..03566799d3b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -0,0 +1,53 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
19#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
20#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
21#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
22#define AT91_AIC_SRCTYPE_LOW (0 << 5)
23#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
24#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
25#define AT91_AIC_SRCTYPE_RISING (3 << 5)
26
27#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
28#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
29#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
30#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
31#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
32
33#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
34#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
35#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
36#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
37#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
38
39#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
40#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
41#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
42#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
43#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
44#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
45#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
46#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
47#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
48
49#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
50#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
51#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
new file mode 100644
index 00000000000..974d0bd05b5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_pit.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Periodic Interval Timer (PIT) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PIT_H
17#define AT91_PIT_H
18
19#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
20#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
21#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
22#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
23
24#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
25#define AT91_PIT_PITS (1 << 0) /* Timer Status */
26
27#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
28#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
29#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
30#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
31
32#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
new file mode 100644
index 00000000000..cbd2bf052c1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_rstc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Reset Controller (RSTC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RSTC_H
17#define AT91_RSTC_H
18
19#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
20#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
21#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
22#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
23#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
24
25#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
26#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
27#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
28#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
29#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
30#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
31#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
32#define AT91_RSTC_RSTTYP_USER (4 << 8)
33#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
34#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
35
36#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
37#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
38#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
39#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
40
41#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
new file mode 100644
index 00000000000..e56f4701a3e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -0,0 +1,75 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_rtc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Real Time Clock (RTC) - System peripheral registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RTC_H
17#define AT91_RTC_H
18
19#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
20#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
28#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
29#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
30#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
31
32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
34
35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
40
41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
42#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
43#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
44#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
45#define AT91_RTC_DAY (7 << 21) /* Current Day */
46#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
47
48#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
49#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
50#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
51#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
52
53#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
54#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
55#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
56
57#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
58#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
59#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
60#define AT91_RTC_SECEV (1 << 2) /* Second Event */
61#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
62#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
63
64#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
65#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
66#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
67#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
68
69#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
70#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
71#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
72#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
73#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
74
75#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
new file mode 100644
index 00000000000..c4ce07e8a8f
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_shdwc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Shutdown Controller (SHDWC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_SHDWC_H
17#define AT91_SHDWC_H
18
19#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
20#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
21#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
22
23#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
24#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
25#define AT91_SHDW_WKMODE0_NONE 0
26#define AT91_SHDW_WKMODE0_HIGH 1
27#define AT91_SHDW_WKMODE0_LOW 2
28#define AT91_SHDW_WKMODE0_ANYLEVEL 3
29#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
30#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
31#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
32
33#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
34#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
35#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
36#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
37
38#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
new file mode 100644
index 00000000000..2f6ba0c5636
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_spi.h
@@ -0,0 +1,81 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_spi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Serial Peripheral Interface (SPI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_SPI_H
17#define AT91_SPI_H
18
19#define AT91_SPI_CR 0x00 /* Control Register */
20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
21#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
22#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
23#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
24
25#define AT91_SPI_MR 0x04 /* Mode Register */
26#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
27#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
28#define AT91_SPI_PS_FIXED (0 << 1)
29#define AT91_SPI_PS_VARIABLE (1 << 1)
30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
35#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
36
37#define AT91_SPI_RDR 0x08 /* Receive Data Register */
38#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
39#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
40
41#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
42#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
43#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
44#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
45
46#define AT91_SPI_SR 0x10 /* Status Register */
47#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
48#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
49#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
50#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
51#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
52#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
53#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
54#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
55#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
56#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
57#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
58
59#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
60#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
61#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
62
63#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
64#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
65#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
66#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
67#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
68#define AT91_SPI_BITS_8 (0 << 4)
69#define AT91_SPI_BITS_9 (1 << 4)
70#define AT91_SPI_BITS_10 (2 << 4)
71#define AT91_SPI_BITS_11 (3 << 4)
72#define AT91_SPI_BITS_12 (4 << 4)
73#define AT91_SPI_BITS_13 (5 << 4)
74#define AT91_SPI_BITS_14 (6 << 4)
75#define AT91_SPI_BITS_15 (7 << 4)
76#define AT91_SPI_BITS_16 (8 << 4)
77#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
78#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
79#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
80
81#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h
new file mode 100644
index 00000000000..a81114c11c7
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ssc.h
@@ -0,0 +1,106 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_ssc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Serial Synchronous Controller (SSC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_SSC_H
16#define AT91_SSC_H
17
18#define AT91_SSC_CR 0x00 /* Control Register */
19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
20#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
21#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
22#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
23#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
24
25#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
26#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
27
28#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
29#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
30#define AT91_SSC_CKS_DIV (0 << 0)
31#define AT91_SSC_CKS_CLOCK (1 << 0)
32#define AT91_SSC_CKS_PIN (2 << 0)
33#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
34#define AT91_SSC_CKO_NONE (0 << 2)
35#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
37#define AT91_SSC_CKI_FALLING (0 << 5)
38#define AT91_SSC_CK_RISING (1 << 5)
39#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
40#define AT91_SSC_CKG_NONE (0 << 6)
41#define AT91_SSC_CKG_RFLOW (1 << 6)
42#define AT91_SSC_CKG_RFHIGH (2 << 6)
43#define AT91_SSC_START (0xf << 8) /* Start Selection */
44#define AT91_SSC_START_CONTINUOUS (0 << 8)
45#define AT91_SSC_START_TX_RX (1 << 8)
46#define AT91_SSC_START_LOW_RF (2 << 8)
47#define AT91_SSC_START_HIGH_RF (3 << 8)
48#define AT91_SSC_START_FALLING_RF (4 << 8)
49#define AT91_SSC_START_RISING_RF (5 << 8)
50#define AT91_SSC_START_LEVEL_RF (6 << 8)
51#define AT91_SSC_START_EDGE_RF (7 << 8)
52#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
53#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
54#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
55
56#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
57#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
58#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
59#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
60#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
61#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
62#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
63#define AT91_SSC_FSOS_NONE (0 << 20)
64#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
65#define AT91_SSC_FSOS_POSITIVE (2 << 20)
66#define AT91_SSC_FSOS_LOW (3 << 20)
67#define AT91_SSC_FSOS_HIGH (4 << 20)
68#define AT91_SSC_FSOS_TOGGLE (5 << 20)
69#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
70#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
71#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
72
73#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
74#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
75#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
76#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
77
78#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
79#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
80#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
81#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
82
83#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
84#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
85
86#define AT91_SSC_SR 0x40 /* Status Register */
87#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
88#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
89#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
90#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
91#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
92#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
93#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
94#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
95#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
96#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
97#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
98#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
99#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
100#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
101
102#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
103#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
104#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
105
106#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h
new file mode 100644
index 00000000000..46a317fd716
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_tc.h
@@ -0,0 +1,146 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_tc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Timer/Counter Unit (TC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_TC_H
16#define AT91_TC_H
17
18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
20
21#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
22#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
23#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
24#define AT91_TC_TC0XC0S_NONE (1 << 0)
25#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
26#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
27#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
28#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
29#define AT91_TC_TC1XC1S_NONE (1 << 2)
30#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
31#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
32#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
33#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
34#define AT91_TC_TC2XC2S_NONE (1 << 4)
35#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
36#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
37
38
39#define AT91_TC_CCR 0x00 /* Channel Control Register */
40#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
41#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
42#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
43
44#define AT91_TC_CMR 0x04 /* Channel Mode Register */
45#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
46#define AT91_TC_TIMER_CLOCK1 (0 << 0)
47#define AT91_TC_TIMER_CLOCK2 (1 << 0)
48#define AT91_TC_TIMER_CLOCK3 (2 << 0)
49#define AT91_TC_TIMER_CLOCK4 (3 << 0)
50#define AT91_TC_TIMER_CLOCK5 (4 << 0)
51#define AT91_TC_XC0 (5 << 0)
52#define AT91_TC_XC1 (6 << 0)
53#define AT91_TC_XC2 (7 << 0)
54#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
55#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
56#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
57#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
58#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
59#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
60#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
61#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
62#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
63#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
64
65#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
66#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
67#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
68#define AT91_TC_EEVTEDG_NONE (0 << 8)
69#define AT91_TC_EEVTEDG_RISING (1 << 8)
70#define AT91_TC_EEVTEDG_FALLING (2 << 8)
71#define AT91_TC_EEVTEDG_BOTH (3 << 8)
72#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
73#define AT91_TC_EEVT_TIOB (0 << 10)
74#define AT91_TC_EEVT_XC0 (1 << 10)
75#define AT91_TC_EEVT_XC1 (2 << 10)
76#define AT91_TC_EEVT_XC2 (3 << 10)
77#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
78#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
79#define AT91_TC_WAVESEL_UP (0 << 13)
80#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
81#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
82#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
83#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
84#define AT91_TC_ACPA_NONE (0 << 16)
85#define AT91_TC_ACPA_SET (1 << 16)
86#define AT91_TC_ACPA_CLEAR (2 << 16)
87#define AT91_TC_ACPA_TOGGLE (3 << 16)
88#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
89#define AT91_TC_ACPC_NONE (0 << 18)
90#define AT91_TC_ACPC_SET (1 << 18)
91#define AT91_TC_ACPC_CLEAR (2 << 18)
92#define AT91_TC_ACPC_TOGGLE (3 << 18)
93#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
94#define AT91_TC_AEEVT_NONE (0 << 20)
95#define AT91_TC_AEEVT_SET (1 << 20)
96#define AT91_TC_AEEVT_CLEAR (2 << 20)
97#define AT91_TC_AEEVT_TOGGLE (3 << 20)
98#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
99#define AT91_TC_ASWTRG_NONE (0 << 22)
100#define AT91_TC_ASWTRG_SET (1 << 22)
101#define AT91_TC_ASWTRG_CLEAR (2 << 22)
102#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
103#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
104#define AT91_TC_BCPB_NONE (0 << 24)
105#define AT91_TC_BCPB_SET (1 << 24)
106#define AT91_TC_BCPB_CLEAR (2 << 24)
107#define AT91_TC_BCPB_TOGGLE (3 << 24)
108#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
109#define AT91_TC_BCPC_NONE (0 << 26)
110#define AT91_TC_BCPC_SET (1 << 26)
111#define AT91_TC_BCPC_CLEAR (2 << 26)
112#define AT91_TC_BCPC_TOGGLE (3 << 26)
113#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
114#define AT91_TC_BEEVT_NONE (0 << 28)
115#define AT91_TC_BEEVT_SET (1 << 28)
116#define AT91_TC_BEEVT_CLEAR (2 << 28)
117#define AT91_TC_BEEVT_TOGGLE (3 << 28)
118#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
119#define AT91_TC_BSWTRG_NONE (0 << 30)
120#define AT91_TC_BSWTRG_SET (1 << 30)
121#define AT91_TC_BSWTRG_CLEAR (2 << 30)
122#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
123
124#define AT91_TC_CV 0x10 /* Counter Value */
125#define AT91_TC_RA 0x14 /* Register A */
126#define AT91_TC_RB 0x18 /* Register B */
127#define AT91_TC_RC 0x1c /* Register C */
128
129#define AT91_TC_SR 0x20 /* Status Register */
130#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
131#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
132#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
133#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
134#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
135#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
136#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
137#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
138#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
139#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
140#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
141
142#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
143#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
144#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
145
146#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h
new file mode 100644
index 00000000000..bb2880f6ba3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_twi.h
@@ -0,0 +1,68 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_twi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Two-wire Interface (TWI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_TWI_H
17#define AT91_TWI_H
18
19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
24#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */
25#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */
26#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
27
28#define AT91_TWI_MMR 0x04 /* Master Mode Register */
29#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
30#define AT91_TWI_IADRSZ_NO (0 << 8)
31#define AT91_TWI_IADRSZ_1 (1 << 8)
32#define AT91_TWI_IADRSZ_2 (2 << 8)
33#define AT91_TWI_IADRSZ_3 (3 << 8)
34#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
35#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
36
37#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */
38#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */
39
40#define AT91_TWI_IADR 0x0c /* Internal Address Register */
41
42#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
43#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
44#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
45#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
46
47#define AT91_TWI_SR 0x20 /* Status Register */
48#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
49#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
50#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
51#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */
52#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */
53#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */
54#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
55#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
56#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
57#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */
58#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */
59#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */
60
61#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
62#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
63#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
64#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
65#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
66
67#endif
68
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
new file mode 100644
index 00000000000..c5df1e8f195
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -0,0 +1,123 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * Common definitions.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_H
18#define AT91CAP9_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
24#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
25#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
26#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
27#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
28#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
29#define AT91CAP9_ID_US0 8 /* USART 0 */
30#define AT91CAP9_ID_US1 9 /* USART 1 */
31#define AT91CAP9_ID_US2 10 /* USART 2 */
32#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
33#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
34#define AT91CAP9_ID_CAN 13 /* CAN */
35#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
36#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
37#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
38#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
39#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
40#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
41#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
42#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
43#define AT91CAP9_ID_EMAC 22 /* Ethernet */
44#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
45#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
46#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
47#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
48#define AT91CAP9_ID_DMA 27 /* DMA Controller */
49#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
50#define AT91CAP9_ID_UHP 29 /* USB Host Port */
51#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
52#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
53
54/*
55 * User Peripheral physical base addresses.
56 */
57#define AT91CAP9_BASE_UDPHS 0xfff78000
58#define AT91CAP9_BASE_TCB0 0xfff7c000
59#define AT91CAP9_BASE_TC0 0xfff7c000
60#define AT91CAP9_BASE_TC1 0xfff7c040
61#define AT91CAP9_BASE_TC2 0xfff7c080
62#define AT91CAP9_BASE_MCI0 0xfff80000
63#define AT91CAP9_BASE_MCI1 0xfff84000
64#define AT91CAP9_BASE_TWI 0xfff88000
65#define AT91CAP9_BASE_US0 0xfff8c000
66#define AT91CAP9_BASE_US1 0xfff90000
67#define AT91CAP9_BASE_US2 0xfff94000
68#define AT91CAP9_BASE_SSC0 0xfff98000
69#define AT91CAP9_BASE_SSC1 0xfff9c000
70#define AT91CAP9_BASE_AC97C 0xfffa0000
71#define AT91CAP9_BASE_SPI0 0xfffa4000
72#define AT91CAP9_BASE_SPI1 0xfffa8000
73#define AT91CAP9_BASE_CAN 0xfffac000
74#define AT91CAP9_BASE_PWMC 0xfffb8000
75#define AT91CAP9_BASE_EMAC 0xfffbc000
76#define AT91CAP9_BASE_ADC 0xfffc0000
77#define AT91CAP9_BASE_ISI 0xfffc4000
78
79/*
80 * System Peripherals (offset from AT91_BASE_SYS)
81 */
82#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
83#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
84#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
85#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
86#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
87#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
88#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
89#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
90#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
91#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
92#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
93#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
94#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
98#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
99#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
100#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
101#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
102 (0xfffffd50 - AT91_BASE_SYS) : \
103 (0xfffffd60 - AT91_BASE_SYS))
104
105#define AT91_USART0 AT91CAP9_BASE_US0
106#define AT91_USART1 AT91CAP9_BASE_US1
107#define AT91_USART2 AT91CAP9_BASE_US2
108
109
110/*
111 * Internal Memory.
112 */
113#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
114#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
115
116#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
117#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
118
119#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
120#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
121#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
new file mode 100644
index 00000000000..976f4a6c335
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -0,0 +1,108 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
3 *
4 * (C) 2008 Andrew Victor
5 *
6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
7 * Based on AT91CAP9 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H
17
18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1
22#define AT91_DDRSDRC_MODE_PRECHARGE 2
23#define AT91_DDRSDRC_MODE_LMR 3
24#define AT91_DDRSDRC_MODE_REFRESH 4
25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6
27
28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30
31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
35#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
36#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
37#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
38#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
39#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
40#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
42#define AT91_DDRSDRC_NR_11 (0 << 2)
43#define AT91_DDRSDRC_NR_12 (1 << 2)
44#define AT91_DDRSDRC_NR_13 (2 << 2)
45#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
46#define AT91_DDRSDRC_CAS_2 (2 << 4)
47#define AT91_DDRSDRC_CAS_3 (3 << 4)
48#define AT91_DDRSDRC_CAS_25 (6 << 4)
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51
52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
56#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
57#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
58#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61
62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67
68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
72#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
73#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
74#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
75#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
76#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
77#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
78#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
79#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82
83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89
90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
94#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
95#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
96#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
97#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
107
108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
new file mode 100644
index 00000000000..4b9d4aff4b4
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
@@ -0,0 +1,137 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2006 Atmel Corporation.
7 *
8 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_MATRIX_H
18#define AT91CAP9_MATRIX_H
19
20#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
21#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
22#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
23#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
24#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
25#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
26#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
27#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
28#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
29#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
30#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
31#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
32#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
33#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
34#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
35#define AT91_MATRIX_ULBT_FOUR (2 << 0)
36#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
37#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
38
39#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
40#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
41#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
42#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
43#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
44#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
45#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
46#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
47#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
48#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
49#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
50#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
51#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
53#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
54#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
55#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
56#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
57#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
58
59#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
60#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
61#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
62#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
63#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
64#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
65#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
66#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
67#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
68#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
69#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
70#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
71#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
72#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
73#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
74#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
75#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
76#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
77#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
78#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
79#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
80#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
81#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
82#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
83#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
84#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
85#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
86#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
87#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
88#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
89#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
90#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
91
92#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
93#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
94#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
95#define AT91_MATRIX_RCB2 (1 << 2)
96#define AT91_MATRIX_RCB3 (1 << 3)
97#define AT91_MATRIX_RCB4 (1 << 4)
98#define AT91_MATRIX_RCB5 (1 << 5)
99#define AT91_MATRIX_RCB6 (1 << 6)
100#define AT91_MATRIX_RCB7 (1 << 7)
101#define AT91_MATRIX_RCB8 (1 << 8)
102#define AT91_MATRIX_RCB9 (1 << 9)
103#define AT91_MATRIX_RCB10 (1 << 10)
104#define AT91_MATRIX_RCB11 (1 << 11)
105
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108
109#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
110#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
111#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
112#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
113
114#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
115#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
116#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
117#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
118#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
119#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
120#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
121#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
122#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
123#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
124#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
125#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
126#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
127#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
128#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
129#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
130#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
131#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
132
133#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
134#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
135#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
136
137#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
new file mode 100644
index 00000000000..b8260cd8041
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
@@ -0,0 +1,138 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_emac.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Ethernet MAC registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_EMAC_H
17#define AT91RM9200_EMAC_H
18
19#define AT91_EMAC_CTL 0x00 /* Control Register */
20#define AT91_EMAC_LB (1 << 0) /* Loopback */
21#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
22#define AT91_EMAC_RE (1 << 2) /* Receive Enable */
23#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
24#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
25#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
26#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
27#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
28#define AT91_EMAC_BP (1 << 8) /* Back Pressure */
29
30#define AT91_EMAC_CFG 0x04 /* Configuration Register */
31#define AT91_EMAC_SPD (1 << 0) /* Speed */
32#define AT91_EMAC_FD (1 << 1) /* Full Duplex */
33#define AT91_EMAC_BR (1 << 2) /* Bit Rate */
34#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
35#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
36#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
37#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
38#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
39#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
40#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
41#define AT91_EMAC_CLK_DIV8 (0 << 10)
42#define AT91_EMAC_CLK_DIV16 (1 << 10)
43#define AT91_EMAC_CLK_DIV32 (2 << 10)
44#define AT91_EMAC_CLK_DIV64 (3 << 10)
45#define AT91_EMAC_RTY (1 << 12) /* Retry Test */
46#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
47
48#define AT91_EMAC_SR 0x08 /* Status Register */
49#define AT91_EMAC_SR_LINK (1 << 0) /* Link */
50#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
51#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
52
53#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
54
55#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
56#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
57#define AT91_EMAC_NCRC (1 << 15) /* No CRC */
58
59#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
60#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
61#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
62#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
63#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
64#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
65#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
66#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
67
68#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
69
70#define AT91_EMAC_RSR 0x20 /* Receive Status Register */
71#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
72#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
73#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
74
75#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
76#define AT91_EMAC_DONE (1 << 0) /* Management Done */
77#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
78#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
79#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
80#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
81#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
82#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
83#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
84#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
85#define AT91_EMAC_LINK (1 << 9) /* Link */
86#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
87#define AT91_EMAC_ABT (1 << 11) /* Abort */
88
89#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
90#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
91#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
92
93#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
94#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
95#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
96#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
97#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
98#define AT91_EMAC_RW_W (1 << 28)
99#define AT91_EMAC_RW_R (2 << 28)
100#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
101
102/*
103 * Statistics Registers.
104 */
105#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
106#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
107#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
108#define AT91_EMAC_OK 0x4c /* Frames Received OK */
109#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
110#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
111#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
112#define AT91_EMAC_LCOL 0x5c /* Late Collision */
113#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
114#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
115#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
116#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
117#define AT91_EMAC_ROV 0x70 /* Receive Overrun */
118#define AT91_EMAC_CDE 0x74 /* Code Error */
119#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
120#define AT91_EMAC_RJB 0x7c /* Receive Jabber */
121#define AT91_EMAC_USF 0x80 /* Undersize Frame */
122#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
123
124/*
125 * Address Registers.
126 */
127#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
128#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
129#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
130#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
131#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
132#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
133#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
134#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
135#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
136#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
137
138#endif
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
new file mode 100644
index 00000000000..187cb58345c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -0,0 +1,102 @@
1/*
2 * Header file for the Atmel AHB DMA Controller driver
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef AT_HDMAC_H
12#define AT_HDMAC_H
13
14#include <linux/dmaengine.h>
15
16/**
17 * struct at_dma_platform_data - Controller configuration parameters
18 * @nr_channels: Number of channels supported by hardware (max 8)
19 * @cap_mask: dma_capability flags supported by the platform
20 */
21struct at_dma_platform_data {
22 unsigned int nr_channels;
23 dma_cap_mask_t cap_mask;
24};
25
26/**
27 * enum at_dma_slave_width - DMA slave register access width.
28 * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
29 * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
30 * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
31 */
32enum at_dma_slave_width {
33 AT_DMA_SLAVE_WIDTH_8BIT = 0,
34 AT_DMA_SLAVE_WIDTH_16BIT,
35 AT_DMA_SLAVE_WIDTH_32BIT,
36};
37
38/**
39 * struct at_dma_slave - Controller-specific information about a slave
40 * @dma_dev: required DMA master device
41 * @tx_reg: physical address of data register used for
42 * memory-to-peripheral transfers
43 * @rx_reg: physical address of data register used for
44 * peripheral-to-memory transfers
45 * @reg_width: peripheral register width
46 * @cfg: Platform-specific initializer for the CFG register
47 * @ctrla: Platform-specific initializer for the CTRLA register
48 */
49struct at_dma_slave {
50 struct device *dma_dev;
51 dma_addr_t tx_reg;
52 dma_addr_t rx_reg;
53 enum at_dma_slave_width reg_width;
54 u32 cfg;
55 u32 ctrla;
56};
57
58
59/* Platform-configurable bits in CFG */
60#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
61#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
62#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
63#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
64#define ATC_SRC_H2SEL_SW (0x0 << 9)
65#define ATC_SRC_H2SEL_HW (0x1 << 9)
66#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
67#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
68#define ATC_DST_H2SEL_SW (0x0 << 13)
69#define ATC_DST_H2SEL_HW (0x1 << 13)
70#define ATC_SOD (0x1 << 16) /* Stop On Done */
71#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
72#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
73#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
74#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
75#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
76#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
77#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
78#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
79#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
80#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
81
82/* Platform-configurable bits in CTRLA */
83#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
84#define ATC_SCSIZE_1 (0x0 << 16)
85#define ATC_SCSIZE_4 (0x1 << 16)
86#define ATC_SCSIZE_8 (0x2 << 16)
87#define ATC_SCSIZE_16 (0x3 << 16)
88#define ATC_SCSIZE_32 (0x4 << 16)
89#define ATC_SCSIZE_64 (0x5 << 16)
90#define ATC_SCSIZE_128 (0x6 << 16)
91#define ATC_SCSIZE_256 (0x7 << 16)
92#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
93#define ATC_DCSIZE_1 (0x0 << 20)
94#define ATC_DCSIZE_4 (0x1 << 20)
95#define ATC_DCSIZE_8 (0x2 << 20)
96#define ATC_DCSIZE_16 (0x3 << 20)
97#define ATC_DCSIZE_32 (0x4 << 20)
98#define ATC_DCSIZE_64 (0x5 << 20)
99#define ATC_DCSIZE_128 (0x6 << 20)
100#define ATC_DCSIZE_256 (0x7 << 20)
101
102#endif /* AT_HDMAC_H */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
new file mode 100644
index 00000000000..ed544a0d5a1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -0,0 +1,210 @@
1/*
2 * arch/arm/mach-at91/include/mach/board.h
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * These are data structures found in platform_device.dev.platform_data,
23 * and describing board-specific data needed by drivers. For example,
24 * which pin is used for a given GPIO role.
25 *
26 * In 2.6, drivers should strongly avoid board-specific knowledge so
27 * that supporting new boards normally won't require driver patches.
28 * Most board-specific knowledge should be in arch/.../board-*.c files.
29 */
30
31#ifndef __ASM_ARCH_BOARD_H
32#define __ASM_ARCH_BOARD_H
33
34#include <linux/mtd/partitions.h>
35#include <linux/device.h>
36#include <linux/i2c.h>
37#include <linux/leds.h>
38#include <linux/spi/spi.h>
39#include <linux/usb/atmel_usba_udc.h>
40#include <linux/atmel-mci.h>
41#include <sound/atmel-ac97c.h>
42#include <linux/serial.h>
43
44 /* USB Device */
45struct at91_udc_data {
46 u8 vbus_pin; /* high == host powering us */
47 u8 vbus_active_low; /* vbus polarity */
48 u8 vbus_polled; /* Use polling, not interrupt */
49 u8 pullup_pin; /* active == D+ pulled up */
50 u8 pullup_active_low; /* true == pullup_pin is active low */
51};
52extern void __init at91_add_device_udc(struct at91_udc_data *data);
53
54 /* USB High Speed Device */
55extern void __init at91_add_device_usba(struct usba_platform_data *data);
56
57 /* Compact Flash */
58struct at91_cf_data {
59 u8 irq_pin; /* I/O IRQ */
60 u8 det_pin; /* Card detect */
61 u8 vcc_pin; /* power switching */
62 u8 rst_pin; /* card reset */
63 u8 chipselect; /* EBI Chip Select number */
64 u8 flags;
65#define AT91_CF_TRUE_IDE 0x01
66#define AT91_IDE_SWAP_A0_A2 0x02
67};
68extern void __init at91_add_device_cf(struct at91_cf_data *data);
69
70 /* MMC / SD */
71 /* at91_mci platform config */
72struct at91_mmc_data {
73 u8 det_pin; /* card detect IRQ */
74 unsigned slot_b:1; /* uses Slot B */
75 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
76 u8 wp_pin; /* (SD) writeprotect detect */
77 u8 vcc_pin; /* power switching (high == on) */
78};
79extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
80
81 /* atmel-mci platform config */
82extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
83
84 /* Ethernet (EMAC & MACB) */
85struct at91_eth_data {
86 u32 phy_mask;
87 u8 phy_irq_pin; /* PHY IRQ */
88 u8 is_rmii; /* using RMII interface? */
89};
90extern void __init at91_add_device_eth(struct at91_eth_data *data);
91
92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
93 || defined(CONFIG_ARCH_AT91SAM9G45)
94#define eth_platform_data at91_eth_data
95#endif
96
97 /* USB Host */
98struct at91_usbh_data {
99 u8 ports; /* number of ports on root hub */
100 u8 vbus_pin[2]; /* port power-control pin */
101};
102extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
103extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
104extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
105
106 /* NAND / SmartMedia */
107struct atmel_nand_data {
108 u8 enable_pin; /* chip enable */
109 u8 det_pin; /* card detect */
110 u8 rdy_pin; /* ready/busy */
111 u8 rdy_pin_active_low; /* rdy_pin value is inverted */
112 u8 ale; /* address line number connected to ALE */
113 u8 cle; /* address line number connected to CLE */
114 u8 bus_width_16; /* buswidth is 16 bit */
115 struct mtd_partition* (*partition_info)(int, int*);
116};
117extern void __init at91_add_device_nand(struct atmel_nand_data *data);
118
119 /* I2C*/
120#if defined(CONFIG_ARCH_AT91SAM9G45)
121extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
122#else
123extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
124#endif
125
126 /* SPI */
127extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
128
129 /* Serial */
130#define ATMEL_UART_CTS 0x01
131#define ATMEL_UART_RTS 0x02
132#define ATMEL_UART_DSR 0x04
133#define ATMEL_UART_DTR 0x08
134#define ATMEL_UART_DCD 0x10
135#define ATMEL_UART_RI 0x20
136
137extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
138extern void __init at91_set_serial_console(unsigned portnr);
139
140extern struct platform_device *atmel_default_console_device;
141
142struct atmel_uart_data {
143 int num; /* port num */
144 short use_dma_tx; /* use transmit DMA? */
145 short use_dma_rx; /* use receive DMA? */
146 void __iomem *regs; /* virt. base address, if any */
147 struct serial_rs485 rs485; /* rs485 settings */
148};
149extern void __init at91_add_device_serial(void);
150
151/*
152 * PWM
153 */
154#define AT91_PWM0 0
155#define AT91_PWM1 1
156#define AT91_PWM2 2
157#define AT91_PWM3 3
158
159extern void __init at91_add_device_pwm(u32 mask);
160
161/*
162 * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
163 * platform devices. Their SSC ID is part of their configuration data,
164 * along with information about which SSC signals they should use.
165 */
166#define ATMEL_SSC_TK 0x01
167#define ATMEL_SSC_TF 0x02
168#define ATMEL_SSC_TD 0x04
169#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
170
171#define ATMEL_SSC_RK 0x10
172#define ATMEL_SSC_RF 0x20
173#define ATMEL_SSC_RD 0x40
174#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
175
176extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
177
178 /* LCD Controller */
179struct atmel_lcdfb_info;
180extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
181
182 /* AC97 */
183extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
184
185 /* ISI */
186extern void __init at91_add_device_isi(void);
187
188 /* Touchscreen Controller */
189struct at91_tsadcc_data {
190 unsigned int adc_clock;
191 u8 pendet_debounce;
192 u8 ts_sample_hold_time;
193};
194extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data);
195
196/* CAN */
197struct at91_can_data {
198 void (*transceiver_switch)(int on);
199};
200extern void __init at91_add_device_can(struct at91_can_data *data);
201
202 /* LEDs */
203extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
204extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
205extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
206
207/* FIXME: this needs a better location, but gets stuff building again */
208extern int at91_suspend_entering_slow_clock(void);
209
210#endif
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
new file mode 100644
index 00000000000..7ab68f97222
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-at91/include/mach/entry-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Low-level IRQ helper macros for AT91RM9200 platforms
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <mach/hardware.h>
14#include <mach/at91_aic.h>
15
16 .macro disable_fiq
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
28 ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
29 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
30 streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now.
31 .endm
32
diff --git a/arch/arm/mach-at91/include/mach/gsia18s.h b/arch/arm/mach-at91/include/mach/gsia18s.h
new file mode 100644
index 00000000000..307c194926f
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/gsia18s.h
@@ -0,0 +1,33 @@
1/* Buttons */
2#define GPIO_TRIG_NET_IN AT91_PIN_PB21
3#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
4#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
5#define GPIO_KEY_POWER AT91_PIN_PA25
6
7/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
8#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
9#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
10#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
11#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
12#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
13#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
14#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
15#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
16#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
17
18/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
19#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
20#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
21#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
22#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
23#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
24/* bits 4, 5, 6 not used */
25#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
26
27/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
28#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
29#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
30#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
31/* bits 1, 2, 4, 5 not used */
32#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
33/* bit 7 not used */
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
new file mode 100644
index 00000000000..36bd55f3fc6
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/mach-at91/include/mach/irqs.h
3 *
4 * Copyright (C) 2004 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_IRQS_H
22#define __ASM_ARCH_IRQS_H
23
24#include <linux/io.h>
25#include <mach/at91_aic.h>
26
27#define NR_AIC_IRQS 32
28
29
30/*
31 * Acknowledge interrupt with AIC after interrupt has been handled.
32 * (by kernel/irq.c)
33 */
34#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
35
36
37/*
38 * IRQ interrupt symbols are the AT91xxx_ID_* symbols
39 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
40 * symbols in gpio.h for ones handled indirectly as GPIOs.
41 * We make provision for 5 banks of GPIO.
42 */
43#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
44
45/* FIQ is AIC source 0. */
46#define FIQ_START AT91_ID_FIQ
47
48#endif
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 00000000000..f62c0abca4b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_STAMP9G20_H
2#define __MACH_STAMP9G20_H
3
4void stamp9g20_init_early(void);
5void stamp9g20_board_init(void);
6
7#endif
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
new file mode 100644
index 00000000000..36af14bc13b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -0,0 +1,59 @@
1/*
2 * arch/arm/mach-at91/include/mach/system.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <mach/hardware.h>
25#include <mach/at91_st.h>
26#include <mach/at91_dbgu.h>
27#include <mach/at91_pmc.h>
28
29static inline void arch_idle(void)
30{
31 /*
32 * Disable the processor clock. The processor will be automatically
33 * re-enabled by an interrupt or by a reset.
34 */
35#ifdef AT91_PS
36 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
37#else
38 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
39#endif
40#ifndef CONFIG_CPU_ARM920T
41 /*
42 * Set the processor (CP15) into 'Wait for Interrupt' mode.
43 * Post-RM9200 processors need this in conjunction with the above
44 * to save power when idle.
45 */
46 cpu_do_idle();
47#endif
48}
49
50void (*at91_arch_reset)(void);
51
52static inline void arch_reset(char mode, const char *cmd)
53{
54 /* call the CPU-specific reset function */
55 if (at91_arch_reset)
56 (at91_arch_reset)();
57}
58
59#endif
diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h
new file mode 100644
index 00000000000..8eb459f3f5b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/vmalloc.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-at91/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_VMALLOC_H
22#define __ASM_ARCH_VMALLOC_H
23
24#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
25
26#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 20:43:58 -0400