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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /Documentation/devicetree/bindings/mtd
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
-rw-r--r--Documentation/devicetree/bindings/mtd/arm-versatile.txt4
-rw-r--r--Documentation/devicetree/bindings/mtd/atmel-dataflash.txt17
-rw-r--r--Documentation/devicetree/bindings/mtd/atmel-nand.txt79
-rw-r--r--Documentation/devicetree/bindings/mtd/denali-nand.txt23
-rw-r--r--Documentation/devicetree/bindings/mtd/flctl-nand.txt49
-rw-r--r--Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt4
-rw-r--r--Documentation/devicetree/bindings/mtd/fsmc-nand.txt31
-rw-r--r--Documentation/devicetree/bindings/mtd/gpio-control-nand.txt47
-rw-r--r--Documentation/devicetree/bindings/mtd/gpmi-nand.txt37
-rw-r--r--Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt50
-rw-r--r--Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt52
-rw-r--r--Documentation/devicetree/bindings/mtd/m25p80.txt29
-rw-r--r--Documentation/devicetree/bindings/mtd/mtd-physmap.txt33
-rw-r--r--Documentation/devicetree/bindings/mtd/mxc-nand.txt19
-rw-r--r--Documentation/devicetree/bindings/mtd/nand.txt7
-rw-r--r--Documentation/devicetree/bindings/mtd/orion-nand.txt50
-rw-r--r--Documentation/devicetree/bindings/mtd/partition.txt38
-rw-r--r--Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt31
-rw-r--r--Documentation/devicetree/bindings/mtd/spear_smi.txt31
19 files changed, 23 insertions, 608 deletions
diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
index beace4b89da..476845db94d 100644
--- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt
+++ b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
@@ -4,5 +4,5 @@ Required properties:
4- compatible : must be "arm,versatile-flash"; 4- compatible : must be "arm,versatile-flash";
5- bank-width : width in bytes of flash interface. 5- bank-width : width in bytes of flash interface.
6 6
7The device tree may optionally contain sub-nodes describing partitions of the 7Optional properties:
8address space. See partition.txt for more detail. 8- Subnode partition map from mtd flash binding
diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
deleted file mode 100644
index 1889a4db5b7..00000000000
--- a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
+++ /dev/null
@@ -1,17 +0,0 @@
1* Atmel Data Flash
2
3Required properties:
4- compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash".
5
6The device tree may optionally contain sub-nodes describing partitions of the
7address space. See partition.txt for more detail.
8
9Example:
10
11flash@1 {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
15 spi-max-frequency = <25000000>;
16 reg = <1>;
17};
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
deleted file mode 100644
index d555421ea49..00000000000
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ /dev/null
@@ -1,79 +0,0 @@
1Atmel NAND flash
2
3Required properties:
4- compatible : "atmel,at91rm9200-nand".
5- reg : should specify localbus address and size used for the chip,
6 and hardware ECC controller if available.
7 If the hardware ECC is PMECC, it should contain address and size for
8 PMECC, PMECC Error Location controller and ROM which has lookup tables.
9- atmel,nand-addr-offset : offset for the address latch.
10- atmel,nand-cmd-offset : offset for the command latch.
11- #address-cells, #size-cells : Must be present if the device has sub-nodes
12 representing partitions.
13
14- gpios : specifies the gpio pins to control the NAND device. detect is an
15 optional gpio and may be set to 0 if not present.
16
17Optional properties:
18- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
19 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
20 "soft_bch".
21- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
22 Only supported by at91sam9x5 or later sam9 product.
23- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
24 Controller. Supported values are: 2, 4, 8, 12, 24.
25- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
26 are: 512, 1024.
27- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
28 for different sector size. First one is for sector size 512, the next is for
29 sector size 1024.
30- nand-bus-width : 8 or 16 bus width if not present 8
31- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
32
33Examples:
34nand0: nand@40000000,0 {
35 compatible = "atmel,at91rm9200-nand";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 reg = <0x40000000 0x10000000
39 0xffffe800 0x200
40 >;
41 atmel,nand-addr-offset = <21>; /* ale */
42 atmel,nand-cmd-offset = <22>; /* cle */
43 nand-on-flash-bbt;
44 nand-ecc-mode = "soft";
45 gpios = <&pioC 13 0 /* rdy */
46 &pioC 14 0 /* nce */
47 0 /* cd */
48 >;
49 partition@0 {
50 ...
51 };
52};
53
54/* for PMECC supported chips */
55nand0: nand@40000000 {
56 compatible = "atmel,at91rm9200-nand";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 reg = < 0x40000000 0x10000000 /* bus addr & size */
60 0xffffe000 0x00000600 /* PMECC addr & size */
61 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
62 0x00100000 0x00100000 /* ROM addr & size */
63 >;
64 atmel,nand-addr-offset = <21>; /* ale */
65 atmel,nand-cmd-offset = <22>; /* cle */
66 nand-on-flash-bbt;
67 nand-ecc-mode = "hw";
68 atmel,has-pmecc; /* enable PMECC */
69 atmel,pmecc-cap = <2>;
70 atmel,pmecc-sector-size = <512>;
71 atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
72 gpios = <&pioD 5 0 /* rdy */
73 &pioD 4 0 /* nce */
74 0 /* cd */
75 >;
76 partition@0 {
77 ...
78 };
79};
diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
deleted file mode 100644
index b04d03a1d49..00000000000
--- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
+++ /dev/null
@@ -1,23 +0,0 @@
1* Denali NAND controller
2
3Required properties:
4 - compatible : should be "denali,denali-nand-dt"
5 - reg : should contain registers location and length for data and reg.
6 - reg-names: Should contain the reg names "nand_data" and "denali_reg"
7 - interrupts : The interrupt number.
8 - dm-mask : DMA bit mask
9
10The device tree may optionally contain sub-nodes describing partitions of the
11address space. See partition.txt for more detail.
12
13Examples:
14
15nand: nand@ff900000 {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 compatible = "denali,denali-nand-dt";
19 reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
20 reg-names = "nand_data", "denali_reg";
21 interrupts = <0 144 4>;
22 dma-mask = <0xffffffff>;
23};
diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt
deleted file mode 100644
index 427f46dc60a..00000000000
--- a/Documentation/devicetree/bindings/mtd/flctl-nand.txt
+++ /dev/null
@@ -1,49 +0,0 @@
1FLCTL NAND controller
2
3Required properties:
4- compatible : "renesas,shmobile-flctl-sh7372"
5- reg : Address range of the FLCTL
6- interrupts : flste IRQ number
7- nand-bus-width : bus width to NAND chip
8
9Optional properties:
10- dmas: DMA specifier(s)
11- dma-names: name for each DMA specifier. Valid names are
12 "data_tx", "data_rx", "ecc_tx", "ecc_rx"
13
14The DMA fields are not used yet in the driver but are listed here for
15completing the bindings.
16
17The device tree may optionally contain sub-nodes describing partitions of the
18address space. See partition.txt for more detail.
19
20Example:
21
22 flctl@e6a30000 {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "renesas,shmobile-flctl-sh7372";
26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
28
29 nand-bus-width = <16>;
30
31 dmas = <&dmac 1 /* data_tx */
32 &dmac 2;> /* data_rx */
33 dma-names = "data_tx", "data_rx";
34
35 system@0 {
36 label = "system";
37 reg = <0x0 0x8000000>;
38 };
39
40 userdata@8000000 {
41 label = "userdata";
42 reg = <0x8000000 0x10000000>;
43 };
44
45 cache@18000000 {
46 label = "cache";
47 reg = <0x18000000 0x8000000>;
48 };
49 };
diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
index fce4894f5a9..00f1f546b32 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
@@ -19,10 +19,6 @@ Optional properties:
19 read registers (tR). Required if property "gpios" is not used 19 read registers (tR). Required if property "gpios" is not used
20 (R/B# pins not connected). 20 (R/B# pins not connected).
21 21
22Each flash chip described may optionally contain additional sub-nodes
23describing partitions of the address space. See partition.txt for more
24detail.
25
26Examples: 22Examples:
27 23
28upm@1,0 { 24upm@1,0 {
diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
deleted file mode 100644
index e3ea32e7de3..00000000000
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ /dev/null
@@ -1,31 +0,0 @@
1* FSMC NAND
2
3Required properties:
4- compatible : "st,spear600-fsmc-nand"
5- reg : Address range of the mtd chip
6- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
7
8Optional properties:
9- bank-width : Width (in bytes) of the device. If not present, the width
10 defaults to 1 byte
11- nand-skip-bbtscan: Indicates the the BBT scanning should be skipped
12
13Example:
14
15 fsmc: flash@d1800000 {
16 compatible = "st,spear600-fsmc-nand";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 reg = <0xd1800000 0x1000 /* FSMC Register */
20 0xd2000000 0x0010 /* NAND Base DATA */
21 0xd2020000 0x0010 /* NAND Base ADDR */
22 0xd2010000 0x0010>; /* NAND Base CMD */
23 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
24
25 bank-width = <1>;
26 nand-skip-bbtscan;
27
28 partition@0 {
29 ...
30 };
31 };
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
deleted file mode 100644
index 36ef07d3c90..00000000000
--- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
+++ /dev/null
@@ -1,47 +0,0 @@
1GPIO assisted NAND flash
2
3The GPIO assisted NAND flash uses a memory mapped interface to
4read/write the NAND commands and data and GPIO pins for the control
5signals.
6
7Required properties:
8- compatible : "gpio-control-nand"
9- reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to the NAND flash and all accesses
11 are made in native endianness.
12- #address-cells, #size-cells : Must be present if the device has sub-nodes
13 representing partitions.
14- gpios : specifies the gpio pins to control the NAND device. nwp is an
15 optional gpio and may be set to 0 if not present.
16
17Optional properties:
18- bank-width : Width (in bytes) of the device. If not present, the width
19 defaults to 1 byte.
20- chip-delay : chip dependent delay for transferring data from array to
21 read registers (tR). If not present then a default of 20us is used.
22- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
23 location used to guard against bus reordering with regards to accesses to
24 the GPIO's and the NAND flash data bus. If present, then after changing
25 GPIO state and before and after command byte writes, this register will be
26 read to ensure that the GPIO accesses have completed.
27
28The device tree may optionally contain sub-nodes describing partitions of the
29address space. See partition.txt for more detail.
30
31Examples:
32
33gpio-nand@1,0 {
34 compatible = "gpio-control-nand";
35 reg = <1 0x0000 0x2>;
36 #address-cells = <1>;
37 #size-cells = <1>;
38 gpios = <&banka 1 0 /* rdy */
39 &banka 2 0 /* nce */
40 &banka 3 0 /* ale */
41 &banka 4 0 /* cle */
42 0 /* nwp */>;
43
44 partition@0 {
45 ...
46 };
47};
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
deleted file mode 100644
index 3fb3f901536..00000000000
--- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
+++ /dev/null
@@ -1,37 +0,0 @@
1* Freescale General-Purpose Media Interface (GPMI)
2
3The GPMI nand controller provides an interface to control the
4NAND flash chips. We support only one NAND chip now.
5
6Required properties:
7 - compatible : should be "fsl,<chip>-gpmi-nand"
8 - reg : should contain registers location and length for gpmi and bch.
9 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
10 - interrupts : The first is the DMA interrupt number for GPMI.
11 The second is the BCH interrupt number.
12 - interrupt-names : The interrupt names "gpmi-dma", "bch";
13 - fsl,gpmi-dma-channel : Should contain the dma channel it uses.
14
15Optional properties:
16 - nand-on-flash-bbt: boolean to enable on flash bbt option if not
17 present false
18
19The device tree may optionally contain sub-nodes describing partitions of the
20address space. See partition.txt for more detail.
21
22Examples:
23
24gpmi-nand@8000c000 {
25 compatible = "fsl,imx28-gpmi-nand";
26 #address-cells = <1>;
27 #size-cells = <1>;
28 reg = <0x8000c000 2000>, <0x8000a000 2000>;
29 reg-names = "gpmi-nand", "bch";
30 interrupts = <88>, <41>;
31 interrupt-names = "gpmi-dma", "bch";
32 fsl,gpmi-dma-channel = <4>;
33
34 partition@0 {
35 ...
36 };
37};
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
deleted file mode 100644
index d0a37252eb2..00000000000
--- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
+++ /dev/null
@@ -1,50 +0,0 @@
1NXP LPC32xx SoC NAND MLC controller
2
3Required properties:
4- compatible: "nxp,lpc3220-mlc"
5- reg: Address and size of the controller
6- interrupts: The NAND interrupt specification
7- gpios: GPIO specification for NAND write protect
8
9The following required properties are very controller specific. See the LPC32xx
10User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
11Hz, to make them independent of actual clock speed and to provide for good
12accuracy:)
13- nxp,tcea_delay: TCEA_DELAY
14- nxp,busy_delay: BUSY_DELAY
15- nxp,nand_ta: NAND_TA
16- nxp,rd_high: RD_HIGH
17- nxp,rd_low: RD_LOW
18- nxp,wr_high: WR_HIGH
19- nxp,wr_low: WR_LOW
20
21Optional subnodes:
22- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
23
24Example:
25
26 mlc: flash@200A8000 {
27 compatible = "nxp,lpc3220-mlc";
28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>;
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 nxp,tcea-delay = <333333333>;
34 nxp,busy-delay = <10000000>;
35 nxp,nand-ta = <18181818>;
36 nxp,rd-high = <31250000>;
37 nxp,rd-low = <45454545>;
38 nxp,wr-high = <40000000>;
39 nxp,wr-low = <83333333>;
40 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
41
42 mtd0@00000000 {
43 label = "boot";
44 reg = <0x00000000 0x00064000>;
45 read-only;
46 };
47
48 ...
49
50 };
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
deleted file mode 100644
index d94edc0fc55..00000000000
--- a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
+++ /dev/null
@@ -1,52 +0,0 @@
1NXP LPC32xx SoC NAND SLC controller
2
3Required properties:
4- compatible: "nxp,lpc3220-slc"
5- reg: Address and size of the controller
6- nand-on-flash-bbt: Use bad block table on flash
7- gpios: GPIO specification for NAND write protect
8
9The following required properties are very controller specific. See the LPC32xx
10User Manual:
11- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
13(The following values are specified in Hz, to make them independent of actual
14clock speed:)
15- nxp,wwidth: Write pulse width (W_WIDTH)
16- nxp,whold: Write hold time (W_HOLD)
17- nxp,wsetup: Write setup time (W_SETUP)
18- nxp,rwidth: Read pulse width (R_WIDTH)
19- nxp,rhold: Read hold time (R_HOLD)
20- nxp,rsetup: Read setup time (R_SETUP)
21
22Optional subnodes:
23- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
24
25Example:
26
27 slc: flash@20020000 {
28 compatible = "nxp,lpc3220-slc";
29 reg = <0x20020000 0x1000>;
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 nxp,wdr-clks = <14>;
34 nxp,wwidth = <40000000>;
35 nxp,whold = <100000000>;
36 nxp,wsetup = <100000000>;
37 nxp,rdr-clks = <14>;
38 nxp,rwidth = <40000000>;
39 nxp,rhold = <66666666>;
40 nxp,rsetup = <100000000>;
41 nand-on-flash-bbt;
42 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
43
44 mtd0@00000000 {
45 label = "phy3250-boot";
46 reg = <0x00000000 0x00064000>;
47 read-only;
48 };
49
50 ...
51
52 };
diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt
deleted file mode 100644
index 6d3d5760947..00000000000
--- a/Documentation/devicetree/bindings/mtd/m25p80.txt
+++ /dev/null
@@ -1,29 +0,0 @@
1* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
2
3Required properties:
4- #address-cells, #size-cells : Must be present if the device has sub-nodes
5 representing partitions.
6- compatible : Should be the manufacturer and the name of the chip. Bear in mind
7 the DT binding is not Linux-only, but in case of Linux, see the
8 "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of
9 supported chips.
10- reg : Chip-Select number
11- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
12
13Optional properties:
14- m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
15 of the usual "read" opcode. This opcode is not supported by
16 all chips and support for it can not be detected at runtime.
17 Refer to your chips' datasheet to check if this is supported
18 by your chip.
19
20Example:
21
22 flash: m25p80@0 {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "spansion,m25p80";
26 reg = <0>;
27 spi-max-frequency = <40000000>;
28 m25p,fast-read;
29 };
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
index dab7847fc80..80152cb567d 100644
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
@@ -16,16 +16,6 @@ file systems on embedded devices.
16 - #address-cells, #size-cells : Must be present if the device has 16 - #address-cells, #size-cells : Must be present if the device has
17 sub-nodes representing partitions (see below). In this case 17 sub-nodes representing partitions (see below). In this case
18 both #address-cells and #size-cells must be equal to 1. 18 both #address-cells and #size-cells must be equal to 1.
19 - no-unaligned-direct-access: boolean to disable the default direct
20 mapping of the flash.
21 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
22 problems with JFFS2 usage, as the local bus (LPB) doesn't support
23 unaligned accesses as implemented in the JFFS2 code via memcpy().
24 By defining "no-unaligned-direct-access", the flash will not be
25 exposed directly to the MTD users (e.g. JFFS2) any more.
26 - linux,mtd-name: allow to specify the mtd name for retro capability with
27 physmap-flash drivers as boot loader pass the mtd partition via the old
28 device name physmap-flash.
29 19
30For JEDEC compatible devices, the following additional properties 20For JEDEC compatible devices, the following additional properties
31are defined: 21are defined:
@@ -33,8 +23,27 @@ are defined:
33 - vendor-id : Contains the flash chip's vendor id (1 byte). 23 - vendor-id : Contains the flash chip's vendor id (1 byte).
34 - device-id : Contains the flash chip's device id (1 byte). 24 - device-id : Contains the flash chip's device id (1 byte).
35 25
36The device tree may optionally contain sub-nodes describing partitions of the 26In addition to the information on the mtd bank itself, the
37address space. See partition.txt for more detail. 27device tree may optionally contain additional information
28describing partitions of the address space. This can be
29used on platforms which have strong conventions about which
30portions of a flash are used for what purposes, but which don't
31use an on-flash partition table such as RedBoot.
32
33Each partition is represented as a sub-node of the mtd device.
34Each node's name represents the name of the corresponding
35partition of the mtd device.
36
37Flash partitions
38 - reg : The partition's offset and size within the mtd bank.
39 - label : (optional) The label / name for this partition.
40 If omitted, the label is taken from the node name (excluding
41 the unit address).
42 - read-only : (optional) This parameter, if present, is a hint to
43 Linux that this partition should only be mounted
44 read-only. This is usually used for flash partitions
45 containing early-boot firmware images or data which should not
46 be clobbered.
38 47
39Example: 48Example:
40 49
diff --git a/Documentation/devicetree/bindings/mtd/mxc-nand.txt b/Documentation/devicetree/bindings/mtd/mxc-nand.txt
deleted file mode 100644
index b5833d11c7b..00000000000
--- a/Documentation/devicetree/bindings/mtd/mxc-nand.txt
+++ /dev/null
@@ -1,19 +0,0 @@
1* Freescale's mxc_nand
2
3Required properties:
4- compatible: "fsl,imxXX-nand"
5- reg: address range of the nfc block
6- interrupts: irq to be used
7- nand-bus-width: see nand.txt
8- nand-ecc-mode: see nand.txt
9- nand-on-flash-bbt: see nand.txt
10
11Example:
12
13 nand@d8000000 {
14 compatible = "fsl,imx27-nand";
15 reg = <0xd8000000 0x1000>;
16 interrupts = <29>;
17 nand-bus-width = <8>;
18 nand-ecc-mode = "hw";
19 };
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
deleted file mode 100644
index 03855c8c492..00000000000
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ /dev/null
@@ -1,7 +0,0 @@
1* MTD generic binding
2
3- nand-ecc-mode : String, operation mode of the NAND ecc mode.
4 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
5 "soft_bch".
6- nand-bus-width : 8 or 16 bus width if not present 8
7- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
deleted file mode 100644
index 2d6ab660e60..00000000000
--- a/Documentation/devicetree/bindings/mtd/orion-nand.txt
+++ /dev/null
@@ -1,50 +0,0 @@
1NAND support for Marvell Orion SoC platforms
2
3Required properties:
4- compatible : "marvell,orion-nand".
5- reg : Base physical address of the NAND and length of memory mapped
6 region
7
8Optional properties:
9- cle : Address line number connected to CLE. Default is 0
10- ale : Address line number connected to ALE. Default is 1
11- bank-width : Width in bytes of the device. Default is 1
12- chip-delay : Chip dependent delay for transferring data from array to read
13 registers in usecs
14
15The device tree may optionally contain sub-nodes describing partitions of the
16address space. See partition.txt for more detail.
17
18Example:
19
20nand@f4000000 {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 cle = <0>;
24 ale = <1>;
25 bank-width = <1>;
26 chip-delay = <25>;
27 compatible = "marvell,orion-nand";
28 reg = <0xf4000000 0x400>;
29
30 partition@0 {
31 label = "u-boot";
32 reg = <0x0000000 0x100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "uImage";
38 reg = <0x0100000 0x200000>;
39 };
40
41 partition@300000 {
42 label = "dtb";
43 reg = <0x0300000 0x100000>;
44 };
45
46 partition@400000 {
47 label = "root";
48 reg = <0x0400000 0x7d00000>;
49 };
50};
diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt
deleted file mode 100644
index 6e1f61f1e78..00000000000
--- a/Documentation/devicetree/bindings/mtd/partition.txt
+++ /dev/null
@@ -1,38 +0,0 @@
1Representing flash partitions in devicetree
2
3Partitions can be represented by sub-nodes of an mtd device. This can be used
4on platforms which have strong conventions about which portions of a flash are
5used for what purposes, but which don't use an on-flash partition table such
6as RedBoot.
7
8#address-cells & #size-cells must both be present in the mtd device and be
9equal to 1.
10
11Required properties:
12- reg : The partition's offset and size within the mtd bank.
13
14Optional properties:
15- label : The label / name for this partition. If omitted, the label is taken
16 from the node name (excluding the unit address).
17- read-only : This parameter, if present, is a hint to Linux that this
18 partition should only be mounted read-only. This is usually used for flash
19 partitions containing early-boot firmware images or data which should not be
20 clobbered.
21
22Examples:
23
24
25flash@0 {
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 partition@0 {
30 label = "u-boot";
31 reg = <0x0000000 0x100000>;
32 read-only;
33 };
34
35 uimage@100000 {
36 reg = <0x0100000 0x200000>;
37 };
38};
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
deleted file mode 100644
index f1421e2bbab..00000000000
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ /dev/null
@@ -1,31 +0,0 @@
1PXA3xx NAND DT bindings
2
3Required properties:
4
5 - compatible: Should be "marvell,pxa3xx-nand"
6 - reg: The register base for the controller
7 - interrupts: The interrupt to map
8 - #address-cells: Set to <1> if the node includes partitions
9
10Optional properties:
11
12 - marvell,nand-enable-arbiter: Set to enable the bus arbiter
13 - marvell,nand-keep-config: Set to keep the NAND controller config as set
14 by the bootloader
15 - num-cs: Number of chipselect lines to usw
16
17Example:
18
19 nand0: nand@43100000 {
20 compatible = "marvell,pxa3xx-nand";
21 reg = <0x43100000 90>;
22 interrupts = <45>;
23 #address-cells = <1>;
24
25 marvell,nand-enable-arbiter;
26 marvell,nand-keep-config;
27 num-cs = <1>;
28
29 /* partitions (optional) */
30 };
31
diff --git a/Documentation/devicetree/bindings/mtd/spear_smi.txt b/Documentation/devicetree/bindings/mtd/spear_smi.txt
deleted file mode 100644
index 7248aadd89e..00000000000
--- a/Documentation/devicetree/bindings/mtd/spear_smi.txt
+++ /dev/null
@@ -1,31 +0,0 @@
1* SPEAr SMI
2
3Required properties:
4- compatible : "st,spear600-smi"
5- reg : Address range of the mtd chip
6- #address-cells, #size-cells : Must be present if the device has sub-nodes
7 representing partitions.
8- interrupt-parent: Should be the phandle for the interrupt controller
9 that services interrupts for this device
10- interrupts: Should contain the STMMAC interrupts
11- clock-rate : Functional clock rate of SMI in Hz
12
13Optional properties:
14- st,smi-fast-mode : Flash supports read in fast mode
15
16Example:
17
18 smi: flash@fc000000 {
19 compatible = "st,spear600-smi";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 reg = <0xfc000000 0x1000>;
23 interrupt-parent = <&vic1>;
24 interrupts = <12>;
25 clock-rate = <50000000>; /* 50MHz */
26
27 flash@f8000000 {
28 st,smi-fast-mode;
29 ...
30 };
31 };
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-11 10:37:10 -0500