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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-06-29 03:18:33 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-06-29 03:18:53 -0400
commite5310ed70dc2c06d9102424bb97ee3e68783394f (patch)
treecd5114edfeb1f1dd4ae30f886f176236c5e5eb84
parent3a5383a2373fd5bc5ebdd781c8ac89ab5d0cb8a4 (diff)
parentbd5a7b11a0bfd172b4cd6ef3e01e6beb1753c3f1 (diff)
Merge Misc DSS clean ups from Archit
This series does the following things: - Remove passive matrix LCD support: There are no panel drivers with passive matrix LCD drivers in DSS2. There are no passive matrix panels even available to test with DSS. Since no one is using passive matrix panels, stop trying to support it. It cleans up the DSS driver. - Add some new fields to omap_video_timings: There were some standard panel timing fields missing from omap_video_timings. Namely Hsync/Vsync/DE levels and interlace. Add these to omap_video_timings to align it more with xorg modeline. Add some other OMAP DSS specific fields to omap_video_timings. - Remove some hacks done because omap_video_timings didn't have the above fields. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat
-rw-r--r--drivers/video/omap2/displays/panel-acx565akm.c10
-rw-r--r--drivers/video/omap2/displays/panel-generic-dpi.c179
-rw-r--r--drivers/video/omap2/displays/panel-lgphilips-lb035q02.c8
-rw-r--r--drivers/video/omap2/displays/panel-n8x0.c1
-rw-r--r--drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c9
-rw-r--r--drivers/video/omap2/displays/panel-picodlp.c9
-rw-r--r--drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c9
-rw-r--r--drivers/video/omap2/displays/panel-taal.c1
-rw-r--r--drivers/video/omap2/displays/panel-tfp410.c7
-rw-r--r--drivers/video/omap2/displays/panel-tpo-td043mtea1.c8
-rw-r--r--drivers/video/omap2/dss/apply.c6
-rw-r--r--drivers/video/omap2/dss/dispc.c124
-rw-r--r--drivers/video/omap2/dss/display.c6
-rw-r--r--drivers/video/omap2/dss/dpi.c39
-rw-r--r--drivers/video/omap2/dss/dsi.c61
-rw-r--r--drivers/video/omap2/dss/dss.c7
-rw-r--r--drivers/video/omap2/dss/dss.h17
-rw-r--r--drivers/video/omap2/dss/hdmi.c241
-rw-r--r--drivers/video/omap2/dss/hdmi_panel.c9
-rw-r--r--drivers/video/omap2/dss/rfbi.c3
-rw-r--r--drivers/video/omap2/dss/sdi.c12
-rw-r--r--drivers/video/omap2/dss/ti_hdmi.h19
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c8
-rw-r--r--drivers/video/omap2/dss/venc.c4
-rw-r--r--drivers/video/omap2/omapfb/omapfb-main.c51
-rw-r--r--include/video/omapdss.h39
26 files changed, 568 insertions, 319 deletions
diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
index ad741c3d1ae..eaeed4340e0 100644
--- a/drivers/video/omap2/displays/panel-acx565akm.c
+++ b/drivers/video/omap2/displays/panel-acx565akm.c
@@ -487,6 +487,13 @@ static struct omap_video_timings acx_panel_timings = {
487 .vfp = 3, 487 .vfp = 3,
488 .vsw = 3, 488 .vsw = 3,
489 .vbp = 4, 489 .vbp = 4,
490
491 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
492 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
493
494 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
495 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
496 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
490}; 497};
491 498
492static int acx_panel_probe(struct omap_dss_device *dssdev) 499static int acx_panel_probe(struct omap_dss_device *dssdev)
@@ -498,8 +505,7 @@ static int acx_panel_probe(struct omap_dss_device *dssdev)
498 struct backlight_properties props; 505 struct backlight_properties props;
499 506
500 dev_dbg(&dssdev->dev, "%s\n", __func__); 507 dev_dbg(&dssdev->dev, "%s\n", __func__);
501 dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | 508
502 OMAP_DSS_LCD_IHS;
503 /* FIXME AC bias ? */ 509 /* FIXME AC bias ? */
504 dssdev->panel.timings = acx_panel_timings; 510 dssdev->panel.timings = acx_panel_timings;
505 511
diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c
index e42f9dc2212..bc5af2500eb 100644
--- a/drivers/video/omap2/displays/panel-generic-dpi.c
+++ b/drivers/video/omap2/displays/panel-generic-dpi.c
@@ -40,12 +40,6 @@
40struct panel_config { 40struct panel_config {
41 struct omap_video_timings timings; 41 struct omap_video_timings timings;
42 42
43 int acbi; /* ac-bias pin transitions per interrupt */
44 /* Unit: line clocks */
45 int acb; /* ac-bias pin frequency */
46
47 enum omap_panel_config config;
48
49 int power_on_delay; 43 int power_on_delay;
50 int power_off_delay; 44 int power_off_delay;
51 45
@@ -73,11 +67,13 @@ static struct panel_config generic_dpi_panels[] = {
73 .vsw = 11, 67 .vsw = 11,
74 .vfp = 3, 68 .vfp = 3,
75 .vbp = 2, 69 .vbp = 2,
70
71 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
72 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
73 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
74 .de_level = OMAPDSS_SIG_ACTIVE_LOW,
75 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
76 }, 76 },
77 .acbi = 0x0,
78 .acb = 0x0,
79 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
80 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
81 .power_on_delay = 50, 77 .power_on_delay = 50,
82 .power_off_delay = 100, 78 .power_off_delay = 100,
83 .name = "sharp_lq", 79 .name = "sharp_lq",
@@ -98,11 +94,13 @@ static struct panel_config generic_dpi_panels[] = {
98 .vsw = 1, 94 .vsw = 1,
99 .vfp = 1, 95 .vfp = 1,
100 .vbp = 1, 96 .vbp = 1,
97
98 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
99 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
100 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
101 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
102 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
101 }, 103 },
102 .acbi = 0x0,
103 .acb = 0x28,
104 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
105 OMAP_DSS_LCD_IHS,
106 .power_on_delay = 50, 104 .power_on_delay = 50,
107 .power_off_delay = 100, 105 .power_off_delay = 100,
108 .name = "sharp_ls", 106 .name = "sharp_ls",
@@ -123,12 +121,13 @@ static struct panel_config generic_dpi_panels[] = {
123 .vfp = 4, 121 .vfp = 4,
124 .vsw = 2, 122 .vsw = 2,
125 .vbp = 2, 123 .vbp = 2,
124
125 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
126 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
127 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
128 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
129 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
126 }, 130 },
127 .acbi = 0x0,
128 .acb = 0x0,
129 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
130 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
131 OMAP_DSS_LCD_ONOFF,
132 .power_on_delay = 0, 131 .power_on_delay = 0,
133 .power_off_delay = 0, 132 .power_off_delay = 0,
134 .name = "toppoly_tdo35s", 133 .name = "toppoly_tdo35s",
@@ -149,11 +148,13 @@ static struct panel_config generic_dpi_panels[] = {
149 .vfp = 4, 148 .vfp = 4,
150 .vsw = 10, 149 .vsw = 10,
151 .vbp = 12 - 10, 150 .vbp = 12 - 10,
151
152 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
153 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
154 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
155 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
156 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
152 }, 157 },
153 .acbi = 0x0,
154 .acb = 0x0,
155 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
156 OMAP_DSS_LCD_IHS,
157 .power_on_delay = 0, 158 .power_on_delay = 0,
158 .power_off_delay = 0, 159 .power_off_delay = 0,
159 .name = "samsung_lte430wq_f0c", 160 .name = "samsung_lte430wq_f0c",
@@ -174,11 +175,13 @@ static struct panel_config generic_dpi_panels[] = {
174 .vsw = 2, 175 .vsw = 2,
175 .vfp = 4, 176 .vfp = 4,
176 .vbp = 11, 177 .vbp = 11,
178
179 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
180 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
181 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
182 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
183 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
177 }, 184 },
178 .acbi = 0x0,
179 .acb = 0x0,
180 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
181 OMAP_DSS_LCD_IHS,
182 .power_on_delay = 0, 185 .power_on_delay = 0,
183 .power_off_delay = 0, 186 .power_off_delay = 0,
184 .name = "seiko_70wvw1tz3", 187 .name = "seiko_70wvw1tz3",
@@ -199,11 +202,13 @@ static struct panel_config generic_dpi_panels[] = {
199 .vsw = 10, 202 .vsw = 10,
200 .vfp = 2, 203 .vfp = 2,
201 .vbp = 2, 204 .vbp = 2,
205
206 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
207 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
208 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
209 .de_level = OMAPDSS_SIG_ACTIVE_LOW,
210 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
202 }, 211 },
203 .acbi = 0x0,
204 .acb = 0x0,
205 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
206 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
207 .power_on_delay = 0, 212 .power_on_delay = 0,
208 .power_off_delay = 0, 213 .power_off_delay = 0,
209 .name = "powertip_ph480272t", 214 .name = "powertip_ph480272t",
@@ -224,11 +229,13 @@ static struct panel_config generic_dpi_panels[] = {
224 .vsw = 3, 229 .vsw = 3,
225 .vfp = 12, 230 .vfp = 12,
226 .vbp = 25, 231 .vbp = 25,
232
233 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
234 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
235 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
236 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
237 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
227 }, 238 },
228 .acbi = 0x0,
229 .acb = 0x28,
230 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
231 OMAP_DSS_LCD_IHS,
232 .power_on_delay = 0, 239 .power_on_delay = 0,
233 .power_off_delay = 0, 240 .power_off_delay = 0,
234 .name = "innolux_at070tn83", 241 .name = "innolux_at070tn83",
@@ -249,9 +256,13 @@ static struct panel_config generic_dpi_panels[] = {
249 .vsw = 1, 256 .vsw = 1,
250 .vfp = 2, 257 .vfp = 2,
251 .vbp = 7, 258 .vbp = 7,
259
260 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
261 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
262 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
263 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
264 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
252 }, 265 },
253 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
254 OMAP_DSS_LCD_IHS,
255 .name = "nec_nl2432dr22-11b", 266 .name = "nec_nl2432dr22-11b",
256 }, 267 },
257 268
@@ -270,9 +281,13 @@ static struct panel_config generic_dpi_panels[] = {
270 .vsw = 1, 281 .vsw = 1,
271 .vfp = 1, 282 .vfp = 1,
272 .vbp = 1, 283 .vbp = 1,
273 },
274 .config = OMAP_DSS_LCD_TFT,
275 284
285 .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
286 .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
287 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
288 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
289 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
290 },
276 .name = "h4", 291 .name = "h4",
277 }, 292 },
278 293
@@ -291,10 +306,13 @@ static struct panel_config generic_dpi_panels[] = {
291 .vsw = 10, 306 .vsw = 10,
292 .vfp = 2, 307 .vfp = 2,
293 .vbp = 2, 308 .vbp = 2,
294 },
295 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
296 OMAP_DSS_LCD_IHS,
297 309
310 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
311 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
312 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
313 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
314 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
315 },
298 .name = "apollon", 316 .name = "apollon",
299 }, 317 },
300 /* FocalTech ETM070003DH6 */ 318 /* FocalTech ETM070003DH6 */
@@ -312,9 +330,13 @@ static struct panel_config generic_dpi_panels[] = {
312 .vsw = 3, 330 .vsw = 3,
313 .vfp = 13, 331 .vfp = 13,
314 .vbp = 29, 332 .vbp = 29,
333
334 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
335 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
336 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
337 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
338 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
315 }, 339 },
316 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
317 OMAP_DSS_LCD_IHS,
318 .name = "focaltech_etm070003dh6", 340 .name = "focaltech_etm070003dh6",
319 }, 341 },
320 342
@@ -333,11 +355,13 @@ static struct panel_config generic_dpi_panels[] = {
333 .vsw = 23, 355 .vsw = 23,
334 .vfp = 1, 356 .vfp = 1,
335 .vbp = 1, 357 .vbp = 1,
358
359 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
360 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
361 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
362 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
363 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
336 }, 364 },
337 .acbi = 0x0,
338 .acb = 0x0,
339 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
340 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
341 .power_on_delay = 0, 365 .power_on_delay = 0,
342 .power_off_delay = 0, 366 .power_off_delay = 0,
343 .name = "microtips_umsh_8173md", 367 .name = "microtips_umsh_8173md",
@@ -358,9 +382,13 @@ static struct panel_config generic_dpi_panels[] = {
358 .vsw = 10, 382 .vsw = 10,
359 .vfp = 4, 383 .vfp = 4,
360 .vbp = 2, 384 .vbp = 2,
361 },
362 .config = OMAP_DSS_LCD_TFT,
363 385
386 .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
387 .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
388 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
389 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
390 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
391 },
364 .name = "ortustech_com43h4m10xtc", 392 .name = "ortustech_com43h4m10xtc",
365 }, 393 },
366 394
@@ -379,11 +407,13 @@ static struct panel_config generic_dpi_panels[] = {
379 .vsw = 10, 407 .vsw = 10,
380 .vfp = 12, 408 .vfp = 12,
381 .vbp = 23, 409 .vbp = 23,
382 },
383 .acb = 0x0,
384 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
385 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
386 410
411 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
412 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
413 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
414 .de_level = OMAPDSS_SIG_ACTIVE_LOW,
415 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
416 },
387 .name = "innolux_at080tn52", 417 .name = "innolux_at080tn52",
388 }, 418 },
389 419
@@ -401,8 +431,13 @@ static struct panel_config generic_dpi_panels[] = {
401 .vsw = 1, 431 .vsw = 1,
402 .vfp = 26, 432 .vfp = 26,
403 .vbp = 1, 433 .vbp = 1,
434
435 .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
436 .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
437 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
438 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
439 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
404 }, 440 },
405 .config = OMAP_DSS_LCD_TFT,
406 .name = "mitsubishi_aa084sb01", 441 .name = "mitsubishi_aa084sb01",
407 }, 442 },
408 /* EDT ET0500G0DH6 */ 443 /* EDT ET0500G0DH6 */
@@ -419,8 +454,13 @@ static struct panel_config generic_dpi_panels[] = {
419 .vsw = 2, 454 .vsw = 2,
420 .vfp = 35, 455 .vfp = 35,
421 .vbp = 10, 456 .vbp = 10,
457
458 .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
459 .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
460 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
461 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
462 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
422 }, 463 },
423 .config = OMAP_DSS_LCD_TFT,
424 .name = "edt_et0500g0dh6", 464 .name = "edt_et0500g0dh6",
425 }, 465 },
426 466
@@ -439,9 +479,13 @@ static struct panel_config generic_dpi_panels[] = {
439 .vsw = 2, 479 .vsw = 2,
440 .vfp = 10, 480 .vfp = 10,
441 .vbp = 33, 481 .vbp = 33,
482
483 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
484 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
485 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
486 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
487 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
442 }, 488 },
443 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
444 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
445 .name = "primeview_pd050vl1", 489 .name = "primeview_pd050vl1",
446 }, 490 },
447 491
@@ -460,9 +504,13 @@ static struct panel_config generic_dpi_panels[] = {
460 .vsw = 2, 504 .vsw = 2,
461 .vfp = 10, 505 .vfp = 10,
462 .vbp = 33, 506 .vbp = 33,
507
508 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
509 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
510 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
511 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
512 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
463 }, 513 },
464 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
465 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
466 .name = "primeview_pm070wl4", 514 .name = "primeview_pm070wl4",
467 }, 515 },
468 516
@@ -481,9 +529,13 @@ static struct panel_config generic_dpi_panels[] = {
481 .vsw = 4, 529 .vsw = 4,
482 .vfp = 1, 530 .vfp = 1,
483 .vbp = 23, 531 .vbp = 23,
532
533 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
534 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
535 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
536 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
537 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
484 }, 538 },
485 .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
486 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC,
487 .name = "primeview_pd104slf", 539 .name = "primeview_pd104slf",
488 }, 540 },
489}; 541};
@@ -573,10 +625,7 @@ static int generic_dpi_panel_probe(struct omap_dss_device *dssdev)
573 if (!panel_config) 625 if (!panel_config)
574 return -EINVAL; 626 return -EINVAL;
575 627
576 dssdev->panel.config = panel_config->config;
577 dssdev->panel.timings = panel_config->timings; 628 dssdev->panel.timings = panel_config->timings;
578 dssdev->panel.acb = panel_config->acb;
579 dssdev->panel.acbi = panel_config->acbi;
580 629
581 drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL); 630 drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL);
582 if (!drv_data) 631 if (!drv_data)
diff --git a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
index 0841cc2b3f7..80280779884 100644
--- a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
+++ b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
@@ -40,6 +40,12 @@ static struct omap_video_timings lb035q02_timings = {
40 .vsw = 2, 40 .vsw = 2,
41 .vfp = 4, 41 .vfp = 4,
42 .vbp = 18, 42 .vbp = 18,
43
44 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
45 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
46 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
47 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
48 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
43}; 49};
44 50
45static int lb035q02_panel_power_on(struct omap_dss_device *dssdev) 51static int lb035q02_panel_power_on(struct omap_dss_device *dssdev)
@@ -82,8 +88,6 @@ static int lb035q02_panel_probe(struct omap_dss_device *dssdev)
82 struct lb035q02_data *ld; 88 struct lb035q02_data *ld;
83 int r; 89 int r;
84 90
85 dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
86 OMAP_DSS_LCD_IHS;
87 dssdev->panel.timings = lb035q02_timings; 91 dssdev->panel.timings = lb035q02_timings;
88 92
89 ld = kzalloc(sizeof(*ld), GFP_KERNEL); 93 ld = kzalloc(sizeof(*ld), GFP_KERNEL);
diff --git a/drivers/video/omap2/displays/panel-n8x0.c b/drivers/video/omap2/displays/panel-n8x0.c
index 4a34cdc1371..e6c115373c0 100644
--- a/drivers/video/omap2/displays/panel-n8x0.c
+++ b/drivers/video/omap2/displays/panel-n8x0.c
@@ -473,7 +473,6 @@ static int n8x0_panel_probe(struct omap_dss_device *dssdev)
473 473
474 mutex_init(&ddata->lock); 474 mutex_init(&ddata->lock);
475 475
476 dssdev->panel.config = OMAP_DSS_LCD_TFT;
477 dssdev->panel.timings.x_res = 800; 476 dssdev->panel.timings.x_res = 800;
478 dssdev->panel.timings.y_res = 480; 477 dssdev->panel.timings.y_res = 480;
479 dssdev->ctrl.pixel_size = 16; 478 dssdev->ctrl.pixel_size = 16;
diff --git a/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c b/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
index 8b38b39213f..b122b0f31c4 100644
--- a/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
+++ b/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
@@ -76,6 +76,12 @@ static struct omap_video_timings nec_8048_panel_timings = {
76 .vfp = 3, 76 .vfp = 3,
77 .vsw = 1, 77 .vsw = 1,
78 .vbp = 4, 78 .vbp = 4,
79
80 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
81 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
82 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
83 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
84 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
79}; 85};
80 86
81static int nec_8048_bl_update_status(struct backlight_device *bl) 87static int nec_8048_bl_update_status(struct backlight_device *bl)
@@ -116,9 +122,6 @@ static int nec_8048_panel_probe(struct omap_dss_device *dssdev)
116 struct backlight_properties props; 122 struct backlight_properties props;
117 int r; 123 int r;
118 124
119 dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
120 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_RF |
121 OMAP_DSS_LCD_ONOFF;
122 dssdev->panel.timings = nec_8048_panel_timings; 125 dssdev->panel.timings = nec_8048_panel_timings;
123 126
124 necd = kzalloc(sizeof(*necd), GFP_KERNEL); 127 necd = kzalloc(sizeof(*necd), GFP_KERNEL);
diff --git a/drivers/video/omap2/displays/panel-picodlp.c b/drivers/video/omap2/displays/panel-picodlp.c
index 98ebdaddab5..2d35bd38886 100644
--- a/drivers/video/omap2/displays/panel-picodlp.c
+++ b/drivers/video/omap2/displays/panel-picodlp.c
@@ -69,6 +69,12 @@ static struct omap_video_timings pico_ls_timings = {
69 .vsw = 2, 69 .vsw = 2,
70 .vfp = 3, 70 .vfp = 3,
71 .vbp = 14, 71 .vbp = 14,
72
73 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
74 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
75 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
76 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
77 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
72}; 78};
73 79
74static inline struct picodlp_panel_data 80static inline struct picodlp_panel_data
@@ -414,9 +420,6 @@ static int picodlp_panel_probe(struct omap_dss_device *dssdev)
414 struct i2c_client *picodlp_i2c_client; 420 struct i2c_client *picodlp_i2c_client;
415 int r = 0, picodlp_adapter_id; 421 int r = 0, picodlp_adapter_id;
416 422
417 dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_ONOFF |
418 OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS;
419 dssdev->panel.acb = 0x0;
420 dssdev->panel.timings = pico_ls_timings; 423 dssdev->panel.timings = pico_ls_timings;
421 424
422 picod = kzalloc(sizeof(struct picodlp_data), GFP_KERNEL); 425 picod = kzalloc(sizeof(struct picodlp_data), GFP_KERNEL);
diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
index ba38b3ad17d..bd86ba9ccf7 100644
--- a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
@@ -44,6 +44,12 @@ static struct omap_video_timings sharp_ls_timings = {
44 .vsw = 1, 44 .vsw = 1,
45 .vfp = 1, 45 .vfp = 1,
46 .vbp = 1, 46 .vbp = 1,
47
48 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
49 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
50 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
51 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
52 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
47}; 53};
48 54
49static int sharp_ls_bl_update_status(struct backlight_device *bl) 55static int sharp_ls_bl_update_status(struct backlight_device *bl)
@@ -86,9 +92,6 @@ static int sharp_ls_panel_probe(struct omap_dss_device *dssdev)
86 struct sharp_data *sd; 92 struct sharp_data *sd;
87 int r; 93 int r;
88 94
89 dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
90 OMAP_DSS_LCD_IHS;
91 dssdev->panel.acb = 0x28;
92 dssdev->panel.timings = sharp_ls_timings; 95 dssdev->panel.timings = sharp_ls_timings;
93 96
94 sd = kzalloc(sizeof(*sd), GFP_KERNEL); 97 sd = kzalloc(sizeof(*sd), GFP_KERNEL);
diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
index 901576eb5a8..3f5acc7771d 100644
--- a/drivers/video/omap2/displays/panel-taal.c
+++ b/drivers/video/omap2/displays/panel-taal.c
@@ -882,7 +882,6 @@ static int taal_probe(struct omap_dss_device *dssdev)
882 goto err; 882 goto err;
883 } 883 }
884 884
885 dssdev->panel.config = OMAP_DSS_LCD_TFT;
886 dssdev->panel.timings = panel_config->timings; 885 dssdev->panel.timings = panel_config->timings;
887 dssdev->panel.dsi_pix_fmt = OMAP_DSS_DSI_FMT_RGB888; 886 dssdev->panel.dsi_pix_fmt = OMAP_DSS_DSI_FMT_RGB888;
888 887
diff --git a/drivers/video/omap2/displays/panel-tfp410.c b/drivers/video/omap2/displays/panel-tfp410.c
index bff306e041c..40cc0cfa5d1 100644
--- a/drivers/video/omap2/displays/panel-tfp410.c
+++ b/drivers/video/omap2/displays/panel-tfp410.c
@@ -39,6 +39,12 @@ static const struct omap_video_timings tfp410_default_timings = {
39 .vfp = 3, 39 .vfp = 3,
40 .vsw = 4, 40 .vsw = 4,
41 .vbp = 7, 41 .vbp = 7,
42
43 .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
44 .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
45 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
46 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
47 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
42}; 48};
43 49
44struct panel_drv_data { 50struct panel_drv_data {
@@ -95,7 +101,6 @@ static int tfp410_probe(struct omap_dss_device *dssdev)
95 return -ENOMEM; 101 return -ENOMEM;
96 102
97 dssdev->panel.timings = tfp410_default_timings; 103 dssdev->panel.timings = tfp410_default_timings;
98 dssdev->panel.config = OMAP_DSS_LCD_TFT;
99 104
100 ddata->dssdev = dssdev; 105 ddata->dssdev = dssdev;
101 mutex_init(&ddata->lock); 106 mutex_init(&ddata->lock);
diff --git a/drivers/video/omap2/displays/panel-tpo-td043mtea1.c b/drivers/video/omap2/displays/panel-tpo-td043mtea1.c
index 4b6448b3c31..fa7baa650ae 100644
--- a/drivers/video/omap2/displays/panel-tpo-td043mtea1.c
+++ b/drivers/video/omap2/displays/panel-tpo-td043mtea1.c
@@ -267,6 +267,12 @@ static const struct omap_video_timings tpo_td043_timings = {
267 .vsw = 1, 267 .vsw = 1,
268 .vfp = 39, 268 .vfp = 39,
269 .vbp = 34, 269 .vbp = 34,
270
271 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
272 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
273 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
274 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
275 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
270}; 276};
271 277
272static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043) 278static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043)
@@ -423,8 +429,6 @@ static int tpo_td043_probe(struct omap_dss_device *dssdev)
423 return -ENODEV; 429 return -ENODEV;
424 } 430 }
425 431
426 dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IHS |
427 OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IPC;
428 dssdev->panel.timings = tpo_td043_timings; 432 dssdev->panel.timings = tpo_td043_timings;
429 dssdev->ctrl.pixel_size = 24; 433 dssdev->ctrl.pixel_size = 24;
430 434
diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c
index ab22cc224f3..3ce7a3ec622 100644
--- a/drivers/video/omap2/dss/apply.c
+++ b/drivers/video/omap2/dss/apply.c
@@ -537,7 +537,7 @@ static void dss_ovl_write_regs(struct omap_overlay *ovl)
537{ 537{
538 struct ovl_priv_data *op = get_ovl_priv(ovl); 538 struct ovl_priv_data *op = get_ovl_priv(ovl);
539 struct omap_overlay_info *oi; 539 struct omap_overlay_info *oi;
540 bool ilace, replication; 540 bool replication;
541 struct mgr_priv_data *mp; 541 struct mgr_priv_data *mp;
542 int r; 542 int r;
543 543
@@ -552,9 +552,7 @@ static void dss_ovl_write_regs(struct omap_overlay *ovl)
552 552
553 replication = dss_use_replication(ovl->manager->device, oi->color_mode); 553 replication = dss_use_replication(ovl->manager->device, oi->color_mode);
554 554
555 ilace = ovl->manager->device->type == OMAP_DISPLAY_TYPE_VENC; 555 r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings);
556
557 r = dispc_ovl_setup(ovl->id, oi, ilace, replication, &mp->timings);
558 if (r) { 556 if (r) {
559 /* 557 /*
560 * We can't do much here, as this function can be called from 558 * We can't do much here, as this function can be called from
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e48d1c10a3c..d1a7a0c9028 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2157,8 +2157,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
2157} 2157}
2158 2158
2159int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi, 2159int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2160 bool ilace, bool replication, 2160 bool replication, const struct omap_video_timings *mgr_timings)
2161 const struct omap_video_timings *mgr_timings)
2162{ 2161{
2163 struct omap_overlay *ovl = omap_dss_get_overlay(plane); 2162 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2164 bool five_taps = true; 2163 bool five_taps = true;
@@ -2174,6 +2173,7 @@ int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2174 u16 out_width, out_height; 2173 u16 out_width, out_height;
2175 enum omap_channel channel; 2174 enum omap_channel channel;
2176 int x_predecim = 1, y_predecim = 1; 2175 int x_predecim = 1, y_predecim = 1;
2176 bool ilace = mgr_timings->interlace;
2177 2177
2178 channel = dispc_ovl_get_channel_out(plane); 2178 channel = dispc_ovl_get_channel_out(plane);
2179 2179
@@ -2490,26 +2490,9 @@ void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2490} 2490}
2491 2491
2492 2492
2493void dispc_mgr_set_lcd_display_type(enum omap_channel channel, 2493void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2494 enum omap_lcd_display_type type)
2495{ 2494{
2496 int mode; 2495 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2497
2498 switch (type) {
2499 case OMAP_DSS_LCD_DISPLAY_STN:
2500 mode = 0;
2501 break;
2502
2503 case OMAP_DSS_LCD_DISPLAY_TFT:
2504 mode = 1;
2505 break;
2506
2507 default:
2508 BUG();
2509 return;
2510 }
2511
2512 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, mode);
2513} 2496}
2514 2497
2515void dispc_set_loadmode(enum omap_dss_load_mode mode) 2498void dispc_set_loadmode(enum omap_dss_load_mode mode)
@@ -2669,9 +2652,16 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
2669} 2652}
2670 2653
2671static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, 2654static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2672 int hfp, int hbp, int vsw, int vfp, int vbp) 2655 int hfp, int hbp, int vsw, int vfp, int vbp,
2656 enum omap_dss_signal_level vsync_level,
2657 enum omap_dss_signal_level hsync_level,
2658 enum omap_dss_signal_edge data_pclk_edge,
2659 enum omap_dss_signal_level de_level,
2660 enum omap_dss_signal_edge sync_pclk_edge)
2661
2673{ 2662{
2674 u32 timing_h, timing_v; 2663 u32 timing_h, timing_v, l;
2664 bool onoff, rf, ipc;
2675 2665
2676 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { 2666 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2677 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) | 2667 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
@@ -2689,6 +2679,44 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2689 2679
2690 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 2680 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2691 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 2681 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2682
2683 switch (data_pclk_edge) {
2684 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2685 ipc = false;
2686 break;
2687 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2688 ipc = true;
2689 break;
2690 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2691 default:
2692 BUG();
2693 }
2694
2695 switch (sync_pclk_edge) {
2696 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2697 onoff = false;
2698 rf = false;
2699 break;
2700 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2701 onoff = true;
2702 rf = false;
2703 break;
2704 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2705 onoff = true;
2706 rf = true;
2707 break;
2708 default:
2709 BUG();
2710 };
2711
2712 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2713 l |= FLD_VAL(onoff, 17, 17);
2714 l |= FLD_VAL(rf, 16, 16);
2715 l |= FLD_VAL(de_level, 15, 15);
2716 l |= FLD_VAL(ipc, 14, 14);
2717 l |= FLD_VAL(hsync_level, 13, 13);
2718 l |= FLD_VAL(vsync_level, 12, 12);
2719 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2692} 2720}
2693 2721
2694/* change name to mode? */ 2722/* change name to mode? */
@@ -2708,7 +2736,8 @@ void dispc_mgr_set_timings(enum omap_channel channel,
2708 2736
2709 if (dispc_mgr_is_lcd(channel)) { 2737 if (dispc_mgr_is_lcd(channel)) {
2710 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, 2738 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2711 t.vfp, t.vbp); 2739 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2740 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2712 2741
2713 xtot = t.x_res + t.hfp + t.hsw + t.hbp; 2742 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2714 ytot = t.y_res + t.vfp + t.vsw + t.vbp; 2743 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
@@ -2719,14 +2748,13 @@ void dispc_mgr_set_timings(enum omap_channel channel,
2719 DSSDBG("pck %u\n", timings->pixel_clock); 2748 DSSDBG("pck %u\n", timings->pixel_clock);
2720 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 2749 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2721 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); 2750 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2751 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2752 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2753 t.de_level, t.sync_pclk_edge);
2722 2754
2723 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 2755 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2724 } else { 2756 } else {
2725 enum dss_hdmi_venc_clk_source_select source; 2757 if (t.interlace == true)
2726
2727 source = dss_get_hdmi_venc_clk_source();
2728
2729 if (source == DSS_VENC_TV_CLK)
2730 t.y_res /= 2; 2758 t.y_res /= 2;
2731 } 2759 }
2732 2760
@@ -3133,41 +3161,8 @@ static void dispc_dump_regs(struct seq_file *s)
3133#undef DUMPREG 3161#undef DUMPREG
3134} 3162}
3135 3163
3136static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3137 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3138 u8 acb)
3139{
3140 u32 l = 0;
3141
3142 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3143 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3144
3145 l |= FLD_VAL(onoff, 17, 17);
3146 l |= FLD_VAL(rf, 16, 16);
3147 l |= FLD_VAL(ieo, 15, 15);
3148 l |= FLD_VAL(ipc, 14, 14);
3149 l |= FLD_VAL(ihs, 13, 13);
3150 l |= FLD_VAL(ivs, 12, 12);
3151 l |= FLD_VAL(acbi, 11, 8);
3152 l |= FLD_VAL(acb, 7, 0);
3153
3154 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3155}
3156
3157void dispc_mgr_set_pol_freq(enum omap_channel channel,
3158 enum omap_panel_config config, u8 acbi, u8 acb)
3159{
3160 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
3161 (config & OMAP_DSS_LCD_RF) != 0,
3162 (config & OMAP_DSS_LCD_IEO) != 0,
3163 (config & OMAP_DSS_LCD_IPC) != 0,
3164 (config & OMAP_DSS_LCD_IHS) != 0,
3165 (config & OMAP_DSS_LCD_IVS) != 0,
3166 acbi, acb);
3167}
3168
3169/* with fck as input clock rate, find dispc dividers that produce req_pck */ 3164/* with fck as input clock rate, find dispc dividers that produce req_pck */
3170void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, 3165void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3171 struct dispc_clock_info *cinfo) 3166 struct dispc_clock_info *cinfo)
3172{ 3167{
3173 u16 pcd_min, pcd_max; 3168 u16 pcd_min, pcd_max;
@@ -3178,9 +3173,6 @@ void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3178 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); 3173 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3179 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); 3174 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3180 3175
3181 if (!is_tft)
3182 pcd_min = 3;
3183
3184 best_pck = 0; 3176 best_pck = 0;
3185 best_ld = 0; 3177 best_ld = 0;
3186 best_pd = 0; 3178 best_pd = 0;
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index 24901063037..1a0c15f83d0 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -116,7 +116,7 @@ static ssize_t display_timings_store(struct device *dev,
116 struct device_attribute *attr, const char *buf, size_t size) 116 struct device_attribute *attr, const char *buf, size_t size)
117{ 117{
118 struct omap_dss_device *dssdev = to_dss_device(dev); 118 struct omap_dss_device *dssdev = to_dss_device(dev);
119 struct omap_video_timings t; 119 struct omap_video_timings t = dssdev->panel.timings;
120 int r, found; 120 int r, found;
121 121
122 if (!dssdev->driver->set_timings || !dssdev->driver->check_timings) 122 if (!dssdev->driver->set_timings || !dssdev->driver->check_timings)
@@ -327,10 +327,6 @@ bool dss_use_replication(struct omap_dss_device *dssdev,
327 if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16) 327 if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16)
328 return false; 328 return false;
329 329
330 if (dssdev->type == OMAP_DISPLAY_TYPE_DPI &&
331 (dssdev->panel.config & OMAP_DSS_LCD_TFT) == 0)
332 return false;
333
334 switch (dssdev->type) { 330 switch (dssdev->type) {
335 case OMAP_DISPLAY_TYPE_DPI: 331 case OMAP_DISPLAY_TYPE_DPI:
336 bpp = dssdev->phy.dpi.data_lines; 332 bpp = dssdev->phy.dpi.data_lines;
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 8c2056c9537..a81b6d6deb5 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -64,7 +64,7 @@ static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
64 return false; 64 return false;
65} 65}
66 66
67static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft, 67static int dpi_set_dsi_clk(struct omap_dss_device *dssdev,
68 unsigned long pck_req, unsigned long *fck, int *lck_div, 68 unsigned long pck_req, unsigned long *fck, int *lck_div,
69 int *pck_div) 69 int *pck_div)
70{ 70{
@@ -72,8 +72,8 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
72 struct dispc_clock_info dispc_cinfo; 72 struct dispc_clock_info dispc_cinfo;
73 int r; 73 int r;
74 74
75 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req, 75 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, pck_req, &dsi_cinfo,
76 &dsi_cinfo, &dispc_cinfo); 76 &dispc_cinfo);
77 if (r) 77 if (r)
78 return r; 78 return r;
79 79
@@ -96,7 +96,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
96 return 0; 96 return 0;
97} 97}
98 98
99static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft, 99static int dpi_set_dispc_clk(struct omap_dss_device *dssdev,
100 unsigned long pck_req, unsigned long *fck, int *lck_div, 100 unsigned long pck_req, unsigned long *fck, int *lck_div,
101 int *pck_div) 101 int *pck_div)
102{ 102{
@@ -104,7 +104,7 @@ static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
104 struct dispc_clock_info dispc_cinfo; 104 struct dispc_clock_info dispc_cinfo;
105 int r; 105 int r;
106 106
107 r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo); 107 r = dss_calc_clock_div(pck_req, &dss_cinfo, &dispc_cinfo);
108 if (r) 108 if (r)
109 return r; 109 return r;
110 110
@@ -129,20 +129,14 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
129 int lck_div = 0, pck_div = 0; 129 int lck_div = 0, pck_div = 0;
130 unsigned long fck = 0; 130 unsigned long fck = 0;
131 unsigned long pck; 131 unsigned long pck;
132 bool is_tft;
133 int r = 0; 132 int r = 0;
134 133
135 dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
136 dssdev->panel.acbi, dssdev->panel.acb);
137
138 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
139
140 if (dpi_use_dsi_pll(dssdev)) 134 if (dpi_use_dsi_pll(dssdev))
141 r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, 135 r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
142 &fck, &lck_div, &pck_div); 136 &lck_div, &pck_div);
143 else 137 else
144 r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, 138 r = dpi_set_dispc_clk(dssdev, t->pixel_clock * 1000, &fck,
145 &fck, &lck_div, &pck_div); 139 &lck_div, &pck_div);
146 if (r) 140 if (r)
147 return r; 141 return r;
148 142
@@ -163,15 +157,11 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
163 157
164static void dpi_basic_init(struct omap_dss_device *dssdev) 158static void dpi_basic_init(struct omap_dss_device *dssdev)
165{ 159{
166 bool is_tft;
167
168 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
169
170 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS); 160 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
171 dispc_mgr_enable_stallmode(dssdev->manager->id, false); 161 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
172 162
173 dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ? 163 dispc_mgr_set_lcd_type_tft(dssdev->manager->id);
174 OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN); 164
175 dispc_mgr_set_tft_data_lines(dssdev->manager->id, 165 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
176 dssdev->phy.dpi.data_lines); 166 dssdev->phy.dpi.data_lines);
177} 167}
@@ -292,7 +282,6 @@ EXPORT_SYMBOL(dpi_set_timings);
292int dpi_check_timings(struct omap_dss_device *dssdev, 282int dpi_check_timings(struct omap_dss_device *dssdev,
293 struct omap_video_timings *timings) 283 struct omap_video_timings *timings)
294{ 284{
295 bool is_tft;
296 int r; 285 int r;
297 int lck_div, pck_div; 286 int lck_div, pck_div;
298 unsigned long fck; 287 unsigned long fck;
@@ -305,11 +294,9 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
305 if (timings->pixel_clock == 0) 294 if (timings->pixel_clock == 0)
306 return -EINVAL; 295 return -EINVAL;
307 296
308 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
309
310 if (dpi_use_dsi_pll(dssdev)) { 297 if (dpi_use_dsi_pll(dssdev)) {
311 struct dsi_clock_info dsi_cinfo; 298 struct dsi_clock_info dsi_cinfo;
312 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, 299 r = dsi_pll_calc_clock_div_pck(dpi.dsidev,
313 timings->pixel_clock * 1000, 300 timings->pixel_clock * 1000,
314 &dsi_cinfo, &dispc_cinfo); 301 &dsi_cinfo, &dispc_cinfo);
315 302
@@ -319,7 +306,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
319 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; 306 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
320 } else { 307 } else {
321 struct dss_clock_info dss_cinfo; 308 struct dss_clock_info dss_cinfo;
322 r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000, 309 r = dss_calc_clock_div(timings->pixel_clock * 1000,
323 &dss_cinfo, &dispc_cinfo); 310 &dss_cinfo, &dispc_cinfo);
324 311
325 if (r) 312 if (r)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index df65b93c065..e0d43b275e3 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1316,7 +1316,7 @@ static int dsi_calc_clock_rates(struct platform_device *dsidev,
1316 return 0; 1316 return 0;
1317} 1317}
1318 1318
1319int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, 1319int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1320 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, 1320 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1321 struct dispc_clock_info *dispc_cinfo) 1321 struct dispc_clock_info *dispc_cinfo)
1322{ 1322{
@@ -1335,8 +1335,8 @@ int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1335 dsi->cache_cinfo.clkin == dss_sys_clk) { 1335 dsi->cache_cinfo.clkin == dss_sys_clk) {
1336 DSSDBG("DSI clock info found from cache\n"); 1336 DSSDBG("DSI clock info found from cache\n");
1337 *dsi_cinfo = dsi->cache_cinfo; 1337 *dsi_cinfo = dsi->cache_cinfo;
1338 dispc_find_clk_divs(is_tft, req_pck, 1338 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1339 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); 1339 dispc_cinfo);
1340 return 0; 1340 return 0;
1341 } 1341 }
1342 1342
@@ -1402,7 +1402,7 @@ retry:
1402 1402
1403 match = 1; 1403 match = 1;
1404 1404
1405 dispc_find_clk_divs(is_tft, req_pck, 1405 dispc_find_clk_divs(req_pck,
1406 cur.dsi_pll_hsdiv_dispc_clk, 1406 cur.dsi_pll_hsdiv_dispc_clk,
1407 &cur_dispc); 1407 &cur_dispc);
1408 1408
@@ -3631,17 +3631,14 @@ static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3631static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev) 3631static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3632{ 3632{
3633 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3633 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3634 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3635 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3636 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3637 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end; 3634 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3638 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; 3635 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3639 u32 r; 3636 u32 r;
3640 3637
3641 r = dsi_read_reg(dsidev, DSI_CTRL); 3638 r = dsi_read_reg(dsidev, DSI_CTRL);
3642 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */ 3639 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3643 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */ 3640 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3644 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */ 3641 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3645 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3642 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3646 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ 3643 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3647 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3644 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
@@ -4343,22 +4340,22 @@ EXPORT_SYMBOL(omap_dsi_update);
4343static int dsi_display_init_dispc(struct omap_dss_device *dssdev) 4340static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4344{ 4341{
4345 int r; 4342 int r;
4343 struct omap_video_timings timings;
4346 4344
4347 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { 4345 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4348 u16 dw, dh; 4346 u16 dw, dh;
4349 u32 irq; 4347 u32 irq;
4350 struct omap_video_timings timings = {
4351 .hsw = 1,
4352 .hfp = 1,
4353 .hbp = 1,
4354 .vsw = 1,
4355 .vfp = 0,
4356 .vbp = 0,
4357 };
4358 4348
4359 dssdev->driver->get_resolution(dssdev, &dw, &dh); 4349 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4350
4360 timings.x_res = dw; 4351 timings.x_res = dw;
4361 timings.y_res = dh; 4352 timings.y_res = dh;
4353 timings.hsw = 1;
4354 timings.hfp = 1;
4355 timings.hbp = 1;
4356 timings.vsw = 1;
4357 timings.vfp = 0;
4358 timings.vbp = 0;
4362 4359
4363 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id); 4360 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
4364 4361
@@ -4371,19 +4368,31 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4371 4368
4372 dispc_mgr_enable_stallmode(dssdev->manager->id, true); 4369 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4373 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1); 4370 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4374
4375 dss_mgr_set_timings(dssdev->manager, &timings);
4376 } else { 4371 } else {
4372 timings = dssdev->panel.timings;
4373
4377 dispc_mgr_enable_stallmode(dssdev->manager->id, false); 4374 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4378 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0); 4375 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4379
4380 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
4381 } 4376 }
4382 4377
4383 dispc_mgr_set_lcd_display_type(dssdev->manager->id, 4378 /*
4384 OMAP_DSS_LCD_DISPLAY_TFT); 4379 * override interlace, logic level and edge related parameters in
4385 dispc_mgr_set_tft_data_lines(dssdev->manager->id, 4380 * omap_video_timings with default values
4386 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)); 4381 */
4382 timings.interlace = false;
4383 timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4384 timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4385 timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4386 timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4387 timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4388
4389 dss_mgr_set_timings(dssdev->manager, &timings);
4390
4391 dispc_mgr_set_lcd_type_tft(dssdev->manager->id);
4392
4393 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4394 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4395
4387 return 0; 4396 return 0;
4388} 4397}
4389 4398
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index fc0c3ce802e..04b4586113e 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -506,8 +506,7 @@ unsigned long dss_get_dpll4_rate(void)
506 return 0; 506 return 0;
507} 507}
508 508
509int dss_calc_clock_div(bool is_tft, unsigned long req_pck, 509int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
510 struct dss_clock_info *dss_cinfo,
511 struct dispc_clock_info *dispc_cinfo) 510 struct dispc_clock_info *dispc_cinfo)
512{ 511{
513 unsigned long prate; 512 unsigned long prate;
@@ -555,7 +554,7 @@ retry:
555 fck = clk_get_rate(dss.dss_clk); 554 fck = clk_get_rate(dss.dss_clk);
556 fck_div = 1; 555 fck_div = 1;
557 556
558 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); 557 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
559 match = 1; 558 match = 1;
560 559
561 best_dss.fck = fck; 560 best_dss.fck = fck;
@@ -585,7 +584,7 @@ retry:
585 584
586 match = 1; 585 match = 1;
587 586
588 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); 587 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
589 588
590 if (abs(cur_dispc.pck - req_pck) < 589 if (abs(cur_dispc.pck - req_pck) <
591 abs(best_dispc.pck - req_pck)) { 590 abs(best_dispc.pck - req_pck)) {
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index df131fc6895..6c5ecf02759 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -274,8 +274,7 @@ unsigned long dss_get_dpll4_rate(void);
274int dss_calc_clock_rates(struct dss_clock_info *cinfo); 274int dss_calc_clock_rates(struct dss_clock_info *cinfo);
275int dss_set_clock_div(struct dss_clock_info *cinfo); 275int dss_set_clock_div(struct dss_clock_info *cinfo);
276int dss_get_clock_div(struct dss_clock_info *cinfo); 276int dss_get_clock_div(struct dss_clock_info *cinfo);
277int dss_calc_clock_div(bool is_tft, unsigned long req_pck, 277int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
278 struct dss_clock_info *dss_cinfo,
279 struct dispc_clock_info *dispc_cinfo); 278 struct dispc_clock_info *dispc_cinfo);
280 279
281/* SDI */ 280/* SDI */
@@ -302,7 +301,7 @@ u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
302unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev); 301unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
303int dsi_pll_set_clock_div(struct platform_device *dsidev, 302int dsi_pll_set_clock_div(struct platform_device *dsidev,
304 struct dsi_clock_info *cinfo); 303 struct dsi_clock_info *cinfo);
305int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, 304int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
306 unsigned long req_pck, struct dsi_clock_info *cinfo, 305 unsigned long req_pck, struct dsi_clock_info *cinfo,
307 struct dispc_clock_info *dispc_cinfo); 306 struct dispc_clock_info *dispc_cinfo);
308int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, 307int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
@@ -336,7 +335,7 @@ static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
336 return -ENODEV; 335 return -ENODEV;
337} 336}
338static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, 337static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
339 bool is_tft, unsigned long req_pck, 338 unsigned long req_pck,
340 struct dsi_clock_info *dsi_cinfo, 339 struct dsi_clock_info *dsi_cinfo,
341 struct dispc_clock_info *dispc_cinfo) 340 struct dispc_clock_info *dispc_cinfo)
342{ 341{
@@ -393,7 +392,7 @@ void dispc_set_loadmode(enum omap_dss_load_mode mode);
393bool dispc_mgr_timings_ok(enum omap_channel channel, 392bool dispc_mgr_timings_ok(enum omap_channel channel,
394 const struct omap_video_timings *timings); 393 const struct omap_video_timings *timings);
395unsigned long dispc_fclk_rate(void); 394unsigned long dispc_fclk_rate(void);
396void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, 395void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
397 struct dispc_clock_info *cinfo); 396 struct dispc_clock_info *cinfo);
398int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 397int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
399 struct dispc_clock_info *cinfo); 398 struct dispc_clock_info *cinfo);
@@ -404,8 +403,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
404 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 403 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
405 bool manual_update); 404 bool manual_update);
406int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi, 405int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
407 bool ilace, bool replication, 406 bool replication, const struct omap_video_timings *mgr_timings);
408 const struct omap_video_timings *mgr_timings);
409int dispc_ovl_enable(enum omap_plane plane, bool enable); 407int dispc_ovl_enable(enum omap_plane plane, bool enable);
410void dispc_ovl_set_channel_out(enum omap_plane plane, 408void dispc_ovl_set_channel_out(enum omap_plane plane,
411 enum omap_channel channel); 409 enum omap_channel channel);
@@ -421,12 +419,9 @@ bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
421void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode); 419void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
422void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable); 420void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
423void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines); 421void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
424void dispc_mgr_set_lcd_display_type(enum omap_channel channel, 422void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
425 enum omap_lcd_display_type type);
426void dispc_mgr_set_timings(enum omap_channel channel, 423void dispc_mgr_set_timings(enum omap_channel channel,
427 struct omap_video_timings *timings); 424 struct omap_video_timings *timings);
428void dispc_mgr_set_pol_freq(enum omap_channel channel,
429 enum omap_panel_config config, u8 acbi, u8 acb);
430unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 425unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
431unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 426unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
432unsigned long dispc_core_clk_rate(void); 427unsigned long dispc_core_clk_rate(void);
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index fb834abc5c2..060216fdc57 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -78,43 +78,214 @@ static struct {
78 */ 78 */
79 79
80static const struct hdmi_config cea_timings[] = { 80static const struct hdmi_config cea_timings[] = {
81{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} }, 81 {
82{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} }, 82 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
83{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} }, 83 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
84{ {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} }, 84 false, },
85{ {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} }, 85 { 1, HDMI_HDMI },
86{ {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} }, 86 },
87{ {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} }, 87 {
88{ {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} }, 88 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
89{ {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} }, 89 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
90{ {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} }, 90 false, },
91{ {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} }, 91 { 2, HDMI_HDMI },
92{ {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} }, 92 },
93{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} }, 93 {
94{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} }, 94 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
95{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} }, 95 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
96 false, },
97 { 4, HDMI_HDMI },
98 },
99 {
100 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
101 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
102 true, },
103 { 5, HDMI_HDMI },
104 },
105 {
106 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
107 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
108 true, },
109 { 6, HDMI_HDMI },
110 },
111 {
112 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
113 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
114 false, },
115 { 16, HDMI_HDMI },
116 },
117 {
118 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
119 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
120 false, },
121 { 17, HDMI_HDMI },
122 },
123 {
124 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
125 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
126 false, },
127 { 19, HDMI_HDMI },
128 },
129 {
130 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
131 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
132 true, },
133 { 20, HDMI_HDMI },
134 },
135 {
136 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
137 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
138 true, },
139 { 21, HDMI_HDMI },
140 },
141 {
142 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
143 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
144 false, },
145 { 29, HDMI_HDMI },
146 },
147 {
148 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
149 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
150 false, },
151 { 31, HDMI_HDMI },
152 },
153 {
154 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
155 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
156 false, },
157 { 32, HDMI_HDMI },
158 },
159 {
160 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
161 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
162 false, },
163 { 35, HDMI_HDMI },
164 },
165 {
166 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
167 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
168 false, },
169 { 37, HDMI_HDMI },
170 },
96}; 171};
172
97static const struct hdmi_config vesa_timings[] = { 173static const struct hdmi_config vesa_timings[] = {
98/* VESA From Here */ 174/* VESA From Here */
99{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} }, 175 {
100{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} }, 176 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
101{ {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} }, 177 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
102{ {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} }, 178 false, },
103{ {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} }, 179 { 4, HDMI_DVI },
104{ {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} }, 180 },
105{ {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} }, 181 {
106{ {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} }, 182 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
107{ {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} }, 183 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
108{ {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} }, 184 false, },
109{ {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} }, 185 { 9, HDMI_DVI },
110{ {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} }, 186 },
111{ {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} }, 187 {
112{ {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} }, 188 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
113{ {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} }, 189 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
114{ {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} }, 190 false, },
115{ {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} }, 191 { 0xE, HDMI_DVI },
116{ {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} }, 192 },
117{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} } 193 {
194 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
195 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
196 false, },
197 { 0x17, HDMI_DVI },
198 },
199 {
200 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
201 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
202 false, },
203 { 0x1C, HDMI_DVI },
204 },
205 {
206 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
207 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
208 false, },
209 { 0x27, HDMI_DVI },
210 },
211 {
212 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
213 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
214 false, },
215 { 0x20, HDMI_DVI },
216 },
217 {
218 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
219 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
220 false, },
221 { 0x23, HDMI_DVI },
222 },
223 {
224 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
225 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
226 false, },
227 { 0x10, HDMI_DVI },
228 },
229 {
230 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
231 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
232 false, },
233 { 0x2A, HDMI_DVI },
234 },
235 {
236 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
237 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
238 false, },
239 { 0x2F, HDMI_DVI },
240 },
241 {
242 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
243 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
244 false, },
245 { 0x3A, HDMI_DVI },
246 },
247 {
248 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
249 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
250 false, },
251 { 0x51, HDMI_DVI },
252 },
253 {
254 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
255 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
256 false, },
257 { 0x52, HDMI_DVI },
258 },
259 {
260 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
261 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
262 false, },
263 { 0x16, HDMI_DVI },
264 },
265 {
266 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
267 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
268 false, },
269 { 0x29, HDMI_DVI },
270 },
271 {
272 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
273 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
274 false, },
275 { 0x39, HDMI_DVI },
276 },
277 {
278 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
279 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
280 false, },
281 { 0x1B, HDMI_DVI },
282 },
283 {
284 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
285 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
286 false, },
287 { 0x55, HDMI_DVI },
288 },
118}; 289};
119 290
120static int hdmi_runtime_get(void) 291static int hdmi_runtime_get(void)
@@ -179,7 +350,7 @@ static const struct hdmi_config *hdmi_get_timings(void)
179} 350}
180 351
181static bool hdmi_timings_compare(struct omap_video_timings *timing1, 352static bool hdmi_timings_compare(struct omap_video_timings *timing1,
182 const struct hdmi_video_timings *timing2) 353 const struct omap_video_timings *timing2)
183{ 354{
184 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; 355 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
185 356
diff --git a/drivers/video/omap2/dss/hdmi_panel.c b/drivers/video/omap2/dss/hdmi_panel.c
index 1179e3c4b1c..e10844faadf 100644
--- a/drivers/video/omap2/dss/hdmi_panel.c
+++ b/drivers/video/omap2/dss/hdmi_panel.c
@@ -43,10 +43,11 @@ static int hdmi_panel_probe(struct omap_dss_device *dssdev)
43{ 43{
44 DSSDBG("ENTER hdmi_panel_probe\n"); 44 DSSDBG("ENTER hdmi_panel_probe\n");
45 45
46 dssdev->panel.config = OMAP_DSS_LCD_TFT | 46 dssdev->panel.timings = (struct omap_video_timings)
47 OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS; 47 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
48 48 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
49 dssdev->panel.timings = (struct omap_video_timings){640, 480, 25175, 96, 16, 48, 2 , 11, 31}; 49 false,
50 };
50 51
51 DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n", 52 DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",
52 dssdev->panel.timings.x_res, 53 dssdev->panel.timings.x_res,
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index 7985fa12b9b..539d709c6c0 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -885,8 +885,7 @@ int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
885 goto err1; 885 goto err1;
886 } 886 }
887 887
888 dispc_mgr_set_lcd_display_type(dssdev->manager->id, 888 dispc_mgr_set_lcd_type_tft(dssdev->manager->id);
889 OMAP_DSS_LCD_DISPLAY_TFT);
890 889
891 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_RFBI); 890 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_RFBI);
892 dispc_mgr_enable_stallmode(dssdev->manager->id, true); 891 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index 3a43dc2a9b4..0fcd4d7e202 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -40,8 +40,7 @@ static void sdi_basic_init(struct omap_dss_device *dssdev)
40 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS); 40 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
41 dispc_mgr_enable_stallmode(dssdev->manager->id, false); 41 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
42 42
43 dispc_mgr_set_lcd_display_type(dssdev->manager->id, 43 dispc_mgr_set_lcd_type_tft(dssdev->manager->id);
44 OMAP_DSS_LCD_DISPLAY_TFT);
45 44
46 dispc_mgr_set_tft_data_lines(dssdev->manager->id, 24); 45 dispc_mgr_set_tft_data_lines(dssdev->manager->id, 24);
47 dispc_lcd_enable_signal_polarity(1); 46 dispc_lcd_enable_signal_polarity(1);
@@ -79,13 +78,10 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
79 sdi_basic_init(dssdev); 78 sdi_basic_init(dssdev);
80 79
81 /* 15.5.9.1.2 */ 80 /* 15.5.9.1.2 */
82 dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF; 81 dssdev->panel.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
82 dssdev->panel.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
83 83
84 dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config, 84 r = dss_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
85 dssdev->panel.acbi, dssdev->panel.acb);
86
87 r = dss_calc_clock_div(1, t->pixel_clock * 1000,
88 &dss_cinfo, &dispc_cinfo);
89 if (r) 85 if (r)
90 goto err_calc_clock_div; 86 goto err_calc_clock_div;
91 87
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h
index cc292b829c9..b046c208cb9 100644
--- a/drivers/video/omap2/dss/ti_hdmi.h
+++ b/drivers/video/omap2/dss/ti_hdmi.h
@@ -42,30 +42,13 @@ enum hdmi_clk_refsel {
42 HDMI_REFSEL_SYSCLK = 3 42 HDMI_REFSEL_SYSCLK = 3
43}; 43};
44 44
45/* HDMI timing structure */
46struct hdmi_video_timings {
47 u16 x_res;
48 u16 y_res;
49 /* Unit: KHz */
50 u32 pixel_clock;
51 u16 hsw;
52 u16 hfp;
53 u16 hbp;
54 u16 vsw;
55 u16 vfp;
56 u16 vbp;
57 bool vsync_pol;
58 bool hsync_pol;
59 bool interlace;
60};
61
62struct hdmi_cm { 45struct hdmi_cm {
63 int code; 46 int code;
64 int mode; 47 int mode;
65}; 48};
66 49
67struct hdmi_config { 50struct hdmi_config {
68 struct hdmi_video_timings timings; 51 struct omap_video_timings timings;
69 struct hdmi_cm cm; 52 struct hdmi_cm cm;
70}; 53};
71 54
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 49b171b1f4a..c23b85a20cd 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -741,11 +741,15 @@ static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
741static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data) 741static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
742{ 742{
743 u32 r; 743 u32 r;
744 bool vsync_pol, hsync_pol;
744 pr_debug("Enter hdmi_wp_video_config_interface\n"); 745 pr_debug("Enter hdmi_wp_video_config_interface\n");
745 746
747 vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
748 hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
749
746 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); 750 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
747 r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7); 751 r = FLD_MOD(r, vsync_pol, 7, 7);
748 r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6); 752 r = FLD_MOD(r, hsync_pol, 6, 6);
749 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3); 753 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
750 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ 754 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
751 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); 755 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index 416d478803e..3a220877461 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -272,6 +272,8 @@ const struct omap_video_timings omap_dss_pal_timings = {
272 .vsw = 5, 272 .vsw = 5,
273 .vfp = 5, 273 .vfp = 5,
274 .vbp = 41, 274 .vbp = 41,
275
276 .interlace = true,
275}; 277};
276EXPORT_SYMBOL(omap_dss_pal_timings); 278EXPORT_SYMBOL(omap_dss_pal_timings);
277 279
@@ -285,6 +287,8 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
285 .vsw = 6, 287 .vsw = 6,
286 .vfp = 6, 288 .vfp = 6,
287 .vbp = 31, 289 .vbp = 31,
290
291 .interlace = true,
288}; 292};
289EXPORT_SYMBOL(omap_dss_ntsc_timings); 293EXPORT_SYMBOL(omap_dss_ntsc_timings);
290 294
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 3450ea0966c..08ec1a7103f 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -733,6 +733,12 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
733 var->lower_margin = timings.vfp; 733 var->lower_margin = timings.vfp;
734 var->hsync_len = timings.hsw; 734 var->hsync_len = timings.hsw;
735 var->vsync_len = timings.vsw; 735 var->vsync_len = timings.vsw;
736 var->sync |= timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH ?
737 FB_SYNC_HOR_HIGH_ACT : 0;
738 var->sync |= timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH ?
739 FB_SYNC_VERT_HIGH_ACT : 0;
740 var->vmode = timings.interlace ?
741 FB_VMODE_INTERLACED : FB_VMODE_NONINTERLACED;
736 } else { 742 } else {
737 var->pixclock = 0; 743 var->pixclock = 0;
738 var->left_margin = 0; 744 var->left_margin = 0;
@@ -741,12 +747,10 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
741 var->lower_margin = 0; 747 var->lower_margin = 0;
742 var->hsync_len = 0; 748 var->hsync_len = 0;
743 var->vsync_len = 0; 749 var->vsync_len = 0;
750 var->sync = 0;
751 var->vmode = FB_VMODE_NONINTERLACED;
744 } 752 }
745 753
746 /* TODO: get these from panel->config */
747 var->vmode = FB_VMODE_NONINTERLACED;
748 var->sync = 0;
749
750 return 0; 754 return 0;
751} 755}
752 756
@@ -1993,6 +1997,7 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
1993} 1997}
1994 1998
1995static int omapfb_mode_to_timings(const char *mode_str, 1999static int omapfb_mode_to_timings(const char *mode_str,
2000 struct omap_dss_device *display,
1996 struct omap_video_timings *timings, u8 *bpp) 2001 struct omap_video_timings *timings, u8 *bpp)
1997{ 2002{
1998 struct fb_info *fbi; 2003 struct fb_info *fbi;
@@ -2046,6 +2051,14 @@ static int omapfb_mode_to_timings(const char *mode_str,
2046 goto err; 2051 goto err;
2047 } 2052 }
2048 2053
2054 if (display->driver->get_timings) {
2055 display->driver->get_timings(display, timings);
2056 } else {
2057 timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
2058 timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
2059 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
2060 }
2061
2049 timings->pixel_clock = PICOS2KHZ(var->pixclock); 2062 timings->pixel_clock = PICOS2KHZ(var->pixclock);
2050 timings->hbp = var->left_margin; 2063 timings->hbp = var->left_margin;
2051 timings->hfp = var->right_margin; 2064 timings->hfp = var->right_margin;
@@ -2055,6 +2068,13 @@ static int omapfb_mode_to_timings(const char *mode_str,
2055 timings->vsw = var->vsync_len; 2068 timings->vsw = var->vsync_len;
2056 timings->x_res = var->xres; 2069 timings->x_res = var->xres;
2057 timings->y_res = var->yres; 2070 timings->y_res = var->yres;
2071 timings->hsync_level = var->sync & FB_SYNC_HOR_HIGH_ACT ?
2072 OMAPDSS_SIG_ACTIVE_HIGH :
2073 OMAPDSS_SIG_ACTIVE_LOW;
2074 timings->vsync_level = var->sync & FB_SYNC_VERT_HIGH_ACT ?
2075 OMAPDSS_SIG_ACTIVE_HIGH :
2076 OMAPDSS_SIG_ACTIVE_LOW;
2077 timings->interlace = var->vmode & FB_VMODE_INTERLACED;
2058 2078
2059 switch (var->bits_per_pixel) { 2079 switch (var->bits_per_pixel) {
2060 case 16: 2080 case 16:
@@ -2085,7 +2105,7 @@ static int omapfb_set_def_mode(struct omapfb2_device *fbdev,
2085 struct omap_video_timings timings, temp_timings; 2105 struct omap_video_timings timings, temp_timings;
2086 struct omapfb_display_data *d; 2106 struct omapfb_display_data *d;
2087 2107
2088 r = omapfb_mode_to_timings(mode_str, &timings, &bpp); 2108 r = omapfb_mode_to_timings(mode_str, display, &timings, &bpp);
2089 if (r) 2109 if (r)
2090 return r; 2110 return r;
2091 2111
@@ -2178,8 +2198,17 @@ static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
2178} 2198}
2179 2199
2180static void fb_videomode_to_omap_timings(struct fb_videomode *m, 2200static void fb_videomode_to_omap_timings(struct fb_videomode *m,
2201 struct omap_dss_device *display,
2181 struct omap_video_timings *t) 2202 struct omap_video_timings *t)
2182{ 2203{
2204 if (display->driver->get_timings) {
2205 display->driver->get_timings(display, t);
2206 } else {
2207 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
2208 t->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
2209 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
2210 }
2211
2183 t->x_res = m->xres; 2212 t->x_res = m->xres;
2184 t->y_res = m->yres; 2213 t->y_res = m->yres;
2185 t->pixel_clock = PICOS2KHZ(m->pixclock); 2214 t->pixel_clock = PICOS2KHZ(m->pixclock);
@@ -2189,6 +2218,13 @@ static void fb_videomode_to_omap_timings(struct fb_videomode *m,
2189 t->vsw = m->vsync_len; 2218 t->vsw = m->vsync_len;
2190 t->vfp = m->lower_margin; 2219 t->vfp = m->lower_margin;
2191 t->vbp = m->upper_margin; 2220 t->vbp = m->upper_margin;
2221 t->hsync_level = m->sync & FB_SYNC_HOR_HIGH_ACT ?
2222 OMAPDSS_SIG_ACTIVE_HIGH :
2223 OMAPDSS_SIG_ACTIVE_LOW;
2224 t->vsync_level = m->sync & FB_SYNC_VERT_HIGH_ACT ?
2225 OMAPDSS_SIG_ACTIVE_HIGH :
2226 OMAPDSS_SIG_ACTIVE_LOW;
2227 t->interlace = m->vmode & FB_VMODE_INTERLACED;
2192} 2228}
2193 2229
2194static int omapfb_find_best_mode(struct omap_dss_device *display, 2230static int omapfb_find_best_mode(struct omap_dss_device *display,
@@ -2231,7 +2267,7 @@ static int omapfb_find_best_mode(struct omap_dss_device *display,
2231 if (m->xres == 2880 || m->xres == 1440) 2267 if (m->xres == 2880 || m->xres == 1440)
2232 continue; 2268 continue;
2233 2269
2234 fb_videomode_to_omap_timings(m, &t); 2270 fb_videomode_to_omap_timings(m, display, &t);
2235 2271
2236 r = display->driver->check_timings(display, &t); 2272 r = display->driver->check_timings(display, &t);
2237 if (r == 0 && best_xres < m->xres) { 2273 if (r == 0 && best_xres < m->xres) {
@@ -2245,7 +2281,8 @@ static int omapfb_find_best_mode(struct omap_dss_device *display,
2245 goto err2; 2281 goto err2;
2246 } 2282 }
2247 2283
2248 fb_videomode_to_omap_timings(&specs->modedb[best_idx], timings); 2284 fb_videomode_to_omap_timings(&specs->modedb[best_idx], display,
2285 timings);
2249 2286
2250 r = 0; 2287 r = 0;
2251 2288
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 117de0e695f..a6267a2d292 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -104,11 +104,6 @@ enum omap_color_mode {
104 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ 104 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
105}; 105};
106 106
107enum omap_lcd_display_type {
108 OMAP_DSS_LCD_DISPLAY_STN,
109 OMAP_DSS_LCD_DISPLAY_TFT,
110};
111
112enum omap_dss_load_mode { 107enum omap_dss_load_mode {
113 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 108 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
114 OMAP_DSS_LOAD_CLUT_ONLY = 1, 109 OMAP_DSS_LOAD_CLUT_ONLY = 1,
@@ -126,15 +121,15 @@ enum omap_rfbi_te_mode {
126 OMAP_DSS_RFBI_TE_MODE_2 = 2, 121 OMAP_DSS_RFBI_TE_MODE_2 = 2,
127}; 122};
128 123
129enum omap_panel_config { 124enum omap_dss_signal_level {
130 OMAP_DSS_LCD_IVS = 1<<0, 125 OMAPDSS_SIG_ACTIVE_HIGH = 0,
131 OMAP_DSS_LCD_IHS = 1<<1, 126 OMAPDSS_SIG_ACTIVE_LOW = 1,
132 OMAP_DSS_LCD_IPC = 1<<2, 127};
133 OMAP_DSS_LCD_IEO = 1<<3,
134 OMAP_DSS_LCD_RF = 1<<4,
135 OMAP_DSS_LCD_ONOFF = 1<<5,
136 128
137 OMAP_DSS_LCD_TFT = 1<<20, 129enum omap_dss_signal_edge {
130 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
131 OMAPDSS_DRIVE_SIG_RISING_EDGE,
132 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
138}; 133};
139 134
140enum omap_dss_venc_type { 135enum omap_dss_venc_type {
@@ -266,9 +261,6 @@ struct omap_dss_dsi_videomode_data {
266 int hfp_blanking_mode; 261 int hfp_blanking_mode;
267 262
268 /* Video port sync events */ 263 /* Video port sync events */
269 int vp_de_pol;
270 int vp_hsync_pol;
271 int vp_vsync_pol;
272 bool vp_vsync_end; 264 bool vp_vsync_end;
273 bool vp_hsync_end; 265 bool vp_hsync_end;
274 266
@@ -344,6 +336,19 @@ struct omap_video_timings {
344 u16 vfp; /* Vertical front porch */ 336 u16 vfp; /* Vertical front porch */
345 /* Unit: line clocks */ 337 /* Unit: line clocks */
346 u16 vbp; /* Vertical back porch */ 338 u16 vbp; /* Vertical back porch */
339
340 /* Vsync logic level */
341 enum omap_dss_signal_level vsync_level;
342 /* Hsync logic level */
343 enum omap_dss_signal_level hsync_level;
344 /* Interlaced or Progressive timings */
345 bool interlace;
346 /* Pixel clock edge to drive LCD data */
347 enum omap_dss_signal_edge data_pclk_edge;
348 /* Data enable logic level */
349 enum omap_dss_signal_level de_level;
350 /* Pixel clock edges to drive HSYNC and VSYNC signals */
351 enum omap_dss_signal_edge sync_pclk_edge;
347}; 352};
348 353
349#ifdef CONFIG_OMAP2_DSS_VENC 354#ifdef CONFIG_OMAP2_DSS_VENC
@@ -557,8 +562,6 @@ struct omap_dss_device {
557 /* Unit: line clocks */ 562 /* Unit: line clocks */
558 int acb; /* ac-bias pin frequency */ 563 int acb; /* ac-bias pin frequency */
559 564
560 enum omap_panel_config config;
561
562 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 565 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
563 enum omap_dss_dsi_mode dsi_mode; 566 enum omap_dss_dsi_mode dsi_mode;
564 struct omap_dss_dsi_videomode_data dsi_vm_data; 567 struct omap_dss_dsi_videomode_data dsi_vm_data;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 17:59:33 -0500