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path: root/drivers/video/omap2/dss/dsi.c
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Diffstat (limited to 'drivers/video/omap2/dss/dsi.c')
-rw-r--r--drivers/video/omap2/dss/dsi.c61
1 files changed, 35 insertions, 26 deletions
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index df65b93c065..e0d43b275e3 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1316,7 +1316,7 @@ static int dsi_calc_clock_rates(struct platform_device *dsidev,
1316 return 0; 1316 return 0;
1317} 1317}
1318 1318
1319int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, 1319int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1320 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, 1320 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1321 struct dispc_clock_info *dispc_cinfo) 1321 struct dispc_clock_info *dispc_cinfo)
1322{ 1322{
@@ -1335,8 +1335,8 @@ int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1335 dsi->cache_cinfo.clkin == dss_sys_clk) { 1335 dsi->cache_cinfo.clkin == dss_sys_clk) {
1336 DSSDBG("DSI clock info found from cache\n"); 1336 DSSDBG("DSI clock info found from cache\n");
1337 *dsi_cinfo = dsi->cache_cinfo; 1337 *dsi_cinfo = dsi->cache_cinfo;
1338 dispc_find_clk_divs(is_tft, req_pck, 1338 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1339 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); 1339 dispc_cinfo);
1340 return 0; 1340 return 0;
1341 } 1341 }
1342 1342
@@ -1402,7 +1402,7 @@ retry:
1402 1402
1403 match = 1; 1403 match = 1;
1404 1404
1405 dispc_find_clk_divs(is_tft, req_pck, 1405 dispc_find_clk_divs(req_pck,
1406 cur.dsi_pll_hsdiv_dispc_clk, 1406 cur.dsi_pll_hsdiv_dispc_clk,
1407 &cur_dispc); 1407 &cur_dispc);
1408 1408
@@ -3631,17 +3631,14 @@ static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3631static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev) 3631static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3632{ 3632{
3633 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3633 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3634 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3635 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3636 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3637 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end; 3634 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3638 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; 3635 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3639 u32 r; 3636 u32 r;
3640 3637
3641 r = dsi_read_reg(dsidev, DSI_CTRL); 3638 r = dsi_read_reg(dsidev, DSI_CTRL);
3642 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */ 3639 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3643 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */ 3640 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3644 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */ 3641 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3645 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3642 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3646 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ 3643 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3647 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3644 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
@@ -4343,22 +4340,22 @@ EXPORT_SYMBOL(omap_dsi_update);
4343static int dsi_display_init_dispc(struct omap_dss_device *dssdev) 4340static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4344{ 4341{
4345 int r; 4342 int r;
4343 struct omap_video_timings timings;
4346 4344
4347 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { 4345 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4348 u16 dw, dh; 4346 u16 dw, dh;
4349 u32 irq; 4347 u32 irq;
4350 struct omap_video_timings timings = {
4351 .hsw = 1,
4352 .hfp = 1,
4353 .hbp = 1,
4354 .vsw = 1,
4355 .vfp = 0,
4356 .vbp = 0,
4357 };
4358 4348
4359 dssdev->driver->get_resolution(dssdev, &dw, &dh); 4349 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4350
4360 timings.x_res = dw; 4351 timings.x_res = dw;
4361 timings.y_res = dh; 4352 timings.y_res = dh;
4353 timings.hsw = 1;
4354 timings.hfp = 1;
4355 timings.hbp = 1;
4356 timings.vsw = 1;
4357 timings.vfp = 0;
4358 timings.vbp = 0;
4362 4359
4363 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id); 4360 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
4364 4361
@@ -4371,19 +4368,31 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4371 4368
4372 dispc_mgr_enable_stallmode(dssdev->manager->id, true); 4369 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4373 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1); 4370 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4374
4375 dss_mgr_set_timings(dssdev->manager, &timings);
4376 } else { 4371 } else {
4372 timings = dssdev->panel.timings;
4373
4377 dispc_mgr_enable_stallmode(dssdev->manager->id, false); 4374 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4378 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0); 4375 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4379
4380 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
4381 } 4376 }
4382 4377
4383 dispc_mgr_set_lcd_display_type(dssdev->manager->id, 4378 /*
4384 OMAP_DSS_LCD_DISPLAY_TFT); 4379 * override interlace, logic level and edge related parameters in
4385 dispc_mgr_set_tft_data_lines(dssdev->manager->id, 4380 * omap_video_timings with default values
4386 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)); 4381 */
4382 timings.interlace = false;
4383 timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4384 timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4385 timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4386 timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4387 timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4388
4389 dss_mgr_set_timings(dssdev->manager, &timings);
4390
4391 dispc_mgr_set_lcd_type_tft(dssdev->manager->id);
4392
4393 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4394 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4395
4387 return 0; 4396 return 0;
4388} 4397}
4389 4398