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authorStephen Warren <swarren@nvidia.com>2012-05-11 18:11:38 -0400
committerStephen Warren <swarren@nvidia.com>2012-05-14 12:54:55 -0400
commit95decf84742d712a5875bb655cd7440f6d7c1184 (patch)
tree8e08897a8b279cb40b4f4679651bd8f1871a0942
parent1dfebb426cfd16e2080f8c95e00ca2462f2325d4 (diff)
ARM: dt: tegra: whitespace cleanup
Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts4
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts8
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts26
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts4
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts8
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi101
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi120
7 files changed, 135 insertions, 136 deletions
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 74d1ca4fc1b..378b65e186e 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -7,7 +7,7 @@
7 compatible = "nvidia,cardhu", "nvidia,tegra30"; 7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8 8
9 memory { 9 memory {
10 reg = < 0x80000000 0x40000000 >; 10 reg = <0x80000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux@70000000 {
@@ -64,7 +64,7 @@
64 }; 64 };
65 65
66 serial@70006000 { 66 serial@70006000 {
67 clock-frequency = < 408000000 >; 67 clock-frequency = <408000000>;
68 }; 68 };
69 69
70 serial@70006040 { 70 serial@70006040 {
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6857cec8382..04647b3175d 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -7,7 +7,7 @@
7 compatible = "nvidia,harmony", "nvidia,tegra20"; 7 compatible = "nvidia,harmony", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory@0 {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux@70000000 {
@@ -245,14 +245,14 @@
245 compatible = "wlf,wm8903"; 245 compatible = "wlf,wm8903";
246 reg = <0x1a>; 246 reg = <0x1a>;
247 interrupt-parent = <&gpio>; 247 interrupt-parent = <&gpio>;
248 interrupts = < 187 0x04 >; 248 interrupts = <187 0x04>;
249 249
250 gpio-controller; 250 gpio-controller;
251 #gpio-cells = <2>; 251 #gpio-cells = <2>;
252 252
253 micdet-cfg = <0>; 253 micdet-cfg = <0>;
254 micdet-delay = <100>; 254 micdet-delay = <100>;
255 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 255 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
256 }; 256 };
257 }; 257 };
258 258
@@ -309,7 +309,7 @@
309 }; 309 };
310 310
311 serial@70006300 { 311 serial@70006300 {
312 clock-frequency = < 216000000 >; 312 clock-frequency = <216000000>;
313 }; 313 };
314 314
315 serial@70006400 { 315 serial@70006400 {
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index c4d171ec9ee..d4cbd8054c0 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -8,7 +8,7 @@
8 8
9 memory { 9 memory {
10 device_type = "memory"; 10 device_type = "memory";
11 reg = < 0x00000000 0x40000000 >; 11 reg = <0x00000000 0x40000000>;
12 }; 12 };
13 13
14 pinmux@70000000 { 14 pinmux@70000000 {
@@ -265,14 +265,14 @@
265 compatible = "wlf,wm8903"; 265 compatible = "wlf,wm8903";
266 reg = <0x1a>; 266 reg = <0x1a>;
267 interrupt-parent = <&gpio>; 267 interrupt-parent = <&gpio>;
268 interrupts = < 187 0x04 >; 268 interrupts = <187 0x04>;
269 269
270 gpio-controller; 270 gpio-controller;
271 #gpio-cells = <2>; 271 #gpio-cells = <2>;
272 272
273 micdet-cfg = <0>; 273 micdet-cfg = <0>;
274 micdet-delay = <100>; 274 micdet-delay = <100>;
275 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 275 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
276 }; 276 };
277 277
278 /* ALS and proximity sensor */ 278 /* ALS and proximity sensor */
@@ -280,7 +280,7 @@
280 compatible = "isil,isl29018"; 280 compatible = "isil,isl29018";
281 reg = <0x44>; 281 reg = <0x44>;
282 interrupt-parent = <&gpio>; 282 interrupt-parent = <&gpio>;
283 interrupts = < 202 0x04 >; /* GPIO PZ2 */ 283 interrupts = <202 0x04>; /* GPIO PZ2 */
284 }; 284 };
285 285
286 gyrometer@68 { 286 gyrometer@68 {
@@ -361,7 +361,7 @@
361 }; 361 };
362 362
363 serial@70006300 { 363 serial@70006300 {
364 clock-frequency = < 216000000 >; 364 clock-frequency = <216000000>;
365 }; 365 };
366 366
367 serial@70006400 { 367 serial@70006400 {
@@ -413,10 +413,10 @@
413 413
414 emc@7000f400 { 414 emc@7000f400 {
415 emc-table@190000 { 415 emc-table@190000 {
416 reg = < 190000 >; 416 reg = <190000>;
417 compatible = "nvidia,tegra20-emc-table"; 417 compatible = "nvidia,tegra20-emc-table";
418 clock-frequency = < 190000 >; 418 clock-frequency = <190000>;
419 nvidia,emc-registers = < 0x0000000c 0x00000026 419 nvidia,emc-registers = <0x0000000c 0x00000026
420 0x00000009 0x00000003 0x00000004 0x00000004 420 0x00000009 0x00000003 0x00000004 0x00000004
421 0x00000002 0x0000000c 0x00000003 0x00000003 421 0x00000002 0x0000000c 0x00000003 0x00000003
422 0x00000002 0x00000001 0x00000004 0x00000005 422 0x00000002 0x00000001 0x00000004 0x00000005
@@ -427,14 +427,14 @@
427 0x00000002 0x00000000 0x00000000 0x00000002 427 0x00000002 0x00000000 0x00000000 0x00000002
428 0x00000000 0x00000000 0x00000083 0xa06204ae 428 0x00000000 0x00000000 0x00000083 0xa06204ae
429 0x007dc010 0x00000000 0x00000000 0x00000000 429 0x007dc010 0x00000000 0x00000000 0x00000000
430 0x00000000 0x00000000 0x00000000 0x00000000 >; 430 0x00000000 0x00000000 0x00000000 0x00000000>;
431 }; 431 };
432 432
433 emc-table@380000 { 433 emc-table@380000 {
434 reg = < 380000 >; 434 reg = <380000>;
435 compatible = "nvidia,tegra20-emc-table"; 435 compatible = "nvidia,tegra20-emc-table";
436 clock-frequency = < 380000 >; 436 clock-frequency = <380000>;
437 nvidia,emc-registers = < 0x00000017 0x0000004b 437 nvidia,emc-registers = <0x00000017 0x0000004b
438 0x00000012 0x00000006 0x00000004 0x00000005 438 0x00000012 0x00000006 0x00000004 0x00000005
439 0x00000003 0x0000000c 0x00000006 0x00000006 439 0x00000003 0x0000000c 0x00000006 0x00000006
440 0x00000003 0x00000001 0x00000004 0x00000005 440 0x00000003 0x00000001 0x00000004 0x00000005
@@ -445,7 +445,7 @@
445 0x00000002 0x00000000 0x00000000 0x00000002 445 0x00000002 0x00000000 0x00000000 0x00000002
446 0x00000000 0x00000000 0x00000083 0xe044048b 446 0x00000000 0x00000000 0x00000083 0xe044048b
447 0x007d8010 0x00000000 0x00000000 0x00000000 447 0x007d8010 0x00000000 0x00000000 0x00000000
448 0x00000000 0x00000000 0x00000000 0x00000000 >; 448 0x00000000 0x00000000 0x00000000 0x00000000>;
449 }; 449 };
450 }; 450 };
451 451
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index ead93657dd0..7181a5e9e48 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -7,7 +7,7 @@
7 compatible = "compulab,trimslice", "nvidia,tegra20"; 7 compatible = "compulab,trimslice", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory@0 {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux@70000000 {
@@ -277,7 +277,7 @@
277 }; 277 };
278 278
279 serial@70006000 { 279 serial@70006000 {
280 clock-frequency = < 216000000 >; 280 clock-frequency = <216000000>;
281 }; 281 };
282 282
283 serial@70006040 { 283 serial@70006040 {
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index c20d5e93f9c..9d2bc270b35 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -7,7 +7,7 @@
7 compatible = "nvidia,ventana", "nvidia,tegra20"; 7 compatible = "nvidia,ventana", "nvidia,tegra20";
8 8
9 memory { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux@70000000 {
@@ -247,14 +247,14 @@
247 compatible = "wlf,wm8903"; 247 compatible = "wlf,wm8903";
248 reg = <0x1a>; 248 reg = <0x1a>;
249 interrupt-parent = <&gpio>; 249 interrupt-parent = <&gpio>;
250 interrupts = < 187 0x04 >; 250 interrupts = <187 0x04>;
251 251
252 gpio-controller; 252 gpio-controller;
253 #gpio-cells = <2>; 253 #gpio-cells = <2>;
254 254
255 micdet-cfg = <0>; 255 micdet-cfg = <0>;
256 micdet-delay = <100>; 256 micdet-delay = <100>;
257 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 257 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
258 }; 258 };
259 259
260 /* ALS and proximity sensor */ 260 /* ALS and proximity sensor */
@@ -319,7 +319,7 @@
319 }; 319 };
320 320
321 serial@70006300 { 321 serial@70006300 {
322 clock-frequency = < 216000000 >; 322 clock-frequency = <216000000>;
323 }; 323 };
324 324
325 serial@70006400 { 325 serial@70006400 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index a76c8a85020..f98be33da70 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -13,8 +13,8 @@
13 compatible = "arm,cortex-a9-gic"; 13 compatible = "arm,cortex-a9-gic";
14 interrupt-controller; 14 interrupt-controller;
15 #interrupt-cells = <3>; 15 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >, 16 reg = <0x50041000 0x1000>,
17 < 0x50040100 0x0100 >; 17 <0x50040100 0x0100>;
18 }; 18 };
19 19
20 pmu { 20 pmu {
@@ -26,22 +26,22 @@
26 apbdma: dma@6000a000 { 26 apbdma: dma@6000a000 {
27 compatible = "nvidia,tegra20-apbdma"; 27 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>; 28 reg = <0x6000a000 0x1200>;
29 interrupts = < 0 104 0x04 29 interrupts = <0 104 0x04
30 0 105 0x04 30 0 105 0x04
31 0 106 0x04 31 0 106 0x04
32 0 107 0x04 32 0 107 0x04
33 0 108 0x04 33 0 108 0x04
34 0 109 0x04 34 0 109 0x04
35 0 110 0x04 35 0 110 0x04
36 0 111 0x04 36 0 111 0x04
37 0 112 0x04 37 0 112 0x04
38 0 113 0x04 38 0 113 0x04
39 0 114 0x04 39 0 114 0x04
40 0 115 0x04 40 0 115 0x04
41 0 116 0x04 41 0 116 0x04
42 0 117 0x04 42 0 117 0x04
43 0 118 0x04 43 0 118 0x04
44 0 119 0x04 >; 44 0 119 0x04>;
45 }; 45 };
46 46
47 i2c@7000c000 { 47 i2c@7000c000 {
@@ -49,7 +49,7 @@
49 #size-cells = <0>; 49 #size-cells = <0>;
50 compatible = "nvidia,tegra20-i2c"; 50 compatible = "nvidia,tegra20-i2c";
51 reg = <0x7000C000 0x100>; 51 reg = <0x7000C000 0x100>;
52 interrupts = < 0 38 0x04 >; 52 interrupts = <0 38 0x04>;
53 }; 53 };
54 54
55 i2c@7000c400 { 55 i2c@7000c400 {
@@ -57,7 +57,7 @@
57 #size-cells = <0>; 57 #size-cells = <0>;
58 compatible = "nvidia,tegra20-i2c"; 58 compatible = "nvidia,tegra20-i2c";
59 reg = <0x7000C400 0x100>; 59 reg = <0x7000C400 0x100>;
60 interrupts = < 0 84 0x04 >; 60 interrupts = <0 84 0x04>;
61 }; 61 };
62 62
63 i2c@7000c500 { 63 i2c@7000c500 {
@@ -65,7 +65,7 @@
65 #size-cells = <0>; 65 #size-cells = <0>;
66 compatible = "nvidia,tegra20-i2c"; 66 compatible = "nvidia,tegra20-i2c";
67 reg = <0x7000C500 0x100>; 67 reg = <0x7000C500 0x100>;
68 interrupts = < 0 92 0x04 >; 68 interrupts = <0 92 0x04>;
69 }; 69 };
70 70
71 i2c@7000d000 { 71 i2c@7000d000 {
@@ -73,21 +73,21 @@
73 #size-cells = <0>; 73 #size-cells = <0>;
74 compatible = "nvidia,tegra20-i2c-dvc"; 74 compatible = "nvidia,tegra20-i2c-dvc";
75 reg = <0x7000D000 0x200>; 75 reg = <0x7000D000 0x200>;
76 interrupts = < 0 53 0x04 >; 76 interrupts = <0 53 0x04>;
77 }; 77 };
78 78
79 tegra_i2s1: i2s@70002800 { 79 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s"; 80 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>; 81 reg = <0x70002800 0x200>;
82 interrupts = < 0 13 0x04 >; 82 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = < &apbdma 2 >; 83 nvidia,dma-request-selector = <&apbdma 2>;
84 }; 84 };
85 85
86 tegra_i2s2: i2s@70002a00 { 86 tegra_i2s2: i2s@70002a00 {
87 compatible = "nvidia,tegra20-i2s"; 87 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>; 88 reg = <0x70002a00 0x200>;
89 interrupts = < 0 3 0x04 >; 89 interrupts = <0 3 0x04>;
90 nvidia,dma-request-selector = < &apbdma 1 >; 90 nvidia,dma-request-selector = <&apbdma 1>;
91 }; 91 };
92 92
93 das@70000c00 { 93 das@70000c00 {
@@ -97,14 +97,14 @@
97 97
98 gpio: gpio@6000d000 { 98 gpio: gpio@6000d000 {
99 compatible = "nvidia,tegra20-gpio"; 99 compatible = "nvidia,tegra20-gpio";
100 reg = < 0x6000d000 0x1000 >; 100 reg = <0x6000d000 0x1000>;
101 interrupts = < 0 32 0x04 101 interrupts = <0 32 0x04
102 0 33 0x04 102 0 33 0x04
103 0 34 0x04 103 0 34 0x04
104 0 35 0x04 104 0 35 0x04
105 0 55 0x04 105 0 55 0x04
106 0 87 0x04 106 0 87 0x04
107 0 89 0x04 >; 107 0 89 0x04>;
108 #gpio-cells = <2>; 108 #gpio-cells = <2>;
109 gpio-controller; 109 gpio-controller;
110 #interrupt-cells = <2>; 110 #interrupt-cells = <2>;
@@ -113,45 +113,45 @@
113 113
114 pinmux: pinmux@70000000 { 114 pinmux: pinmux@70000000 {
115 compatible = "nvidia,tegra20-pinmux"; 115 compatible = "nvidia,tegra20-pinmux";
116 reg = < 0x70000014 0x10 /* Tri-state registers */ 116 reg = <0x70000014 0x10 /* Tri-state registers */
117 0x70000080 0x20 /* Mux registers */ 117 0x70000080 0x20 /* Mux registers */
118 0x700000a0 0x14 /* Pull-up/down registers */ 118 0x700000a0 0x14 /* Pull-up/down registers */
119 0x70000868 0xa8 >; /* Pad control registers */ 119 0x70000868 0xa8>; /* Pad control registers */
120 }; 120 };
121 121
122 serial@70006000 { 122 serial@70006000 {
123 compatible = "nvidia,tegra20-uart"; 123 compatible = "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 124 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 125 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 126 interrupts = <0 36 0x04>;
127 }; 127 };
128 128
129 serial@70006040 { 129 serial@70006040 {
130 compatible = "nvidia,tegra20-uart"; 130 compatible = "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 131 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 132 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 133 interrupts = <0 37 0x04>;
134 }; 134 };
135 135
136 serial@70006200 { 136 serial@70006200 {
137 compatible = "nvidia,tegra20-uart"; 137 compatible = "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 138 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 139 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 140 interrupts = <0 46 0x04>;
141 }; 141 };
142 142
143 serial@70006300 { 143 serial@70006300 {
144 compatible = "nvidia,tegra20-uart"; 144 compatible = "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 145 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 146 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 147 interrupts = <0 90 0x04>;
148 }; 148 };
149 149
150 serial@70006400 { 150 serial@70006400 {
151 compatible = "nvidia,tegra20-uart"; 151 compatible = "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 152 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 153 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 154 interrupts = <0 91 0x04>;
155 }; 155 };
156 156
157 emc@7000f400 { 157 emc@7000f400 {
@@ -164,31 +164,31 @@
164 sdhci@c8000000 { 164 sdhci@c8000000 {
165 compatible = "nvidia,tegra20-sdhci"; 165 compatible = "nvidia,tegra20-sdhci";
166 reg = <0xc8000000 0x200>; 166 reg = <0xc8000000 0x200>;
167 interrupts = < 0 14 0x04 >; 167 interrupts = <0 14 0x04>;
168 }; 168 };
169 169
170 sdhci@c8000200 { 170 sdhci@c8000200 {
171 compatible = "nvidia,tegra20-sdhci"; 171 compatible = "nvidia,tegra20-sdhci";
172 reg = <0xc8000200 0x200>; 172 reg = <0xc8000200 0x200>;
173 interrupts = < 0 15 0x04 >; 173 interrupts = <0 15 0x04>;
174 }; 174 };
175 175
176 sdhci@c8000400 { 176 sdhci@c8000400 {
177 compatible = "nvidia,tegra20-sdhci"; 177 compatible = "nvidia,tegra20-sdhci";
178 reg = <0xc8000400 0x200>; 178 reg = <0xc8000400 0x200>;
179 interrupts = < 0 19 0x04 >; 179 interrupts = <0 19 0x04>;
180 }; 180 };
181 181
182 sdhci@c8000600 { 182 sdhci@c8000600 {
183 compatible = "nvidia,tegra20-sdhci"; 183 compatible = "nvidia,tegra20-sdhci";
184 reg = <0xc8000600 0x200>; 184 reg = <0xc8000600 0x200>;
185 interrupts = < 0 31 0x04 >; 185 interrupts = <0 31 0x04>;
186 }; 186 };
187 187
188 usb@c5000000 { 188 usb@c5000000 {
189 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 189 compatible = "nvidia,tegra20-ehci", "usb-ehci";
190 reg = <0xc5000000 0x4000>; 190 reg = <0xc5000000 0x4000>;
191 interrupts = < 0 20 0x04 >; 191 interrupts = <0 20 0x04>;
192 phy_type = "utmi"; 192 phy_type = "utmi";
193 nvidia,has-legacy-mode; 193 nvidia,has-legacy-mode;
194 }; 194 };
@@ -196,14 +196,14 @@
196 usb@c5004000 { 196 usb@c5004000 {
197 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 197 compatible = "nvidia,tegra20-ehci", "usb-ehci";
198 reg = <0xc5004000 0x4000>; 198 reg = <0xc5004000 0x4000>;
199 interrupts = < 0 21 0x04 >; 199 interrupts = <0 21 0x04>;
200 phy_type = "ulpi"; 200 phy_type = "ulpi";
201 }; 201 };
202 202
203 usb@c5008000 { 203 usb@c5008000 {
204 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 204 compatible = "nvidia,tegra20-ehci", "usb-ehci";
205 reg = <0xc5008000 0x4000>; 205 reg = <0xc5008000 0x4000>;
206 interrupts = < 0 97 0x04 >; 206 interrupts = <0 97 0x04>;
207 phy_type = "utmi"; 207 phy_type = "utmi";
208 }; 208 };
209 209
@@ -225,4 +225,3 @@
225 0x58000000 0x02000000>; /* GART aperture */ 225 0x58000000 0x02000000>; /* GART aperture */
226 }; 226 };
227}; 227};
228
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index e9792ac0363..5dd6556fce0 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -13,8 +13,8 @@
13 compatible = "arm,cortex-a9-gic"; 13 compatible = "arm,cortex-a9-gic";
14 interrupt-controller; 14 interrupt-controller;
15 #interrupt-cells = <3>; 15 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >, 16 reg = <0x50041000 0x1000>,
17 < 0x50040100 0x0100 >; 17 <0x50040100 0x0100>;
18 }; 18 };
19 19
20 pmu { 20 pmu {
@@ -28,38 +28,38 @@
28 apbdma: dma@6000a000 { 28 apbdma: dma@6000a000 {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>; 30 reg = <0x6000a000 0x1400>;
31 interrupts = < 0 104 0x04 31 interrupts = <0 104 0x04
32 0 105 0x04 32 0 105 0x04
33 0 106 0x04 33 0 106 0x04
34 0 107 0x04 34 0 107 0x04
35 0 108 0x04 35 0 108 0x04
36 0 109 0x04 36 0 109 0x04
37 0 110 0x04 37 0 110 0x04
38 0 111 0x04 38 0 111 0x04
39 0 112 0x04 39 0 112 0x04
40 0 113 0x04 40 0 113 0x04
41 0 114 0x04 41 0 114 0x04
42 0 115 0x04 42 0 115 0x04
43 0 116 0x04 43 0 116 0x04
44 0 117 0x04 44 0 117 0x04
45 0 118 0x04 45 0 118 0x04
46 0 119 0x04 46 0 119 0x04
47 0 128 0x04 47 0 128 0x04
48 0 129 0x04 48 0 129 0x04
49 0 130 0x04 49 0 130 0x04
50 0 131 0x04 50 0 131 0x04
51 0 132 0x04 51 0 132 0x04
52 0 133 0x04 52 0 133 0x04
53 0 134 0x04 53 0 134 0x04
54 0 135 0x04 54 0 135 0x04
55 0 136 0x04 55 0 136 0x04
56 0 137 0x04 56 0 137 0x04
57 0 138 0x04 57 0 138 0x04
58 0 139 0x04 58 0 139 0x04
59 0 140 0x04 59 0 140 0x04
60 0 141 0x04 60 0 141 0x04
61 0 142 0x04 61 0 142 0x04
62 0 143 0x04 >; 62 0 143 0x04>;
63 }; 63 };
64 64
65 i2c@7000c000 { 65 i2c@7000c000 {
@@ -67,7 +67,7 @@
67 #size-cells = <0>; 67 #size-cells = <0>;
68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69 reg = <0x7000C000 0x100>; 69 reg = <0x7000C000 0x100>;
70 interrupts = < 0 38 0x04 >; 70 interrupts = <0 38 0x04>;
71 }; 71 };
72 72
73 i2c@7000c400 { 73 i2c@7000c400 {
@@ -75,7 +75,7 @@
75 #size-cells = <0>; 75 #size-cells = <0>;
76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77 reg = <0x7000C400 0x100>; 77 reg = <0x7000C400 0x100>;
78 interrupts = < 0 84 0x04 >; 78 interrupts = <0 84 0x04>;
79 }; 79 };
80 80
81 i2c@7000c500 { 81 i2c@7000c500 {
@@ -83,7 +83,7 @@
83 #size-cells = <0>; 83 #size-cells = <0>;
84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85 reg = <0x7000C500 0x100>; 85 reg = <0x7000C500 0x100>;
86 interrupts = < 0 92 0x04 >; 86 interrupts = <0 92 0x04>;
87 }; 87 };
88 88
89 i2c@7000c700 { 89 i2c@7000c700 {
@@ -91,7 +91,7 @@
91 #size-cells = <0>; 91 #size-cells = <0>;
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c700 0x100>; 93 reg = <0x7000c700 0x100>;
94 interrupts = < 0 120 0x04 >; 94 interrupts = <0 120 0x04>;
95 }; 95 };
96 96
97 i2c@7000d000 { 97 i2c@7000d000 {
@@ -99,20 +99,20 @@
99 #size-cells = <0>; 99 #size-cells = <0>;
100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
101 reg = <0x7000D000 0x100>; 101 reg = <0x7000D000 0x100>;
102 interrupts = < 0 53 0x04 >; 102 interrupts = <0 53 0x04>;
103 }; 103 };
104 104
105 gpio: gpio@6000d000 { 105 gpio: gpio@6000d000 {
106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; 106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
107 reg = < 0x6000d000 0x1000 >; 107 reg = <0x6000d000 0x1000>;
108 interrupts = < 0 32 0x04 108 interrupts = <0 32 0x04
109 0 33 0x04 109 0 33 0x04
110 0 34 0x04 110 0 34 0x04
111 0 35 0x04 111 0 35 0x04
112 0 55 0x04 112 0 55 0x04
113 0 87 0x04 113 0 87 0x04
114 0 89 0x04 114 0 89 0x04
115 0 125 0x04 >; 115 0 125 0x04>;
116 #gpio-cells = <2>; 116 #gpio-cells = <2>;
117 gpio-controller; 117 gpio-controller;
118 #interrupt-cells = <2>; 118 #interrupt-cells = <2>;
@@ -123,71 +123,71 @@
123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 124 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 125 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 126 interrupts = <0 36 0x04>;
127 }; 127 };
128 128
129 serial@70006040 { 129 serial@70006040 {
130 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 130 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 131 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 132 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 133 interrupts = <0 37 0x04>;
134 }; 134 };
135 135
136 serial@70006200 { 136 serial@70006200 {
137 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 137 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 138 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 139 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 140 interrupts = <0 46 0x04>;
141 }; 141 };
142 142
143 serial@70006300 { 143 serial@70006300 {
144 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 144 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 145 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 146 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 147 interrupts = <0 90 0x04>;
148 }; 148 };
149 149
150 serial@70006400 { 150 serial@70006400 {
151 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 151 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 152 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 153 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 154 interrupts = <0 91 0x04>;
155 }; 155 };
156 156
157 sdhci@78000000 { 157 sdhci@78000000 {
158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
159 reg = <0x78000000 0x200>; 159 reg = <0x78000000 0x200>;
160 interrupts = < 0 14 0x04 >; 160 interrupts = <0 14 0x04>;
161 }; 161 };
162 162
163 sdhci@78000200 { 163 sdhci@78000200 {
164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
165 reg = <0x78000200 0x200>; 165 reg = <0x78000200 0x200>;
166 interrupts = < 0 15 0x04 >; 166 interrupts = <0 15 0x04>;
167 }; 167 };
168 168
169 sdhci@78000400 { 169 sdhci@78000400 {
170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
171 reg = <0x78000400 0x200>; 171 reg = <0x78000400 0x200>;
172 interrupts = < 0 19 0x04 >; 172 interrupts = <0 19 0x04>;
173 }; 173 };
174 174
175 sdhci@78000600 { 175 sdhci@78000600 {
176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
177 reg = <0x78000600 0x200>; 177 reg = <0x78000600 0x200>;
178 interrupts = < 0 31 0x04 >; 178 interrupts = <0 31 0x04>;
179 }; 179 };
180 180
181 pinmux: pinmux@70000000 { 181 pinmux: pinmux@70000000 {
182 compatible = "nvidia,tegra30-pinmux"; 182 compatible = "nvidia,tegra30-pinmux";
183 reg = < 0x70000868 0xd0 /* Pad control registers */ 183 reg = <0x70000868 0xd0 /* Pad control registers */
184 0x70003000 0x3e0 >; /* Mux registers */ 184 0x70003000 0x3e0>; /* Mux registers */
185 }; 185 };
186 186
187 ahub { 187 ahub {
188 compatible = "nvidia,tegra30-ahub"; 188 compatible = "nvidia,tegra30-ahub";
189 reg = <0x70080000 0x200 0x70080200 0x100>; 189 reg = <0x70080000 0x200 0x70080200 0x100>;
190 interrupts = < 0 103 0x04 >; 190 interrupts = <0 103 0x04>;
191 nvidia,dma-request-selector = <&apbdma 1>; 191 nvidia,dma-request-selector = <&apbdma 1>;
192 192
193 ranges; 193 ranges;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 16:38:22 -0400