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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 12:39:42 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 12:39:42 -0400
commit813a95e5b4fa936bbde10ef89188932745dcd7f4 (patch)
tree571ca345861ffb89b45fabe26fcab4e133c8537b
parent9f639269ed1522c7d69c54cc8b80ab8ee53fcb10 (diff)
parentf3f08dcb9965f42378851ce888fb7539607712e6 (diff)
Merge tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm soc-specific pinctrl changes from Olof Johansson: "With this, five platforms are moving to the relatively new pinctrl subsystem for their pin management, replacing the older soc specific in-kernel interfaces with common code. There is quite a bit of net addition of code for each platform being added to the pinctrl subsystem. But the payback comes later when adding new boards can be done by only providing new device trees instead." Fix up trivial conflicts in arch/arm/mach-ux500/{Makefile,board-mop500.c} * tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (61 commits) mtd: nand: gpmi: fix compile error caused by pinctrl call ARM: PRIMA2: select PINCTRL and PINCTRL_SIRF in Kconfig ARM: nomadik: enable PINCTRL_NOMADIK where needed ARM: mxs: enable pinctrl support video: mxsfb: adopt pinctrl support ASoC: mxs-saif: adopt pinctrl support i2c: mxs: adopt pinctrl support mtd: nand: gpmi: adopt pinctrl support mmc: mxs-mmc: adopt pinctrl support serial: mxs-auart: adopt pinctrl support serial: amba-pl011: adopt pinctrl support spi/imx: adopt pinctrl support i2c: imx: adopt pinctrl support can: flexcan: adopt pinctrl support net: fec: adopt pinctrl support ARM: ux500: switch MSP to using pinctrl for pins ARM: ux500: alter MSP registration to return a device pointer ARM: ux500: switch to using pinctrl for uart0 ARM: ux500: delete custom pin control system ARM: ux500: switch over to Nomadik pinctrl driver ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt108
-rw-r--r--MAINTAINERS23
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts38
-rw-r--r--arch/arm/boot/dts/spear300.dtsi5
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts61
-rw-r--r--arch/arm/boot/dts/spear310.dtsi5
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts61
-rw-r--r--arch/arm/boot/dts/spear320.dtsi7
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts44
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts224
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts220
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts243
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts230
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts230
-rw-r--r--arch/arm/configs/nhk8815_defconfig1
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rw-r--r--arch/arm/mach-imx/imx51-dt.c3
-rw-r--r--arch/arm/mach-imx/imx53-dt.c3
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c7
-rw-r--r--arch/arm/mach-imx/mm-imx1.c2
-rw-r--r--arch/arm/mach-imx/mm-imx21.c2
-rw-r--r--arch/arm/mach-imx/mm-imx25.c2
-rw-r--r--arch/arm/mach-imx/mm-imx27.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c2
-rw-r--r--arch/arm/mach-imx/mm-imx5.c2
-rw-r--r--arch/arm/mach-mxs/Kconfig2
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h2
-rw-r--r--arch/arm/mach-mxs/mach-apx4devkit.c2
-rw-r--r--arch/arm/mach-mxs/mach-m28evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-stmp378x_devb.c2
-rw-r--r--arch/arm/mach-mxs/mach-tx28.c2
-rw-r--r--arch/arm/mach-mxs/mm.c11
-rw-r--r--arch/arm/mach-nomadik/Kconfig1
-rw-r--r--arch/arm/mach-spear3xx/Kconfig3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h128
-rw-r--r--arch/arm/mach-spear3xx/spear300.c389
-rw-r--r--arch/arm/mach-spear3xx/spear310.c161
-rw-r--r--arch/arm/mach-spear3xx/spear320.c403
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c425
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c31
-rw-r--r--arch/arm/mach-tegra/board-harmony-pinmux.c266
-rw-r--r--arch/arm/mach-tegra/board-paz00-pinmux.c263
-rw-r--r--arch/arm/mach-tegra/board-pinmux.c105
-rw-r--r--arch/arm/mach-tegra/board-pinmux.h40
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c346
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c21
-rw-r--r--arch/arm/mach-tegra/board-trimslice-pinmux.c264
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c15
-rw-r--r--arch/arm/mach-tegra/devices.c5
-rw-r--r--arch/arm/mach-tegra/include/mach/gpio-tegra.h9
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra20.h184
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra30.h320
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h302
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra20-tables.c244
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra30-tables.c376
-rw-r--r--arch/arm/mach-tegra/pinmux.c987
-rw-r--r--arch/arm/mach-tegra/usb_phy.c1
-rw-r--r--arch/arm/mach-ux500/Kconfig3
-rw-r--r--arch/arm/mach-ux500/Makefile3
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.c267
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.h14
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c733
-rw-r--r--arch/arm/mach-ux500/board-mop500.c99
-rw-r--r--arch/arm/mach-ux500/board-mop500.h10
-rw-r--r--arch/arm/mach-ux500/clock.c8
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c1
-rw-r--r--arch/arm/mach-ux500/cpu.c12
-rw-r--r--arch/arm/mach-ux500/devices-common.h12
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h10
-rw-r--r--arch/arm/mach-ux500/include/mach/msp.h29
-rw-r--r--arch/arm/mach-ux500/pins-db8500.h72
-rw-r--r--arch/arm/plat-nomadik/include/plat/gpio-nomadik.h8
-rw-r--r--arch/arm/plat-nomadik/include/plat/pincfg.h32
-rw-r--r--arch/arm/plat-spear/Kconfig1
-rw-r--r--arch/arm/plat-spear/Makefile2
-rw-r--r--arch/arm/plat-spear/include/plat/padmux.h92
-rw-r--r--arch/arm/plat-spear/padmux.c164
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-tegra.c39
-rw-r--r--drivers/i2c/busses/i2c-imx.c8
-rw-r--r--drivers/i2c/busses/i2c-mxs.c6
-rw-r--r--drivers/mmc/host/mxs-mmc.c8
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c9
-rw-r--r--drivers/mmc/host/sdhci-tegra.c24
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-nand.c9
-rw-r--r--drivers/net/can/flexcan.c6
-rw-r--r--drivers/net/ethernet/freescale/fec.c9
-rw-r--r--drivers/pinctrl/Kconfig12
-rw-r--r--drivers/pinctrl/Makefile4
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c857
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c (renamed from drivers/gpio/gpio-nomadik.c)857
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h77
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c236
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h23
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c40
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c40
-rw-r--r--drivers/pinctrl/spear/Kconfig34
-rw-r--r--drivers/pinctrl/spear/Makefile7
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c354
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.h142
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c708
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear310.c431
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c3468
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.c588
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.h92
-rw-r--r--drivers/spi/spi-imx.c8
-rw-r--r--drivers/tty/serial/amba-pl011.c8
-rw-r--r--drivers/tty/serial/imx.c8
-rw-r--r--drivers/tty/serial/mxs-auart.c8
-rw-r--r--drivers/usb/host/ehci-tegra.c13
-rw-r--r--drivers/video/mxsfb.c9
-rw-r--r--include/linux/pinctrl/pinctrl-state.h13
-rw-r--r--include/linux/platform_data/tegra_usb.h1
-rw-r--r--sound/soc/mxs/mxs-saif.c8
118 files changed, 10999 insertions, 5588 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644
index 00000000000..3664d37e679
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,108 @@
1ST Microelectronics, SPEAr pinmux controller
2
3Required properties:
4- compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7- reg : Address range of the pinctrl registers
8- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
9 - Its values for SPEAr300:
10 - NAND_MODE : <0>
11 - NOR_MODE : <1>
12 - PHOTO_FRAME_MODE : <2>
13 - LEND_IP_PHONE_MODE : <3>
14 - HEND_IP_PHONE_MODE : <4>
15 - LEND_WIFI_PHONE_MODE : <5>
16 - HEND_WIFI_PHONE_MODE : <6>
17 - ATA_PABX_WI2S_MODE : <7>
18 - ATA_PABX_I2S_MODE : <8>
19 - CAML_LCDW_MODE : <9>
20 - CAMU_LCD_MODE : <10>
21 - CAMU_WLCD_MODE : <11>
22 - CAML_LCD_MODE : <12>
23 - Its values for SPEAr320:
24 - AUTO_NET_SMII_MODE : <0>
25 - AUTO_NET_MII_MODE : <1>
26 - AUTO_EXP_MODE : <2>
27 - SMALL_PRINTERS_MODE : <3>
28 - EXTENDED_MODE : <4>
29
30Please refer to pinctrl-bindings.txt in this directory for details of the common
31pinctrl bindings used by client devices.
32
33SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
34of these subnodes represents muxing for a pin, a group, or a list of pins or
35groups.
36
37The name of each subnode is not important; all subnodes should be enumerated
38and processed purely based on their content.
39
40Required subnode-properties:
41- st,pins : An array of strings. Each string contains the name of a pin or
42 group.
43- st,function: A string containing the name of the function to mux to the pin or
44 group. See the SPEAr's TRM to determine which are valid for each pin or group.
45
46 Valid values for group and function names can be found from looking at the
47 group and function arrays in driver files:
48 drivers/pinctrl/spear/pinctrl-spear3*0.c
49
50Valid values for group names are:
51For All SPEAr3xx machines:
52 "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
53 "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
54 "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
55 "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
56
57For SPEAr300 machines:
58 "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
59 "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
60 "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
61 "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
62
63For SPEAr310 machines:
64 "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
65 "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
66
67For SPEAr320 machines:
68 "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
69 "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
70 "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
71 "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
72 "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
73 "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
74 "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
75 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
76 "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
77 "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
78 "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
79 "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
80 "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
81 "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
82 "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
83 "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
84 "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
85 "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
86 "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
87 "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
88 "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
89 "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
90 "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
91
92Valid values for function names are:
93For All SPEAr3xx machines:
94 "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
95 "uart0", "timer_0_1", "timer_2_3"
96
97For SPEAr300 machines:
98 "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
99
100For SPEAr310 machines:
101 "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
102 "rs485_1", "tdm"
103
104For SPEAr320 machines:
105 "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
106 "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
107 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
108 "mii0_1", "i2c1", "i2c2"
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a4bf92495b..17360c7ac27 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5240,6 +5240,14 @@ M: Linus Walleij <linus.walleij@linaro.org>
5240S: Maintained 5240S: Maintained
5241F: drivers/pinctrl/ 5241F: drivers/pinctrl/
5242 5242
5243PIN CONTROLLER - ST SPEAR
5244M: Viresh Kumar <viresh.kumar@st.com>
5245L: spear-devel@list.st.com
5246L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
5247W: http://www.st.com/spear
5248S: Maintained
5249F: driver/pinctrl/spear/
5250
5243PKTCDVD DRIVER 5251PKTCDVD DRIVER
5244M: Peter Osterlund <petero2@telia.com> 5252M: Peter Osterlund <petero2@telia.com>
5245S: Maintained 5253S: Maintained
@@ -6344,21 +6352,6 @@ F: arch/arm/mach-spear*/clock.c
6344F: arch/arm/plat-spear/clock.c 6352F: arch/arm/plat-spear/clock.c
6345F: arch/arm/plat-spear/include/plat/clock.h 6353F: arch/arm/plat-spear/include/plat/clock.h
6346 6354
6347SPEAR PAD MULTIPLEXING SUPPORT
6348M: Viresh Kumar <viresh.kumar@st.com>
6349L: spear-devel@list.st.com
6350L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6351W: http://www.st.com/spear
6352S: Maintained
6353F: arch/arm/plat-spear/include/plat/padmux.h
6354F: arch/arm/plat-spear/padmux.c
6355F: arch/arm/mach-spear*/spear*xx.c
6356F: arch/arm/mach-spear*/include/mach/generic.h
6357F: arch/arm/mach-spear3xx/spear3*0.c
6358F: arch/arm/mach-spear3xx/spear3*0_evb.c
6359F: arch/arm/mach-spear6xx/spear600.c
6360F: arch/arm/mach-spear6xx/spear600_evb.c
6361
6362SPI SUBSYSTEM 6355SPI SUBSYSTEM
6363M: Grant Likely <grant.likely@secretlab.ca> 6356M: Grant Likely <grant.likely@secretlab.ca>
6364L: spi-devel-general@lists.sourceforge.net 6357L: spi-devel-general@lists.sourceforge.net
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 82936f63cf1..58e2f7865f5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -403,6 +403,8 @@ config ARCH_PRIMA2
403 select CLKDEV_LOOKUP 403 select CLKDEV_LOOKUP
404 select GENERIC_IRQ_CHIP 404 select GENERIC_IRQ_CHIP
405 select MIGHT_HAVE_CACHE_L2X0 405 select MIGHT_HAVE_CACHE_L2X0
406 select PINCTRL
407 select PINCTRL_SIRF
406 select USE_OF 408 select USE_OF
407 select ZONE_DMA 409 select ZONE_DMA
408 help 410 help
@@ -465,6 +467,7 @@ config ARCH_MXS
465 select CLKDEV_LOOKUP 467 select CLKDEV_LOOKUP
466 select CLKSRC_MMIO 468 select CLKSRC_MMIO
467 select HAVE_CLK_PREPARE 469 select HAVE_CLK_PREPARE
470 select PINCTRL
468 help 471 help
469 Support for Freescale MXS-based family of processors 472 Support for Freescale MXS-based family of processors
470 473
@@ -919,6 +922,7 @@ config ARCH_NOMADIK
919 select CPU_ARM926T 922 select CPU_ARM926T
920 select CLKDEV_LOOKUP 923 select CLKDEV_LOOKUP
921 select GENERIC_CLOCKEVENTS 924 select GENERIC_CLOCKEVENTS
925 select PINCTRL
922 select MIGHT_HAVE_CACHE_L2X0 926 select MIGHT_HAVE_CACHE_L2X0
923 select ARCH_REQUIRE_GPIOLIB 927 select ARCH_REQUIRE_GPIOLIB
924 help 928 help
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 6a79d69775b..910e264b87c 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -25,6 +25,44 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
28 clcd@60000000 { 66 clcd@60000000 {
29 status = "okay"; 67 status = "okay";
30 }; 68 };
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index f9fcbf4f477..01c5e358fdb 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -21,6 +21,11 @@
21 ranges = <0x60000000 0x60000000 0x50000000 21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
24 clcd@60000000 { 29 clcd@60000000 {
25 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,clcd-pl110", "arm,primecell";
26 reg = <0x60000000 0x1000>; 31 reg = <0x60000000 0x1000>;
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index c86af33f700..6d95317100a 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -25,6 +25,67 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
28 dma@fc400000 { 89 dma@fc400000 {
29 status = "okay"; 90 status = "okay";
30 }; 91 };
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index dc7fa14da84..e47081c494d 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -22,6 +22,11 @@
22 0xb0000000 0xb0000000 0x10000000 22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>; 23 0xd0000000 0xd0000000 0x30000000>;
24 24
25 pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 };
29
25 fsmc: flash@44000000 { 30 fsmc: flash@44000000 {
26 compatible = "st,spear600-fsmc-nand"; 31 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>; 32 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index d43de712e86..0c6463b71a3 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -25,6 +25,67 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <3>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp";
80 st,function = "pwm0_1";
81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 };
87 };
88
28 clcd@90000000 { 89 clcd@90000000 {
29 status = "okay"; 90 status = "okay";
30 }; 91 };
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 9a0267a5a0b..5372ca399b1 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -18,9 +18,14 @@
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 compatible = "simple-bus"; 20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x70000000 21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 };
28
24 clcd@90000000 { 29 clcd@90000000 {
25 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,clcd-pl110", "arm,primecell";
26 reg = <0x90000000 0x1000>; 31 reg = <0x90000000 0x1000>;
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb755845..0a9f34a2c3a 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
10 reg = < 0x80000000 0x40000000 >; 10 reg = < 0x80000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
54 };
55 };
56
13 serial@70006000 { 57 serial@70006000 {
14 clock-frequency = < 408000000 >; 58 clock-frequency = < 408000000 >;
15 }; 59 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447dc020..1a0b1f18294 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,6 +10,230 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
32 "spia", "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc";
69 nvidia,function = "i2c2";
70 };
71 dta {
72 nvidia,pins = "dta", "dtd";
73 nvidia,function = "sdio2";
74 };
75 dtb {
76 nvidia,pins = "dtb", "dtc", "dte";
77 nvidia,function = "rsvd1";
78 };
79 dtf {
80 nvidia,pins = "dtf";
81 nvidia,function = "i2c3";
82 };
83 gmc {
84 nvidia,pins = "gmc";
85 nvidia,function = "uartd";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "pta";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uarta";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc", "spdi", "spdo", "uac";
126 nvidia,function = "rsvd2";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdb {
137 nvidia,pins = "sdb", "sdc", "sdd";
138 nvidia,function = "pwm";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spdif";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spif";
150 nvidia,function = "spi1";
151 };
152 spig {
153 nvidia,pins = "spig", "spih";
154 nvidia,function = "spi2_alt";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab", "uda";
158 nvidia,function = "ulpi";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 conf_ata {
169 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
170 "cdev1", "dap1", "dtb", "gma", "gmb",
171 "gmc", "gmd", "gme", "gpu7", "gpv",
172 "i2cp", "pta", "rm", "slxa", "slxk",
173 "spia", "spib";
174 nvidia,pull = <0>;
175 nvidia,tristate = <0>;
176 };
177 conf_cdev2 {
178 nvidia,pins = "cdev2", "csus", "spid", "spif";
179 nvidia,pull = <1>;
180 nvidia,tristate = <1>;
181 };
182 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>;
186 };
187 conf_crtp {
188 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
189 "dtc", "dte", "dtf", "gpu", "sdio1",
190 "slxc", "slxd", "spdi", "spdo", "spig",
191 "uac", "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_ddc {
196 nvidia,pins = "ddc", "dta", "dtd", "kbca",
197 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
198 "sdc";
199 nvidia,pull = <2>;
200 nvidia,tristate = <0>;
201 };
202 conf_hdint {
203 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
204 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
205 "lvp0", "owc", "sdb";
206 nvidia,tristate = <1>;
207 };
208 conf_irrx {
209 nvidia,pins = "irrx", "irtx", "sdd", "spic",
210 "spie", "spih", "uaa", "uab", "uad",
211 "uca", "ucb";
212 nvidia,pull = <2>;
213 nvidia,tristate = <1>;
214 };
215 conf_lc {
216 nvidia,pins = "lc", "ls";
217 nvidia,pull = <2>;
218 };
219 conf_ld0 {
220 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
221 "ld5", "ld6", "ld7", "ld8", "ld9",
222 "ld10", "ld11", "ld12", "ld13", "ld14",
223 "ld15", "ld16", "ld17", "ldi", "lhp0",
224 "lhp1", "lhp2", "lhs", "lm0", "lpp",
225 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
226 "lvs", "pmc";
227 nvidia,tristate = <0>;
228 };
229 conf_ld17_0 {
230 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
231 "ld23_22";
232 nvidia,pull = <1>;
233 };
234 };
235 };
236
13 pmc@7000f400 { 237 pmc@7000f400 {
14 nvidia,invert-interrupt; 238 nvidia,invert-interrupt;
15 }; 239 };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb469d..10943fb2561 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -10,6 +10,226 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atc", "atd", "ate",
20 "dap2", "gmb", "gmc", "gmd", "spia",
21 "spib", "spic", "spid", "spie";
22 nvidia,function = "gmi";
23 };
24 atb {
25 nvidia,pins = "atb", "gma", "gme";
26 nvidia,function = "sdio4";
27 };
28 cdev1 {
29 nvidia,pins = "cdev1";
30 nvidia,function = "plla_out";
31 };
32 cdev2 {
33 nvidia,pins = "cdev2";
34 nvidia,function = "pllp_out4";
35 };
36 crtp {
37 nvidia,pins = "crtp";
38 nvidia,function = "crt";
39 };
40 csus {
41 nvidia,pins = "csus";
42 nvidia,function = "pllc_out1";
43 };
44 dap1 {
45 nvidia,pins = "dap1";
46 nvidia,function = "dap1";
47 };
48 dap3 {
49 nvidia,pins = "dap3";
50 nvidia,function = "dap3";
51 };
52 dap4 {
53 nvidia,pins = "dap4";
54 nvidia,function = "dap4";
55 };
56 ddc {
57 nvidia,pins = "ddc";
58 nvidia,function = "i2c2";
59 };
60 dta {
61 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
62 nvidia,function = "rsvd1";
63 };
64 dtf {
65 nvidia,pins = "dtf";
66 nvidia,function = "i2c3";
67 };
68 gpu {
69 nvidia,pins = "gpu", "sdb", "sdd";
70 nvidia,function = "pwm";
71 };
72 gpu7 {
73 nvidia,pins = "gpu7";
74 nvidia,function = "rtck";
75 };
76 gpv {
77 nvidia,pins = "gpv", "slxa", "slxk";
78 nvidia,function = "pcie";
79 };
80 hdint {
81 nvidia,pins = "hdint", "pta";
82 nvidia,function = "hdmi";
83 };
84 i2cp {
85 nvidia,pins = "i2cp";
86 nvidia,function = "i2cp";
87 };
88 irrx {
89 nvidia,pins = "irrx", "irtx";
90 nvidia,function = "uarta";
91 };
92 kbca {
93 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
94 nvidia,function = "kbc";
95 };
96 kbcb {
97 nvidia,pins = "kbcb", "kbcd";
98 nvidia,function = "sdio2";
99 };
100 lcsn {
101 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
102 "ld3", "ld4", "ld5", "ld6", "ld7",
103 "ld8", "ld9", "ld10", "ld11", "ld12",
104 "ld13", "ld14", "ld15", "ld16", "ld17",
105 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
106 "lhs", "lm0", "lm1", "lpp", "lpw0",
107 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
108 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
109 "lvs";
110 nvidia,function = "displaya";
111 };
112 owc {
113 nvidia,pins = "owc";
114 nvidia,function = "owr";
115 };
116 pmc {
117 nvidia,pins = "pmc";
118 nvidia,function = "pwr_on";
119 };
120 rm {
121 nvidia,pins = "rm";
122 nvidia,function = "i2c1";
123 };
124 sdc {
125 nvidia,pins = "sdc";
126 nvidia,function = "twc";
127 };
128 sdio1 {
129 nvidia,pins = "sdio1";
130 nvidia,function = "sdio1";
131 };
132 slxc {
133 nvidia,pins = "slxc", "slxd";
134 nvidia,function = "spi4";
135 };
136 spdi {
137 nvidia,pins = "spdi", "spdo";
138 nvidia,function = "rsvd2";
139 };
140 spif {
141 nvidia,pins = "spif", "uac";
142 nvidia,function = "rsvd4";
143 };
144 spig {
145 nvidia,pins = "spig", "spih";
146 nvidia,function = "spi2_alt";
147 };
148 uaa {
149 nvidia,pins = "uaa", "uab", "uda";
150 nvidia,function = "ulpi";
151 };
152 uad {
153 nvidia,pins = "uad";
154 nvidia,function = "spdif";
155 };
156 uca {
157 nvidia,pins = "uca", "ucb";
158 nvidia,function = "uartc";
159 };
160 conf_ata {
161 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
162 "cdev1", "dap1", "dap2", "dtf", "gma",
163 "gmb", "gmc", "gmd", "gme", "gpu",
164 "gpu7", "gpv", "i2cp", "pta", "rm",
165 "sdio1", "slxk", "spdo", "uac", "uda";
166 nvidia,pull = <0>;
167 nvidia,tristate = <0>;
168 };
169 conf_cdev2 {
170 nvidia,pins = "cdev2";
171 nvidia,pull = <1>;
172 nvidia,tristate = <0>;
173 };
174 conf_ck32 {
175 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
176 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
177 nvidia,pull = <0>;
178 };
179 conf_crtp {
180 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
181 "dtc", "dte", "slxa", "slxc", "slxd",
182 "spdi";
183 nvidia,pull = <0>;
184 nvidia,tristate = <1>;
185 };
186 conf_csus {
187 nvidia,pins = "csus", "spia", "spib", "spid",
188 "spif";
189 nvidia,pull = <1>;
190 nvidia,tristate = <1>;
191 };
192 conf_ddc {
193 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
194 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
195 "spic", "spig", "uaa", "uab";
196 nvidia,pull = <2>;
197 nvidia,tristate = <0>;
198 };
199 conf_dta {
200 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
201 "spie", "spih", "uad", "uca", "ucb";
202 nvidia,pull = <2>;
203 nvidia,tristate = <1>;
204 };
205 conf_hdint {
206 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
207 "ld3", "ld4", "ld5", "ld6", "ld7",
208 "ld8", "ld9", "ld10", "ld11", "ld12",
209 "ld13", "ld14", "ld15", "ld16", "ld17",
210 "ldc", "ldi", "lhs", "lsc0", "lspi",
211 "lvs", "pmc";
212 nvidia,tristate = <0>;
213 };
214 conf_lc {
215 nvidia,pins = "lc", "ls";
216 nvidia,pull = <2>;
217 };
218 conf_lcsn {
219 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
220 "lm0", "lm1", "lpp", "lpw0", "lpw1",
221 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
222 "lvp0", "lvp1", "sdb";
223 nvidia,tristate = <1>;
224 };
225 conf_ld17_0 {
226 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
227 "ld23_22";
228 nvidia,pull = <1>;
229 };
230 };
231 };
232
13 i2c@7000c000 { 233 i2c@7000c000 {
14 clock-frequency = <400000>; 234 clock-frequency = <400000>;
15 235
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a171c..ec33116f5df 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -11,6 +11,249 @@
11 reg = < 0x00000000 0x40000000 >; 11 reg = < 0x00000000 0x40000000 >;
12 }; 12 };
13 13
14 pinmux@70000000 {
15 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>;
17
18 state_default: pinmux {
19 ata {
20 nvidia,pins = "ata";
21 nvidia,function = "ide";
22 };
23 atb {
24 nvidia,pins = "atb", "gma", "gme";
25 nvidia,function = "sdio4";
26 };
27 atc {
28 nvidia,pins = "atc";
29 nvidia,function = "nand";
30 };
31 atd {
32 nvidia,pins = "atd", "ate", "gmb", "spia",
33 "spib", "spic";
34 nvidia,function = "gmi";
35 };
36 cdev1 {
37 nvidia,pins = "cdev1";
38 nvidia,function = "plla_out";
39 };
40 cdev2 {
41 nvidia,pins = "cdev2";
42 nvidia,function = "pllp_out4";
43 };
44 crtp {
45 nvidia,pins = "crtp", "lm1";
46 nvidia,function = "crt";
47 };
48 csus {
49 nvidia,pins = "csus";
50 nvidia,function = "vi_sensor_clk";
51 };
52 dap1 {
53 nvidia,pins = "dap1";
54 nvidia,function = "dap1";
55 };
56 dap2 {
57 nvidia,pins = "dap2";
58 nvidia,function = "dap2";
59 };
60 dap3 {
61 nvidia,pins = "dap3";
62 nvidia,function = "dap3";
63 };
64 dap4 {
65 nvidia,pins = "dap4";
66 nvidia,function = "dap4";
67 };
68 ddc {
69 nvidia,pins = "ddc", "owc", "spdi", "spdo",
70 "uac";
71 nvidia,function = "rsvd2";
72 };
73 dta {
74 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
75 nvidia,function = "vi";
76 };
77 dtf {
78 nvidia,pins = "dtf";
79 nvidia,function = "i2c3";
80 };
81 gmc {
82 nvidia,pins = "gmc";
83 nvidia,function = "uartd";
84 };
85 gmd {
86 nvidia,pins = "gmd";
87 nvidia,function = "sflash";
88 };
89 gpu {
90 nvidia,pins = "gpu";
91 nvidia,function = "pwm";
92 };
93 gpu7 {
94 nvidia,pins = "gpu7";
95 nvidia,function = "rtck";
96 };
97 gpv {
98 nvidia,pins = "gpv", "slxa", "slxk";
99 nvidia,function = "pcie";
100 };
101 hdint {
102 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
103 "lsck", "lsda", "pta";
104 nvidia,function = "hdmi";
105 };
106 i2cp {
107 nvidia,pins = "i2cp";
108 nvidia,function = "i2cp";
109 };
110 irrx {
111 nvidia,pins = "irrx", "irtx";
112 nvidia,function = "uartb";
113 };
114 kbca {
115 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
116 "kbce", "kbcf";
117 nvidia,function = "kbc";
118 };
119 lcsn {
120 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
121 "lsdi", "lvp0";
122 nvidia,function = "rsvd4";
123 };
124 ld0 {
125 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
126 "ld5", "ld6", "ld7", "ld8", "ld9",
127 "ld10", "ld11", "ld12", "ld13", "ld14",
128 "ld15", "ld16", "ld17", "ldi", "lhp0",
129 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
130 "lspi", "lvp1", "lvs";
131 nvidia,function = "displaya";
132 };
133 pmc {
134 nvidia,pins = "pmc";
135 nvidia,function = "pwr_on";
136 };
137 rm {
138 nvidia,pins = "rm";
139 nvidia,function = "i2c1";
140 };
141 sdb {
142 nvidia,pins = "sdb", "sdc", "sdd";
143 nvidia,function = "sdio3";
144 };
145 sdio1 {
146 nvidia,pins = "sdio1";
147 nvidia,function = "sdio1";
148 };
149 slxc {
150 nvidia,pins = "slxc", "slxd";
151 nvidia,function = "spdif";
152 };
153 spid {
154 nvidia,pins = "spid", "spie", "spif";
155 nvidia,function = "spi1";
156 };
157 spig {
158 nvidia,pins = "spig", "spih";
159 nvidia,function = "spi2_alt";
160 };
161 uaa {
162 nvidia,pins = "uaa", "uab", "uda";
163 nvidia,function = "ulpi";
164 };
165 uad {
166 nvidia,pins = "uad";
167 nvidia,function = "irda";
168 };
169 uca {
170 nvidia,pins = "uca", "ucb";
171 nvidia,function = "uartc";
172 };
173 conf_ata {
174 nvidia,pins = "ata", "atb", "atc", "atd",
175 "cdev1", "cdev2", "dap1", "dap2",
176 "dap4", "dtf", "gma", "gmc", "gmd",
177 "gme", "gpu", "gpu7", "i2cp", "irrx",
178 "irtx", "pta", "rm", "sdc", "sdd",
179 "slxd", "slxk", "spdi", "spdo", "uac",
180 "uad", "uca", "ucb", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <0>;
183 };
184 conf_ate {
185 nvidia,pins = "ate", "csus", "dap3", "ddc",
186 "gpv", "owc", "slxc", "spib", "spid",
187 "spie";
188 nvidia,pull = <0>;
189 nvidia,tristate = <1>;
190 };
191 conf_ck32 {
192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
194 nvidia,pull = <0>;
195 };
196 conf_crtp {
197 nvidia,pins = "crtp", "gmb", "slxa", "spia",
198 "spig", "spih";
199 nvidia,pull = <2>;
200 nvidia,tristate = <1>;
201 };
202 conf_dta {
203 nvidia,pins = "dta", "dtb", "dtc", "dtd";
204 nvidia,pull = <1>;
205 nvidia,tristate = <0>;
206 };
207 conf_dte {
208 nvidia,pins = "dte", "spif";
209 nvidia,pull = <1>;
210 nvidia,tristate = <1>;
211 };
212 conf_hdint {
213 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
214 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
215 "lvp0";
216 nvidia,tristate = <1>;
217 };
218 conf_kbca {
219 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
220 "kbce", "kbcf", "sdio1", "spic", "uaa",
221 "uab";
222 nvidia,pull = <2>;
223 nvidia,tristate = <0>;
224 };
225 conf_lc {
226 nvidia,pins = "lc", "ls";
227 nvidia,pull = <2>;
228 };
229 conf_ld0 {
230 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
231 "ld5", "ld6", "ld7", "ld8", "ld9",
232 "ld10", "ld11", "ld12", "ld13", "ld14",
233 "ld15", "ld16", "ld17", "ldi", "lhp0",
234 "lhp1", "lhp2", "lhs", "lm0", "lpp",
235 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
236 "lvs", "pmc", "sdb";
237 nvidia,tristate = <0>;
238 };
239 conf_ld17_0 {
240 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
241 "ld23_22";
242 nvidia,pull = <1>;
243 };
244 drive_sdio1 {
245 nvidia,pins = "drive_sdio1";
246 nvidia,high-speed-mode = <0>;
247 nvidia,schmitt = <0>;
248 nvidia,low-power-mode = <3>;
249 nvidia,pull-down-strength = <31>;
250 nvidia,pull-up-strength = <31>;
251 nvidia,slew-rate-rising = <3>;
252 nvidia,slew-rate-falling = <3>;
253 };
254 };
255 };
256
14 i2c@7000c000 { 257 i2c@7000c000 {
15 clock-frequency = <400000>; 258 clock-frequency = <400000>;
16 259
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 252476867b5..98efd5b0d7f 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -10,6 +10,236 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc", "gmb";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gme", "pta";
32 nvidia,function = "gmi";
33 };
34 cdev1 {
35 nvidia,pins = "cdev1";
36 nvidia,function = "plla_out";
37 };
38 cdev2 {
39 nvidia,pins = "cdev2";
40 nvidia,function = "pllp_out4";
41 };
42 crtp {
43 nvidia,pins = "crtp";
44 nvidia,function = "crt";
45 };
46 csus {
47 nvidia,pins = "csus";
48 nvidia,function = "vi_sensor_clk";
49 };
50 dap1 {
51 nvidia,pins = "dap1";
52 nvidia,function = "dap1";
53 };
54 dap2 {
55 nvidia,pins = "dap2";
56 nvidia,function = "dap2";
57 };
58 dap3 {
59 nvidia,pins = "dap3";
60 nvidia,function = "dap3";
61 };
62 dap4 {
63 nvidia,pins = "dap4";
64 nvidia,function = "dap4";
65 };
66 ddc {
67 nvidia,pins = "ddc";
68 nvidia,function = "i2c2";
69 };
70 dta {
71 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
72 nvidia,function = "vi";
73 };
74 dtf {
75 nvidia,pins = "dtf";
76 nvidia,function = "i2c3";
77 };
78 gmc {
79 nvidia,pins = "gmc", "gmd";
80 nvidia,function = "sflash";
81 };
82 gpu {
83 nvidia,pins = "gpu";
84 nvidia,function = "uarta";
85 };
86 gpu7 {
87 nvidia,pins = "gpu7";
88 nvidia,function = "rtck";
89 };
90 gpv {
91 nvidia,pins = "gpv", "slxa", "slxk";
92 nvidia,function = "pcie";
93 };
94 hdint {
95 nvidia,pins = "hdint";
96 nvidia,function = "hdmi";
97 };
98 i2cp {
99 nvidia,pins = "i2cp";
100 nvidia,function = "i2cp";
101 };
102 irrx {
103 nvidia,pins = "irrx", "irtx";
104 nvidia,function = "uartb";
105 };
106 kbca {
107 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
108 "kbce", "kbcf";
109 nvidia,function = "kbc";
110 };
111 lcsn {
112 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
113 "ld3", "ld4", "ld5", "ld6", "ld7",
114 "ld8", "ld9", "ld10", "ld11", "ld12",
115 "ld13", "ld14", "ld15", "ld16", "ld17",
116 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
117 "lhs", "lm0", "lm1", "lpp", "lpw0",
118 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
119 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "rsvd2";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd";
137 nvidia,function = "pwm";
138 };
139 sdio1 {
140 nvidia,pins = "sdio1";
141 nvidia,function = "sdio1";
142 };
143 slxc {
144 nvidia,pins = "slxc", "slxd";
145 nvidia,function = "sdio3";
146 };
147 spdi {
148 nvidia,pins = "spdi", "spdo";
149 nvidia,function = "spdif";
150 };
151 spia {
152 nvidia,pins = "spia", "spib", "spic";
153 nvidia,function = "spi2";
154 };
155 spid {
156 nvidia,pins = "spid", "spie", "spif";
157 nvidia,function = "spi1";
158 };
159 spig {
160 nvidia,pins = "spig", "spih";
161 nvidia,function = "spi2_alt";
162 };
163 uaa {
164 nvidia,pins = "uaa", "uab", "uda";
165 nvidia,function = "ulpi";
166 };
167 uad {
168 nvidia,pins = "uad";
169 nvidia,function = "irda";
170 };
171 uca {
172 nvidia,pins = "uca", "ucb";
173 nvidia,function = "uartc";
174 };
175 conf_ata {
176 nvidia,pins = "ata", "atc", "atd", "ate",
177 "crtp", "dap2", "dap3", "dap4", "dta",
178 "dtb", "dtc", "dtd", "dte", "gmb",
179 "gme", "i2cp", "pta", "slxc", "slxd",
180 "spdi", "spdo", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <1>;
183 };
184 conf_atb {
185 nvidia,pins = "atb", "cdev1", "dap1", "gma",
186 "gmc", "gmd", "gpu", "gpu7", "gpv",
187 "sdio1", "slxa", "slxk", "uac";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_cdev2 {
192 nvidia,pins = "cdev2", "csus", "spia", "spib",
193 "spid", "spif";
194 nvidia,pull = <1>;
195 nvidia,tristate = <1>;
196 };
197 conf_ck32 {
198 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
199 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
200 nvidia,pull = <0>;
201 };
202 conf_ddc {
203 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "pmc";
211 nvidia,tristate = <1>;
212 };
213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
215 "kbcc", "kbcd", "kbce", "kbcf", "owc",
216 "spic", "spie", "spig", "spih", "uaa",
217 "uab", "uad", "uca", "ucb";
218 nvidia,pull = <2>;
219 nvidia,tristate = <1>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
232 "lvs", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
14 clock-frequency = <400000>; 244 clock-frequency = <400000>;
15 }; 245 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff8728e9..71eb2e50a66 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -10,6 +10,236 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
14 clock-frequency = <400000>; 244 clock-frequency = <400000>;
15 245
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 37207d1bf44..bf123c5384d 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -97,6 +97,7 @@ CONFIG_I2C=y
97CONFIG_I2C_CHARDEV=y 97CONFIG_I2C_CHARDEV=y
98CONFIG_I2C_GPIO=y 98CONFIG_I2C_GPIO=y
99CONFIG_DEBUG_GPIO=y 99CONFIG_DEBUG_GPIO=y
100CONFIG_PINCTRL_NOMADIK=y
100# CONFIG_HWMON is not set 101# CONFIG_HWMON is not set
101# CONFIG_VGA_CONSOLE is not set 102# CONFIG_VGA_CONSOLE is not set
102CONFIG_RTC_CLASS=y 103CONFIG_RTC_CLASS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f72d399ff3d..c8f83e9e563 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -844,6 +844,8 @@ config SOC_IMX6Q
844 select HAVE_IMX_MMDC 844 select HAVE_IMX_MMDC
845 select HAVE_IMX_SRC 845 select HAVE_IMX_SRC
846 select HAVE_SMP 846 select HAVE_SMP
847 select PINCTRL
848 select PINCTRL_IMX6Q
847 select USE_OF 849 select USE_OF
848 850
849 help 851 help
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573964f..5f577fbda2c 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -14,6 +14,7 @@
14#include <linux/irqdomain.h> 14#include <linux/irqdomain.h>
15#include <linux/of_irq.h> 15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/pinctrl/machine.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
18#include <asm/mach/time.h> 19#include <asm/mach/time.h>
19#include <mach/common.h> 20#include <mach/common.h>
@@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
81 82
82 of_irq_init(imx51_irq_match); 83 of_irq_init(imx51_irq_match);
83 84
85 pinctrl_provide_dummies();
86
84 node = of_find_matching_node(NULL, imx51_iomuxc_of_match); 87 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
85 if (node) { 88 if (node) {
86 of_id = of_match_node(imx51_iomuxc_of_match, node); 89 of_id = of_match_node(imx51_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 4172279b390..574eca4b89a 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,6 +15,7 @@
15#include <linux/irqdomain.h> 15#include <linux/irqdomain.h>
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/pinctrl/machine.h>
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach/time.h> 20#include <asm/mach/time.h>
20#include <mach/common.h> 21#include <mach/common.h>
@@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
88 89
89 of_irq_init(imx53_irq_match); 90 of_irq_init(imx53_irq_match);
90 91
92 pinctrl_provide_dummies();
93
91 node = of_find_matching_node(NULL, imx53_iomuxc_of_match); 94 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
92 if (node) { 95 if (node) {
93 of_id = of_match_node(imx53_iomuxc_of_match, node); 96 of_id = of_match_node(imx53_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index da6c1d9af76..3df360a52c1 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,7 @@
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/of_irq.h> 20#include <linux/of_irq.h>
21#include <linux/of_platform.h> 21#include <linux/of_platform.h>
22#include <linux/pinctrl/machine.h>
22#include <linux/phy.h> 23#include <linux/phy.h>
23#include <linux/micrel_phy.h> 24#include <linux/micrel_phy.h>
24#include <asm/smp_twd.h> 25#include <asm/smp_twd.h>
@@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
77 78
78static void __init imx6q_init_machine(void) 79static void __init imx6q_init_machine(void)
79{ 80{
81 /*
82 * This should be removed when all imx6q boards have pinctrl
83 * states for devices defined in device tree.
84 */
85 pinctrl_provide_dummies();
86
80 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 87 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
81 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 88 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
82 ksz9021rn_phy_fixup); 89 ksz9021rn_phy_fixup);
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 2bded591d5c..fcafd3dafb8 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -18,6 +18,7 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/pinctrl/machine.h>
21 22
22#include <asm/mach/map.h> 23#include <asm/mach/map.h>
23 24
@@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
58 MX1_GPIO_INT_PORTC, 0); 59 MX1_GPIO_INT_PORTC, 0);
59 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256, 60 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
60 MX1_GPIO_INT_PORTD, 0); 61 MX1_GPIO_INT_PORTD, 0);
62 pinctrl_provide_dummies();
61} 63}
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 14d540edfd1..5f43905e529 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -20,6 +20,7 @@
20 20
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/pinctrl/machine.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <mach/common.h> 25#include <mach/common.h>
25#include <mach/devices-common.h> 26#include <mach/devices-common.h>
@@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
88 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 89 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
89 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 90 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
90 91
92 pinctrl_provide_dummies();
91 imx_add_imx_dma(); 93 imx_add_imx_dma();
92 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, 94 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
93 ARRAY_SIZE(imx21_audmux_res)); 95 ARRAY_SIZE(imx21_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 153b457acdc..6ff37140a4f 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -19,6 +19,7 @@
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/pinctrl/machine.h>
22 23
23#include <asm/pgtable.h> 24#include <asm/pgtable.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
95 mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); 96 mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
96 mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); 97 mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
97 98
99 pinctrl_provide_dummies();
98 /* i.mx25 has the i.mx35 type sdma */ 100 /* i.mx25 has the i.mx35 type sdma */
99 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); 101 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
100 /* i.mx25 has the i.mx31 type audmux */ 102 /* i.mx25 has the i.mx31 type audmux */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 8cb3f5e3e56..25662558e01 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -20,6 +20,7 @@
20 20
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/pinctrl/machine.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <mach/common.h> 25#include <mach/common.h>
25#include <mach/devices-common.h> 26#include <mach/devices-common.h>
@@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
89 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); 90 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
90 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); 91 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
91 92
93 pinctrl_provide_dummies();
92 imx_add_imx_dma(); 94 imx_add_imx_dma();
93 /* imx27 has the imx21 type audmux */ 95 /* imx27 has the imx21 type audmux */
94 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, 96 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 74127389e7a..9128d15b1eb 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -19,6 +19,7 @@
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/pinctrl/machine.h>
22 23
23#include <asm/pgtable.h> 24#include <asm/pgtable.h>
24#include <asm/system_misc.h> 25#include <asm/system_misc.h>
@@ -267,6 +268,7 @@ void __init imx35_soc_init(void)
267 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 268 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
268 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); 269 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
269 270
271 pinctrl_provide_dummies();
270 if (to_version == 1) { 272 if (to_version == 1) {
271 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", 273 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
272 strlen(imx35_sdma_pdata.fw_name)); 274 strlen(imx35_sdma_pdata.fw_name));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index e10f3914fcf..ba91e6b31cf 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -14,6 +14,7 @@
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/pinctrl/machine.h>
17 18
18#include <asm/system_misc.h> 19#include <asm/system_misc.h>
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
@@ -223,6 +224,7 @@ void __init imx53_soc_init(void)
223 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); 224 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
224 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); 225 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
225 226
227 pinctrl_provide_dummies();
226 /* i.mx53 has the i.mx35 type sdma */ 228 /* i.mx53 has the i.mx35 type sdma */
227 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); 229 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
228 230
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f9964a71..07d5383d68e 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -9,11 +9,13 @@ config SOC_IMX23
9 bool 9 bool
10 select CPU_ARM926T 10 select CPU_ARM926T
11 select HAVE_PWM 11 select HAVE_PWM
12 select PINCTRL_IMX23
12 13
13config SOC_IMX28 14config SOC_IMX28
14 bool 15 bool
15 select CPU_ARM926T 16 select CPU_ARM926T
16 select HAVE_PWM 17 select HAVE_PWM
18 select PINCTRL_IMX28
17 19
18comment "MXS platforms:" 20comment "MXS platforms:"
19 21
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index c50c3ea28a9..8d88399b73e 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -19,11 +19,13 @@ extern void mxs_timer_init(struct clk *, int);
19extern void mxs_restart(char, const char *); 19extern void mxs_restart(char, const char *);
20extern int mxs_saif_clkmux_select(unsigned int clkmux); 20extern int mxs_saif_clkmux_select(unsigned int clkmux);
21 21
22extern void mx23_soc_init(void);
22extern int mx23_register_gpios(void); 23extern int mx23_register_gpios(void);
23extern int mx23_clocks_init(void); 24extern int mx23_clocks_init(void);
24extern void mx23_map_io(void); 25extern void mx23_map_io(void);
25extern void mx23_init_irq(void); 26extern void mx23_init_irq(void);
26 27
28extern void mx28_soc_init(void);
27extern int mx28_register_gpios(void); 29extern int mx28_register_gpios(void);
28extern int mx28_clocks_init(void); 30extern int mx28_clocks_init(void);
29extern void mx28_map_io(void); 31extern void mx28_map_io(void);
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
index 48a7fab571a..5e90b9dcdef 100644
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
207 207
208static void __init apx4devkit_init(void) 208static void __init apx4devkit_init(void)
209{ 209{
210 mx28_soc_init();
211
210 mxs_iomux_setup_multiple_pads(apx4devkit_pads, 212 mxs_iomux_setup_multiple_pads(apx4devkit_pads,
211 ARRAY_SIZE(apx4devkit_pads)); 213 ARRAY_SIZE(apx4devkit_pads));
212 214
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 06d79963611..4c00c879b89 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
319 319
320static void __init m28evk_init(void) 320static void __init m28evk_init(void)
321{ 321{
322 mx28_soc_init();
323
322 mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); 324 mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
323 325
324 mx28_add_duart(); 326 mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 5ea1c57d260..e7272a41939 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
141{ 141{
142 int ret; 142 int ret;
143 143
144 mx23_soc_init();
145
144 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); 146 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
145 147
146 mx23_add_duart(); 148 mx23_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index e386c142f93..da4610ebe9e 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
413{ 413{
414 int ret; 414 int ret;
415 415
416 mx28_soc_init();
417
416 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); 418 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
417 419
418 mx28_add_duart(); 420 mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index a626c07b871..6548965e4a7 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
85{ 85{
86 int ret; 86 int ret;
87 87
88 mx23_soc_init();
89
88 mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, 90 mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
89 ARRAY_SIZE(stmp378x_dvb_pads)); 91 ARRAY_SIZE(stmp378x_dvb_pads));
90 92
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 2c0862e655e..8837029de1a 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
146 146
147static void __init tx28_stk5v3_init(void) 147static void __init tx28_stk5v3_init(void)
148{ 148{
149 mx28_soc_init();
150
149 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, 151 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
150 ARRAY_SIZE(tx28_stk5v3_pads)); 152 ARRAY_SIZE(tx28_stk5v3_pads));
151 153
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index 50af5ceebf6..67a384edcf5 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/pinctrl/machine.h>
16 17
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
18 19
@@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
61{ 62{
62 icoll_init_irq(); 63 icoll_init_irq();
63} 64}
65
66void __init mx23_soc_init(void)
67{
68 pinctrl_provide_dummies();
69}
70
71void __init mx28_soc_init(void)
72{
73 pinctrl_provide_dummies();
74}
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 3c5e0f522e9..365879b47c0 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -15,6 +15,7 @@ config NOMADIK_8815
15config I2C_BITBANG_8815NHK 15config I2C_BITBANG_8815NHK
16 tristate "Driver for bit-bang busses found on the 8815 NHK" 16 tristate "Driver for bit-bang busses found on the 8815 NHK"
17 depends on I2C && MACH_NOMADIK_8815NHK 17 depends on I2C && MACH_NOMADIK_8815NHK
18 depends on PINCTRL_NOMADIK
18 select I2C_ALGOBIT 19 select I2C_ALGOBIT
19 default y 20 default y
20 21
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index d9fe11cb6f1..8bd37291fa4 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -7,16 +7,19 @@ if ARCH_SPEAR3XX
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config MACH_SPEAR300 8config MACH_SPEAR300
9 bool "SPEAr300 Machine support with Device Tree" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
10 help 11 help
11 Supports ST SPEAr300 machine configured via the device-tree 12 Supports ST SPEAr300 machine configured via the device-tree
12 13
13config MACH_SPEAR310 14config MACH_SPEAR310
14 bool "SPEAr310 Machine support with Device Tree" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
15 help 17 help
16 Supports ST SPEAr310 machine configured via the device-tree 18 Supports ST SPEAr310 machine configured via the device-tree
17 19
18config MACH_SPEAR320 20config MACH_SPEAR320
19 bool "SPEAr320 Machine support with Device Tree" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
20 help 23 help
21 Supports ST SPEAr320 machine configured via the device-tree 24 Supports ST SPEAr320 machine configured via the device-tree
22endmenu 25endmenu
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index e4f4d721cda..bdb304551ca 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -20,7 +20,6 @@
20#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <plat/padmux.h>
24 23
25/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
26extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
@@ -34,147 +33,20 @@ void __init spear3xx_dt_init_irq(void);
34 33
35void spear_restart(char, const char *); 34void spear_restart(char, const char *);
36 35
37/* pad mux declarations */
38#define PMX_FIRDA_MASK (1 << 14)
39#define PMX_I2C_MASK (1 << 13)
40#define PMX_SSP_CS_MASK (1 << 12)
41#define PMX_SSP_MASK (1 << 11)
42#define PMX_MII_MASK (1 << 10)
43#define PMX_GPIO_PIN0_MASK (1 << 9)
44#define PMX_GPIO_PIN1_MASK (1 << 8)
45#define PMX_GPIO_PIN2_MASK (1 << 7)
46#define PMX_GPIO_PIN3_MASK (1 << 6)
47#define PMX_GPIO_PIN4_MASK (1 << 5)
48#define PMX_GPIO_PIN5_MASK (1 << 4)
49#define PMX_UART0_MODEM_MASK (1 << 3)
50#define PMX_UART0_MASK (1 << 2)
51#define PMX_TIMER_3_4_MASK (1 << 1)
52#define PMX_TIMER_1_2_MASK (1 << 0)
53
54/* pad mux devices */
55extern struct pmx_dev spear3xx_pmx_firda;
56extern struct pmx_dev spear3xx_pmx_i2c;
57extern struct pmx_dev spear3xx_pmx_ssp_cs;
58extern struct pmx_dev spear3xx_pmx_ssp;
59extern struct pmx_dev spear3xx_pmx_mii;
60extern struct pmx_dev spear3xx_pmx_gpio_pin0;
61extern struct pmx_dev spear3xx_pmx_gpio_pin1;
62extern struct pmx_dev spear3xx_pmx_gpio_pin2;
63extern struct pmx_dev spear3xx_pmx_gpio_pin3;
64extern struct pmx_dev spear3xx_pmx_gpio_pin4;
65extern struct pmx_dev spear3xx_pmx_gpio_pin5;
66extern struct pmx_dev spear3xx_pmx_uart0_modem;
67extern struct pmx_dev spear3xx_pmx_uart0;
68extern struct pmx_dev spear3xx_pmx_timer_3_4;
69extern struct pmx_dev spear3xx_pmx_timer_1_2;
70
71#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
72/* padmux plgpio devices */
73extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
74extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
75extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
76extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
77extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
78extern struct pmx_dev spear3xx_pmx_plgpio_28;
79extern struct pmx_dev spear3xx_pmx_plgpio_29;
80extern struct pmx_dev spear3xx_pmx_plgpio_30;
81extern struct pmx_dev spear3xx_pmx_plgpio_31;
82extern struct pmx_dev spear3xx_pmx_plgpio_32;
83extern struct pmx_dev spear3xx_pmx_plgpio_33;
84extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
85extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
86extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
87extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
88#endif
89
90/* spear300 declarations */ 36/* spear300 declarations */
91#ifdef CONFIG_MACH_SPEAR300 37#ifdef CONFIG_MACH_SPEAR300
92/* pad mux modes */
93extern struct pmx_mode spear300_nand_mode;
94extern struct pmx_mode spear300_nor_mode;
95extern struct pmx_mode spear300_photo_frame_mode;
96extern struct pmx_mode spear300_lend_ip_phone_mode;
97extern struct pmx_mode spear300_hend_ip_phone_mode;
98extern struct pmx_mode spear300_lend_wifi_phone_mode;
99extern struct pmx_mode spear300_hend_wifi_phone_mode;
100extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
101extern struct pmx_mode spear300_ata_pabx_i2s_mode;
102extern struct pmx_mode spear300_caml_lcdw_mode;
103extern struct pmx_mode spear300_camu_lcd_mode;
104extern struct pmx_mode spear300_camu_wlcd_mode;
105extern struct pmx_mode spear300_caml_lcd_mode;
106
107/* pad mux devices */
108extern struct pmx_dev spear300_pmx_fsmc_2_chips;
109extern struct pmx_dev spear300_pmx_fsmc_4_chips;
110extern struct pmx_dev spear300_pmx_keyboard;
111extern struct pmx_dev spear300_pmx_clcd;
112extern struct pmx_dev spear300_pmx_telecom_gpio;
113extern struct pmx_dev spear300_pmx_telecom_tdm;
114extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
115extern struct pmx_dev spear300_pmx_telecom_camera;
116extern struct pmx_dev spear300_pmx_telecom_dac;
117extern struct pmx_dev spear300_pmx_telecom_i2s;
118extern struct pmx_dev spear300_pmx_telecom_boot_pins;
119extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
120extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
121extern struct pmx_dev spear300_pmx_gpio1;
122
123/* Add spear300 machine declarations here */
124void __init spear300_clk_init(void); 38void __init spear300_clk_init(void);
125 39
126#endif /* CONFIG_MACH_SPEAR300 */ 40#endif /* CONFIG_MACH_SPEAR300 */
127 41
128/* spear310 declarations */ 42/* spear310 declarations */
129#ifdef CONFIG_MACH_SPEAR310 43#ifdef CONFIG_MACH_SPEAR310
130/* pad mux devices */
131extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
132extern struct pmx_dev spear310_pmx_emi_cs_2_3;
133extern struct pmx_dev spear310_pmx_uart1;
134extern struct pmx_dev spear310_pmx_uart2;
135extern struct pmx_dev spear310_pmx_uart3_4_5;
136extern struct pmx_dev spear310_pmx_fsmc;
137extern struct pmx_dev spear310_pmx_rs485_0_1;
138extern struct pmx_dev spear310_pmx_tdm0;
139
140/* Add spear310 machine declarations here */
141void __init spear310_clk_init(void); 44void __init spear310_clk_init(void);
142 45
143#endif /* CONFIG_MACH_SPEAR310 */ 46#endif /* CONFIG_MACH_SPEAR310 */
144 47
145/* spear320 declarations */ 48/* spear320 declarations */
146#ifdef CONFIG_MACH_SPEAR320 49#ifdef CONFIG_MACH_SPEAR320
147/* pad mux modes */
148extern struct pmx_mode spear320_auto_net_smii_mode;
149extern struct pmx_mode spear320_auto_net_mii_mode;
150extern struct pmx_mode spear320_auto_exp_mode;
151extern struct pmx_mode spear320_small_printers_mode;
152
153/* pad mux devices */
154extern struct pmx_dev spear320_pmx_clcd;
155extern struct pmx_dev spear320_pmx_emi;
156extern struct pmx_dev spear320_pmx_fsmc;
157extern struct pmx_dev spear320_pmx_spp;
158extern struct pmx_dev spear320_pmx_sdhci;
159extern struct pmx_dev spear320_pmx_i2s;
160extern struct pmx_dev spear320_pmx_uart1;
161extern struct pmx_dev spear320_pmx_uart1_modem;
162extern struct pmx_dev spear320_pmx_uart2;
163extern struct pmx_dev spear320_pmx_touchscreen;
164extern struct pmx_dev spear320_pmx_can;
165extern struct pmx_dev spear320_pmx_sdhci_led;
166extern struct pmx_dev spear320_pmx_pwm0;
167extern struct pmx_dev spear320_pmx_pwm1;
168extern struct pmx_dev spear320_pmx_pwm2;
169extern struct pmx_dev spear320_pmx_pwm3;
170extern struct pmx_dev spear320_pmx_ssp1;
171extern struct pmx_dev spear320_pmx_ssp2;
172extern struct pmx_dev spear320_pmx_mii1;
173extern struct pmx_dev spear320_pmx_smii0;
174extern struct pmx_dev spear320_pmx_smii1;
175extern struct pmx_dev spear320_pmx_i2c1;
176
177/* Add spear320 machine declarations here */
178void __init spear320_clk_init(void); 50void __init spear320_clk_init(void);
179 51
180#endif /* CONFIG_MACH_SPEAR320 */ 52#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index febcdd8d4e9..f75fe25a620 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -60,357 +60,6 @@
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
62 62
63/* pad multiplexing support */
64/* muxing registers */
65#define PAD_MUX_CONFIG_REG 0x00
66#define MODE_CONFIG_REG 0x04
67
68/* modes */
69#define NAND_MODE (1 << 0)
70#define NOR_MODE (1 << 1)
71#define PHOTO_FRAME_MODE (1 << 2)
72#define LEND_IP_PHONE_MODE (1 << 3)
73#define HEND_IP_PHONE_MODE (1 << 4)
74#define LEND_WIFI_PHONE_MODE (1 << 5)
75#define HEND_WIFI_PHONE_MODE (1 << 6)
76#define ATA_PABX_WI2S_MODE (1 << 7)
77#define ATA_PABX_I2S_MODE (1 << 8)
78#define CAML_LCDW_MODE (1 << 9)
79#define CAMU_LCD_MODE (1 << 10)
80#define CAMU_WLCD_MODE (1 << 11)
81#define CAML_LCD_MODE (1 << 12)
82#define ALL_MODES 0x1FFF
83
84struct pmx_mode spear300_nand_mode = {
85 .id = NAND_MODE,
86 .name = "nand mode",
87 .mask = 0x00,
88};
89
90struct pmx_mode spear300_nor_mode = {
91 .id = NOR_MODE,
92 .name = "nor mode",
93 .mask = 0x01,
94};
95
96struct pmx_mode spear300_photo_frame_mode = {
97 .id = PHOTO_FRAME_MODE,
98 .name = "photo frame mode",
99 .mask = 0x02,
100};
101
102struct pmx_mode spear300_lend_ip_phone_mode = {
103 .id = LEND_IP_PHONE_MODE,
104 .name = "lend ip phone mode",
105 .mask = 0x03,
106};
107
108struct pmx_mode spear300_hend_ip_phone_mode = {
109 .id = HEND_IP_PHONE_MODE,
110 .name = "hend ip phone mode",
111 .mask = 0x04,
112};
113
114struct pmx_mode spear300_lend_wifi_phone_mode = {
115 .id = LEND_WIFI_PHONE_MODE,
116 .name = "lend wifi phone mode",
117 .mask = 0x05,
118};
119
120struct pmx_mode spear300_hend_wifi_phone_mode = {
121 .id = HEND_WIFI_PHONE_MODE,
122 .name = "hend wifi phone mode",
123 .mask = 0x06,
124};
125
126struct pmx_mode spear300_ata_pabx_wi2s_mode = {
127 .id = ATA_PABX_WI2S_MODE,
128 .name = "ata pabx wi2s mode",
129 .mask = 0x07,
130};
131
132struct pmx_mode spear300_ata_pabx_i2s_mode = {
133 .id = ATA_PABX_I2S_MODE,
134 .name = "ata pabx i2s mode",
135 .mask = 0x08,
136};
137
138struct pmx_mode spear300_caml_lcdw_mode = {
139 .id = CAML_LCDW_MODE,
140 .name = "caml lcdw mode",
141 .mask = 0x0C,
142};
143
144struct pmx_mode spear300_camu_lcd_mode = {
145 .id = CAMU_LCD_MODE,
146 .name = "camu lcd mode",
147 .mask = 0x0D,
148};
149
150struct pmx_mode spear300_camu_wlcd_mode = {
151 .id = CAMU_WLCD_MODE,
152 .name = "camu wlcd mode",
153 .mask = 0x0E,
154};
155
156struct pmx_mode spear300_caml_lcd_mode = {
157 .id = CAML_LCD_MODE,
158 .name = "caml lcd mode",
159 .mask = 0x0F,
160};
161
162/* devices */
163static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
164 {
165 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
166 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
167 .mask = PMX_FIRDA_MASK,
168 },
169};
170
171struct pmx_dev spear300_pmx_fsmc_2_chips = {
172 .name = "fsmc_2_chips",
173 .modes = pmx_fsmc_2_chips_modes,
174 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
175 .enb_on_reset = 1,
176};
177
178static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
179 {
180 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
181 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
182 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
183 },
184};
185
186struct pmx_dev spear300_pmx_fsmc_4_chips = {
187 .name = "fsmc_4_chips",
188 .modes = pmx_fsmc_4_chips_modes,
189 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
190 .enb_on_reset = 1,
191};
192
193static struct pmx_dev_mode pmx_keyboard_modes[] = {
194 {
195 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
196 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
197 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
198 CAML_LCD_MODE,
199 .mask = 0x0,
200 },
201};
202
203struct pmx_dev spear300_pmx_keyboard = {
204 .name = "keyboard",
205 .modes = pmx_keyboard_modes,
206 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
207 .enb_on_reset = 1,
208};
209
210static struct pmx_dev_mode pmx_clcd_modes[] = {
211 {
212 .ids = PHOTO_FRAME_MODE,
213 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
214 }, {
215 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
216 CAMU_LCD_MODE | CAML_LCD_MODE,
217 .mask = PMX_TIMER_3_4_MASK,
218 },
219};
220
221struct pmx_dev spear300_pmx_clcd = {
222 .name = "clcd",
223 .modes = pmx_clcd_modes,
224 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
225 .enb_on_reset = 1,
226};
227
228static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
229 {
230 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
231 .mask = PMX_MII_MASK,
232 }, {
233 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
234 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
235 }, {
236 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
237 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
238 }, {
239 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
240 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
241 }, {
242 .ids = ATA_PABX_WI2S_MODE,
243 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
244 | PMX_UART0_MODEM_MASK,
245 },
246};
247
248struct pmx_dev spear300_pmx_telecom_gpio = {
249 .name = "telecom_gpio",
250 .modes = pmx_telecom_gpio_modes,
251 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
256 {
257 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
258 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
259 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
260 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
261 | CAMU_WLCD_MODE | CAML_LCD_MODE,
262 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
263 },
264};
265
266struct pmx_dev spear300_pmx_telecom_tdm = {
267 .name = "telecom_tdm",
268 .modes = pmx_telecom_tdm_modes,
269 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
270 .enb_on_reset = 1,
271};
272
273static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
274 {
275 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
276 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
277 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
278 CAML_LCDW_MODE | CAML_LCD_MODE,
279 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
280 },
281};
282
283struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
284 .name = "telecom_spi_cs_i2c_clk",
285 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
286 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
287 .enb_on_reset = 1,
288};
289
290static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
291 {
292 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
293 .mask = PMX_MII_MASK,
294 }, {
295 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
296 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
297 },
298};
299
300struct pmx_dev spear300_pmx_telecom_camera = {
301 .name = "telecom_camera",
302 .modes = pmx_telecom_camera_modes,
303 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
304 .enb_on_reset = 1,
305};
306
307static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
308 {
309 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
310 | CAMU_WLCD_MODE | CAML_LCD_MODE,
311 .mask = PMX_TIMER_1_2_MASK,
312 },
313};
314
315struct pmx_dev spear300_pmx_telecom_dac = {
316 .name = "telecom_dac",
317 .modes = pmx_telecom_dac_modes,
318 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
319 .enb_on_reset = 1,
320};
321
322static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
323 {
324 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
325 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
326 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
327 | CAMU_WLCD_MODE | CAML_LCD_MODE,
328 .mask = PMX_UART0_MODEM_MASK,
329 },
330};
331
332struct pmx_dev spear300_pmx_telecom_i2s = {
333 .name = "telecom_i2s",
334 .modes = pmx_telecom_i2s_modes,
335 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
336 .enb_on_reset = 1,
337};
338
339static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
340 {
341 .ids = NAND_MODE | NOR_MODE,
342 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
343 PMX_TIMER_3_4_MASK,
344 },
345};
346
347struct pmx_dev spear300_pmx_telecom_boot_pins = {
348 .name = "telecom_boot_pins",
349 .modes = pmx_telecom_boot_pins_modes,
350 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
355 {
356 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
357 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
358 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
359 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
360 ATA_PABX_I2S_MODE,
361 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
362 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
363 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
364 },
365};
366
367struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
368 .name = "telecom_sdhci_4bit",
369 .modes = pmx_telecom_sdhci_4bit_modes,
370 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
371 .enb_on_reset = 1,
372};
373
374static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
375 {
376 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
377 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
378 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
379 CAMU_WLCD_MODE | CAML_LCD_MODE,
380 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
381 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
382 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
383 },
384};
385
386struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
387 .name = "telecom_sdhci_8bit",
388 .modes = pmx_telecom_sdhci_8bit_modes,
389 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
390 .enb_on_reset = 1,
391};
392
393static struct pmx_dev_mode pmx_gpio1_modes[] = {
394 {
395 .ids = PHOTO_FRAME_MODE,
396 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
397 PMX_TIMER_3_4_MASK,
398 },
399};
400
401struct pmx_dev spear300_pmx_gpio1 = {
402 .name = "arm gpio1",
403 .modes = pmx_gpio1_modes,
404 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
405 .enb_on_reset = 1,
406};
407
408/* pmx driver structure */
409static struct pmx_driver pmx_driver = {
410 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
411 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
412};
413
414/* spear3xx shared irq */ 63/* spear3xx shared irq */
415static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
416 { 65 {
@@ -464,22 +113,6 @@ static struct spear_shirq shirq_ras1 = {
464 }, 113 },
465}; 114};
466 115
467/* padmux devices to enable */
468static struct pmx_dev *spear300_evb_pmx_devs[] = {
469 /* spear3xx specific devices */
470 &spear3xx_pmx_i2c,
471 &spear3xx_pmx_ssp_cs,
472 &spear3xx_pmx_ssp,
473 &spear3xx_pmx_mii,
474 &spear3xx_pmx_uart0,
475
476 /* spear300 specific devices */
477 &spear300_pmx_fsmc_2_chips,
478 &spear300_pmx_clcd,
479 &spear300_pmx_telecom_sdhci_4bit,
480 &spear300_pmx_gpio1,
481};
482
483/* DMAC platform data's slave info */ 116/* DMAC platform data's slave info */
484struct pl08x_channel_data spear300_dma_info[] = { 117struct pl08x_channel_data spear300_dma_info[] = {
485 { 118 {
@@ -678,7 +311,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
678 311
679static void __init spear300_dt_init(void) 312static void __init spear300_dt_init(void)
680{ 313{
681 int ret = -EINVAL; 314 int ret;
682 315
683 pl080_plat_data.slave_channels = spear300_dma_info; 316 pl080_plat_data.slave_channels = spear300_dma_info;
684 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); 317 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
@@ -693,26 +326,6 @@ static void __init spear300_dt_init(void)
693 if (ret) 326 if (ret)
694 pr_err("Error registering Shared IRQ\n"); 327 pr_err("Error registering Shared IRQ\n");
695 } 328 }
696
697 if (of_machine_is_compatible("st,spear300-evb")) {
698 /* pmx initialization */
699 pmx_driver.mode = &spear300_photo_frame_mode;
700 pmx_driver.devs = spear300_evb_pmx_devs;
701 pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
702
703 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
704 if (pmx_driver.base) {
705 ret = pmx_register(&pmx_driver);
706 if (ret)
707 pr_err("padmux: registration failed. err no: %d\n",
708 ret);
709 /* Free Mapping, device selection already done */
710 iounmap(pmx_driver.base);
711 }
712
713 if (ret)
714 pr_err("Initialization Failed");
715 }
716} 329}
717 330
718static const char * const spear300_dt_board_compat[] = { 331static const char * const spear300_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b26e41566b5..f0842a58dc0 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -82,128 +82,6 @@
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) 82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83 83
84 84
85/* pad multiplexing support */
86/* muxing registers */
87#define PAD_MUX_CONFIG_REG 0x08
88
89/* devices */
90static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
91 {
92 .ids = 0x00,
93 .mask = PMX_TIMER_3_4_MASK,
94 },
95};
96
97struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
98 .name = "emi_cs_0_1_4_5",
99 .modes = pmx_emi_cs_0_1_4_5_modes,
100 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
101 .enb_on_reset = 1,
102};
103
104static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
105 {
106 .ids = 0x00,
107 .mask = PMX_TIMER_1_2_MASK,
108 },
109};
110
111struct pmx_dev spear310_pmx_emi_cs_2_3 = {
112 .name = "emi_cs_2_3",
113 .modes = pmx_emi_cs_2_3_modes,
114 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
115 .enb_on_reset = 1,
116};
117
118static struct pmx_dev_mode pmx_uart1_modes[] = {
119 {
120 .ids = 0x00,
121 .mask = PMX_FIRDA_MASK,
122 },
123};
124
125struct pmx_dev spear310_pmx_uart1 = {
126 .name = "uart1",
127 .modes = pmx_uart1_modes,
128 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
129 .enb_on_reset = 1,
130};
131
132static struct pmx_dev_mode pmx_uart2_modes[] = {
133 {
134 .ids = 0x00,
135 .mask = PMX_TIMER_1_2_MASK,
136 },
137};
138
139struct pmx_dev spear310_pmx_uart2 = {
140 .name = "uart2",
141 .modes = pmx_uart2_modes,
142 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
143 .enb_on_reset = 1,
144};
145
146static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
147 {
148 .ids = 0x00,
149 .mask = PMX_UART0_MODEM_MASK,
150 },
151};
152
153struct pmx_dev spear310_pmx_uart3_4_5 = {
154 .name = "uart3_4_5",
155 .modes = pmx_uart3_4_5_modes,
156 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
157 .enb_on_reset = 1,
158};
159
160static struct pmx_dev_mode pmx_fsmc_modes[] = {
161 {
162 .ids = 0x00,
163 .mask = PMX_SSP_CS_MASK,
164 },
165};
166
167struct pmx_dev spear310_pmx_fsmc = {
168 .name = "fsmc",
169 .modes = pmx_fsmc_modes,
170 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
171 .enb_on_reset = 1,
172};
173
174static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
175 {
176 .ids = 0x00,
177 .mask = PMX_MII_MASK,
178 },
179};
180
181struct pmx_dev spear310_pmx_rs485_0_1 = {
182 .name = "rs485_0_1",
183 .modes = pmx_rs485_0_1_modes,
184 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
185 .enb_on_reset = 1,
186};
187
188static struct pmx_dev_mode pmx_tdm0_modes[] = {
189 {
190 .ids = 0x00,
191 .mask = PMX_MII_MASK,
192 },
193};
194
195struct pmx_dev spear310_pmx_tdm0 = {
196 .name = "tdm0",
197 .modes = pmx_tdm0_modes,
198 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
199 .enb_on_reset = 1,
200};
201
202/* pmx driver structure */
203static struct pmx_driver pmx_driver = {
204 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
205};
206
207/* spear3xx shared irq */ 85/* spear3xx shared irq */
208static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
209 { 87 {
@@ -320,30 +198,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
320 }, 198 },
321}; 199};
322 200
323/* padmux devices to enable */
324static struct pmx_dev *spear310_evb_pmx_devs[] = {
325 /* spear3xx specific devices */
326 &spear3xx_pmx_i2c,
327 &spear3xx_pmx_ssp,
328 &spear3xx_pmx_gpio_pin0,
329 &spear3xx_pmx_gpio_pin1,
330 &spear3xx_pmx_gpio_pin2,
331 &spear3xx_pmx_gpio_pin3,
332 &spear3xx_pmx_gpio_pin4,
333 &spear3xx_pmx_gpio_pin5,
334 &spear3xx_pmx_uart0,
335
336 /* spear310 specific devices */
337 &spear310_pmx_emi_cs_0_1_4_5,
338 &spear310_pmx_emi_cs_2_3,
339 &spear310_pmx_uart1,
340 &spear310_pmx_uart2,
341 &spear310_pmx_uart3_4_5,
342 &spear310_pmx_fsmc,
343 &spear310_pmx_rs485_0_1,
344 &spear310_pmx_tdm0,
345};
346
347/* DMAC platform data's slave info */ 201/* DMAC platform data's slave info */
348struct pl08x_channel_data spear310_dma_info[] = { 202struct pl08x_channel_data spear310_dma_info[] = {
349 { 203 {
@@ -578,7 +432,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
578static void __init spear310_dt_init(void) 432static void __init spear310_dt_init(void)
579{ 433{
580 void __iomem *base; 434 void __iomem *base;
581 int ret = 0; 435 int ret;
582 436
583 pl080_plat_data.slave_channels = spear310_dma_info; 437 pl080_plat_data.slave_channels = spear310_dma_info;
584 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); 438 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
@@ -613,19 +467,6 @@ static void __init spear310_dt_init(void)
613 if (ret) 467 if (ret)
614 pr_err("Error registering Shared IRQ 4\n"); 468 pr_err("Error registering Shared IRQ 4\n");
615 } 469 }
616
617 if (of_machine_is_compatible("st,spear310-evb")) {
618 /* pmx initialization */
619 pmx_driver.base = base;
620 pmx_driver.mode = NULL;
621 pmx_driver.devs = spear310_evb_pmx_devs;
622 pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
623
624 ret = pmx_register(&pmx_driver);
625 if (ret)
626 pr_err("padmux: registration failed. err no: %d\n",
627 ret);
628 }
629} 470}
630 471
631static const char * const spear310_dt_board_compat[] = { 472static const char * const spear310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 2f5979b0c16..e8caeef50a5 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -83,373 +83,6 @@
83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) 83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) 84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
85 85
86/* pad multiplexing support */
87/* muxing registers */
88#define PAD_MUX_CONFIG_REG 0x0C
89#define MODE_CONFIG_REG 0x10
90
91/* modes */
92#define AUTO_NET_SMII_MODE (1 << 0)
93#define AUTO_NET_MII_MODE (1 << 1)
94#define AUTO_EXP_MODE (1 << 2)
95#define SMALL_PRINTERS_MODE (1 << 3)
96#define ALL_MODES 0xF
97
98struct pmx_mode spear320_auto_net_smii_mode = {
99 .id = AUTO_NET_SMII_MODE,
100 .name = "Automation Networking SMII Mode",
101 .mask = 0x00,
102};
103
104struct pmx_mode spear320_auto_net_mii_mode = {
105 .id = AUTO_NET_MII_MODE,
106 .name = "Automation Networking MII Mode",
107 .mask = 0x01,
108};
109
110struct pmx_mode spear320_auto_exp_mode = {
111 .id = AUTO_EXP_MODE,
112 .name = "Automation Expanded Mode",
113 .mask = 0x02,
114};
115
116struct pmx_mode spear320_small_printers_mode = {
117 .id = SMALL_PRINTERS_MODE,
118 .name = "Small Printers Mode",
119 .mask = 0x03,
120};
121
122/* devices */
123static struct pmx_dev_mode pmx_clcd_modes[] = {
124 {
125 .ids = AUTO_NET_SMII_MODE,
126 .mask = 0x0,
127 },
128};
129
130struct pmx_dev spear320_pmx_clcd = {
131 .name = "clcd",
132 .modes = pmx_clcd_modes,
133 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_emi_modes[] = {
138 {
139 .ids = AUTO_EXP_MODE,
140 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
141 },
142};
143
144struct pmx_dev spear320_pmx_emi = {
145 .name = "emi",
146 .modes = pmx_emi_modes,
147 .mode_count = ARRAY_SIZE(pmx_emi_modes),
148 .enb_on_reset = 1,
149};
150
151static struct pmx_dev_mode pmx_fsmc_modes[] = {
152 {
153 .ids = ALL_MODES,
154 .mask = 0x0,
155 },
156};
157
158struct pmx_dev spear320_pmx_fsmc = {
159 .name = "fsmc",
160 .modes = pmx_fsmc_modes,
161 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
162 .enb_on_reset = 1,
163};
164
165static struct pmx_dev_mode pmx_spp_modes[] = {
166 {
167 .ids = SMALL_PRINTERS_MODE,
168 .mask = 0x0,
169 },
170};
171
172struct pmx_dev spear320_pmx_spp = {
173 .name = "spp",
174 .modes = pmx_spp_modes,
175 .mode_count = ARRAY_SIZE(pmx_spp_modes),
176 .enb_on_reset = 1,
177};
178
179static struct pmx_dev_mode pmx_sdhci_modes[] = {
180 {
181 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
182 SMALL_PRINTERS_MODE,
183 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
184 },
185};
186
187struct pmx_dev spear320_pmx_sdhci = {
188 .name = "sdhci",
189 .modes = pmx_sdhci_modes,
190 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
191 .enb_on_reset = 1,
192};
193
194static struct pmx_dev_mode pmx_i2s_modes[] = {
195 {
196 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
197 .mask = PMX_UART0_MODEM_MASK,
198 },
199};
200
201struct pmx_dev spear320_pmx_i2s = {
202 .name = "i2s",
203 .modes = pmx_i2s_modes,
204 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
205 .enb_on_reset = 1,
206};
207
208static struct pmx_dev_mode pmx_uart1_modes[] = {
209 {
210 .ids = ALL_MODES,
211 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
212 },
213};
214
215struct pmx_dev spear320_pmx_uart1 = {
216 .name = "uart1",
217 .modes = pmx_uart1_modes,
218 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
219 .enb_on_reset = 1,
220};
221
222static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
223 {
224 .ids = AUTO_EXP_MODE,
225 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
226 PMX_SSP_CS_MASK,
227 }, {
228 .ids = SMALL_PRINTERS_MODE,
229 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
230 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
231 },
232};
233
234struct pmx_dev spear320_pmx_uart1_modem = {
235 .name = "uart1_modem",
236 .modes = pmx_uart1_modem_modes,
237 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
238 .enb_on_reset = 1,
239};
240
241static struct pmx_dev_mode pmx_uart2_modes[] = {
242 {
243 .ids = ALL_MODES,
244 .mask = PMX_FIRDA_MASK,
245 },
246};
247
248struct pmx_dev spear320_pmx_uart2 = {
249 .name = "uart2",
250 .modes = pmx_uart2_modes,
251 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_touchscreen_modes[] = {
256 {
257 .ids = AUTO_NET_SMII_MODE,
258 .mask = PMX_SSP_CS_MASK,
259 },
260};
261
262struct pmx_dev spear320_pmx_touchscreen = {
263 .name = "touchscreen",
264 .modes = pmx_touchscreen_modes,
265 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
266 .enb_on_reset = 1,
267};
268
269static struct pmx_dev_mode pmx_can_modes[] = {
270 {
271 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
272 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
273 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_can = {
278 .name = "can",
279 .modes = pmx_can_modes,
280 .mode_count = ARRAY_SIZE(pmx_can_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
285 {
286 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
287 .mask = PMX_SSP_CS_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_sdhci_led = {
292 .name = "sdhci_led",
293 .modes = pmx_sdhci_led_modes,
294 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_pwm0_modes[] = {
299 {
300 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
301 .mask = PMX_UART0_MODEM_MASK,
302 }, {
303 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
304 .mask = PMX_MII_MASK,
305 },
306};
307
308struct pmx_dev spear320_pmx_pwm0 = {
309 .name = "pwm0",
310 .modes = pmx_pwm0_modes,
311 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
312 .enb_on_reset = 1,
313};
314
315static struct pmx_dev_mode pmx_pwm1_modes[] = {
316 {
317 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
318 .mask = PMX_UART0_MODEM_MASK,
319 }, {
320 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
321 .mask = PMX_MII_MASK,
322 },
323};
324
325struct pmx_dev spear320_pmx_pwm1 = {
326 .name = "pwm1",
327 .modes = pmx_pwm1_modes,
328 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
329 .enb_on_reset = 1,
330};
331
332static struct pmx_dev_mode pmx_pwm2_modes[] = {
333 {
334 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
335 .mask = PMX_SSP_CS_MASK,
336 }, {
337 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
338 .mask = PMX_MII_MASK,
339 },
340};
341
342struct pmx_dev spear320_pmx_pwm2 = {
343 .name = "pwm2",
344 .modes = pmx_pwm2_modes,
345 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
346 .enb_on_reset = 1,
347};
348
349static struct pmx_dev_mode pmx_pwm3_modes[] = {
350 {
351 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
352 .mask = PMX_MII_MASK,
353 },
354};
355
356struct pmx_dev spear320_pmx_pwm3 = {
357 .name = "pwm3",
358 .modes = pmx_pwm3_modes,
359 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
360 .enb_on_reset = 1,
361};
362
363static struct pmx_dev_mode pmx_ssp1_modes[] = {
364 {
365 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
366 .mask = PMX_MII_MASK,
367 },
368};
369
370struct pmx_dev spear320_pmx_ssp1 = {
371 .name = "ssp1",
372 .modes = pmx_ssp1_modes,
373 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
374 .enb_on_reset = 1,
375};
376
377static struct pmx_dev_mode pmx_ssp2_modes[] = {
378 {
379 .ids = AUTO_NET_SMII_MODE,
380 .mask = PMX_MII_MASK,
381 },
382};
383
384struct pmx_dev spear320_pmx_ssp2 = {
385 .name = "ssp2",
386 .modes = pmx_ssp2_modes,
387 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
388 .enb_on_reset = 1,
389};
390
391static struct pmx_dev_mode pmx_mii1_modes[] = {
392 {
393 .ids = AUTO_NET_MII_MODE,
394 .mask = 0x0,
395 },
396};
397
398struct pmx_dev spear320_pmx_mii1 = {
399 .name = "mii1",
400 .modes = pmx_mii1_modes,
401 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
402 .enb_on_reset = 1,
403};
404
405static struct pmx_dev_mode pmx_smii0_modes[] = {
406 {
407 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
408 .mask = PMX_MII_MASK,
409 },
410};
411
412struct pmx_dev spear320_pmx_smii0 = {
413 .name = "smii0",
414 .modes = pmx_smii0_modes,
415 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
416 .enb_on_reset = 1,
417};
418
419static struct pmx_dev_mode pmx_smii1_modes[] = {
420 {
421 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
422 .mask = PMX_MII_MASK,
423 },
424};
425
426struct pmx_dev spear320_pmx_smii1 = {
427 .name = "smii1",
428 .modes = pmx_smii1_modes,
429 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
430 .enb_on_reset = 1,
431};
432
433static struct pmx_dev_mode pmx_i2c1_modes[] = {
434 {
435 .ids = AUTO_EXP_MODE,
436 .mask = 0x0,
437 },
438};
439
440struct pmx_dev spear320_pmx_i2c1 = {
441 .name = "i2c1",
442 .modes = pmx_i2c1_modes,
443 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
444 .enb_on_reset = 1,
445};
446
447/* pmx driver structure */
448static struct pmx_driver pmx_driver = {
449 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
450 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
451};
452
453/* spear3xx shared irq */ 86/* spear3xx shared irq */
454static struct shirq_dev_config shirq_ras1_config[] = { 87static struct shirq_dev_config shirq_ras1_config[] = {
455 { 88 {
@@ -574,27 +207,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
574 }, 207 },
575}; 208};
576 209
577/* padmux devices to enable */
578static struct pmx_dev *spear320_evb_pmx_devs[] = {
579 /* spear3xx specific devices */
580 &spear3xx_pmx_i2c,
581 &spear3xx_pmx_ssp,
582 &spear3xx_pmx_mii,
583 &spear3xx_pmx_uart0,
584
585 /* spear320 specific devices */
586 &spear320_pmx_fsmc,
587 &spear320_pmx_sdhci,
588 &spear320_pmx_i2s,
589 &spear320_pmx_uart1,
590 &spear320_pmx_uart2,
591 &spear320_pmx_can,
592 &spear320_pmx_pwm0,
593 &spear320_pmx_pwm1,
594 &spear320_pmx_pwm2,
595 &spear320_pmx_mii1,
596};
597
598/* DMAC platform data's slave info */ 210/* DMAC platform data's slave info */
599struct pl08x_channel_data spear320_dma_info[] = { 211struct pl08x_channel_data spear320_dma_info[] = {
600 { 212 {
@@ -832,7 +444,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
832static void __init spear320_dt_init(void) 444static void __init spear320_dt_init(void)
833{ 445{
834 void __iomem *base; 446 void __iomem *base;
835 int ret = 0; 447 int ret;
836 448
837 pl080_plat_data.slave_channels = spear320_dma_info; 449 pl080_plat_data.slave_channels = spear320_dma_info;
838 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 450 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
@@ -861,19 +473,6 @@ static void __init spear320_dt_init(void)
861 if (ret) 473 if (ret)
862 pr_err("Error registering Shared IRQ 4\n"); 474 pr_err("Error registering Shared IRQ 4\n");
863 } 475 }
864
865 if (of_machine_is_compatible("st,spear320-evb")) {
866 /* pmx initialization */
867 pmx_driver.base = base;
868 pmx_driver.mode = &spear320_auto_net_mii_mode;
869 pmx_driver.devs = spear320_evb_pmx_devs;
870 pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
871
872 ret = pmx_register(&pmx_driver);
873 if (ret)
874 pr_err("padmux: registration failed. err no: %d\n",
875 ret);
876 }
877} 476}
878 477
879static const char * const spear320_dt_board_compat[] = { 478static const char * const spear320_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index bbb11efa605..826ac20ef1e 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -23,431 +23,6 @@
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/spear.h> 24#include <mach/spear.h>
25 25
26/* pad multiplexing support */
27/* devices */
28static struct pmx_dev_mode pmx_firda_modes[] = {
29 {
30 .ids = 0xffffffff,
31 .mask = PMX_FIRDA_MASK,
32 },
33};
34
35struct pmx_dev spear3xx_pmx_firda = {
36 .name = "firda",
37 .modes = pmx_firda_modes,
38 .mode_count = ARRAY_SIZE(pmx_firda_modes),
39 .enb_on_reset = 0,
40};
41
42static struct pmx_dev_mode pmx_i2c_modes[] = {
43 {
44 .ids = 0xffffffff,
45 .mask = PMX_I2C_MASK,
46 },
47};
48
49struct pmx_dev spear3xx_pmx_i2c = {
50 .name = "i2c",
51 .modes = pmx_i2c_modes,
52 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
53 .enb_on_reset = 0,
54};
55
56static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
57 {
58 .ids = 0xffffffff,
59 .mask = PMX_SSP_CS_MASK,
60 },
61};
62
63struct pmx_dev spear3xx_pmx_ssp_cs = {
64 .name = "ssp_chip_selects",
65 .modes = pmx_ssp_cs_modes,
66 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
67 .enb_on_reset = 0,
68};
69
70static struct pmx_dev_mode pmx_ssp_modes[] = {
71 {
72 .ids = 0xffffffff,
73 .mask = PMX_SSP_MASK,
74 },
75};
76
77struct pmx_dev spear3xx_pmx_ssp = {
78 .name = "ssp",
79 .modes = pmx_ssp_modes,
80 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
81 .enb_on_reset = 0,
82};
83
84static struct pmx_dev_mode pmx_mii_modes[] = {
85 {
86 .ids = 0xffffffff,
87 .mask = PMX_MII_MASK,
88 },
89};
90
91struct pmx_dev spear3xx_pmx_mii = {
92 .name = "mii",
93 .modes = pmx_mii_modes,
94 .mode_count = ARRAY_SIZE(pmx_mii_modes),
95 .enb_on_reset = 0,
96};
97
98static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
99 {
100 .ids = 0xffffffff,
101 .mask = PMX_GPIO_PIN0_MASK,
102 },
103};
104
105struct pmx_dev spear3xx_pmx_gpio_pin0 = {
106 .name = "gpio_pin0",
107 .modes = pmx_gpio_pin0_modes,
108 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
109 .enb_on_reset = 0,
110};
111
112static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
113 {
114 .ids = 0xffffffff,
115 .mask = PMX_GPIO_PIN1_MASK,
116 },
117};
118
119struct pmx_dev spear3xx_pmx_gpio_pin1 = {
120 .name = "gpio_pin1",
121 .modes = pmx_gpio_pin1_modes,
122 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
123 .enb_on_reset = 0,
124};
125
126static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
127 {
128 .ids = 0xffffffff,
129 .mask = PMX_GPIO_PIN2_MASK,
130 },
131};
132
133struct pmx_dev spear3xx_pmx_gpio_pin2 = {
134 .name = "gpio_pin2",
135 .modes = pmx_gpio_pin2_modes,
136 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
137 .enb_on_reset = 0,
138};
139
140static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
141 {
142 .ids = 0xffffffff,
143 .mask = PMX_GPIO_PIN3_MASK,
144 },
145};
146
147struct pmx_dev spear3xx_pmx_gpio_pin3 = {
148 .name = "gpio_pin3",
149 .modes = pmx_gpio_pin3_modes,
150 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
151 .enb_on_reset = 0,
152};
153
154static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
155 {
156 .ids = 0xffffffff,
157 .mask = PMX_GPIO_PIN4_MASK,
158 },
159};
160
161struct pmx_dev spear3xx_pmx_gpio_pin4 = {
162 .name = "gpio_pin4",
163 .modes = pmx_gpio_pin4_modes,
164 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
165 .enb_on_reset = 0,
166};
167
168static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
169 {
170 .ids = 0xffffffff,
171 .mask = PMX_GPIO_PIN5_MASK,
172 },
173};
174
175struct pmx_dev spear3xx_pmx_gpio_pin5 = {
176 .name = "gpio_pin5",
177 .modes = pmx_gpio_pin5_modes,
178 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
179 .enb_on_reset = 0,
180};
181
182static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
183 {
184 .ids = 0xffffffff,
185 .mask = PMX_UART0_MODEM_MASK,
186 },
187};
188
189struct pmx_dev spear3xx_pmx_uart0_modem = {
190 .name = "uart0_modem",
191 .modes = pmx_uart0_modem_modes,
192 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
193 .enb_on_reset = 0,
194};
195
196static struct pmx_dev_mode pmx_uart0_modes[] = {
197 {
198 .ids = 0xffffffff,
199 .mask = PMX_UART0_MASK,
200 },
201};
202
203struct pmx_dev spear3xx_pmx_uart0 = {
204 .name = "uart0",
205 .modes = pmx_uart0_modes,
206 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
207 .enb_on_reset = 0,
208};
209
210static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
211 {
212 .ids = 0xffffffff,
213 .mask = PMX_TIMER_3_4_MASK,
214 },
215};
216
217struct pmx_dev spear3xx_pmx_timer_3_4 = {
218 .name = "timer_3_4",
219 .modes = pmx_timer_3_4_modes,
220 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
221 .enb_on_reset = 0,
222};
223
224static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
225 {
226 .ids = 0xffffffff,
227 .mask = PMX_TIMER_1_2_MASK,
228 },
229};
230
231struct pmx_dev spear3xx_pmx_timer_1_2 = {
232 .name = "timer_1_2",
233 .modes = pmx_timer_1_2_modes,
234 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
235 .enb_on_reset = 0,
236};
237
238#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
239/* plgpios devices */
240static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
241 {
242 .ids = 0x00,
243 .mask = PMX_FIRDA_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
248 .name = "plgpio 0 and 1",
249 .modes = pmx_plgpio_0_1_modes,
250 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
251 .enb_on_reset = 1,
252};
253
254static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
255 {
256 .ids = 0x00,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
262 .name = "plgpio 2 and 3",
263 .modes = pmx_plgpio_2_3_modes,
264 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
265 .enb_on_reset = 1,
266};
267
268static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
269 {
270 .ids = 0x00,
271 .mask = PMX_I2C_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
276 .name = "plgpio 4 and 5",
277 .modes = pmx_plgpio_4_5_modes,
278 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
279 .enb_on_reset = 1,
280};
281
282static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
283 {
284 .ids = 0x00,
285 .mask = PMX_SSP_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
290 .name = "plgpio 6 to 9",
291 .modes = pmx_plgpio_6_9_modes,
292 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
293 .enb_on_reset = 1,
294};
295
296static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
297 {
298 .ids = 0x00,
299 .mask = PMX_MII_MASK,
300 },
301};
302
303struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
304 .name = "plgpio 10 to 27",
305 .modes = pmx_plgpio_10_27_modes,
306 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
307 .enb_on_reset = 1,
308};
309
310static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
311 {
312 .ids = 0x00,
313 .mask = PMX_GPIO_PIN0_MASK,
314 },
315};
316
317struct pmx_dev spear3xx_pmx_plgpio_28 = {
318 .name = "plgpio 28",
319 .modes = pmx_plgpio_28_modes,
320 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
321 .enb_on_reset = 1,
322};
323
324static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
325 {
326 .ids = 0x00,
327 .mask = PMX_GPIO_PIN1_MASK,
328 },
329};
330
331struct pmx_dev spear3xx_pmx_plgpio_29 = {
332 .name = "plgpio 29",
333 .modes = pmx_plgpio_29_modes,
334 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
335 .enb_on_reset = 1,
336};
337
338static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
339 {
340 .ids = 0x00,
341 .mask = PMX_GPIO_PIN2_MASK,
342 },
343};
344
345struct pmx_dev spear3xx_pmx_plgpio_30 = {
346 .name = "plgpio 30",
347 .modes = pmx_plgpio_30_modes,
348 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
353 {
354 .ids = 0x00,
355 .mask = PMX_GPIO_PIN3_MASK,
356 },
357};
358
359struct pmx_dev spear3xx_pmx_plgpio_31 = {
360 .name = "plgpio 31",
361 .modes = pmx_plgpio_31_modes,
362 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
363 .enb_on_reset = 1,
364};
365
366static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
367 {
368 .ids = 0x00,
369 .mask = PMX_GPIO_PIN4_MASK,
370 },
371};
372
373struct pmx_dev spear3xx_pmx_plgpio_32 = {
374 .name = "plgpio 32",
375 .modes = pmx_plgpio_32_modes,
376 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
377 .enb_on_reset = 1,
378};
379
380static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
381 {
382 .ids = 0x00,
383 .mask = PMX_GPIO_PIN5_MASK,
384 },
385};
386
387struct pmx_dev spear3xx_pmx_plgpio_33 = {
388 .name = "plgpio 33",
389 .modes = pmx_plgpio_33_modes,
390 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
391 .enb_on_reset = 1,
392};
393
394static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
395 {
396 .ids = 0x00,
397 .mask = PMX_SSP_CS_MASK,
398 },
399};
400
401struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
402 .name = "plgpio 34 to 36",
403 .modes = pmx_plgpio_34_36_modes,
404 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
405 .enb_on_reset = 1,
406};
407
408static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
409 {
410 .ids = 0x00,
411 .mask = PMX_UART0_MODEM_MASK,
412 },
413};
414
415struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
416 .name = "plgpio 37 to 42",
417 .modes = pmx_plgpio_37_42_modes,
418 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
419 .enb_on_reset = 1,
420};
421
422static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
423 {
424 .ids = 0x00,
425 .mask = PMX_TIMER_1_2_MASK,
426 },
427};
428
429struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
430 .name = "plgpio 43, 44, 47 and 48",
431 .modes = pmx_plgpio_43_44_47_48_modes,
432 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
433 .enb_on_reset = 1,
434};
435
436static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
437 {
438 .ids = 0x00,
439 .mask = PMX_TIMER_3_4_MASK,
440 },
441};
442
443struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
444 .name = "plgpio 45, 46, 49 and 50",
445 .modes = pmx_plgpio_45_46_49_50_modes,
446 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
447 .enb_on_reset = 1,
448};
449#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
450
451/* ssp device registration */ 26/* ssp device registration */
452struct pl022_ssp_controller pl022_plat_data = { 27struct pl022_ssp_controller pl022_plat_data = {
453 .bus_id = 0, 28 .bus_id = 0,
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968115e..2eb4445ddb1 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y += io.o
5obj-y += irq.o 5obj-y += irq.o
6obj-y += clock.o 6obj-y += clock.o
7obj-y += timer.o 7obj-y += timer.o
8obj-y += pinmux.o
9obj-y += fuse.o 8obj-y += fuse.o
10obj-y += pmc.o 9obj-y += pmc.o
11obj-y += flowctrl.o 10obj-y += flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 16obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 18obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 72ae6200352..8351c4c147a 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -46,15 +46,7 @@
46#include "clock.h" 46#include "clock.h"
47#include "devices.h" 47#include "devices.h"
48 48
49void harmony_pinmux_init(void);
50void paz00_pinmux_init(void);
51void seaboard_pinmux_init(void);
52void trimslice_pinmux_init(void);
53void ventana_pinmux_init(void);
54
55struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 49struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
56 OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
57 OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
58 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), 50 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), 51 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), 52 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -94,33 +86,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
94 {} 86 {}
95}; 87};
96 88
97static struct {
98 char *machine;
99 void (*init)(void);
100} pinmux_configs[] = {
101 { "compulab,trimslice", trimslice_pinmux_init },
102 { "nvidia,harmony", harmony_pinmux_init },
103 { "compal,paz00", paz00_pinmux_init },
104 { "nvidia,seaboard", seaboard_pinmux_init },
105 { "nvidia,ventana", ventana_pinmux_init },
106};
107
108static void __init tegra_dt_init(void) 89static void __init tegra_dt_init(void)
109{ 90{
110 int i;
111
112 tegra_clk_init_from_table(tegra_dt_clk_init_table); 91 tegra_clk_init_from_table(tegra_dt_clk_init_table);
113 92
114 for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
115 if (of_machine_is_compatible(pinmux_configs[i].machine)) {
116 pinmux_configs[i].init();
117 break;
118 }
119 }
120
121 WARN(i == ARRAY_SIZE(pinmux_configs),
122 "Unknown platform! Pinmuxing not initialized\n");
123
124 /* 93 /*
125 * Finished with the static registrations now; fill in the missing 94 * Finished with the static registrations now; fill in the missing
126 * devices 95 * devices
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 1af85bccc0f..83d420fbc58 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-harmony-pinmux.c 2 * arch/arm/mach-tegra/board-harmony-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,153 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 19
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-harmony.h" 20#include "board-harmony.h"
26#include "board-pinmux.h" 21#include "board-pinmux.h"
27 22
28static struct tegra_pingroup_config harmony_pinmux[] = { 23static struct pinctrl_map harmony_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 38 TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 41 TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 49 TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
145}; 140 TEGRA_MAP_CONF("ls", up, na),
146 141 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 142 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, 143 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, 144 TEGRA_MAP_CONF("ld21_20", down, na),
150 { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, 145 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TEGRA_GPIO_SD4_CD, .enable = true },
152 { .gpio = TEGRA_GPIO_SD4_WP, .enable = true },
153 { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true },
154 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
155 { .gpio = TEGRA_GPIO_HP_DET, .enable = true },
156 { .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true },
157 { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true },
158}; 146};
159 147
160static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
161 .pgs = harmony_pinmux, 149 .maps = harmony_map,
162 .pg_count = ARRAY_SIZE(harmony_pinmux), 150 .map_count = ARRAY_SIZE(harmony_map),
163 .gpios = gpio_table,
164 .gpio_count = ARRAY_SIZE(gpio_table),
165}; 151};
166 152
167void harmony_pinmux_init(void) 153void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572dcea..6f1111b48e7 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-paz00-pinmux.c 2 * arch/arm/mach-tegra/board-paz00-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> 4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,150 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 19
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-paz00.h" 20#include "board-paz00.h"
26#include "board-pinmux.h" 21#include "board-pinmux.h"
27 22
28static struct tegra_pingroup_config paz00_pinmux[] = { 23static struct pinctrl_map paz00_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 34 TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 107 TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
145}; 140 TEGRA_MAP_CONF("ls", up, na),
146 141 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 142 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, 143 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, 144 TEGRA_MAP_CONF("ld21_20", down, na),
150 { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, 145 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TEGRA_ULPI_RST, .enable = true },
152 { .gpio = TEGRA_WIFI_PWRN, .enable = true },
153 { .gpio = TEGRA_WIFI_RST, .enable = true },
154 { .gpio = TEGRA_WIFI_LED, .enable = true },
155}; 146};
156 147
157static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
158 .pgs = paz00_pinmux, 149 .maps = paz00_map,
159 .pg_count = ARRAY_SIZE(paz00_pinmux), 150 .map_count = ARRAY_SIZE(paz00_map),
160 .gpios = gpio_table,
161 .gpio_count = ARRAY_SIZE(gpio_table),
162}; 151};
163 152
164void paz00_pinmux_init(void) 153void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe979b..a5574c71b93 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,75 +15,59 @@
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/notifier.h> 17#include <linux/notifier.h>
18#include <linux/of.h>
19#include <linux/string.h> 18#include <linux/string.h>
20 19
21#include <mach/gpio-tegra.h>
22#include <mach/pinmux.h>
23
24#include "board-pinmux.h" 20#include "board-pinmux.h"
25#include "devices.h" 21#include "devices.h"
26 22
27struct tegra_board_pinmux_conf *confs[2]; 23unsigned long tegra_pincfg_pullnone_driven[2] = {
28 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
29static void tegra_board_pinmux_setup_gpios(void) 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
30{ 26};
31 int i;
32
33 for (i = 0; i < ARRAY_SIZE(confs); i++) {
34 if (!confs[i])
35 continue;
36
37 tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
38 }
39}
40
41static void tegra_board_pinmux_setup_pinmux(void)
42{
43 int i;
44 27
45 for (i = 0; i < ARRAY_SIZE(confs); i++) { 28unsigned long tegra_pincfg_pullnone_tristate[2] = {
46 if (!confs[i]) 29 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
47 continue; 30 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
31};
48 32
49 tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count); 33unsigned long tegra_pincfg_pullnone_na[1] = {
34 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
35};
50 36
51 if (confs[i]->drives) 37unsigned long tegra_pincfg_pullup_driven[2] = {
52 tegra_drive_pinmux_config_table(confs[i]->drives, 38 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
53 confs[i]->drive_count); 39 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54 } 40};
55}
56 41
57static int tegra_board_pinmux_bus_notify(struct notifier_block *nb, 42unsigned long tegra_pincfg_pullup_tristate[2] = {
58 unsigned long event, void *vdev) 43 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
59{ 44 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
60 static bool had_gpio; 45};
61 static bool had_pinmux;
62 46
63 struct device *dev = vdev; 47unsigned long tegra_pincfg_pullup_na[1] = {
64 const char *devname; 48 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
49};
65 50
66 if (event != BUS_NOTIFY_BOUND_DRIVER) 51unsigned long tegra_pincfg_pulldown_driven[2] = {
67 return NOTIFY_DONE; 52 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
53 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54};
68 55
69 devname = dev_name(dev); 56unsigned long tegra_pincfg_pulldown_tristate[2] = {
57 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
58 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
59};
70 60
71 if (!had_gpio && !strcmp(devname, GPIO_DEV)) { 61unsigned long tegra_pincfg_pulldown_na[1] = {
72 tegra_board_pinmux_setup_gpios(); 62 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
73 had_gpio = true; 63};
74 } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
75 tegra_board_pinmux_setup_pinmux();
76 had_pinmux = true;
77 }
78 64
79 if (had_gpio && had_pinmux) 65unsigned long tegra_pincfg_pullna_driven[1] = {
80 return NOTIFY_STOP_MASK; 66 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
81 else 67};
82 return NOTIFY_DONE;
83}
84 68
85static struct notifier_block nb = { 69unsigned long tegra_pincfg_pullna_tristate[1] = {
86 .notifier_call = tegra_board_pinmux_bus_notify, 70 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
87}; 71};
88 72
89static struct platform_device *devices[] = { 73static struct platform_device *devices[] = {
@@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
94void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 78void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
95 struct tegra_board_pinmux_conf *conf_b) 79 struct tegra_board_pinmux_conf *conf_b)
96{ 80{
97 confs[0] = conf_a; 81 if (conf_a)
98 confs[1] = conf_b; 82 pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
99 83 if (conf_b)
100 bus_register_notifier(&platform_bus_type, &nb); 84 pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
101 85
102 if (!of_machine_is_compatible("nvidia,tegra20")) 86 platform_add_devices(devices, ARRAY_SIZE(devices));
103 platform_add_devices(devices, ARRAY_SIZE(devices));
104} 87}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac73546f5..c5f3f3381e8 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,21 +15,37 @@
15#ifndef __MACH_TEGRA_BOARD_PINMUX_H 15#ifndef __MACH_TEGRA_BOARD_PINMUX_H
16#define __MACH_TEGRA_BOARD_PINMUX_H 16#define __MACH_TEGRA_BOARD_PINMUX_H
17 17
18#define GPIO_DEV "tegra-gpio" 18#include <linux/pinctrl/machine.h>
19#define PINMUX_DEV "tegra-pinmux"
20 19
21struct tegra_pingroup_config; 20#include <mach/pinconf-tegra.h>
22struct tegra_gpio_table;
23 21
24struct tegra_board_pinmux_conf { 22#define PINMUX_DEV "tegra20-pinctrl"
25 struct tegra_pingroup_config *pgs; 23
26 int pg_count; 24#define TEGRA_MAP_MUX(_group_, _function_) \
25 PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
26
27#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
28 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
27 29
28 struct tegra_drive_pingroup_config *drives; 30#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
29 int drive_count; 31 TEGRA_MAP_MUX(_group_, _function_), \
32 TEGRA_MAP_CONF(_group_, _pull_, _drive_)
30 33
31 struct tegra_gpio_table *gpios; 34extern unsigned long tegra_pincfg_pullnone_driven[2];
32 int gpio_count; 35extern unsigned long tegra_pincfg_pullnone_tristate[2];
36extern unsigned long tegra_pincfg_pullnone_na[1];
37extern unsigned long tegra_pincfg_pullup_driven[2];
38extern unsigned long tegra_pincfg_pullup_tristate[2];
39extern unsigned long tegra_pincfg_pullup_na[1];
40extern unsigned long tegra_pincfg_pulldown_driven[2];
41extern unsigned long tegra_pincfg_pulldown_tristate[2];
42extern unsigned long tegra_pincfg_pulldown_na[1];
43extern unsigned long tegra_pincfg_pullna_driven[1];
44extern unsigned long tegra_pincfg_pullna_tristate[1];
45
46struct tegra_board_pinmux_conf {
47 struct pinctrl_map *maps;
48 int map_count;
33}; 49};
34 50
35void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 51void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43a14a..11fc8a568c6 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010,2011 NVIDIA Corporation 2 * Copyright (C) 2010-2012 NVIDIA Corporation
3 * Copyright (C) 2011 Google, Inc. 3 * Copyright (C) 2011 Google, Inc.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
@@ -14,216 +14,176 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 17
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-pinmux.h"
26#include "board-seaboard.h" 18#include "board-seaboard.h"
19#include "board-pinmux.h"
27 20
28#define DEFAULT_DRIVE(_name) \ 21static unsigned long seaboard_pincfg_drive_sdio1[] = {
29 { \ 22 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
30 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ 23 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
31 .hsm = TEGRA_HSM_DISABLE, \ 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
32 .schmitt = TEGRA_SCHMITT_ENABLE, \ 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
33 .drive = TEGRA_DRIVE_DIV_1, \ 26 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
34 .pull_down = TEGRA_PULL_31, \ 27 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
35 .pull_up = TEGRA_PULL_31, \ 28 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
36 .slew_rising = TEGRA_SLEW_SLOWEST, \
37 .slew_falling = TEGRA_SLEW_SLOWEST, \
38 }
39
40static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
41 DEFAULT_DRIVE(SDIO1),
42};
43
44static struct tegra_pingroup_config common_pinmux[] = {
45 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
46 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
47 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
48 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
49 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
50 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
51 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
52 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
53 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
54 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
55 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
56 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
57 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
58 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
59 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
60 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
61 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
62 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
63 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
64 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
65 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
66 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
67 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
68 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
69 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
70 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
71 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
72 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
73 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
74 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
75 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
76 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
77 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
78 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
79 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
80 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
81 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
82 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
83 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
84 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
85 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
86 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
87 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
88 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
89 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
90 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
91 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
92 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
93 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
94 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
95 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
96 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
97 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
98 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
99 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
100 {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
101 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
102 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
103 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
104 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
105 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
106 {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
107 {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
108 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
109 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
110 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
111 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
112 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
113 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
114 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
115 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
116 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
117 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
118 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
119 {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
120 {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
121 {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
122 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
123 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
124 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
125 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
126 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
127 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
128 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
129 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
130 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
131 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
132 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
133 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
134 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
135 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
136 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
137 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
138 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
139 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
140 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
141 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
142 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
143 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
144 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
145 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
146 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
147 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
148};
149
150static struct tegra_pingroup_config seaboard_pinmux[] = {
151 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
152 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
153 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
154 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
155 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
156 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
157 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
158 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
159 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
160 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
161 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
162 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
163 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
164};
165
166static struct tegra_pingroup_config ventana_pinmux[] = {
167 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
168 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
169 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
170 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
171 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
172 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
173 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
174 {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
175 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
176 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
177 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
178 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
179 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
180}; 29};
181 30
182static struct tegra_gpio_table common_gpio_table[] = { 31static struct pinctrl_map common_map[] = {
183 { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, 32 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
184 { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, 33 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
185 { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, 34 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
186 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, 35 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
36 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
37 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
38 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
39 TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
40 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
41 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
42 TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
43 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
44 TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
45 TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
46 TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
47 TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
48 TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
49 TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
50 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
51 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
52 TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
53 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
54 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
55 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
56 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
57 TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
58 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
59 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
60 TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
61 TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
62 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
63 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
64 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
65 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
66 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
67 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
68 TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
69 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
70 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
71 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
72 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
73 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
74 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
75 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
76 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
77 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
78 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
79 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
80 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
81 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
82 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
83 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
84 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
85 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
86 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
87 TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
88 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
89 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
90 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
91 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
92 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
93 TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
94 TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
95 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
96 TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
97 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
98 TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
99 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
100 TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
101 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
102 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
103 TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
104 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
105 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
106 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
107 TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
108 TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
109 TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
110 TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
111 TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
116 TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
117 TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
118 TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
119 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
120 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
121 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
122 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
123 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
124 TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
125 TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
126 TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
127 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
128 TEGRA_MAP_CONF("ck32", none, na),
129 TEGRA_MAP_CONF("ddrc", none, na),
130 TEGRA_MAP_CONF("pmca", none, na),
131 TEGRA_MAP_CONF("pmcb", none, na),
132 TEGRA_MAP_CONF("pmcc", none, na),
133 TEGRA_MAP_CONF("pmcd", none, na),
134 TEGRA_MAP_CONF("pmce", none, na),
135 TEGRA_MAP_CONF("xm2c", none, na),
136 TEGRA_MAP_CONF("xm2d", none, na),
137 TEGRA_MAP_CONF("ls", up, na),
138 TEGRA_MAP_CONF("lc", up, na),
139 TEGRA_MAP_CONF("ld17_0", down, na),
140 TEGRA_MAP_CONF("ld19_18", down, na),
141 TEGRA_MAP_CONF("ld21_20", down, na),
142 TEGRA_MAP_CONF("ld23_22", down, na),
187}; 143};
188 144
189static struct tegra_gpio_table seaboard_gpio_table[] = { 145static struct pinctrl_map seaboard_map[] = {
190 { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, 146 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
191 { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, 147 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
192 { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, 148 TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
193 { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, 149 TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
194 { .gpio = TEGRA_GPIO_USB1, .enable = true }, 150 TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
151 TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
152 TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
153 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
154 TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
155 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
156 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
157 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
195}; 158};
196 159
197static struct tegra_gpio_table ventana_gpio_table[] = { 160static struct pinctrl_map ventana_map[] = {
198 /* hp_det */ 161 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
199 { .gpio = TEGRA_GPIO_PW2, .enable = true }, 162 TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
200 /* int_mic_en */ 163 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
201 { .gpio = TEGRA_GPIO_PX0, .enable = true }, 164 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
202 /* ext_mic_en */ 165 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
203 { .gpio = TEGRA_GPIO_PX1, .enable = true }, 166 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
167 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
168 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
169 TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
170 TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
171 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
204}; 172};
205 173
206static struct tegra_board_pinmux_conf common_conf = { 174static struct tegra_board_pinmux_conf common_conf = {
207 .pgs = common_pinmux, 175 .maps = common_map,
208 .pg_count = ARRAY_SIZE(common_pinmux), 176 .map_count = ARRAY_SIZE(common_map),
209 .gpios = common_gpio_table,
210 .gpio_count = ARRAY_SIZE(common_gpio_table),
211}; 177};
212 178
213static struct tegra_board_pinmux_conf seaboard_conf = { 179static struct tegra_board_pinmux_conf seaboard_conf = {
214 .pgs = seaboard_pinmux, 180 .maps = seaboard_map,
215 .pg_count = ARRAY_SIZE(seaboard_pinmux), 181 .map_count = ARRAY_SIZE(seaboard_map),
216 .drives = seaboard_drive_pinmux,
217 .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
218 .gpios = seaboard_gpio_table,
219 .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
220}; 182};
221 183
222static struct tegra_board_pinmux_conf ventana_conf = { 184static struct tegra_board_pinmux_conf ventana_conf = {
223 .pgs = ventana_pinmux, 185 .maps = ventana_map,
224 .pg_count = ARRAY_SIZE(ventana_pinmux), 186 .map_count = ARRAY_SIZE(ventana_map),
225 .gpios = ventana_gpio_table,
226 .gpio_count = ARRAY_SIZE(ventana_gpio_table),
227}; 187};
228 188
229void seaboard_pinmux_init(void) 189void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index d669847f048..a0184fb4422 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -24,6 +24,7 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/gpio_keys.h> 26#include <linux/gpio_keys.h>
27#include <linux/platform_data/tegra_usb.h>
27 28
28#include <sound/wm8903.h> 29#include <sound/wm8903.h>
29 30
@@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
186 187
187static int seaboard_ehci_init(void) 188static int seaboard_ehci_init(void)
188{ 189{
189 int gpio_status; 190 struct tegra_ehci_platform_data *pdata;
190 191
191 gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1"); 192 pdata = tegra_ehci1_device.dev.platform_data;
192 if (gpio_status < 0) { 193 pdata->vbus_gpio = TEGRA_GPIO_USB1;
193 pr_err("VBUS_USB1 request GPIO FAILED\n");
194 WARN_ON(1);
195 }
196
197 gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
198 if (gpio_status < 0) {
199 pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
200 WARN_ON(1);
201 }
202 gpio_set_value(TEGRA_GPIO_USB1, 1);
203 194
204 platform_device_register(&tegra_ehci1_device); 195 platform_device_register(&tegra_ehci1_device);
205 platform_device_register(&tegra_ehci3_device); 196 platform_device_register(&tegra_ehci3_device);
@@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
209 200
210static void __init seaboard_i2c_init(void) 201static void __init seaboard_i2c_init(void)
211{ 202{
212 gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
213 gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
214
215 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ); 203 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
216 i2c_register_board_info(0, &isl29018_device, 1); 204 i2c_register_board_info(0, &isl29018_device, 1);
217 205
@@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
261 debug_uart_platform_data[0].irq = INT_UARTB; 249 debug_uart_platform_data[0].irq = INT_UARTB;
262 250
263 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE; 251 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
264 tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
265 252
266 seaboard_common_init(); 253 seaboard_common_init();
267 254
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be57cb..7b39511c0d4 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-trimslice-pinmux.c 2 * arch/arm/mach-tegra/board-trimslice-pinmux.c
3 * 3 *
4 * Copyright (C) 2011 CompuLab, Ltd. 4 * Copyright (C) 2011 CompuLab, Ltd.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -13,150 +14,139 @@
13 * GNU General Public License for more details. 14 * GNU General Public License for more details.
14 * 15 *
15 */ 16 */
16#include <linux/gpio.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of.h>
20 18
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-pinmux.h"
26#include "board-trimslice.h" 19#include "board-trimslice.h"
20#include "board-pinmux.h"
27 21
28static struct tegra_pingroup_config trimslice_pinmux[] = { 22static struct pinctrl_map trimslice_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 23 TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 25 TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 26 TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 27 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 29 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 32 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 33 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 36 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 37 TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 42 TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 44 TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 47 TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 51 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 53 TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 56 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 57 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 58 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 59 TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 60 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 61 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 62 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 80 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 88 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 91 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 93 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 97 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 98 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 99 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 101 TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 103 TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 106 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 108 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 112 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 113 TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2d", none, na),
145}; 139 TEGRA_MAP_CONF("ls", up, na),
146 140 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 141 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ 142 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ 143 TEGRA_MAP_CONF("ld21_20", down, na),
150 144 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
152 { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
153}; 145};
154 146
155static struct tegra_board_pinmux_conf conf = { 147static struct tegra_board_pinmux_conf conf = {
156 .pgs = trimslice_pinmux, 148 .maps = trimslice_map,
157 .pg_count = ARRAY_SIZE(trimslice_pinmux), 149 .map_count = ARRAY_SIZE(trimslice_map),
158 .gpios = gpio_table,
159 .gpio_count = ARRAY_SIZE(gpio_table),
160}; 150};
161 151
162void trimslice_pinmux_init(void) 152void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cd52820a3e3..f6f5b6a1132 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -25,6 +25,7 @@
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/platform_data/tegra_usb.h>
28 29
29#include <asm/hardware/gic.h> 30#include <asm/hardware/gic.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
111 112
112static void trimslice_usb_init(void) 113static void trimslice_usb_init(void)
113{ 114{
114 int err; 115 struct tegra_ehci_platform_data *pdata;
115 116
116 platform_device_register(&tegra_ehci3_device); 117 pdata = tegra_ehci1_device.dev.platform_data;
118 pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
117 119
120 platform_device_register(&tegra_ehci3_device);
118 platform_device_register(&tegra_ehci2_device); 121 platform_device_register(&tegra_ehci2_device);
119
120 err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
121 "usb1mode");
122 if (err) {
123 pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
124 return;
125 }
126
127 platform_device_register(&tegra_ehci1_device); 122 platform_device_register(&tegra_ehci1_device);
128} 123}
129 124
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 5f6b867e20b..bd3035e0cea 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
110}; 110};
111 111
112struct platform_device tegra_pinmux_device = { 112struct platform_device tegra_pinmux_device = {
113 .name = "tegra-pinmux", 113 .name = "tegra20-pinctrl",
114 .id = -1, 114 .id = -1,
115 .resource = pinmux_resource, 115 .resource = pinmux_resource,
116 .num_resources = ARRAY_SIZE(pinmux_resource), 116 .num_resources = ARRAY_SIZE(pinmux_resource),
@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
448struct tegra_ehci_platform_data tegra_ehci1_pdata = { 448struct tegra_ehci_platform_data tegra_ehci1_pdata = {
449 .operating_mode = TEGRA_USB_OTG, 449 .operating_mode = TEGRA_USB_OTG,
450 .power_down_on_bus_suspend = 1, 450 .power_down_on_bus_suspend = 1,
451 .vbus_gpio = -1,
451}; 452};
452 453
453struct tegra_ehci_platform_data tegra_ehci2_pdata = { 454struct tegra_ehci_platform_data tegra_ehci2_pdata = {
454 .phy_config = &tegra_ehci2_ulpi_phy_config, 455 .phy_config = &tegra_ehci2_ulpi_phy_config,
455 .operating_mode = TEGRA_USB_HOST, 456 .operating_mode = TEGRA_USB_HOST,
456 .power_down_on_bus_suspend = 1, 457 .power_down_on_bus_suspend = 1,
458 .vbus_gpio = -1,
457}; 459};
458 460
459struct tegra_ehci_platform_data tegra_ehci3_pdata = { 461struct tegra_ehci_platform_data tegra_ehci3_pdata = {
460 .operating_mode = TEGRA_USB_HOST, 462 .operating_mode = TEGRA_USB_HOST,
461 .power_down_on_bus_suspend = 1, 463 .power_down_on_bus_suspend = 1,
464 .vbus_gpio = -1,
462}; 465};
463 466
464static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); 467static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820555e..a978b3cc3a8 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
25 25
26#define TEGRA_NR_GPIOS INT_GPIO_NR 26#define TEGRA_NR_GPIOS INT_GPIO_NR
27 27
28struct tegra_gpio_table {
29 int gpio; /* GPIO number */
30 bool enable; /* Enable for GPIO at init? */
31};
32
33void tegra_gpio_config(struct tegra_gpio_table *table, int num);
34void tegra_gpio_enable(int gpio);
35void tegra_gpio_disable(int gpio);
36
37#endif 28#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1dbab1..00000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
18#define __MACH_TEGRA_PINMUX_TEGRA20_H
19
20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0,
22 TEGRA_PINGROUP_ATB,
23 TEGRA_PINGROUP_ATC,
24 TEGRA_PINGROUP_ATD,
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140
141enum tegra_drive_pingroup {
142 TEGRA_DRIVE_PINGROUP_AO1 = 0,
143 TEGRA_DRIVE_PINGROUP_AO2,
144 TEGRA_DRIVE_PINGROUP_AT1,
145 TEGRA_DRIVE_PINGROUP_AT2,
146 TEGRA_DRIVE_PINGROUP_CDEV1,
147 TEGRA_DRIVE_PINGROUP_CDEV2,
148 TEGRA_DRIVE_PINGROUP_CSUS,
149 TEGRA_DRIVE_PINGROUP_DAP1,
150 TEGRA_DRIVE_PINGROUP_DAP2,
151 TEGRA_DRIVE_PINGROUP_DAP3,
152 TEGRA_DRIVE_PINGROUP_DAP4,
153 TEGRA_DRIVE_PINGROUP_DBG,
154 TEGRA_DRIVE_PINGROUP_LCD1,
155 TEGRA_DRIVE_PINGROUP_LCD2,
156 TEGRA_DRIVE_PINGROUP_SDMMC2,
157 TEGRA_DRIVE_PINGROUP_SDMMC3,
158 TEGRA_DRIVE_PINGROUP_SPI,
159 TEGRA_DRIVE_PINGROUP_UAA,
160 TEGRA_DRIVE_PINGROUP_UAB,
161 TEGRA_DRIVE_PINGROUP_UART2,
162 TEGRA_DRIVE_PINGROUP_UART3,
163 TEGRA_DRIVE_PINGROUP_VI1,
164 TEGRA_DRIVE_PINGROUP_VI2,
165 TEGRA_DRIVE_PINGROUP_XM2A,
166 TEGRA_DRIVE_PINGROUP_XM2C,
167 TEGRA_DRIVE_PINGROUP_XM2D,
168 TEGRA_DRIVE_PINGROUP_XM2CLK,
169 TEGRA_DRIVE_PINGROUP_MEMCOMP,
170 TEGRA_DRIVE_PINGROUP_SDIO1,
171 TEGRA_DRIVE_PINGROUP_CRT,
172 TEGRA_DRIVE_PINGROUP_DDC,
173 TEGRA_DRIVE_PINGROUP_GMA,
174 TEGRA_DRIVE_PINGROUP_GMB,
175 TEGRA_DRIVE_PINGROUP_GMC,
176 TEGRA_DRIVE_PINGROUP_GMD,
177 TEGRA_DRIVE_PINGROUP_GME,
178 TEGRA_DRIVE_PINGROUP_OWR,
179 TEGRA_DRIVE_PINGROUP_UAD,
180 TEGRA_MAX_DRIVE_PINGROUP,
181};
182
183#endif
184
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3eb2df..00000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
19#define __MACH_TEGRA_PINMUX_TEGRA30_H
20
21enum tegra_pingroup {
22 TEGRA_PINGROUP_ULPI_DATA0 = 0,
23 TEGRA_PINGROUP_ULPI_DATA1,
24 TEGRA_PINGROUP_ULPI_DATA2,
25 TEGRA_PINGROUP_ULPI_DATA3,
26 TEGRA_PINGROUP_ULPI_DATA4,
27 TEGRA_PINGROUP_ULPI_DATA5,
28 TEGRA_PINGROUP_ULPI_DATA6,
29 TEGRA_PINGROUP_ULPI_DATA7,
30 TEGRA_PINGROUP_ULPI_CLK,
31 TEGRA_PINGROUP_ULPI_DIR,
32 TEGRA_PINGROUP_ULPI_NXT,
33 TEGRA_PINGROUP_ULPI_STP,
34 TEGRA_PINGROUP_DAP3_FS,
35 TEGRA_PINGROUP_DAP3_DIN,
36 TEGRA_PINGROUP_DAP3_DOUT,
37 TEGRA_PINGROUP_DAP3_SCLK,
38 TEGRA_PINGROUP_GPIO_PV0,
39 TEGRA_PINGROUP_GPIO_PV1,
40 TEGRA_PINGROUP_SDMMC1_CLK,
41 TEGRA_PINGROUP_SDMMC1_CMD,
42 TEGRA_PINGROUP_SDMMC1_DAT3,
43 TEGRA_PINGROUP_SDMMC1_DAT2,
44 TEGRA_PINGROUP_SDMMC1_DAT1,
45 TEGRA_PINGROUP_SDMMC1_DAT0,
46 TEGRA_PINGROUP_GPIO_PV2,
47 TEGRA_PINGROUP_GPIO_PV3,
48 TEGRA_PINGROUP_CLK2_OUT,
49 TEGRA_PINGROUP_CLK2_REQ,
50 TEGRA_PINGROUP_LCD_PWR1,
51 TEGRA_PINGROUP_LCD_PWR2,
52 TEGRA_PINGROUP_LCD_SDIN,
53 TEGRA_PINGROUP_LCD_SDOUT,
54 TEGRA_PINGROUP_LCD_WR_N,
55 TEGRA_PINGROUP_LCD_CS0_N,
56 TEGRA_PINGROUP_LCD_DC0,
57 TEGRA_PINGROUP_LCD_SCK,
58 TEGRA_PINGROUP_LCD_PWR0,
59 TEGRA_PINGROUP_LCD_PCLK,
60 TEGRA_PINGROUP_LCD_DE,
61 TEGRA_PINGROUP_LCD_HSYNC,
62 TEGRA_PINGROUP_LCD_VSYNC,
63 TEGRA_PINGROUP_LCD_D0,
64 TEGRA_PINGROUP_LCD_D1,
65 TEGRA_PINGROUP_LCD_D2,
66 TEGRA_PINGROUP_LCD_D3,
67 TEGRA_PINGROUP_LCD_D4,
68 TEGRA_PINGROUP_LCD_D5,
69 TEGRA_PINGROUP_LCD_D6,
70 TEGRA_PINGROUP_LCD_D7,
71 TEGRA_PINGROUP_LCD_D8,
72 TEGRA_PINGROUP_LCD_D9,
73 TEGRA_PINGROUP_LCD_D10,
74 TEGRA_PINGROUP_LCD_D11,
75 TEGRA_PINGROUP_LCD_D12,
76 TEGRA_PINGROUP_LCD_D13,
77 TEGRA_PINGROUP_LCD_D14,
78 TEGRA_PINGROUP_LCD_D15,
79 TEGRA_PINGROUP_LCD_D16,
80 TEGRA_PINGROUP_LCD_D17,
81 TEGRA_PINGROUP_LCD_D18,
82 TEGRA_PINGROUP_LCD_D19,
83 TEGRA_PINGROUP_LCD_D20,
84 TEGRA_PINGROUP_LCD_D21,
85 TEGRA_PINGROUP_LCD_D22,
86 TEGRA_PINGROUP_LCD_D23,
87 TEGRA_PINGROUP_LCD_CS1_N,
88 TEGRA_PINGROUP_LCD_M1,
89 TEGRA_PINGROUP_LCD_DC1,
90 TEGRA_PINGROUP_HDMI_INT,
91 TEGRA_PINGROUP_DDC_SCL,
92 TEGRA_PINGROUP_DDC_SDA,
93 TEGRA_PINGROUP_CRT_HSYNC,
94 TEGRA_PINGROUP_CRT_VSYNC,
95 TEGRA_PINGROUP_VI_D0,
96 TEGRA_PINGROUP_VI_D1,
97 TEGRA_PINGROUP_VI_D2,
98 TEGRA_PINGROUP_VI_D3,
99 TEGRA_PINGROUP_VI_D4,
100 TEGRA_PINGROUP_VI_D5,
101 TEGRA_PINGROUP_VI_D6,
102 TEGRA_PINGROUP_VI_D7,
103 TEGRA_PINGROUP_VI_D8,
104 TEGRA_PINGROUP_VI_D9,
105 TEGRA_PINGROUP_VI_D10,
106 TEGRA_PINGROUP_VI_D11,
107 TEGRA_PINGROUP_VI_PCLK,
108 TEGRA_PINGROUP_VI_MCLK,
109 TEGRA_PINGROUP_VI_VSYNC,
110 TEGRA_PINGROUP_VI_HSYNC,
111 TEGRA_PINGROUP_UART2_RXD,
112 TEGRA_PINGROUP_UART2_TXD,
113 TEGRA_PINGROUP_UART2_RTS_N,
114 TEGRA_PINGROUP_UART2_CTS_N,
115 TEGRA_PINGROUP_UART3_TXD,
116 TEGRA_PINGROUP_UART3_RXD,
117 TEGRA_PINGROUP_UART3_CTS_N,
118 TEGRA_PINGROUP_UART3_RTS_N,
119 TEGRA_PINGROUP_GPIO_PU0,
120 TEGRA_PINGROUP_GPIO_PU1,
121 TEGRA_PINGROUP_GPIO_PU2,
122 TEGRA_PINGROUP_GPIO_PU3,
123 TEGRA_PINGROUP_GPIO_PU4,
124 TEGRA_PINGROUP_GPIO_PU5,
125 TEGRA_PINGROUP_GPIO_PU6,
126 TEGRA_PINGROUP_GEN1_I2C_SDA,
127 TEGRA_PINGROUP_GEN1_I2C_SCL,
128 TEGRA_PINGROUP_DAP4_FS,
129 TEGRA_PINGROUP_DAP4_DIN,
130 TEGRA_PINGROUP_DAP4_DOUT,
131 TEGRA_PINGROUP_DAP4_SCLK,
132 TEGRA_PINGROUP_CLK3_OUT,
133 TEGRA_PINGROUP_CLK3_REQ,
134 TEGRA_PINGROUP_GMI_WP_N,
135 TEGRA_PINGROUP_GMI_IORDY,
136 TEGRA_PINGROUP_GMI_WAIT,
137 TEGRA_PINGROUP_GMI_ADV_N,
138 TEGRA_PINGROUP_GMI_CLK,
139 TEGRA_PINGROUP_GMI_CS0_N,
140 TEGRA_PINGROUP_GMI_CS1_N,
141 TEGRA_PINGROUP_GMI_CS2_N,
142 TEGRA_PINGROUP_GMI_CS3_N,
143 TEGRA_PINGROUP_GMI_CS4_N,
144 TEGRA_PINGROUP_GMI_CS6_N,
145 TEGRA_PINGROUP_GMI_CS7_N,
146 TEGRA_PINGROUP_GMI_AD0,
147 TEGRA_PINGROUP_GMI_AD1,
148 TEGRA_PINGROUP_GMI_AD2,
149 TEGRA_PINGROUP_GMI_AD3,
150 TEGRA_PINGROUP_GMI_AD4,
151 TEGRA_PINGROUP_GMI_AD5,
152 TEGRA_PINGROUP_GMI_AD6,
153 TEGRA_PINGROUP_GMI_AD7,
154 TEGRA_PINGROUP_GMI_AD8,
155 TEGRA_PINGROUP_GMI_AD9,
156 TEGRA_PINGROUP_GMI_AD10,
157 TEGRA_PINGROUP_GMI_AD11,
158 TEGRA_PINGROUP_GMI_AD12,
159 TEGRA_PINGROUP_GMI_AD13,
160 TEGRA_PINGROUP_GMI_AD14,
161 TEGRA_PINGROUP_GMI_AD15,
162 TEGRA_PINGROUP_GMI_A16,
163 TEGRA_PINGROUP_GMI_A17,
164 TEGRA_PINGROUP_GMI_A18,
165 TEGRA_PINGROUP_GMI_A19,
166 TEGRA_PINGROUP_GMI_WR_N,
167 TEGRA_PINGROUP_GMI_OE_N,
168 TEGRA_PINGROUP_GMI_DQS,
169 TEGRA_PINGROUP_GMI_RST_N,
170 TEGRA_PINGROUP_GEN2_I2C_SCL,
171 TEGRA_PINGROUP_GEN2_I2C_SDA,
172 TEGRA_PINGROUP_SDMMC4_CLK,
173 TEGRA_PINGROUP_SDMMC4_CMD,
174 TEGRA_PINGROUP_SDMMC4_DAT0,
175 TEGRA_PINGROUP_SDMMC4_DAT1,
176 TEGRA_PINGROUP_SDMMC4_DAT2,
177 TEGRA_PINGROUP_SDMMC4_DAT3,
178 TEGRA_PINGROUP_SDMMC4_DAT4,
179 TEGRA_PINGROUP_SDMMC4_DAT5,
180 TEGRA_PINGROUP_SDMMC4_DAT6,
181 TEGRA_PINGROUP_SDMMC4_DAT7,
182 TEGRA_PINGROUP_SDMMC4_RST_N,
183 TEGRA_PINGROUP_CAM_MCLK,
184 TEGRA_PINGROUP_GPIO_PCC1,
185 TEGRA_PINGROUP_GPIO_PBB0,
186 TEGRA_PINGROUP_CAM_I2C_SCL,
187 TEGRA_PINGROUP_CAM_I2C_SDA,
188 TEGRA_PINGROUP_GPIO_PBB3,
189 TEGRA_PINGROUP_GPIO_PBB4,
190 TEGRA_PINGROUP_GPIO_PBB5,
191 TEGRA_PINGROUP_GPIO_PBB6,
192 TEGRA_PINGROUP_GPIO_PBB7,
193 TEGRA_PINGROUP_GPIO_PCC2,
194 TEGRA_PINGROUP_JTAG_RTCK,
195 TEGRA_PINGROUP_PWR_I2C_SCL,
196 TEGRA_PINGROUP_PWR_I2C_SDA,
197 TEGRA_PINGROUP_KB_ROW0,
198 TEGRA_PINGROUP_KB_ROW1,
199 TEGRA_PINGROUP_KB_ROW2,
200 TEGRA_PINGROUP_KB_ROW3,
201 TEGRA_PINGROUP_KB_ROW4,
202 TEGRA_PINGROUP_KB_ROW5,
203 TEGRA_PINGROUP_KB_ROW6,
204 TEGRA_PINGROUP_KB_ROW7,
205 TEGRA_PINGROUP_KB_ROW8,
206 TEGRA_PINGROUP_KB_ROW9,
207 TEGRA_PINGROUP_KB_ROW10,
208 TEGRA_PINGROUP_KB_ROW11,
209 TEGRA_PINGROUP_KB_ROW12,
210 TEGRA_PINGROUP_KB_ROW13,
211 TEGRA_PINGROUP_KB_ROW14,
212 TEGRA_PINGROUP_KB_ROW15,
213 TEGRA_PINGROUP_KB_COL0,
214 TEGRA_PINGROUP_KB_COL1,
215 TEGRA_PINGROUP_KB_COL2,
216 TEGRA_PINGROUP_KB_COL3,
217 TEGRA_PINGROUP_KB_COL4,
218 TEGRA_PINGROUP_KB_COL5,
219 TEGRA_PINGROUP_KB_COL6,
220 TEGRA_PINGROUP_KB_COL7,
221 TEGRA_PINGROUP_CLK_32K_OUT,
222 TEGRA_PINGROUP_SYS_CLK_REQ,
223 TEGRA_PINGROUP_CORE_PWR_REQ,
224 TEGRA_PINGROUP_CPU_PWR_REQ,
225 TEGRA_PINGROUP_PWR_INT_N,
226 TEGRA_PINGROUP_CLK_32K_IN,
227 TEGRA_PINGROUP_OWR,
228 TEGRA_PINGROUP_DAP1_FS,
229 TEGRA_PINGROUP_DAP1_DIN,
230 TEGRA_PINGROUP_DAP1_DOUT,
231 TEGRA_PINGROUP_DAP1_SCLK,
232 TEGRA_PINGROUP_CLK1_REQ,
233 TEGRA_PINGROUP_CLK1_OUT,
234 TEGRA_PINGROUP_SPDIF_IN,
235 TEGRA_PINGROUP_SPDIF_OUT,
236 TEGRA_PINGROUP_DAP2_FS,
237 TEGRA_PINGROUP_DAP2_DIN,
238 TEGRA_PINGROUP_DAP2_DOUT,
239 TEGRA_PINGROUP_DAP2_SCLK,
240 TEGRA_PINGROUP_SPI2_MOSI,
241 TEGRA_PINGROUP_SPI2_MISO,
242 TEGRA_PINGROUP_SPI2_CS0_N,
243 TEGRA_PINGROUP_SPI2_SCK,
244 TEGRA_PINGROUP_SPI1_MOSI,
245 TEGRA_PINGROUP_SPI1_SCK,
246 TEGRA_PINGROUP_SPI1_CS0_N,
247 TEGRA_PINGROUP_SPI1_MISO,
248 TEGRA_PINGROUP_SPI2_CS1_N,
249 TEGRA_PINGROUP_SPI2_CS2_N,
250 TEGRA_PINGROUP_SDMMC3_CLK,
251 TEGRA_PINGROUP_SDMMC3_CMD,
252 TEGRA_PINGROUP_SDMMC3_DAT0,
253 TEGRA_PINGROUP_SDMMC3_DAT1,
254 TEGRA_PINGROUP_SDMMC3_DAT2,
255 TEGRA_PINGROUP_SDMMC3_DAT3,
256 TEGRA_PINGROUP_SDMMC3_DAT4,
257 TEGRA_PINGROUP_SDMMC3_DAT5,
258 TEGRA_PINGROUP_SDMMC3_DAT6,
259 TEGRA_PINGROUP_SDMMC3_DAT7,
260 TEGRA_PINGROUP_PEX_L0_PRSNT_N,
261 TEGRA_PINGROUP_PEX_L0_RST_N,
262 TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
263 TEGRA_PINGROUP_PEX_WAKE_N,
264 TEGRA_PINGROUP_PEX_L1_PRSNT_N,
265 TEGRA_PINGROUP_PEX_L1_RST_N,
266 TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
267 TEGRA_PINGROUP_PEX_L2_PRSNT_N,
268 TEGRA_PINGROUP_PEX_L2_RST_N,
269 TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
270 TEGRA_PINGROUP_HDMI_CEC,
271 TEGRA_MAX_PINGROUP,
272};
273
274enum tegra_drive_pingroup {
275 TEGRA_DRIVE_PINGROUP_AO1 = 0,
276 TEGRA_DRIVE_PINGROUP_AO2,
277 TEGRA_DRIVE_PINGROUP_AT1,
278 TEGRA_DRIVE_PINGROUP_AT2,
279 TEGRA_DRIVE_PINGROUP_AT3,
280 TEGRA_DRIVE_PINGROUP_AT4,
281 TEGRA_DRIVE_PINGROUP_AT5,
282 TEGRA_DRIVE_PINGROUP_CDEV1,
283 TEGRA_DRIVE_PINGROUP_CDEV2,
284 TEGRA_DRIVE_PINGROUP_CSUS,
285 TEGRA_DRIVE_PINGROUP_DAP1,
286 TEGRA_DRIVE_PINGROUP_DAP2,
287 TEGRA_DRIVE_PINGROUP_DAP3,
288 TEGRA_DRIVE_PINGROUP_DAP4,
289 TEGRA_DRIVE_PINGROUP_DBG,
290 TEGRA_DRIVE_PINGROUP_LCD1,
291 TEGRA_DRIVE_PINGROUP_LCD2,
292 TEGRA_DRIVE_PINGROUP_SDIO2,
293 TEGRA_DRIVE_PINGROUP_SDIO3,
294 TEGRA_DRIVE_PINGROUP_SPI,
295 TEGRA_DRIVE_PINGROUP_UAA,
296 TEGRA_DRIVE_PINGROUP_UAB,
297 TEGRA_DRIVE_PINGROUP_UART2,
298 TEGRA_DRIVE_PINGROUP_UART3,
299 TEGRA_DRIVE_PINGROUP_VI1,
300 TEGRA_DRIVE_PINGROUP_SDIO1,
301 TEGRA_DRIVE_PINGROUP_CRT,
302 TEGRA_DRIVE_PINGROUP_DDC,
303 TEGRA_DRIVE_PINGROUP_GMA,
304 TEGRA_DRIVE_PINGROUP_GMB,
305 TEGRA_DRIVE_PINGROUP_GMC,
306 TEGRA_DRIVE_PINGROUP_GMD,
307 TEGRA_DRIVE_PINGROUP_GME,
308 TEGRA_DRIVE_PINGROUP_GMF,
309 TEGRA_DRIVE_PINGROUP_GMG,
310 TEGRA_DRIVE_PINGROUP_GMH,
311 TEGRA_DRIVE_PINGROUP_OWR,
312 TEGRA_DRIVE_PINGROUP_UAD,
313 TEGRA_DRIVE_PINGROUP_GPV,
314 TEGRA_DRIVE_PINGROUP_DEV3,
315 TEGRA_DRIVE_PINGROUP_CEC,
316 TEGRA_MAX_DRIVE_PINGROUP,
317};
318
319#endif
320
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f1792c8f..00000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_H
19#define __MACH_TEGRA_PINMUX_H
20
21enum tegra_mux_func {
22 TEGRA_MUX_RSVD = 0x8000,
23 TEGRA_MUX_RSVD1 = 0x8000,
24 TEGRA_MUX_RSVD2 = 0x8001,
25 TEGRA_MUX_RSVD3 = 0x8002,
26 TEGRA_MUX_RSVD4 = 0x8003,
27 TEGRA_MUX_INVALID = 0x4000,
28 TEGRA_MUX_NONE = -1,
29 TEGRA_MUX_AHB_CLK,
30 TEGRA_MUX_APB_CLK,
31 TEGRA_MUX_AUDIO_SYNC,
32 TEGRA_MUX_CRT,
33 TEGRA_MUX_DAP1,
34 TEGRA_MUX_DAP2,
35 TEGRA_MUX_DAP3,
36 TEGRA_MUX_DAP4,
37 TEGRA_MUX_DAP5,
38 TEGRA_MUX_DISPLAYA,
39 TEGRA_MUX_DISPLAYB,
40 TEGRA_MUX_EMC_TEST0_DLL,
41 TEGRA_MUX_EMC_TEST1_DLL,
42 TEGRA_MUX_GMI,
43 TEGRA_MUX_GMI_INT,
44 TEGRA_MUX_HDMI,
45 TEGRA_MUX_I2C,
46 TEGRA_MUX_I2C2,
47 TEGRA_MUX_I2C3,
48 TEGRA_MUX_IDE,
49 TEGRA_MUX_IRDA,
50 TEGRA_MUX_KBC,
51 TEGRA_MUX_MIO,
52 TEGRA_MUX_MIPI_HS,
53 TEGRA_MUX_NAND,
54 TEGRA_MUX_OSC,
55 TEGRA_MUX_OWR,
56 TEGRA_MUX_PCIE,
57 TEGRA_MUX_PLLA_OUT,
58 TEGRA_MUX_PLLC_OUT1,
59 TEGRA_MUX_PLLM_OUT1,
60 TEGRA_MUX_PLLP_OUT2,
61 TEGRA_MUX_PLLP_OUT3,
62 TEGRA_MUX_PLLP_OUT4,
63 TEGRA_MUX_PWM,
64 TEGRA_MUX_PWR_INTR,
65 TEGRA_MUX_PWR_ON,
66 TEGRA_MUX_RTCK,
67 TEGRA_MUX_SDIO1,
68 TEGRA_MUX_SDIO2,
69 TEGRA_MUX_SDIO3,
70 TEGRA_MUX_SDIO4,
71 TEGRA_MUX_SFLASH,
72 TEGRA_MUX_SPDIF,
73 TEGRA_MUX_SPI1,
74 TEGRA_MUX_SPI2,
75 TEGRA_MUX_SPI2_ALT,
76 TEGRA_MUX_SPI3,
77 TEGRA_MUX_SPI4,
78 TEGRA_MUX_TRACE,
79 TEGRA_MUX_TWC,
80 TEGRA_MUX_UARTA,
81 TEGRA_MUX_UARTB,
82 TEGRA_MUX_UARTC,
83 TEGRA_MUX_UARTD,
84 TEGRA_MUX_UARTE,
85 TEGRA_MUX_ULPI,
86 TEGRA_MUX_VI,
87 TEGRA_MUX_VI_SENSOR_CLK,
88 TEGRA_MUX_XIO,
89 TEGRA_MUX_BLINK,
90 TEGRA_MUX_CEC,
91 TEGRA_MUX_CLK12,
92 TEGRA_MUX_DAP,
93 TEGRA_MUX_DAPSDMMC2,
94 TEGRA_MUX_DDR,
95 TEGRA_MUX_DEV3,
96 TEGRA_MUX_DTV,
97 TEGRA_MUX_VI_ALT1,
98 TEGRA_MUX_VI_ALT2,
99 TEGRA_MUX_VI_ALT3,
100 TEGRA_MUX_EMC_DLL,
101 TEGRA_MUX_EXTPERIPH1,
102 TEGRA_MUX_EXTPERIPH2,
103 TEGRA_MUX_EXTPERIPH3,
104 TEGRA_MUX_GMI_ALT,
105 TEGRA_MUX_HDA,
106 TEGRA_MUX_HSI,
107 TEGRA_MUX_I2C4,
108 TEGRA_MUX_I2C5,
109 TEGRA_MUX_I2CPWR,
110 TEGRA_MUX_I2S0,
111 TEGRA_MUX_I2S1,
112 TEGRA_MUX_I2S2,
113 TEGRA_MUX_I2S3,
114 TEGRA_MUX_I2S4,
115 TEGRA_MUX_NAND_ALT,
116 TEGRA_MUX_POPSDIO4,
117 TEGRA_MUX_POPSDMMC4,
118 TEGRA_MUX_PWM0,
119 TEGRA_MUX_PWM1,
120 TEGRA_MUX_PWM2,
121 TEGRA_MUX_PWM3,
122 TEGRA_MUX_SATA,
123 TEGRA_MUX_SPI5,
124 TEGRA_MUX_SPI6,
125 TEGRA_MUX_SYSCLK,
126 TEGRA_MUX_VGP1,
127 TEGRA_MUX_VGP2,
128 TEGRA_MUX_VGP3,
129 TEGRA_MUX_VGP4,
130 TEGRA_MUX_VGP5,
131 TEGRA_MUX_VGP6,
132 TEGRA_MUX_SAFE,
133 TEGRA_MAX_MUX,
134};
135
136enum tegra_pullupdown {
137 TEGRA_PUPD_NORMAL = 0,
138 TEGRA_PUPD_PULL_DOWN,
139 TEGRA_PUPD_PULL_UP,
140};
141
142enum tegra_tristate {
143 TEGRA_TRI_NORMAL = 0,
144 TEGRA_TRI_TRISTATE = 1,
145};
146
147enum tegra_pin_io {
148 TEGRA_PIN_OUTPUT = 0,
149 TEGRA_PIN_INPUT = 1,
150};
151
152enum tegra_vddio {
153 TEGRA_VDDIO_BB = 0,
154 TEGRA_VDDIO_LCD,
155 TEGRA_VDDIO_VI,
156 TEGRA_VDDIO_UART,
157 TEGRA_VDDIO_DDR,
158 TEGRA_VDDIO_NAND,
159 TEGRA_VDDIO_SYS,
160 TEGRA_VDDIO_AUDIO,
161 TEGRA_VDDIO_SD,
162 TEGRA_VDDIO_CAM,
163 TEGRA_VDDIO_GMI,
164 TEGRA_VDDIO_PEXCTL,
165 TEGRA_VDDIO_SDMMC1,
166 TEGRA_VDDIO_SDMMC3,
167 TEGRA_VDDIO_SDMMC4,
168};
169
170struct tegra_pingroup_config {
171 int pingroup;
172 enum tegra_mux_func func;
173 enum tegra_pullupdown pupd;
174 enum tegra_tristate tristate;
175};
176
177enum tegra_slew {
178 TEGRA_SLEW_FASTEST = 0,
179 TEGRA_SLEW_FAST,
180 TEGRA_SLEW_SLOW,
181 TEGRA_SLEW_SLOWEST,
182 TEGRA_MAX_SLEW,
183};
184
185enum tegra_pull_strength {
186 TEGRA_PULL_0 = 0,
187 TEGRA_PULL_1,
188 TEGRA_PULL_2,
189 TEGRA_PULL_3,
190 TEGRA_PULL_4,
191 TEGRA_PULL_5,
192 TEGRA_PULL_6,
193 TEGRA_PULL_7,
194 TEGRA_PULL_8,
195 TEGRA_PULL_9,
196 TEGRA_PULL_10,
197 TEGRA_PULL_11,
198 TEGRA_PULL_12,
199 TEGRA_PULL_13,
200 TEGRA_PULL_14,
201 TEGRA_PULL_15,
202 TEGRA_PULL_16,
203 TEGRA_PULL_17,
204 TEGRA_PULL_18,
205 TEGRA_PULL_19,
206 TEGRA_PULL_20,
207 TEGRA_PULL_21,
208 TEGRA_PULL_22,
209 TEGRA_PULL_23,
210 TEGRA_PULL_24,
211 TEGRA_PULL_25,
212 TEGRA_PULL_26,
213 TEGRA_PULL_27,
214 TEGRA_PULL_28,
215 TEGRA_PULL_29,
216 TEGRA_PULL_30,
217 TEGRA_PULL_31,
218 TEGRA_MAX_PULL,
219};
220
221enum tegra_drive {
222 TEGRA_DRIVE_DIV_8 = 0,
223 TEGRA_DRIVE_DIV_4,
224 TEGRA_DRIVE_DIV_2,
225 TEGRA_DRIVE_DIV_1,
226 TEGRA_MAX_DRIVE,
227};
228
229enum tegra_hsm {
230 TEGRA_HSM_DISABLE = 0,
231 TEGRA_HSM_ENABLE,
232};
233
234enum tegra_schmitt {
235 TEGRA_SCHMITT_DISABLE = 0,
236 TEGRA_SCHMITT_ENABLE,
237};
238
239struct tegra_drive_pingroup_config {
240 int pingroup;
241 enum tegra_hsm hsm;
242 enum tegra_schmitt schmitt;
243 enum tegra_drive drive;
244 enum tegra_pull_strength pull_down;
245 enum tegra_pull_strength pull_up;
246 enum tegra_slew slew_rising;
247 enum tegra_slew slew_falling;
248};
249
250struct tegra_drive_pingroup_desc {
251 const char *name;
252 s16 reg_bank;
253 s16 reg;
254};
255
256struct tegra_pingroup_desc {
257 const char *name;
258 int funcs[4];
259 int func_safe;
260 int vddio;
261 enum tegra_pin_io io_default;
262 s16 tri_bank; /* Register bank the tri_reg exists within */
263 s16 mux_bank; /* Register bank the mux_reg exists within */
264 s16 pupd_bank; /* Register bank the pupd_reg exists within */
265 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
266 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
267 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
268 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
269 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
270 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
271 s8 lock_bit; /* offset of the LOCK bit into mux register bit */
272 s8 od_bit; /* offset of the OD bit into mux register bit */
273 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
274};
275
276typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
277 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
278 int *pgdrive_max);
279
280void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
281 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
282
283void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
284 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
285
286int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
287int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
288
289void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
290 int len);
291
292void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
293 int len);
294void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
295 int len);
296void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
297 int len);
298void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
299 int len, enum tegra_tristate tristate);
300void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
301 int len, enum tegra_pullupdown pupd);
302#endif
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1280b..00000000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
3 *
4 * Common pinmux configurations for Tegra20 SoCs
5 *
6 * Copyright (C) 2010 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/spinlock.h>
26#include <linux/io.h>
27#include <linux/init.h>
28#include <linux/string.h>
29
30#include <mach/iomap.h>
31#include <mach/pinmux.h>
32#include <mach/pinmux-tegra20.h>
33#include <mach/suspend.h>
34
35#define TRISTATE_REG_A 0x14
36#define PIN_MUX_CTL_REG_A 0x80
37#define PULLUPDOWN_REG_A 0xa0
38#define PINGROUP_REG_A 0x868
39
40#define DRIVE_PINGROUP(pg_name, r) \
41 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
42 .name = #pg_name, \
43 .reg_bank = 3, \
44 .reg = ((r) - PINGROUP_REG_A) \
45 }
46
47static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
48 DRIVE_PINGROUP(AO1, 0x868),
49 DRIVE_PINGROUP(AO2, 0x86c),
50 DRIVE_PINGROUP(AT1, 0x870),
51 DRIVE_PINGROUP(AT2, 0x874),
52 DRIVE_PINGROUP(CDEV1, 0x878),
53 DRIVE_PINGROUP(CDEV2, 0x87c),
54 DRIVE_PINGROUP(CSUS, 0x880),
55 DRIVE_PINGROUP(DAP1, 0x884),
56 DRIVE_PINGROUP(DAP2, 0x888),
57 DRIVE_PINGROUP(DAP3, 0x88c),
58 DRIVE_PINGROUP(DAP4, 0x890),
59 DRIVE_PINGROUP(DBG, 0x894),
60 DRIVE_PINGROUP(LCD1, 0x898),
61 DRIVE_PINGROUP(LCD2, 0x89c),
62 DRIVE_PINGROUP(SDMMC2, 0x8a0),
63 DRIVE_PINGROUP(SDMMC3, 0x8a4),
64 DRIVE_PINGROUP(SPI, 0x8a8),
65 DRIVE_PINGROUP(UAA, 0x8ac),
66 DRIVE_PINGROUP(UAB, 0x8b0),
67 DRIVE_PINGROUP(UART2, 0x8b4),
68 DRIVE_PINGROUP(UART3, 0x8b8),
69 DRIVE_PINGROUP(VI1, 0x8bc),
70 DRIVE_PINGROUP(VI2, 0x8c0),
71 DRIVE_PINGROUP(XM2A, 0x8c4),
72 DRIVE_PINGROUP(XM2C, 0x8c8),
73 DRIVE_PINGROUP(XM2D, 0x8cc),
74 DRIVE_PINGROUP(XM2CLK, 0x8d0),
75 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
76 DRIVE_PINGROUP(SDIO1, 0x8e0),
77 DRIVE_PINGROUP(CRT, 0x8ec),
78 DRIVE_PINGROUP(DDC, 0x8f0),
79 DRIVE_PINGROUP(GMA, 0x8f4),
80 DRIVE_PINGROUP(GMB, 0x8f8),
81 DRIVE_PINGROUP(GMC, 0x8fc),
82 DRIVE_PINGROUP(GMD, 0x900),
83 DRIVE_PINGROUP(GME, 0x904),
84 DRIVE_PINGROUP(OWR, 0x908),
85 DRIVE_PINGROUP(UAD, 0x90c),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
89 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
90 [TEGRA_PINGROUP_ ## pg_name] = { \
91 .name = #pg_name, \
92 .vddio = TEGRA_VDDIO_ ## vdd, \
93 .funcs = { \
94 TEGRA_MUX_ ## f0, \
95 TEGRA_MUX_ ## f1, \
96 TEGRA_MUX_ ## f2, \
97 TEGRA_MUX_ ## f3, \
98 }, \
99 .func_safe = TEGRA_MUX_ ## f_safe, \
100 .tri_bank = 0, \
101 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
102 .tri_bit = tri_b, \
103 .mux_bank = 1, \
104 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
105 .mux_bit = mux_b, \
106 .pupd_bank = 2, \
107 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
108 .pupd_bit = pupd_b, \
109 .lock_bit = -1, \
110 .od_bit = -1, \
111 .ioreset_bit = -1, \
112 .io_default = -1, \
113 }
114
115static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
116 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
117 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
118 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
119 PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
120 PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
121 PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
122 PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
123 PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
124 PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
125 PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
126 PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
127 PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
128 PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
129 PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
130 PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
131 PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
132 PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
133 PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
134 PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
135 PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
136 PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
137 PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
138 PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
139 PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
140 PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
141 PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
142 PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
143 PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
144 PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
145 PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
146 PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
147 PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
148 PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
149 PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
150 PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
151 PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
152 PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
153 PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
154 PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
155 PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
156 PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
157 PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
158 PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
159 PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
160 PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
161 PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
162 PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
163 PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
164 PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
165 PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
166 PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
167 PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
168 PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
169 PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
170 PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
171 PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
172 PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
173 PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
174 PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
175 PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
176 PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
177 PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
178 PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
179 PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
180 PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
181 PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
182 PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
183 PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
184 PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
185 PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
186 PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
187 PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
188 PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
189 PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
190 PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
191 PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
192 PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
193 PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
194 PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
195 PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
196 PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
197 PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
198 PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
199 PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
200 PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
201 PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
202 PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
203 PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
204 PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
205 PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
206 PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
207 PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
208 PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
209 PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
210 PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
211 PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
212 PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
213 PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
214 PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
215 PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
216 PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
217 PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
218 PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
219 PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
220 PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
221 PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
222 PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
223 /* these pin groups only have pullup and pull down control */
224 PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
225 PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
226 PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
227 PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
228 PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
229 PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
230 PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
231 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
232 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
233};
234
235void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
236 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
237 int *pgdrive_max)
238{
239 *pg = tegra_soc_pingroups;
240 *pg_max = TEGRA_MAX_PINGROUP;
241 *pgdrive = tegra_soc_drive_pingroups;
242 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
243}
244
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4c1c4..00000000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
3 *
4 * Common pinmux configurations for Tegra30 SoCs
5 *
6 * Copyright (C) 2010,2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
26#include <linux/init.h>
27#include <linux/string.h>
28
29#include <mach/iomap.h>
30#include <mach/pinmux.h>
31#include <mach/pinmux-tegra30.h>
32#include <mach/suspend.h>
33
34#define PINGROUP_REG_A 0x868
35#define MUXCTL_REG_A 0x3000
36
37#define DRIVE_PINGROUP(pg_name, r) \
38 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
39 .name = #pg_name, \
40 .reg_bank = 0, \
41 .reg = ((r) - PINGROUP_REG_A) \
42 }
43
44static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
45 DRIVE_PINGROUP(AO1, 0x868),
46 DRIVE_PINGROUP(AO2, 0x86c),
47 DRIVE_PINGROUP(AT1, 0x870),
48 DRIVE_PINGROUP(AT2, 0x874),
49 DRIVE_PINGROUP(AT3, 0x878),
50 DRIVE_PINGROUP(AT4, 0x87c),
51 DRIVE_PINGROUP(AT5, 0x880),
52 DRIVE_PINGROUP(CDEV1, 0x884),
53 DRIVE_PINGROUP(CDEV2, 0x888),
54 DRIVE_PINGROUP(CSUS, 0x88c),
55 DRIVE_PINGROUP(DAP1, 0x890),
56 DRIVE_PINGROUP(DAP2, 0x894),
57 DRIVE_PINGROUP(DAP3, 0x898),
58 DRIVE_PINGROUP(DAP4, 0x89c),
59 DRIVE_PINGROUP(DBG, 0x8a0),
60 DRIVE_PINGROUP(LCD1, 0x8a4),
61 DRIVE_PINGROUP(LCD2, 0x8a8),
62 DRIVE_PINGROUP(SDIO2, 0x8ac),
63 DRIVE_PINGROUP(SDIO3, 0x8b0),
64 DRIVE_PINGROUP(SPI, 0x8b4),
65 DRIVE_PINGROUP(UAA, 0x8b8),
66 DRIVE_PINGROUP(UAB, 0x8bc),
67 DRIVE_PINGROUP(UART2, 0x8c0),
68 DRIVE_PINGROUP(UART3, 0x8c4),
69 DRIVE_PINGROUP(VI1, 0x8c8),
70 DRIVE_PINGROUP(SDIO1, 0x8ec),
71 DRIVE_PINGROUP(CRT, 0x8f8),
72 DRIVE_PINGROUP(DDC, 0x8fc),
73 DRIVE_PINGROUP(GMA, 0x900),
74 DRIVE_PINGROUP(GMB, 0x904),
75 DRIVE_PINGROUP(GMC, 0x908),
76 DRIVE_PINGROUP(GMD, 0x90c),
77 DRIVE_PINGROUP(GME, 0x910),
78 DRIVE_PINGROUP(GMF, 0x914),
79 DRIVE_PINGROUP(GMG, 0x918),
80 DRIVE_PINGROUP(GMH, 0x91c),
81 DRIVE_PINGROUP(OWR, 0x920),
82 DRIVE_PINGROUP(UAD, 0x924),
83 DRIVE_PINGROUP(GPV, 0x928),
84 DRIVE_PINGROUP(DEV3, 0x92c),
85 DRIVE_PINGROUP(CEC, 0x938),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
89 [TEGRA_PINGROUP_ ## pg_name] = { \
90 .name = #pg_name, \
91 .vddio = TEGRA_VDDIO_ ## vdd, \
92 .funcs = { \
93 TEGRA_MUX_ ## f0, \
94 TEGRA_MUX_ ## f1, \
95 TEGRA_MUX_ ## f2, \
96 TEGRA_MUX_ ## f3, \
97 }, \
98 .func_safe = TEGRA_MUX_ ## fs, \
99 .tri_bank = 1, \
100 .tri_reg = ((reg) - MUXCTL_REG_A), \
101 .tri_bit = 4, \
102 .mux_bank = 1, \
103 .mux_reg = ((reg) - MUXCTL_REG_A), \
104 .mux_bit = 0, \
105 .pupd_bank = 1, \
106 .pupd_reg = ((reg) - MUXCTL_REG_A), \
107 .pupd_bit = 2, \
108 .io_default = TEGRA_PIN_ ## iod, \
109 .od_bit = 6, \
110 .lock_bit = 7, \
111 .ioreset_bit = 8, \
112 }
113
114static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
115 /* NAME VDD f0 f1 f2 f3 fSafe io reg */
116 PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
117 PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
118 PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
119 PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
120 PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
121 PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
122 PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
123 PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
124 PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
125 PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
126 PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
127 PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
128 PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
129 PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
130 PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
131 PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
132 PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
133 PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
134 PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
135 PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
136 PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
137 PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
138 PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
139 PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
140 PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
141 PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
142 PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
143 PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
144 PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
145 PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
146 PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
147 PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
148 PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
149 PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
150 PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
151 PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
152 PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
153 PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
154 PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
155 PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
156 PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
157 PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
158 PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
159 PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
160 PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
161 PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
162 PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
163 PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
164 PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
165 PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
166 PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
167 PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
168 PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
169 PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
170 PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
171 PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
172 PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
173 PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
174 PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
175 PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
176 PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
177 PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
178 PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
179 PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
180 PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
181 PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
182 PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
183 PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
184 PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
185 PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
186 PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
187 PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
188 PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
189 PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
190 PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
191 PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
192 PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
193 PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
194 PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
195 PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
196 PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
197 PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
198 PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
199 PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
200 PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
201 PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
202 PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
203 PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
204 PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
205 PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
206 PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
207 PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
208 PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
209 PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
210 PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
211 PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
212 PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
213 PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
214 PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
215 PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
216 PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
217 PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
218 PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
219 PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
220 PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
221 PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
222 PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
223 PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
224 PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
225 PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
226 PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
227 PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
228 PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
229 PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
230 PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
231 PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
232 PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
233 PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
234 PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
235 PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
236 PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
237 PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
238 PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
239 PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
240 PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
241 PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
242 PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
243 PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
244 PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
245 PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
246 PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
247 PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
248 PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
249 PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
250 PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
251 PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
252 PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
253 PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
254 PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
255 PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
256 PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
257 PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
258 PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
259 PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
260 PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
261 PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
262 PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
263 PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
264 PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
265 PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
266 PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
267 PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
268 PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
269 PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
270 PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
271 PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
272 PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
273 PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
274 PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
275 PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
276 PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
277 PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
278 PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
279 PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
280 PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
281 PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
282 PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
283 PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
284 PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
285 PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
286 PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
287 PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
288 PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
289 PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
290 PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
291 PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
292 PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
293 PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
294 PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
295 PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
296 PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
297 PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
298 PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
299 PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
300 PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
301 PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
302 PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
303 PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
304 PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
305 PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
306 PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
307 PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
308 PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
309 PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
310 PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
311 PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
312 PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
313 PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
314 PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
315 PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
316 PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
317 PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
318 PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
319 PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
320 PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
321 PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
322 PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
323 PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
324 PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
325 PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
326 PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
327 PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
328 PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
329 PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
330 PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
331 PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
332 PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
333 PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
334 PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
335 PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
336 PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
337 PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
338 PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
339 PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
340 PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
341 PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
342 PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
343 PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
344 PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
345 PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
346 PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
347 PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
348 PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
349 PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
350 PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
351 PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
352 PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
353 PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
354 PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
355 PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
356 PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
357 PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
358 PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
359 PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
360 PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
361 PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
362 PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
363 PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
364 PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
365};
366
367void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
368 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
369 int *pgdrive_max)
370{
371 *pg = tegra_soc_pingroups;
372 *pg_max = TEGRA_MAX_PINGROUP;
373 *pgdrive = tegra_soc_drive_pingroups;
374 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
375}
376
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index ac35d2b7685..00000000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25
26#include <mach/iomap.h>
27#include <mach/pinmux.h>
28
29#define HSM_EN(reg) (((reg) >> 2) & 0x1)
30#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
31#define LPMD(reg) (((reg) >> 4) & 0x3)
32#define DRVDN(reg) (((reg) >> 12) & 0x1f)
33#define DRVUP(reg) (((reg) >> 20) & 0x1f)
34#define SLWR(reg) (((reg) >> 28) & 0x3)
35#define SLWF(reg) (((reg) >> 30) & 0x3)
36
37static const struct tegra_pingroup_desc *pingroups;
38static const struct tegra_drive_pingroup_desc *drive_pingroups;
39static int pingroup_max;
40static int drive_max;
41
42static char *tegra_mux_names[TEGRA_MAX_MUX] = {
43 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
44 [TEGRA_MUX_APB_CLK] = "APB_CLK",
45 [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
46 [TEGRA_MUX_CRT] = "CRT",
47 [TEGRA_MUX_DAP1] = "DAP1",
48 [TEGRA_MUX_DAP2] = "DAP2",
49 [TEGRA_MUX_DAP3] = "DAP3",
50 [TEGRA_MUX_DAP4] = "DAP4",
51 [TEGRA_MUX_DAP5] = "DAP5",
52 [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
53 [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
54 [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
55 [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
56 [TEGRA_MUX_GMI] = "GMI",
57 [TEGRA_MUX_GMI_INT] = "GMI_INT",
58 [TEGRA_MUX_HDMI] = "HDMI",
59 [TEGRA_MUX_I2C] = "I2C",
60 [TEGRA_MUX_I2C2] = "I2C2",
61 [TEGRA_MUX_I2C3] = "I2C3",
62 [TEGRA_MUX_IDE] = "IDE",
63 [TEGRA_MUX_IRDA] = "IRDA",
64 [TEGRA_MUX_KBC] = "KBC",
65 [TEGRA_MUX_MIO] = "MIO",
66 [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
67 [TEGRA_MUX_NAND] = "NAND",
68 [TEGRA_MUX_OSC] = "OSC",
69 [TEGRA_MUX_OWR] = "OWR",
70 [TEGRA_MUX_PCIE] = "PCIE",
71 [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
72 [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
73 [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
74 [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
75 [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
76 [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
77 [TEGRA_MUX_PWM] = "PWM",
78 [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
79 [TEGRA_MUX_PWR_ON] = "PWR_ON",
80 [TEGRA_MUX_RTCK] = "RTCK",
81 [TEGRA_MUX_SDIO1] = "SDIO1",
82 [TEGRA_MUX_SDIO2] = "SDIO2",
83 [TEGRA_MUX_SDIO3] = "SDIO3",
84 [TEGRA_MUX_SDIO4] = "SDIO4",
85 [TEGRA_MUX_SFLASH] = "SFLASH",
86 [TEGRA_MUX_SPDIF] = "SPDIF",
87 [TEGRA_MUX_SPI1] = "SPI1",
88 [TEGRA_MUX_SPI2] = "SPI2",
89 [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
90 [TEGRA_MUX_SPI3] = "SPI3",
91 [TEGRA_MUX_SPI4] = "SPI4",
92 [TEGRA_MUX_TRACE] = "TRACE",
93 [TEGRA_MUX_TWC] = "TWC",
94 [TEGRA_MUX_UARTA] = "UARTA",
95 [TEGRA_MUX_UARTB] = "UARTB",
96 [TEGRA_MUX_UARTC] = "UARTC",
97 [TEGRA_MUX_UARTD] = "UARTD",
98 [TEGRA_MUX_UARTE] = "UARTE",
99 [TEGRA_MUX_ULPI] = "ULPI",
100 [TEGRA_MUX_VI] = "VI",
101 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
102 [TEGRA_MUX_XIO] = "XIO",
103 [TEGRA_MUX_BLINK] = "BLINK",
104 [TEGRA_MUX_CEC] = "CEC",
105 [TEGRA_MUX_CLK12] = "CLK12",
106 [TEGRA_MUX_DAP] = "DAP",
107 [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
108 [TEGRA_MUX_DDR] = "DDR",
109 [TEGRA_MUX_DEV3] = "DEV3",
110 [TEGRA_MUX_DTV] = "DTV",
111 [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
112 [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
113 [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
114 [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
115 [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
116 [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
117 [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
118 [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
119 [TEGRA_MUX_HDA] = "HDA",
120 [TEGRA_MUX_HSI] = "HSI",
121 [TEGRA_MUX_I2C4] = "I2C4",
122 [TEGRA_MUX_I2C5] = "I2C5",
123 [TEGRA_MUX_I2CPWR] = "I2CPWR",
124 [TEGRA_MUX_I2S0] = "I2S0",
125 [TEGRA_MUX_I2S1] = "I2S1",
126 [TEGRA_MUX_I2S2] = "I2S2",
127 [TEGRA_MUX_I2S3] = "I2S3",
128 [TEGRA_MUX_I2S4] = "I2S4",
129 [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
130 [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
131 [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
132 [TEGRA_MUX_PWM0] = "PWM0",
133 [TEGRA_MUX_PWM1] = "PWM2",
134 [TEGRA_MUX_PWM2] = "PWM2",
135 [TEGRA_MUX_PWM3] = "PWM3",
136 [TEGRA_MUX_SATA] = "SATA",
137 [TEGRA_MUX_SPI5] = "SPI5",
138 [TEGRA_MUX_SPI6] = "SPI6",
139 [TEGRA_MUX_SYSCLK] = "SYSCLK",
140 [TEGRA_MUX_VGP1] = "VGP1",
141 [TEGRA_MUX_VGP2] = "VGP2",
142 [TEGRA_MUX_VGP3] = "VGP3",
143 [TEGRA_MUX_VGP4] = "VGP4",
144 [TEGRA_MUX_VGP5] = "VGP5",
145 [TEGRA_MUX_VGP6] = "VGP6",
146 [TEGRA_MUX_SAFE] = "<safe>",
147};
148
149static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
150 [TEGRA_DRIVE_DIV_8] = "DIV_8",
151 [TEGRA_DRIVE_DIV_4] = "DIV_4",
152 [TEGRA_DRIVE_DIV_2] = "DIV_2",
153 [TEGRA_DRIVE_DIV_1] = "DIV_1",
154};
155
156static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
157 [TEGRA_SLEW_FASTEST] = "FASTEST",
158 [TEGRA_SLEW_FAST] = "FAST",
159 [TEGRA_SLEW_SLOW] = "SLOW",
160 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
161};
162
163static DEFINE_SPINLOCK(mux_lock);
164
165static const char *pingroup_name(int pg)
166{
167 if (pg < 0 || pg >= pingroup_max)
168 return "<UNKNOWN>";
169
170 return pingroups[pg].name;
171}
172
173static const char *func_name(enum tegra_mux_func func)
174{
175 if (func == TEGRA_MUX_RSVD1)
176 return "RSVD1";
177
178 if (func == TEGRA_MUX_RSVD2)
179 return "RSVD2";
180
181 if (func == TEGRA_MUX_RSVD3)
182 return "RSVD3";
183
184 if (func == TEGRA_MUX_RSVD4)
185 return "RSVD4";
186
187 if (func == TEGRA_MUX_NONE)
188 return "NONE";
189
190 if (func < 0 || func >= TEGRA_MAX_MUX)
191 return "<UNKNOWN>";
192
193 return tegra_mux_names[func];
194}
195
196
197static const char *tri_name(unsigned long val)
198{
199 return val ? "TRISTATE" : "NORMAL";
200}
201
202static const char *pupd_name(unsigned long val)
203{
204 switch (val) {
205 case 0:
206 return "NORMAL";
207
208 case 1:
209 return "PULL_DOWN";
210
211 case 2:
212 return "PULL_UP";
213
214 default:
215 return "RSVD";
216 }
217}
218
219static int nbanks;
220static void __iomem **regs;
221
222static inline u32 pg_readl(u32 bank, u32 reg)
223{
224 return readl(regs[bank] + reg);
225}
226
227static inline void pg_writel(u32 val, u32 bank, u32 reg)
228{
229 writel(val, regs[bank] + reg);
230}
231
232static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
233{
234 int mux = -1;
235 int i;
236 unsigned long reg;
237 unsigned long flags;
238 int pg = config->pingroup;
239 enum tegra_mux_func func = config->func;
240
241 if (pg < 0 || pg >= pingroup_max)
242 return -ERANGE;
243
244 if (pingroups[pg].mux_reg < 0)
245 return -EINVAL;
246
247 if (func < 0)
248 return -ERANGE;
249
250 if (func == TEGRA_MUX_SAFE)
251 func = pingroups[pg].func_safe;
252
253 if (func & TEGRA_MUX_RSVD) {
254 mux = func & 0x3;
255 } else {
256 for (i = 0; i < 4; i++) {
257 if (pingroups[pg].funcs[i] == func) {
258 mux = i;
259 break;
260 }
261 }
262 }
263
264 if (mux < 0)
265 return -EINVAL;
266
267 spin_lock_irqsave(&mux_lock, flags);
268
269 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
270 reg &= ~(0x3 << pingroups[pg].mux_bit);
271 reg |= mux << pingroups[pg].mux_bit;
272 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
273
274 spin_unlock_irqrestore(&mux_lock, flags);
275
276 return 0;
277}
278
279int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
280{
281 unsigned long reg;
282 unsigned long flags;
283
284 if (pg < 0 || pg >= pingroup_max)
285 return -ERANGE;
286
287 if (pingroups[pg].tri_reg < 0)
288 return -EINVAL;
289
290 spin_lock_irqsave(&mux_lock, flags);
291
292 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
293 reg &= ~(0x1 << pingroups[pg].tri_bit);
294 if (tristate)
295 reg |= 1 << pingroups[pg].tri_bit;
296 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
297
298 spin_unlock_irqrestore(&mux_lock, flags);
299
300 return 0;
301}
302
303int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
304{
305 unsigned long reg;
306 unsigned long flags;
307
308 if (pg < 0 || pg >= pingroup_max)
309 return -ERANGE;
310
311 if (pingroups[pg].pupd_reg < 0)
312 return -EINVAL;
313
314 if (pupd != TEGRA_PUPD_NORMAL &&
315 pupd != TEGRA_PUPD_PULL_DOWN &&
316 pupd != TEGRA_PUPD_PULL_UP)
317 return -EINVAL;
318
319
320 spin_lock_irqsave(&mux_lock, flags);
321
322 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
323 reg &= ~(0x3 << pingroups[pg].pupd_bit);
324 reg |= pupd << pingroups[pg].pupd_bit;
325 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
326
327 spin_unlock_irqrestore(&mux_lock, flags);
328
329 return 0;
330}
331
332static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
333{
334 int pingroup = config->pingroup;
335 enum tegra_mux_func func = config->func;
336 enum tegra_pullupdown pupd = config->pupd;
337 enum tegra_tristate tristate = config->tristate;
338 int err;
339
340 if (pingroups[pingroup].mux_reg >= 0) {
341 err = tegra_pinmux_set_func(config);
342 if (err < 0)
343 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
344 pingroup_name(pingroup), func_name(func), err);
345 }
346
347 if (pingroups[pingroup].pupd_reg >= 0) {
348 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
349 if (err < 0)
350 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
351 pingroup_name(pingroup), pupd_name(pupd), err);
352 }
353
354 if (pingroups[pingroup].tri_reg >= 0) {
355 err = tegra_pinmux_set_tristate(pingroup, tristate);
356 if (err < 0)
357 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
358 pingroup_name(pingroup), tri_name(func), err);
359 }
360}
361
362void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
363{
364 int i;
365
366 for (i = 0; i < len; i++)
367 tegra_pinmux_config_pingroup(&config[i]);
368}
369
370static const char *drive_pinmux_name(int pg)
371{
372 if (pg < 0 || pg >= drive_max)
373 return "<UNKNOWN>";
374
375 return drive_pingroups[pg].name;
376}
377
378static const char *enable_name(unsigned long val)
379{
380 return val ? "ENABLE" : "DISABLE";
381}
382
383static const char *drive_name(unsigned long val)
384{
385 if (val >= TEGRA_MAX_DRIVE)
386 return "<UNKNOWN>";
387
388 return tegra_drive_names[val];
389}
390
391static const char *slew_name(unsigned long val)
392{
393 if (val >= TEGRA_MAX_SLEW)
394 return "<UNKNOWN>";
395
396 return tegra_slew_names[val];
397}
398
399static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
400{
401 unsigned long flags;
402 u32 reg;
403 if (pg < 0 || pg >= drive_max)
404 return -ERANGE;
405
406 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
407 return -EINVAL;
408
409 spin_lock_irqsave(&mux_lock, flags);
410
411 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
412 if (hsm == TEGRA_HSM_ENABLE)
413 reg |= (1 << 2);
414 else
415 reg &= ~(1 << 2);
416 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
417
418 spin_unlock_irqrestore(&mux_lock, flags);
419
420 return 0;
421}
422
423static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
424{
425 unsigned long flags;
426 u32 reg;
427 if (pg < 0 || pg >= drive_max)
428 return -ERANGE;
429
430 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
431 return -EINVAL;
432
433 spin_lock_irqsave(&mux_lock, flags);
434
435 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
436 if (schmitt == TEGRA_SCHMITT_ENABLE)
437 reg |= (1 << 3);
438 else
439 reg &= ~(1 << 3);
440 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
441
442 spin_unlock_irqrestore(&mux_lock, flags);
443
444 return 0;
445}
446
447static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
448{
449 unsigned long flags;
450 u32 reg;
451 if (pg < 0 || pg >= drive_max)
452 return -ERANGE;
453
454 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
455 return -EINVAL;
456
457 spin_lock_irqsave(&mux_lock, flags);
458
459 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
460 reg &= ~(0x3 << 4);
461 reg |= drive << 4;
462 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
463
464 spin_unlock_irqrestore(&mux_lock, flags);
465
466 return 0;
467}
468
469static int tegra_drive_pinmux_set_pull_down(int pg,
470 enum tegra_pull_strength pull_down)
471{
472 unsigned long flags;
473 u32 reg;
474 if (pg < 0 || pg >= drive_max)
475 return -ERANGE;
476
477 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
478 return -EINVAL;
479
480 spin_lock_irqsave(&mux_lock, flags);
481
482 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
483 reg &= ~(0x1f << 12);
484 reg |= pull_down << 12;
485 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
486
487 spin_unlock_irqrestore(&mux_lock, flags);
488
489 return 0;
490}
491
492static int tegra_drive_pinmux_set_pull_up(int pg,
493 enum tegra_pull_strength pull_up)
494{
495 unsigned long flags;
496 u32 reg;
497 if (pg < 0 || pg >= drive_max)
498 return -ERANGE;
499
500 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
501 return -EINVAL;
502
503 spin_lock_irqsave(&mux_lock, flags);
504
505 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
506 reg &= ~(0x1f << 12);
507 reg |= pull_up << 12;
508 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
509
510 spin_unlock_irqrestore(&mux_lock, flags);
511
512 return 0;
513}
514
515static int tegra_drive_pinmux_set_slew_rising(int pg,
516 enum tegra_slew slew_rising)
517{
518 unsigned long flags;
519 u32 reg;
520 if (pg < 0 || pg >= drive_max)
521 return -ERANGE;
522
523 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
524 return -EINVAL;
525
526 spin_lock_irqsave(&mux_lock, flags);
527
528 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
529 reg &= ~(0x3 << 28);
530 reg |= slew_rising << 28;
531 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
532
533 spin_unlock_irqrestore(&mux_lock, flags);
534
535 return 0;
536}
537
538static int tegra_drive_pinmux_set_slew_falling(int pg,
539 enum tegra_slew slew_falling)
540{
541 unsigned long flags;
542 u32 reg;
543 if (pg < 0 || pg >= drive_max)
544 return -ERANGE;
545
546 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
547 return -EINVAL;
548
549 spin_lock_irqsave(&mux_lock, flags);
550
551 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
552 reg &= ~(0x3 << 30);
553 reg |= slew_falling << 30;
554 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
555
556 spin_unlock_irqrestore(&mux_lock, flags);
557
558 return 0;
559}
560
561static void tegra_drive_pinmux_config_pingroup(int pingroup,
562 enum tegra_hsm hsm,
563 enum tegra_schmitt schmitt,
564 enum tegra_drive drive,
565 enum tegra_pull_strength pull_down,
566 enum tegra_pull_strength pull_up,
567 enum tegra_slew slew_rising,
568 enum tegra_slew slew_falling)
569{
570 int err;
571
572 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
573 if (err < 0)
574 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
575 drive_pinmux_name(pingroup),
576 enable_name(hsm), err);
577
578 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
579 if (err < 0)
580 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
581 drive_pinmux_name(pingroup),
582 enable_name(schmitt), err);
583
584 err = tegra_drive_pinmux_set_drive(pingroup, drive);
585 if (err < 0)
586 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
587 drive_pinmux_name(pingroup),
588 drive_name(drive), err);
589
590 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
591 if (err < 0)
592 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
593 drive_pinmux_name(pingroup),
594 pull_down, err);
595
596 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
597 if (err < 0)
598 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
599 drive_pinmux_name(pingroup),
600 pull_up, err);
601
602 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
603 if (err < 0)
604 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
605 drive_pinmux_name(pingroup),
606 slew_name(slew_rising), err);
607
608 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
609 if (err < 0)
610 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
611 drive_pinmux_name(pingroup),
612 slew_name(slew_falling), err);
613}
614
615void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
616 int len)
617{
618 int i;
619
620 for (i = 0; i < len; i++)
621 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
622 config[i].hsm,
623 config[i].schmitt,
624 config[i].drive,
625 config[i].pull_down,
626 config[i].pull_up,
627 config[i].slew_rising,
628 config[i].slew_falling);
629}
630
631void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
632 int len)
633{
634 int i;
635 struct tegra_pingroup_config c;
636
637 for (i = 0; i < len; i++) {
638 int err;
639 c = config[i];
640 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
641 WARN_ON(1);
642 continue;
643 }
644 c.func = pingroups[c.pingroup].func_safe;
645 err = tegra_pinmux_set_func(&c);
646 if (err < 0)
647 pr_err("%s: tegra_pinmux_set_func returned %d setting "
648 "%s to %s\n", __func__, err,
649 pingroup_name(c.pingroup), func_name(c.func));
650 }
651}
652
653void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
654 int len)
655{
656 int i;
657
658 for (i = 0; i < len; i++) {
659 int err;
660 if (config[i].pingroup < 0 ||
661 config[i].pingroup >= pingroup_max) {
662 WARN_ON(1);
663 continue;
664 }
665 err = tegra_pinmux_set_func(&config[i]);
666 if (err < 0)
667 pr_err("%s: tegra_pinmux_set_func returned %d setting "
668 "%s to %s\n", __func__, err,
669 pingroup_name(config[i].pingroup),
670 func_name(config[i].func));
671 }
672}
673
674void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
675 int len, enum tegra_tristate tristate)
676{
677 int i;
678 int err;
679 int pingroup;
680
681 for (i = 0; i < len; i++) {
682 pingroup = config[i].pingroup;
683 if (pingroups[pingroup].tri_reg >= 0) {
684 err = tegra_pinmux_set_tristate(pingroup, tristate);
685 if (err < 0)
686 pr_err("pinmux: can't set pingroup %s tristate"
687 " to %s: %d\n", pingroup_name(pingroup),
688 tri_name(tristate), err);
689 }
690 }
691}
692
693void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
694 int len, enum tegra_pullupdown pupd)
695{
696 int i;
697 int err;
698 int pingroup;
699
700 for (i = 0; i < len; i++) {
701 pingroup = config[i].pingroup;
702 if (pingroups[pingroup].pupd_reg >= 0) {
703 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
704 if (err < 0)
705 pr_err("pinmux: can't set pingroup %s pullupdown"
706 " to %s: %d\n", pingroup_name(pingroup),
707 pupd_name(pupd), err);
708 }
709 }
710}
711
712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
713#ifdef CONFIG_ARCH_TEGRA_2x_SOC
714 { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
715#endif
716#ifdef CONFIG_ARCH_TEGRA_3x_SOC
717 { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
718#endif
719 { },
720};
721
722static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
723{
724 struct resource *res;
725 int i;
726 int config_bad = 0;
727 const struct of_device_id *match;
728
729 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
730
731 if (match)
732 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
733 &drive_pingroups, &drive_max);
734#ifdef CONFIG_ARCH_TEGRA_2x_SOC
735 else
736 /* no device tree available, so we must be on tegra20 */
737 tegra20_pinmux_init(&pingroups, &pingroup_max,
738 &drive_pingroups, &drive_max);
739#else
740 pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
741#endif
742
743 for (i = 0; ; i++) {
744 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
745 if (!res)
746 break;
747 }
748 nbanks = i;
749
750 for (i = 0; i < pingroup_max; i++) {
751 if (pingroups[i].tri_bank >= nbanks) {
752 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
753 config_bad = 1;
754 }
755
756 if (pingroups[i].mux_bank >= nbanks) {
757 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
758 config_bad = 1;
759 }
760
761 if (pingroups[i].pupd_bank >= nbanks) {
762 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
763 config_bad = 1;
764 }
765 }
766
767 for (i = 0; i < drive_max; i++) {
768 if (drive_pingroups[i].reg_bank >= nbanks) {
769 dev_err(&pdev->dev,
770 "drive pingroup %d: bad reg_bank\n", i);
771 config_bad = 1;
772 }
773 }
774
775 if (config_bad)
776 return -ENODEV;
777
778 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
779 if (!regs) {
780 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
781 return -ENODEV;
782 }
783
784 for (i = 0; i < nbanks; i++) {
785 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
786 if (!res) {
787 dev_err(&pdev->dev, "Missing MEM resource\n");
788 return -ENODEV;
789 }
790
791 if (!devm_request_mem_region(&pdev->dev, res->start,
792 resource_size(res),
793 dev_name(&pdev->dev))) {
794 dev_err(&pdev->dev,
795 "Couldn't request MEM resource %d\n", i);
796 return -ENODEV;
797 }
798
799 regs[i] = devm_ioremap(&pdev->dev, res->start,
800 resource_size(res));
801 if (!regs) {
802 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
803 return -ENODEV;
804 }
805 }
806
807 return 0;
808}
809
810static struct platform_driver tegra_pinmux_driver = {
811 .driver = {
812 .name = "tegra-pinmux",
813 .owner = THIS_MODULE,
814 .of_match_table = tegra_pinmux_of_match,
815 },
816 .probe = tegra_pinmux_probe,
817};
818
819static int __init tegra_pinmux_init(void)
820{
821 return platform_driver_register(&tegra_pinmux_driver);
822}
823postcore_initcall(tegra_pinmux_init);
824
825#ifdef CONFIG_DEBUG_FS
826
827#include <linux/debugfs.h>
828#include <linux/seq_file.h>
829
830static void dbg_pad_field(struct seq_file *s, int len)
831{
832 seq_putc(s, ',');
833
834 while (len-- > -1)
835 seq_putc(s, ' ');
836}
837
838static int dbg_pinmux_show(struct seq_file *s, void *unused)
839{
840 int i;
841 int len;
842
843 for (i = 0; i < pingroup_max; i++) {
844 unsigned long reg;
845 unsigned long tri;
846 unsigned long mux;
847 unsigned long pupd;
848
849 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
850 len = strlen(pingroups[i].name);
851 dbg_pad_field(s, 5 - len);
852
853 if (pingroups[i].mux_reg < 0) {
854 seq_printf(s, "TEGRA_MUX_NONE");
855 len = strlen("NONE");
856 } else {
857 reg = pg_readl(pingroups[i].mux_bank,
858 pingroups[i].mux_reg);
859 mux = (reg >> pingroups[i].mux_bit) & 0x3;
860 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
861 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
862 len = 5;
863 } else {
864 seq_printf(s, "TEGRA_MUX_%s",
865 tegra_mux_names[pingroups[i].funcs[mux]]);
866 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
867 }
868 }
869 dbg_pad_field(s, 13-len);
870
871 if (pingroups[i].pupd_reg < 0) {
872 seq_printf(s, "TEGRA_PUPD_NORMAL");
873 len = strlen("NORMAL");
874 } else {
875 reg = pg_readl(pingroups[i].pupd_bank,
876 pingroups[i].pupd_reg);
877 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
878 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
879 len = strlen(pupd_name(pupd));
880 }
881 dbg_pad_field(s, 9 - len);
882
883 if (pingroups[i].tri_reg < 0) {
884 seq_printf(s, "TEGRA_TRI_NORMAL");
885 } else {
886 reg = pg_readl(pingroups[i].tri_bank,
887 pingroups[i].tri_reg);
888 tri = (reg >> pingroups[i].tri_bit) & 0x1;
889
890 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
891 }
892 seq_printf(s, "},\n");
893 }
894 return 0;
895}
896
897static int dbg_pinmux_open(struct inode *inode, struct file *file)
898{
899 return single_open(file, dbg_pinmux_show, &inode->i_private);
900}
901
902static const struct file_operations debug_fops = {
903 .open = dbg_pinmux_open,
904 .read = seq_read,
905 .llseek = seq_lseek,
906 .release = single_release,
907};
908
909static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
910{
911 int i;
912 int len;
913
914 for (i = 0; i < drive_max; i++) {
915 u32 reg;
916
917 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
918 drive_pingroups[i].name);
919 len = strlen(drive_pingroups[i].name);
920 dbg_pad_field(s, 7 - len);
921
922
923 reg = pg_readl(drive_pingroups[i].reg_bank,
924 drive_pingroups[i].reg);
925 if (HSM_EN(reg)) {
926 seq_printf(s, "TEGRA_HSM_ENABLE");
927 len = 16;
928 } else {
929 seq_printf(s, "TEGRA_HSM_DISABLE");
930 len = 17;
931 }
932 dbg_pad_field(s, 17 - len);
933
934 if (SCHMT_EN(reg)) {
935 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
936 len = 21;
937 } else {
938 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
939 len = 22;
940 }
941 dbg_pad_field(s, 22 - len);
942
943 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
944 len = strlen(drive_name(LPMD(reg)));
945 dbg_pad_field(s, 5 - len);
946
947 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
948 len = DRVDN(reg) < 10 ? 1 : 2;
949 dbg_pad_field(s, 2 - len);
950
951 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
952 len = DRVUP(reg) < 10 ? 1 : 2;
953 dbg_pad_field(s, 2 - len);
954
955 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
956 len = strlen(slew_name(SLWR(reg)));
957 dbg_pad_field(s, 7 - len);
958
959 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
960
961 seq_printf(s, "},\n");
962 }
963 return 0;
964}
965
966static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
967{
968 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
969}
970
971static const struct file_operations debug_drive_fops = {
972 .open = dbg_drive_pinmux_open,
973 .read = seq_read,
974 .llseek = seq_lseek,
975 .release = single_release,
976};
977
978static int __init tegra_pinmux_debuginit(void)
979{
980 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
981 NULL, NULL, &debug_fops);
982 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
983 NULL, NULL, &debug_drive_fops);
984 return 0;
985}
986late_initcall(tegra_pinmux_debuginit);
987#endif
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac04e2a..d71d2fed672 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
711 err = -ENXIO; 711 err = -ENXIO;
712 goto err1; 712 goto err1;
713 } 713 }
714 tegra_gpio_enable(ulpi_config->reset_gpio);
715 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); 714 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
716 gpio_direction_output(ulpi_config->reset_gpio, 0); 715 gpio_direction_output(ulpi_config->reset_gpio, 0);
717 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); 716 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 0e8470a3fbe..53d3d46dec1 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -9,6 +9,8 @@ config UX500_SOC_COMMON
9 select ARM_ERRATA_754322 9 select ARM_ERRATA_754322
10 select ARM_ERRATA_764369 10 select ARM_ERRATA_764369
11 select CACHE_L2X0 11 select CACHE_L2X0
12 select PINCTRL
13 select PINCTRL_NOMADIK
12 14
13config UX500_SOC_DB8500 15config UX500_SOC_DB8500
14 bool 16 bool
@@ -16,6 +18,7 @@ config UX500_SOC_DB8500
16 select REGULATOR 18 select REGULATOR
17 select REGULATOR_DB8500_PRCMU 19 select REGULATOR_DB8500_PRCMU
18 select CPU_FREQ_TABLE if CPU_FREQ 20 select CPU_FREQ_TABLE if CPU_FREQ
21 select PINCTRL_DB8500
19 22
20menu "Ux500 target platform (boards)" 23menu "Ux500 target platform (boards)"
21 24
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index fc7db5df970..041c3588598 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
10 board-mop500-regulators.o \ 10 board-mop500-regulators.o \
11 board-mop500-uib.o board-mop500-stuib.o \ 11 board-mop500-uib.o board-mop500-stuib.o \
12 board-mop500-u8500uib.o \ 12 board-mop500-u8500uib.o \
13 board-mop500-pins.o 13 board-mop500-pins.o \
14 board-mop500-msp.o
14obj-$(CONFIG_SMP) += platsmp.o headsmp.o 15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
15obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 16obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
new file mode 100644
index 00000000000..99604803874
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -0,0 +1,267 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/gpio.h>
10#include <linux/pinctrl/consumer.h>
11
12#include <plat/gpio-nomadik.h>
13#include <plat/pincfg.h>
14#include <plat/ste_dma40.h>
15
16#include <mach/devices.h>
17#include <mach/hardware.h>
18#include <mach/irqs.h>
19#include <mach/msp.h>
20
21#include "ste-dma40-db8500.h"
22#include "board-mop500.h"
23#include "devices-db8500.h"
24#include "pins-db8500.h"
25
26/* MSP1/3 Tx/Rx usage protection */
27static DEFINE_SPINLOCK(msp_rxtx_lock);
28
29/* Reference Count */
30static int msp_rxtx_ref;
31
32/* Pin modes */
33struct pinctrl *msp1_p;
34struct pinctrl_state *msp1_def;
35struct pinctrl_state *msp1_sleep;
36
37int msp13_i2s_init(void)
38{
39 int retval = 0;
40 unsigned long flags;
41
42 spin_lock_irqsave(&msp_rxtx_lock, flags);
43 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
44 retval = pinctrl_select_state(msp1_p, msp1_def);
45 if (retval)
46 pr_err("could not set MSP1 defstate\n");
47 }
48 if (!retval)
49 msp_rxtx_ref++;
50 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
51
52 return retval;
53}
54
55int msp13_i2s_exit(void)
56{
57 int retval = 0;
58 unsigned long flags;
59
60 spin_lock_irqsave(&msp_rxtx_lock, flags);
61 WARN_ON(!msp_rxtx_ref);
62 msp_rxtx_ref--;
63 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
64 retval = pinctrl_select_state(msp1_p, msp1_sleep);
65 if (retval)
66 pr_err("could not set MSP1 sleepstate\n");
67 }
68 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
69
70 return retval;
71}
72
73static struct stedma40_chan_cfg msp0_dma_rx = {
74 .high_priority = true,
75 .dir = STEDMA40_PERIPH_TO_MEM,
76
77 .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
78 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
79
80 .src_info.psize = STEDMA40_PSIZE_LOG_4,
81 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
82
83 /* data_width is set during configuration */
84};
85
86static struct stedma40_chan_cfg msp0_dma_tx = {
87 .high_priority = true,
88 .dir = STEDMA40_MEM_TO_PERIPH,
89
90 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
91 .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
92
93 .src_info.psize = STEDMA40_PSIZE_LOG_4,
94 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
95
96 /* data_width is set during configuration */
97};
98
99static struct msp_i2s_platform_data msp0_platform_data = {
100 .id = MSP_I2S_0,
101 .msp_i2s_dma_rx = &msp0_dma_rx,
102 .msp_i2s_dma_tx = &msp0_dma_tx,
103};
104
105static struct stedma40_chan_cfg msp1_dma_rx = {
106 .high_priority = true,
107 .dir = STEDMA40_PERIPH_TO_MEM,
108
109 .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
110 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
111
112 .src_info.psize = STEDMA40_PSIZE_LOG_4,
113 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
114
115 /* data_width is set during configuration */
116};
117
118static struct stedma40_chan_cfg msp1_dma_tx = {
119 .high_priority = true,
120 .dir = STEDMA40_MEM_TO_PERIPH,
121
122 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
123 .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
124
125 .src_info.psize = STEDMA40_PSIZE_LOG_4,
126 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
127
128 /* data_width is set during configuration */
129};
130
131static struct msp_i2s_platform_data msp1_platform_data = {
132 .id = MSP_I2S_1,
133 .msp_i2s_dma_rx = NULL,
134 .msp_i2s_dma_tx = &msp1_dma_tx,
135 .msp_i2s_init = msp13_i2s_init,
136 .msp_i2s_exit = msp13_i2s_exit,
137};
138
139static struct stedma40_chan_cfg msp2_dma_rx = {
140 .high_priority = true,
141 .dir = STEDMA40_PERIPH_TO_MEM,
142
143 .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
144 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
145
146 /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
147 .src_info.psize = STEDMA40_PSIZE_LOG_1,
148 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
149
150 /* data_width is set during configuration */
151};
152
153static struct stedma40_chan_cfg msp2_dma_tx = {
154 .high_priority = true,
155 .dir = STEDMA40_MEM_TO_PERIPH,
156
157 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
158 .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
159
160 .src_info.psize = STEDMA40_PSIZE_LOG_4,
161 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
162
163 .use_fixed_channel = true,
164 .phy_channel = 1,
165
166 /* data_width is set during configuration */
167};
168
169static struct platform_device *db8500_add_msp_i2s(struct device *parent,
170 int id,
171 resource_size_t base, int irq,
172 struct msp_i2s_platform_data *pdata)
173{
174 struct platform_device *pdev;
175 struct resource res[] = {
176 DEFINE_RES_MEM(base, SZ_4K),
177 DEFINE_RES_IRQ(irq),
178 };
179
180 pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
181 id, irq);
182 pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
183 res, ARRAY_SIZE(res),
184 pdata, sizeof(*pdata));
185 if (!pdev) {
186 pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
187 id);
188 return NULL;
189 }
190
191 return pdev;
192}
193
194/* Platform device for ASoC U8500 machine */
195static struct platform_device snd_soc_u8500 = {
196 .name = "snd-soc-u8500",
197 .id = 0,
198 .dev = {
199 .platform_data = NULL,
200 },
201};
202
203/* Platform device for Ux500-PCM */
204static struct platform_device ux500_pcm = {
205 .name = "ux500-pcm",
206 .id = 0,
207 .dev = {
208 .platform_data = NULL,
209 },
210};
211
212static struct msp_i2s_platform_data msp2_platform_data = {
213 .id = MSP_I2S_2,
214 .msp_i2s_dma_rx = &msp2_dma_rx,
215 .msp_i2s_dma_tx = &msp2_dma_tx,
216};
217
218static struct msp_i2s_platform_data msp3_platform_data = {
219 .id = MSP_I2S_3,
220 .msp_i2s_dma_rx = &msp1_dma_rx,
221 .msp_i2s_dma_tx = NULL,
222 .msp_i2s_init = msp13_i2s_init,
223 .msp_i2s_exit = msp13_i2s_exit,
224};
225
226int mop500_msp_init(struct device *parent)
227{
228 struct platform_device *msp1;
229
230 pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
231 platform_device_register(&snd_soc_u8500);
232
233 pr_info("Initialize MSP I2S-devices.\n");
234 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
235 &msp0_platform_data);
236 msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
237 &msp1_platform_data);
238 db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
239 &msp2_platform_data);
240 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
241 &msp3_platform_data);
242
243 /* Get the pinctrl handle for MSP1 */
244 if (msp1) {
245 msp1_p = pinctrl_get(&msp1->dev);
246 if (IS_ERR(msp1_p))
247 dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
248 else {
249 msp1_def = pinctrl_lookup_state(msp1_p,
250 PINCTRL_STATE_DEFAULT);
251 if (IS_ERR(msp1_def)) {
252 dev_err(&msp1->dev,
253 "could not get MSP1 defstate\n");
254 }
255 msp1_sleep = pinctrl_lookup_state(msp1_p,
256 PINCTRL_STATE_SLEEP);
257 if (IS_ERR(msp1_sleep))
258 dev_err(&msp1->dev,
259 "could not get MSP1 idlestate\n");
260 }
261 }
262
263 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
264 platform_device_register(&ux500_pcm);
265
266 return 0;
267}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
new file mode 100644
index 00000000000..6fcfb5e2cc9
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.h
@@ -0,0 +1,14 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * for ST-Ericsson.
6 *
7 * License terms:
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f5413dca532..32fd9920446 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -7,299 +7,508 @@
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/bug.h> 9#include <linux/bug.h>
10#include <linux/string.h>
11#include <linux/pinctrl/machine.h>
10 12
11#include <asm/mach-types.h> 13#include <asm/mach-types.h>
12#include <plat/pincfg.h> 14#include <plat/pincfg.h>
13#include <plat/gpio-nomadik.h> 15#include <plat/gpio-nomadik.h>
16
14#include <mach/hardware.h> 17#include <mach/hardware.h>
15 18
16#include "pins-db8500.h" 19#include "pins-db8500.h"
20#include "board-mop500.h"
17 21
18static pin_cfg_t mop500_pins_common[] = { 22enum custom_pin_cfg_t {
19 /* I2C */ 23 PINS_FOR_DEFAULT,
20 GPIO147_I2C0_SCL, 24 PINS_FOR_U9500,
21 GPIO148_I2C0_SDA, 25};
22 GPIO16_I2C1_SCL,
23 GPIO17_I2C1_SDA,
24 GPIO10_I2C2_SDA,
25 GPIO11_I2C2_SCL,
26 GPIO229_I2C3_SDA,
27 GPIO230_I2C3_SCL,
28
29 /* MSP0 */
30 GPIO12_MSP0_TXD,
31 GPIO13_MSP0_TFS,
32 GPIO14_MSP0_TCK,
33 GPIO15_MSP0_RXD,
34
35 /* MSP2: HDMI */
36 GPIO193_MSP2_TXD,
37 GPIO194_MSP2_TCK,
38 GPIO195_MSP2_TFS,
39 GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
40
41 /* Touch screen INTERFACE */
42 GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
43
44 /* STMPE1601/tc35893 keypad IRQ */
45 GPIO218_GPIO | PIN_INPUT_PULLUP,
46
47 /* MMC0 (MicroSD card) */
48 GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
49 GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
50 GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
51
52 GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
53 GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
54 GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
55 GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
56 GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
57 GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
58 GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
59
60 /* SDI1 (SDIO) */
61 GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
62 GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
63 GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
64 GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
65 GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
66 GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
67 GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
68
69 /* MMC2 (On-board DATA INTERFACE eMMC) */
70 GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
71 GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
72 GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
73 GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
74 GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
75 GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
76 GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
77 GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
78 GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
79 GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
80 GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
81
82 /* MMC4 (On-board STORAGE INTERFACE eMMC) */
83 GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
84 GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
85 GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
86 GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
87 GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
88 GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
89 GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
90 GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
91 GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
92 GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
93 GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
94
95 /* SKE keypad */
96 GPIO153_KP_I7,
97 GPIO154_KP_I6,
98 GPIO155_KP_I5,
99 GPIO156_KP_I4,
100 GPIO157_KP_O7,
101 GPIO158_KP_O6,
102 GPIO159_KP_O5,
103 GPIO160_KP_O4,
104 GPIO161_KP_I3,
105 GPIO162_KP_I2,
106 GPIO163_KP_I1,
107 GPIO164_KP_I0,
108 GPIO165_KP_O3,
109 GPIO166_KP_O2,
110 GPIO167_KP_O1,
111 GPIO168_KP_O0,
112 26
113 /* UART */ 27static enum custom_pin_cfg_t pinsfor;
114 /* uart-0 pins gpio configuration should be 28
115 * kept intact to prevent glitch in tx line 29/* These simply sets bias for pins */
116 * when tty dev is opened. Later these pins 30#define BIAS(a,b) static unsigned long a[] = { b }
31
32BIAS(pd, PIN_PULL_DOWN);
33BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
34BIAS(in_nopull, PIN_INPUT_NOPULL);
35BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
36BIAS(in_pu, PIN_INPUT_PULLUP);
37BIAS(in_pd, PIN_INPUT_PULLDOWN);
38BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
39BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
40BIAS(out_hi, PIN_OUTPUT_HIGH);
41BIAS(out_lo, PIN_OUTPUT_LOW);
42BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
43/* These also force them into GPIO mode */
44BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
45BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
46BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
47BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
48BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
49BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
50/* Sleep modes */
51BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
52BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
53BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
54BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
55BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
56
57/* We use these to define hog settings that are always done on boot */
58#define DB8500_MUX_HOG(group,func) \
59 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
60#define DB8500_PIN_HOG(pin,conf) \
61 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
62
63/* These are default states associated with device and changed runtime */
64#define DB8500_MUX(group,func,dev) \
65 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
66#define DB8500_PIN(pin,conf,dev) \
67 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
68
69#define DB8500_PIN_SLEEP(pin,conf,dev) \
70 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
71 pin, conf)
72
73/* Pin control settings */
74static struct pinctrl_map __initdata mop500_family_pinmap[] = {
75 /*
76 * uMSP0, mux in 4 pins, regular placement of RX/TX
77 * explicitly set the pins to no pull
78 */
79 DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
80 DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
81 DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
82 DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
83 DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
84 DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
85 /* MSP2 for HDMI, pull down TXD, TCK, TFS */
86 DB8500_MUX_HOG("msp2_a_1", "msp2"),
87 DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
88 DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
89 DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
90 DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
91 /*
92 * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
93 * pull-up
94 * TODO: is this really correct? Snowball doesn't have a LCD.
95 */
96 DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
97 DB8500_PIN_HOG("GPIO68_E1", in_pu),
98 DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
99 /*
100 * STMPE1601/tc35893 keypad IRQ GPIO 218
101 * TODO: set for snowball and HREF really??
102 */
103 DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
104 /*
105 * UART0, we do not mux in u0 here.
106 * uart-0 pins gpio configuration should be kept intact to prevent
107 * a glitch in tx line when the tty dev is opened. Later these pins
117 * are configured to uart mop500_pins_uart0 108 * are configured to uart mop500_pins_uart0
118 *
119 * It will be replaced with uart configuration
120 * once the issue is solved.
121 */ 109 */
122 GPIO0_GPIO | PIN_INPUT_PULLUP, 110 DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
123 GPIO1_GPIO | PIN_OUTPUT_HIGH, 111 DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
124 GPIO2_GPIO | PIN_INPUT_PULLUP, 112 DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
125 GPIO3_GPIO | PIN_OUTPUT_HIGH, 113 DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
126 114 /*
127 GPIO29_U2_RXD | PIN_INPUT_PULLUP, 115 * Mux in UART2 on altfunction C and set pull-ups.
128 GPIO30_U2_TXD | PIN_OUTPUT_HIGH, 116 * TODO: is this used on U8500 variants and Snowball really?
129 GPIO31_U2_CTSn | PIN_INPUT_PULLUP, 117 * The setting on GPIO31 conflicts with magnetometer use on hrefv60
130 GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, 118 */
131 119 DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
132 /* Display & HDMI HW sync */ 120 DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
133 GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP, 121 DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
134 GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP, 122 DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
123 DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
124 DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
125 /*
126 * The following pin sets were known as "runtime pins" before being
127 * converted to the pinctrl model. Here we model them as "default"
128 * states.
129 */
130 /* Mux in UART0 after initialization */
131 DB8500_MUX("u0_a_1", "u0", "uart0"),
132 DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
133 DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
134 DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
135 DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
136 /* UART0 sleep state */
137 DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
138 DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
139 DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
140 DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
141 /* MSP1 for ALSA codec */
142 DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
143 DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
144 DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
145 DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
146 DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
147 DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
148 /* MSP1 sleep state */
149 DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
150 DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
151 DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
152 DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
153 /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
154 DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
155 DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
156 /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
157 DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
158 /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
159 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
160 DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
161 DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
162 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
163 DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
164 DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
165 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
166 DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
167 DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
168 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
169 DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
170 DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
171 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
172 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
173 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
174 DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
175 DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
176 DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
177 DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
178 DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
179 DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
180 DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
181 DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
182 DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
183 /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
184 DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
185 DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
186 DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
187 DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
188 DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
189 DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
190 DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
191 DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
192 /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
193 DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
194 DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
195 DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
196 DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
197 DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
198 DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
199 DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
200 DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
201 DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
202 DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
203 DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
204 DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
205 /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
206 DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
207 DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
208 DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
209 DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
210 DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
211 DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
212 DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
213 DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
214 DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
215 DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
216 DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
217 DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
218 /* Mux in USB pins, drive STP high */
219 DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
220 DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
221 /* Mux in SPI2 pins on the "other C1" altfunction */
222 DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
223 DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
224 DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
225 DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
226 DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
135}; 227};
136 228
137static pin_cfg_t mop500_pins_default[] = { 229/*
138 /* SSP0 */ 230 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
139 GPIO143_SSP0_CLK, 231 * board, which utilized a TC35892 GPIO expander instead of using a lot of
140 GPIO144_SSP0_FRM, 232 * on-chip pins as the HREFv60 and later does.
141 GPIO145_SSP0_RXD | PIN_PULL_DOWN, 233 */
142 GPIO146_SSP0_TXD, 234static struct pinctrl_map __initdata mop500_pinmap[] = {
143 235 /* Mux in SSP0, pull down RXD pin */
144 236 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
145 GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */ 237 DB8500_PIN_HOG("GPIO145_C13", pd),
146 238 /*
147 /* SDI0 (MicroSD card) */ 239 * XENON Flashgun on image processor GPIO (controlled from image
148 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, 240 * processor firmware), mux in these image processor GPIO lines 0
149 241 * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
150 /* UART */ 242 * the pins.
151 GPIO4_U1_RXD | PIN_INPUT_PULLUP, 243 */
152 GPIO5_U1_TXD | PIN_OUTPUT_HIGH, 244 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
153 GPIO6_U1_CTSn | PIN_INPUT_PULLUP, 245 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
154 GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, 246 DB8500_PIN_HOG("GPIO6_AF6", in_pu),
247 DB8500_PIN_HOG("GPIO7_AG5", in_pu),
248 /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
249 DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
250 /* Mux in UART1 and set the pull-ups */
251 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
252 DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
253 DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
254 DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
255 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
256 DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
257 /*
258 * Runtime stuff: make it possible to mux in the SKE keypad
259 * and bias the pins
260 */
261 DB8500_MUX("kp_a_2", "kp", "ske"),
262 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
263 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
264 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
265 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
266 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
267 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
268 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
269 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
270 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
271 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
272 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
273 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
274 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
275 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
276 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
277 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
278 /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
279 DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
280 DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
155}; 281};
156 282
157static pin_cfg_t hrefv60_pins[] = { 283/*
158 /* WLAN */ 284 * The HREFv60 series of platforms is using available pins on the DB8500
159 GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ 285 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
160 GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ 286 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
161 287 */
162 /* XENON Flashgun INTERFACE */ 288static struct pinctrl_map __initdata hrefv60_pinmap[] = {
163 GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */ 289 /* Drive WLAN_ENA low */
164 GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */ 290 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
165 GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */ 291 /*
166 292 * XENON Flashgun on image processor GPIO (controlled from image
167 /* Assistant LED INTERFACE */ 293 * processor firmware), mux in these image processor GPIO lines 0
168 GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */ 294 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
169 GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */ 295 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
170 296 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
171 /* Magnetometer */ 297 */
172 GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */ 298 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
173 GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */ 299 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
174 300 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
175 /* Display Interface */ 301 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
176 GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */ 302 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
177 GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */ 303 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
178 304 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
179 /* Touch screen INTERFACE */ 305 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
180 GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */ 306 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
181 307 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
182 /* Touch screen INTERFACE 2 */ 308 /*
183 GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */ 309 * Display Interface 1 uses GPIO 65 for RST (reset).
184 GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */ 310 * Display Interface 2 uses GPIO 66 for RST (reset).
185 311 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
186 /* ETM_PTM_TRACE INTERFACE */ 312 */
187 GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */ 313 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
188 GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */ 314 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
189 GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */ 315 /*
190 GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */ 316 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
191 GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */ 317 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
192 318 * reset signals low.
193 /* NAHJ INTERFACE */ 319 */
194 GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */ 320 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
195 GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */ 321 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
196 322 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
197 /* NFC INTERFACE */ 323 /*
198 GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */ 324 * Drive D19-D23 for the ETM PTM trace interface low,
199 GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */ 325 * (presumably pins are unconnected therefore grounded here,
200 GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */ 326 * the "other alt C1" setting enables these pins)
201 327 */
202 /* Keyboard MATRIX INTERFACE */ 328 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
203 GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */ 329 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
204 GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */ 330 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
205 GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */ 331 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
206 GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */ 332 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
207 GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */ 333 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
208 GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */ 334 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
209 GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */ 335 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
210 GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */ 336 /* NFC ENA and RESET to low, pulldown IRQ line */
211 GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */ 337 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
212 GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */ 338 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
213 GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */ 339 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
214 340 /*
215 /* DiPro Sensor Interface */ 341 * SKE keyboard partly on alt A and partly on "Other alt C1"
216 GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */ 342 * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
217 343 * rows of 6 keys, then pull up force sensing interrup and
218 /* HAL SWITCH INTERFACE */ 344 * drive reset and force sensing WU low.
219 GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */ 345 */
220 346 DB8500_MUX_HOG("kp_a_1", "kp"),
221 /* Audio Amplifier Interface */ 347 DB8500_MUX_HOG("kp_oc1_1", "kp"),
222 GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */ 348 DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
223 349 DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
224 /* GBF INTERFACE */ 350 DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
225 GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */ 351 DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
226 352 DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
227 /* MSP : HDTV INTERFACE */ 353 DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
228 GPIO192_GPIO | PIN_INPUT_PULLDOWN, 354 DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
229 355 DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
230 /* ACCELEROMETER_INTERFACE */ 356 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
231 GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */ 357 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
232 GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */ 358 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
233 359 /* DiPro Sensor interrupt */
234 /* Proximity Sensor */ 360 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
235 GPIO217_GPIO | PIN_INPUT_PULLUP, 361 /* Audio Amplifier HF enable */
236 362 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
237 363 /* GBF interface, pull low to reset state */
364 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
365 /* MSP : HDTV INTERFACE GPIO line */
366 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
367 /* Accelerometer interrupt lines */
368 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
369 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
370 /* SD card detect GPIO pin */
371 DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
372 /*
373 * Runtime stuff
374 * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
375 * etc.
376 */
377 DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
378 DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
379 DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
380 /*
381 * Make it possible to mux in the SKE keypad and bias the pins
382 * FIXME: what's the point with this on HREFv60? KP/SKE is already
383 * muxed in at another place! Enabling this will bork.
384 */
385 DB8500_MUX("kp_a_2", "kp", "ske"),
386 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
387 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
388 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
389 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
390 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
391 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
392 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
393 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
394 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
395 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
396 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
397 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
398 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
399 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
400 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
401 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
238}; 402};
239 403
240static pin_cfg_t snowball_pins[] = { 404static struct pinctrl_map __initdata u9500_pinmap[] = {
241 /* SSP0, to AB8500 */ 405 /* Mux in UART1 (just RX/TX) and set the pull-ups */
242 GPIO143_SSP0_CLK, 406 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
243 GPIO144_SSP0_FRM, 407 DB8500_PIN_HOG("GPIO4_AH6", in_pu),
244 GPIO145_SSP0_RXD | PIN_PULL_DOWN, 408 DB8500_PIN_HOG("GPIO5_AG6", out_hi),
245 GPIO146_SSP0_TXD, 409 /* WLAN_IRQ line */
410 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
411 /* HSI */
412 DB8500_MUX_HOG("hsir_a_1", "hsi"),
413 DB8500_MUX_HOG("hsit_a_1", "hsi"),
414 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
415 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
416 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
417 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
418 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
419 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
420 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
421 DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
422};
246 423
247 /* MMC0: MicroSD card */ 424static struct pinctrl_map __initdata u8500_pinmap[] = {
248 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, 425 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
426 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
427};
249 428
250 /* MMC2: LAN */ 429static struct pinctrl_map __initdata snowball_pinmap[] = {
251 GPIO86_SM_ADQ0, 430 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
252 GPIO87_SM_ADQ1, 431 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
253 GPIO88_SM_ADQ2, 432 DB8500_PIN_HOG("GPIO145_C13", pd),
254 GPIO89_SM_ADQ3, 433 /* Always drive the MC0 DAT31DIR line high on these boards */
255 GPIO90_SM_ADQ4, 434 DB8500_PIN_HOG("GPIO21_AB3", out_hi),
256 GPIO91_SM_ADQ5, 435 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
257 GPIO92_SM_ADQ6, 436 DB8500_MUX_HOG("sm_b_1", "sm"),
258 GPIO93_SM_ADQ7, 437 /* Drive RSTn_LAN high */
438 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
439 /* Accelerometer/Magnetometer */
440 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
441 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
442 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
443 /* WLAN/GBF */
444 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
445 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
446 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
447 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
448};
259 449
260 GPIO94_SM_ADVn, 450/*
261 GPIO95_SM_CS0n, 451 * passing "pinsfor=" in kernel cmdline allows for custom
262 GPIO96_SM_OEn, 452 * configuration of GPIOs on u8500 derived boards.
263 GPIO97_SM_WEn, 453 */
454static int __init early_pinsfor(char *p)
455{
456 pinsfor = PINS_FOR_DEFAULT;
264 457
265 GPIO128_SM_CKO, 458 if (strcmp(p, "u9500-21") == 0)
266 GPIO130_SM_FBCLK, 459 pinsfor = PINS_FOR_U9500;
267 GPIO131_SM_ADQ8,
268 GPIO132_SM_ADQ9,
269 GPIO133_SM_ADQ10,
270 GPIO134_SM_ADQ11,
271 GPIO135_SM_ADQ12,
272 GPIO136_SM_ADQ13,
273 GPIO137_SM_ADQ14,
274 GPIO138_SM_ADQ15,
275 460
276 /* RSTn_LAN */ 461 return 0;
277 GPIO141_GPIO | PIN_OUTPUT_HIGH, 462}
278}; 463early_param("pinsfor", early_pinsfor);
279 464
280void __init mop500_pins_init(void) 465int pins_for_u9500(void)
281{ 466{
282 nmk_config_pins(mop500_pins_common, 467 if (pinsfor == PINS_FOR_U9500)
283 ARRAY_SIZE(mop500_pins_common)); 468 return 1;
284 469
285 nmk_config_pins(mop500_pins_default, 470 return 0;
286 ARRAY_SIZE(mop500_pins_default));
287} 471}
288 472
289void __init snowball_pins_init(void) 473static void __init mop500_href_family_pinmaps_init(void)
290{ 474{
291 nmk_config_pins(mop500_pins_common, 475 switch (pinsfor) {
292 ARRAY_SIZE(mop500_pins_common)); 476 case PINS_FOR_U9500:
477 pinctrl_register_mappings(u9500_pinmap,
478 ARRAY_SIZE(u9500_pinmap));
479 break;
480 case PINS_FOR_DEFAULT:
481 pinctrl_register_mappings(u8500_pinmap,
482 ARRAY_SIZE(u8500_pinmap));
483 default:
484 break;
485 }
486}
293 487
294 nmk_config_pins(snowball_pins, 488void __init mop500_pinmaps_init(void)
295 ARRAY_SIZE(snowball_pins)); 489{
490 pinctrl_register_mappings(mop500_family_pinmap,
491 ARRAY_SIZE(mop500_family_pinmap));
492 pinctrl_register_mappings(mop500_pinmap,
493 ARRAY_SIZE(mop500_pinmap));
494 mop500_href_family_pinmaps_init();
296} 495}
297 496
298void __init hrefv60_pins_init(void) 497void __init snowball_pinmaps_init(void)
299{ 498{
300 nmk_config_pins(mop500_pins_common, 499 pinctrl_register_mappings(mop500_family_pinmap,
301 ARRAY_SIZE(mop500_pins_common)); 500 ARRAY_SIZE(mop500_family_pinmap));
501 pinctrl_register_mappings(snowball_pinmap,
502 ARRAY_SIZE(snowball_pinmap));
503 pinctrl_register_mappings(u8500_pinmap,
504 ARRAY_SIZE(u8500_pinmap));
505}
302 506
303 nmk_config_pins(hrefv60_pins, 507void __init hrefv60_pinmaps_init(void)
304 ARRAY_SIZE(hrefv60_pins)); 508{
509 pinctrl_register_mappings(mop500_family_pinmap,
510 ARRAY_SIZE(mop500_family_pinmap));
511 pinctrl_register_mappings(hrefv60_pinmap,
512 ARRAY_SIZE(hrefv60_pinmap));
513 mop500_href_family_pinmaps_init();
305} 514}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f8150155a44..4bc0cbc5f07 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * Copyright (C) 2008-2009 ST-Ericsson 3 * Copyright (C) 2008-2009 ST-Ericsson
3 * 4 *
@@ -29,18 +30,17 @@
29#include <linux/smsc911x.h> 30#include <linux/smsc911x.h>
30#include <linux/gpio_keys.h> 31#include <linux/gpio_keys.h>
31#include <linux/delay.h> 32#include <linux/delay.h>
32
33#include <linux/of.h> 33#include <linux/of.h>
34#include <linux/of_platform.h> 34#include <linux/of_platform.h>
35
36#include <linux/leds.h> 35#include <linux/leds.h>
36#include <linux/pinctrl/consumer.h>
37
37#include <asm/mach-types.h> 38#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
39#include <asm/hardware/gic.h> 40#include <asm/hardware/gic.h>
40 41
41#include <plat/i2c.h> 42#include <plat/i2c.h>
42#include <plat/ste_dma40.h> 43#include <plat/ste_dma40.h>
43#include <plat/pincfg.h>
44#include <plat/gpio-nomadik.h> 44#include <plat/gpio-nomadik.h>
45 45
46#include <mach/hardware.h> 46#include <mach/hardware.h>
@@ -48,11 +48,11 @@
48#include <mach/devices.h> 48#include <mach/devices.h>
49#include <mach/irqs.h> 49#include <mach/irqs.h>
50 50
51#include "pins-db8500.h"
52#include "ste-dma40-db8500.h" 51#include "ste-dma40-db8500.h"
53#include "devices-db8500.h" 52#include "devices-db8500.h"
54#include "board-mop500.h" 53#include "board-mop500.h"
55#include "board-mop500-regulators.h" 54#include "board-mop500-regulators.h"
55#include "board-mop500-msp.h"
56 56
57static struct gpio_led snowball_led_array[] = { 57static struct gpio_led snowball_led_array[] = {
58 { 58 {
@@ -520,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
520}; 520};
521#endif 521#endif
522 522
523
524static pin_cfg_t mop500_pins_uart0[] = {
525 GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
526 GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
527 GPIO2_U0_RXD | PIN_INPUT_PULLUP,
528 GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
529};
530
531#define PRCC_K_SOFTRST_SET 0x18 523#define PRCC_K_SOFTRST_SET 0x18
532#define PRCC_K_SOFTRST_CLEAR 0x1C 524#define PRCC_K_SOFTRST_CLEAR 0x1C
533static void ux500_uart0_reset(void) 525static void ux500_uart0_reset(void)
@@ -548,24 +540,33 @@ static void ux500_uart0_reset(void)
548 udelay(1); 540 udelay(1);
549} 541}
550 542
543/* This needs to be referenced by callbacks */
544struct pinctrl *u0_p;
545struct pinctrl_state *u0_def;
546struct pinctrl_state *u0_sleep;
547
551static void ux500_uart0_init(void) 548static void ux500_uart0_init(void)
552{ 549{
553 int ret; 550 int ret;
554 551
555 ret = nmk_config_pins(mop500_pins_uart0, 552 if (IS_ERR(u0_p) || IS_ERR(u0_def))
556 ARRAY_SIZE(mop500_pins_uart0)); 553 return;
557 if (ret < 0) 554
558 pr_err("pl011: uart pins_enable failed\n"); 555 ret = pinctrl_select_state(u0_p, u0_def);
556 if (ret)
557 pr_err("could not set UART0 defstate\n");
559} 558}
560 559
561static void ux500_uart0_exit(void) 560static void ux500_uart0_exit(void)
562{ 561{
563 int ret; 562 int ret;
564 563
565 ret = nmk_config_pins_sleep(mop500_pins_uart0, 564 if (IS_ERR(u0_p) || IS_ERR(u0_sleep))
566 ARRAY_SIZE(mop500_pins_uart0)); 565 return;
567 if (ret < 0) 566
568 pr_err("pl011: uart pins_disable failed\n"); 567 ret = pinctrl_select_state(u0_p, u0_sleep);
568 if (ret)
569 pr_err("could not set UART0 idlestate\n");
569} 570}
570 571
571static struct amba_pl011_data uart0_plat = { 572static struct amba_pl011_data uart0_plat = {
@@ -597,7 +598,28 @@ static struct amba_pl011_data uart2_plat = {
597 598
598static void __init mop500_uart_init(struct device *parent) 599static void __init mop500_uart_init(struct device *parent)
599{ 600{
600 db8500_add_uart0(parent, &uart0_plat); 601 struct amba_device *uart0_device;
602
603 uart0_device = db8500_add_uart0(parent, &uart0_plat);
604 if (uart0_device) {
605 u0_p = pinctrl_get(&uart0_device->dev);
606 if (IS_ERR(u0_p))
607 dev_err(&uart0_device->dev,
608 "could not get UART0 pinctrl\n");
609 else {
610 u0_def = pinctrl_lookup_state(u0_p,
611 PINCTRL_STATE_DEFAULT);
612 if (IS_ERR(u0_def)) {
613 dev_err(&uart0_device->dev,
614 "could not get UART0 defstate\n");
615 }
616 u0_sleep = pinctrl_lookup_state(u0_p,
617 PINCTRL_STATE_SLEEP);
618 if (IS_ERR(u0_sleep))
619 dev_err(&uart0_device->dev,
620 "could not get UART0 idlestate\n");
621 }
622 }
601 db8500_add_uart1(parent, &uart1_plat); 623 db8500_add_uart1(parent, &uart1_plat);
602 db8500_add_uart2(parent, &uart2_plat); 624 db8500_add_uart2(parent, &uart2_plat);
603} 625}
@@ -616,10 +638,9 @@ static void __init mop500_init_machine(void)
616 638
617 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 639 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
618 640
641 mop500_pinmaps_init();
619 parent = u8500_init_devices(); 642 parent = u8500_init_devices();
620 643
621 mop500_pins_init();
622
623 /* FIXME: parent of ab8500 should be prcmu */ 644 /* FIXME: parent of ab8500 should be prcmu */
624 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 645 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
625 mop500_platform_devs[i]->dev.parent = parent; 646 mop500_platform_devs[i]->dev.parent = parent;
@@ -630,6 +651,7 @@ static void __init mop500_init_machine(void)
630 mop500_i2c_init(parent); 651 mop500_i2c_init(parent);
631 mop500_sdi_init(parent); 652 mop500_sdi_init(parent);
632 mop500_spi_init(parent); 653 mop500_spi_init(parent);
654 mop500_msp_init(parent);
633 mop500_uart_init(parent); 655 mop500_uart_init(parent);
634 656
635 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 657 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -647,10 +669,9 @@ static void __init snowball_init_machine(void)
647 struct device *parent = NULL; 669 struct device *parent = NULL;
648 int i; 670 int i;
649 671
672 snowball_pinmaps_init();
650 parent = u8500_init_devices(); 673 parent = u8500_init_devices();
651 674
652 snowball_pins_init();
653
654 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) 675 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
655 snowball_platform_devs[i]->dev.parent = parent; 676 snowball_platform_devs[i]->dev.parent = parent;
656 677
@@ -660,6 +681,7 @@ static void __init snowball_init_machine(void)
660 mop500_i2c_init(parent); 681 mop500_i2c_init(parent);
661 snowball_sdi_init(parent); 682 snowball_sdi_init(parent);
662 mop500_spi_init(parent); 683 mop500_spi_init(parent);
684 mop500_msp_init(parent);
663 mop500_uart_init(parent); 685 mop500_uart_init(parent);
664 686
665 /* This board has full regulator constraints */ 687 /* This board has full regulator constraints */
@@ -679,10 +701,9 @@ static void __init hrefv60_init_machine(void)
679 */ 701 */
680 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 702 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
681 703
704 hrefv60_pinmaps_init();
682 parent = u8500_init_devices(); 705 parent = u8500_init_devices();
683 706
684 hrefv60_pins_init();
685
686 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 707 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
687 mop500_platform_devs[i]->dev.parent = parent; 708 mop500_platform_devs[i]->dev.parent = parent;
688 709
@@ -692,6 +713,7 @@ static void __init hrefv60_init_machine(void)
692 mop500_i2c_init(parent); 713 mop500_i2c_init(parent);
693 hrefv60_sdi_init(parent); 714 hrefv60_sdi_init(parent);
694 mop500_spi_init(parent); 715 mop500_spi_init(parent);
716 mop500_msp_init(parent);
695 mop500_uart_init(parent); 717 mop500_uart_init(parent);
696 718
697 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 719 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -739,10 +761,22 @@ MACHINE_END
739#ifdef CONFIG_MACH_UX500_DT 761#ifdef CONFIG_MACH_UX500_DT
740 762
741struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 763struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
764 /* Requires DMA and call-back bindings. */
742 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 765 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
743 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 766 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
744 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 767 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
768 /* Requires DMA bindings. */
745 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 769 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
770 /* Requires clock name bindings. */
771 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
772 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
773 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
774 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
775 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
776 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
777 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
778 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
779 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
746 {}, 780 {},
747}; 781};
748 782
@@ -759,6 +793,14 @@ static void __init u8500_init_machine(void)
759 int i2c0_devs; 793 int i2c0_devs;
760 int i; 794 int i;
761 795
796 /* Pinmaps must be in place before devices register */
797 if (of_machine_is_compatible("st-ericsson,mop500"))
798 mop500_pinmaps_init();
799 else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
800 snowball_pinmaps_init();
801 else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
802 hrefv60_pinmaps_init();
803
762 parent = u8500_init_devices(); 804 parent = u8500_init_devices();
763 805
764 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 806 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
@@ -771,7 +813,6 @@ static void __init u8500_init_machine(void)
771 813
772 if (of_machine_is_compatible("st-ericsson,mop500")) { 814 if (of_machine_is_compatible("st-ericsson,mop500")) {
773 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 815 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
774 mop500_pins_init();
775 816
776 platform_add_devices(mop500_platform_devs, 817 platform_add_devices(mop500_platform_devs,
777 ARRAY_SIZE(mop500_platform_devs)); 818 ARRAY_SIZE(mop500_platform_devs));
@@ -784,7 +825,6 @@ static void __init u8500_init_machine(void)
784 ARRAY_SIZE(mop500_i2c2_devices)); 825 ARRAY_SIZE(mop500_i2c2_devices));
785 826
786 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { 827 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
787 snowball_pins_init();
788 platform_add_devices(snowball_platform_devs, 828 platform_add_devices(snowball_platform_devs,
789 ARRAY_SIZE(snowball_platform_devs)); 829 ARRAY_SIZE(snowball_platform_devs));
790 830
@@ -796,7 +836,6 @@ static void __init u8500_init_machine(void)
796 * instead. 836 * instead.
797 */ 837 */
798 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 838 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
799 hrefv60_pins_init();
800 platform_add_devices(mop500_platform_devs, 839 platform_add_devices(mop500_platform_devs,
801 ARRAY_SIZE(mop500_platform_devs)); 840 ARRAY_SIZE(mop500_platform_devs));
802 841
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index fdcfa8721bb..bc44c07c71a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,9 @@
7#ifndef __BOARD_MOP500_H 7#ifndef __BOARD_MOP500_H
8#define __BOARD_MOP500_H 8#define __BOARD_MOP500_H
9 9
10/* For NOMADIK_NR_GPIO */
11#include <mach/irqs.h>
12
10/* Snowball specific GPIO assignments, this board has no GPIO expander */ 13/* Snowball specific GPIO assignments, this board has no GPIO expander */
11#define SNOWBALL_ACCEL_INT1_GPIO 163 14#define SNOWBALL_ACCEL_INT1_GPIO 163
12#define SNOWBALL_ACCEL_INT2_GPIO 164 15#define SNOWBALL_ACCEL_INT2_GPIO 164
@@ -73,6 +76,7 @@
73#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ 76#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */
74#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ 77#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */
75 78
79struct device;
76struct i2c_board_info; 80struct i2c_board_info;
77 81
78extern void mop500_sdi_init(struct device *parent); 82extern void mop500_sdi_init(struct device *parent);
@@ -81,9 +85,9 @@ extern void hrefv60_sdi_init(struct device *parent);
81extern void mop500_sdi_tc35892_init(struct device *parent); 85extern void mop500_sdi_tc35892_init(struct device *parent);
82void __init mop500_u8500uib_init(void); 86void __init mop500_u8500uib_init(void);
83void __init mop500_stuib_init(void); 87void __init mop500_stuib_init(void);
84void __init mop500_pins_init(void); 88void __init mop500_pinmaps_init(void);
85void __init hrefv60_pins_init(void); 89void __init snowball_pinmaps_init(void);
86void __init snowball_pins_init(void); 90void __init hrefv60_pinmaps_init(void);
87 91
88void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 92void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
89 unsigned n); 93 unsigned n);
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 063f3dbd45a..a121cb472dd 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -334,6 +334,7 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
334 */ 334 */
335 335
336/* Peripheral Cluster #1 */ 336/* Peripheral Cluster #1 */
337static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
337static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); 338static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
338static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); 339static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
339static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); 340static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
@@ -403,7 +404,7 @@ static struct clk_lookup u8500_clks[] = {
403 CLK(slimbus0, "slimbus0", NULL), 404 CLK(slimbus0, "slimbus0", NULL),
404 CLK(i2c2, "nmk-i2c.2", NULL), 405 CLK(i2c2, "nmk-i2c.2", NULL),
405 CLK(sdi0, "sdi0", NULL), 406 CLK(sdi0, "sdi0", NULL),
406 CLK(msp0, "msp0", NULL), 407 CLK(msp0, "ux500-msp-i2s.0", NULL),
407 CLK(i2c1, "nmk-i2c.1", NULL), 408 CLK(i2c1, "nmk-i2c.1", NULL),
408 CLK(uart1, "uart1", NULL), 409 CLK(uart1, "uart1", NULL),
409 CLK(uart0, "uart0", NULL), 410 CLK(uart0, "uart0", NULL),
@@ -453,7 +454,8 @@ static struct clk_lookup u8500_clks[] = {
453 /* Peripheral Cluster #1 */ 454 /* Peripheral Cluster #1 */
454 CLK(i2c4, "nmk-i2c.4", NULL), 455 CLK(i2c4, "nmk-i2c.4", NULL),
455 CLK(spi3, "spi3", NULL), 456 CLK(spi3, "spi3", NULL),
456 CLK(msp1, "msp1", NULL), 457 CLK(msp1, "ux500-msp-i2s.1", NULL),
458 CLK(msp3, "ux500-msp-i2s.3", NULL),
457 459
458 /* Peripheral Cluster #2 */ 460 /* Peripheral Cluster #2 */
459 CLK(gpio1, "gpio.6", NULL), 461 CLK(gpio1, "gpio.6", NULL),
@@ -463,7 +465,7 @@ static struct clk_lookup u8500_clks[] = {
463 CLK(spi0, "spi0", NULL), 465 CLK(spi0, "spi0", NULL),
464 CLK(sdi3, "sdi3", NULL), 466 CLK(sdi3, "sdi3", NULL),
465 CLK(sdi1, "sdi1", NULL), 467 CLK(sdi1, "sdi1", NULL),
466 CLK(msp2, "msp2", NULL), 468 CLK(msp2, "ux500-msp-i2s.2", NULL),
467 CLK(sdi4, "sdi4", NULL), 469 CLK(sdi4, "sdi4", NULL),
468 CLK(pwl, "pwl", NULL), 470 CLK(pwl, "pwl", NULL),
469 CLK(spi1, "spi1", NULL), 471 CLK(spi1, "spi1", NULL),
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 76a7503a11a..16169c4bf6c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -163,6 +163,7 @@ static void __init db8500_add_gpios(struct device *parent)
163 163
164 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 164 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
165 IRQ_DB8500_GPIO0, &pdata); 165 IRQ_DB8500_GPIO0, &pdata);
166 dbx500_add_pinctrl(parent, "pinctrl-db8500");
166} 167}
167 168
168static int usb_db8500_rx_dma_cfg[] = { 169static int usb_db8500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 0982279f51f..a29a0e3adcf 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -29,6 +29,18 @@
29 29
30void __iomem *_PRCMU_BASE; 30void __iomem *_PRCMU_BASE;
31 31
32/*
33 * FIXME: Should we set up the GPIO domain here?
34 *
35 * The problem is that we cannot put the interrupt resources into the platform
36 * device until the irqdomain has been added. Right now, we set the GIC interrupt
37 * domain from init_irq(), then load the gpio driver from
38 * core_initcall(nmk_gpio_init) and add the platform devices from
39 * arch_initcall(customize_machine).
40 *
41 * This feels fragile because it depends on the gpio device getting probed
42 * _before_ any device uses the gpio interrupts.
43*/
32static const struct of_device_id ux500_dt_irq_match[] = { 44static const struct of_device_id ux500_dt_irq_match[] = {
33 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 45 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
34 {}, 46 {},
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index f75bcb2ab13..7cbccfd9e15 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -90,4 +90,16 @@ struct nmk_gpio_platform_data;
90void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, 90void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
91 int irq, struct nmk_gpio_platform_data *pdata); 91 int irq, struct nmk_gpio_platform_data *pdata);
92 92
93static inline void
94dbx500_add_pinctrl(struct device *parent, const char *name)
95{
96 struct platform_device_info pdevinfo = {
97 .parent = parent,
98 .name = name,
99 .id = -1,
100 };
101
102 platform_device_register_full(&pdevinfo);
103}
104
93#endif 105#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 6fc7eb24d9a..0b9677a95bb 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -34,7 +34,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
34 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); 34 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
35} 35}
36 36
37
38#define db8500_add_i2c0(parent, pdata) \ 37#define db8500_add_i2c0(parent, pdata) \
39 dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) 38 dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
40#define db8500_add_i2c1(parent, pdata) \ 39#define db8500_add_i2c1(parent, pdata) \
@@ -46,15 +45,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
46#define db8500_add_i2c4(parent, pdata) \ 45#define db8500_add_i2c4(parent, pdata) \
47 dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) 46 dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
48 47
49#define db8500_add_msp0_i2s(parent, pdata) \
50 dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
51#define db8500_add_msp1_i2s(parent, pdata) \
52 dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
53#define db8500_add_msp2_i2s(parent, pdata) \
54 dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
55#define db8500_add_msp3_i2s(parent, pdata) \
56 dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
57
58#define db8500_add_msp0_spi(parent, pdata) \ 48#define db8500_add_msp0_spi(parent, pdata) \
59 dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \ 49 dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
60 IRQ_DB8500_MSP0, pdata) 50 IRQ_DB8500_MSP0, pdata)
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
new file mode 100644
index 00000000000..798be19129e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __MSP_H
9#define __MSP_H
10
11#include <plat/ste_dma40.h>
12
13enum msp_i2s_id {
14 MSP_I2S_0 = 0,
15 MSP_I2S_1,
16 MSP_I2S_2,
17 MSP_I2S_3,
18};
19
20/* Platform data structure for a MSP I2S-device */
21struct msp_i2s_platform_data {
22 enum msp_i2s_id id;
23 struct stedma40_chan_cfg *msp_i2s_dma_rx;
24 struct stedma40_chan_cfg *msp_i2s_dma_tx;
25 int (*msp_i2s_init) (void);
26 int (*msp_i2s_exit) (void);
27};
28
29#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 8b1d1a7a679..062c7acf457 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -35,40 +35,40 @@
35 35
36#define GPIO4_GPIO PIN_CFG(4, GPIO) 36#define GPIO4_GPIO PIN_CFG(4, GPIO)
37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) 37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
38#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP) 38#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B)
39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) 39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
40 40
41#define GPIO5_GPIO PIN_CFG(5, GPIO) 41#define GPIO5_GPIO PIN_CFG(5, GPIO)
42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) 42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
43#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP) 43#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B)
44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) 44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
45 45
46#define GPIO6_GPIO PIN_CFG(6, GPIO) 46#define GPIO6_GPIO PIN_CFG(6, GPIO)
47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) 47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
48#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP) 48#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B)
49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) 49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
50 50
51#define GPIO7_GPIO PIN_CFG(7, GPIO) 51#define GPIO7_GPIO PIN_CFG(7, GPIO)
52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) 52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
53#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP) 53#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B)
54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) 54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
55 55
56#define GPIO8_GPIO PIN_CFG(8, GPIO) 56#define GPIO8_GPIO PIN_CFG(8, GPIO)
57#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP) 57#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A)
58#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP) 58#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B)
59 59
60#define GPIO9_GPIO PIN_CFG(9, GPIO) 60#define GPIO9_GPIO PIN_CFG(9, GPIO)
61#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP) 61#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A)
62#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP) 62#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B)
63 63
64#define GPIO10_GPIO PIN_CFG(10, GPIO) 64#define GPIO10_GPIO PIN_CFG(10, GPIO)
65#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP) 65#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A)
66#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP) 66#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B)
67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) 67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
68 68
69#define GPIO11_GPIO PIN_CFG(11, GPIO) 69#define GPIO11_GPIO PIN_CFG(11, GPIO)
70#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP) 70#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A)
71#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP) 71#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B)
72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) 72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
73 73
74#define GPIO12_GPIO PIN_CFG(12, GPIO) 74#define GPIO12_GPIO PIN_CFG(12, GPIO)
@@ -87,12 +87,12 @@
87 87
88#define GPIO16_GPIO PIN_CFG(16, GPIO) 88#define GPIO16_GPIO PIN_CFG(16, GPIO)
89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) 89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
90#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP) 90#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B)
91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) 91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
92 92
93#define GPIO17_GPIO PIN_CFG(17, GPIO) 93#define GPIO17_GPIO PIN_CFG(17, GPIO)
94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) 94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
95#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP) 95#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B)
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) 96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97 97
98#define GPIO18_GPIO PIN_CFG(18, GPIO) 98#define GPIO18_GPIO PIN_CFG(18, GPIO)
@@ -434,10 +434,10 @@
434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) 434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
435 435
436#define GPIO147_GPIO PIN_CFG(147, GPIO) 436#define GPIO147_GPIO PIN_CFG(147, GPIO)
437#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP) 437#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A)
438 438
439#define GPIO148_GPIO PIN_CFG(148, GPIO) 439#define GPIO148_GPIO PIN_CFG(148, GPIO)
440#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP) 440#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A)
441 441
442#define GPIO149_GPIO PIN_CFG(149, GPIO) 442#define GPIO149_GPIO PIN_CFG(149, GPIO)
443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) 443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
@@ -459,82 +459,82 @@
459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) 459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
460 460
461#define GPIO153_GPIO PIN_CFG(153, GPIO) 461#define GPIO153_GPIO PIN_CFG(153, GPIO)
462#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN) 462#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) 463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) 464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
465 465
466#define GPIO154_GPIO PIN_CFG(154, GPIO) 466#define GPIO154_GPIO PIN_CFG(154, GPIO)
467#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN) 467#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) 468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) 469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
470 470
471#define GPIO155_GPIO PIN_CFG(155, GPIO) 471#define GPIO155_GPIO PIN_CFG(155, GPIO)
472#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN) 472#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) 473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) 474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
475 475
476#define GPIO156_GPIO PIN_CFG(156, GPIO) 476#define GPIO156_GPIO PIN_CFG(156, GPIO)
477#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN) 477#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) 478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) 479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
480 480
481#define GPIO157_GPIO PIN_CFG(157, GPIO) 481#define GPIO157_GPIO PIN_CFG(157, GPIO)
482#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP) 482#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) 483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) 484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
485 485
486#define GPIO158_GPIO PIN_CFG(158, GPIO) 486#define GPIO158_GPIO PIN_CFG(158, GPIO)
487#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP) 487#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) 488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) 489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
490 490
491#define GPIO159_GPIO PIN_CFG(159, GPIO) 491#define GPIO159_GPIO PIN_CFG(159, GPIO)
492#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP) 492#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) 493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) 494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
495 495
496#define GPIO160_GPIO PIN_CFG(160, GPIO) 496#define GPIO160_GPIO PIN_CFG(160, GPIO)
497#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP) 497#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) 498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
499#define GPIO160_NONE PIN_CFG(160, ALT_C) 499#define GPIO160_NONE PIN_CFG(160, ALT_C)
500 500
501#define GPIO161_GPIO PIN_CFG(161, GPIO) 501#define GPIO161_GPIO PIN_CFG(161, GPIO)
502#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN) 502#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) 503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) 504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
505 505
506#define GPIO162_GPIO PIN_CFG(162, GPIO) 506#define GPIO162_GPIO PIN_CFG(162, GPIO)
507#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN) 507#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) 508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) 509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
510 510
511#define GPIO163_GPIO PIN_CFG(163, GPIO) 511#define GPIO163_GPIO PIN_CFG(163, GPIO)
512#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN) 512#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) 513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) 514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
515 515
516#define GPIO164_GPIO PIN_CFG(164, GPIO) 516#define GPIO164_GPIO PIN_CFG(164, GPIO)
517#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP) 517#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) 518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) 519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
520 520
521#define GPIO165_GPIO PIN_CFG(165, GPIO) 521#define GPIO165_GPIO PIN_CFG(165, GPIO)
522#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP) 522#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) 523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) 524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
525 525
526#define GPIO166_GPIO PIN_CFG(166, GPIO) 526#define GPIO166_GPIO PIN_CFG(166, GPIO)
527#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP) 527#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) 528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) 529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
530 530
531#define GPIO167_GPIO PIN_CFG(167, GPIO) 531#define GPIO167_GPIO PIN_CFG(167, GPIO)
532#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP) 532#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) 533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) 534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
535 535
536#define GPIO168_GPIO PIN_CFG(168, GPIO) 536#define GPIO168_GPIO PIN_CFG(168, GPIO)
537#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP) 537#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) 538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
539#define GPIO168_NONE PIN_CFG(168, ALT_C) 539#define GPIO168_NONE PIN_CFG(168, ALT_C)
540 540
@@ -637,7 +637,7 @@
637#define GPIO216_GPIO PIN_CFG(216, GPIO) 637#define GPIO216_GPIO PIN_CFG(216, GPIO)
638#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) 638#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
639#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) 639#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
640#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP) 640#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C)
641#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C) 641#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C)
642 642
643#define GPIO217_GPIO PIN_CFG(217, GPIO) 643#define GPIO217_GPIO PIN_CFG(217, GPIO)
@@ -649,7 +649,7 @@
649#define GPIO218_GPIO PIN_CFG(218, GPIO) 649#define GPIO218_GPIO PIN_CFG(218, GPIO)
650#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) 650#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
651#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) 651#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
652#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP) 652#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C)
653#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C) 653#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C)
654 654
655#define GPIO219_GPIO PIN_CFG(219, GPIO) 655#define GPIO219_GPIO PIN_CFG(219, GPIO)
@@ -698,12 +698,12 @@
698#define GPIO229_GPIO PIN_CFG(229, GPIO) 698#define GPIO229_GPIO PIN_CFG(229, GPIO)
699#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) 699#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
700#define GPIO229_PWL PIN_CFG(229, ALT_B) 700#define GPIO229_PWL PIN_CFG(229, ALT_B)
701#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP) 701#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C)
702 702
703#define GPIO230_GPIO PIN_CFG(230, GPIO) 703#define GPIO230_GPIO PIN_CFG(230, GPIO)
704#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) 704#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
705#define GPIO230_PWL PIN_CFG(230, ALT_B) 705#define GPIO230_PWL PIN_CFG(230, ALT_B)
706#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP) 706#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C)
707 707
708#define GPIO256_GPIO PIN_CFG(256, GPIO) 708#define GPIO256_GPIO PIN_CFG(256, GPIO)
709#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) 709#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
index 9605bf227df..826de74bfdd 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
@@ -29,6 +29,7 @@
29#define NMK_GPIO_SLPC 0x1c 29#define NMK_GPIO_SLPC 0x1c
30#define NMK_GPIO_AFSLA 0x20 30#define NMK_GPIO_AFSLA 0x20
31#define NMK_GPIO_AFSLB 0x24 31#define NMK_GPIO_AFSLB 0x24
32#define NMK_GPIO_LOWEMI 0x28
32 33
33#define NMK_GPIO_RIMSC 0x40 34#define NMK_GPIO_RIMSC 0x40
34#define NMK_GPIO_FIMSC 0x44 35#define NMK_GPIO_FIMSC 0x44
@@ -61,7 +62,14 @@ enum nmk_gpio_slpm {
61 62
62extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); 63extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
63extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull); 64extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
65#ifdef CONFIG_PINCTRL_NOMADIK
64extern int nmk_gpio_set_mode(int gpio, int gpio_mode); 66extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
67#else
68static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
69{
70 return -ENODEV;
71}
72#endif
65extern int nmk_gpio_get_mode(int gpio); 73extern int nmk_gpio_get_mode(int gpio);
66 74
67extern void nmk_gpio_wakeups_suspend(void); 75extern void nmk_gpio_wakeups_suspend(void);
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 22cb97d2d8a..9c949c7c98a 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -24,6 +24,7 @@
24 * bit 16..18 - SLPM pull up/down state 24 * bit 16..18 - SLPM pull up/down state
25 * bit 19..20 - SLPM direction 25 * bit 19..20 - SLPM direction
26 * bit 21..22 - SLPM Value (if output) 26 * bit 21..22 - SLPM Value (if output)
27 * bit 23..25 - PDIS value (if input)
27 * 28 *
28 * to facilitate the definition, the following macros are provided 29 * to facilitate the definition, the following macros are provided
29 * 30 *
@@ -67,6 +68,10 @@ typedef unsigned long pin_cfg_t;
67/* These two replace the above in DB8500v2+ */ 68/* These two replace the above in DB8500v2+ */
68#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 69#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
69#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 70#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
71#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
72
73#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
74#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
70 75
71#define PIN_DIR_SHIFT 14 76#define PIN_DIR_SHIFT 14
72#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 77#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
@@ -105,6 +110,33 @@ typedef unsigned long pin_cfg_t;
105#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 110#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
106#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 111#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
107 112
113#define PIN_SLPM_PDIS_SHIFT 23
114#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
115#define PIN_SLPM_PDIS(x) \
116 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
117#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
118#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
119#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
120
121#define PIN_LOWEMI_SHIFT 25
122#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
123#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
124#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
125#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
126
127#define PIN_GPIOMODE_SHIFT 26
128#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
129#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
130#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
131#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
132
133#define PIN_SLEEPMODE_SHIFT 27
134#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
135#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
136#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
137#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
138
139
108/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 140/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
109#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 141#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
110#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 142#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 6c066fcb297..387655b5ce0 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -13,6 +13,7 @@ config ARCH_SPEAR3XX
13 select ARM_VIC 13 select ARM_VIC
14 select CPU_ARM926T 14 select CPU_ARM926T
15 select USE_OF 15 select USE_OF
16 select PINCTRL
16 help 17 help
17 Supports for ARM's SPEAR3XX family 18 Supports for ARM's SPEAR3XX family
18 19
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4af6258d0fe..7744802c83e 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,4 +5,4 @@
5# Common support 5# Common support
6obj-y := clock.o restart.o time.o pl080.o 6obj-y := clock.o restart.o time.o pl080.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf61..00000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.h
3 *
4 * SPEAr platform specific gpio pads muxing file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PADMUX_H
15#define __PLAT_PADMUX_H
16
17#include <linux/types.h>
18
19/*
20 * struct pmx_reg: configuration structure for mode reg and mux reg
21 *
22 * offset: offset of mode reg
23 * mask: mask of mode reg
24 */
25struct pmx_reg {
26 u32 offset;
27 u32 mask;
28};
29
30/*
31 * struct pmx_dev_mode: configuration structure every group of modes of a device
32 *
33 * ids: all modes for this configuration
34 * mask: mask for supported mode
35 */
36struct pmx_dev_mode {
37 u32 ids;
38 u32 mask;
39};
40
41/*
42 * struct pmx_mode: mode definition structure
43 *
44 * name: mode name
45 * mask: mode mask
46 */
47struct pmx_mode {
48 char *name;
49 u32 id;
50 u32 mask;
51};
52
53/*
54 * struct pmx_dev: device definition structure
55 *
56 * name: device name
57 * modes: device configuration array for different modes supported
58 * mode_count: size of modes array
59 * is_active: is peripheral active/enabled
60 * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61 */
62struct pmx_dev {
63 char *name;
64 struct pmx_dev_mode *modes;
65 u8 mode_count;
66 bool is_active;
67 bool enb_on_reset;
68};
69
70/*
71 * struct pmx_driver: driver definition structure
72 *
73 * mode: mode to be set
74 * devs: array of pointer to pmx devices
75 * devs_count: ARRAY_SIZE of devs
76 * base: base address of soc config registers
77 * mode_reg: structure of mode config register
78 * mux_reg: structure of device mux config register
79 */
80struct pmx_driver {
81 struct pmx_mode *mode;
82 struct pmx_dev **devs;
83 u8 devs_count;
84 u32 *base;
85 struct pmx_reg mode_reg;
86 struct pmx_reg mux_reg;
87};
88
89/* pmx functions */
90int pmx_register(struct pmx_driver *driver);
91
92#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1c..00000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.c
3 *
4 * SPEAr platform specific gpio pads muxing source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <plat/padmux.h>
18
19/*
20 * struct pmx: pmx definition structure
21 *
22 * base: base address of configuration registers
23 * mode_reg: mode configurations
24 * mux_reg: muxing configurations
25 * active_mode: pointer to current active mode
26 */
27struct pmx {
28 u32 base;
29 struct pmx_reg mode_reg;
30 struct pmx_reg mux_reg;
31 struct pmx_mode *active_mode;
32};
33
34static struct pmx *pmx;
35
36/**
37 * pmx_mode_set - Enables an multiplexing mode
38 * @mode - pointer to pmx mode
39 *
40 * It will set mode of operation in hardware.
41 * Returns -ve on Err otherwise 0
42 */
43static int pmx_mode_set(struct pmx_mode *mode)
44{
45 u32 val;
46
47 if (!mode->name)
48 return -EFAULT;
49
50 pmx->active_mode = mode;
51
52 val = readl(pmx->base + pmx->mode_reg.offset);
53 val &= ~pmx->mode_reg.mask;
54 val |= mode->mask & pmx->mode_reg.mask;
55 writel(val, pmx->base + pmx->mode_reg.offset);
56
57 return 0;
58}
59
60/**
61 * pmx_devs_enable - Enables list of devices
62 * @devs - pointer to pmx device array
63 * @count - number of devices to enable
64 *
65 * It will enable pads for all required peripherals once and only once.
66 * If peripheral is not supported by current mode then request is rejected.
67 * Conflicts between peripherals are not handled and peripherals will be
68 * enabled in the order they are present in pmx_dev array.
69 * In case of conflicts last peripheral enabled will be present.
70 * Returns -ve on Err otherwise 0
71 */
72static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73{
74 u32 val, i, mask;
75
76 if (!count)
77 return -EINVAL;
78
79 val = readl(pmx->base + pmx->mux_reg.offset);
80 for (i = 0; i < count; i++) {
81 u8 j = 0;
82
83 if (!devs[i]->name || !devs[i]->modes) {
84 printk(KERN_ERR "padmux: dev name or modes is null\n");
85 continue;
86 }
87 /* check if peripheral exists in active mode */
88 if (pmx->active_mode) {
89 bool found = false;
90 for (j = 0; j < devs[i]->mode_count; j++) {
91 if (devs[i]->modes[j].ids &
92 pmx->active_mode->id) {
93 found = true;
94 break;
95 }
96 }
97 if (found == false) {
98 printk(KERN_ERR "%s device not available in %s"\
99 "mode\n", devs[i]->name,
100 pmx->active_mode->name);
101 continue;
102 }
103 }
104
105 /* enable peripheral */
106 mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107 if (devs[i]->enb_on_reset)
108 val &= ~mask;
109 else
110 val |= mask;
111
112 devs[i]->is_active = true;
113 }
114 writel(val, pmx->base + pmx->mux_reg.offset);
115 kfree(pmx);
116
117 /* this will ensure that multiplexing can't be changed now */
118 pmx = (struct pmx *)-1;
119
120 return 0;
121}
122
123/**
124 * pmx_register - registers a platform requesting pad mux feature
125 * @driver - pointer to driver structure containing driver specific parameters
126 *
127 * Also this must be called only once. This will allocate memory for pmx
128 * structure, will call pmx_mode_set, will call pmx_devs_enable.
129 * Returns -ve on Err otherwise 0
130 */
131int pmx_register(struct pmx_driver *driver)
132{
133 int ret = 0;
134
135 if (pmx)
136 return -EPERM;
137 if (!driver->base || !driver->devs)
138 return -EFAULT;
139
140 pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141 if (!pmx)
142 return -ENOMEM;
143
144 pmx->base = (u32)driver->base;
145 pmx->mode_reg.offset = driver->mode_reg.offset;
146 pmx->mode_reg.mask = driver->mode_reg.mask;
147 pmx->mux_reg.offset = driver->mux_reg.offset;
148 pmx->mux_reg.mask = driver->mux_reg.mask;
149
150 /* choose mode to enable */
151 if (driver->mode) {
152 ret = pmx_mode_set(driver->mode);
153 if (ret)
154 goto pmx_fail;
155 }
156 ret = pmx_devs_enable(driver->devs, driver->devs_count);
157 if (ret)
158 goto pmx_fail;
159
160 return 0;
161
162pmx_fail:
163 return ret;
164}
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3f1f829260b..708ffb2165e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
37obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o 37obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
38obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o 38obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
39obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o 39obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
40obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
41obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o 40obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
42obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o 41obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
43obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o 42obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 12f349b3830..dc5184d5789 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -26,10 +26,10 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/irqdomain.h> 28#include <linux/irqdomain.h>
29#include <linux/pinctrl/consumer.h>
29 30
30#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
31 32
32#include <mach/gpio-tegra.h>
33#include <mach/iomap.h> 33#include <mach/iomap.h>
34#include <mach/suspend.h> 34#include <mach/suspend.h>
35 35
@@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
108 tegra_gpio_writel(val, reg); 108 tegra_gpio_writel(val, reg);
109} 109}
110 110
111void tegra_gpio_enable(int gpio) 111static void tegra_gpio_enable(int gpio)
112{ 112{
113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
114} 114}
115EXPORT_SYMBOL_GPL(tegra_gpio_enable); 115EXPORT_SYMBOL_GPL(tegra_gpio_enable);
116 116
117void tegra_gpio_disable(int gpio) 117static void tegra_gpio_disable(int gpio)
118{ 118{
119 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 119 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
120} 120}
121EXPORT_SYMBOL_GPL(tegra_gpio_disable); 121EXPORT_SYMBOL_GPL(tegra_gpio_disable);
122 122
123int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
124{
125 return pinctrl_request_gpio(offset);
126}
127
128void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
129{
130 pinctrl_free_gpio(offset);
131 tegra_gpio_disable(offset);
132}
133
123static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 134static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
124{ 135{
125 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); 136 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
@@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
133static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 144static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
134{ 145{
135 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); 146 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
147 tegra_gpio_enable(offset);
136 return 0; 148 return 0;
137} 149}
138 150
@@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
141{ 153{
142 tegra_gpio_set(chip, offset, value); 154 tegra_gpio_set(chip, offset, value);
143 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); 155 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
156 tegra_gpio_enable(offset);
144 return 0; 157 return 0;
145} 158}
146 159
@@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
151 164
152static struct gpio_chip tegra_gpio_chip = { 165static struct gpio_chip tegra_gpio_chip = {
153 .label = "tegra-gpio", 166 .label = "tegra-gpio",
167 .request = tegra_gpio_request,
168 .free = tegra_gpio_free,
154 .direction_input = tegra_gpio_direction_input, 169 .direction_input = tegra_gpio_direction_input,
155 .get = tegra_gpio_get, 170 .get = tegra_gpio_get,
156 .direction_output = tegra_gpio_direction_output, 171 .direction_output = tegra_gpio_direction_output,
157 .set = tegra_gpio_set, 172 .set = tegra_gpio_set,
158 .to_irq = tegra_gpio_to_irq, 173 .to_irq = tegra_gpio_to_irq,
159 .base = 0, 174 .base = 0,
160 .ngpio = TEGRA_NR_GPIOS,
161}; 175};
162 176
163static void tegra_gpio_irq_ack(struct irq_data *d) 177static void tegra_gpio_irq_ack(struct irq_data *d)
@@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
224 238
225 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 239 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
226 240
241 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
242 tegra_gpio_enable(gpio);
243
227 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 244 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
228 __irq_set_handler_locked(d->irq, handle_level_irq); 245 __irq_set_handler_locked(d->irq, handle_level_irq);
229 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 246 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void)
490} 507}
491postcore_initcall(tegra_gpio_init); 508postcore_initcall(tegra_gpio_init);
492 509
493void tegra_gpio_config(struct tegra_gpio_table *table, int num)
494{
495 int i;
496
497 for (i = 0; i < num; i++) {
498 int gpio = table[i].gpio;
499
500 if (table[i].enable)
501 tegra_gpio_enable(gpio);
502 else
503 tegra_gpio_disable(gpio);
504 }
505}
506
507#ifdef CONFIG_DEBUG_FS 510#ifdef CONFIG_DEBUG_FS
508 511
509#include <linux/debugfs.h> 512#include <linux/debugfs.h>
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index dfb84b7ee55..56bce9a8bcb 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -51,6 +51,7 @@
51#include <linux/of.h> 51#include <linux/of.h>
52#include <linux/of_device.h> 52#include <linux/of_device.h>
53#include <linux/of_i2c.h> 53#include <linux/of_i2c.h>
54#include <linux/pinctrl/consumer.h>
54 55
55#include <mach/irqs.h> 56#include <mach/irqs.h>
56#include <mach/hardware.h> 57#include <mach/hardware.h>
@@ -470,6 +471,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
470 struct imx_i2c_struct *i2c_imx; 471 struct imx_i2c_struct *i2c_imx;
471 struct resource *res; 472 struct resource *res;
472 struct imxi2c_platform_data *pdata = pdev->dev.platform_data; 473 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
474 struct pinctrl *pinctrl;
473 void __iomem *base; 475 void __iomem *base;
474 resource_size_t res_size; 476 resource_size_t res_size;
475 int irq, bitrate; 477 int irq, bitrate;
@@ -520,6 +522,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
520 i2c_imx->base = base; 522 i2c_imx->base = base;
521 i2c_imx->res = res; 523 i2c_imx->res = res;
522 524
525 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
526 if (IS_ERR(pinctrl)) {
527 ret = PTR_ERR(pinctrl);
528 goto fail3;
529 }
530
523 /* Get I2C clock */ 531 /* Get I2C clock */
524 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk"); 532 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
525 if (IS_ERR(i2c_imx->clk)) { 533 if (IS_ERR(i2c_imx->clk)) {
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 76b8af44f63..7fa73eed84a 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -26,6 +26,7 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/jiffies.h> 27#include <linux/jiffies.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/pinctrl/consumer.h>
29 30
30#include <mach/common.h> 31#include <mach/common.h>
31 32
@@ -325,10 +326,15 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
325 struct device *dev = &pdev->dev; 326 struct device *dev = &pdev->dev;
326 struct mxs_i2c_dev *i2c; 327 struct mxs_i2c_dev *i2c;
327 struct i2c_adapter *adap; 328 struct i2c_adapter *adap;
329 struct pinctrl *pinctrl;
328 struct resource *res; 330 struct resource *res;
329 resource_size_t res_size; 331 resource_size_t res_size;
330 int err, irq; 332 int err, irq;
331 333
334 pinctrl = devm_pinctrl_get_select_default(dev);
335 if (IS_ERR(pinctrl))
336 return PTR_ERR(pinctrl);
337
332 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); 338 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
333 if (!i2c) 339 if (!i2c)
334 return -ENOMEM; 340 return -ENOMEM;
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index e3f5af96ab8..bb03ddda481 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -39,6 +39,7 @@
39#include <linux/regulator/consumer.h> 39#include <linux/regulator/consumer.h>
40#include <linux/module.h> 40#include <linux/module.h>
41#include <linux/fsl/mxs-dma.h> 41#include <linux/fsl/mxs-dma.h>
42#include <linux/pinctrl/consumer.h>
42 43
43#include <mach/mxs.h> 44#include <mach/mxs.h>
44#include <mach/common.h> 45#include <mach/common.h>
@@ -682,6 +683,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
682 struct mmc_host *mmc; 683 struct mmc_host *mmc;
683 struct resource *iores, *dmares, *r; 684 struct resource *iores, *dmares, *r;
684 struct mxs_mmc_platform_data *pdata; 685 struct mxs_mmc_platform_data *pdata;
686 struct pinctrl *pinctrl;
685 int ret = 0, irq_err, irq_dma; 687 int ret = 0, irq_err, irq_dma;
686 dma_cap_mask_t mask; 688 dma_cap_mask_t mask;
687 689
@@ -719,6 +721,12 @@ static int mxs_mmc_probe(struct platform_device *pdev)
719 host->irq = irq_err; 721 host->irq = irq_err;
720 host->sdio_irq_en = 0; 722 host->sdio_irq_en = 0;
721 723
724 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
725 if (IS_ERR(pinctrl)) {
726 ret = PTR_ERR(pinctrl);
727 goto out_iounmap;
728 }
729
722 host->clk = clk_get(&pdev->dev, NULL); 730 host->clk = clk_get(&pdev->dev, NULL);
723 if (IS_ERR(host->clk)) { 731 if (IS_ERR(host->clk)) {
724 ret = PTR_ERR(host->clk); 732 ret = PTR_ERR(host->clk);
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 8abdaf6697a..d190d04636a 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -24,6 +24,7 @@
24#include <linux/of.h> 24#include <linux/of.h>
25#include <linux/of_device.h> 25#include <linux/of_device.h>
26#include <linux/of_gpio.h> 26#include <linux/of_gpio.h>
27#include <linux/pinctrl/consumer.h>
27#include <mach/esdhc.h> 28#include <mach/esdhc.h>
28#include "sdhci-pltfm.h" 29#include "sdhci-pltfm.h"
29#include "sdhci-esdhc.h" 30#include "sdhci-esdhc.h"
@@ -68,6 +69,7 @@ struct pltfm_imx_data {
68 int flags; 69 int flags;
69 u32 scratchpad; 70 u32 scratchpad;
70 enum imx_esdhc_type devtype; 71 enum imx_esdhc_type devtype;
72 struct pinctrl *pinctrl;
71 struct esdhc_platform_data boarddata; 73 struct esdhc_platform_data boarddata;
72}; 74};
73 75
@@ -467,6 +469,12 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
467 clk_prepare_enable(clk); 469 clk_prepare_enable(clk);
468 pltfm_host->clk = clk; 470 pltfm_host->clk = clk;
469 471
472 imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
473 if (IS_ERR(imx_data->pinctrl)) {
474 err = PTR_ERR(imx_data->pinctrl);
475 goto pin_err;
476 }
477
470 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 478 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
471 479
472 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 480 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
@@ -558,6 +566,7 @@ no_card_detect_irq:
558 gpio_free(boarddata->wp_gpio); 566 gpio_free(boarddata->wp_gpio);
559no_card_detect_pin: 567no_card_detect_pin:
560no_board_data: 568no_board_data:
569pin_err:
561 clk_disable_unprepare(pltfm_host->clk); 570 clk_disable_unprepare(pltfm_host->clk);
562 clk_put(pltfm_host->clk); 571 clk_put(pltfm_host->clk);
563err_clk_get: 572err_clk_get:
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 53b26502f6e..ff5a1699193 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
269 "failed to allocate power gpio\n"); 269 "failed to allocate power gpio\n");
270 goto err_power_req; 270 goto err_power_req;
271 } 271 }
272 tegra_gpio_enable(plat->power_gpio);
273 gpio_direction_output(plat->power_gpio, 1); 272 gpio_direction_output(plat->power_gpio, 1);
274 } 273 }
275 274
@@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
280 "failed to allocate cd gpio\n"); 279 "failed to allocate cd gpio\n");
281 goto err_cd_req; 280 goto err_cd_req;
282 } 281 }
283 tegra_gpio_enable(plat->cd_gpio);
284 gpio_direction_input(plat->cd_gpio); 282 gpio_direction_input(plat->cd_gpio);
285 283
286 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, 284 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
@@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
301 "failed to allocate wp gpio\n"); 299 "failed to allocate wp gpio\n");
302 goto err_wp_req; 300 goto err_wp_req;
303 } 301 }
304 tegra_gpio_enable(plat->wp_gpio);
305 gpio_direction_input(plat->wp_gpio); 302 gpio_direction_input(plat->wp_gpio);
306 } 303 }
307 304
@@ -329,23 +326,17 @@ err_add_host:
329 clk_disable(pltfm_host->clk); 326 clk_disable(pltfm_host->clk);
330 clk_put(pltfm_host->clk); 327 clk_put(pltfm_host->clk);
331err_clk_get: 328err_clk_get:
332 if (gpio_is_valid(plat->wp_gpio)) { 329 if (gpio_is_valid(plat->wp_gpio))
333 tegra_gpio_disable(plat->wp_gpio);
334 gpio_free(plat->wp_gpio); 330 gpio_free(plat->wp_gpio);
335 }
336err_wp_req: 331err_wp_req:
337 if (gpio_is_valid(plat->cd_gpio)) 332 if (gpio_is_valid(plat->cd_gpio))
338 free_irq(gpio_to_irq(plat->cd_gpio), host); 333 free_irq(gpio_to_irq(plat->cd_gpio), host);
339err_cd_irq_req: 334err_cd_irq_req:
340 if (gpio_is_valid(plat->cd_gpio)) { 335 if (gpio_is_valid(plat->cd_gpio))
341 tegra_gpio_disable(plat->cd_gpio);
342 gpio_free(plat->cd_gpio); 336 gpio_free(plat->cd_gpio);
343 }
344err_cd_req: 337err_cd_req:
345 if (gpio_is_valid(plat->power_gpio)) { 338 if (gpio_is_valid(plat->power_gpio))
346 tegra_gpio_disable(plat->power_gpio);
347 gpio_free(plat->power_gpio); 339 gpio_free(plat->power_gpio);
348 }
349err_power_req: 340err_power_req:
350err_no_plat: 341err_no_plat:
351 sdhci_pltfm_free(pdev); 342 sdhci_pltfm_free(pdev);
@@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
362 353
363 sdhci_remove_host(host, dead); 354 sdhci_remove_host(host, dead);
364 355
365 if (gpio_is_valid(plat->wp_gpio)) { 356 if (gpio_is_valid(plat->wp_gpio))
366 tegra_gpio_disable(plat->wp_gpio);
367 gpio_free(plat->wp_gpio); 357 gpio_free(plat->wp_gpio);
368 }
369 358
370 if (gpio_is_valid(plat->cd_gpio)) { 359 if (gpio_is_valid(plat->cd_gpio)) {
371 free_irq(gpio_to_irq(plat->cd_gpio), host); 360 free_irq(gpio_to_irq(plat->cd_gpio), host);
372 tegra_gpio_disable(plat->cd_gpio);
373 gpio_free(plat->cd_gpio); 361 gpio_free(plat->cd_gpio);
374 } 362 }
375 363
376 if (gpio_is_valid(plat->power_gpio)) { 364 if (gpio_is_valid(plat->power_gpio))
377 tegra_gpio_disable(plat->power_gpio);
378 gpio_free(plat->power_gpio); 365 gpio_free(plat->power_gpio);
379 }
380 366
381 clk_disable(pltfm_host->clk); 367 clk_disable(pltfm_host->clk);
382 clk_put(pltfm_host->clk); 368 clk_put(pltfm_host->clk);
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 9ec51cec2e1..b68e04310bd 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -24,6 +24,7 @@
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/mtd/gpmi-nand.h> 25#include <linux/mtd/gpmi-nand.h>
26#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
27#include <linux/pinctrl/consumer.h>
27#include "gpmi-nand.h" 28#include "gpmi-nand.h"
28 29
29/* add our owner bbt descriptor */ 30/* add our owner bbt descriptor */
@@ -476,6 +477,7 @@ acquire_err:
476static int __devinit acquire_resources(struct gpmi_nand_data *this) 477static int __devinit acquire_resources(struct gpmi_nand_data *this)
477{ 478{
478 struct resources *res = &this->resources; 479 struct resources *res = &this->resources;
480 struct pinctrl *pinctrl;
479 int ret; 481 int ret;
480 482
481 ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME); 483 ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
@@ -494,6 +496,12 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
494 if (ret) 496 if (ret)
495 goto exit_dma_channels; 497 goto exit_dma_channels;
496 498
499 pinctrl = devm_pinctrl_get_select_default(&this->pdev->dev);
500 if (IS_ERR(pinctrl)) {
501 ret = PTR_ERR(pinctrl);
502 goto exit_pin;
503 }
504
497 res->clock = clk_get(&this->pdev->dev, NULL); 505 res->clock = clk_get(&this->pdev->dev, NULL);
498 if (IS_ERR(res->clock)) { 506 if (IS_ERR(res->clock)) {
499 pr_err("can not get the clock\n"); 507 pr_err("can not get the clock\n");
@@ -503,6 +511,7 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
503 return 0; 511 return 0;
504 512
505exit_clock: 513exit_clock:
514exit_pin:
506 release_dma_channels(this); 515 release_dma_channels(this);
507exit_dma_channels: 516exit_dma_channels:
508 release_bch_irq(this); 517 release_bch_irq(this);
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 1efb08386c6..38c0690df5c 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -35,6 +35,7 @@
35#include <linux/module.h> 35#include <linux/module.h>
36#include <linux/of.h> 36#include <linux/of.h>
37#include <linux/platform_device.h> 37#include <linux/platform_device.h>
38#include <linux/pinctrl/consumer.h>
38 39
39#define DRV_NAME "flexcan" 40#define DRV_NAME "flexcan"
40 41
@@ -927,11 +928,16 @@ static int __devinit flexcan_probe(struct platform_device *pdev)
927 struct flexcan_priv *priv; 928 struct flexcan_priv *priv;
928 struct resource *mem; 929 struct resource *mem;
929 struct clk *clk = NULL; 930 struct clk *clk = NULL;
931 struct pinctrl *pinctrl;
930 void __iomem *base; 932 void __iomem *base;
931 resource_size_t mem_size; 933 resource_size_t mem_size;
932 int err, irq; 934 int err, irq;
933 u32 clock_freq = 0; 935 u32 clock_freq = 0;
934 936
937 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
938 if (IS_ERR(pinctrl))
939 return PTR_ERR(pinctrl);
940
935 if (pdev->dev.of_node) { 941 if (pdev->dev.of_node) {
936 const u32 *clock_freq_p; 942 const u32 *clock_freq_p;
937 943
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 7fa0227c9c0..8f2cf8c09e2 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -48,6 +48,7 @@
48#include <linux/of_device.h> 48#include <linux/of_device.h>
49#include <linux/of_gpio.h> 49#include <linux/of_gpio.h>
50#include <linux/of_net.h> 50#include <linux/of_net.h>
51#include <linux/pinctrl/consumer.h>
51 52
52#include <asm/cacheflush.h> 53#include <asm/cacheflush.h>
53 54
@@ -1543,6 +1544,7 @@ fec_probe(struct platform_device *pdev)
1543 struct resource *r; 1544 struct resource *r;
1544 const struct of_device_id *of_id; 1545 const struct of_device_id *of_id;
1545 static int dev_id; 1546 static int dev_id;
1547 struct pinctrl *pinctrl;
1546 1548
1547 of_id = of_match_device(fec_dt_ids, &pdev->dev); 1549 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1548 if (of_id) 1550 if (of_id)
@@ -1610,6 +1612,12 @@ fec_probe(struct platform_device *pdev)
1610 } 1612 }
1611 } 1613 }
1612 1614
1615 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1616 if (IS_ERR(pinctrl)) {
1617 ret = PTR_ERR(pinctrl);
1618 goto failed_pin;
1619 }
1620
1613 fep->clk = clk_get(&pdev->dev, NULL); 1621 fep->clk = clk_get(&pdev->dev, NULL);
1614 if (IS_ERR(fep->clk)) { 1622 if (IS_ERR(fep->clk)) {
1615 ret = PTR_ERR(fep->clk); 1623 ret = PTR_ERR(fep->clk);
@@ -1640,6 +1648,7 @@ failed_mii_init:
1640failed_init: 1648failed_init:
1641 clk_disable_unprepare(fep->clk); 1649 clk_disable_unprepare(fep->clk);
1642 clk_put(fep->clk); 1650 clk_put(fep->clk);
1651failed_pin:
1643failed_clk: 1652failed_clk:
1644 for (i = 0; i < FEC_IRQ_NUM; i++) { 1653 for (i = 0; i < FEC_IRQ_NUM; i++) {
1645 irq = platform_get_irq(pdev, i); 1654 irq = platform_get_irq(pdev, i);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 91c1f64102f..c6e6ae0aa3b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -80,6 +80,16 @@ config PINCTRL_IMX28
80 select PINCONF 80 select PINCONF
81 select PINCTRL_MXS 81 select PINCTRL_MXS
82 82
83config PINCTRL_NOMADIK
84 bool "Nomadik pin controller driver"
85 depends on ARCH_U8500 || ARCH_NOMADIK
86 select PINMUX
87 select PINCONF
88
89config PINCTRL_DB8500
90 bool "DB8500 pin controller driver"
91 depends on PINCTRL_NOMADIK && ARCH_U8500
92
83config PINCTRL_PXA168 93config PINCTRL_PXA168
84 bool "PXA168 pin controller driver" 94 bool "PXA168 pin controller driver"
85 depends on ARCH_MMP 95 depends on ARCH_MMP
@@ -127,6 +137,8 @@ config PINCTRL_COH901
127 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 137 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
128 ports of 8 GPIO pins each. 138 ports of 8 GPIO pins each.
129 139
140source "drivers/pinctrl/spear/Kconfig"
141
130endmenu 142endmenu
131 143
132endif 144endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 515e32ff159..8c074376cde 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
18obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 18obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
19obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 19obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
20obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 20obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
21obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
22obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
21obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 23obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
22obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 24obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
23obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 25obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
@@ -26,3 +28,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
26obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 28obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
27obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 29obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
28obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 30obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
31
32obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
new file mode 100644
index 00000000000..8b2022276f7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -0,0 +1,857 @@
1#include <linux/kernel.h>
2#include <linux/pinctrl/pinctrl.h>
3#include "pinctrl-nomadik.h"
4
5/* All the pins that can be used for GPIO and some other functions */
6#define _GPIO(offset) (offset)
7
8#define DB8500_PIN_AJ5 _GPIO(0)
9#define DB8500_PIN_AJ3 _GPIO(1)
10#define DB8500_PIN_AH4 _GPIO(2)
11#define DB8500_PIN_AH3 _GPIO(3)
12#define DB8500_PIN_AH6 _GPIO(4)
13#define DB8500_PIN_AG6 _GPIO(5)
14#define DB8500_PIN_AF6 _GPIO(6)
15#define DB8500_PIN_AG5 _GPIO(7)
16#define DB8500_PIN_AD5 _GPIO(8)
17#define DB8500_PIN_AE4 _GPIO(9)
18#define DB8500_PIN_AF5 _GPIO(10)
19#define DB8500_PIN_AG4 _GPIO(11)
20#define DB8500_PIN_AC4 _GPIO(12)
21#define DB8500_PIN_AF3 _GPIO(13)
22#define DB8500_PIN_AE3 _GPIO(14)
23#define DB8500_PIN_AC3 _GPIO(15)
24#define DB8500_PIN_AD3 _GPIO(16)
25#define DB8500_PIN_AD4 _GPIO(17)
26#define DB8500_PIN_AC2 _GPIO(18)
27#define DB8500_PIN_AC1 _GPIO(19)
28#define DB8500_PIN_AB4 _GPIO(20)
29#define DB8500_PIN_AB3 _GPIO(21)
30#define DB8500_PIN_AA3 _GPIO(22)
31#define DB8500_PIN_AA4 _GPIO(23)
32#define DB8500_PIN_AB2 _GPIO(24)
33#define DB8500_PIN_Y4 _GPIO(25)
34#define DB8500_PIN_Y2 _GPIO(26)
35#define DB8500_PIN_AA2 _GPIO(27)
36#define DB8500_PIN_AA1 _GPIO(28)
37#define DB8500_PIN_W2 _GPIO(29)
38#define DB8500_PIN_W3 _GPIO(30)
39#define DB8500_PIN_V3 _GPIO(31)
40#define DB8500_PIN_V2 _GPIO(32)
41#define DB8500_PIN_AF2 _GPIO(33)
42#define DB8500_PIN_AE1 _GPIO(34)
43#define DB8500_PIN_AE2 _GPIO(35)
44#define DB8500_PIN_AG2 _GPIO(36)
45/* Hole */
46#define DB8500_PIN_F3 _GPIO(64)
47#define DB8500_PIN_F1 _GPIO(65)
48#define DB8500_PIN_G3 _GPIO(66)
49#define DB8500_PIN_G2 _GPIO(67)
50#define DB8500_PIN_E1 _GPIO(68)
51#define DB8500_PIN_E2 _GPIO(69)
52#define DB8500_PIN_G5 _GPIO(70)
53#define DB8500_PIN_G4 _GPIO(71)
54#define DB8500_PIN_H4 _GPIO(72)
55#define DB8500_PIN_H3 _GPIO(73)
56#define DB8500_PIN_J3 _GPIO(74)
57#define DB8500_PIN_H2 _GPIO(75)
58#define DB8500_PIN_J2 _GPIO(76)
59#define DB8500_PIN_H1 _GPIO(77)
60#define DB8500_PIN_F4 _GPIO(78)
61#define DB8500_PIN_E3 _GPIO(79)
62#define DB8500_PIN_E4 _GPIO(80)
63#define DB8500_PIN_D2 _GPIO(81)
64#define DB8500_PIN_C1 _GPIO(82)
65#define DB8500_PIN_D3 _GPIO(83)
66#define DB8500_PIN_C2 _GPIO(84)
67#define DB8500_PIN_D5 _GPIO(85)
68#define DB8500_PIN_C6 _GPIO(86)
69#define DB8500_PIN_B3 _GPIO(87)
70#define DB8500_PIN_C4 _GPIO(88)
71#define DB8500_PIN_E6 _GPIO(89)
72#define DB8500_PIN_A3 _GPIO(90)
73#define DB8500_PIN_B6 _GPIO(91)
74#define DB8500_PIN_D6 _GPIO(92)
75#define DB8500_PIN_B7 _GPIO(93)
76#define DB8500_PIN_D7 _GPIO(94)
77#define DB8500_PIN_E8 _GPIO(95)
78#define DB8500_PIN_D8 _GPIO(96)
79#define DB8500_PIN_D9 _GPIO(97)
80/* Hole */
81#define DB8500_PIN_A5 _GPIO(128)
82#define DB8500_PIN_B4 _GPIO(129)
83#define DB8500_PIN_C8 _GPIO(130)
84#define DB8500_PIN_A12 _GPIO(131)
85#define DB8500_PIN_C10 _GPIO(132)
86#define DB8500_PIN_B10 _GPIO(133)
87#define DB8500_PIN_B9 _GPIO(134)
88#define DB8500_PIN_A9 _GPIO(135)
89#define DB8500_PIN_C7 _GPIO(136)
90#define DB8500_PIN_A7 _GPIO(137)
91#define DB8500_PIN_C5 _GPIO(138)
92#define DB8500_PIN_C9 _GPIO(139)
93#define DB8500_PIN_B11 _GPIO(140)
94#define DB8500_PIN_C12 _GPIO(141)
95#define DB8500_PIN_C11 _GPIO(142)
96#define DB8500_PIN_D12 _GPIO(143)
97#define DB8500_PIN_B13 _GPIO(144)
98#define DB8500_PIN_C13 _GPIO(145)
99#define DB8500_PIN_D13 _GPIO(146)
100#define DB8500_PIN_C15 _GPIO(147)
101#define DB8500_PIN_B16 _GPIO(148)
102#define DB8500_PIN_B14 _GPIO(149)
103#define DB8500_PIN_C14 _GPIO(150)
104#define DB8500_PIN_D17 _GPIO(151)
105#define DB8500_PIN_D16 _GPIO(152)
106#define DB8500_PIN_B17 _GPIO(153)
107#define DB8500_PIN_C16 _GPIO(154)
108#define DB8500_PIN_C19 _GPIO(155)
109#define DB8500_PIN_C17 _GPIO(156)
110#define DB8500_PIN_A18 _GPIO(157)
111#define DB8500_PIN_C18 _GPIO(158)
112#define DB8500_PIN_B19 _GPIO(159)
113#define DB8500_PIN_B20 _GPIO(160)
114#define DB8500_PIN_D21 _GPIO(161)
115#define DB8500_PIN_D20 _GPIO(162)
116#define DB8500_PIN_C20 _GPIO(163)
117#define DB8500_PIN_B21 _GPIO(164)
118#define DB8500_PIN_C21 _GPIO(165)
119#define DB8500_PIN_A22 _GPIO(166)
120#define DB8500_PIN_B24 _GPIO(167)
121#define DB8500_PIN_C22 _GPIO(168)
122#define DB8500_PIN_D22 _GPIO(169)
123#define DB8500_PIN_C23 _GPIO(170)
124#define DB8500_PIN_D23 _GPIO(171)
125/* Hole */
126#define DB8500_PIN_AJ27 _GPIO(192)
127#define DB8500_PIN_AH27 _GPIO(193)
128#define DB8500_PIN_AF27 _GPIO(194)
129#define DB8500_PIN_AG28 _GPIO(195)
130#define DB8500_PIN_AG26 _GPIO(196)
131#define DB8500_PIN_AH24 _GPIO(197)
132#define DB8500_PIN_AG25 _GPIO(198)
133#define DB8500_PIN_AH23 _GPIO(199)
134#define DB8500_PIN_AH26 _GPIO(200)
135#define DB8500_PIN_AF24 _GPIO(201)
136#define DB8500_PIN_AF25 _GPIO(202)
137#define DB8500_PIN_AE23 _GPIO(203)
138#define DB8500_PIN_AF23 _GPIO(204)
139#define DB8500_PIN_AG23 _GPIO(205)
140#define DB8500_PIN_AG24 _GPIO(206)
141#define DB8500_PIN_AJ23 _GPIO(207)
142#define DB8500_PIN_AH16 _GPIO(208)
143#define DB8500_PIN_AG15 _GPIO(209)
144#define DB8500_PIN_AJ15 _GPIO(210)
145#define DB8500_PIN_AG14 _GPIO(211)
146#define DB8500_PIN_AF13 _GPIO(212)
147#define DB8500_PIN_AG13 _GPIO(213)
148#define DB8500_PIN_AH15 _GPIO(214)
149#define DB8500_PIN_AH13 _GPIO(215)
150#define DB8500_PIN_AG12 _GPIO(216)
151#define DB8500_PIN_AH12 _GPIO(217)
152#define DB8500_PIN_AH11 _GPIO(218)
153#define DB8500_PIN_AG10 _GPIO(219)
154#define DB8500_PIN_AH10 _GPIO(220)
155#define DB8500_PIN_AJ11 _GPIO(221)
156#define DB8500_PIN_AJ9 _GPIO(222)
157#define DB8500_PIN_AH9 _GPIO(223)
158#define DB8500_PIN_AG9 _GPIO(224)
159#define DB8500_PIN_AG8 _GPIO(225)
160#define DB8500_PIN_AF8 _GPIO(226)
161#define DB8500_PIN_AH7 _GPIO(227)
162#define DB8500_PIN_AJ6 _GPIO(228)
163#define DB8500_PIN_AG7 _GPIO(229)
164#define DB8500_PIN_AF7 _GPIO(230)
165/* Hole */
166#define DB8500_PIN_AF28 _GPIO(256)
167#define DB8500_PIN_AE29 _GPIO(257)
168#define DB8500_PIN_AD29 _GPIO(258)
169#define DB8500_PIN_AC29 _GPIO(259)
170#define DB8500_PIN_AD28 _GPIO(260)
171#define DB8500_PIN_AD26 _GPIO(261)
172#define DB8500_PIN_AE26 _GPIO(262)
173#define DB8500_PIN_AG29 _GPIO(263)
174#define DB8500_PIN_AE27 _GPIO(264)
175#define DB8500_PIN_AD27 _GPIO(265)
176#define DB8500_PIN_AC28 _GPIO(266)
177#define DB8500_PIN_AC27 _GPIO(267)
178
179/*
180 * The names of the pins are denoted by GPIO number and ball name, even
181 * though they can be used for other things than GPIO, this is the first
182 * column in the table of the data sheet and often used on schematics and
183 * such.
184 */
185static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
186 PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
187 PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
188 PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
189 PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
190 PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
191 PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
192 PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
193 PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
194 PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
195 PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
196 PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
197 PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
198 PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
199 PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
200 PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
201 PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
202 PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
203 PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
204 PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
205 PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
206 PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
207 PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
208 PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
209 PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
210 PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
211 PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
212 PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
213 PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
214 PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
215 PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
216 PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
217 PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
218 PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
219 PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
220 PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
221 PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
222 PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
223 /* Hole */
224 PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
225 PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
226 PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
227 PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
228 PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
229 PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
230 PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
231 PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
232 PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
233 PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
234 PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
235 PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
236 PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
237 PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
238 PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
239 PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
240 PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
241 PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
242 PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
243 PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
244 PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
245 PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
246 PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
247 PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
248 PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
249 PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
250 PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
251 PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
252 PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
253 PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
254 PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
255 PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
256 PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
257 PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
258 /* Hole */
259 PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
260 PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
261 PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
262 PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
263 PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
264 PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
265 PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
266 PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
267 PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
268 PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
269 PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
270 PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
271 PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
272 PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
273 PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
274 PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
275 PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
276 PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
277 PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
278 PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
279 PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
280 PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
281 PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
282 PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
283 PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
284 PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
285 PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
286 PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
287 PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
288 PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
289 PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
290 PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
291 PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
292 PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
293 PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
294 PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
295 PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
296 PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
297 PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
298 PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
299 PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
300 PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
301 PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
302 PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
303 /* Hole */
304 PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
305 PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
306 PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
307 PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
308 PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
309 PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
310 PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
311 PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
312 PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
313 PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
314 PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
315 PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
316 PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
317 PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
318 PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
319 PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
320 PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
321 PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
322 PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
323 PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
324 PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
325 PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
326 PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
327 PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
328 PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
329 PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
330 PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
331 PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
332 PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
333 PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
334 PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
335 PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
336 PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
337 PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
338 PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
339 PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
340 PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
341 PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
342 PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
343 /* Hole */
344 PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
345 PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
346 PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
347 PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
348 PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
349 PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
350 PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
351 PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
352 PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
353 PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
354 PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
355 PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
356};
357
358#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
359 .pin_base = b, .npins = c }
360
361/*
362 * This matches the 32-pin gpio chips registered by the GPIO portion. This
363 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
364 */
365static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
366 DB8500_GPIO_RANGE(0, 0, 32),
367 DB8500_GPIO_RANGE(1, 32, 5),
368 DB8500_GPIO_RANGE(2, 64, 32),
369 DB8500_GPIO_RANGE(3, 96, 2),
370 DB8500_GPIO_RANGE(4, 128, 32),
371 DB8500_GPIO_RANGE(5, 160, 12),
372 DB8500_GPIO_RANGE(6, 192, 32),
373 DB8500_GPIO_RANGE(7, 224, 7),
374 DB8500_GPIO_RANGE(8, 256, 12),
375};
376
377/*
378 * Read the pin group names like this:
379 * u0_a_1 = first groups of pins for uart0 on alt function a
380 * i2c2_b_2 = second group of pins for i2c2 on alt function b
381 *
382 * The groups are arranged as sets per altfunction column, so we can
383 * mux in one group at a time by selecting the same altfunction for them
384 * all. When functions require pins on different altfunctions, you need
385 * to combine several groups.
386 */
387
388/* Altfunction A column */
389static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
390 DB8500_PIN_AH4, DB8500_PIN_AH3 };
391static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
392static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
393/* Image processor I2C line, this is driven by image processor firmware */
394static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
395static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
396/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
397static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
398static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
399static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
400/* Basic pins of the MMC/SD card 0 interface */
401static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
402 DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
403 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
404/* Often only 4 bits are used, then these are not needed (only used for MMC) */
405static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
406 DB8500_PIN_V3, DB8500_PIN_V2};
407static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
408/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
409static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
410static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
411/* LCD interface */
412static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
413 DB8500_PIN_G3, DB8500_PIN_G2 };
414static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
415static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
416static const unsigned lcd_d0_d7_a_1_pins[] = {
417 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
418 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
419/* D8 thru D11 often used as TVOUT lines */
420static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
421 DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
422static const unsigned lcd_d12_d23_a_1_pins[] = {
423 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
424 DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
425 DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
426static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
427 DB8500_PIN_D8, DB8500_PIN_D9 };
428static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
429static const unsigned kp_a_2_pins[] = {
430 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
431 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
432 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
433 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
434/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
435static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
436 DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
437 DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
438 DB8500_PIN_C5 };
439static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
440 DB8500_PIN_C12, DB8500_PIN_C11 };
441static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
442 DB8500_PIN_C13, DB8500_PIN_D13 };
443static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
444/*
445 * Image processor GPIO pins are named "ipgpio" and have their own
446 * numberspace
447 */
448static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
449static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
450/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
451static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
452 DB8500_PIN_D23 };
453/*
454 * This MSP cannot switch RX and TX, SCK in a separate group since this
455 * seems to be optional.
456 */
457static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
458static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
459 DB8500_PIN_AG28, DB8500_PIN_AG26 };
460static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
461 DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
462 DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
463 DB8500_PIN_AJ23 };
464/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
465static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
466 DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
467 DB8500_PIN_AH15 };
468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
469 DB8500_PIN_AH12, DB8500_PIN_AH11 };
470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 };
471static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9,
472 DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
473static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
474static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
475static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
476 DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
477 DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
478 DB8500_PIN_AC28, DB8500_PIN_AC27 };
479
480/* Altfunction B column */
481static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
482static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
483static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
484static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
485static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
486static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
487static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
488/* Just RX and TX for UART2 */
489static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
490static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
491static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
492static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
493static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
494 DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
495static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
496static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
497 DB8500_PIN_V3, DB8500_PIN_V2 };
498static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
499static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
500 DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
501 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
502 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
503 DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
504 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
505static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
506 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
507 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
508 DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
509 DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
510 DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
511 DB8500_PIN_C9, DB8500_PIN_B14 };
512/* This chip select pin can be "ps0" in alt B so have it separately */
513static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
514static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
515static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
516static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
517static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
518static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
519 DB8500_PIN_C23, DB8500_PIN_D23 };
520static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
521 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
522 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
523 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
524 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
525static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
526static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
527static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
528 DB8500_PIN_AG13, DB8500_PIN_AH15 };
529static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
530 DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
531 DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
532 DB8500_PIN_AG8 };
533static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
534static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
535static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
536
537/* Altfunction C column */
538static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
539 DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
540static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
541static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
542static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
543static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
544static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
545static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
546/* Optional 4-bit Memory Stick interface */
547static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
548 DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
549 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
550static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
551static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
552static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
553static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
554 DB8500_PIN_AE2, DB8500_PIN_AG2 };
555static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
556static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
557static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
558static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
559static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
560static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
561 DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
562static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
563static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
564static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
565static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
566static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
567static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
568 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
569 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
570 DB8500_PIN_D9 };
571static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
572static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
573 DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
574 DB8500_PIN_C23, DB8500_PIN_D23 };
575static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
576static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
577static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
578 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
579static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
580static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
581static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
582 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
583static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
584static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
585static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 };
586static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
587static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
588 DB8500_PIN_AG9, DB8500_PIN_AG8 };
589static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
590static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
591
592/* Other C1 column */
593static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
594 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
595 DB8500_PIN_D6, DB8500_PIN_B7 };
596static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
597 DB8500_PIN_AH12, DB8500_PIN_AH11 };
598
599#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
600 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
601
602static const struct nmk_pingroup nmk_db8500_groups[] = {
603 /* Altfunction A column */
604 DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
605 DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
606 DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
607 DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
608 DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
609 DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
610 DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
611 DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
612 DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
613 DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
614 DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
615 DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
616 DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
617 DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
618 DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
619 DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
620 DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
621 DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
622 DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
623 DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
624 DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
625 DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
626 DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
627 DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
628 DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
629 DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
630 DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
631 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
632 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
633 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
634 DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
635 DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
636 DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
637 /* Altfunction B column */
638 DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
639 DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
640 DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
641 DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
642 DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
643 DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
644 DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
645 DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
646 DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
647 DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
648 DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
649 DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
650 DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
651 DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
652 DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
653 DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
654 DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
655 DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
656 DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
657 DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
658 DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
659 DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
660 DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
661 DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
662 DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
663 DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
664 DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
665 DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
666 DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
667 DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
668 DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
669 /* Altfunction C column */
670 DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
671 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
672 DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
673 DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
674 DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
675 DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
676 DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
677 DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
678 DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
679 DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
680 DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
681 DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
682 DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
683 DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
684 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
685 DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
686 DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
687 DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
688 DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
689 DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
690 DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
691 DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
692 DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
693 DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
694 DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
695 DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
696 DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
697 DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
698 DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
699 DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
700 DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
701 DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
702 DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
703 DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
704 DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C),
705 DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
706 DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
707 DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
708 DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
709 /* Other alt C1 column, these are still configured as alt C */
710 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
711 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
712};
713
714/* We use this macro to define the groups applicable to a function */
715#define DB8500_FUNC_GROUPS(a, b...) \
716static const char * const a##_groups[] = { b };
717
718DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
719DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
720/*
721 * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
722 * only available on two pins in alternative function C
723 */
724DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
725 "u2rxtx_c_2", "u2rxtx_c_3");
726DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
727/*
728 * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
729 * switched around by selecting the altfunction A or B. The SCK pin is
730 * only available on the altfunction B.
731 */
732DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
733 "msp0txrx_b_1", "msp0sck_b_1");
734DB8500_FUNC_GROUPS(mc0, "mc0_a_1");
735/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
736DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
737DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
738DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
739 "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
740DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
741DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
742DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
743DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
744DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
745/* The image processor has 8 GPIO pins that can be muxed out */
746DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
747 "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
748 "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
749 "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
750 "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
751/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
752DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
753DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
754DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
755DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1");
756DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
757DB8500_FUNC_GROUPS(usb, "usb_a_1");
758DB8500_FUNC_GROUPS(trig, "trig_b_1");
759DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
760DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
761DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
762/*
763 * The modem UART can output its RX and TX pins in some different places,
764 * so select one of each.
765 */
766DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
767 "uartmodrx_c_1", "uartmod_tx_c_1");
768DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
769DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
770/* Select between CS0 on alt B or PS1 on alt C */
771DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1");
772DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
773DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
774DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
775DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
776DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
777DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
778DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
779DB8500_FUNC_GROUPS(ms, "ms_c_1");
780DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
781DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2");
782DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
783DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
784DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
785DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
786DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1");
787
788#define FUNCTION(fname) \
789 { \
790 .name = #fname, \
791 .groups = fname##_groups, \
792 .ngroups = ARRAY_SIZE(fname##_groups), \
793 }
794
795static const struct nmk_function nmk_db8500_functions[] = {
796 FUNCTION(u0),
797 FUNCTION(u1),
798 FUNCTION(u2),
799 FUNCTION(ipi2c),
800 FUNCTION(msp0),
801 FUNCTION(mc0),
802 FUNCTION(msp1),
803 FUNCTION(lcdb),
804 FUNCTION(lcd),
805 FUNCTION(kp),
806 FUNCTION(mc2),
807 FUNCTION(ssp1),
808 FUNCTION(ssp0),
809 FUNCTION(i2c0),
810 FUNCTION(ipgpio),
811 FUNCTION(msp2),
812 FUNCTION(mc4),
813 FUNCTION(mc1),
814 FUNCTION(hsi),
815 FUNCTION(clkout),
816 FUNCTION(usb),
817 FUNCTION(trig),
818 FUNCTION(i2c4),
819 FUNCTION(i2c1),
820 FUNCTION(i2c2),
821 FUNCTION(uartmod),
822 FUNCTION(stmmod),
823 FUNCTION(spi3),
824 FUNCTION(sm),
825 FUNCTION(lcda),
826 FUNCTION(ddrtrig),
827 FUNCTION(pwl),
828 FUNCTION(spi1),
829 FUNCTION(mc3),
830 FUNCTION(ipjtag),
831 FUNCTION(slim0),
832 FUNCTION(ms),
833 FUNCTION(iptrigout),
834 FUNCTION(stmape),
835 FUNCTION(mc5),
836 FUNCTION(usbsim),
837 FUNCTION(i2c3),
838 FUNCTION(spi0),
839 FUNCTION(spi2),
840};
841
842static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
843 .gpio_ranges = nmk_db8500_ranges,
844 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
845 .pins = nmk_db8500_pins,
846 .npins = ARRAY_SIZE(nmk_db8500_pins),
847 .functions = nmk_db8500_functions,
848 .nfunctions = ARRAY_SIZE(nmk_db8500_functions),
849 .groups = nmk_db8500_groups,
850 .ngroups = ARRAY_SIZE(nmk_db8500_groups),
851};
852
853void __devinit
854nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
855{
856 *soc = &nmk_db8500_soc;
857}
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 839624f9fe6..b8e01c3eaa9 100644
--- a/drivers/gpio/gpio-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -22,14 +22,20 @@
22#include <linux/spinlock.h> 22#include <linux/spinlock.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqdomain.h>
25#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf.h>
30/* Since we request GPIOs from ourself */
31#include <linux/pinctrl/consumer.h>
26 32
27#include <asm/mach/irq.h> 33#include <asm/mach/irq.h>
28 34
29#include <plat/pincfg.h> 35#include <plat/pincfg.h>
30#include <plat/gpio-nomadik.h> 36#include <plat/gpio-nomadik.h>
31#include <mach/hardware.h> 37
32#include <asm/gpio.h> 38#include "pinctrl-nomadik.h"
33 39
34/* 40/*
35 * The GPIO module in the Nomadik family of Systems-on-Chip is an 41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -43,6 +49,7 @@
43 49
44struct nmk_gpio_chip { 50struct nmk_gpio_chip {
45 struct gpio_chip chip; 51 struct gpio_chip chip;
52 struct irq_domain *domain;
46 void __iomem *addr; 53 void __iomem *addr;
47 struct clk *clk; 54 struct clk *clk;
48 unsigned int bank; 55 unsigned int bank;
@@ -58,8 +65,16 @@ struct nmk_gpio_chip {
58 u32 real_wake; 65 u32 real_wake;
59 u32 rwimsc; 66 u32 rwimsc;
60 u32 fwimsc; 67 u32 fwimsc;
61 u32 slpm; 68 u32 rimsc;
69 u32 fimsc;
62 u32 pull_up; 70 u32 pull_up;
71 u32 lowemi;
72};
73
74struct nmk_pinctrl {
75 struct device *dev;
76 struct pinctrl_dev *pctl;
77 const struct nmk_pinctrl_soc_data *soc;
63}; 78};
64 79
65static struct nmk_gpio_chip * 80static struct nmk_gpio_chip *
@@ -124,6 +139,24 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
124 } 139 }
125} 140}
126 141
142static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
143 unsigned offset, bool lowemi)
144{
145 u32 bit = BIT(offset);
146 bool enabled = nmk_chip->lowemi & bit;
147
148 if (lowemi == enabled)
149 return;
150
151 if (lowemi)
152 nmk_chip->lowemi |= bit;
153 else
154 nmk_chip->lowemi &= ~bit;
155
156 writel_relaxed(nmk_chip->lowemi,
157 nmk_chip->addr + NMK_GPIO_LOWEMI);
158}
159
127static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 160static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
128 unsigned offset) 161 unsigned offset)
129{ 162{
@@ -150,8 +183,8 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
150 unsigned offset, int gpio_mode, 183 unsigned offset, int gpio_mode,
151 bool glitch) 184 bool glitch)
152{ 185{
153 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); 186 u32 rwimsc = nmk_chip->rwimsc;
154 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); 187 u32 fwimsc = nmk_chip->fwimsc;
155 188
156 if (glitch && nmk_chip->set_ioforce) { 189 if (glitch && nmk_chip->set_ioforce) {
157 u32 bit = BIT(offset); 190 u32 bit = BIT(offset);
@@ -173,6 +206,36 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
173 } 206 }
174} 207}
175 208
209static void
210nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
211{
212 u32 falling = nmk_chip->fimsc & BIT(offset);
213 u32 rising = nmk_chip->rimsc & BIT(offset);
214 int gpio = nmk_chip->chip.base + offset;
215 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
216 struct irq_data *d = irq_get_irq_data(irq);
217
218 if (!rising && !falling)
219 return;
220
221 if (!d || !irqd_irq_disabled(d))
222 return;
223
224 if (rising) {
225 nmk_chip->rimsc &= ~BIT(offset);
226 writel_relaxed(nmk_chip->rimsc,
227 nmk_chip->addr + NMK_GPIO_RIMSC);
228 }
229
230 if (falling) {
231 nmk_chip->fimsc &= ~BIT(offset);
232 writel_relaxed(nmk_chip->fimsc,
233 nmk_chip->addr + NMK_GPIO_FIMSC);
234 }
235
236 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
237}
238
176static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, 239static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
177 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) 240 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
178{ 241{
@@ -238,6 +301,17 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
238 __nmk_gpio_set_pull(nmk_chip, offset, pull); 301 __nmk_gpio_set_pull(nmk_chip, offset, pull);
239 } 302 }
240 303
304 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
305
306 /*
307 * If the pin is switching to altfunc, and there was an interrupt
308 * installed on it which has been lazy disabled, actually mask the
309 * interrupt to prevent spurious interrupts that would occur while the
310 * pin is under control of the peripheral. Only SKE does this.
311 */
312 if (af != NMK_GPIO_ALT_GPIO)
313 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
314
241 /* 315 /*
242 * If we've backed up the SLPM registers (glitch workaround), modify 316 * If we've backed up the SLPM registers (glitch workaround), modify
243 * the backups since they will be restored. 317 * the backups since they will be restored.
@@ -334,7 +408,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
334 struct nmk_gpio_chip *nmk_chip; 408 struct nmk_gpio_chip *nmk_chip;
335 int pin = PIN_NUM(cfgs[i]); 409 int pin = PIN_NUM(cfgs[i]);
336 410
337 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); 411 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
338 if (!nmk_chip) { 412 if (!nmk_chip) {
339 ret = -EINVAL; 413 ret = -EINVAL;
340 break; 414 break;
@@ -342,7 +416,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
342 416
343 clk_enable(nmk_chip->clk); 417 clk_enable(nmk_chip->clk);
344 spin_lock(&nmk_chip->lock); 418 spin_lock(&nmk_chip->lock);
345 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, 419 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
346 cfgs[i], sleep, glitch ? slpm : NULL); 420 cfgs[i], sleep, glitch ? slpm : NULL);
347 spin_unlock(&nmk_chip->lock); 421 spin_unlock(&nmk_chip->lock);
348 clk_disable(nmk_chip->clk); 422 clk_disable(nmk_chip->clk);
@@ -426,7 +500,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
426 struct nmk_gpio_chip *nmk_chip; 500 struct nmk_gpio_chip *nmk_chip;
427 unsigned long flags; 501 unsigned long flags;
428 502
429 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 503 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
430 if (!nmk_chip) 504 if (!nmk_chip)
431 return -EINVAL; 505 return -EINVAL;
432 506
@@ -434,7 +508,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
434 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 508 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
435 spin_lock(&nmk_chip->lock); 509 spin_lock(&nmk_chip->lock);
436 510
437 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); 511 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
438 512
439 spin_unlock(&nmk_chip->lock); 513 spin_unlock(&nmk_chip->lock);
440 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 514 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
@@ -461,13 +535,13 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
461 struct nmk_gpio_chip *nmk_chip; 535 struct nmk_gpio_chip *nmk_chip;
462 unsigned long flags; 536 unsigned long flags;
463 537
464 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 538 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
465 if (!nmk_chip) 539 if (!nmk_chip)
466 return -EINVAL; 540 return -EINVAL;
467 541
468 clk_enable(nmk_chip->clk); 542 clk_enable(nmk_chip->clk);
469 spin_lock_irqsave(&nmk_chip->lock, flags); 543 spin_lock_irqsave(&nmk_chip->lock, flags);
470 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); 544 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
471 spin_unlock_irqrestore(&nmk_chip->lock, flags); 545 spin_unlock_irqrestore(&nmk_chip->lock, flags);
472 clk_disable(nmk_chip->clk); 546 clk_disable(nmk_chip->clk);
473 547
@@ -489,13 +563,13 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode)
489 struct nmk_gpio_chip *nmk_chip; 563 struct nmk_gpio_chip *nmk_chip;
490 unsigned long flags; 564 unsigned long flags;
491 565
492 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 566 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
493 if (!nmk_chip) 567 if (!nmk_chip)
494 return -EINVAL; 568 return -EINVAL;
495 569
496 clk_enable(nmk_chip->clk); 570 clk_enable(nmk_chip->clk);
497 spin_lock_irqsave(&nmk_chip->lock, flags); 571 spin_lock_irqsave(&nmk_chip->lock, flags);
498 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); 572 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
499 spin_unlock_irqrestore(&nmk_chip->lock, flags); 573 spin_unlock_irqrestore(&nmk_chip->lock, flags);
500 clk_disable(nmk_chip->clk); 574 clk_disable(nmk_chip->clk);
501 575
@@ -508,11 +582,11 @@ int nmk_gpio_get_mode(int gpio)
508 struct nmk_gpio_chip *nmk_chip; 582 struct nmk_gpio_chip *nmk_chip;
509 u32 afunc, bfunc, bit; 583 u32 afunc, bfunc, bit;
510 584
511 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 585 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
512 if (!nmk_chip) 586 if (!nmk_chip)
513 return -EINVAL; 587 return -EINVAL;
514 588
515 bit = 1 << (gpio - nmk_chip->chip.base); 589 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
516 590
517 clk_enable(nmk_chip->clk); 591 clk_enable(nmk_chip->clk);
518 592
@@ -529,21 +603,19 @@ EXPORT_SYMBOL(nmk_gpio_get_mode);
529/* IRQ functions */ 603/* IRQ functions */
530static inline int nmk_gpio_get_bitmask(int gpio) 604static inline int nmk_gpio_get_bitmask(int gpio)
531{ 605{
532 return 1 << (gpio % 32); 606 return 1 << (gpio % NMK_GPIO_PER_CHIP);
533} 607}
534 608
535static void nmk_gpio_irq_ack(struct irq_data *d) 609static void nmk_gpio_irq_ack(struct irq_data *d)
536{ 610{
537 int gpio;
538 struct nmk_gpio_chip *nmk_chip; 611 struct nmk_gpio_chip *nmk_chip;
539 612
540 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
541 nmk_chip = irq_data_get_irq_chip_data(d); 613 nmk_chip = irq_data_get_irq_chip_data(d);
542 if (!nmk_chip) 614 if (!nmk_chip)
543 return; 615 return;
544 616
545 clk_enable(nmk_chip->clk); 617 clk_enable(nmk_chip->clk);
546 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); 618 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
547 clk_disable(nmk_chip->clk); 619 clk_disable(nmk_chip->clk);
548} 620}
549 621
@@ -556,37 +628,52 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
556 int gpio, enum nmk_gpio_irq_type which, 628 int gpio, enum nmk_gpio_irq_type which,
557 bool enable) 629 bool enable)
558{ 630{
559 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
560 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
561 u32 bitmask = nmk_gpio_get_bitmask(gpio); 631 u32 bitmask = nmk_gpio_get_bitmask(gpio);
562 u32 reg; 632 u32 *rimscval;
633 u32 *fimscval;
634 u32 rimscreg;
635 u32 fimscreg;
636
637 if (which == NORMAL) {
638 rimscreg = NMK_GPIO_RIMSC;
639 fimscreg = NMK_GPIO_FIMSC;
640 rimscval = &nmk_chip->rimsc;
641 fimscval = &nmk_chip->fimsc;
642 } else {
643 rimscreg = NMK_GPIO_RWIMSC;
644 fimscreg = NMK_GPIO_FWIMSC;
645 rimscval = &nmk_chip->rwimsc;
646 fimscval = &nmk_chip->fwimsc;
647 }
563 648
564 /* we must individually set/clear the two edges */ 649 /* we must individually set/clear the two edges */
565 if (nmk_chip->edge_rising & bitmask) { 650 if (nmk_chip->edge_rising & bitmask) {
566 reg = readl(nmk_chip->addr + rimsc);
567 if (enable) 651 if (enable)
568 reg |= bitmask; 652 *rimscval |= bitmask;
569 else 653 else
570 reg &= ~bitmask; 654 *rimscval &= ~bitmask;
571 writel(reg, nmk_chip->addr + rimsc); 655 writel(*rimscval, nmk_chip->addr + rimscreg);
572 } 656 }
573 if (nmk_chip->edge_falling & bitmask) { 657 if (nmk_chip->edge_falling & bitmask) {
574 reg = readl(nmk_chip->addr + fimsc);
575 if (enable) 658 if (enable)
576 reg |= bitmask; 659 *fimscval |= bitmask;
577 else 660 else
578 reg &= ~bitmask; 661 *fimscval &= ~bitmask;
579 writel(reg, nmk_chip->addr + fimsc); 662 writel(*fimscval, nmk_chip->addr + fimscreg);
580 } 663 }
581} 664}
582 665
583static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 666static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
584 int gpio, bool on) 667 int gpio, bool on)
585{ 668{
586 if (nmk_chip->sleepmode) { 669 /*
587 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, 670 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
588 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE 671 * disabled, since setting SLPM to 1 increases power consumption, and
589 : NMK_GPIO_SLPM_WAKEUP_DISABLE); 672 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
673 */
674 if (nmk_chip->sleepmode && on) {
675 __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
676 NMK_GPIO_SLPM_WAKEUP_ENABLE);
590 } 677 }
591 678
592 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 679 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
@@ -594,14 +681,12 @@ static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
594 681
595static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 682static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
596{ 683{
597 int gpio;
598 struct nmk_gpio_chip *nmk_chip; 684 struct nmk_gpio_chip *nmk_chip;
599 unsigned long flags; 685 unsigned long flags;
600 u32 bitmask; 686 u32 bitmask;
601 687
602 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
603 nmk_chip = irq_data_get_irq_chip_data(d); 688 nmk_chip = irq_data_get_irq_chip_data(d);
604 bitmask = nmk_gpio_get_bitmask(gpio); 689 bitmask = nmk_gpio_get_bitmask(d->hwirq);
605 if (!nmk_chip) 690 if (!nmk_chip)
606 return -EINVAL; 691 return -EINVAL;
607 692
@@ -609,10 +694,10 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
609 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 694 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
610 spin_lock(&nmk_chip->lock); 695 spin_lock(&nmk_chip->lock);
611 696
612 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); 697 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
613 698
614 if (!(nmk_chip->real_wake & bitmask)) 699 if (!(nmk_chip->real_wake & bitmask))
615 __nmk_gpio_set_wake(nmk_chip, gpio, enable); 700 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
616 701
617 spin_unlock(&nmk_chip->lock); 702 spin_unlock(&nmk_chip->lock);
618 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 703 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
@@ -636,20 +721,18 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
636 struct nmk_gpio_chip *nmk_chip; 721 struct nmk_gpio_chip *nmk_chip;
637 unsigned long flags; 722 unsigned long flags;
638 u32 bitmask; 723 u32 bitmask;
639 int gpio;
640 724
641 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
642 nmk_chip = irq_data_get_irq_chip_data(d); 725 nmk_chip = irq_data_get_irq_chip_data(d);
643 if (!nmk_chip) 726 if (!nmk_chip)
644 return -EINVAL; 727 return -EINVAL;
645 bitmask = nmk_gpio_get_bitmask(gpio); 728 bitmask = nmk_gpio_get_bitmask(d->hwirq);
646 729
647 clk_enable(nmk_chip->clk); 730 clk_enable(nmk_chip->clk);
648 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 731 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
649 spin_lock(&nmk_chip->lock); 732 spin_lock(&nmk_chip->lock);
650 733
651 if (irqd_irq_disabled(d)) 734 if (irqd_irq_disabled(d))
652 __nmk_gpio_set_wake(nmk_chip, gpio, on); 735 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
653 736
654 if (on) 737 if (on)
655 nmk_chip->real_wake |= bitmask; 738 nmk_chip->real_wake |= bitmask;
@@ -667,17 +750,14 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
667{ 750{
668 bool enabled = !irqd_irq_disabled(d); 751 bool enabled = !irqd_irq_disabled(d);
669 bool wake = irqd_is_wakeup_set(d); 752 bool wake = irqd_is_wakeup_set(d);
670 int gpio;
671 struct nmk_gpio_chip *nmk_chip; 753 struct nmk_gpio_chip *nmk_chip;
672 unsigned long flags; 754 unsigned long flags;
673 u32 bitmask; 755 u32 bitmask;
674 756
675 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
676 nmk_chip = irq_data_get_irq_chip_data(d); 757 nmk_chip = irq_data_get_irq_chip_data(d);
677 bitmask = nmk_gpio_get_bitmask(gpio); 758 bitmask = nmk_gpio_get_bitmask(d->hwirq);
678 if (!nmk_chip) 759 if (!nmk_chip)
679 return -EINVAL; 760 return -EINVAL;
680
681 if (type & IRQ_TYPE_LEVEL_HIGH) 761 if (type & IRQ_TYPE_LEVEL_HIGH)
682 return -EINVAL; 762 return -EINVAL;
683 if (type & IRQ_TYPE_LEVEL_LOW) 763 if (type & IRQ_TYPE_LEVEL_LOW)
@@ -687,10 +767,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
687 spin_lock_irqsave(&nmk_chip->lock, flags); 767 spin_lock_irqsave(&nmk_chip->lock, flags);
688 768
689 if (enabled) 769 if (enabled)
690 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); 770 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
691 771
692 if (enabled || wake) 772 if (enabled || wake)
693 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); 773 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
694 774
695 nmk_chip->edge_rising &= ~bitmask; 775 nmk_chip->edge_rising &= ~bitmask;
696 if (type & IRQ_TYPE_EDGE_RISING) 776 if (type & IRQ_TYPE_EDGE_RISING)
@@ -701,10 +781,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
701 nmk_chip->edge_falling |= bitmask; 781 nmk_chip->edge_falling |= bitmask;
702 782
703 if (enabled) 783 if (enabled)
704 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); 784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
705 785
706 if (enabled || wake) 786 if (enabled || wake)
707 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); 787 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
708 788
709 spin_unlock_irqrestore(&nmk_chip->lock, flags); 789 spin_unlock_irqrestore(&nmk_chip->lock, flags);
710 clk_disable(nmk_chip->clk); 790 clk_disable(nmk_chip->clk);
@@ -750,7 +830,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
750 chained_irq_enter(host_chip, desc); 830 chained_irq_enter(host_chip, desc);
751 831
752 nmk_chip = irq_get_handler_data(irq); 832 nmk_chip = irq_get_handler_data(irq);
753 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 833 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
754 while (status) { 834 while (status) {
755 int bit = __ffs(status); 835 int bit = __ffs(status);
756 836
@@ -784,18 +864,6 @@ static void nmk_gpio_secondary_irq_handler(unsigned int irq,
784 864
785static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) 865static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
786{ 866{
787 unsigned int first_irq;
788 int i;
789
790 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
791 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
792 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
793 handle_edge_irq);
794 set_irq_flags(i, IRQF_VALID);
795 irq_set_chip_data(i, nmk_chip);
796 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
797 }
798
799 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); 867 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
800 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); 868 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
801 869
@@ -809,6 +877,25 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
809} 877}
810 878
811/* I/O Functions */ 879/* I/O Functions */
880
881static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
882{
883 /*
884 * Map back to global GPIO space and request muxing, the direction
885 * parameter does not matter for this controller.
886 */
887 int gpio = chip->base + offset;
888
889 return pinctrl_request_gpio(gpio);
890}
891
892static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
893{
894 int gpio = chip->base + offset;
895
896 pinctrl_free_gpio(gpio);
897}
898
812static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 899static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
813{ 900{
814 struct nmk_gpio_chip *nmk_chip = 901 struct nmk_gpio_chip *nmk_chip =
@@ -872,21 +959,23 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
872 struct nmk_gpio_chip *nmk_chip = 959 struct nmk_gpio_chip *nmk_chip =
873 container_of(chip, struct nmk_gpio_chip, chip); 960 container_of(chip, struct nmk_gpio_chip, chip);
874 961
875 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; 962 return irq_find_mapping(nmk_chip->domain, offset);
876} 963}
877 964
878#ifdef CONFIG_DEBUG_FS 965#ifdef CONFIG_DEBUG_FS
879 966
880#include <linux/seq_file.h> 967#include <linux/seq_file.h>
881 968
882static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 969static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
970 unsigned offset, unsigned gpio)
883{ 971{
884 int mode; 972 const char *label = gpiochip_is_requested(chip, offset);
885 unsigned i;
886 unsigned gpio = chip->base;
887 int is_out;
888 struct nmk_gpio_chip *nmk_chip = 973 struct nmk_gpio_chip *nmk_chip =
889 container_of(chip, struct nmk_gpio_chip, chip); 974 container_of(chip, struct nmk_gpio_chip, chip);
975 int mode;
976 bool is_out;
977 bool pull;
978 u32 bit = 1 << offset;
890 const char *modes[] = { 979 const char *modes[] = {
891 [NMK_GPIO_ALT_GPIO] = "gpio", 980 [NMK_GPIO_ALT_GPIO] = "gpio",
892 [NMK_GPIO_ALT_A] = "altA", 981 [NMK_GPIO_ALT_A] = "altA",
@@ -895,61 +984,70 @@ static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
895 }; 984 };
896 985
897 clk_enable(nmk_chip->clk); 986 clk_enable(nmk_chip->clk);
898 987 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
899 for (i = 0; i < chip->ngpio; i++, gpio++) { 988 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
900 const char *label = gpiochip_is_requested(chip, i); 989 mode = nmk_gpio_get_mode(gpio);
901 bool pull; 990
902 u32 bit = 1 << i; 991 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
903 992 gpio, label ?: "(none)",
904 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; 993 is_out ? "out" : "in ",
905 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 994 chip->get
906 mode = nmk_gpio_get_mode(gpio); 995 ? (chip->get(chip, offset) ? "hi" : "lo")
907 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 996 : "? ",
908 gpio, label ?: "(none)", 997 (mode < 0) ? "unknown" : modes[mode],
909 is_out ? "out" : "in ", 998 pull ? "pull" : "none");
910 chip->get 999
911 ? (chip->get(chip, i) ? "hi" : "lo") 1000 if (label && !is_out) {
912 : "? ", 1001 int irq = gpio_to_irq(gpio);
913 (mode < 0) ? "unknown" : modes[mode], 1002 struct irq_desc *desc = irq_to_desc(irq);
914 pull ? "pull" : "none"); 1003
915 1004 /* This races with request_irq(), set_irq_type(),
916 if (label && !is_out) { 1005 * and set_irq_wake() ... but those are "rare".
917 int irq = gpio_to_irq(gpio); 1006 */
918 struct irq_desc *desc = irq_to_desc(irq); 1007 if (irq >= 0 && desc->action) {
919 1008 char *trigger;
920 /* This races with request_irq(), set_irq_type(), 1009 u32 bitmask = nmk_gpio_get_bitmask(gpio);
921 * and set_irq_wake() ... but those are "rare". 1010
922 */ 1011 if (nmk_chip->edge_rising & bitmask)
923 if (irq >= 0 && desc->action) { 1012 trigger = "edge-rising";
924 char *trigger; 1013 else if (nmk_chip->edge_falling & bitmask)
925 u32 bitmask = nmk_gpio_get_bitmask(gpio); 1014 trigger = "edge-falling";
926 1015 else
927 if (nmk_chip->edge_rising & bitmask) 1016 trigger = "edge-undefined";
928 trigger = "edge-rising"; 1017
929 else if (nmk_chip->edge_falling & bitmask) 1018 seq_printf(s, " irq-%d %s%s",
930 trigger = "edge-falling"; 1019 irq, trigger,
931 else 1020 irqd_is_wakeup_set(&desc->irq_data)
932 trigger = "edge-undefined"; 1021 ? " wakeup" : "");
933
934 seq_printf(s, " irq-%d %s%s",
935 irq, trigger,
936 irqd_is_wakeup_set(&desc->irq_data)
937 ? " wakeup" : "");
938 }
939 } 1022 }
1023 }
1024 clk_disable(nmk_chip->clk);
1025}
940 1026
1027static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1028{
1029 unsigned i;
1030 unsigned gpio = chip->base;
1031
1032 for (i = 0; i < chip->ngpio; i++, gpio++) {
1033 nmk_gpio_dbg_show_one(s, chip, i, gpio);
941 seq_printf(s, "\n"); 1034 seq_printf(s, "\n");
942 } 1035 }
943
944 clk_disable(nmk_chip->clk);
945} 1036}
946 1037
947#else 1038#else
1039static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1040 struct gpio_chip *chip,
1041 unsigned offset, unsigned gpio)
1042{
1043}
948#define nmk_gpio_dbg_show NULL 1044#define nmk_gpio_dbg_show NULL
949#endif 1045#endif
950 1046
951/* This structure is replicated for each GPIO block allocated at probe time */ 1047/* This structure is replicated for each GPIO block allocated at probe time */
952static struct gpio_chip nmk_gpio_template = { 1048static struct gpio_chip nmk_gpio_template = {
1049 .request = nmk_gpio_request,
1050 .free = nmk_gpio_free,
953 .direction_input = nmk_gpio_make_input, 1051 .direction_input = nmk_gpio_make_input,
954 .get = nmk_gpio_get_input, 1052 .get = nmk_gpio_get_input,
955 .direction_output = nmk_gpio_make_output, 1053 .direction_output = nmk_gpio_make_output,
@@ -1008,21 +1106,11 @@ void nmk_gpio_wakeups_suspend(void)
1008 1106
1009 clk_enable(chip->clk); 1107 clk_enable(chip->clk);
1010 1108
1011 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
1012 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
1013
1014 writel(chip->rwimsc & chip->real_wake, 1109 writel(chip->rwimsc & chip->real_wake,
1015 chip->addr + NMK_GPIO_RWIMSC); 1110 chip->addr + NMK_GPIO_RWIMSC);
1016 writel(chip->fwimsc & chip->real_wake, 1111 writel(chip->fwimsc & chip->real_wake,
1017 chip->addr + NMK_GPIO_FWIMSC); 1112 chip->addr + NMK_GPIO_FWIMSC);
1018 1113
1019 if (chip->sleepmode) {
1020 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
1021
1022 /* 0 -> wakeup enable */
1023 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
1024 }
1025
1026 clk_disable(chip->clk); 1114 clk_disable(chip->clk);
1027 } 1115 }
1028} 1116}
@@ -1042,9 +1130,6 @@ void nmk_gpio_wakeups_resume(void)
1042 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 1130 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1043 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 1131 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1044 1132
1045 if (chip->sleepmode)
1046 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
1047
1048 clk_disable(chip->clk); 1133 clk_disable(chip->clk);
1049 } 1134 }
1050} 1135}
@@ -1068,19 +1153,62 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1068 } 1153 }
1069} 1154}
1070 1155
1156int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1157 irq_hw_number_t hwirq)
1158{
1159 struct nmk_gpio_chip *nmk_chip = d->host_data;
1160
1161 if (!nmk_chip)
1162 return -EINVAL;
1163
1164 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1165 set_irq_flags(irq, IRQF_VALID);
1166 irq_set_chip_data(irq, nmk_chip);
1167 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1168
1169 return 0;
1170}
1171
1172const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1173 .map = nmk_gpio_irq_map,
1174 .xlate = irq_domain_xlate_twocell,
1175};
1176
1071static int __devinit nmk_gpio_probe(struct platform_device *dev) 1177static int __devinit nmk_gpio_probe(struct platform_device *dev)
1072{ 1178{
1073 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 1179 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1180 struct device_node *np = dev->dev.of_node;
1074 struct nmk_gpio_chip *nmk_chip; 1181 struct nmk_gpio_chip *nmk_chip;
1075 struct gpio_chip *chip; 1182 struct gpio_chip *chip;
1076 struct resource *res; 1183 struct resource *res;
1077 struct clk *clk; 1184 struct clk *clk;
1078 int secondary_irq; 1185 int secondary_irq;
1186 void __iomem *base;
1079 int irq; 1187 int irq;
1080 int ret; 1188 int ret;
1081 1189
1082 if (!pdata) 1190 if (!pdata && !np) {
1191 dev_err(&dev->dev, "No platform data or device tree found\n");
1083 return -ENODEV; 1192 return -ENODEV;
1193 }
1194
1195 if (np) {
1196 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1197 if (!pdata)
1198 return -ENOMEM;
1199
1200 if (of_get_property(np, "supports-sleepmode", NULL))
1201 pdata->supports_sleepmode = true;
1202
1203 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1204 dev_err(&dev->dev, "gpio-bank property not found\n");
1205 ret = -EINVAL;
1206 goto out;
1207 }
1208
1209 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1210 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1211 }
1084 1212
1085 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1213 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1086 if (!res) { 1214 if (!res) {
@@ -1106,10 +1234,16 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1106 goto out; 1234 goto out;
1107 } 1235 }
1108 1236
1237 base = ioremap(res->start, resource_size(res));
1238 if (!base) {
1239 ret = -ENOMEM;
1240 goto out_release;
1241 }
1242
1109 clk = clk_get(&dev->dev, NULL); 1243 clk = clk_get(&dev->dev, NULL);
1110 if (IS_ERR(clk)) { 1244 if (IS_ERR(clk)) {
1111 ret = PTR_ERR(clk); 1245 ret = PTR_ERR(clk);
1112 goto out_release; 1246 goto out_unmap;
1113 } 1247 }
1114 1248
1115 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); 1249 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
@@ -1117,13 +1251,14 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1117 ret = -ENOMEM; 1251 ret = -ENOMEM;
1118 goto out_clk; 1252 goto out_clk;
1119 } 1253 }
1254
1120 /* 1255 /*
1121 * The virt address in nmk_chip->addr is in the nomadik register space, 1256 * The virt address in nmk_chip->addr is in the nomadik register space,
1122 * so we can simply convert the resource address, without remapping 1257 * so we can simply convert the resource address, without remapping
1123 */ 1258 */
1124 nmk_chip->bank = dev->id; 1259 nmk_chip->bank = dev->id;
1125 nmk_chip->clk = clk; 1260 nmk_chip->clk = clk;
1126 nmk_chip->addr = io_p2v(res->start); 1261 nmk_chip->addr = base;
1127 nmk_chip->chip = nmk_gpio_template; 1262 nmk_chip->chip = nmk_gpio_template;
1128 nmk_chip->parent_irq = irq; 1263 nmk_chip->parent_irq = irq;
1129 nmk_chip->secondary_parent_irq = secondary_irq; 1264 nmk_chip->secondary_parent_irq = secondary_irq;
@@ -1139,6 +1274,14 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1139 chip->dev = &dev->dev; 1274 chip->dev = &dev->dev;
1140 chip->owner = THIS_MODULE; 1275 chip->owner = THIS_MODULE;
1141 1276
1277 clk_enable(nmk_chip->clk);
1278 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1279 clk_disable(nmk_chip->clk);
1280
1281#ifdef CONFIG_OF_GPIO
1282 chip->of_node = np;
1283#endif
1284
1142 ret = gpiochip_add(&nmk_chip->chip); 1285 ret = gpiochip_add(&nmk_chip->chip);
1143 if (ret) 1286 if (ret)
1144 goto out_free; 1287 goto out_free;
@@ -1146,12 +1289,22 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1146 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1289 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1147 1290
1148 nmk_gpio_chips[nmk_chip->bank] = nmk_chip; 1291 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1292
1149 platform_set_drvdata(dev, nmk_chip); 1293 platform_set_drvdata(dev, nmk_chip);
1150 1294
1295 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1296 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1297 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1298 if (!nmk_chip->domain) {
1299 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1300 ret = -ENOSYS;
1301 goto out_free;
1302 }
1303
1151 nmk_gpio_init_irq(nmk_chip); 1304 nmk_gpio_init_irq(nmk_chip);
1152 1305
1153 dev_info(&dev->dev, "at address %p\n", 1306 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1154 nmk_chip->addr); 1307
1155 return 0; 1308 return 0;
1156 1309
1157out_free: 1310out_free:
@@ -1159,25 +1312,465 @@ out_free:
1159out_clk: 1312out_clk:
1160 clk_disable(clk); 1313 clk_disable(clk);
1161 clk_put(clk); 1314 clk_put(clk);
1315out_unmap:
1316 iounmap(base);
1162out_release: 1317out_release:
1163 release_mem_region(res->start, resource_size(res)); 1318 release_mem_region(res->start, resource_size(res));
1164out: 1319out:
1165 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, 1320 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1166 pdata->first_gpio, pdata->first_gpio+31); 1321 pdata->first_gpio, pdata->first_gpio+31);
1322 if (np)
1323 kfree(pdata);
1324
1167 return ret; 1325 return ret;
1168} 1326}
1169 1327
1328static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1329{
1330 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1331
1332 return npct->soc->ngroups;
1333}
1334
1335static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1336 unsigned selector)
1337{
1338 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1339
1340 return npct->soc->groups[selector].name;
1341}
1342
1343static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1344 const unsigned **pins,
1345 unsigned *num_pins)
1346{
1347 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1348
1349 *pins = npct->soc->groups[selector].pins;
1350 *num_pins = npct->soc->groups[selector].npins;
1351 return 0;
1352}
1353
1354static struct pinctrl_gpio_range *
1355nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1356{
1357 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1358 int i;
1359
1360 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1361 struct pinctrl_gpio_range *range;
1362
1363 range = &npct->soc->gpio_ranges[i];
1364 if (offset >= range->pin_base &&
1365 offset <= (range->pin_base + range->npins - 1))
1366 return range;
1367 }
1368 return NULL;
1369}
1370
1371static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1372 unsigned offset)
1373{
1374 struct pinctrl_gpio_range *range;
1375 struct gpio_chip *chip;
1376
1377 range = nmk_match_gpio_range(pctldev, offset);
1378 if (!range || !range->gc) {
1379 seq_printf(s, "invalid pin offset");
1380 return;
1381 }
1382 chip = range->gc;
1383 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1384}
1385
1386static struct pinctrl_ops nmk_pinctrl_ops = {
1387 .get_groups_count = nmk_get_groups_cnt,
1388 .get_group_name = nmk_get_group_name,
1389 .get_group_pins = nmk_get_group_pins,
1390 .pin_dbg_show = nmk_pin_dbg_show,
1391};
1392
1393static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1394{
1395 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1396
1397 return npct->soc->nfunctions;
1398}
1399
1400static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1401 unsigned function)
1402{
1403 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1404
1405 return npct->soc->functions[function].name;
1406}
1407
1408static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1409 unsigned function,
1410 const char * const **groups,
1411 unsigned * const num_groups)
1412{
1413 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1414
1415 *groups = npct->soc->functions[function].groups;
1416 *num_groups = npct->soc->functions[function].ngroups;
1417
1418 return 0;
1419}
1420
1421static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1422 unsigned group)
1423{
1424 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1425 const struct nmk_pingroup *g;
1426 static unsigned int slpm[NUM_BANKS];
1427 unsigned long flags;
1428 bool glitch;
1429 int ret = -EINVAL;
1430 int i;
1431
1432 g = &npct->soc->groups[group];
1433
1434 if (g->altsetting < 0)
1435 return -EINVAL;
1436
1437 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1438
1439 /* Handle this special glitch on altfunction C */
1440 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1441
1442 if (glitch) {
1443 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1444
1445 /* Initially don't put any pins to sleep when switching */
1446 memset(slpm, 0xff, sizeof(slpm));
1447
1448 /*
1449 * Then mask the pins that need to be sleeping now when we're
1450 * switching to the ALT C function.
1451 */
1452 for (i = 0; i < g->npins; i++)
1453 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1454 nmk_gpio_glitch_slpm_init(slpm);
1455 }
1456
1457 for (i = 0; i < g->npins; i++) {
1458 struct pinctrl_gpio_range *range;
1459 struct nmk_gpio_chip *nmk_chip;
1460 struct gpio_chip *chip;
1461 unsigned bit;
1462
1463 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1464 if (!range) {
1465 dev_err(npct->dev,
1466 "invalid pin offset %d in group %s at index %d\n",
1467 g->pins[i], g->name, i);
1468 goto out_glitch;
1469 }
1470 if (!range->gc) {
1471 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1472 g->pins[i], g->name, i);
1473 goto out_glitch;
1474 }
1475 chip = range->gc;
1476 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1477 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1478
1479 clk_enable(nmk_chip->clk);
1480 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1481 /*
1482 * If the pin is switching to altfunc, and there was an
1483 * interrupt installed on it which has been lazy disabled,
1484 * actually mask the interrupt to prevent spurious interrupts
1485 * that would occur while the pin is under control of the
1486 * peripheral. Only SKE does this.
1487 */
1488 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1489
1490 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1491 clk_disable(nmk_chip->clk);
1492 }
1493
1494 /* When all pins are successfully reconfigured we get here */
1495 ret = 0;
1496
1497out_glitch:
1498 if (glitch) {
1499 nmk_gpio_glitch_slpm_restore(slpm);
1500 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1501 }
1502
1503 return ret;
1504}
1505
1506static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1507 unsigned function, unsigned group)
1508{
1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1510 const struct nmk_pingroup *g;
1511
1512 g = &npct->soc->groups[group];
1513
1514 if (g->altsetting < 0)
1515 return;
1516
1517 /* Poke out the mux, set the pin to some default state? */
1518 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1519}
1520
1521int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1522 struct pinctrl_gpio_range *range,
1523 unsigned offset)
1524{
1525 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1526 struct nmk_gpio_chip *nmk_chip;
1527 struct gpio_chip *chip;
1528 unsigned bit;
1529
1530 if (!range) {
1531 dev_err(npct->dev, "invalid range\n");
1532 return -EINVAL;
1533 }
1534 if (!range->gc) {
1535 dev_err(npct->dev, "missing GPIO chip in range\n");
1536 return -EINVAL;
1537 }
1538 chip = range->gc;
1539 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1540
1541 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1542
1543 clk_enable(nmk_chip->clk);
1544 bit = offset % NMK_GPIO_PER_CHIP;
1545 /* There is no glitch when converting any pin to GPIO */
1546 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1547 clk_disable(nmk_chip->clk);
1548
1549 return 0;
1550}
1551
1552void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1553 struct pinctrl_gpio_range *range,
1554 unsigned offset)
1555{
1556 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1557
1558 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1559 /* Set the pin to some default state, GPIO is usually default */
1560}
1561
1562static struct pinmux_ops nmk_pinmux_ops = {
1563 .get_functions_count = nmk_pmx_get_funcs_cnt,
1564 .get_function_name = nmk_pmx_get_func_name,
1565 .get_function_groups = nmk_pmx_get_func_groups,
1566 .enable = nmk_pmx_enable,
1567 .disable = nmk_pmx_disable,
1568 .gpio_request_enable = nmk_gpio_request_enable,
1569 .gpio_disable_free = nmk_gpio_disable_free,
1570};
1571
1572int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1573 unsigned pin,
1574 unsigned long *config)
1575{
1576 /* Not implemented */
1577 return -EINVAL;
1578}
1579
1580int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1581 unsigned pin,
1582 unsigned long config)
1583{
1584 static const char *pullnames[] = {
1585 [NMK_GPIO_PULL_NONE] = "none",
1586 [NMK_GPIO_PULL_UP] = "up",
1587 [NMK_GPIO_PULL_DOWN] = "down",
1588 [3] /* illegal */ = "??"
1589 };
1590 static const char *slpmnames[] = {
1591 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1592 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1593 };
1594 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1595 struct nmk_gpio_chip *nmk_chip;
1596 struct pinctrl_gpio_range *range;
1597 struct gpio_chip *chip;
1598 unsigned bit;
1599
1600 /*
1601 * The pin config contains pin number and altfunction fields, here
1602 * we just ignore that part. It's being handled by the framework and
1603 * pinmux callback respectively.
1604 */
1605 pin_cfg_t cfg = (pin_cfg_t) config;
1606 int pull = PIN_PULL(cfg);
1607 int slpm = PIN_SLPM(cfg);
1608 int output = PIN_DIR(cfg);
1609 int val = PIN_VAL(cfg);
1610 bool lowemi = PIN_LOWEMI(cfg);
1611 bool gpiomode = PIN_GPIOMODE(cfg);
1612 bool sleep = PIN_SLEEPMODE(cfg);
1613
1614 range = nmk_match_gpio_range(pctldev, pin);
1615 if (!range) {
1616 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1617 return -EINVAL;
1618 }
1619 if (!range->gc) {
1620 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1621 pin);
1622 return -EINVAL;
1623 }
1624 chip = range->gc;
1625 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1626
1627 if (sleep) {
1628 int slpm_pull = PIN_SLPM_PULL(cfg);
1629 int slpm_output = PIN_SLPM_DIR(cfg);
1630 int slpm_val = PIN_SLPM_VAL(cfg);
1631
1632 /* All pins go into GPIO mode at sleep */
1633 gpiomode = true;
1634
1635 /*
1636 * The SLPM_* values are normal values + 1 to allow zero to
1637 * mean "same as normal".
1638 */
1639 if (slpm_pull)
1640 pull = slpm_pull - 1;
1641 if (slpm_output)
1642 output = slpm_output - 1;
1643 if (slpm_val)
1644 val = slpm_val - 1;
1645
1646 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1647 pin,
1648 slpm_pull ? pullnames[pull] : "same",
1649 slpm_output ? (output ? "output" : "input") : "same",
1650 slpm_val ? (val ? "high" : "low") : "same");
1651 }
1652
1653 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1654 pin, cfg, pullnames[pull], slpmnames[slpm],
1655 output ? "output " : "input",
1656 output ? (val ? "high" : "low") : "",
1657 lowemi ? "on" : "off" );
1658
1659 clk_enable(nmk_chip->clk);
1660 bit = pin % NMK_GPIO_PER_CHIP;
1661 if (gpiomode)
1662 /* No glitch when going to GPIO mode */
1663 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1664 if (output)
1665 __nmk_gpio_make_output(nmk_chip, bit, val);
1666 else {
1667 __nmk_gpio_make_input(nmk_chip, bit);
1668 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1669 }
1670 /* TODO: isn't this only applicable on output pins? */
1671 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1672
1673 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1674 clk_disable(nmk_chip->clk);
1675 return 0;
1676}
1677
1678static struct pinconf_ops nmk_pinconf_ops = {
1679 .pin_config_get = nmk_pin_config_get,
1680 .pin_config_set = nmk_pin_config_set,
1681};
1682
1683static struct pinctrl_desc nmk_pinctrl_desc = {
1684 .name = "pinctrl-nomadik",
1685 .pctlops = &nmk_pinctrl_ops,
1686 .pmxops = &nmk_pinmux_ops,
1687 .confops = &nmk_pinconf_ops,
1688 .owner = THIS_MODULE,
1689};
1690
1691static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1692{
1693 const struct platform_device_id *platid = platform_get_device_id(pdev);
1694 struct nmk_pinctrl *npct;
1695 int i;
1696
1697 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1698 if (!npct)
1699 return -ENOMEM;
1700
1701 /* Poke in other ASIC variants here */
1702 if (platid->driver_data == PINCTRL_NMK_DB8500)
1703 nmk_pinctrl_db8500_init(&npct->soc);
1704
1705 /*
1706 * We need all the GPIO drivers to probe FIRST, or we will not be able
1707 * to obtain references to the struct gpio_chip * for them, and we
1708 * need this to proceed.
1709 */
1710 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1711 if (!nmk_gpio_chips[i]) {
1712 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1713 devm_kfree(&pdev->dev, npct);
1714 return -EPROBE_DEFER;
1715 }
1716 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1717 }
1718
1719 nmk_pinctrl_desc.pins = npct->soc->pins;
1720 nmk_pinctrl_desc.npins = npct->soc->npins;
1721 npct->dev = &pdev->dev;
1722 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1723 if (!npct->pctl) {
1724 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1725 return -EINVAL;
1726 }
1727
1728 /* We will handle a range of GPIO pins */
1729 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1730 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1731
1732 platform_set_drvdata(pdev, npct);
1733 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1734
1735 return 0;
1736}
1737
1738static const struct of_device_id nmk_gpio_match[] = {
1739 { .compatible = "st,nomadik-gpio", },
1740 {}
1741};
1742
1170static struct platform_driver nmk_gpio_driver = { 1743static struct platform_driver nmk_gpio_driver = {
1171 .driver = { 1744 .driver = {
1172 .owner = THIS_MODULE, 1745 .owner = THIS_MODULE,
1173 .name = "gpio", 1746 .name = "gpio",
1747 .of_match_table = nmk_gpio_match,
1174 }, 1748 },
1175 .probe = nmk_gpio_probe, 1749 .probe = nmk_gpio_probe,
1176}; 1750};
1177 1751
1752static const struct platform_device_id nmk_pinctrl_id[] = {
1753 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1754 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1755};
1756
1757static struct platform_driver nmk_pinctrl_driver = {
1758 .driver = {
1759 .owner = THIS_MODULE,
1760 .name = "pinctrl-nomadik",
1761 },
1762 .probe = nmk_pinctrl_probe,
1763 .id_table = nmk_pinctrl_id,
1764};
1765
1178static int __init nmk_gpio_init(void) 1766static int __init nmk_gpio_init(void)
1179{ 1767{
1180 return platform_driver_register(&nmk_gpio_driver); 1768 int ret;
1769
1770 ret = platform_driver_register(&nmk_gpio_driver);
1771 if (ret)
1772 return ret;
1773 return platform_driver_register(&nmk_pinctrl_driver);
1181} 1774}
1182 1775
1183core_initcall(nmk_gpio_init); 1776core_initcall(nmk_gpio_init);
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
new file mode 100644
index 00000000000..bc91aed7185
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -0,0 +1,77 @@
1#ifndef PINCTRL_PINCTRL_NOMADIK_H
2#define PINCTRL_PINCTRL_NOMADIK_H
3
4#include <plat/gpio-nomadik.h>
5
6/* Package definitions */
7#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1
9
10/**
11 * struct nmk_function - Nomadik pinctrl mux function
12 * @name: The name of the function, exported to pinctrl core.
13 * @groups: An array of pin groups that may select this function.
14 * @ngroups: The number of entries in @groups.
15 */
16struct nmk_function {
17 const char *name;
18 const char * const *groups;
19 unsigned ngroups;
20};
21
22/**
23 * struct nmk_pingroup - describes a Nomadik pin group
24 * @name: the name of this specific pin group
25 * @pins: an array of discrete physical pins used in this group, taken
26 * from the driver-local pin enumeration space
27 * @num_pins: the number of pins in this group array, i.e. the number of
28 * elements in .pins so we can iterate over that array
29 * @altsetting: the altsetting to apply to all pins in this group to
30 * configure them to be used by a function
31 */
32struct nmk_pingroup {
33 const char *name;
34 const unsigned int *pins;
35 const unsigned npins;
36 int altsetting;
37};
38
39/**
40 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
41 * @gpio_ranges: An array of GPIO ranges for this SoC
42 * @gpio_num_ranges: The number of GPIO ranges for this SoC
43 * @pins: An array describing all pins the pin controller affects.
44 * All pins which are also GPIOs must be listed first within the
45 * array, and be numbered identically to the GPIO controller's
46 * numbering.
47 * @npins: The number of entries in @pins.
48 * @functions: The functions supported on this SoC.
49 * @nfunction: The number of entries in @functions.
50 * @groups: An array describing all pin groups the pin SoC supports.
51 * @ngroups: The number of entries in @groups.
52 */
53struct nmk_pinctrl_soc_data {
54 struct pinctrl_gpio_range *gpio_ranges;
55 unsigned gpio_num_ranges;
56 const struct pinctrl_pin_desc *pins;
57 unsigned npins;
58 const struct nmk_function *functions;
59 unsigned nfunctions;
60 const struct nmk_pingroup *groups;
61 unsigned ngroups;
62};
63
64#ifdef CONFIG_PINCTRL_DB8500
65
66void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
67
68#else
69
70static inline void
71nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
72{
73}
74
75#endif
76
77#endif /* PINCTRL_PINCTRL_NOMADIK_H */
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 2c98fba01ca..b6934867d8d 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Driver for the NVIDIA Tegra pinmux 2 * Driver for the NVIDIA Tegra pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
@@ -22,7 +22,8 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/of_device.h> 25#include <linux/of.h>
26#include <linux/platform_device.h>
26#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinctrl.h> 28#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h> 29#include <linux/pinctrl/pinmux.h>
@@ -31,10 +32,9 @@
31 32
32#include <mach/pinconf-tegra.h> 33#include <mach/pinconf-tegra.h>
33 34
35#include "core.h"
34#include "pinctrl-tegra.h" 36#include "pinctrl-tegra.h"
35 37
36#define DRIVER_NAME "tegra-pinmux-disabled"
37
38struct tegra_pmx { 38struct tegra_pmx {
39 struct device *dev; 39 struct device *dev;
40 struct pinctrl_dev *pctl; 40 struct pinctrl_dev *pctl;
@@ -83,15 +83,18 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
83 return 0; 83 return 0;
84} 84}
85 85
86#ifdef CONFIG_DEBUG_FS
86static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 87static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
87 struct seq_file *s, 88 struct seq_file *s,
88 unsigned offset) 89 unsigned offset)
89{ 90{
90 seq_printf(s, " " DRIVER_NAME); 91 seq_printf(s, " %s", dev_name(pctldev->dev));
91} 92}
93#endif
92 94
93static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, 95static int reserve_map(struct device *dev, struct pinctrl_map **map,
94 unsigned *num_maps, unsigned reserve) 96 unsigned *reserved_maps, unsigned *num_maps,
97 unsigned reserve)
95{ 98{
96 unsigned old_num = *reserved_maps; 99 unsigned old_num = *reserved_maps;
97 unsigned new_num = *num_maps + reserve; 100 unsigned new_num = *num_maps + reserve;
@@ -101,8 +104,10 @@ static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
101 return 0; 104 return 0;
102 105
103 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); 106 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
104 if (!new_map) 107 if (!new_map) {
108 dev_err(dev, "krealloc(map) failed\n");
105 return -ENOMEM; 109 return -ENOMEM;
110 }
106 111
107 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); 112 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
108 113
@@ -116,7 +121,7 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
116 unsigned *num_maps, const char *group, 121 unsigned *num_maps, const char *group,
117 const char *function) 122 const char *function)
118{ 123{
119 if (*num_maps == *reserved_maps) 124 if (WARN_ON(*num_maps == *reserved_maps))
120 return -ENOSPC; 125 return -ENOSPC;
121 126
122 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 127 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
@@ -127,19 +132,22 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
127 return 0; 132 return 0;
128} 133}
129 134
130static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps, 135static int add_map_configs(struct device *dev, struct pinctrl_map **map,
131 unsigned *num_maps, const char *group, 136 unsigned *reserved_maps, unsigned *num_maps,
132 unsigned long *configs, unsigned num_configs) 137 const char *group, unsigned long *configs,
138 unsigned num_configs)
133{ 139{
134 unsigned long *dup_configs; 140 unsigned long *dup_configs;
135 141
136 if (*num_maps == *reserved_maps) 142 if (WARN_ON(*num_maps == *reserved_maps))
137 return -ENOSPC; 143 return -ENOSPC;
138 144
139 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 145 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
140 GFP_KERNEL); 146 GFP_KERNEL);
141 if (!dup_configs) 147 if (!dup_configs) {
148 dev_err(dev, "kmemdup(configs) failed\n");
142 return -ENOMEM; 149 return -ENOMEM;
150 }
143 151
144 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 152 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
145 (*map)[*num_maps].data.configs.group_or_pin = group; 153 (*map)[*num_maps].data.configs.group_or_pin = group;
@@ -150,8 +158,8 @@ static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
150 return 0; 158 return 0;
151} 159}
152 160
153static int add_config(unsigned long **configs, unsigned *num_configs, 161static int add_config(struct device *dev, unsigned long **configs,
154 unsigned long config) 162 unsigned *num_configs, unsigned long config)
155{ 163{
156 unsigned old_num = *num_configs; 164 unsigned old_num = *num_configs;
157 unsigned new_num = old_num + 1; 165 unsigned new_num = old_num + 1;
@@ -159,8 +167,10 @@ static int add_config(unsigned long **configs, unsigned *num_configs,
159 167
160 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, 168 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
161 GFP_KERNEL); 169 GFP_KERNEL);
162 if (!new_configs) 170 if (!new_configs) {
171 dev_err(dev, "krealloc(configs) failed\n");
163 return -ENOMEM; 172 return -ENOMEM;
173 }
164 174
165 new_configs[old_num] = config; 175 new_configs[old_num] = config;
166 176
@@ -201,7 +211,8 @@ static const struct cfg_param {
201 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 211 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
202}; 212};
203 213
204int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, 214int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
215 struct device_node *np,
205 struct pinctrl_map **map, 216 struct pinctrl_map **map,
206 unsigned *reserved_maps, 217 unsigned *reserved_maps,
207 unsigned *num_maps) 218 unsigned *num_maps)
@@ -217,16 +228,25 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
217 const char *group; 228 const char *group;
218 229
219 ret = of_property_read_string(np, "nvidia,function", &function); 230 ret = of_property_read_string(np, "nvidia,function", &function);
220 if (ret < 0) 231 if (ret < 0) {
232 /* EINVAL=missing, which is fine since it's optional */
233 if (ret != -EINVAL)
234 dev_err(dev,
235 "could not parse property nvidia,function\n");
221 function = NULL; 236 function = NULL;
237 }
222 238
223 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 239 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
224 ret = of_property_read_u32(np, cfg_params[i].property, &val); 240 ret = of_property_read_u32(np, cfg_params[i].property, &val);
225 if (!ret) { 241 if (!ret) {
226 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 242 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
227 ret = add_config(&configs, &num_configs, config); 243 ret = add_config(dev, &configs, &num_configs, config);
228 if (ret < 0) 244 if (ret < 0)
229 goto exit; 245 goto exit;
246 /* EINVAL=missing, which is fine since it's optional */
247 } else if (ret != -EINVAL) {
248 dev_err(dev, "could not parse property %s\n",
249 cfg_params[i].property);
230 } 250 }
231 } 251 }
232 252
@@ -236,11 +256,13 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
236 if (num_configs) 256 if (num_configs)
237 reserve++; 257 reserve++;
238 ret = of_property_count_strings(np, "nvidia,pins"); 258 ret = of_property_count_strings(np, "nvidia,pins");
239 if (ret < 0) 259 if (ret < 0) {
260 dev_err(dev, "could not parse property nvidia,pins\n");
240 goto exit; 261 goto exit;
262 }
241 reserve *= ret; 263 reserve *= ret;
242 264
243 ret = reserve_map(map, reserved_maps, num_maps, reserve); 265 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
244 if (ret < 0) 266 if (ret < 0)
245 goto exit; 267 goto exit;
246 268
@@ -253,8 +275,9 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
253 } 275 }
254 276
255 if (num_configs) { 277 if (num_configs) {
256 ret = add_map_configs(map, reserved_maps, num_maps, 278 ret = add_map_configs(dev, map, reserved_maps,
257 group, configs, num_configs); 279 num_maps, group, configs,
280 num_configs);
258 if (ret < 0) 281 if (ret < 0)
259 goto exit; 282 goto exit;
260 } 283 }
@@ -280,8 +303,8 @@ int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
280 *num_maps = 0; 303 *num_maps = 0;
281 304
282 for_each_child_of_node(np_config, np) { 305 for_each_child_of_node(np_config, np) {
283 ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps, 306 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
284 num_maps); 307 &reserved_maps, num_maps);
285 if (ret < 0) { 308 if (ret < 0) {
286 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); 309 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
287 return ret; 310 return ret;
@@ -295,7 +318,9 @@ static struct pinctrl_ops tegra_pinctrl_ops = {
295 .get_groups_count = tegra_pinctrl_get_groups_count, 318 .get_groups_count = tegra_pinctrl_get_groups_count,
296 .get_group_name = tegra_pinctrl_get_group_name, 319 .get_group_name = tegra_pinctrl_get_group_name,
297 .get_group_pins = tegra_pinctrl_get_group_pins, 320 .get_group_pins = tegra_pinctrl_get_group_pins,
321#ifdef CONFIG_DEBUG_FS
298 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 322 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
323#endif
299 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 324 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
300 .dt_free_map = tegra_pinctrl_dt_free_map, 325 .dt_free_map = tegra_pinctrl_dt_free_map,
301}; 326};
@@ -338,14 +363,14 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
338 363
339 g = &pmx->soc->groups[group]; 364 g = &pmx->soc->groups[group];
340 365
341 if (g->mux_reg < 0) 366 if (WARN_ON(g->mux_reg < 0))
342 return -EINVAL; 367 return -EINVAL;
343 368
344 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 369 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
345 if (g->funcs[i] == function) 370 if (g->funcs[i] == function)
346 break; 371 break;
347 } 372 }
348 if (i == ARRAY_SIZE(g->funcs)) 373 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
349 return -EINVAL; 374 return -EINVAL;
350 375
351 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 376 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -365,7 +390,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
365 390
366 g = &pmx->soc->groups[group]; 391 g = &pmx->soc->groups[group];
367 392
368 if (g->mux_reg < 0) 393 if (WARN_ON(g->mux_reg < 0))
369 return; 394 return;
370 395
371 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 396 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -385,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = {
385static int tegra_pinconf_reg(struct tegra_pmx *pmx, 410static int tegra_pinconf_reg(struct tegra_pmx *pmx,
386 const struct tegra_pingroup *g, 411 const struct tegra_pingroup *g,
387 enum tegra_pinconf_param param, 412 enum tegra_pinconf_param param,
413 bool report_err,
388 s8 *bank, s16 *reg, s8 *bit, s8 *width) 414 s8 *bank, s16 *reg, s8 *bit, s8 *width)
389{ 415{
390 switch (param) { 416 switch (param) {
@@ -472,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
472 } 498 }
473 499
474 if (*reg < 0) { 500 if (*reg < 0) {
475 dev_err(pmx->dev, 501 if (report_err)
476 "Config param %04x not supported on group %s\n", 502 dev_err(pmx->dev,
477 param, g->name); 503 "Config param %04x not supported on group %s\n",
504 param, g->name);
478 return -ENOTSUPP; 505 return -ENOTSUPP;
479 } 506 }
480 507
@@ -484,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
484static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 511static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
485 unsigned pin, unsigned long *config) 512 unsigned pin, unsigned long *config)
486{ 513{
514 dev_err(pctldev->dev, "pin_config_get op not supported\n");
487 return -ENOTSUPP; 515 return -ENOTSUPP;
488} 516}
489 517
490static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 518static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
491 unsigned pin, unsigned long config) 519 unsigned pin, unsigned long config)
492{ 520{
521 dev_err(pctldev->dev, "pin_config_set op not supported\n");
493 return -ENOTSUPP; 522 return -ENOTSUPP;
494} 523}
495 524
@@ -507,7 +536,8 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
507 536
508 g = &pmx->soc->groups[group]; 537 g = &pmx->soc->groups[group];
509 538
510 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 539 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
540 &width);
511 if (ret < 0) 541 if (ret < 0)
512 return ret; 542 return ret;
513 543
@@ -534,7 +564,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
534 564
535 g = &pmx->soc->groups[group]; 565 g = &pmx->soc->groups[group];
536 566
537 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 567 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
568 &width);
538 if (ret < 0) 569 if (ret < 0)
539 return ret; 570 return ret;
540 571
@@ -542,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
542 573
543 /* LOCK can't be cleared */ 574 /* LOCK can't be cleared */
544 if (param == TEGRA_PINCONF_PARAM_LOCK) { 575 if (param == TEGRA_PINCONF_PARAM_LOCK) {
545 if ((val & BIT(bit)) && !arg) 576 if ((val & BIT(bit)) && !arg) {
577 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
546 return -EINVAL; 578 return -EINVAL;
579 }
547 } 580 }
548 581
549 /* Special-case Boolean values; allow any non-zero as true */ 582 /* Special-case Boolean values; allow any non-zero as true */
@@ -552,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
552 585
553 /* Range-check user-supplied value */ 586 /* Range-check user-supplied value */
554 mask = (1 << width) - 1; 587 mask = (1 << width) - 1;
555 if (arg & ~mask) 588 if (arg & ~mask) {
589 dev_err(pctldev->dev,
590 "config %lx: %x too big for %d bit register\n",
591 config, arg, width);
556 return -EINVAL; 592 return -EINVAL;
593 }
557 594
558 /* Update register */ 595 /* Update register */
559 val &= ~(mask << bit); 596 val &= ~(mask << bit);
@@ -563,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
563 return 0; 600 return 0;
564} 601}
565 602
603#ifdef CONFIG_DEBUG_FS
566static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 604static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
567 struct seq_file *s, unsigned offset) 605 struct seq_file *s, unsigned offset)
568{ 606{
569} 607}
570 608
609static const char *strip_prefix(const char *s)
610{
611 const char *comma = strchr(s, ',');
612 if (!comma)
613 return s;
614
615 return comma + 1;
616}
617
571static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 618static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
572 struct seq_file *s, unsigned selector) 619 struct seq_file *s, unsigned group)
620{
621 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
622 const struct tegra_pingroup *g;
623 int i, ret;
624 s8 bank, bit, width;
625 s16 reg;
626 u32 val;
627
628 g = &pmx->soc->groups[group];
629
630 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
631 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
632 &bank, &reg, &bit, &width);
633 if (ret < 0)
634 continue;
635
636 val = pmx_readl(pmx, bank, reg);
637 val >>= bit;
638 val &= (1 << width) - 1;
639
640 seq_printf(s, "\n\t%s=%u",
641 strip_prefix(cfg_params[i].property), val);
642 }
643}
644
645static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
646 struct seq_file *s,
647 unsigned long config)
573{ 648{
649 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
650 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
651 const char *pname = "unknown";
652 int i;
653
654 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
655 if (cfg_params[i].param == param) {
656 pname = cfg_params[i].property;
657 break;
658 }
659 }
660
661 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
574} 662}
663#endif
575 664
576struct pinconf_ops tegra_pinconf_ops = { 665struct pinconf_ops tegra_pinconf_ops = {
577 .pin_config_get = tegra_pinconf_get, 666 .pin_config_get = tegra_pinconf_get,
578 .pin_config_set = tegra_pinconf_set, 667 .pin_config_set = tegra_pinconf_set,
579 .pin_config_group_get = tegra_pinconf_group_get, 668 .pin_config_group_get = tegra_pinconf_group_get,
580 .pin_config_group_set = tegra_pinconf_group_set, 669 .pin_config_group_set = tegra_pinconf_group_set,
670#ifdef CONFIG_DEBUG_FS
581 .pin_config_dbg_show = tegra_pinconf_dbg_show, 671 .pin_config_dbg_show = tegra_pinconf_dbg_show,
582 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 672 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
673 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
674#endif
583}; 675};
584 676
585static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { 677static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
@@ -589,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
589}; 681};
590 682
591static struct pinctrl_desc tegra_pinctrl_desc = { 683static struct pinctrl_desc tegra_pinctrl_desc = {
592 .name = DRIVER_NAME,
593 .pctlops = &tegra_pinctrl_ops, 684 .pctlops = &tegra_pinctrl_ops,
594 .pmxops = &tegra_pinmux_ops, 685 .pmxops = &tegra_pinmux_ops,
595 .confops = &tegra_pinconf_ops, 686 .confops = &tegra_pinconf_ops,
596 .owner = THIS_MODULE, 687 .owner = THIS_MODULE,
597}; 688};
598 689
599static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = { 690int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
600#ifdef CONFIG_PINCTRL_TEGRA20 691 const struct tegra_pinctrl_soc_data *soc_data)
601 {
602 .compatible = "nvidia,tegra20-pinmux-disabled",
603 .data = tegra20_pinctrl_init,
604 },
605#endif
606#ifdef CONFIG_PINCTRL_TEGRA30
607 {
608 .compatible = "nvidia,tegra30-pinmux-disabled",
609 .data = tegra30_pinctrl_init,
610 },
611#endif
612 {},
613};
614
615static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
616{ 692{
617 const struct of_device_id *match;
618 tegra_pinctrl_soc_initf initf = NULL;
619 struct tegra_pmx *pmx; 693 struct tegra_pmx *pmx;
620 struct resource *res; 694 struct resource *res;
621 int i; 695 int i;
622 696
623 match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
624 if (match)
625 initf = (tegra_pinctrl_soc_initf)match->data;
626#ifdef CONFIG_PINCTRL_TEGRA20
627 if (!initf)
628 initf = tegra20_pinctrl_init;
629#endif
630 if (!initf) {
631 dev_err(&pdev->dev,
632 "Could not determine SoC-specific init func\n");
633 return -EINVAL;
634 }
635
636 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 697 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
637 if (!pmx) { 698 if (!pmx) {
638 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); 699 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
639 return -ENOMEM; 700 return -ENOMEM;
640 } 701 }
641 pmx->dev = &pdev->dev; 702 pmx->dev = &pdev->dev;
642 703 pmx->soc = soc_data;
643 (*initf)(&pmx->soc);
644 704
645 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; 705 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
706 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
646 tegra_pinctrl_desc.pins = pmx->soc->pins; 707 tegra_pinctrl_desc.pins = pmx->soc->pins;
647 tegra_pinctrl_desc.npins = pmx->soc->npins; 708 tegra_pinctrl_desc.npins = pmx->soc->npins;
648 709
@@ -697,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
697 758
698 return 0; 759 return 0;
699} 760}
761EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
700 762
701static int __devexit tegra_pinctrl_remove(struct platform_device *pdev) 763int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
702{ 764{
703 struct tegra_pmx *pmx = platform_get_drvdata(pdev); 765 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
704 766
@@ -707,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
707 769
708 return 0; 770 return 0;
709} 771}
710 772EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
711static struct platform_driver tegra_pinctrl_driver = {
712 .driver = {
713 .name = DRIVER_NAME,
714 .owner = THIS_MODULE,
715 .of_match_table = tegra_pinctrl_of_match,
716 },
717 .probe = tegra_pinctrl_probe,
718 .remove = __devexit_p(tegra_pinctrl_remove),
719};
720
721static int __init tegra_pinctrl_init(void)
722{
723 return platform_driver_register(&tegra_pinctrl_driver);
724}
725arch_initcall(tegra_pinctrl_init);
726
727static void __exit tegra_pinctrl_exit(void)
728{
729 platform_driver_unregister(&tegra_pinctrl_driver);
730}
731module_exit(tegra_pinctrl_exit);
732
733MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
734MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
735MODULE_LICENSE("GPL v2");
736MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 782c795326e..705c007a38c 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
139 unsigned ngroups; 139 unsigned ngroups;
140}; 140};
141 141
142/** 142int tegra_pinctrl_probe(struct platform_device *pdev,
143 * tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC. 143 const struct tegra_pinctrl_soc_data *soc_data);
144 * @soc_data: This pointer must be updated to point at a struct containing 144int tegra_pinctrl_remove(struct platform_device *pdev);
145 * details of the SoC.
146 */
147typedef void (*tegra_pinctrl_soc_initf)(
148 const struct tegra_pinctrl_soc_data **soc_data);
149
150/**
151 * tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
152 * @soc_data: This pointer will be updated to point at a struct containing
153 * details of Tegra20's pin controller.
154 */
155void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
156/**
157 * tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
158 * @soc_data: This pointer will be updated to point at a struct containing
159 * details of Tegra30's pin controller.
160 */
161void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
162 145
163#endif 146#endif
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index f69ff96aa29..a74f9a56853 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra20 pinmux 2 * Pinctrl data for the NVIDIA Tegra20 pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
@@ -17,6 +17,8 @@
17 * more details. 17 * more details.
18 */ 18 */
19 19
20#include <linux/module.h>
21#include <linux/of.h>
20#include <linux/platform_device.h> 22#include <linux/platform_device.h>
21#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinmux.h>
@@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2854 .ngroups = ARRAY_SIZE(tegra20_groups), 2856 .ngroups = ARRAY_SIZE(tegra20_groups),
2855}; 2857};
2856 2858
2857void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) 2859static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
2858{ 2860{
2859 *soc = &tegra20_pinctrl; 2861 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2860} 2862}
2863
2864static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
2865 { .compatible = "nvidia,tegra20-pinmux", },
2866 { },
2867};
2868
2869static struct platform_driver tegra20_pinctrl_driver = {
2870 .driver = {
2871 .name = "tegra20-pinctrl",
2872 .owner = THIS_MODULE,
2873 .of_match_table = tegra20_pinctrl_of_match,
2874 },
2875 .probe = tegra20_pinctrl_probe,
2876 .remove = __devexit_p(tegra_pinctrl_remove),
2877};
2878
2879static int __init tegra20_pinctrl_init(void)
2880{
2881 return platform_driver_register(&tegra20_pinctrl_driver);
2882}
2883arch_initcall(tegra20_pinctrl_init);
2884
2885static void __exit tegra20_pinctrl_exit(void)
2886{
2887 platform_driver_unregister(&tegra20_pinctrl_driver);
2888}
2889module_exit(tegra20_pinctrl_exit);
2890
2891MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
2892MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
2893MODULE_LICENSE("GPL v2");
2894MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 4d7571d4a43..0386fdf0da1 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra30 pinmux 2 * Pinctrl data for the NVIDIA Tegra30 pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -13,6 +13,8 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <linux/module.h>
17#include <linux/of.h>
16#include <linux/platform_device.h> 18#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h> 19#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h> 20#include <linux/pinctrl/pinmux.h>
@@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
3720 .ngroups = ARRAY_SIZE(tegra30_groups), 3722 .ngroups = ARRAY_SIZE(tegra30_groups),
3721}; 3723};
3722 3724
3723void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) 3725static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev)
3724{ 3726{
3725 *soc = &tegra30_pinctrl; 3727 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
3726} 3728}
3729
3730static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = {
3731 { .compatible = "nvidia,tegra30-pinmux", },
3732 { },
3733};
3734
3735static struct platform_driver tegra30_pinctrl_driver = {
3736 .driver = {
3737 .name = "tegra30-pinctrl",
3738 .owner = THIS_MODULE,
3739 .of_match_table = tegra30_pinctrl_of_match,
3740 },
3741 .probe = tegra30_pinctrl_probe,
3742 .remove = __devexit_p(tegra_pinctrl_remove),
3743};
3744
3745static int __init tegra30_pinctrl_init(void)
3746{
3747 return platform_driver_register(&tegra30_pinctrl_driver);
3748}
3749arch_initcall(tegra30_pinctrl_init);
3750
3751static void __exit tegra30_pinctrl_exit(void)
3752{
3753 platform_driver_unregister(&tegra30_pinctrl_driver);
3754}
3755module_exit(tegra30_pinctrl_exit);
3756
3757MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
3758MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
3759MODULE_LICENSE("GPL v2");
3760MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
new file mode 100644
index 00000000000..6a2596b4f35
--- /dev/null
+++ b/drivers/pinctrl/spear/Kconfig
@@ -0,0 +1,34 @@
1#
2# ST Microelectronics SPEAr PINCTRL drivers
3#
4
5if PLAT_SPEAR
6
7config PINCTRL_SPEAR
8 bool
9 depends on OF
10 select PINMUX
11 help
12 This enables pin control drivers for SPEAr Platform
13
14config PINCTRL_SPEAR3XX
15 bool
16 depends on ARCH_SPEAR3XX
17 select PINCTRL_SPEAR
18
19config PINCTRL_SPEAR300
20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
21 depends on MACH_SPEAR300
22 select PINCTRL_SPEAR3XX
23
24config PINCTRL_SPEAR310
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26 depends on MACH_SPEAR310
27 select PINCTRL_SPEAR3XX
28
29config PINCTRL_SPEAR320
30 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX
33
34endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
new file mode 100644
index 00000000000..15dcb85da22
--- /dev/null
+++ b/drivers/pinctrl/spear/Makefile
@@ -0,0 +1,7 @@
1# SPEAr pinmux support
2
3obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
4obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
new file mode 100644
index 00000000000..5ae50aadf88
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -0,0 +1,354 @@
1/*
2 * Driver for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * Inspired from:
8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26
27#include "pinctrl-spear.h"
28
29#define DRIVER_NAME "spear-pinmux"
30
31static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
32{
33 return readl_relaxed(pmx->vbase + reg);
34}
35
36static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
37{
38 writel_relaxed(val, pmx->vbase + reg);
39}
40
41static int set_mode(struct spear_pmx *pmx, int mode)
42{
43 struct spear_pmx_mode *pmx_mode = NULL;
44 int i;
45 u32 val;
46
47 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
48 return -EINVAL;
49
50 for (i = 0; i < pmx->machdata->npmx_modes; i++) {
51 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
52 pmx_mode = pmx->machdata->pmx_modes[i];
53 break;
54 }
55 }
56
57 if (!pmx_mode)
58 return -EINVAL;
59
60 val = pmx_readl(pmx, pmx_mode->reg);
61 val &= ~pmx_mode->mask;
62 val |= pmx_mode->val;
63 pmx_writel(pmx, val, pmx_mode->reg);
64
65 pmx->machdata->mode = pmx_mode->mode;
66 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
67 pmx_mode->name ? pmx_mode->name : "no_name",
68 pmx_mode->reg);
69
70 return 0;
71}
72
73void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74{
75 struct spear_pingroup *pgroup;
76 struct spear_modemux *modemux;
77 int i, j, group;
78
79 for (group = 0; group < machdata->ngroups; group++) {
80 pgroup = machdata->groups[group];
81
82 for (i = 0; i < pgroup->nmodemuxs; i++) {
83 modemux = &pgroup->modemuxs[i];
84
85 for (j = 0; j < modemux->nmuxregs; j++)
86 if (modemux->muxregs[j].reg == 0xFFFF)
87 modemux->muxregs[j].reg = reg;
88 }
89 }
90}
91
92static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
93{
94 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
95
96 return pmx->machdata->ngroups;
97}
98
99static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
100 unsigned group)
101{
102 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
103
104 return pmx->machdata->groups[group]->name;
105}
106
107static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
108 unsigned group, const unsigned **pins, unsigned *num_pins)
109{
110 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
111
112 *pins = pmx->machdata->groups[group]->pins;
113 *num_pins = pmx->machdata->groups[group]->npins;
114
115 return 0;
116}
117
118static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
119 struct seq_file *s, unsigned offset)
120{
121 seq_printf(s, " " DRIVER_NAME);
122}
123
124int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
125 struct device_node *np_config,
126 struct pinctrl_map **map, unsigned *num_maps)
127{
128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
129 struct device_node *np;
130 struct property *prop;
131 const char *function, *group;
132 int ret, index = 0, count = 0;
133
134 /* calculate number of maps required */
135 for_each_child_of_node(np_config, np) {
136 ret = of_property_read_string(np, "st,function", &function);
137 if (ret < 0)
138 return ret;
139
140 ret = of_property_count_strings(np, "st,pins");
141 if (ret < 0)
142 return ret;
143
144 count += ret;
145 }
146
147 if (!count) {
148 dev_err(pmx->dev, "No child nodes passed via DT\n");
149 return -ENODEV;
150 }
151
152 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
153 if (!*map)
154 return -ENOMEM;
155
156 for_each_child_of_node(np_config, np) {
157 of_property_read_string(np, "st,function", &function);
158 of_property_for_each_string(np, "st,pins", prop, group) {
159 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
160 (*map)[index].data.mux.group = group;
161 (*map)[index].data.mux.function = function;
162 index++;
163 }
164 }
165
166 *num_maps = count;
167
168 return 0;
169}
170
171void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
172 struct pinctrl_map *map, unsigned num_maps)
173{
174 kfree(map);
175}
176
177static struct pinctrl_ops spear_pinctrl_ops = {
178 .get_groups_count = spear_pinctrl_get_groups_cnt,
179 .get_group_name = spear_pinctrl_get_group_name,
180 .get_group_pins = spear_pinctrl_get_group_pins,
181 .pin_dbg_show = spear_pinctrl_pin_dbg_show,
182 .dt_node_to_map = spear_pinctrl_dt_node_to_map,
183 .dt_free_map = spear_pinctrl_dt_free_map,
184};
185
186static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
187{
188 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
189
190 return pmx->machdata->nfunctions;
191}
192
193static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
194 unsigned function)
195{
196 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
197
198 return pmx->machdata->functions[function]->name;
199}
200
201static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
202 unsigned function, const char *const **groups,
203 unsigned * const ngroups)
204{
205 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
206
207 *groups = pmx->machdata->functions[function]->groups;
208 *ngroups = pmx->machdata->functions[function]->ngroups;
209
210 return 0;
211}
212
213static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
214 unsigned function, unsigned group, bool enable)
215{
216 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217 const struct spear_pingroup *pgroup;
218 const struct spear_modemux *modemux;
219 struct spear_muxreg *muxreg;
220 u32 val, temp;
221 int i, j;
222 bool found = false;
223
224 pgroup = pmx->machdata->groups[group];
225
226 for (i = 0; i < pgroup->nmodemuxs; i++) {
227 modemux = &pgroup->modemuxs[i];
228
229 /* SoC have any modes */
230 if (pmx->machdata->modes_supported) {
231 if (!(pmx->machdata->mode & modemux->modes))
232 continue;
233 }
234
235 found = true;
236 for (j = 0; j < modemux->nmuxregs; j++) {
237 muxreg = &modemux->muxregs[j];
238
239 val = pmx_readl(pmx, muxreg->reg);
240 val &= ~muxreg->mask;
241
242 if (enable)
243 temp = muxreg->val;
244 else
245 temp = ~muxreg->val;
246
247 val |= temp;
248 pmx_writel(pmx, val, muxreg->reg);
249 }
250 }
251
252 if (!found) {
253 dev_err(pmx->dev, "pinmux group: %s not supported\n",
254 pgroup->name);
255 return -ENODEV;
256 }
257
258 return 0;
259}
260
261static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
262 unsigned group)
263{
264 return spear_pinctrl_endisable(pctldev, function, group, true);
265}
266
267static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
268 unsigned function, unsigned group)
269{
270 spear_pinctrl_endisable(pctldev, function, group, false);
271}
272
273static struct pinmux_ops spear_pinmux_ops = {
274 .get_functions_count = spear_pinctrl_get_funcs_count,
275 .get_function_name = spear_pinctrl_get_func_name,
276 .get_function_groups = spear_pinctrl_get_func_groups,
277 .enable = spear_pinctrl_enable,
278 .disable = spear_pinctrl_disable,
279};
280
281static struct pinctrl_desc spear_pinctrl_desc = {
282 .name = DRIVER_NAME,
283 .pctlops = &spear_pinctrl_ops,
284 .pmxops = &spear_pinmux_ops,
285 .owner = THIS_MODULE,
286};
287
288int __devinit spear_pinctrl_probe(struct platform_device *pdev,
289 struct spear_pinctrl_machdata *machdata)
290{
291 struct device_node *np = pdev->dev.of_node;
292 struct resource *res;
293 struct spear_pmx *pmx;
294
295 if (!machdata)
296 return -ENODEV;
297
298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 if (!res)
300 return -EINVAL;
301
302 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
303 if (!pmx) {
304 dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
305 return -ENOMEM;
306 }
307
308 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
309 if (!pmx->vbase) {
310 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
311 return -ENODEV;
312 }
313
314 pmx->dev = &pdev->dev;
315 pmx->machdata = machdata;
316
317 /* configure mode, if supported by SoC */
318 if (machdata->modes_supported) {
319 int mode = 0;
320
321 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
322 dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
323 return -EINVAL;
324 }
325
326 if (set_mode(pmx, mode)) {
327 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
328 mode);
329 return -EINVAL;
330 }
331 }
332
333 platform_set_drvdata(pdev, pmx);
334
335 spear_pinctrl_desc.pins = machdata->pins;
336 spear_pinctrl_desc.npins = machdata->npins;
337
338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339 if (IS_ERR(pmx->pctl)) {
340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341 return PTR_ERR(pmx->pctl);
342 }
343
344 return 0;
345}
346
347int __devexit spear_pinctrl_remove(struct platform_device *pdev)
348{
349 struct spear_pmx *pmx = platform_get_drvdata(pdev);
350
351 pinctrl_unregister(pmx->pctl);
352
353 return 0;
354}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
new file mode 100644
index 00000000000..47a6b5b72f9
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -0,0 +1,142 @@
1/*
2 * Driver header file for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR_H__
13#define __PINMUX_SPEAR_H__
14
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/types.h>
17
18struct platform_device;
19struct device;
20
21/**
22 * struct spear_pmx_mode - SPEAr pmx mode
23 * @name: name of pmx mode
24 * @mode: mode id
25 * @reg: register for configuring this mode
26 * @mask: mask of this mode in reg
27 * @val: val to be configured at reg after doing (val & mask)
28 */
29struct spear_pmx_mode {
30 const char *const name;
31 u16 mode;
32 u16 reg;
33 u16 mask;
34 u32 val;
35};
36
37/**
38 * struct spear_muxreg - SPEAr mux reg configuration
39 * @reg: register offset
40 * @mask: mask bits
41 * @val: val to be written on mask bits
42 */
43struct spear_muxreg {
44 u16 reg;
45 u32 mask;
46 u32 val;
47};
48
49/**
50 * struct spear_modemux - SPEAr mode mux configuration
51 * @modes: mode ids supported by this group of muxregs
52 * @nmuxregs: number of muxreg configurations to be done for modes
53 * @muxregs: array of muxreg configurations to be done for modes
54 */
55struct spear_modemux {
56 u16 modes;
57 u8 nmuxregs;
58 struct spear_muxreg *muxregs;
59};
60
61/**
62 * struct spear_pingroup - SPEAr pin group configurations
63 * @name: name of pin group
64 * @pins: array containing pin numbers
65 * @npins: size of pins array
66 * @modemuxs: array of modemux configurations for this pin group
67 * @nmodemuxs: size of array modemuxs
68 *
69 * A representation of a group of pins in the SPEAr pin controller. Each group
70 * allows some parameter or parameters to be configured.
71 */
72struct spear_pingroup {
73 const char *name;
74 const unsigned *pins;
75 unsigned npins;
76 struct spear_modemux *modemuxs;
77 unsigned nmodemuxs;
78};
79
80/**
81 * struct spear_function - SPEAr pinctrl mux function
82 * @name: The name of the function, exported to pinctrl core.
83 * @groups: An array of pin groups that may select this function.
84 * @ngroups: The number of entries in @groups.
85 */
86struct spear_function {
87 const char *name;
88 const char *const *groups;
89 unsigned ngroups;
90};
91
92/**
93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94 * configuration
95 * @pins: An array describing all pins the pin controller affects.
96 * All pins which are also GPIOs must be listed first within the *array,
97 * and be numbered identically to the GPIO controller's *numbering.
98 * @npins: The numbmer of entries in @pins.
99 * @functions: An array describing all mux functions the SoC supports.
100 * @nfunctions: The numbmer of entries in @functions.
101 * @groups: An array describing all pin groups the pin SoC supports.
102 * @ngroups: The numbmer of entries in @groups.
103 *
104 * @modes_supported: Does SoC support modes
105 * @mode: mode configured from probe
106 * @pmx_modes: array of modes supported by SoC
107 * @npmx_modes: number of entries in pmx_modes.
108 */
109struct spear_pinctrl_machdata {
110 const struct pinctrl_pin_desc *pins;
111 unsigned npins;
112 struct spear_function **functions;
113 unsigned nfunctions;
114 struct spear_pingroup **groups;
115 unsigned ngroups;
116
117 bool modes_supported;
118 u16 mode;
119 struct spear_pmx_mode **pmx_modes;
120 unsigned npmx_modes;
121};
122
123/**
124 * struct spear_pmx - SPEAr pinctrl mux
125 * @dev: pointer to struct dev of platform_device registered
126 * @pctl: pointer to struct pinctrl_dev
127 * @machdata: pointer to SoC or machine specific structure
128 * @vbase: virtual base address of pinmux controller
129 */
130struct spear_pmx {
131 struct device *dev;
132 struct pinctrl_dev *pctl;
133 struct spear_pinctrl_machdata *machdata;
134 void __iomem *vbase;
135};
136
137/* exported routines */
138void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata);
141int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644
index 00000000000..9c82a35e4e7
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
1/*
2 * Driver for the ST Microelectronics SPEAr300 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear300-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x00
23#define MODE_CONFIG_REG 0x04
24
25/* modes */
26#define NAND_MODE (1 << 0)
27#define NOR_MODE (1 << 1)
28#define PHOTO_FRAME_MODE (1 << 2)
29#define LEND_IP_PHONE_MODE (1 << 3)
30#define HEND_IP_PHONE_MODE (1 << 4)
31#define LEND_WIFI_PHONE_MODE (1 << 5)
32#define HEND_WIFI_PHONE_MODE (1 << 6)
33#define ATA_PABX_WI2S_MODE (1 << 7)
34#define ATA_PABX_I2S_MODE (1 << 8)
35#define CAML_LCDW_MODE (1 << 9)
36#define CAMU_LCD_MODE (1 << 10)
37#define CAMU_WLCD_MODE (1 << 11)
38#define CAML_LCD_MODE (1 << 12)
39
40static struct spear_pmx_mode pmx_mode_nand = {
41 .name = "nand",
42 .mode = NAND_MODE,
43 .reg = MODE_CONFIG_REG,
44 .mask = 0x0000000F,
45 .val = 0x00,
46};
47
48static struct spear_pmx_mode pmx_mode_nor = {
49 .name = "nor",
50 .mode = NOR_MODE,
51 .reg = MODE_CONFIG_REG,
52 .mask = 0x0000000F,
53 .val = 0x01,
54};
55
56static struct spear_pmx_mode pmx_mode_photo_frame = {
57 .name = "photo frame mode",
58 .mode = PHOTO_FRAME_MODE,
59 .reg = MODE_CONFIG_REG,
60 .mask = 0x0000000F,
61 .val = 0x02,
62};
63
64static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65 .name = "lend ip phone mode",
66 .mode = LEND_IP_PHONE_MODE,
67 .reg = MODE_CONFIG_REG,
68 .mask = 0x0000000F,
69 .val = 0x03,
70};
71
72static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73 .name = "hend ip phone mode",
74 .mode = HEND_IP_PHONE_MODE,
75 .reg = MODE_CONFIG_REG,
76 .mask = 0x0000000F,
77 .val = 0x04,
78};
79
80static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81 .name = "lend wifi phone mode",
82 .mode = LEND_WIFI_PHONE_MODE,
83 .reg = MODE_CONFIG_REG,
84 .mask = 0x0000000F,
85 .val = 0x05,
86};
87
88static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89 .name = "hend wifi phone mode",
90 .mode = HEND_WIFI_PHONE_MODE,
91 .reg = MODE_CONFIG_REG,
92 .mask = 0x0000000F,
93 .val = 0x06,
94};
95
96static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97 .name = "ata pabx wi2s mode",
98 .mode = ATA_PABX_WI2S_MODE,
99 .reg = MODE_CONFIG_REG,
100 .mask = 0x0000000F,
101 .val = 0x07,
102};
103
104static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105 .name = "ata pabx i2s mode",
106 .mode = ATA_PABX_I2S_MODE,
107 .reg = MODE_CONFIG_REG,
108 .mask = 0x0000000F,
109 .val = 0x08,
110};
111
112static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113 .name = "caml lcdw mode",
114 .mode = CAML_LCDW_MODE,
115 .reg = MODE_CONFIG_REG,
116 .mask = 0x0000000F,
117 .val = 0x0C,
118};
119
120static struct spear_pmx_mode pmx_mode_camu_lcd = {
121 .name = "camu lcd mode",
122 .mode = CAMU_LCD_MODE,
123 .reg = MODE_CONFIG_REG,
124 .mask = 0x0000000F,
125 .val = 0x0D,
126};
127
128static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129 .name = "camu wlcd mode",
130 .mode = CAMU_WLCD_MODE,
131 .reg = MODE_CONFIG_REG,
132 .mask = 0x0000000F,
133 .val = 0xE,
134};
135
136static struct spear_pmx_mode pmx_mode_caml_lcd = {
137 .name = "caml lcd mode",
138 .mode = CAML_LCD_MODE,
139 .reg = MODE_CONFIG_REG,
140 .mask = 0x0000000F,
141 .val = 0x0F,
142};
143
144static struct spear_pmx_mode *spear300_pmx_modes[] = {
145 &pmx_mode_nand,
146 &pmx_mode_nor,
147 &pmx_mode_photo_frame,
148 &pmx_mode_lend_ip_phone,
149 &pmx_mode_hend_ip_phone,
150 &pmx_mode_lend_wifi_phone,
151 &pmx_mode_hend_wifi_phone,
152 &pmx_mode_ata_pabx_wi2s,
153 &pmx_mode_ata_pabx_i2s,
154 &pmx_mode_caml_lcdw,
155 &pmx_mode_camu_lcd,
156 &pmx_mode_camu_wlcd,
157 &pmx_mode_caml_lcd,
158};
159
160/* fsmc_2chips_pins */
161static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162static struct spear_muxreg fsmc_2chips_muxreg[] = {
163 {
164 .reg = PMX_CONFIG_REG,
165 .mask = PMX_FIRDA_MASK,
166 .val = 0,
167 },
168};
169
170static struct spear_modemux fsmc_2chips_modemux[] = {
171 {
172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174 .muxregs = fsmc_2chips_muxreg,
175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176 },
177};
178
179static struct spear_pingroup fsmc_2chips_pingroup = {
180 .name = "fsmc_2chips_grp",
181 .pins = fsmc_2chips_pins,
182 .npins = ARRAY_SIZE(fsmc_2chips_pins),
183 .modemuxs = fsmc_2chips_modemux,
184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185};
186
187/* fsmc_4chips_pins */
188static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189static struct spear_muxreg fsmc_4chips_muxreg[] = {
190 {
191 .reg = PMX_CONFIG_REG,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193 .val = 0,
194 },
195};
196
197static struct spear_modemux fsmc_4chips_modemux[] = {
198 {
199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201 .muxregs = fsmc_4chips_muxreg,
202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203 },
204};
205
206static struct spear_pingroup fsmc_4chips_pingroup = {
207 .name = "fsmc_4chips_grp",
208 .pins = fsmc_4chips_pins,
209 .npins = ARRAY_SIZE(fsmc_4chips_pins),
210 .modemuxs = fsmc_4chips_modemux,
211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212};
213
214static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215};
216static struct spear_function fsmc_function = {
217 .name = "fsmc",
218 .groups = fsmc_grps,
219 .ngroups = ARRAY_SIZE(fsmc_grps),
220};
221
222/* clcd_lcdmode_pins */
223static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225 {
226 .reg = PMX_CONFIG_REG,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228 .val = 0,
229 },
230};
231
232static struct spear_modemux clcd_lcdmode_modemux[] = {
233 {
234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235 CAMU_LCD_MODE | CAML_LCD_MODE,
236 .muxregs = clcd_lcdmode_muxreg,
237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238 },
239};
240
241static struct spear_pingroup clcd_lcdmode_pingroup = {
242 .name = "clcd_lcdmode_grp",
243 .pins = clcd_lcdmode_pins,
244 .npins = ARRAY_SIZE(clcd_lcdmode_pins),
245 .modemuxs = clcd_lcdmode_modemux,
246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247};
248
249/* clcd_pfmode_pins */
250static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251static struct spear_muxreg clcd_pfmode_muxreg[] = {
252 {
253 .reg = PMX_CONFIG_REG,
254 .mask = PMX_TIMER_2_3_MASK,
255 .val = 0,
256 },
257};
258
259static struct spear_modemux clcd_pfmode_modemux[] = {
260 {
261 .modes = PHOTO_FRAME_MODE,
262 .muxregs = clcd_pfmode_muxreg,
263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264 },
265};
266
267static struct spear_pingroup clcd_pfmode_pingroup = {
268 .name = "clcd_pfmode_grp",
269 .pins = clcd_pfmode_pins,
270 .npins = ARRAY_SIZE(clcd_pfmode_pins),
271 .modemuxs = clcd_pfmode_modemux,
272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273};
274
275static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276};
277static struct spear_function clcd_function = {
278 .name = "clcd",
279 .groups = clcd_grps,
280 .ngroups = ARRAY_SIZE(clcd_grps),
281};
282
283/* tdm_pins */
284static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285static struct spear_muxreg tdm_muxreg[] = {
286 {
287 .reg = PMX_CONFIG_REG,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289 .val = 0,
290 },
291};
292
293static struct spear_modemux tdm_modemux[] = {
294 {
295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299 | CAMU_WLCD_MODE | CAML_LCD_MODE,
300 .muxregs = tdm_muxreg,
301 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
302 },
303};
304
305static struct spear_pingroup tdm_pingroup = {
306 .name = "tdm_grp",
307 .pins = tdm_pins,
308 .npins = ARRAY_SIZE(tdm_pins),
309 .modemuxs = tdm_modemux,
310 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
311};
312
313static const char *const tdm_grps[] = { "tdm_grp" };
314static struct spear_function tdm_function = {
315 .name = "tdm",
316 .groups = tdm_grps,
317 .ngroups = ARRAY_SIZE(tdm_grps),
318};
319
320/* i2c_clk_pins */
321static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322static struct spear_muxreg i2c_clk_muxreg[] = {
323 {
324 .reg = PMX_CONFIG_REG,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326 .val = 0,
327 },
328};
329
330static struct spear_modemux i2c_clk_modemux[] = {
331 {
332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335 | CAML_LCD_MODE,
336 .muxregs = i2c_clk_muxreg,
337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338 },
339};
340
341static struct spear_pingroup i2c_clk_pingroup = {
342 .name = "i2c_clk_grp_grp",
343 .pins = i2c_clk_pins,
344 .npins = ARRAY_SIZE(i2c_clk_pins),
345 .modemuxs = i2c_clk_modemux,
346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347};
348
349static const char *const i2c_grps[] = { "i2c_clk_grp" };
350static struct spear_function i2c_function = {
351 .name = "i2c1",
352 .groups = i2c_grps,
353 .ngroups = ARRAY_SIZE(i2c_grps),
354};
355
356/* caml_pins */
357static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358static struct spear_muxreg caml_muxreg[] = {
359 {
360 .reg = PMX_CONFIG_REG,
361 .mask = PMX_MII_MASK,
362 .val = 0,
363 },
364};
365
366static struct spear_modemux caml_modemux[] = {
367 {
368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369 .muxregs = caml_muxreg,
370 .nmuxregs = ARRAY_SIZE(caml_muxreg),
371 },
372};
373
374static struct spear_pingroup caml_pingroup = {
375 .name = "caml_grp",
376 .pins = caml_pins,
377 .npins = ARRAY_SIZE(caml_pins),
378 .modemuxs = caml_modemux,
379 .nmodemuxs = ARRAY_SIZE(caml_modemux),
380};
381
382/* camu_pins */
383static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384static struct spear_muxreg camu_muxreg[] = {
385 {
386 .reg = PMX_CONFIG_REG,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388 .val = 0,
389 },
390};
391
392static struct spear_modemux camu_modemux[] = {
393 {
394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395 .muxregs = camu_muxreg,
396 .nmuxregs = ARRAY_SIZE(camu_muxreg),
397 },
398};
399
400static struct spear_pingroup camu_pingroup = {
401 .name = "camu_grp",
402 .pins = camu_pins,
403 .npins = ARRAY_SIZE(camu_pins),
404 .modemuxs = camu_modemux,
405 .nmodemuxs = ARRAY_SIZE(camu_modemux),
406};
407
408static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409static struct spear_function cam_function = {
410 .name = "cam",
411 .groups = cam_grps,
412 .ngroups = ARRAY_SIZE(cam_grps),
413};
414
415/* dac_pins */
416static const unsigned dac_pins[] = { 43, 44 };
417static struct spear_muxreg dac_muxreg[] = {
418 {
419 .reg = PMX_CONFIG_REG,
420 .mask = PMX_TIMER_0_1_MASK,
421 .val = 0,
422 },
423};
424
425static struct spear_modemux dac_modemux[] = {
426 {
427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428 | CAMU_WLCD_MODE | CAML_LCD_MODE,
429 .muxregs = dac_muxreg,
430 .nmuxregs = ARRAY_SIZE(dac_muxreg),
431 },
432};
433
434static struct spear_pingroup dac_pingroup = {
435 .name = "dac_grp",
436 .pins = dac_pins,
437 .npins = ARRAY_SIZE(dac_pins),
438 .modemuxs = dac_modemux,
439 .nmodemuxs = ARRAY_SIZE(dac_modemux),
440};
441
442static const char *const dac_grps[] = { "dac_grp" };
443static struct spear_function dac_function = {
444 .name = "dac",
445 .groups = dac_grps,
446 .ngroups = ARRAY_SIZE(dac_grps),
447};
448
449/* i2s_pins */
450static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451static struct spear_muxreg i2s_muxreg[] = {
452 {
453 .reg = PMX_CONFIG_REG,
454 .mask = PMX_UART0_MODEM_MASK,
455 .val = 0,
456 },
457};
458
459static struct spear_modemux i2s_modemux[] = {
460 {
461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464 | CAMU_WLCD_MODE | CAML_LCD_MODE,
465 .muxregs = i2s_muxreg,
466 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
467 },
468};
469
470static struct spear_pingroup i2s_pingroup = {
471 .name = "i2s_grp",
472 .pins = i2s_pins,
473 .npins = ARRAY_SIZE(i2s_pins),
474 .modemuxs = i2s_modemux,
475 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
476};
477
478static const char *const i2s_grps[] = { "i2s_grp" };
479static struct spear_function i2s_function = {
480 .name = "i2s",
481 .groups = i2s_grps,
482 .ngroups = ARRAY_SIZE(i2s_grps),
483};
484
485/* sdhci_4bit_pins */
486static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487static struct spear_muxreg sdhci_4bit_muxreg[] = {
488 {
489 .reg = PMX_CONFIG_REG,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493 .val = 0,
494 },
495};
496
497static struct spear_modemux sdhci_4bit_modemux[] = {
498 {
499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503 .muxregs = sdhci_4bit_muxreg,
504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505 },
506};
507
508static struct spear_pingroup sdhci_4bit_pingroup = {
509 .name = "sdhci_4bit_grp",
510 .pins = sdhci_4bit_pins,
511 .npins = ARRAY_SIZE(sdhci_4bit_pins),
512 .modemuxs = sdhci_4bit_modemux,
513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514};
515
516/* sdhci_8bit_pins */
517static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518 33 };
519static struct spear_muxreg sdhci_8bit_muxreg[] = {
520 {
521 .reg = PMX_CONFIG_REG,
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525 .val = 0,
526 },
527};
528
529static struct spear_modemux sdhci_8bit_modemux[] = {
530 {
531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534 CAMU_WLCD_MODE | CAML_LCD_MODE,
535 .muxregs = sdhci_8bit_muxreg,
536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537 },
538};
539
540static struct spear_pingroup sdhci_8bit_pingroup = {
541 .name = "sdhci_8bit_grp",
542 .pins = sdhci_8bit_pins,
543 .npins = ARRAY_SIZE(sdhci_8bit_pins),
544 .modemuxs = sdhci_8bit_modemux,
545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546};
547
548static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549static struct spear_function sdhci_function = {
550 .name = "sdhci",
551 .groups = sdhci_grps,
552 .ngroups = ARRAY_SIZE(sdhci_grps),
553};
554
555/* gpio1_0_to_3_pins */
556static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558 {
559 .reg = PMX_CONFIG_REG,
560 .mask = PMX_UART0_MODEM_MASK,
561 .val = 0,
562 },
563};
564
565static struct spear_modemux gpio1_0_to_3_modemux[] = {
566 {
567 .modes = PHOTO_FRAME_MODE,
568 .muxregs = gpio1_0_to_3_muxreg,
569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570 },
571};
572
573static struct spear_pingroup gpio1_0_to_3_pingroup = {
574 .name = "gpio1_0_to_3_grp",
575 .pins = gpio1_0_to_3_pins,
576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577 .modemuxs = gpio1_0_to_3_modemux,
578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579};
580
581/* gpio1_4_to_7_pins */
582static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583
584static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585 {
586 .reg = PMX_CONFIG_REG,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588 .val = 0,
589 },
590};
591
592static struct spear_modemux gpio1_4_to_7_modemux[] = {
593 {
594 .modes = PHOTO_FRAME_MODE,
595 .muxregs = gpio1_4_to_7_muxreg,
596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597 },
598};
599
600static struct spear_pingroup gpio1_4_to_7_pingroup = {
601 .name = "gpio1_4_to_7_grp",
602 .pins = gpio1_4_to_7_pins,
603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604 .modemuxs = gpio1_4_to_7_modemux,
605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606};
607
608static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609};
610static struct spear_function gpio1_function = {
611 .name = "gpio1",
612 .groups = gpio1_grps,
613 .ngroups = ARRAY_SIZE(gpio1_grps),
614};
615
616/* pingroups */
617static struct spear_pingroup *spear300_pingroups[] = {
618 SPEAR3XX_COMMON_PINGROUPS,
619 &fsmc_2chips_pingroup,
620 &fsmc_4chips_pingroup,
621 &clcd_lcdmode_pingroup,
622 &clcd_pfmode_pingroup,
623 &tdm_pingroup,
624 &i2c_clk_pingroup,
625 &caml_pingroup,
626 &camu_pingroup,
627 &dac_pingroup,
628 &i2s_pingroup,
629 &sdhci_4bit_pingroup,
630 &sdhci_8bit_pingroup,
631 &gpio1_0_to_3_pingroup,
632 &gpio1_4_to_7_pingroup,
633};
634
635/* functions */
636static struct spear_function *spear300_functions[] = {
637 SPEAR3XX_COMMON_FUNCTIONS,
638 &fsmc_function,
639 &clcd_function,
640 &tdm_function,
641 &i2c_function,
642 &cam_function,
643 &dac_function,
644 &i2s_function,
645 &sdhci_function,
646 &gpio1_function,
647};
648
649static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
650 {
651 .compatible = "st,spear300-pinmux",
652 },
653 {},
654};
655
656static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657{
658 int ret;
659
660 spear3xx_machdata.groups = spear300_pingroups;
661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 spear3xx_machdata.functions = spear300_functions;
663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664
665 spear3xx_machdata.modes_supported = true;
666 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668
669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670
671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672 if (ret)
673 return ret;
674
675 return 0;
676}
677
678static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
679{
680 return spear_pinctrl_remove(pdev);
681}
682
683static struct platform_driver spear300_pinctrl_driver = {
684 .driver = {
685 .name = DRIVER_NAME,
686 .owner = THIS_MODULE,
687 .of_match_table = spear300_pinctrl_of_match,
688 },
689 .probe = spear300_pinctrl_probe,
690 .remove = __devexit_p(spear300_pinctrl_remove),
691};
692
693static int __init spear300_pinctrl_init(void)
694{
695 return platform_driver_register(&spear300_pinctrl_driver);
696}
697arch_initcall(spear300_pinctrl_init);
698
699static void __exit spear300_pinctrl_exit(void)
700{
701 platform_driver_unregister(&spear300_pinctrl_driver);
702}
703module_exit(spear300_pinctrl_exit);
704
705MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
706MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707MODULE_LICENSE("GPL v2");
708MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644
index 00000000000..1a970760512
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
1/*
2 * Driver for the ST Microelectronics SPEAr310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear310-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x08
23
24/* emi_cs_0_to_5_pins */
25static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27 {
28 .reg = PMX_CONFIG_REG,
29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30 .val = 0,
31 },
32};
33
34static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35 {
36 .muxregs = emi_cs_0_to_5_muxreg,
37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38 },
39};
40
41static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42 .name = "emi_cs_0_to_5_grp",
43 .pins = emi_cs_0_to_5_pins,
44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45 .modemuxs = emi_cs_0_to_5_modemux,
46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47};
48
49static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50static struct spear_function emi_cs_0_to_5_function = {
51 .name = "emi",
52 .groups = emi_cs_0_to_5_grps,
53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54};
55
56/* uart1_pins */
57static const unsigned uart1_pins[] = { 0, 1 };
58static struct spear_muxreg uart1_muxreg[] = {
59 {
60 .reg = PMX_CONFIG_REG,
61 .mask = PMX_FIRDA_MASK,
62 .val = 0,
63 },
64};
65
66static struct spear_modemux uart1_modemux[] = {
67 {
68 .muxregs = uart1_muxreg,
69 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
70 },
71};
72
73static struct spear_pingroup uart1_pingroup = {
74 .name = "uart1_grp",
75 .pins = uart1_pins,
76 .npins = ARRAY_SIZE(uart1_pins),
77 .modemuxs = uart1_modemux,
78 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
79};
80
81static const char *const uart1_grps[] = { "uart1_grp" };
82static struct spear_function uart1_function = {
83 .name = "uart1",
84 .groups = uart1_grps,
85 .ngroups = ARRAY_SIZE(uart1_grps),
86};
87
88/* uart2_pins */
89static const unsigned uart2_pins[] = { 43, 44 };
90static struct spear_muxreg uart2_muxreg[] = {
91 {
92 .reg = PMX_CONFIG_REG,
93 .mask = PMX_TIMER_0_1_MASK,
94 .val = 0,
95 },
96};
97
98static struct spear_modemux uart2_modemux[] = {
99 {
100 .muxregs = uart2_muxreg,
101 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
102 },
103};
104
105static struct spear_pingroup uart2_pingroup = {
106 .name = "uart2_grp",
107 .pins = uart2_pins,
108 .npins = ARRAY_SIZE(uart2_pins),
109 .modemuxs = uart2_modemux,
110 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
111};
112
113static const char *const uart2_grps[] = { "uart2_grp" };
114static struct spear_function uart2_function = {
115 .name = "uart2",
116 .groups = uart2_grps,
117 .ngroups = ARRAY_SIZE(uart2_grps),
118};
119
120/* uart3_pins */
121static const unsigned uart3_pins[] = { 37, 38 };
122static struct spear_muxreg uart3_muxreg[] = {
123 {
124 .reg = PMX_CONFIG_REG,
125 .mask = PMX_UART0_MODEM_MASK,
126 .val = 0,
127 },
128};
129
130static struct spear_modemux uart3_modemux[] = {
131 {
132 .muxregs = uart3_muxreg,
133 .nmuxregs = ARRAY_SIZE(uart3_muxreg),
134 },
135};
136
137static struct spear_pingroup uart3_pingroup = {
138 .name = "uart3_grp",
139 .pins = uart3_pins,
140 .npins = ARRAY_SIZE(uart3_pins),
141 .modemuxs = uart3_modemux,
142 .nmodemuxs = ARRAY_SIZE(uart3_modemux),
143};
144
145static const char *const uart3_grps[] = { "uart3_grp" };
146static struct spear_function uart3_function = {
147 .name = "uart3",
148 .groups = uart3_grps,
149 .ngroups = ARRAY_SIZE(uart3_grps),
150};
151
152/* uart4_pins */
153static const unsigned uart4_pins[] = { 39, 40 };
154static struct spear_muxreg uart4_muxreg[] = {
155 {
156 .reg = PMX_CONFIG_REG,
157 .mask = PMX_UART0_MODEM_MASK,
158 .val = 0,
159 },
160};
161
162static struct spear_modemux uart4_modemux[] = {
163 {
164 .muxregs = uart4_muxreg,
165 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
166 },
167};
168
169static struct spear_pingroup uart4_pingroup = {
170 .name = "uart4_grp",
171 .pins = uart4_pins,
172 .npins = ARRAY_SIZE(uart4_pins),
173 .modemuxs = uart4_modemux,
174 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
175};
176
177static const char *const uart4_grps[] = { "uart4_grp" };
178static struct spear_function uart4_function = {
179 .name = "uart4",
180 .groups = uart4_grps,
181 .ngroups = ARRAY_SIZE(uart4_grps),
182};
183
184/* uart5_pins */
185static const unsigned uart5_pins[] = { 41, 42 };
186static struct spear_muxreg uart5_muxreg[] = {
187 {
188 .reg = PMX_CONFIG_REG,
189 .mask = PMX_UART0_MODEM_MASK,
190 .val = 0,
191 },
192};
193
194static struct spear_modemux uart5_modemux[] = {
195 {
196 .muxregs = uart5_muxreg,
197 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
198 },
199};
200
201static struct spear_pingroup uart5_pingroup = {
202 .name = "uart5_grp",
203 .pins = uart5_pins,
204 .npins = ARRAY_SIZE(uart5_pins),
205 .modemuxs = uart5_modemux,
206 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
207};
208
209static const char *const uart5_grps[] = { "uart5_grp" };
210static struct spear_function uart5_function = {
211 .name = "uart5",
212 .groups = uart5_grps,
213 .ngroups = ARRAY_SIZE(uart5_grps),
214};
215
216/* fsmc_pins */
217static const unsigned fsmc_pins[] = { 34, 35, 36 };
218static struct spear_muxreg fsmc_muxreg[] = {
219 {
220 .reg = PMX_CONFIG_REG,
221 .mask = PMX_SSP_CS_MASK,
222 .val = 0,
223 },
224};
225
226static struct spear_modemux fsmc_modemux[] = {
227 {
228 .muxregs = fsmc_muxreg,
229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230 },
231};
232
233static struct spear_pingroup fsmc_pingroup = {
234 .name = "fsmc_grp",
235 .pins = fsmc_pins,
236 .npins = ARRAY_SIZE(fsmc_pins),
237 .modemuxs = fsmc_modemux,
238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239};
240
241static const char *const fsmc_grps[] = { "fsmc_grp" };
242static struct spear_function fsmc_function = {
243 .name = "fsmc",
244 .groups = fsmc_grps,
245 .ngroups = ARRAY_SIZE(fsmc_grps),
246};
247
248/* rs485_0_pins */
249static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250static struct spear_muxreg rs485_0_muxreg[] = {
251 {
252 .reg = PMX_CONFIG_REG,
253 .mask = PMX_MII_MASK,
254 .val = 0,
255 },
256};
257
258static struct spear_modemux rs485_0_modemux[] = {
259 {
260 .muxregs = rs485_0_muxreg,
261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262 },
263};
264
265static struct spear_pingroup rs485_0_pingroup = {
266 .name = "rs485_0_grp",
267 .pins = rs485_0_pins,
268 .npins = ARRAY_SIZE(rs485_0_pins),
269 .modemuxs = rs485_0_modemux,
270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271};
272
273static const char *const rs485_0_grps[] = { "rs485_0" };
274static struct spear_function rs485_0_function = {
275 .name = "rs485_0",
276 .groups = rs485_0_grps,
277 .ngroups = ARRAY_SIZE(rs485_0_grps),
278};
279
280/* rs485_1_pins */
281static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282static struct spear_muxreg rs485_1_muxreg[] = {
283 {
284 .reg = PMX_CONFIG_REG,
285 .mask = PMX_MII_MASK,
286 .val = 0,
287 },
288};
289
290static struct spear_modemux rs485_1_modemux[] = {
291 {
292 .muxregs = rs485_1_muxreg,
293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294 },
295};
296
297static struct spear_pingroup rs485_1_pingroup = {
298 .name = "rs485_1_grp",
299 .pins = rs485_1_pins,
300 .npins = ARRAY_SIZE(rs485_1_pins),
301 .modemuxs = rs485_1_modemux,
302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303};
304
305static const char *const rs485_1_grps[] = { "rs485_1" };
306static struct spear_function rs485_1_function = {
307 .name = "rs485_1",
308 .groups = rs485_1_grps,
309 .ngroups = ARRAY_SIZE(rs485_1_grps),
310};
311
312/* tdm_pins */
313static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314static struct spear_muxreg tdm_muxreg[] = {
315 {
316 .reg = PMX_CONFIG_REG,
317 .mask = PMX_MII_MASK,
318 .val = 0,
319 },
320};
321
322static struct spear_modemux tdm_modemux[] = {
323 {
324 .muxregs = tdm_muxreg,
325 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
326 },
327};
328
329static struct spear_pingroup tdm_pingroup = {
330 .name = "tdm_grp",
331 .pins = tdm_pins,
332 .npins = ARRAY_SIZE(tdm_pins),
333 .modemuxs = tdm_modemux,
334 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
335};
336
337static const char *const tdm_grps[] = { "tdm_grp" };
338static struct spear_function tdm_function = {
339 .name = "tdm",
340 .groups = tdm_grps,
341 .ngroups = ARRAY_SIZE(tdm_grps),
342};
343
344/* pingroups */
345static struct spear_pingroup *spear310_pingroups[] = {
346 SPEAR3XX_COMMON_PINGROUPS,
347 &emi_cs_0_to_5_pingroup,
348 &uart1_pingroup,
349 &uart2_pingroup,
350 &uart3_pingroup,
351 &uart4_pingroup,
352 &uart5_pingroup,
353 &fsmc_pingroup,
354 &rs485_0_pingroup,
355 &rs485_1_pingroup,
356 &tdm_pingroup,
357};
358
359/* functions */
360static struct spear_function *spear310_functions[] = {
361 SPEAR3XX_COMMON_FUNCTIONS,
362 &emi_cs_0_to_5_function,
363 &uart1_function,
364 &uart2_function,
365 &uart3_function,
366 &uart4_function,
367 &uart5_function,
368 &fsmc_function,
369 &rs485_0_function,
370 &rs485_1_function,
371 &tdm_function,
372};
373
374static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
375 {
376 .compatible = "st,spear310-pinmux",
377 },
378 {},
379};
380
381static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382{
383 int ret;
384
385 spear3xx_machdata.groups = spear310_pingroups;
386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387 spear3xx_machdata.functions = spear310_functions;
388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389
390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391
392 spear3xx_machdata.modes_supported = false;
393
394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395 if (ret)
396 return ret;
397
398 return 0;
399}
400
401static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
402{
403 return spear_pinctrl_remove(pdev);
404}
405
406static struct platform_driver spear310_pinctrl_driver = {
407 .driver = {
408 .name = DRIVER_NAME,
409 .owner = THIS_MODULE,
410 .of_match_table = spear310_pinctrl_of_match,
411 },
412 .probe = spear310_pinctrl_probe,
413 .remove = __devexit_p(spear310_pinctrl_remove),
414};
415
416static int __init spear310_pinctrl_init(void)
417{
418 return platform_driver_register(&spear310_pinctrl_driver);
419}
420arch_initcall(spear310_pinctrl_init);
421
422static void __exit spear310_pinctrl_exit(void)
423{
424 platform_driver_unregister(&spear310_pinctrl_driver);
425}
426module_exit(spear310_pinctrl_exit);
427
428MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
429MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430MODULE_LICENSE("GPL v2");
431MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644
index 00000000000..de726e6c283
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
1/*
2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear320-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x0C
23#define MODE_CONFIG_REG 0x10
24#define MODE_EXT_CONFIG_REG 0x18
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define EXTENDED_MODE (1 << 4)
32
33static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34 .name = "Automation Networking SMII mode",
35 .mode = AUTO_NET_SMII_MODE,
36 .reg = MODE_CONFIG_REG,
37 .mask = 0x00000007,
38 .val = 0x0,
39};
40
41static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42 .name = "Automation Networking MII mode",
43 .mode = AUTO_NET_MII_MODE,
44 .reg = MODE_CONFIG_REG,
45 .mask = 0x00000007,
46 .val = 0x1,
47};
48
49static struct spear_pmx_mode pmx_mode_auto_exp = {
50 .name = "Automation Expanded mode",
51 .mode = AUTO_EXP_MODE,
52 .reg = MODE_CONFIG_REG,
53 .mask = 0x00000007,
54 .val = 0x2,
55};
56
57static struct spear_pmx_mode pmx_mode_small_printers = {
58 .name = "Small Printers mode",
59 .mode = SMALL_PRINTERS_MODE,
60 .reg = MODE_CONFIG_REG,
61 .mask = 0x00000007,
62 .val = 0x3,
63};
64
65static struct spear_pmx_mode pmx_mode_extended = {
66 .name = "extended mode",
67 .mode = EXTENDED_MODE,
68 .reg = MODE_EXT_CONFIG_REG,
69 .mask = 0x00000001,
70 .val = 0x1,
71};
72
73static struct spear_pmx_mode *spear320_pmx_modes[] = {
74 &pmx_mode_auto_net_smii,
75 &pmx_mode_auto_net_mii,
76 &pmx_mode_auto_exp,
77 &pmx_mode_small_printers,
78 &pmx_mode_extended,
79};
80
81/* Extended mode registers and their offsets */
82#define EXT_CTRL_REG 0x0018
83 #define MII_MDIO_MASK (1 << 4)
84 #define MII_MDIO_10_11_VAL 0
85 #define MII_MDIO_81_VAL (1 << 4)
86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87 #define MAC_MODE_MII 0
88 #define MAC_MODE_RMII 1
89 #define MAC_MODE_SMII 2
90 #define MAC_MODE_SS_SMII 3
91 #define MAC_MODE_MASK 0x3
92 #define MAC1_MODE_SHIFT 16
93 #define MAC2_MODE_SHIFT 18
94
95#define IP_SEL_PAD_0_9_REG 0x00A4
96 #define PMX_PL_0_1_MASK (0x3F << 0)
97 #define PMX_UART2_PL_0_1_VAL 0x0
98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99
100 #define PMX_PL_2_3_MASK (0x3F << 6)
101 #define PMX_I2C2_PL_2_3_VAL 0x0
102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104
105 #define PMX_PL_4_5_MASK (0x3F << 12)
106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108 #define PMX_PL_5_MASK (0x7 << 15)
109 #define PMX_TOUCH_Y_PL_5_VAL 0x0
110
111 #define PMX_PL_6_7_MASK (0x3F << 18)
112 #define PMX_PL_6_MASK (0x7 << 18)
113 #define PMX_PL_7_MASK (0x7 << 21)
114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118
119 #define PMX_PL_8_9_MASK (0x3F << 24)
120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123
124#define IP_SEL_PAD_10_19_REG 0x00A8
125 #define PMX_PL_10_11_MASK (0x3F << 0)
126 #define PMX_SMII_PL_10_11_VAL 0
127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128
129 #define PMX_PL_12_MASK (0x7 << 6)
130 #define PMX_PWM3_PL_12_VAL 0
131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132
133 #define PMX_PL_13_14_MASK (0x3F << 9)
134 #define PMX_PL_13_MASK (0x7 << 9)
135 #define PMX_PL_14_MASK (0x7 << 12)
136 #define PMX_SSP2_PL_13_14_15_16_VAL 0
137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
141
142 #define PMX_PL_15_MASK (0x7 << 15)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
144 #define PMX_PL_15_16_MASK (0x3F << 15)
145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147
148 #define PMX_PL_17_18_MASK (0x3F << 21)
149 #define PMX_SSP1_PL_17_18_19_20_VAL 0
150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151
152 #define PMX_PL_19_MASK (0x7 << 27)
153 #define PMX_I2C2_PL_19_VAL (0x1 << 27)
154 #define PMX_RMII_PL_19_VAL (0x4 << 27)
155
156#define IP_SEL_PAD_20_29_REG 0x00AC
157 #define PMX_PL_20_MASK (0x7 << 0)
158 #define PMX_I2C2_PL_20_VAL (0x1 << 0)
159 #define PMX_RMII_PL_20_VAL (0x4 << 0)
160
161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162 #define PMX_SMII_PL_21_TO_27_VAL 0
163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164
165 #define PMX_PL_28_29_MASK (0x3F << 24)
166 #define PMX_PL_28_MASK (0x7 << 24)
167 #define PMX_PL_29_MASK (0x7 << 27)
168 #define PMX_UART1_PL_28_29_VAL 0
169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171
172#define IP_SEL_PAD_30_39_REG 0x00B0
173 #define PMX_PL_30_31_MASK (0x3F << 0)
174 #define PMX_CAN1_PL_30_31_VAL (0)
175 #define PMX_PL_30_MASK (0x7 << 0)
176 #define PMX_PL_31_MASK (0x7 << 3)
177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180
181 #define PMX_PL_32_33_MASK (0x3F << 6)
182 #define PMX_CAN0_PL_32_33_VAL 0
183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185
186 #define PMX_PL_34_MASK (0x7 << 12)
187 #define PMX_PWM2_PL_34_VAL 0
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189 #define PMX_SSP2_PL_34_VAL (0x4 << 12)
190
191 #define PMX_PL_35_MASK (0x7 << 15)
192 #define PMX_I2S_REF_CLK_PL_35_VAL 0
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194 #define PMX_SSP2_PL_35_VAL (0x4 << 15)
195
196 #define PMX_PL_36_MASK (0x7 << 18)
197 #define PMX_TOUCH_X_PL_36_VAL 0
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199 #define PMX_SSP1_PL_36_VAL (0x4 << 18)
200
201 #define PMX_PL_37_38_MASK (0x3F << 21)
202 #define PMX_PWM0_1_PL_37_38_VAL 0
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205
206 #define PMX_PL_39_MASK (0x7 << 27)
207 #define PMX_I2S_PL_39_VAL 0
208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
209 #define PMX_SSP1_PL_39_VAL (0x4 << 27)
210
211#define IP_SEL_PAD_40_49_REG 0x00B4
212 #define PMX_PL_40_MASK (0x7 << 0)
213 #define PMX_I2S_PL_40_VAL 0
214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
215 #define PMX_PWM3_PL_40_VAL (0x4 << 0)
216
217 #define PMX_PL_41_42_MASK (0x3F << 3)
218 #define PMX_PL_41_MASK (0x7 << 3)
219 #define PMX_PL_42_MASK (0x7 << 6)
220 #define PMX_I2S_PL_41_42_VAL 0
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222 #define PMX_PWM2_PL_41_VAL (0x4 << 3)
223 #define PMX_PWM1_PL_42_VAL (0x4 << 6)
224
225 #define PMX_PL_43_MASK (0x7 << 9)
226 #define PMX_SDHCI_PL_43_VAL 0
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228 #define PMX_PWM0_PL_43_VAL (0x4 << 9)
229
230 #define PMX_PL_44_45_MASK (0x3F << 12)
231 #define PMX_SDHCI_PL_44_45_VAL 0
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234
235 #define PMX_PL_46_47_MASK (0x3F << 18)
236 #define PMX_SDHCI_PL_46_47_VAL 0
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239
240 #define PMX_PL_48_49_MASK (0x3F << 24)
241 #define PMX_SDHCI_PL_48_49_VAL 0
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244
245#define IP_SEL_PAD_50_59_REG 0x00B8
246 #define PMX_PL_50_51_MASK (0x3F << 0)
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249 #define PMX_PL_50_MASK (0x7 << 0)
250 #define PMX_PL_51_MASK (0x7 << 3)
251 #define PMX_SDHCI_PL_50_VAL 0
252 #define PMX_SDHCI_CD_PL_51_VAL 0
253
254 #define PMX_PL_52_53_MASK (0x3F << 6)
255 #define PMX_FSMC_PL_52_53_VAL 0
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258
259 #define PMX_PL_54_55_56_MASK (0x1FF << 12)
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261
262 #define PMX_PL_57_MASK (0x7 << 21)
263 #define PMX_FSMC_PL_57_VAL 0
264 #define PMX_PWM3_PL_57_VAL (0x4 << 21)
265
266 #define PMX_PL_58_59_MASK (0x3F << 24)
267 #define PMX_PL_58_MASK (0x7 << 24)
268 #define PMX_PL_59_MASK (0x7 << 27)
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270 #define PMX_PWM2_PL_58_VAL (0x4 << 24)
271 #define PMX_PWM1_PL_59_VAL (0x4 << 27)
272
273#define IP_SEL_PAD_60_69_REG 0x00BC
274 #define PMX_PL_60_MASK (0x7 << 0)
275 #define PMX_FSMC_PL_60_VAL 0
276 #define PMX_PWM0_PL_60_VAL (0x4 << 0)
277
278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281
282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285
286 #define PMX_PL_69_MASK (0x7 << 27)
287 #define PMX_CLCD_PL_69_VAL (0)
288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
289 #define PMX_SPP_PL_69_VAL (0x3 << 27)
290 #define PMX_UART5_PL_69_VAL (0x4 << 27)
291
292#define IP_SEL_PAD_70_79_REG 0x00C0
293 #define PMX_PL_70_MASK (0x7 << 0)
294 #define PMX_CLCD_PL_70_VAL (0)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296 #define PMX_SPP_PL_70_VAL (0x3 << 0)
297 #define PMX_UART5_PL_70_VAL (0x4 << 0)
298
299 #define PMX_PL_71_72_MASK (0x3F << 3)
300 #define PMX_CLCD_PL_71_72_VAL (0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304
305 #define PMX_PL_73_MASK (0x7 << 9)
306 #define PMX_CLCD_PL_73_VAL (0)
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308 #define PMX_SPP_PL_73_VAL (0x3 << 9)
309 #define PMX_UART3_PL_73_VAL (0x4 << 9)
310
311 #define PMX_PL_74_MASK (0x7 << 12)
312 #define PMX_CLCD_PL_74_VAL (0)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
314 #define PMX_SPP_PL_74_VAL (0x3 << 12)
315 #define PMX_UART3_PL_74_VAL (0x4 << 12)
316
317 #define PMX_PL_75_76_MASK (0x3F << 15)
318 #define PMX_CLCD_PL_75_76_VAL (0)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322
323 #define PMX_PL_77_78_79_MASK (0x1FF << 21)
324 #define PMX_CLCD_PL_77_78_79_VAL (0)
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328
329#define IP_SEL_PAD_80_89_REG 0x00C4
330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331 #define PMX_CLCD_PL_80_TO_85_VAL 0
332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336
337 #define PMX_PL_86_87_MASK (0x3F << 18)
338 #define PMX_PL_86_MASK (0x7 << 18)
339 #define PMX_PL_87_MASK (0x7 << 21)
340 #define PMX_CLCD_PL_86_87_VAL 0
341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343 #define PMX_PWM3_PL_86_VAL (0x4 << 18)
344 #define PMX_PWM2_PL_87_VAL (0x4 << 21)
345
346 #define PMX_PL_88_89_MASK (0x3F << 24)
347 #define PMX_CLCD_PL_88_89_VAL 0
348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352
353#define IP_SEL_PAD_90_99_REG 0x00C8
354 #define PMX_PL_90_91_MASK (0x3F << 0)
355 #define PMX_CLCD_PL_90_91_VAL 0
356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360
361 #define PMX_PL_92_93_MASK (0x3F << 6)
362 #define PMX_CLCD_PL_92_93_VAL 0
363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367
368 #define PMX_PL_94_95_MASK (0x3F << 12)
369 #define PMX_CLCD_PL_94_95_VAL 0
370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374
375 #define PMX_PL_96_97_MASK (0x3F << 18)
376 #define PMX_CLCD_PL_96_97_VAL 0
377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381
382 #define PMX_PL_98_MASK (0x7 << 24)
383 #define PMX_CLCD_PL_98_VAL 0
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
385 #define PMX_UART3_PL_98_VAL (0x4 << 24)
386
387 #define PMX_PL_99_MASK (0x7 << 27)
388 #define PMX_SDHCI_PL_99_VAL 0
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
390 #define PMX_UART3_PL_99_VAL (0x4 << 27)
391
392#define IP_SEL_MIX_PAD_REG 0x00CC
393 #define PMX_PL_100_101_MASK (0x3F << 0)
394 #define PMX_SDHCI_PL_100_101_VAL 0
395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396
397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398 #define PMX_SSP1_PORT_94_TO_97_VAL 0
399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403
404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405 #define PMX_SSP2_PORT_90_TO_93_VAL 0
406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410
411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416
417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418 #define PMX_UART3_PORT_94_VAL 0
419 #define PMX_UART3_PORT_73_VAL (0x1 << 16)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
421 #define PMX_UART3_PORT_41_VAL (0x3 << 16)
422 #define PMX_UART3_PORT_15_VAL (0x4 << 16)
423 #define PMX_UART3_PORT_8_VAL (0x5 << 16)
424 #define PMX_UART3_PORT_99_VAL (0x6 << 16)
425
426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427 #define PMX_UART4_PORT_92_VAL 0
428 #define PMX_UART4_PORT_71_VAL (0x1 << 19)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
430 #define PMX_UART4_PORT_13_VAL (0x3 << 19)
431 #define PMX_UART4_PORT_6_VAL (0x4 << 19)
432 #define PMX_UART4_PORT_101_VAL (0x5 << 19)
433
434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435 #define PMX_UART5_PORT_90_VAL 0
436 #define PMX_UART5_PORT_69_VAL (0x1 << 22)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
438 #define PMX_UART5_PORT_4_VAL (0x3 << 22)
439
440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441 #define PMX_UART6_PORT_88_VAL 0
442 #define PMX_UART6_PORT_2_VAL (0x1 << 24)
443
444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445 #define PMX_I2C1_PORT_8_9_VAL 0
446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447
448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449 #define PMX_I2C2_PORT_96_97_VAL 0
450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454
455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456 #define PMX_SDHCI_CD_PORT_12_VAL 0
457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458
459/* Pad multiplexing for CLCD device */
460static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462 97 };
463static struct spear_muxreg clcd_muxreg[] = {
464 {
465 .reg = IP_SEL_PAD_60_69_REG,
466 .mask = PMX_PL_69_MASK,
467 .val = PMX_CLCD_PL_69_VAL,
468 }, {
469 .reg = IP_SEL_PAD_70_79_REG,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472 PMX_PL_77_78_79_MASK,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476 }, {
477 .reg = IP_SEL_PAD_80_89_REG,
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479 PMX_PL_88_89_MASK,
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481 PMX_CLCD_PL_88_89_VAL,
482 }, {
483 .reg = IP_SEL_PAD_90_99_REG,
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488 PMX_CLCD_PL_98_VAL,
489 },
490};
491
492static struct spear_modemux clcd_modemux[] = {
493 {
494 .modes = EXTENDED_MODE,
495 .muxregs = clcd_muxreg,
496 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
497 },
498};
499
500static struct spear_pingroup clcd_pingroup = {
501 .name = "clcd_grp",
502 .pins = clcd_pins,
503 .npins = ARRAY_SIZE(clcd_pins),
504 .modemuxs = clcd_modemux,
505 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
506};
507
508static const char *const clcd_grps[] = { "clcd_grp" };
509static struct spear_function clcd_function = {
510 .name = "clcd",
511 .groups = clcd_grps,
512 .ngroups = ARRAY_SIZE(clcd_grps),
513};
514
515/* Pad multiplexing for EMI (Parallel NOR flash) device */
516static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519 93, 94, 95, 96, 97 };
520static struct spear_muxreg emi_muxreg[] = {
521 {
522 .reg = PMX_CONFIG_REG,
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524 .val = 0,
525 },
526};
527
528static struct spear_muxreg emi_ext_muxreg[] = {
529 {
530 .reg = IP_SEL_PAD_40_49_REG,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533 }, {
534 .reg = IP_SEL_PAD_50_59_REG,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538 PMX_FSMC_EMI_PL_54_55_56_VAL |
539 PMX_FSMC_EMI_PL_58_59_VAL,
540 }, {
541 .reg = IP_SEL_PAD_60_69_REG,
542 .mask = PMX_PL_69_MASK,
543 .val = PMX_EMI_PL_69_VAL,
544 }, {
545 .reg = IP_SEL_PAD_70_79_REG,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548 PMX_PL_77_78_79_MASK,
549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552 }, {
553 .reg = IP_SEL_PAD_80_89_REG,
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555 PMX_PL_88_89_MASK,
556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557 PMX_EMI_PL_88_89_VAL,
558 }, {
559 .reg = IP_SEL_PAD_90_99_REG,
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564 }, {
565 .reg = EXT_CTRL_REG,
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
568 },
569};
570
571static struct spear_modemux emi_modemux[] = {
572 {
573 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
574 .muxregs = emi_muxreg,
575 .nmuxregs = ARRAY_SIZE(emi_muxreg),
576 }, {
577 .modes = EXTENDED_MODE,
578 .muxregs = emi_ext_muxreg,
579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580 },
581};
582
583static struct spear_pingroup emi_pingroup = {
584 .name = "emi_grp",
585 .pins = emi_pins,
586 .npins = ARRAY_SIZE(emi_pins),
587 .modemuxs = emi_modemux,
588 .nmodemuxs = ARRAY_SIZE(emi_modemux),
589};
590
591static const char *const emi_grps[] = { "emi_grp" };
592static struct spear_function emi_function = {
593 .name = "emi",
594 .groups = emi_grps,
595 .ngroups = ARRAY_SIZE(emi_grps),
596};
597
598/* Pad multiplexing for FSMC (NAND flash) device */
599static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600 61, 62, 63, 64, 65, 66, 67, 68 };
601static struct spear_muxreg fsmc_8bit_muxreg[] = {
602 {
603 .reg = IP_SEL_PAD_50_59_REG,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605 PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608 }, {
609 .reg = IP_SEL_PAD_60_69_REG,
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611 PMX_PL_65_TO_68_MASK,
612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613 PMX_FSMC_PL_65_TO_68_VAL,
614 }, {
615 .reg = EXT_CTRL_REG,
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
618 },
619};
620
621static struct spear_modemux fsmc_8bit_modemux[] = {
622 {
623 .modes = EXTENDED_MODE,
624 .muxregs = fsmc_8bit_muxreg,
625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626 },
627};
628
629static struct spear_pingroup fsmc_8bit_pingroup = {
630 .name = "fsmc_8bit_grp",
631 .pins = fsmc_8bit_pins,
632 .npins = ARRAY_SIZE(fsmc_8bit_pins),
633 .modemuxs = fsmc_8bit_modemux,
634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635};
636
637static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640 {
641 .reg = PMX_CONFIG_REG,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643 .val = 0,
644 },
645};
646
647static struct spear_muxreg fsmc_16bit_muxreg[] = {
648 {
649 .reg = IP_SEL_PAD_40_49_REG,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652 }, {
653 .reg = IP_SEL_PAD_70_79_REG,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656 PMX_FSMC_EMI_PL_73_VAL,
657 }
658};
659
660static struct spear_modemux fsmc_16bit_modemux[] = {
661 {
662 .modes = EXTENDED_MODE,
663 .muxregs = fsmc_8bit_muxreg,
664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665 }, {
666 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
667 .muxregs = fsmc_16bit_autoexp_muxreg,
668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669 }, {
670 .modes = EXTENDED_MODE,
671 .muxregs = fsmc_16bit_muxreg,
672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673 },
674};
675
676static struct spear_pingroup fsmc_16bit_pingroup = {
677 .name = "fsmc_16bit_grp",
678 .pins = fsmc_16bit_pins,
679 .npins = ARRAY_SIZE(fsmc_16bit_pins),
680 .modemuxs = fsmc_16bit_modemux,
681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682};
683
684static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685static struct spear_function fsmc_function = {
686 .name = "fsmc",
687 .groups = fsmc_grps,
688 .ngroups = ARRAY_SIZE(fsmc_grps),
689};
690
691/* Pad multiplexing for SPP device */
692static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693 80, 81, 82, 83, 84, 85 };
694static struct spear_muxreg spp_muxreg[] = {
695 {
696 .reg = IP_SEL_PAD_60_69_REG,
697 .mask = PMX_PL_69_MASK,
698 .val = PMX_SPP_PL_69_VAL,
699 }, {
700 .reg = IP_SEL_PAD_70_79_REG,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703 PMX_PL_77_78_79_MASK,
704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707 }, {
708 .reg = IP_SEL_PAD_80_89_REG,
709 .mask = PMX_PL_80_TO_85_MASK,
710 .val = PMX_SPP_PL_80_TO_85_VAL,
711 },
712};
713
714static struct spear_modemux spp_modemux[] = {
715 {
716 .modes = EXTENDED_MODE,
717 .muxregs = spp_muxreg,
718 .nmuxregs = ARRAY_SIZE(spp_muxreg),
719 },
720};
721
722static struct spear_pingroup spp_pingroup = {
723 .name = "spp_grp",
724 .pins = spp_pins,
725 .npins = ARRAY_SIZE(spp_pins),
726 .modemuxs = spp_modemux,
727 .nmodemuxs = ARRAY_SIZE(spp_modemux),
728};
729
730static const char *const spp_grps[] = { "spp_grp" };
731static struct spear_function spp_function = {
732 .name = "spp",
733 .groups = spp_grps,
734 .ngroups = ARRAY_SIZE(spp_grps),
735};
736
737/* Pad multiplexing for SDHCI device */
738static const unsigned sdhci_led_pins[] = { 34 };
739static struct spear_muxreg sdhci_led_muxreg[] = {
740 {
741 .reg = PMX_CONFIG_REG,
742 .mask = PMX_SSP_CS_MASK,
743 .val = 0,
744 },
745};
746
747static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748 {
749 .reg = IP_SEL_PAD_30_39_REG,
750 .mask = PMX_PL_34_MASK,
751 .val = PMX_PWM2_PL_34_VAL,
752 },
753};
754
755static struct spear_modemux sdhci_led_modemux[] = {
756 {
757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758 .muxregs = sdhci_led_muxreg,
759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760 }, {
761 .modes = EXTENDED_MODE,
762 .muxregs = sdhci_led_ext_muxreg,
763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764 },
765};
766
767static struct spear_pingroup sdhci_led_pingroup = {
768 .name = "sdhci_led_grp",
769 .pins = sdhci_led_pins,
770 .npins = ARRAY_SIZE(sdhci_led_pins),
771 .modemuxs = sdhci_led_modemux,
772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773};
774
775static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776 50};
777static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778};
779static struct spear_muxreg sdhci_muxreg[] = {
780 {
781 .reg = PMX_CONFIG_REG,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783 .val = 0,
784 },
785};
786
787static struct spear_muxreg sdhci_ext_muxreg[] = {
788 {
789 .reg = IP_SEL_PAD_40_49_REG,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791 PMX_PL_48_49_MASK,
792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794 }, {
795 .reg = IP_SEL_PAD_50_59_REG,
796 .mask = PMX_PL_50_MASK,
797 .val = PMX_SDHCI_PL_50_VAL,
798 }, {
799 .reg = IP_SEL_PAD_90_99_REG,
800 .mask = PMX_PL_99_MASK,
801 .val = PMX_SDHCI_PL_99_VAL,
802 }, {
803 .reg = IP_SEL_MIX_PAD_REG,
804 .mask = PMX_PL_100_101_MASK,
805 .val = PMX_SDHCI_PL_100_101_VAL,
806 },
807};
808
809static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810 {
811 .reg = PMX_CONFIG_REG,
812 .mask = PMX_MII_MASK,
813 .val = 0,
814 }, {
815 .reg = IP_SEL_PAD_10_19_REG,
816 .mask = PMX_PL_12_MASK,
817 .val = PMX_SDHCI_CD_PL_12_VAL,
818 }, {
819 .reg = IP_SEL_MIX_PAD_REG,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821 .val = PMX_SDHCI_CD_PORT_12_VAL,
822 },
823};
824
825static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826 {
827 .reg = IP_SEL_PAD_50_59_REG,
828 .mask = PMX_PL_51_MASK,
829 .val = PMX_SDHCI_CD_PL_51_VAL,
830 }, {
831 .reg = IP_SEL_MIX_PAD_REG,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833 .val = PMX_SDHCI_CD_PORT_51_VAL,
834 },
835};
836
837#define pmx_sdhci_common_modemux \
838 { \
839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841 .muxregs = sdhci_muxreg, \
842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843 }, { \
844 .modes = EXTENDED_MODE, \
845 .muxregs = sdhci_ext_muxreg, \
846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847 }
848
849static struct spear_modemux sdhci_modemux[][3] = {
850 {
851 /* select pin 12 for cd */
852 pmx_sdhci_common_modemux,
853 {
854 .modes = EXTENDED_MODE,
855 .muxregs = sdhci_cd_12_muxreg,
856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857 },
858 }, {
859 /* select pin 51 for cd */
860 pmx_sdhci_common_modemux,
861 {
862 .modes = EXTENDED_MODE,
863 .muxregs = sdhci_cd_51_muxreg,
864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865 },
866 }
867};
868
869static struct spear_pingroup sdhci_pingroup[] = {
870 {
871 .name = "sdhci_cd_12_grp",
872 .pins = sdhci_cd_12_pins,
873 .npins = ARRAY_SIZE(sdhci_cd_12_pins),
874 .modemuxs = sdhci_modemux[0],
875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876 }, {
877 .name = "sdhci_cd_51_grp",
878 .pins = sdhci_cd_51_pins,
879 .npins = ARRAY_SIZE(sdhci_cd_51_pins),
880 .modemuxs = sdhci_modemux[1],
881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882 },
883};
884
885static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886 "sdhci_led_grp" };
887
888static struct spear_function sdhci_function = {
889 .name = "sdhci",
890 .groups = sdhci_grps,
891 .ngroups = ARRAY_SIZE(sdhci_grps),
892};
893
894/* Pad multiplexing for I2S device */
895static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896static struct spear_muxreg i2s_muxreg[] = {
897 {
898 .reg = PMX_CONFIG_REG,
899 .mask = PMX_SSP_CS_MASK,
900 .val = 0,
901 }, {
902 .reg = PMX_CONFIG_REG,
903 .mask = PMX_UART0_MODEM_MASK,
904 .val = 0,
905 },
906};
907
908static struct spear_muxreg i2s_ext_muxreg[] = {
909 {
910 .reg = IP_SEL_PAD_30_39_REG,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913 }, {
914 .reg = IP_SEL_PAD_40_49_REG,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917 },
918};
919
920static struct spear_modemux i2s_modemux[] = {
921 {
922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923 .muxregs = i2s_muxreg,
924 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
925 }, {
926 .modes = EXTENDED_MODE,
927 .muxregs = i2s_ext_muxreg,
928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929 },
930};
931
932static struct spear_pingroup i2s_pingroup = {
933 .name = "i2s_grp",
934 .pins = i2s_pins,
935 .npins = ARRAY_SIZE(i2s_pins),
936 .modemuxs = i2s_modemux,
937 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
938};
939
940static const char *const i2s_grps[] = { "i2s_grp" };
941static struct spear_function i2s_function = {
942 .name = "i2s",
943 .groups = i2s_grps,
944 .ngroups = ARRAY_SIZE(i2s_grps),
945};
946
947/* Pad multiplexing for UART1 device */
948static const unsigned uart1_pins[] = { 28, 29 };
949static struct spear_muxreg uart1_muxreg[] = {
950 {
951 .reg = PMX_CONFIG_REG,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953 .val = 0,
954 },
955};
956
957static struct spear_muxreg uart1_ext_muxreg[] = {
958 {
959 .reg = IP_SEL_PAD_20_29_REG,
960 .mask = PMX_PL_28_29_MASK,
961 .val = PMX_UART1_PL_28_29_VAL,
962 },
963};
964
965static struct spear_modemux uart1_modemux[] = {
966 {
967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
969 .muxregs = uart1_muxreg,
970 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
971 }, {
972 .modes = EXTENDED_MODE,
973 .muxregs = uart1_ext_muxreg,
974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975 },
976};
977
978static struct spear_pingroup uart1_pingroup = {
979 .name = "uart1_grp",
980 .pins = uart1_pins,
981 .npins = ARRAY_SIZE(uart1_pins),
982 .modemuxs = uart1_modemux,
983 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
984};
985
986static const char *const uart1_grps[] = { "uart1_grp" };
987static struct spear_function uart1_function = {
988 .name = "uart1",
989 .groups = uart1_grps,
990 .ngroups = ARRAY_SIZE(uart1_grps),
991};
992
993/* Pad multiplexing for UART1 Modem device */
994static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998
999static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000 {
1001 .reg = PMX_CONFIG_REG,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003 .val = 0,
1004 }, {
1005 .reg = IP_SEL_PAD_0_9_REG,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008 PMX_UART1_ENH_PL_6_7_VAL,
1009 }, {
1010 .reg = IP_SEL_MIX_PAD_REG,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013 },
1014};
1015
1016static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017 {
1018 .reg = PMX_CONFIG_REG,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021 .val = 0,
1022 },
1023};
1024
1025static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026 {
1027 .reg = IP_SEL_PAD_30_39_REG,
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029 PMX_PL_35_MASK | PMX_PL_36_MASK,
1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032 PMX_UART1_ENH_PL_36_VAL,
1033 }, {
1034 .reg = IP_SEL_MIX_PAD_REG,
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037 },
1038};
1039
1040static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041 {
1042 .reg = PMX_CONFIG_REG,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044 PMX_SSP_CS_MASK,
1045 .val = 0,
1046 },
1047};
1048
1049static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050 {
1051 .reg = IP_SEL_PAD_30_39_REG,
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054 PMX_UART1_ENH_PL_36_VAL,
1055 }, {
1056 .reg = IP_SEL_PAD_40_49_REG,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059 }, {
1060 .reg = IP_SEL_MIX_PAD_REG,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063 },
1064};
1065
1066static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067 {
1068 .reg = IP_SEL_PAD_80_89_REG,
1069 .mask = PMX_PL_80_TO_85_MASK,
1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071 }, {
1072 .reg = IP_SEL_PAD_40_49_REG,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075 }, {
1076 .reg = IP_SEL_MIX_PAD_REG,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079 },
1080};
1081
1082static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083 {
1084 .modes = EXTENDED_MODE,
1085 .muxregs = uart1_modem_ext_2_to_7_muxreg,
1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087 },
1088};
1089
1090static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091 {
1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093 .muxregs = uart1_modem_31_to_36_muxreg,
1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095 }, {
1096 .modes = EXTENDED_MODE,
1097 .muxregs = uart1_modem_ext_31_to_36_muxreg,
1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099 },
1100};
1101
1102static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103 {
1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105 .muxregs = uart1_modem_34_to_45_muxreg,
1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107 }, {
1108 .modes = EXTENDED_MODE,
1109 .muxregs = uart1_modem_ext_34_to_45_muxreg,
1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111 },
1112};
1113
1114static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115 {
1116 .modes = EXTENDED_MODE,
1117 .muxregs = uart1_modem_ext_80_to_85_muxreg,
1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119 },
1120};
1121
1122static struct spear_pingroup uart1_modem_pingroup[] = {
1123 {
1124 .name = "uart1_modem_2_to_7_grp",
1125 .pins = uart1_modem_2_to_7_pins,
1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127 .modemuxs = uart1_modem_2_to_7_modemux,
1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129 }, {
1130 .name = "uart1_modem_31_to_36_grp",
1131 .pins = uart1_modem_31_to_36_pins,
1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133 .modemuxs = uart1_modem_31_to_36_modemux,
1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135 }, {
1136 .name = "uart1_modem_34_to_45_grp",
1137 .pins = uart1_modem_34_to_45_pins,
1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139 .modemuxs = uart1_modem_34_to_45_modemux,
1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141 }, {
1142 .name = "uart1_modem_80_to_85_grp",
1143 .pins = uart1_modem_80_to_85_pins,
1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145 .modemuxs = uart1_modem_80_to_85_modemux,
1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147 },
1148};
1149
1150static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152 "uart1_modem_80_to_85_grp" };
1153static struct spear_function uart1_modem_function = {
1154 .name = "uart1_modem",
1155 .groups = uart1_modem_grps,
1156 .ngroups = ARRAY_SIZE(uart1_modem_grps),
1157};
1158
1159/* Pad multiplexing for UART2 device */
1160static const unsigned uart2_pins[] = { 0, 1 };
1161static struct spear_muxreg uart2_muxreg[] = {
1162 {
1163 .reg = PMX_CONFIG_REG,
1164 .mask = PMX_FIRDA_MASK,
1165 .val = 0,
1166 },
1167};
1168
1169static struct spear_muxreg uart2_ext_muxreg[] = {
1170 {
1171 .reg = IP_SEL_PAD_0_9_REG,
1172 .mask = PMX_PL_0_1_MASK,
1173 .val = PMX_UART2_PL_0_1_VAL,
1174 },
1175};
1176
1177static struct spear_modemux uart2_modemux[] = {
1178 {
1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181 .muxregs = uart2_muxreg,
1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183 }, {
1184 .modes = EXTENDED_MODE,
1185 .muxregs = uart2_ext_muxreg,
1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187 },
1188};
1189
1190static struct spear_pingroup uart2_pingroup = {
1191 .name = "uart2_grp",
1192 .pins = uart2_pins,
1193 .npins = ARRAY_SIZE(uart2_pins),
1194 .modemuxs = uart2_modemux,
1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196};
1197
1198static const char *const uart2_grps[] = { "uart2_grp" };
1199static struct spear_function uart2_function = {
1200 .name = "uart2",
1201 .groups = uart2_grps,
1202 .ngroups = ARRAY_SIZE(uart2_grps),
1203};
1204
1205/* Pad multiplexing for uart3 device */
1206static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208
1209static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210 {
1211 .reg = PMX_CONFIG_REG,
1212 .mask = PMX_SSP_MASK,
1213 .val = 0,
1214 }, {
1215 .reg = IP_SEL_PAD_0_9_REG,
1216 .mask = PMX_PL_8_9_MASK,
1217 .val = PMX_UART3_PL_8_9_VAL,
1218 }, {
1219 .reg = IP_SEL_MIX_PAD_REG,
1220 .mask = PMX_UART3_PORT_SEL_MASK,
1221 .val = PMX_UART3_PORT_8_VAL,
1222 },
1223};
1224
1225static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226 {
1227 .reg = PMX_CONFIG_REG,
1228 .mask = PMX_MII_MASK,
1229 .val = 0,
1230 }, {
1231 .reg = IP_SEL_PAD_10_19_REG,
1232 .mask = PMX_PL_15_16_MASK,
1233 .val = PMX_UART3_PL_15_16_VAL,
1234 }, {
1235 .reg = IP_SEL_MIX_PAD_REG,
1236 .mask = PMX_UART3_PORT_SEL_MASK,
1237 .val = PMX_UART3_PORT_15_VAL,
1238 },
1239};
1240
1241static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242 {
1243 .reg = PMX_CONFIG_REG,
1244 .mask = PMX_UART0_MODEM_MASK,
1245 .val = 0,
1246 }, {
1247 .reg = IP_SEL_PAD_40_49_REG,
1248 .mask = PMX_PL_41_42_MASK,
1249 .val = PMX_UART3_PL_41_42_VAL,
1250 }, {
1251 .reg = IP_SEL_MIX_PAD_REG,
1252 .mask = PMX_UART3_PORT_SEL_MASK,
1253 .val = PMX_UART3_PORT_41_VAL,
1254 },
1255};
1256
1257static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258 {
1259 .reg = IP_SEL_PAD_50_59_REG,
1260 .mask = PMX_PL_52_53_MASK,
1261 .val = PMX_UART3_PL_52_53_VAL,
1262 }, {
1263 .reg = IP_SEL_MIX_PAD_REG,
1264 .mask = PMX_UART3_PORT_SEL_MASK,
1265 .val = PMX_UART3_PORT_52_VAL,
1266 },
1267};
1268
1269static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270 {
1271 .reg = IP_SEL_PAD_70_79_REG,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274 }, {
1275 .reg = IP_SEL_MIX_PAD_REG,
1276 .mask = PMX_UART3_PORT_SEL_MASK,
1277 .val = PMX_UART3_PORT_73_VAL,
1278 },
1279};
1280
1281static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282 {
1283 .reg = IP_SEL_PAD_90_99_REG,
1284 .mask = PMX_PL_94_95_MASK,
1285 .val = PMX_UART3_PL_94_95_VAL,
1286 }, {
1287 .reg = IP_SEL_MIX_PAD_REG,
1288 .mask = PMX_UART3_PORT_SEL_MASK,
1289 .val = PMX_UART3_PORT_94_VAL,
1290 },
1291};
1292
1293static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294 {
1295 .reg = IP_SEL_PAD_90_99_REG,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298 }, {
1299 .reg = IP_SEL_MIX_PAD_REG,
1300 .mask = PMX_UART3_PORT_SEL_MASK,
1301 .val = PMX_UART3_PORT_99_VAL,
1302 },
1303};
1304
1305static struct spear_modemux uart3_modemux[][1] = {
1306 {
1307 /* Select signals on pins 8_9 */
1308 {
1309 .modes = EXTENDED_MODE,
1310 .muxregs = uart3_ext_8_9_muxreg,
1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312 },
1313 }, {
1314 /* Select signals on pins 15_16 */
1315 {
1316 .modes = EXTENDED_MODE,
1317 .muxregs = uart3_ext_15_16_muxreg,
1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319 },
1320 }, {
1321 /* Select signals on pins 41_42 */
1322 {
1323 .modes = EXTENDED_MODE,
1324 .muxregs = uart3_ext_41_42_muxreg,
1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326 },
1327 }, {
1328 /* Select signals on pins 52_53 */
1329 {
1330 .modes = EXTENDED_MODE,
1331 .muxregs = uart3_ext_52_53_muxreg,
1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333 },
1334 }, {
1335 /* Select signals on pins 73_74 */
1336 {
1337 .modes = EXTENDED_MODE,
1338 .muxregs = uart3_ext_73_74_muxreg,
1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340 },
1341 }, {
1342 /* Select signals on pins 94_95 */
1343 {
1344 .modes = EXTENDED_MODE,
1345 .muxregs = uart3_ext_94_95_muxreg,
1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347 },
1348 }, {
1349 /* Select signals on pins 98_99 */
1350 {
1351 .modes = EXTENDED_MODE,
1352 .muxregs = uart3_ext_98_99_muxreg,
1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354 },
1355 },
1356};
1357
1358static struct spear_pingroup uart3_pingroup[] = {
1359 {
1360 .name = "uart3_8_9_grp",
1361 .pins = uart3_pins[0],
1362 .npins = ARRAY_SIZE(uart3_pins[0]),
1363 .modemuxs = uart3_modemux[0],
1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365 }, {
1366 .name = "uart3_15_16_grp",
1367 .pins = uart3_pins[1],
1368 .npins = ARRAY_SIZE(uart3_pins[1]),
1369 .modemuxs = uart3_modemux[1],
1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371 }, {
1372 .name = "uart3_41_42_grp",
1373 .pins = uart3_pins[2],
1374 .npins = ARRAY_SIZE(uart3_pins[2]),
1375 .modemuxs = uart3_modemux[2],
1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377 }, {
1378 .name = "uart3_52_53_grp",
1379 .pins = uart3_pins[3],
1380 .npins = ARRAY_SIZE(uart3_pins[3]),
1381 .modemuxs = uart3_modemux[3],
1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383 }, {
1384 .name = "uart3_73_74_grp",
1385 .pins = uart3_pins[4],
1386 .npins = ARRAY_SIZE(uart3_pins[4]),
1387 .modemuxs = uart3_modemux[4],
1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389 }, {
1390 .name = "uart3_94_95_grp",
1391 .pins = uart3_pins[5],
1392 .npins = ARRAY_SIZE(uart3_pins[5]),
1393 .modemuxs = uart3_modemux[5],
1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395 }, {
1396 .name = "uart3_98_99_grp",
1397 .pins = uart3_pins[6],
1398 .npins = ARRAY_SIZE(uart3_pins[6]),
1399 .modemuxs = uart3_modemux[6],
1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401 },
1402};
1403
1404static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406 "uart3_94_95_grp", "uart3_98_99_grp" };
1407
1408static struct spear_function uart3_function = {
1409 .name = "uart3",
1410 .groups = uart3_grps,
1411 .ngroups = ARRAY_SIZE(uart3_grps),
1412};
1413
1414/* Pad multiplexing for uart4 device */
1415static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416 { 71, 72 }, { 92, 93 }, { 100, 101 } };
1417
1418static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419 {
1420 .reg = PMX_CONFIG_REG,
1421 .mask = PMX_SSP_MASK,
1422 .val = 0,
1423 }, {
1424 .reg = IP_SEL_PAD_0_9_REG,
1425 .mask = PMX_PL_6_7_MASK,
1426 .val = PMX_UART4_PL_6_7_VAL,
1427 }, {
1428 .reg = IP_SEL_MIX_PAD_REG,
1429 .mask = PMX_UART4_PORT_SEL_MASK,
1430 .val = PMX_UART4_PORT_6_VAL,
1431 },
1432};
1433
1434static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435 {
1436 .reg = PMX_CONFIG_REG,
1437 .mask = PMX_MII_MASK,
1438 .val = 0,
1439 }, {
1440 .reg = IP_SEL_PAD_10_19_REG,
1441 .mask = PMX_PL_13_14_MASK,
1442 .val = PMX_UART4_PL_13_14_VAL,
1443 }, {
1444 .reg = IP_SEL_MIX_PAD_REG,
1445 .mask = PMX_UART4_PORT_SEL_MASK,
1446 .val = PMX_UART4_PORT_13_VAL,
1447 },
1448};
1449
1450static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451 {
1452 .reg = PMX_CONFIG_REG,
1453 .mask = PMX_UART0_MODEM_MASK,
1454 .val = 0,
1455 }, {
1456 .reg = IP_SEL_PAD_30_39_REG,
1457 .mask = PMX_PL_39_MASK,
1458 .val = PMX_UART4_PL_39_VAL,
1459 }, {
1460 .reg = IP_SEL_PAD_40_49_REG,
1461 .mask = PMX_PL_40_MASK,
1462 .val = PMX_UART4_PL_40_VAL,
1463 }, {
1464 .reg = IP_SEL_MIX_PAD_REG,
1465 .mask = PMX_UART4_PORT_SEL_MASK,
1466 .val = PMX_UART4_PORT_39_VAL,
1467 },
1468};
1469
1470static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471 {
1472 .reg = IP_SEL_PAD_70_79_REG,
1473 .mask = PMX_PL_71_72_MASK,
1474 .val = PMX_UART4_PL_71_72_VAL,
1475 }, {
1476 .reg = IP_SEL_MIX_PAD_REG,
1477 .mask = PMX_UART4_PORT_SEL_MASK,
1478 .val = PMX_UART4_PORT_71_VAL,
1479 },
1480};
1481
1482static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483 {
1484 .reg = IP_SEL_PAD_90_99_REG,
1485 .mask = PMX_PL_92_93_MASK,
1486 .val = PMX_UART4_PL_92_93_VAL,
1487 }, {
1488 .reg = IP_SEL_MIX_PAD_REG,
1489 .mask = PMX_UART4_PORT_SEL_MASK,
1490 .val = PMX_UART4_PORT_92_VAL,
1491 },
1492};
1493
1494static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495 {
1496 .reg = IP_SEL_MIX_PAD_REG,
1497 .mask = PMX_PL_100_101_MASK |
1498 PMX_UART4_PORT_SEL_MASK,
1499 .val = PMX_UART4_PL_100_101_VAL |
1500 PMX_UART4_PORT_101_VAL,
1501 },
1502};
1503
1504static struct spear_modemux uart4_modemux[][1] = {
1505 {
1506 /* Select signals on pins 6_7 */
1507 {
1508 .modes = EXTENDED_MODE,
1509 .muxregs = uart4_ext_6_7_muxreg,
1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511 },
1512 }, {
1513 /* Select signals on pins 13_14 */
1514 {
1515 .modes = EXTENDED_MODE,
1516 .muxregs = uart4_ext_13_14_muxreg,
1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518 },
1519 }, {
1520 /* Select signals on pins 39_40 */
1521 {
1522 .modes = EXTENDED_MODE,
1523 .muxregs = uart4_ext_39_40_muxreg,
1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525 },
1526 }, {
1527 /* Select signals on pins 71_72 */
1528 {
1529 .modes = EXTENDED_MODE,
1530 .muxregs = uart4_ext_71_72_muxreg,
1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532 },
1533 }, {
1534 /* Select signals on pins 92_93 */
1535 {
1536 .modes = EXTENDED_MODE,
1537 .muxregs = uart4_ext_92_93_muxreg,
1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539 },
1540 }, {
1541 /* Select signals on pins 100_101_ */
1542 {
1543 .modes = EXTENDED_MODE,
1544 .muxregs = uart4_ext_100_101_muxreg,
1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546 },
1547 },
1548};
1549
1550static struct spear_pingroup uart4_pingroup[] = {
1551 {
1552 .name = "uart4_6_7_grp",
1553 .pins = uart4_pins[0],
1554 .npins = ARRAY_SIZE(uart4_pins[0]),
1555 .modemuxs = uart4_modemux[0],
1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557 }, {
1558 .name = "uart4_13_14_grp",
1559 .pins = uart4_pins[1],
1560 .npins = ARRAY_SIZE(uart4_pins[1]),
1561 .modemuxs = uart4_modemux[1],
1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563 }, {
1564 .name = "uart4_39_40_grp",
1565 .pins = uart4_pins[2],
1566 .npins = ARRAY_SIZE(uart4_pins[2]),
1567 .modemuxs = uart4_modemux[2],
1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569 }, {
1570 .name = "uart4_71_72_grp",
1571 .pins = uart4_pins[3],
1572 .npins = ARRAY_SIZE(uart4_pins[3]),
1573 .modemuxs = uart4_modemux[3],
1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575 }, {
1576 .name = "uart4_92_93_grp",
1577 .pins = uart4_pins[4],
1578 .npins = ARRAY_SIZE(uart4_pins[4]),
1579 .modemuxs = uart4_modemux[4],
1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581 }, {
1582 .name = "uart4_100_101_grp",
1583 .pins = uart4_pins[5],
1584 .npins = ARRAY_SIZE(uart4_pins[5]),
1585 .modemuxs = uart4_modemux[5],
1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587 },
1588};
1589
1590static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592 "uart4_100_101_grp" };
1593
1594static struct spear_function uart4_function = {
1595 .name = "uart4",
1596 .groups = uart4_grps,
1597 .ngroups = ARRAY_SIZE(uart4_grps),
1598};
1599
1600/* Pad multiplexing for uart5 device */
1601static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602 { 90, 91 } };
1603
1604static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605 {
1606 .reg = PMX_CONFIG_REG,
1607 .mask = PMX_I2C_MASK,
1608 .val = 0,
1609 }, {
1610 .reg = IP_SEL_PAD_0_9_REG,
1611 .mask = PMX_PL_4_5_MASK,
1612 .val = PMX_UART5_PL_4_5_VAL,
1613 }, {
1614 .reg = IP_SEL_MIX_PAD_REG,
1615 .mask = PMX_UART5_PORT_SEL_MASK,
1616 .val = PMX_UART5_PORT_4_VAL,
1617 },
1618};
1619
1620static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621 {
1622 .reg = PMX_CONFIG_REG,
1623 .mask = PMX_UART0_MODEM_MASK,
1624 .val = 0,
1625 }, {
1626 .reg = IP_SEL_PAD_30_39_REG,
1627 .mask = PMX_PL_37_38_MASK,
1628 .val = PMX_UART5_PL_37_38_VAL,
1629 }, {
1630 .reg = IP_SEL_MIX_PAD_REG,
1631 .mask = PMX_UART5_PORT_SEL_MASK,
1632 .val = PMX_UART5_PORT_37_VAL,
1633 },
1634};
1635
1636static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637 {
1638 .reg = IP_SEL_PAD_60_69_REG,
1639 .mask = PMX_PL_69_MASK,
1640 .val = PMX_UART5_PL_69_VAL,
1641 }, {
1642 .reg = IP_SEL_PAD_70_79_REG,
1643 .mask = PMX_PL_70_MASK,
1644 .val = PMX_UART5_PL_70_VAL,
1645 }, {
1646 .reg = IP_SEL_MIX_PAD_REG,
1647 .mask = PMX_UART5_PORT_SEL_MASK,
1648 .val = PMX_UART5_PORT_69_VAL,
1649 },
1650};
1651
1652static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653 {
1654 .reg = IP_SEL_PAD_90_99_REG,
1655 .mask = PMX_PL_90_91_MASK,
1656 .val = PMX_UART5_PL_90_91_VAL,
1657 }, {
1658 .reg = IP_SEL_MIX_PAD_REG,
1659 .mask = PMX_UART5_PORT_SEL_MASK,
1660 .val = PMX_UART5_PORT_90_VAL,
1661 },
1662};
1663
1664static struct spear_modemux uart5_modemux[][1] = {
1665 {
1666 /* Select signals on pins 4_5 */
1667 {
1668 .modes = EXTENDED_MODE,
1669 .muxregs = uart5_ext_4_5_muxreg,
1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671 },
1672 }, {
1673 /* Select signals on pins 37_38 */
1674 {
1675 .modes = EXTENDED_MODE,
1676 .muxregs = uart5_ext_37_38_muxreg,
1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678 },
1679 }, {
1680 /* Select signals on pins 69_70 */
1681 {
1682 .modes = EXTENDED_MODE,
1683 .muxregs = uart5_ext_69_70_muxreg,
1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685 },
1686 }, {
1687 /* Select signals on pins 90_91 */
1688 {
1689 .modes = EXTENDED_MODE,
1690 .muxregs = uart5_ext_90_91_muxreg,
1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692 },
1693 },
1694};
1695
1696static struct spear_pingroup uart5_pingroup[] = {
1697 {
1698 .name = "uart5_4_5_grp",
1699 .pins = uart5_pins[0],
1700 .npins = ARRAY_SIZE(uart5_pins[0]),
1701 .modemuxs = uart5_modemux[0],
1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703 }, {
1704 .name = "uart5_37_38_grp",
1705 .pins = uart5_pins[1],
1706 .npins = ARRAY_SIZE(uart5_pins[1]),
1707 .modemuxs = uart5_modemux[1],
1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709 }, {
1710 .name = "uart5_69_70_grp",
1711 .pins = uart5_pins[2],
1712 .npins = ARRAY_SIZE(uart5_pins[2]),
1713 .modemuxs = uart5_modemux[2],
1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715 }, {
1716 .name = "uart5_90_91_grp",
1717 .pins = uart5_pins[3],
1718 .npins = ARRAY_SIZE(uart5_pins[3]),
1719 .modemuxs = uart5_modemux[3],
1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721 },
1722};
1723
1724static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725 "uart5_69_70_grp", "uart5_90_91_grp" };
1726static struct spear_function uart5_function = {
1727 .name = "uart5",
1728 .groups = uart5_grps,
1729 .ngroups = ARRAY_SIZE(uart5_grps),
1730};
1731
1732/* Pad multiplexing for uart6 device */
1733static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735 {
1736 .reg = PMX_CONFIG_REG,
1737 .mask = PMX_UART0_MASK,
1738 .val = 0,
1739 }, {
1740 .reg = IP_SEL_PAD_0_9_REG,
1741 .mask = PMX_PL_2_3_MASK,
1742 .val = PMX_UART6_PL_2_3_VAL,
1743 }, {
1744 .reg = IP_SEL_MIX_PAD_REG,
1745 .mask = PMX_UART6_PORT_SEL_MASK,
1746 .val = PMX_UART6_PORT_2_VAL,
1747 },
1748};
1749
1750static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751 {
1752 .reg = IP_SEL_PAD_80_89_REG,
1753 .mask = PMX_PL_88_89_MASK,
1754 .val = PMX_UART6_PL_88_89_VAL,
1755 }, {
1756 .reg = IP_SEL_MIX_PAD_REG,
1757 .mask = PMX_UART6_PORT_SEL_MASK,
1758 .val = PMX_UART6_PORT_88_VAL,
1759 },
1760};
1761
1762static struct spear_modemux uart6_modemux[][1] = {
1763 {
1764 /* Select signals on pins 2_3 */
1765 {
1766 .modes = EXTENDED_MODE,
1767 .muxregs = uart6_ext_2_3_muxreg,
1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769 },
1770 }, {
1771 /* Select signals on pins 88_89 */
1772 {
1773 .modes = EXTENDED_MODE,
1774 .muxregs = uart6_ext_88_89_muxreg,
1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776 },
1777 },
1778};
1779
1780static struct spear_pingroup uart6_pingroup[] = {
1781 {
1782 .name = "uart6_2_3_grp",
1783 .pins = uart6_pins[0],
1784 .npins = ARRAY_SIZE(uart6_pins[0]),
1785 .modemuxs = uart6_modemux[0],
1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787 }, {
1788 .name = "uart6_88_89_grp",
1789 .pins = uart6_pins[1],
1790 .npins = ARRAY_SIZE(uart6_pins[1]),
1791 .modemuxs = uart6_modemux[1],
1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793 },
1794};
1795
1796static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797static struct spear_function uart6_function = {
1798 .name = "uart6",
1799 .groups = uart6_grps,
1800 .ngroups = ARRAY_SIZE(uart6_grps),
1801};
1802
1803/* UART - RS485 pmx */
1804static const unsigned rs485_pins[] = { 77, 78, 79 };
1805static struct spear_muxreg rs485_muxreg[] = {
1806 {
1807 .reg = IP_SEL_PAD_70_79_REG,
1808 .mask = PMX_PL_77_78_79_MASK,
1809 .val = PMX_RS485_PL_77_78_79_VAL,
1810 },
1811};
1812
1813static struct spear_modemux rs485_modemux[] = {
1814 {
1815 .modes = EXTENDED_MODE,
1816 .muxregs = rs485_muxreg,
1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818 },
1819};
1820
1821static struct spear_pingroup rs485_pingroup = {
1822 .name = "rs485_grp",
1823 .pins = rs485_pins,
1824 .npins = ARRAY_SIZE(rs485_pins),
1825 .modemuxs = rs485_modemux,
1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827};
1828
1829static const char *const rs485_grps[] = { "rs485_grp" };
1830static struct spear_function rs485_function = {
1831 .name = "rs485",
1832 .groups = rs485_grps,
1833 .ngroups = ARRAY_SIZE(rs485_grps),
1834};
1835
1836/* Pad multiplexing for Touchscreen device */
1837static const unsigned touchscreen_pins[] = { 5, 36 };
1838static struct spear_muxreg touchscreen_muxreg[] = {
1839 {
1840 .reg = PMX_CONFIG_REG,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842 .val = 0,
1843 },
1844};
1845
1846static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847 {
1848 .reg = IP_SEL_PAD_0_9_REG,
1849 .mask = PMX_PL_5_MASK,
1850 .val = PMX_TOUCH_Y_PL_5_VAL,
1851 }, {
1852 .reg = IP_SEL_PAD_30_39_REG,
1853 .mask = PMX_PL_36_MASK,
1854 .val = PMX_TOUCH_X_PL_36_VAL,
1855 },
1856};
1857
1858static struct spear_modemux touchscreen_modemux[] = {
1859 {
1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861 .muxregs = touchscreen_muxreg,
1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863 }, {
1864 .modes = EXTENDED_MODE,
1865 .muxregs = touchscreen_ext_muxreg,
1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867 },
1868};
1869
1870static struct spear_pingroup touchscreen_pingroup = {
1871 .name = "touchscreen_grp",
1872 .pins = touchscreen_pins,
1873 .npins = ARRAY_SIZE(touchscreen_pins),
1874 .modemuxs = touchscreen_modemux,
1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876};
1877
1878static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879static struct spear_function touchscreen_function = {
1880 .name = "touchscreen",
1881 .groups = touchscreen_grps,
1882 .ngroups = ARRAY_SIZE(touchscreen_grps),
1883};
1884
1885/* Pad multiplexing for CAN device */
1886static const unsigned can0_pins[] = { 32, 33 };
1887static struct spear_muxreg can0_muxreg[] = {
1888 {
1889 .reg = PMX_CONFIG_REG,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891 .val = 0,
1892 },
1893};
1894
1895static struct spear_muxreg can0_ext_muxreg[] = {
1896 {
1897 .reg = IP_SEL_PAD_30_39_REG,
1898 .mask = PMX_PL_32_33_MASK,
1899 .val = PMX_CAN0_PL_32_33_VAL,
1900 },
1901};
1902
1903static struct spear_modemux can0_modemux[] = {
1904 {
1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906 | EXTENDED_MODE,
1907 .muxregs = can0_muxreg,
1908 .nmuxregs = ARRAY_SIZE(can0_muxreg),
1909 }, {
1910 .modes = EXTENDED_MODE,
1911 .muxregs = can0_ext_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913 },
1914};
1915
1916static struct spear_pingroup can0_pingroup = {
1917 .name = "can0_grp",
1918 .pins = can0_pins,
1919 .npins = ARRAY_SIZE(can0_pins),
1920 .modemuxs = can0_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_modemux),
1922};
1923
1924static const char *const can0_grps[] = { "can0_grp" };
1925static struct spear_function can0_function = {
1926 .name = "can0",
1927 .groups = can0_grps,
1928 .ngroups = ARRAY_SIZE(can0_grps),
1929};
1930
1931static const unsigned can1_pins[] = { 30, 31 };
1932static struct spear_muxreg can1_muxreg[] = {
1933 {
1934 .reg = PMX_CONFIG_REG,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936 .val = 0,
1937 },
1938};
1939
1940static struct spear_muxreg can1_ext_muxreg[] = {
1941 {
1942 .reg = IP_SEL_PAD_30_39_REG,
1943 .mask = PMX_PL_30_31_MASK,
1944 .val = PMX_CAN1_PL_30_31_VAL,
1945 },
1946};
1947
1948static struct spear_modemux can1_modemux[] = {
1949 {
1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951 | EXTENDED_MODE,
1952 .muxregs = can1_muxreg,
1953 .nmuxregs = ARRAY_SIZE(can1_muxreg),
1954 }, {
1955 .modes = EXTENDED_MODE,
1956 .muxregs = can1_ext_muxreg,
1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958 },
1959};
1960
1961static struct spear_pingroup can1_pingroup = {
1962 .name = "can1_grp",
1963 .pins = can1_pins,
1964 .npins = ARRAY_SIZE(can1_pins),
1965 .modemuxs = can1_modemux,
1966 .nmodemuxs = ARRAY_SIZE(can1_modemux),
1967};
1968
1969static const char *const can1_grps[] = { "can1_grp" };
1970static struct spear_function can1_function = {
1971 .name = "can1",
1972 .groups = can1_grps,
1973 .ngroups = ARRAY_SIZE(can1_grps),
1974};
1975
1976/* Pad multiplexing for PWM0_1 device */
1977static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979
1980static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981 {
1982 .reg = PMX_CONFIG_REG,
1983 .mask = PMX_SSP_MASK,
1984 .val = 0,
1985 }, {
1986 .reg = IP_SEL_PAD_0_9_REG,
1987 .mask = PMX_PL_8_9_MASK,
1988 .val = PMX_PWM_0_1_PL_8_9_VAL,
1989 },
1990};
1991
1992static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993 {
1994 .reg = PMX_CONFIG_REG,
1995 .mask = PMX_MII_MASK,
1996 .val = 0,
1997 },
1998};
1999
2000static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001 {
2002 .reg = IP_SEL_PAD_10_19_REG,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005 },
2006};
2007
2008static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009 {
2010 .reg = PMX_CONFIG_REG,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012 .val = 0,
2013 }, {
2014 .reg = IP_SEL_PAD_30_39_REG,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017 },
2018};
2019
2020static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021 {
2022 .reg = PMX_CONFIG_REG,
2023 .mask = PMX_UART0_MODEM_MASK,
2024 .val = 0,
2025 },
2026};
2027
2028static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029 {
2030 .reg = IP_SEL_PAD_30_39_REG,
2031 .mask = PMX_PL_37_38_MASK,
2032 .val = PMX_PWM0_1_PL_37_38_VAL,
2033 },
2034};
2035
2036static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037 {
2038 .reg = PMX_CONFIG_REG,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040 .val = 0,
2041 }, {
2042 .reg = IP_SEL_PAD_40_49_REG,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044 .val = PMX_PWM1_PL_42_VAL |
2045 PMX_PWM0_PL_43_VAL,
2046 },
2047};
2048
2049static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050 {
2051 .reg = IP_SEL_PAD_50_59_REG,
2052 .mask = PMX_PL_59_MASK,
2053 .val = PMX_PWM1_PL_59_VAL,
2054 }, {
2055 .reg = IP_SEL_PAD_60_69_REG,
2056 .mask = PMX_PL_60_MASK,
2057 .val = PMX_PWM0_PL_60_VAL,
2058 },
2059};
2060
2061static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062 {
2063 .reg = IP_SEL_PAD_80_89_REG,
2064 .mask = PMX_PL_88_89_MASK,
2065 .val = PMX_PWM0_1_PL_88_89_VAL,
2066 },
2067};
2068
2069static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070 {
2071 .modes = EXTENDED_MODE,
2072 .muxregs = pwm0_1_pin_8_9_muxreg,
2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074 },
2075};
2076
2077static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078 {
2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082 }, {
2083 .modes = EXTENDED_MODE,
2084 .muxregs = pwm0_1_pin_14_15_muxreg,
2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086 },
2087};
2088
2089static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090 {
2091 .modes = EXTENDED_MODE,
2092 .muxregs = pwm0_1_pin_30_31_muxreg,
2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094 },
2095};
2096
2097static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098 {
2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100 .muxregs = pwm0_1_net_muxreg,
2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102 }, {
2103 .modes = EXTENDED_MODE,
2104 .muxregs = pwm0_1_pin_37_38_muxreg,
2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106 },
2107};
2108
2109static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110 {
2111 .modes = EXTENDED_MODE,
2112 .muxregs = pwm0_1_pin_42_43_muxreg,
2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114 },
2115};
2116
2117static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118 {
2119 .modes = EXTENDED_MODE,
2120 .muxregs = pwm0_1_pin_59_60_muxreg,
2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122 },
2123};
2124
2125static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126 {
2127 .modes = EXTENDED_MODE,
2128 .muxregs = pwm0_1_pin_88_89_muxreg,
2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130 },
2131};
2132
2133static struct spear_pingroup pwm0_1_pingroup[] = {
2134 {
2135 .name = "pwm0_1_pin_8_9_grp",
2136 .pins = pwm0_1_pins[0],
2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138 .modemuxs = pwm0_1_pin_8_9_modemux,
2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140 }, {
2141 .name = "pwm0_1_pin_14_15_grp",
2142 .pins = pwm0_1_pins[1],
2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144 .modemuxs = pwm0_1_pin_14_15_modemux,
2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146 }, {
2147 .name = "pwm0_1_pin_30_31_grp",
2148 .pins = pwm0_1_pins[2],
2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150 .modemuxs = pwm0_1_pin_30_31_modemux,
2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152 }, {
2153 .name = "pwm0_1_pin_37_38_grp",
2154 .pins = pwm0_1_pins[3],
2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156 .modemuxs = pwm0_1_pin_37_38_modemux,
2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158 }, {
2159 .name = "pwm0_1_pin_42_43_grp",
2160 .pins = pwm0_1_pins[4],
2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162 .modemuxs = pwm0_1_pin_42_43_modemux,
2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164 }, {
2165 .name = "pwm0_1_pin_59_60_grp",
2166 .pins = pwm0_1_pins[5],
2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168 .modemuxs = pwm0_1_pin_59_60_modemux,
2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170 }, {
2171 .name = "pwm0_1_pin_88_89_grp",
2172 .pins = pwm0_1_pins[6],
2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174 .modemuxs = pwm0_1_pin_88_89_modemux,
2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176 },
2177};
2178
2179static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182};
2183
2184static struct spear_function pwm0_1_function = {
2185 .name = "pwm0_1",
2186 .groups = pwm0_1_grps,
2187 .ngroups = ARRAY_SIZE(pwm0_1_grps),
2188};
2189
2190/* Pad multiplexing for PWM2 device */
2191static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192 { 58 }, { 87 } };
2193static struct spear_muxreg pwm2_net_muxreg[] = {
2194 {
2195 .reg = PMX_CONFIG_REG,
2196 .mask = PMX_SSP_CS_MASK,
2197 .val = 0,
2198 },
2199};
2200
2201static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202 {
2203 .reg = IP_SEL_PAD_0_9_REG,
2204 .mask = PMX_PL_7_MASK,
2205 .val = PMX_PWM_2_PL_7_VAL,
2206 },
2207};
2208
2209static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210 {
2211 .reg = PMX_CONFIG_REG,
2212 .mask = PMX_MII_MASK,
2213 .val = 0,
2214 },
2215};
2216
2217static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218 {
2219 .reg = IP_SEL_PAD_10_19_REG,
2220 .mask = PMX_PL_13_MASK,
2221 .val = PMX_PWM2_PL_13_VAL,
2222 },
2223};
2224
2225static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226 {
2227 .reg = PMX_CONFIG_REG,
2228 .mask = PMX_GPIO_PIN1_MASK,
2229 .val = 0,
2230 }, {
2231 .reg = IP_SEL_PAD_20_29_REG,
2232 .mask = PMX_PL_29_MASK,
2233 .val = PMX_PWM_2_PL_29_VAL,
2234 },
2235};
2236
2237static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238 {
2239 .reg = PMX_CONFIG_REG,
2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0,
2242 }, {
2243 .reg = IP_SEL_PAD_30_39_REG,
2244 .mask = PMX_PL_34_MASK,
2245 .val = PMX_PWM2_PL_34_VAL,
2246 },
2247};
2248
2249static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2250 {
2251 .reg = PMX_CONFIG_REG,
2252 .mask = PMX_UART0_MODEM_MASK,
2253 .val = 0,
2254 }, {
2255 .reg = IP_SEL_PAD_40_49_REG,
2256 .mask = PMX_PL_41_MASK,
2257 .val = PMX_PWM2_PL_41_VAL,
2258 },
2259};
2260
2261static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2262 {
2263 .reg = IP_SEL_PAD_50_59_REG,
2264 .mask = PMX_PL_58_MASK,
2265 .val = PMX_PWM2_PL_58_VAL,
2266 },
2267};
2268
2269static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2270 {
2271 .reg = IP_SEL_PAD_80_89_REG,
2272 .mask = PMX_PL_87_MASK,
2273 .val = PMX_PWM2_PL_87_VAL,
2274 },
2275};
2276
2277static struct spear_modemux pwm2_pin_7_modemux[] = {
2278 {
2279 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2280 .muxregs = pwm2_net_muxreg,
2281 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2282 }, {
2283 .modes = EXTENDED_MODE,
2284 .muxregs = pwm2_pin_7_muxreg,
2285 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2286 },
2287};
2288static struct spear_modemux pwm2_pin_13_modemux[] = {
2289 {
2290 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2291 .muxregs = pwm2_autoexpsmallpri_muxreg,
2292 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2293 }, {
2294 .modes = EXTENDED_MODE,
2295 .muxregs = pwm2_pin_13_muxreg,
2296 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2297 },
2298};
2299static struct spear_modemux pwm2_pin_29_modemux[] = {
2300 {
2301 .modes = EXTENDED_MODE,
2302 .muxregs = pwm2_pin_29_muxreg,
2303 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2304 },
2305};
2306static struct spear_modemux pwm2_pin_34_modemux[] = {
2307 {
2308 .modes = EXTENDED_MODE,
2309 .muxregs = pwm2_pin_34_muxreg,
2310 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2311 },
2312};
2313
2314static struct spear_modemux pwm2_pin_41_modemux[] = {
2315 {
2316 .modes = EXTENDED_MODE,
2317 .muxregs = pwm2_pin_41_muxreg,
2318 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2319 },
2320};
2321
2322static struct spear_modemux pwm2_pin_58_modemux[] = {
2323 {
2324 .modes = EXTENDED_MODE,
2325 .muxregs = pwm2_pin_58_muxreg,
2326 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2327 },
2328};
2329
2330static struct spear_modemux pwm2_pin_87_modemux[] = {
2331 {
2332 .modes = EXTENDED_MODE,
2333 .muxregs = pwm2_pin_87_muxreg,
2334 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2335 },
2336};
2337
2338static struct spear_pingroup pwm2_pingroup[] = {
2339 {
2340 .name = "pwm2_pin_7_grp",
2341 .pins = pwm2_pins[0],
2342 .npins = ARRAY_SIZE(pwm2_pins[0]),
2343 .modemuxs = pwm2_pin_7_modemux,
2344 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2345 }, {
2346 .name = "pwm2_pin_13_grp",
2347 .pins = pwm2_pins[1],
2348 .npins = ARRAY_SIZE(pwm2_pins[1]),
2349 .modemuxs = pwm2_pin_13_modemux,
2350 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2351 }, {
2352 .name = "pwm2_pin_29_grp",
2353 .pins = pwm2_pins[2],
2354 .npins = ARRAY_SIZE(pwm2_pins[2]),
2355 .modemuxs = pwm2_pin_29_modemux,
2356 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2357 }, {
2358 .name = "pwm2_pin_34_grp",
2359 .pins = pwm2_pins[3],
2360 .npins = ARRAY_SIZE(pwm2_pins[3]),
2361 .modemuxs = pwm2_pin_34_modemux,
2362 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2363 }, {
2364 .name = "pwm2_pin_41_grp",
2365 .pins = pwm2_pins[4],
2366 .npins = ARRAY_SIZE(pwm2_pins[4]),
2367 .modemuxs = pwm2_pin_41_modemux,
2368 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2369 }, {
2370 .name = "pwm2_pin_58_grp",
2371 .pins = pwm2_pins[5],
2372 .npins = ARRAY_SIZE(pwm2_pins[5]),
2373 .modemuxs = pwm2_pin_58_modemux,
2374 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2375 }, {
2376 .name = "pwm2_pin_87_grp",
2377 .pins = pwm2_pins[6],
2378 .npins = ARRAY_SIZE(pwm2_pins[6]),
2379 .modemuxs = pwm2_pin_87_modemux,
2380 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2381 },
2382};
2383
2384static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2385 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2386 "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2387static struct spear_function pwm2_function = {
2388 .name = "pwm2",
2389 .groups = pwm2_grps,
2390 .ngroups = ARRAY_SIZE(pwm2_grps),
2391};
2392
2393/* Pad multiplexing for PWM3 device */
2394static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2395 { 86 } };
2396static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2397 {
2398 .reg = PMX_CONFIG_REG,
2399 .mask = PMX_SSP_MASK,
2400 .val = 0,
2401 }, {
2402 .reg = IP_SEL_PAD_0_9_REG,
2403 .mask = PMX_PL_6_MASK,
2404 .val = PMX_PWM_3_PL_6_VAL,
2405 },
2406};
2407
2408static struct spear_muxreg pwm3_muxreg[] = {
2409 {
2410 .reg = PMX_CONFIG_REG,
2411 .mask = PMX_MII_MASK,
2412 .val = 0,
2413 },
2414};
2415
2416static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2417 {
2418 .reg = IP_SEL_PAD_10_19_REG,
2419 .mask = PMX_PL_12_MASK,
2420 .val = PMX_PWM3_PL_12_VAL,
2421 },
2422};
2423
2424static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2425 {
2426 .reg = PMX_CONFIG_REG,
2427 .mask = PMX_GPIO_PIN0_MASK,
2428 .val = 0,
2429 }, {
2430 .reg = IP_SEL_PAD_20_29_REG,
2431 .mask = PMX_PL_28_MASK,
2432 .val = PMX_PWM_3_PL_28_VAL,
2433 },
2434};
2435
2436static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2437 {
2438 .reg = PMX_CONFIG_REG,
2439 .mask = PMX_UART0_MODEM_MASK,
2440 .val = 0,
2441 }, {
2442 .reg = IP_SEL_PAD_40_49_REG,
2443 .mask = PMX_PL_40_MASK,
2444 .val = PMX_PWM3_PL_40_VAL,
2445 },
2446};
2447
2448static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2449 {
2450 .reg = IP_SEL_PAD_50_59_REG,
2451 .mask = PMX_PL_57_MASK,
2452 .val = PMX_PWM3_PL_57_VAL,
2453 },
2454};
2455
2456static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2457 {
2458 .reg = IP_SEL_PAD_80_89_REG,
2459 .mask = PMX_PL_86_MASK,
2460 .val = PMX_PWM3_PL_86_VAL,
2461 },
2462};
2463
2464static struct spear_modemux pwm3_pin_6_modemux[] = {
2465 {
2466 .modes = EXTENDED_MODE,
2467 .muxregs = pwm3_pin_6_muxreg,
2468 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2469 },
2470};
2471
2472static struct spear_modemux pwm3_pin_12_modemux[] = {
2473 {
2474 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2475 AUTO_NET_SMII_MODE | EXTENDED_MODE,
2476 .muxregs = pwm3_muxreg,
2477 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2478 }, {
2479 .modes = EXTENDED_MODE,
2480 .muxregs = pwm3_pin_12_muxreg,
2481 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2482 },
2483};
2484
2485static struct spear_modemux pwm3_pin_28_modemux[] = {
2486 {
2487 .modes = EXTENDED_MODE,
2488 .muxregs = pwm3_pin_28_muxreg,
2489 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2490 },
2491};
2492
2493static struct spear_modemux pwm3_pin_40_modemux[] = {
2494 {
2495 .modes = EXTENDED_MODE,
2496 .muxregs = pwm3_pin_40_muxreg,
2497 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2498 },
2499};
2500
2501static struct spear_modemux pwm3_pin_57_modemux[] = {
2502 {
2503 .modes = EXTENDED_MODE,
2504 .muxregs = pwm3_pin_57_muxreg,
2505 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2506 },
2507};
2508
2509static struct spear_modemux pwm3_pin_86_modemux[] = {
2510 {
2511 .modes = EXTENDED_MODE,
2512 .muxregs = pwm3_pin_86_muxreg,
2513 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2514 },
2515};
2516
2517static struct spear_pingroup pwm3_pingroup[] = {
2518 {
2519 .name = "pwm3_pin_6_grp",
2520 .pins = pwm3_pins[0],
2521 .npins = ARRAY_SIZE(pwm3_pins[0]),
2522 .modemuxs = pwm3_pin_6_modemux,
2523 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2524 }, {
2525 .name = "pwm3_pin_12_grp",
2526 .pins = pwm3_pins[1],
2527 .npins = ARRAY_SIZE(pwm3_pins[1]),
2528 .modemuxs = pwm3_pin_12_modemux,
2529 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2530 }, {
2531 .name = "pwm3_pin_28_grp",
2532 .pins = pwm3_pins[2],
2533 .npins = ARRAY_SIZE(pwm3_pins[2]),
2534 .modemuxs = pwm3_pin_28_modemux,
2535 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2536 }, {
2537 .name = "pwm3_pin_40_grp",
2538 .pins = pwm3_pins[3],
2539 .npins = ARRAY_SIZE(pwm3_pins[3]),
2540 .modemuxs = pwm3_pin_40_modemux,
2541 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2542 }, {
2543 .name = "pwm3_pin_57_grp",
2544 .pins = pwm3_pins[4],
2545 .npins = ARRAY_SIZE(pwm3_pins[4]),
2546 .modemuxs = pwm3_pin_57_modemux,
2547 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2548 }, {
2549 .name = "pwm3_pin_86_grp",
2550 .pins = pwm3_pins[5],
2551 .npins = ARRAY_SIZE(pwm3_pins[5]),
2552 .modemuxs = pwm3_pin_86_modemux,
2553 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2554 },
2555};
2556
2557static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2558 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2559 "pwm3_pin_86_grp" };
2560static struct spear_function pwm3_function = {
2561 .name = "pwm3",
2562 .groups = pwm3_grps,
2563 .ngroups = ARRAY_SIZE(pwm3_grps),
2564};
2565
2566/* Pad multiplexing for SSP1 device */
2567static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2568 { 65, 68 }, { 94, 97 } };
2569static struct spear_muxreg ssp1_muxreg[] = {
2570 {
2571 .reg = PMX_CONFIG_REG,
2572 .mask = PMX_MII_MASK,
2573 .val = 0,
2574 },
2575};
2576
2577static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2578 {
2579 .reg = IP_SEL_PAD_10_19_REG,
2580 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2581 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2582 }, {
2583 .reg = IP_SEL_PAD_20_29_REG,
2584 .mask = PMX_PL_20_MASK,
2585 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2586 }, {
2587 .reg = IP_SEL_MIX_PAD_REG,
2588 .mask = PMX_SSP1_PORT_SEL_MASK,
2589 .val = PMX_SSP1_PORT_17_TO_20_VAL,
2590 },
2591};
2592
2593static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2594 {
2595 .reg = PMX_CONFIG_REG,
2596 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2597 .val = 0,
2598 }, {
2599 .reg = IP_SEL_PAD_30_39_REG,
2600 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2601 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2602 PMX_SSP1_PL_39_VAL,
2603 }, {
2604 .reg = IP_SEL_MIX_PAD_REG,
2605 .mask = PMX_SSP1_PORT_SEL_MASK,
2606 .val = PMX_SSP1_PORT_36_TO_39_VAL,
2607 },
2608};
2609
2610static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2611 {
2612 .reg = PMX_CONFIG_REG,
2613 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2614 .val = 0,
2615 }, {
2616 .reg = IP_SEL_PAD_40_49_REG,
2617 .mask = PMX_PL_48_49_MASK,
2618 .val = PMX_SSP1_PL_48_49_VAL,
2619 }, {
2620 .reg = IP_SEL_PAD_50_59_REG,
2621 .mask = PMX_PL_50_51_MASK,
2622 .val = PMX_SSP1_PL_50_51_VAL,
2623 }, {
2624 .reg = IP_SEL_MIX_PAD_REG,
2625 .mask = PMX_SSP1_PORT_SEL_MASK,
2626 .val = PMX_SSP1_PORT_48_TO_51_VAL,
2627 },
2628};
2629
2630static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2631 {
2632 .reg = IP_SEL_PAD_60_69_REG,
2633 .mask = PMX_PL_65_TO_68_MASK,
2634 .val = PMX_SSP1_PL_65_TO_68_VAL,
2635 }, {
2636 .reg = IP_SEL_MIX_PAD_REG,
2637 .mask = PMX_SSP1_PORT_SEL_MASK,
2638 .val = PMX_SSP1_PORT_65_TO_68_VAL,
2639 },
2640};
2641
2642static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2643 {
2644 .reg = IP_SEL_PAD_90_99_REG,
2645 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2646 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2647 }, {
2648 .reg = IP_SEL_MIX_PAD_REG,
2649 .mask = PMX_SSP1_PORT_SEL_MASK,
2650 .val = PMX_SSP1_PORT_94_TO_97_VAL,
2651 },
2652};
2653
2654static struct spear_modemux ssp1_17_20_modemux[] = {
2655 {
2656 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2657 EXTENDED_MODE,
2658 .muxregs = ssp1_muxreg,
2659 .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2660 }, {
2661 .modes = EXTENDED_MODE,
2662 .muxregs = ssp1_ext_17_20_muxreg,
2663 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2664 },
2665};
2666
2667static struct spear_modemux ssp1_36_39_modemux[] = {
2668 {
2669 .modes = EXTENDED_MODE,
2670 .muxregs = ssp1_ext_36_39_muxreg,
2671 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2672 },
2673};
2674
2675static struct spear_modemux ssp1_48_51_modemux[] = {
2676 {
2677 .modes = EXTENDED_MODE,
2678 .muxregs = ssp1_ext_48_51_muxreg,
2679 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2680 },
2681};
2682static struct spear_modemux ssp1_65_68_modemux[] = {
2683 {
2684 .modes = EXTENDED_MODE,
2685 .muxregs = ssp1_ext_65_68_muxreg,
2686 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2687 },
2688};
2689
2690static struct spear_modemux ssp1_94_97_modemux[] = {
2691 {
2692 .modes = EXTENDED_MODE,
2693 .muxregs = ssp1_ext_94_97_muxreg,
2694 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2695 },
2696};
2697
2698static struct spear_pingroup ssp1_pingroup[] = {
2699 {
2700 .name = "ssp1_17_20_grp",
2701 .pins = ssp1_pins[0],
2702 .npins = ARRAY_SIZE(ssp1_pins[0]),
2703 .modemuxs = ssp1_17_20_modemux,
2704 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2705 }, {
2706 .name = "ssp1_36_39_grp",
2707 .pins = ssp1_pins[1],
2708 .npins = ARRAY_SIZE(ssp1_pins[1]),
2709 .modemuxs = ssp1_36_39_modemux,
2710 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2711 }, {
2712 .name = "ssp1_48_51_grp",
2713 .pins = ssp1_pins[2],
2714 .npins = ARRAY_SIZE(ssp1_pins[2]),
2715 .modemuxs = ssp1_48_51_modemux,
2716 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2717 }, {
2718 .name = "ssp1_65_68_grp",
2719 .pins = ssp1_pins[3],
2720 .npins = ARRAY_SIZE(ssp1_pins[3]),
2721 .modemuxs = ssp1_65_68_modemux,
2722 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2723 }, {
2724 .name = "ssp1_94_97_grp",
2725 .pins = ssp1_pins[4],
2726 .npins = ARRAY_SIZE(ssp1_pins[4]),
2727 .modemuxs = ssp1_94_97_modemux,
2728 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2729 },
2730};
2731
2732static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2733 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2734};
2735static struct spear_function ssp1_function = {
2736 .name = "ssp1",
2737 .groups = ssp1_grps,
2738 .ngroups = ARRAY_SIZE(ssp1_grps),
2739};
2740
2741/* Pad multiplexing for SSP2 device */
2742static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2743 { 61, 64 }, { 90, 93 } };
2744static struct spear_muxreg ssp2_muxreg[] = {
2745 {
2746 .reg = PMX_CONFIG_REG,
2747 .mask = PMX_MII_MASK,
2748 .val = 0,
2749 },
2750};
2751
2752static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2753 {
2754 .reg = IP_SEL_PAD_10_19_REG,
2755 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2756 .val = PMX_SSP2_PL_13_14_15_16_VAL,
2757 }, {
2758 .reg = IP_SEL_MIX_PAD_REG,
2759 .mask = PMX_SSP2_PORT_SEL_MASK,
2760 .val = PMX_SSP2_PORT_13_TO_16_VAL,
2761 },
2762};
2763
2764static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2765 {
2766 .reg = PMX_CONFIG_REG,
2767 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2768 PMX_GPIO_PIN5_MASK,
2769 .val = 0,
2770 }, {
2771 .reg = IP_SEL_PAD_30_39_REG,
2772 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2773 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2774 PMX_SSP2_PL_35_VAL,
2775 }, {
2776 .reg = IP_SEL_MIX_PAD_REG,
2777 .mask = PMX_SSP2_PORT_SEL_MASK,
2778 .val = PMX_SSP2_PORT_32_TO_35_VAL,
2779 },
2780};
2781
2782static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2783 {
2784 .reg = PMX_CONFIG_REG,
2785 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2786 .val = 0,
2787 }, {
2788 .reg = IP_SEL_PAD_40_49_REG,
2789 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2790 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2791 }, {
2792 .reg = IP_SEL_MIX_PAD_REG,
2793 .mask = PMX_SSP2_PORT_SEL_MASK,
2794 .val = PMX_SSP2_PORT_44_TO_47_VAL,
2795 },
2796};
2797
2798static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2799 {
2800 .reg = IP_SEL_PAD_60_69_REG,
2801 .mask = PMX_PL_61_TO_64_MASK,
2802 .val = PMX_SSP2_PL_61_TO_64_VAL,
2803 }, {
2804 .reg = IP_SEL_MIX_PAD_REG,
2805 .mask = PMX_SSP2_PORT_SEL_MASK,
2806 .val = PMX_SSP2_PORT_61_TO_64_VAL,
2807 },
2808};
2809
2810static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2811 {
2812 .reg = IP_SEL_PAD_90_99_REG,
2813 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2814 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2815 }, {
2816 .reg = IP_SEL_MIX_PAD_REG,
2817 .mask = PMX_SSP2_PORT_SEL_MASK,
2818 .val = PMX_SSP2_PORT_90_TO_93_VAL,
2819 },
2820};
2821
2822static struct spear_modemux ssp2_13_16_modemux[] = {
2823 {
2824 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2825 .muxregs = ssp2_muxreg,
2826 .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2827 }, {
2828 .modes = EXTENDED_MODE,
2829 .muxregs = ssp2_ext_13_16_muxreg,
2830 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2831 },
2832};
2833
2834static struct spear_modemux ssp2_32_35_modemux[] = {
2835 {
2836 .modes = EXTENDED_MODE,
2837 .muxregs = ssp2_ext_32_35_muxreg,
2838 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2839 },
2840};
2841
2842static struct spear_modemux ssp2_44_47_modemux[] = {
2843 {
2844 .modes = EXTENDED_MODE,
2845 .muxregs = ssp2_ext_44_47_muxreg,
2846 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2847 },
2848};
2849
2850static struct spear_modemux ssp2_61_64_modemux[] = {
2851 {
2852 .modes = EXTENDED_MODE,
2853 .muxregs = ssp2_ext_61_64_muxreg,
2854 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2855 },
2856};
2857
2858static struct spear_modemux ssp2_90_93_modemux[] = {
2859 {
2860 .modes = EXTENDED_MODE,
2861 .muxregs = ssp2_ext_90_93_muxreg,
2862 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2863 },
2864};
2865
2866static struct spear_pingroup ssp2_pingroup[] = {
2867 {
2868 .name = "ssp2_13_16_grp",
2869 .pins = ssp2_pins[0],
2870 .npins = ARRAY_SIZE(ssp2_pins[0]),
2871 .modemuxs = ssp2_13_16_modemux,
2872 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2873 }, {
2874 .name = "ssp2_32_35_grp",
2875 .pins = ssp2_pins[1],
2876 .npins = ARRAY_SIZE(ssp2_pins[1]),
2877 .modemuxs = ssp2_32_35_modemux,
2878 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2879 }, {
2880 .name = "ssp2_44_47_grp",
2881 .pins = ssp2_pins[2],
2882 .npins = ARRAY_SIZE(ssp2_pins[2]),
2883 .modemuxs = ssp2_44_47_modemux,
2884 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2885 }, {
2886 .name = "ssp2_61_64_grp",
2887 .pins = ssp2_pins[3],
2888 .npins = ARRAY_SIZE(ssp2_pins[3]),
2889 .modemuxs = ssp2_61_64_modemux,
2890 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2891 }, {
2892 .name = "ssp2_90_93_grp",
2893 .pins = ssp2_pins[4],
2894 .npins = ARRAY_SIZE(ssp2_pins[4]),
2895 .modemuxs = ssp2_90_93_modemux,
2896 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2897 },
2898};
2899
2900static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2901 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2902static struct spear_function ssp2_function = {
2903 .name = "ssp2",
2904 .groups = ssp2_grps,
2905 .ngroups = ARRAY_SIZE(ssp2_grps),
2906};
2907
2908/* Pad multiplexing for cadence mii2 as mii device */
2909static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2910 90, 91, 92, 93, 94, 95, 96, 97 };
2911static struct spear_muxreg mii2_muxreg[] = {
2912 {
2913 .reg = IP_SEL_PAD_80_89_REG,
2914 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2915 PMX_PL_88_89_MASK,
2916 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2917 PMX_MII2_PL_88_89_VAL,
2918 }, {
2919 .reg = IP_SEL_PAD_90_99_REG,
2920 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2921 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2922 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2923 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2924 }, {
2925 .reg = EXT_CTRL_REG,
2926 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2927 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2928 MII_MDIO_MASK,
2929 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2930 (MAC_MODE_MII << MAC1_MODE_SHIFT) |
2931 MII_MDIO_81_VAL,
2932 },
2933};
2934
2935static struct spear_modemux mii2_modemux[] = {
2936 {
2937 .modes = EXTENDED_MODE,
2938 .muxregs = mii2_muxreg,
2939 .nmuxregs = ARRAY_SIZE(mii2_muxreg),
2940 },
2941};
2942
2943static struct spear_pingroup mii2_pingroup = {
2944 .name = "mii2_grp",
2945 .pins = mii2_pins,
2946 .npins = ARRAY_SIZE(mii2_pins),
2947 .modemuxs = mii2_modemux,
2948 .nmodemuxs = ARRAY_SIZE(mii2_modemux),
2949};
2950
2951static const char *const mii2_grps[] = { "mii2_grp" };
2952static struct spear_function mii2_function = {
2953 .name = "mii2",
2954 .groups = mii2_grps,
2955 .ngroups = ARRAY_SIZE(mii2_grps),
2956};
2957
2958/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2959static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2960 21, 22, 23, 24, 25, 26, 27 };
2961static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2962static struct spear_muxreg mii0_1_muxreg[] = {
2963 {
2964 .reg = PMX_CONFIG_REG,
2965 .mask = PMX_MII_MASK,
2966 .val = 0,
2967 },
2968};
2969
2970static struct spear_muxreg smii0_1_ext_muxreg[] = {
2971 {
2972 .reg = IP_SEL_PAD_10_19_REG,
2973 .mask = PMX_PL_10_11_MASK,
2974 .val = PMX_SMII_PL_10_11_VAL,
2975 }, {
2976 .reg = IP_SEL_PAD_20_29_REG,
2977 .mask = PMX_PL_21_TO_27_MASK,
2978 .val = PMX_SMII_PL_21_TO_27_VAL,
2979 }, {
2980 .reg = EXT_CTRL_REG,
2981 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2982 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2983 MII_MDIO_MASK,
2984 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2985 | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2986 | MII_MDIO_10_11_VAL,
2987 },
2988};
2989
2990static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2991 {
2992 .reg = IP_SEL_PAD_10_19_REG,
2993 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2994 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2995 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
2996 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
2997 PMX_RMII_PL_19_VAL,
2998 }, {
2999 .reg = IP_SEL_PAD_20_29_REG,
3000 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3001 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3002 }, {
3003 .reg = EXT_CTRL_REG,
3004 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3005 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3006 MII_MDIO_MASK,
3007 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3008 | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3009 | MII_MDIO_10_11_VAL,
3010 },
3011};
3012
3013static struct spear_modemux mii0_1_modemux[][2] = {
3014 {
3015 /* configure as smii */
3016 {
3017 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3018 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3019 .muxregs = mii0_1_muxreg,
3020 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3021 }, {
3022 .modes = EXTENDED_MODE,
3023 .muxregs = smii0_1_ext_muxreg,
3024 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3025 },
3026 }, {
3027 /* configure as rmii */
3028 {
3029 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3030 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3031 .muxregs = mii0_1_muxreg,
3032 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3033 }, {
3034 .modes = EXTENDED_MODE,
3035 .muxregs = rmii0_1_ext_muxreg,
3036 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3037 },
3038 },
3039};
3040
3041static struct spear_pingroup mii0_1_pingroup[] = {
3042 {
3043 .name = "smii0_1_grp",
3044 .pins = smii0_1_pins,
3045 .npins = ARRAY_SIZE(smii0_1_pins),
3046 .modemuxs = mii0_1_modemux[0],
3047 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3048 }, {
3049 .name = "rmii0_1_grp",
3050 .pins = rmii0_1_pins,
3051 .npins = ARRAY_SIZE(rmii0_1_pins),
3052 .modemuxs = mii0_1_modemux[1],
3053 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3054 },
3055};
3056
3057static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3058static struct spear_function mii0_1_function = {
3059 .name = "mii0_1",
3060 .groups = mii0_1_grps,
3061 .ngroups = ARRAY_SIZE(mii0_1_grps),
3062};
3063
3064/* Pad multiplexing for i2c1 device */
3065static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3066static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3067 {
3068 .reg = PMX_CONFIG_REG,
3069 .mask = PMX_SSP_CS_MASK,
3070 .val = 0,
3071 }, {
3072 .reg = IP_SEL_PAD_0_9_REG,
3073 .mask = PMX_PL_8_9_MASK,
3074 .val = PMX_I2C1_PL_8_9_VAL,
3075 }, {
3076 .reg = IP_SEL_MIX_PAD_REG,
3077 .mask = PMX_I2C1_PORT_SEL_MASK,
3078 .val = PMX_I2C1_PORT_8_9_VAL,
3079 },
3080};
3081
3082static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3083 {
3084 .reg = IP_SEL_PAD_90_99_REG,
3085 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3086 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3087 }, {
3088 .reg = IP_SEL_MIX_PAD_REG,
3089 .mask = PMX_I2C1_PORT_SEL_MASK,
3090 .val = PMX_I2C1_PORT_98_99_VAL,
3091 },
3092};
3093
3094static struct spear_modemux i2c1_modemux[][1] = {
3095 {
3096 /* Select signals on pins 8-9 */
3097 {
3098 .modes = EXTENDED_MODE,
3099 .muxregs = i2c1_ext_8_9_muxreg,
3100 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3101 },
3102 }, {
3103 /* Select signals on pins 98-99 */
3104 {
3105 .modes = EXTENDED_MODE,
3106 .muxregs = i2c1_ext_98_99_muxreg,
3107 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3108 },
3109 },
3110};
3111
3112static struct spear_pingroup i2c1_pingroup[] = {
3113 {
3114 .name = "i2c1_8_9_grp",
3115 .pins = i2c1_pins[0],
3116 .npins = ARRAY_SIZE(i2c1_pins[0]),
3117 .modemuxs = i2c1_modemux[0],
3118 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3119 }, {
3120 .name = "i2c1_98_99_grp",
3121 .pins = i2c1_pins[1],
3122 .npins = ARRAY_SIZE(i2c1_pins[1]),
3123 .modemuxs = i2c1_modemux[1],
3124 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3125 },
3126};
3127
3128static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3129static struct spear_function i2c1_function = {
3130 .name = "i2c1",
3131 .groups = i2c1_grps,
3132 .ngroups = ARRAY_SIZE(i2c1_grps),
3133};
3134
3135/* Pad multiplexing for i2c2 device */
3136static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3137 { 75, 76 }, { 96, 97 } };
3138static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3139 {
3140 .reg = PMX_CONFIG_REG,
3141 .mask = PMX_FIRDA_MASK,
3142 .val = 0,
3143 }, {
3144 .reg = IP_SEL_PAD_0_9_REG,
3145 .mask = PMX_PL_0_1_MASK,
3146 .val = PMX_I2C2_PL_0_1_VAL,
3147 }, {
3148 .reg = IP_SEL_MIX_PAD_REG,
3149 .mask = PMX_I2C2_PORT_SEL_MASK,
3150 .val = PMX_I2C2_PORT_0_1_VAL,
3151 },
3152};
3153
3154static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3155 {
3156 .reg = PMX_CONFIG_REG,
3157 .mask = PMX_UART0_MASK,
3158 .val = 0,
3159 }, {
3160 .reg = IP_SEL_PAD_0_9_REG,
3161 .mask = PMX_PL_2_3_MASK,
3162 .val = PMX_I2C2_PL_2_3_VAL,
3163 }, {
3164 .reg = IP_SEL_MIX_PAD_REG,
3165 .mask = PMX_I2C2_PORT_SEL_MASK,
3166 .val = PMX_I2C2_PORT_2_3_VAL,
3167 },
3168};
3169
3170static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3171 {
3172 .reg = PMX_CONFIG_REG,
3173 .mask = PMX_MII_MASK,
3174 .val = 0,
3175 }, {
3176 .reg = IP_SEL_PAD_10_19_REG,
3177 .mask = PMX_PL_19_MASK,
3178 .val = PMX_I2C2_PL_19_VAL,
3179 }, {
3180 .reg = IP_SEL_PAD_20_29_REG,
3181 .mask = PMX_PL_20_MASK,
3182 .val = PMX_I2C2_PL_20_VAL,
3183 }, {
3184 .reg = IP_SEL_MIX_PAD_REG,
3185 .mask = PMX_I2C2_PORT_SEL_MASK,
3186 .val = PMX_I2C2_PORT_19_20_VAL,
3187 },
3188};
3189
3190static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3191 {
3192 .reg = IP_SEL_PAD_70_79_REG,
3193 .mask = PMX_PL_75_76_MASK,
3194 .val = PMX_I2C2_PL_75_76_VAL,
3195 }, {
3196 .reg = IP_SEL_MIX_PAD_REG,
3197 .mask = PMX_I2C2_PORT_SEL_MASK,
3198 .val = PMX_I2C2_PORT_75_76_VAL,
3199 },
3200};
3201
3202static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3203 {
3204 .reg = IP_SEL_PAD_90_99_REG,
3205 .mask = PMX_PL_96_97_MASK,
3206 .val = PMX_I2C2_PL_96_97_VAL,
3207 }, {
3208 .reg = IP_SEL_MIX_PAD_REG,
3209 .mask = PMX_I2C2_PORT_SEL_MASK,
3210 .val = PMX_I2C2_PORT_96_97_VAL,
3211 },
3212};
3213
3214static struct spear_modemux i2c2_modemux[][1] = {
3215 {
3216 /* Select signals on pins 0_1 */
3217 {
3218 .modes = EXTENDED_MODE,
3219 .muxregs = i2c2_ext_0_1_muxreg,
3220 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3221 },
3222 }, {
3223 /* Select signals on pins 2_3 */
3224 {
3225 .modes = EXTENDED_MODE,
3226 .muxregs = i2c2_ext_2_3_muxreg,
3227 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3228 },
3229 }, {
3230 /* Select signals on pins 19_20 */
3231 {
3232 .modes = EXTENDED_MODE,
3233 .muxregs = i2c2_ext_19_20_muxreg,
3234 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3235 },
3236 }, {
3237 /* Select signals on pins 75_76 */
3238 {
3239 .modes = EXTENDED_MODE,
3240 .muxregs = i2c2_ext_75_76_muxreg,
3241 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3242 },
3243 }, {
3244 /* Select signals on pins 96_97 */
3245 {
3246 .modes = EXTENDED_MODE,
3247 .muxregs = i2c2_ext_96_97_muxreg,
3248 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3249 },
3250 },
3251};
3252
3253static struct spear_pingroup i2c2_pingroup[] = {
3254 {
3255 .name = "i2c2_0_1_grp",
3256 .pins = i2c2_pins[0],
3257 .npins = ARRAY_SIZE(i2c2_pins[0]),
3258 .modemuxs = i2c2_modemux[0],
3259 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3260 }, {
3261 .name = "i2c2_2_3_grp",
3262 .pins = i2c2_pins[1],
3263 .npins = ARRAY_SIZE(i2c2_pins[1]),
3264 .modemuxs = i2c2_modemux[1],
3265 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3266 }, {
3267 .name = "i2c2_19_20_grp",
3268 .pins = i2c2_pins[2],
3269 .npins = ARRAY_SIZE(i2c2_pins[2]),
3270 .modemuxs = i2c2_modemux[2],
3271 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3272 }, {
3273 .name = "i2c2_75_76_grp",
3274 .pins = i2c2_pins[3],
3275 .npins = ARRAY_SIZE(i2c2_pins[3]),
3276 .modemuxs = i2c2_modemux[3],
3277 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3278 }, {
3279 .name = "i2c2_96_97_grp",
3280 .pins = i2c2_pins[4],
3281 .npins = ARRAY_SIZE(i2c2_pins[4]),
3282 .modemuxs = i2c2_modemux[4],
3283 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3284 },
3285};
3286
3287static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3288 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3289static struct spear_function i2c2_function = {
3290 .name = "i2c2",
3291 .groups = i2c2_grps,
3292 .ngroups = ARRAY_SIZE(i2c2_grps),
3293};
3294
3295/* pingroups */
3296static struct spear_pingroup *spear320_pingroups[] = {
3297 SPEAR3XX_COMMON_PINGROUPS,
3298 &clcd_pingroup,
3299 &emi_pingroup,
3300 &fsmc_8bit_pingroup,
3301 &fsmc_16bit_pingroup,
3302 &spp_pingroup,
3303 &sdhci_led_pingroup,
3304 &sdhci_pingroup[0],
3305 &sdhci_pingroup[1],
3306 &i2s_pingroup,
3307 &uart1_pingroup,
3308 &uart1_modem_pingroup[0],
3309 &uart1_modem_pingroup[1],
3310 &uart1_modem_pingroup[2],
3311 &uart1_modem_pingroup[3],
3312 &uart2_pingroup,
3313 &uart3_pingroup[0],
3314 &uart3_pingroup[1],
3315 &uart3_pingroup[2],
3316 &uart3_pingroup[3],
3317 &uart3_pingroup[4],
3318 &uart3_pingroup[5],
3319 &uart3_pingroup[6],
3320 &uart4_pingroup[0],
3321 &uart4_pingroup[1],
3322 &uart4_pingroup[2],
3323 &uart4_pingroup[3],
3324 &uart4_pingroup[4],
3325 &uart4_pingroup[5],
3326 &uart5_pingroup[0],
3327 &uart5_pingroup[1],
3328 &uart5_pingroup[2],
3329 &uart5_pingroup[3],
3330 &uart6_pingroup[0],
3331 &uart6_pingroup[1],
3332 &rs485_pingroup,
3333 &touchscreen_pingroup,
3334 &can0_pingroup,
3335 &can1_pingroup,
3336 &pwm0_1_pingroup[0],
3337 &pwm0_1_pingroup[1],
3338 &pwm0_1_pingroup[2],
3339 &pwm0_1_pingroup[3],
3340 &pwm0_1_pingroup[4],
3341 &pwm0_1_pingroup[5],
3342 &pwm0_1_pingroup[6],
3343 &pwm2_pingroup[0],
3344 &pwm2_pingroup[1],
3345 &pwm2_pingroup[2],
3346 &pwm2_pingroup[3],
3347 &pwm2_pingroup[4],
3348 &pwm2_pingroup[5],
3349 &pwm2_pingroup[6],
3350 &pwm3_pingroup[0],
3351 &pwm3_pingroup[1],
3352 &pwm3_pingroup[2],
3353 &pwm3_pingroup[3],
3354 &pwm3_pingroup[4],
3355 &pwm3_pingroup[5],
3356 &ssp1_pingroup[0],
3357 &ssp1_pingroup[1],
3358 &ssp1_pingroup[2],
3359 &ssp1_pingroup[3],
3360 &ssp1_pingroup[4],
3361 &ssp2_pingroup[0],
3362 &ssp2_pingroup[1],
3363 &ssp2_pingroup[2],
3364 &ssp2_pingroup[3],
3365 &ssp2_pingroup[4],
3366 &mii2_pingroup,
3367 &mii0_1_pingroup[0],
3368 &mii0_1_pingroup[1],
3369 &i2c1_pingroup[0],
3370 &i2c1_pingroup[1],
3371 &i2c2_pingroup[0],
3372 &i2c2_pingroup[1],
3373 &i2c2_pingroup[2],
3374 &i2c2_pingroup[3],
3375 &i2c2_pingroup[4],
3376};
3377
3378/* functions */
3379static struct spear_function *spear320_functions[] = {
3380 SPEAR3XX_COMMON_FUNCTIONS,
3381 &clcd_function,
3382 &emi_function,
3383 &fsmc_function,
3384 &spp_function,
3385 &sdhci_function,
3386 &i2s_function,
3387 &uart1_function,
3388 &uart1_modem_function,
3389 &uart2_function,
3390 &uart3_function,
3391 &uart4_function,
3392 &uart5_function,
3393 &uart6_function,
3394 &rs485_function,
3395 &touchscreen_function,
3396 &can0_function,
3397 &can1_function,
3398 &pwm0_1_function,
3399 &pwm2_function,
3400 &pwm3_function,
3401 &ssp1_function,
3402 &ssp2_function,
3403 &mii2_function,
3404 &mii0_1_function,
3405 &i2c1_function,
3406 &i2c2_function,
3407};
3408
3409static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
3410 {
3411 .compatible = "st,spear320-pinmux",
3412 },
3413 {},
3414};
3415
3416static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3417{
3418 int ret;
3419
3420 spear3xx_machdata.groups = spear320_pingroups;
3421 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3422 spear3xx_machdata.functions = spear320_functions;
3423 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3424
3425 spear3xx_machdata.modes_supported = true;
3426 spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3427 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3428
3429 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3430
3431 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3432 if (ret)
3433 return ret;
3434
3435 return 0;
3436}
3437
3438static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
3439{
3440 return spear_pinctrl_remove(pdev);
3441}
3442
3443static struct platform_driver spear320_pinctrl_driver = {
3444 .driver = {
3445 .name = DRIVER_NAME,
3446 .owner = THIS_MODULE,
3447 .of_match_table = spear320_pinctrl_of_match,
3448 },
3449 .probe = spear320_pinctrl_probe,
3450 .remove = __devexit_p(spear320_pinctrl_remove),
3451};
3452
3453static int __init spear320_pinctrl_init(void)
3454{
3455 return platform_driver_register(&spear320_pinctrl_driver);
3456}
3457arch_initcall(spear320_pinctrl_init);
3458
3459static void __exit spear320_pinctrl_exit(void)
3460{
3461 platform_driver_unregister(&spear320_pinctrl_driver);
3462}
3463module_exit(spear320_pinctrl_exit);
3464
3465MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
3466MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3467MODULE_LICENSE("GPL v2");
3468MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644
index 00000000000..832049a8b1c
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,588 @@
1/*
2 * Driver for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/pinctrl/pinctrl.h>
13
14#include "pinctrl-spear3xx.h"
15
16/* pins */
17static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 PINCTRL_PIN(0, "PLGPIO0"),
19 PINCTRL_PIN(1, "PLGPIO1"),
20 PINCTRL_PIN(2, "PLGPIO2"),
21 PINCTRL_PIN(3, "PLGPIO3"),
22 PINCTRL_PIN(4, "PLGPIO4"),
23 PINCTRL_PIN(5, "PLGPIO5"),
24 PINCTRL_PIN(6, "PLGPIO6"),
25 PINCTRL_PIN(7, "PLGPIO7"),
26 PINCTRL_PIN(8, "PLGPIO8"),
27 PINCTRL_PIN(9, "PLGPIO9"),
28 PINCTRL_PIN(10, "PLGPIO10"),
29 PINCTRL_PIN(11, "PLGPIO11"),
30 PINCTRL_PIN(12, "PLGPIO12"),
31 PINCTRL_PIN(13, "PLGPIO13"),
32 PINCTRL_PIN(14, "PLGPIO14"),
33 PINCTRL_PIN(15, "PLGPIO15"),
34 PINCTRL_PIN(16, "PLGPIO16"),
35 PINCTRL_PIN(17, "PLGPIO17"),
36 PINCTRL_PIN(18, "PLGPIO18"),
37 PINCTRL_PIN(19, "PLGPIO19"),
38 PINCTRL_PIN(20, "PLGPIO20"),
39 PINCTRL_PIN(21, "PLGPIO21"),
40 PINCTRL_PIN(22, "PLGPIO22"),
41 PINCTRL_PIN(23, "PLGPIO23"),
42 PINCTRL_PIN(24, "PLGPIO24"),
43 PINCTRL_PIN(25, "PLGPIO25"),
44 PINCTRL_PIN(26, "PLGPIO26"),
45 PINCTRL_PIN(27, "PLGPIO27"),
46 PINCTRL_PIN(28, "PLGPIO28"),
47 PINCTRL_PIN(29, "PLGPIO29"),
48 PINCTRL_PIN(30, "PLGPIO30"),
49 PINCTRL_PIN(31, "PLGPIO31"),
50 PINCTRL_PIN(32, "PLGPIO32"),
51 PINCTRL_PIN(33, "PLGPIO33"),
52 PINCTRL_PIN(34, "PLGPIO34"),
53 PINCTRL_PIN(35, "PLGPIO35"),
54 PINCTRL_PIN(36, "PLGPIO36"),
55 PINCTRL_PIN(37, "PLGPIO37"),
56 PINCTRL_PIN(38, "PLGPIO38"),
57 PINCTRL_PIN(39, "PLGPIO39"),
58 PINCTRL_PIN(40, "PLGPIO40"),
59 PINCTRL_PIN(41, "PLGPIO41"),
60 PINCTRL_PIN(42, "PLGPIO42"),
61 PINCTRL_PIN(43, "PLGPIO43"),
62 PINCTRL_PIN(44, "PLGPIO44"),
63 PINCTRL_PIN(45, "PLGPIO45"),
64 PINCTRL_PIN(46, "PLGPIO46"),
65 PINCTRL_PIN(47, "PLGPIO47"),
66 PINCTRL_PIN(48, "PLGPIO48"),
67 PINCTRL_PIN(49, "PLGPIO49"),
68 PINCTRL_PIN(50, "PLGPIO50"),
69 PINCTRL_PIN(51, "PLGPIO51"),
70 PINCTRL_PIN(52, "PLGPIO52"),
71 PINCTRL_PIN(53, "PLGPIO53"),
72 PINCTRL_PIN(54, "PLGPIO54"),
73 PINCTRL_PIN(55, "PLGPIO55"),
74 PINCTRL_PIN(56, "PLGPIO56"),
75 PINCTRL_PIN(57, "PLGPIO57"),
76 PINCTRL_PIN(58, "PLGPIO58"),
77 PINCTRL_PIN(59, "PLGPIO59"),
78 PINCTRL_PIN(60, "PLGPIO60"),
79 PINCTRL_PIN(61, "PLGPIO61"),
80 PINCTRL_PIN(62, "PLGPIO62"),
81 PINCTRL_PIN(63, "PLGPIO63"),
82 PINCTRL_PIN(64, "PLGPIO64"),
83 PINCTRL_PIN(65, "PLGPIO65"),
84 PINCTRL_PIN(66, "PLGPIO66"),
85 PINCTRL_PIN(67, "PLGPIO67"),
86 PINCTRL_PIN(68, "PLGPIO68"),
87 PINCTRL_PIN(69, "PLGPIO69"),
88 PINCTRL_PIN(70, "PLGPIO70"),
89 PINCTRL_PIN(71, "PLGPIO71"),
90 PINCTRL_PIN(72, "PLGPIO72"),
91 PINCTRL_PIN(73, "PLGPIO73"),
92 PINCTRL_PIN(74, "PLGPIO74"),
93 PINCTRL_PIN(75, "PLGPIO75"),
94 PINCTRL_PIN(76, "PLGPIO76"),
95 PINCTRL_PIN(77, "PLGPIO77"),
96 PINCTRL_PIN(78, "PLGPIO78"),
97 PINCTRL_PIN(79, "PLGPIO79"),
98 PINCTRL_PIN(80, "PLGPIO80"),
99 PINCTRL_PIN(81, "PLGPIO81"),
100 PINCTRL_PIN(82, "PLGPIO82"),
101 PINCTRL_PIN(83, "PLGPIO83"),
102 PINCTRL_PIN(84, "PLGPIO84"),
103 PINCTRL_PIN(85, "PLGPIO85"),
104 PINCTRL_PIN(86, "PLGPIO86"),
105 PINCTRL_PIN(87, "PLGPIO87"),
106 PINCTRL_PIN(88, "PLGPIO88"),
107 PINCTRL_PIN(89, "PLGPIO89"),
108 PINCTRL_PIN(90, "PLGPIO90"),
109 PINCTRL_PIN(91, "PLGPIO91"),
110 PINCTRL_PIN(92, "PLGPIO92"),
111 PINCTRL_PIN(93, "PLGPIO93"),
112 PINCTRL_PIN(94, "PLGPIO94"),
113 PINCTRL_PIN(95, "PLGPIO95"),
114 PINCTRL_PIN(96, "PLGPIO96"),
115 PINCTRL_PIN(97, "PLGPIO97"),
116 PINCTRL_PIN(98, "PLGPIO98"),
117 PINCTRL_PIN(99, "PLGPIO99"),
118 PINCTRL_PIN(100, "PLGPIO100"),
119 PINCTRL_PIN(101, "PLGPIO101"),
120};
121
122/* firda_pins */
123static const unsigned firda_pins[] = { 0, 1 };
124static struct spear_muxreg firda_muxreg[] = {
125 {
126 .reg = -1,
127 .mask = PMX_FIRDA_MASK,
128 .val = PMX_FIRDA_MASK,
129 },
130};
131
132static struct spear_modemux firda_modemux[] = {
133 {
134 .modes = ~0,
135 .muxregs = firda_muxreg,
136 .nmuxregs = ARRAY_SIZE(firda_muxreg),
137 },
138};
139
140struct spear_pingroup spear3xx_firda_pingroup = {
141 .name = "firda_grp",
142 .pins = firda_pins,
143 .npins = ARRAY_SIZE(firda_pins),
144 .modemuxs = firda_modemux,
145 .nmodemuxs = ARRAY_SIZE(firda_modemux),
146};
147
148static const char *const firda_grps[] = { "firda_grp" };
149struct spear_function spear3xx_firda_function = {
150 .name = "firda",
151 .groups = firda_grps,
152 .ngroups = ARRAY_SIZE(firda_grps),
153};
154
155/* i2c_pins */
156static const unsigned i2c_pins[] = { 4, 5 };
157static struct spear_muxreg i2c_muxreg[] = {
158 {
159 .reg = -1,
160 .mask = PMX_I2C_MASK,
161 .val = PMX_I2C_MASK,
162 },
163};
164
165static struct spear_modemux i2c_modemux[] = {
166 {
167 .modes = ~0,
168 .muxregs = i2c_muxreg,
169 .nmuxregs = ARRAY_SIZE(i2c_muxreg),
170 },
171};
172
173struct spear_pingroup spear3xx_i2c_pingroup = {
174 .name = "i2c0_grp",
175 .pins = i2c_pins,
176 .npins = ARRAY_SIZE(i2c_pins),
177 .modemuxs = i2c_modemux,
178 .nmodemuxs = ARRAY_SIZE(i2c_modemux),
179};
180
181static const char *const i2c_grps[] = { "i2c0_grp" };
182struct spear_function spear3xx_i2c_function = {
183 .name = "i2c0",
184 .groups = i2c_grps,
185 .ngroups = ARRAY_SIZE(i2c_grps),
186};
187
188/* ssp_cs_pins */
189static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
190static struct spear_muxreg ssp_cs_muxreg[] = {
191 {
192 .reg = -1,
193 .mask = PMX_SSP_CS_MASK,
194 .val = PMX_SSP_CS_MASK,
195 },
196};
197
198static struct spear_modemux ssp_cs_modemux[] = {
199 {
200 .modes = ~0,
201 .muxregs = ssp_cs_muxreg,
202 .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
203 },
204};
205
206struct spear_pingroup spear3xx_ssp_cs_pingroup = {
207 .name = "ssp_cs_grp",
208 .pins = ssp_cs_pins,
209 .npins = ARRAY_SIZE(ssp_cs_pins),
210 .modemuxs = ssp_cs_modemux,
211 .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
212};
213
214static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
215struct spear_function spear3xx_ssp_cs_function = {
216 .name = "ssp_cs",
217 .groups = ssp_cs_grps,
218 .ngroups = ARRAY_SIZE(ssp_cs_grps),
219};
220
221/* ssp_pins */
222static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
223static struct spear_muxreg ssp_muxreg[] = {
224 {
225 .reg = -1,
226 .mask = PMX_SSP_MASK,
227 .val = PMX_SSP_MASK,
228 },
229};
230
231static struct spear_modemux ssp_modemux[] = {
232 {
233 .modes = ~0,
234 .muxregs = ssp_muxreg,
235 .nmuxregs = ARRAY_SIZE(ssp_muxreg),
236 },
237};
238
239struct spear_pingroup spear3xx_ssp_pingroup = {
240 .name = "ssp0_grp",
241 .pins = ssp_pins,
242 .npins = ARRAY_SIZE(ssp_pins),
243 .modemuxs = ssp_modemux,
244 .nmodemuxs = ARRAY_SIZE(ssp_modemux),
245};
246
247static const char *const ssp_grps[] = { "ssp0_grp" };
248struct spear_function spear3xx_ssp_function = {
249 .name = "ssp0",
250 .groups = ssp_grps,
251 .ngroups = ARRAY_SIZE(ssp_grps),
252};
253
254/* mii_pins */
255static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
256 21, 22, 23, 24, 25, 26, 27 };
257static struct spear_muxreg mii_muxreg[] = {
258 {
259 .reg = -1,
260 .mask = PMX_MII_MASK,
261 .val = PMX_MII_MASK,
262 },
263};
264
265static struct spear_modemux mii_modemux[] = {
266 {
267 .modes = ~0,
268 .muxregs = mii_muxreg,
269 .nmuxregs = ARRAY_SIZE(mii_muxreg),
270 },
271};
272
273struct spear_pingroup spear3xx_mii_pingroup = {
274 .name = "mii0_grp",
275 .pins = mii_pins,
276 .npins = ARRAY_SIZE(mii_pins),
277 .modemuxs = mii_modemux,
278 .nmodemuxs = ARRAY_SIZE(mii_modemux),
279};
280
281static const char *const mii_grps[] = { "mii0_grp" };
282struct spear_function spear3xx_mii_function = {
283 .name = "mii0",
284 .groups = mii_grps,
285 .ngroups = ARRAY_SIZE(mii_grps),
286};
287
288/* gpio0_pin0_pins */
289static const unsigned gpio0_pin0_pins[] = { 28 };
290static struct spear_muxreg gpio0_pin0_muxreg[] = {
291 {
292 .reg = -1,
293 .mask = PMX_GPIO_PIN0_MASK,
294 .val = PMX_GPIO_PIN0_MASK,
295 },
296};
297
298static struct spear_modemux gpio0_pin0_modemux[] = {
299 {
300 .modes = ~0,
301 .muxregs = gpio0_pin0_muxreg,
302 .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
303 },
304};
305
306struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
307 .name = "gpio0_pin0_grp",
308 .pins = gpio0_pin0_pins,
309 .npins = ARRAY_SIZE(gpio0_pin0_pins),
310 .modemuxs = gpio0_pin0_modemux,
311 .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
312};
313
314/* gpio0_pin1_pins */
315static const unsigned gpio0_pin1_pins[] = { 29 };
316static struct spear_muxreg gpio0_pin1_muxreg[] = {
317 {
318 .reg = -1,
319 .mask = PMX_GPIO_PIN1_MASK,
320 .val = PMX_GPIO_PIN1_MASK,
321 },
322};
323
324static struct spear_modemux gpio0_pin1_modemux[] = {
325 {
326 .modes = ~0,
327 .muxregs = gpio0_pin1_muxreg,
328 .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
329 },
330};
331
332struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
333 .name = "gpio0_pin1_grp",
334 .pins = gpio0_pin1_pins,
335 .npins = ARRAY_SIZE(gpio0_pin1_pins),
336 .modemuxs = gpio0_pin1_modemux,
337 .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
338};
339
340/* gpio0_pin2_pins */
341static const unsigned gpio0_pin2_pins[] = { 30 };
342static struct spear_muxreg gpio0_pin2_muxreg[] = {
343 {
344 .reg = -1,
345 .mask = PMX_GPIO_PIN2_MASK,
346 .val = PMX_GPIO_PIN2_MASK,
347 },
348};
349
350static struct spear_modemux gpio0_pin2_modemux[] = {
351 {
352 .modes = ~0,
353 .muxregs = gpio0_pin2_muxreg,
354 .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
355 },
356};
357
358struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
359 .name = "gpio0_pin2_grp",
360 .pins = gpio0_pin2_pins,
361 .npins = ARRAY_SIZE(gpio0_pin2_pins),
362 .modemuxs = gpio0_pin2_modemux,
363 .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
364};
365
366/* gpio0_pin3_pins */
367static const unsigned gpio0_pin3_pins[] = { 31 };
368static struct spear_muxreg gpio0_pin3_muxreg[] = {
369 {
370 .reg = -1,
371 .mask = PMX_GPIO_PIN3_MASK,
372 .val = PMX_GPIO_PIN3_MASK,
373 },
374};
375
376static struct spear_modemux gpio0_pin3_modemux[] = {
377 {
378 .modes = ~0,
379 .muxregs = gpio0_pin3_muxreg,
380 .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
381 },
382};
383
384struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
385 .name = "gpio0_pin3_grp",
386 .pins = gpio0_pin3_pins,
387 .npins = ARRAY_SIZE(gpio0_pin3_pins),
388 .modemuxs = gpio0_pin3_modemux,
389 .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
390};
391
392/* gpio0_pin4_pins */
393static const unsigned gpio0_pin4_pins[] = { 32 };
394static struct spear_muxreg gpio0_pin4_muxreg[] = {
395 {
396 .reg = -1,
397 .mask = PMX_GPIO_PIN4_MASK,
398 .val = PMX_GPIO_PIN4_MASK,
399 },
400};
401
402static struct spear_modemux gpio0_pin4_modemux[] = {
403 {
404 .modes = ~0,
405 .muxregs = gpio0_pin4_muxreg,
406 .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
407 },
408};
409
410struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
411 .name = "gpio0_pin4_grp",
412 .pins = gpio0_pin4_pins,
413 .npins = ARRAY_SIZE(gpio0_pin4_pins),
414 .modemuxs = gpio0_pin4_modemux,
415 .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
416};
417
418/* gpio0_pin5_pins */
419static const unsigned gpio0_pin5_pins[] = { 33 };
420static struct spear_muxreg gpio0_pin5_muxreg[] = {
421 {
422 .reg = -1,
423 .mask = PMX_GPIO_PIN5_MASK,
424 .val = PMX_GPIO_PIN5_MASK,
425 },
426};
427
428static struct spear_modemux gpio0_pin5_modemux[] = {
429 {
430 .modes = ~0,
431 .muxregs = gpio0_pin5_muxreg,
432 .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
433 },
434};
435
436struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
437 .name = "gpio0_pin5_grp",
438 .pins = gpio0_pin5_pins,
439 .npins = ARRAY_SIZE(gpio0_pin5_pins),
440 .modemuxs = gpio0_pin5_modemux,
441 .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
442};
443
444static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
445 "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
446};
447struct spear_function spear3xx_gpio0_function = {
448 .name = "gpio0",
449 .groups = gpio0_grps,
450 .ngroups = ARRAY_SIZE(gpio0_grps),
451};
452
453/* uart0_ext_pins */
454static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
455static struct spear_muxreg uart0_ext_muxreg[] = {
456 {
457 .reg = -1,
458 .mask = PMX_UART0_MODEM_MASK,
459 .val = PMX_UART0_MODEM_MASK,
460 },
461};
462
463static struct spear_modemux uart0_ext_modemux[] = {
464 {
465 .modes = ~0,
466 .muxregs = uart0_ext_muxreg,
467 .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
468 },
469};
470
471struct spear_pingroup spear3xx_uart0_ext_pingroup = {
472 .name = "uart0_ext_grp",
473 .pins = uart0_ext_pins,
474 .npins = ARRAY_SIZE(uart0_ext_pins),
475 .modemuxs = uart0_ext_modemux,
476 .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
477};
478
479static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
480struct spear_function spear3xx_uart0_ext_function = {
481 .name = "uart0_ext",
482 .groups = uart0_ext_grps,
483 .ngroups = ARRAY_SIZE(uart0_ext_grps),
484};
485
486/* uart0_pins */
487static const unsigned uart0_pins[] = { 2, 3 };
488static struct spear_muxreg uart0_muxreg[] = {
489 {
490 .reg = -1,
491 .mask = PMX_UART0_MASK,
492 .val = PMX_UART0_MASK,
493 },
494};
495
496static struct spear_modemux uart0_modemux[] = {
497 {
498 .modes = ~0,
499 .muxregs = uart0_muxreg,
500 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
501 },
502};
503
504struct spear_pingroup spear3xx_uart0_pingroup = {
505 .name = "uart0_grp",
506 .pins = uart0_pins,
507 .npins = ARRAY_SIZE(uart0_pins),
508 .modemuxs = uart0_modemux,
509 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
510};
511
512static const char *const uart0_grps[] = { "uart0_grp" };
513struct spear_function spear3xx_uart0_function = {
514 .name = "uart0",
515 .groups = uart0_grps,
516 .ngroups = ARRAY_SIZE(uart0_grps),
517};
518
519/* timer_0_1_pins */
520static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
521static struct spear_muxreg timer_0_1_muxreg[] = {
522 {
523 .reg = -1,
524 .mask = PMX_TIMER_0_1_MASK,
525 .val = PMX_TIMER_0_1_MASK,
526 },
527};
528
529static struct spear_modemux timer_0_1_modemux[] = {
530 {
531 .modes = ~0,
532 .muxregs = timer_0_1_muxreg,
533 .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
534 },
535};
536
537struct spear_pingroup spear3xx_timer_0_1_pingroup = {
538 .name = "timer_0_1_grp",
539 .pins = timer_0_1_pins,
540 .npins = ARRAY_SIZE(timer_0_1_pins),
541 .modemuxs = timer_0_1_modemux,
542 .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
543};
544
545static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
546struct spear_function spear3xx_timer_0_1_function = {
547 .name = "timer_0_1",
548 .groups = timer_0_1_grps,
549 .ngroups = ARRAY_SIZE(timer_0_1_grps),
550};
551
552/* timer_2_3_pins */
553static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
554static struct spear_muxreg timer_2_3_muxreg[] = {
555 {
556 .reg = -1,
557 .mask = PMX_TIMER_2_3_MASK,
558 .val = PMX_TIMER_2_3_MASK,
559 },
560};
561
562static struct spear_modemux timer_2_3_modemux[] = {
563 {
564 .modes = ~0,
565 .muxregs = timer_2_3_muxreg,
566 .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
567 },
568};
569
570struct spear_pingroup spear3xx_timer_2_3_pingroup = {
571 .name = "timer_2_3_grp",
572 .pins = timer_2_3_pins,
573 .npins = ARRAY_SIZE(timer_2_3_pins),
574 .modemuxs = timer_2_3_modemux,
575 .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
576};
577
578static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
579struct spear_function spear3xx_timer_2_3_function = {
580 .name = "timer_2_3",
581 .groups = timer_2_3_grps,
582 .ngroups = ARRAY_SIZE(timer_2_3_grps),
583};
584
585struct spear_pinctrl_machdata spear3xx_machdata = {
586 .pins = spear3xx_pins,
587 .npins = ARRAY_SIZE(spear3xx_pins),
588};
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644
index 00000000000..5d5fdd8df7b
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
1/*
2 * Header file for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR3XX_H__
13#define __PINMUX_SPEAR3XX_H__
14
15#include "pinctrl-spear.h"
16
17/* pad mux declarations */
18#define PMX_FIRDA_MASK (1 << 14)
19#define PMX_I2C_MASK (1 << 13)
20#define PMX_SSP_CS_MASK (1 << 12)
21#define PMX_SSP_MASK (1 << 11)
22#define PMX_MII_MASK (1 << 10)
23#define PMX_GPIO_PIN0_MASK (1 << 9)
24#define PMX_GPIO_PIN1_MASK (1 << 8)
25#define PMX_GPIO_PIN2_MASK (1 << 7)
26#define PMX_GPIO_PIN3_MASK (1 << 6)
27#define PMX_GPIO_PIN4_MASK (1 << 5)
28#define PMX_GPIO_PIN5_MASK (1 << 4)
29#define PMX_UART0_MODEM_MASK (1 << 3)
30#define PMX_UART0_MASK (1 << 2)
31#define PMX_TIMER_2_3_MASK (1 << 1)
32#define PMX_TIMER_0_1_MASK (1 << 0)
33
34extern struct spear_pingroup spear3xx_firda_pingroup;
35extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
36extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
37extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
38extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
39extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
40extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
41extern struct spear_pingroup spear3xx_i2c_pingroup;
42extern struct spear_pingroup spear3xx_mii_pingroup;
43extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
44extern struct spear_pingroup spear3xx_ssp_pingroup;
45extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
46extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
47extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
48extern struct spear_pingroup spear3xx_uart0_pingroup;
49
50#define SPEAR3XX_COMMON_PINGROUPS \
51 &spear3xx_firda_pingroup, \
52 &spear3xx_gpio0_pin0_pingroup, \
53 &spear3xx_gpio0_pin1_pingroup, \
54 &spear3xx_gpio0_pin2_pingroup, \
55 &spear3xx_gpio0_pin3_pingroup, \
56 &spear3xx_gpio0_pin4_pingroup, \
57 &spear3xx_gpio0_pin5_pingroup, \
58 &spear3xx_i2c_pingroup, \
59 &spear3xx_mii_pingroup, \
60 &spear3xx_ssp_cs_pingroup, \
61 &spear3xx_ssp_pingroup, \
62 &spear3xx_timer_0_1_pingroup, \
63 &spear3xx_timer_2_3_pingroup, \
64 &spear3xx_uart0_ext_pingroup, \
65 &spear3xx_uart0_pingroup
66
67extern struct spear_function spear3xx_firda_function;
68extern struct spear_function spear3xx_gpio0_function;
69extern struct spear_function spear3xx_i2c_function;
70extern struct spear_function spear3xx_mii_function;
71extern struct spear_function spear3xx_ssp_cs_function;
72extern struct spear_function spear3xx_ssp_function;
73extern struct spear_function spear3xx_timer_0_1_function;
74extern struct spear_function spear3xx_timer_2_3_function;
75extern struct spear_function spear3xx_uart0_ext_function;
76extern struct spear_function spear3xx_uart0_function;
77
78#define SPEAR3XX_COMMON_FUNCTIONS \
79 &spear3xx_firda_function, \
80 &spear3xx_gpio0_function, \
81 &spear3xx_i2c_function, \
82 &spear3xx_mii_function, \
83 &spear3xx_ssp_cs_function, \
84 &spear3xx_ssp_function, \
85 &spear3xx_timer_0_1_function, \
86 &spear3xx_timer_2_3_function, \
87 &spear3xx_uart0_ext_function, \
88 &spear3xx_uart0_function
89
90extern struct spear_pinctrl_machdata spear3xx_machdata;
91
92#endif /* __PINMUX_SPEAR3XX_H__ */
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 570f22053be..69c9a6601f4 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -37,6 +37,7 @@
37#include <linux/of.h> 37#include <linux/of.h>
38#include <linux/of_device.h> 38#include <linux/of_device.h>
39#include <linux/of_gpio.h> 39#include <linux/of_gpio.h>
40#include <linux/pinctrl/consumer.h>
40 41
41#include <mach/spi.h> 42#include <mach/spi.h>
42 43
@@ -758,6 +759,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
758 struct spi_master *master; 759 struct spi_master *master;
759 struct spi_imx_data *spi_imx; 760 struct spi_imx_data *spi_imx;
760 struct resource *res; 761 struct resource *res;
762 struct pinctrl *pinctrl;
761 int i, ret, num_cs; 763 int i, ret, num_cs;
762 764
763 if (!np && !mxc_platform_info) { 765 if (!np && !mxc_platform_info) {
@@ -845,6 +847,12 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
845 goto out_iounmap; 847 goto out_iounmap;
846 } 848 }
847 849
850 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
851 if (IS_ERR(pinctrl)) {
852 ret = PTR_ERR(pinctrl);
853 goto out_free_irq;
854 }
855
848 spi_imx->clk = clk_get(&pdev->dev, NULL); 856 spi_imx->clk = clk_get(&pdev->dev, NULL);
849 if (IS_ERR(spi_imx->clk)) { 857 if (IS_ERR(spi_imx->clk)) {
850 dev_err(&pdev->dev, "unable to get clock\n"); 858 dev_err(&pdev->dev, "unable to get clock\n");
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 3d569cd68f5..062ef8c2b3c 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,7 @@
52#include <linux/scatterlist.h> 52#include <linux/scatterlist.h>
53#include <linux/delay.h> 53#include <linux/delay.h>
54#include <linux/types.h> 54#include <linux/types.h>
55#include <linux/pinctrl/consumer.h>
55 56
56#include <asm/io.h> 57#include <asm/io.h>
57#include <asm/sizes.h> 58#include <asm/sizes.h>
@@ -1916,6 +1917,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1916{ 1917{
1917 struct uart_amba_port *uap; 1918 struct uart_amba_port *uap;
1918 struct vendor_data *vendor = id->data; 1919 struct vendor_data *vendor = id->data;
1920 struct pinctrl *pinctrl;
1919 void __iomem *base; 1921 void __iomem *base;
1920 int i, ret; 1922 int i, ret;
1921 1923
@@ -1940,6 +1942,12 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1940 goto free; 1942 goto free;
1941 } 1943 }
1942 1944
1945 pinctrl = devm_pinctrl_get_select_default(&dev->dev);
1946 if (IS_ERR(pinctrl)) {
1947 ret = PTR_ERR(pinctrl);
1948 goto unmap;
1949 }
1950
1943 uap->clk = clk_get(&dev->dev, NULL); 1951 uap->clk = clk_get(&dev->dev, NULL);
1944 if (IS_ERR(uap->clk)) { 1952 if (IS_ERR(uap->clk)) {
1945 ret = PTR_ERR(uap->clk); 1953 ret = PTR_ERR(uap->clk);
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index e7feceeebc2..ec206732f68 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -47,6 +47,7 @@
47#include <linux/slab.h> 47#include <linux/slab.h>
48#include <linux/of.h> 48#include <linux/of.h>
49#include <linux/of_device.h> 49#include <linux/of_device.h>
50#include <linux/pinctrl/consumer.h>
50 51
51#include <asm/io.h> 52#include <asm/io.h>
52#include <asm/irq.h> 53#include <asm/irq.h>
@@ -1464,6 +1465,7 @@ static int serial_imx_probe(struct platform_device *pdev)
1464 void __iomem *base; 1465 void __iomem *base;
1465 int ret = 0; 1466 int ret = 0;
1466 struct resource *res; 1467 struct resource *res;
1468 struct pinctrl *pinctrl;
1467 1469
1468 sport = kzalloc(sizeof(*sport), GFP_KERNEL); 1470 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1469 if (!sport) 1471 if (!sport)
@@ -1503,6 +1505,12 @@ static int serial_imx_probe(struct platform_device *pdev)
1503 sport->timer.function = imx_timeout; 1505 sport->timer.function = imx_timeout;
1504 sport->timer.data = (unsigned long)sport; 1506 sport->timer.data = (unsigned long)sport;
1505 1507
1508 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1509 if (IS_ERR(pinctrl)) {
1510 ret = PTR_ERR(pinctrl);
1511 goto unmap;
1512 }
1513
1506 sport->clk = clk_get(&pdev->dev, "uart"); 1514 sport->clk = clk_get(&pdev->dev, "uart");
1507 if (IS_ERR(sport->clk)) { 1515 if (IS_ERR(sport->clk)) {
1508 ret = PTR_ERR(sport->clk); 1516 ret = PTR_ERR(sport->clk);
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 55fd362b987..7081600bede 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -32,6 +32,7 @@
32#include <linux/clk.h> 32#include <linux/clk.h>
33#include <linux/delay.h> 33#include <linux/delay.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <linux/pinctrl/consumer.h>
35 36
36#include <asm/cacheflush.h> 37#include <asm/cacheflush.h>
37 38
@@ -678,6 +679,7 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev)
678 u32 version; 679 u32 version;
679 int ret = 0; 680 int ret = 0;
680 struct resource *r; 681 struct resource *r;
682 struct pinctrl *pinctrl;
681 683
682 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); 684 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
683 if (!s) { 685 if (!s) {
@@ -685,6 +687,12 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev)
685 goto out; 687 goto out;
686 } 688 }
687 689
690 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
691 if (IS_ERR(pinctrl)) {
692 ret = PTR_ERR(pinctrl);
693 goto out_free;
694 }
695
688 s->clk = clk_get(&pdev->dev, NULL); 696 s->clk = clk_get(&pdev->dev, NULL);
689 if (IS_ERR(s->clk)) { 697 if (IS_ERR(s->clk)) {
690 ret = PTR_ERR(s->clk); 698 ret = PTR_ERR(s->clk);
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index f214a80cdee..87e271b9c15 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -436,15 +436,16 @@ static const struct hc_driver tegra_ehci_hc_driver = {
436 .port_handed_over = ehci_port_handed_over, 436 .port_handed_over = ehci_port_handed_over,
437}; 437};
438 438
439static int setup_vbus_gpio(struct platform_device *pdev) 439static int setup_vbus_gpio(struct platform_device *pdev,
440 struct tegra_ehci_platform_data *pdata)
440{ 441{
441 int err = 0; 442 int err = 0;
442 int gpio; 443 int gpio;
443 444
444 if (!pdev->dev.of_node) 445 gpio = pdata->vbus_gpio;
445 return 0; 446 if (!gpio_is_valid(gpio))
446 447 gpio = of_get_named_gpio(pdev->dev.of_node,
447 gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); 448 "nvidia,vbus-gpio", 0);
448 if (!gpio_is_valid(gpio)) 449 if (!gpio_is_valid(gpio))
449 return 0; 450 return 0;
450 451
@@ -664,7 +665,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
664 if (!pdev->dev.dma_mask) 665 if (!pdev->dev.dma_mask)
665 pdev->dev.dma_mask = &tegra_ehci_dma_mask; 666 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
666 667
667 setup_vbus_gpio(pdev); 668 setup_vbus_gpio(pdev, pdata);
668 669
669 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); 670 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
670 if (!tegra) 671 if (!tegra)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 4a89f889852..6c6bc578d0f 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -45,6 +45,7 @@
45#include <linux/clk.h> 45#include <linux/clk.h>
46#include <linux/dma-mapping.h> 46#include <linux/dma-mapping.h>
47#include <linux/io.h> 47#include <linux/io.h>
48#include <linux/pinctrl/consumer.h>
48#include <mach/mxsfb.h> 49#include <mach/mxsfb.h>
49 50
50#define REG_SET 4 51#define REG_SET 4
@@ -756,6 +757,7 @@ static int __devinit mxsfb_probe(struct platform_device *pdev)
756 struct mxsfb_info *host; 757 struct mxsfb_info *host;
757 struct fb_info *fb_info; 758 struct fb_info *fb_info;
758 struct fb_modelist *modelist; 759 struct fb_modelist *modelist;
760 struct pinctrl *pinctrl;
759 int i, ret; 761 int i, ret;
760 762
761 if (!pdata) { 763 if (!pdata) {
@@ -793,6 +795,12 @@ static int __devinit mxsfb_probe(struct platform_device *pdev)
793 795
794 host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; 796 host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
795 797
798 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
799 if (IS_ERR(pinctrl)) {
800 ret = PTR_ERR(pinctrl);
801 goto error_getpin;
802 }
803
796 host->clk = clk_get(&host->pdev->dev, NULL); 804 host->clk = clk_get(&host->pdev->dev, NULL);
797 if (IS_ERR(host->clk)) { 805 if (IS_ERR(host->clk)) {
798 ret = PTR_ERR(host->clk); 806 ret = PTR_ERR(host->clk);
@@ -848,6 +856,7 @@ error_init_fb:
848error_pseudo_pallette: 856error_pseudo_pallette:
849 clk_put(host->clk); 857 clk_put(host->clk);
850error_getclock: 858error_getclock:
859error_getpin:
851 iounmap(host->base); 860 iounmap(host->base);
852error_ioremap: 861error_ioremap:
853 framebuffer_release(fb_info); 862 framebuffer_release(fb_info);
diff --git a/include/linux/pinctrl/pinctrl-state.h b/include/linux/pinctrl/pinctrl-state.h
index 3920e28b4da..634608dc6c8 100644
--- a/include/linux/pinctrl/pinctrl-state.h
+++ b/include/linux/pinctrl/pinctrl-state.h
@@ -2,5 +2,18 @@
2 * Standard pin control state definitions 2 * Standard pin control state definitions
3 */ 3 */
4 4
5/**
6 * @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put
7 * into as default, usually this means the pins are up and ready to
8 * be used by the device driver. This state is commonly used by
9 * hogs to configure muxing and pins at boot.
10 * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into
11 * when the pins are idle. Could typically be set from a
12 * pm_runtime_suspend() operation.
13 * @PINCTRL_STATE_SLEEP: the state the pinctrl handle shall be put into
14 * when the pins are sleeping. Could typically be set from a
15 * common suspend() function.
16 */
5#define PINCTRL_STATE_DEFAULT "default" 17#define PINCTRL_STATE_DEFAULT "default"
6#define PINCTRL_STATE_IDLE "idle" 18#define PINCTRL_STATE_IDLE "idle"
19#define PINCTRL_STATE_SLEEP "sleep"
diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h
index 6bca5b569ac..66c673fef40 100644
--- a/include/linux/platform_data/tegra_usb.h
+++ b/include/linux/platform_data/tegra_usb.h
@@ -26,6 +26,7 @@ struct tegra_ehci_platform_data {
26 /* power down the phy on bus suspend */ 26 /* power down the phy on bus suspend */
27 int power_down_on_bus_suspend; 27 int power_down_on_bus_suspend;
28 void *phy_config; 28 void *phy_config;
29 int vbus_gpio;
29}; 30};
30 31
31#endif /* _TEGRA_USB_H_ */ 32#endif /* _TEGRA_USB_H_ */
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 53f4fd8fece..7fd224bb732 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -25,6 +25,7 @@
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/time.h> 26#include <linux/time.h>
27#include <linux/fsl/mxs-dma.h> 27#include <linux/fsl/mxs-dma.h>
28#include <linux/pinctrl/consumer.h>
28#include <sound/core.h> 29#include <sound/core.h>
29#include <sound/pcm.h> 30#include <sound/pcm.h>
30#include <sound/pcm_params.h> 31#include <sound/pcm_params.h>
@@ -625,6 +626,7 @@ static int mxs_saif_probe(struct platform_device *pdev)
625 struct resource *iores, *dmares; 626 struct resource *iores, *dmares;
626 struct mxs_saif *saif; 627 struct mxs_saif *saif;
627 struct mxs_saif_platform_data *pdata; 628 struct mxs_saif_platform_data *pdata;
629 struct pinctrl *pinctrl;
628 int ret = 0; 630 int ret = 0;
629 631
630 if (pdev->id >= ARRAY_SIZE(mxs_saif)) 632 if (pdev->id >= ARRAY_SIZE(mxs_saif))
@@ -650,6 +652,12 @@ static int mxs_saif_probe(struct platform_device *pdev)
650 saif->master_id = saif->id; 652 saif->master_id = saif->id;
651 } 653 }
652 654
655 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
656 if (IS_ERR(pinctrl)) {
657 ret = PTR_ERR(pinctrl);
658 return ret;
659 }
660
653 saif->clk = clk_get(&pdev->dev, NULL); 661 saif->clk = clk_get(&pdev->dev, NULL);
654 if (IS_ERR(saif->clk)) { 662 if (IS_ERR(saif->clk)) {
655 ret = PTR_ERR(saif->clk); 663 ret = PTR_ERR(saif->clk);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 05:27:05 -0400