diff options
Diffstat (limited to 'arch/arm/mach-tegra/board-seaboard-pinmux.c')
-rw-r--r-- | arch/arm/mach-tegra/board-seaboard-pinmux.c | 346 |
1 files changed, 153 insertions, 193 deletions
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index 55e7e43a14a..11fc8a568c6 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2010,2011 NVIDIA Corporation | 2 | * Copyright (C) 2010-2012 NVIDIA Corporation |
3 | * Copyright (C) 2011 Google, Inc. | 3 | * Copyright (C) 2011 Google, Inc. |
4 | * | 4 | * |
5 | * This software is licensed under the terms of the GNU General Public | 5 | * This software is licensed under the terms of the GNU General Public |
@@ -14,216 +14,176 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/init.h> | ||
18 | #include <linux/gpio.h> | ||
19 | #include <linux/of.h> | ||
20 | 17 | ||
21 | #include <mach/pinmux.h> | ||
22 | #include <mach/pinmux-tegra20.h> | ||
23 | |||
24 | #include "gpio-names.h" | ||
25 | #include "board-pinmux.h" | ||
26 | #include "board-seaboard.h" | 18 | #include "board-seaboard.h" |
19 | #include "board-pinmux.h" | ||
27 | 20 | ||
28 | #define DEFAULT_DRIVE(_name) \ | 21 | static unsigned long seaboard_pincfg_drive_sdio1[] = { |
29 | { \ | 22 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0), |
30 | .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ | 23 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0), |
31 | .hsm = TEGRA_HSM_DISABLE, \ | 24 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3), |
32 | .schmitt = TEGRA_SCHMITT_ENABLE, \ | 25 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31), |
33 | .drive = TEGRA_DRIVE_DIV_1, \ | 26 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31), |
34 | .pull_down = TEGRA_PULL_31, \ | 27 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3), |
35 | .pull_up = TEGRA_PULL_31, \ | 28 | TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3), |
36 | .slew_rising = TEGRA_SLEW_SLOWEST, \ | ||
37 | .slew_falling = TEGRA_SLEW_SLOWEST, \ | ||
38 | } | ||
39 | |||
40 | static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = { | ||
41 | DEFAULT_DRIVE(SDIO1), | ||
42 | }; | ||
43 | |||
44 | static struct tegra_pingroup_config common_pinmux[] = { | ||
45 | {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
46 | {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
47 | {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
48 | {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
49 | {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
50 | {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
51 | {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
52 | {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | ||
53 | {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
54 | {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
55 | {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
56 | {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
57 | {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
58 | {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, | ||
59 | {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, | ||
60 | {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, | ||
61 | {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, | ||
62 | {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, | ||
63 | {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
64 | {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
65 | {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | ||
66 | {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
67 | {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
68 | {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
69 | {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
70 | {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
71 | {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
72 | {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
73 | {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
74 | {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
75 | {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
76 | {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
77 | {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
78 | {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
79 | {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
80 | {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
81 | {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
82 | {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
83 | {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
84 | {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
85 | {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
86 | {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
87 | {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
88 | {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
89 | {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
90 | {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
91 | {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
92 | {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
93 | {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
94 | {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
95 | {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
96 | {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
97 | {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
98 | {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
99 | {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
100 | {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
101 | {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
102 | {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
103 | {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
104 | {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
105 | {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
106 | {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
107 | {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
108 | {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
109 | {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
110 | {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
111 | {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
112 | {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
113 | {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
114 | {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
115 | {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
116 | {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
117 | {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
118 | {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
119 | {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
120 | {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
121 | {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
122 | {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
123 | {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | ||
124 | {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
125 | {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
126 | {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
127 | {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
128 | {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
129 | {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
130 | {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, | ||
131 | {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | ||
132 | {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
133 | {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
134 | {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
135 | {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
136 | {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
137 | {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
138 | {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
139 | {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
140 | {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
141 | {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
142 | {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
143 | {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
144 | {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
145 | {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
146 | {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
147 | {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
148 | }; | ||
149 | |||
150 | static struct tegra_pingroup_config seaboard_pinmux[] = { | ||
151 | {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
152 | {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
153 | {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
154 | {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
155 | {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
156 | {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
157 | {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
158 | {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
159 | {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
160 | {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
161 | {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | ||
162 | {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, | ||
163 | {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | ||
164 | }; | ||
165 | |||
166 | static struct tegra_pingroup_config ventana_pinmux[] = { | ||
167 | {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
168 | {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
169 | {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
170 | {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
171 | {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
172 | {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
173 | {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
174 | {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
175 | {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
176 | {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | ||
177 | {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
178 | {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
179 | {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | ||
180 | }; | 29 | }; |
181 | 30 | ||
182 | static struct tegra_gpio_table common_gpio_table[] = { | 31 | static struct pinctrl_map common_map[] = { |
183 | { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, | 32 | TEGRA_MAP_MUXCONF("ata", "ide", none, driven), |
184 | { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, | 33 | TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), |
185 | { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, | 34 | TEGRA_MAP_MUXCONF("atc", "nand", none, driven), |
186 | { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, | 35 | TEGRA_MAP_MUXCONF("atd", "gmi", none, driven), |
36 | TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate), | ||
37 | TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), | ||
38 | TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven), | ||
39 | TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate), | ||
40 | TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate), | ||
41 | TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), | ||
42 | TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven), | ||
43 | TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), | ||
44 | TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven), | ||
45 | TEGRA_MAP_MUXCONF("dta", "vi", down, driven), | ||
46 | TEGRA_MAP_MUXCONF("dtb", "vi", down, driven), | ||
47 | TEGRA_MAP_MUXCONF("dtc", "vi", down, driven), | ||
48 | TEGRA_MAP_MUXCONF("dtd", "vi", down, driven), | ||
49 | TEGRA_MAP_MUXCONF("dte", "vi", down, tristate), | ||
50 | TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven), | ||
51 | TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), | ||
52 | TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate), | ||
53 | TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven), | ||
54 | TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven), | ||
55 | TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven), | ||
56 | TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), | ||
57 | TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate), | ||
58 | TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate), | ||
59 | TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven), | ||
60 | TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven), | ||
61 | TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven), | ||
62 | TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven), | ||
63 | TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven), | ||
64 | TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven), | ||
65 | TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven), | ||
66 | TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven), | ||
67 | TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven), | ||
68 | TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate), | ||
69 | TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), | ||
70 | TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), | ||
71 | TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), | ||
72 | TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), | ||
73 | TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), | ||
74 | TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), | ||
75 | TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), | ||
76 | TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), | ||
77 | TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), | ||
78 | TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), | ||
79 | TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), | ||
80 | TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), | ||
81 | TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), | ||
82 | TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), | ||
83 | TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), | ||
84 | TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), | ||
85 | TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), | ||
86 | TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), | ||
87 | TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate), | ||
88 | TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), | ||
89 | TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven), | ||
90 | TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven), | ||
91 | TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven), | ||
92 | TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), | ||
93 | TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven), | ||
94 | TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate), | ||
95 | TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven), | ||
96 | TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate), | ||
97 | TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), | ||
98 | TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate), | ||
99 | TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), | ||
100 | TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate), | ||
101 | TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven), | ||
102 | TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), | ||
103 | TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate), | ||
104 | TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven), | ||
105 | TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven), | ||
106 | TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven), | ||
107 | TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven), | ||
108 | TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven), | ||
109 | TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven), | ||
110 | TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven), | ||
111 | TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate), | ||
112 | TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven), | ||
113 | TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), | ||
114 | TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven), | ||
115 | TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven), | ||
116 | TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate), | ||
117 | TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate), | ||
118 | TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate), | ||
119 | TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate), | ||
120 | TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), | ||
121 | TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven), | ||
122 | TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven), | ||
123 | TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven), | ||
124 | TEGRA_MAP_MUXCONF("uad", "irda", none, driven), | ||
125 | TEGRA_MAP_MUXCONF("uca", "uartc", none, driven), | ||
126 | TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven), | ||
127 | TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven), | ||
128 | TEGRA_MAP_CONF("ck32", none, na), | ||
129 | TEGRA_MAP_CONF("ddrc", none, na), | ||
130 | TEGRA_MAP_CONF("pmca", none, na), | ||
131 | TEGRA_MAP_CONF("pmcb", none, na), | ||
132 | TEGRA_MAP_CONF("pmcc", none, na), | ||
133 | TEGRA_MAP_CONF("pmcd", none, na), | ||
134 | TEGRA_MAP_CONF("pmce", none, na), | ||
135 | TEGRA_MAP_CONF("xm2c", none, na), | ||
136 | TEGRA_MAP_CONF("xm2d", none, na), | ||
137 | TEGRA_MAP_CONF("ls", up, na), | ||
138 | TEGRA_MAP_CONF("lc", up, na), | ||
139 | TEGRA_MAP_CONF("ld17_0", down, na), | ||
140 | TEGRA_MAP_CONF("ld19_18", down, na), | ||
141 | TEGRA_MAP_CONF("ld21_20", down, na), | ||
142 | TEGRA_MAP_CONF("ld23_22", down, na), | ||
187 | }; | 143 | }; |
188 | 144 | ||
189 | static struct tegra_gpio_table seaboard_gpio_table[] = { | 145 | static struct pinctrl_map seaboard_map[] = { |
190 | { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, | 146 | TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate), |
191 | { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, | 147 | TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven), |
192 | { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, | 148 | TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven), |
193 | { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, | 149 | TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven), |
194 | { .gpio = TEGRA_GPIO_USB1, .enable = true }, | 150 | TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate), |
151 | TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate), | ||
152 | TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate), | ||
153 | TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate), | ||
154 | TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate), | ||
155 | TEGRA_MAP_MUXCONF("spic", "gmi", up, driven), | ||
156 | TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate), | ||
157 | PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1), | ||
195 | }; | 158 | }; |
196 | 159 | ||
197 | static struct tegra_gpio_table ventana_gpio_table[] = { | 160 | static struct pinctrl_map ventana_map[] = { |
198 | /* hp_det */ | 161 | TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven), |
199 | { .gpio = TEGRA_GPIO_PW2, .enable = true }, | 162 | TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate), |
200 | /* int_mic_en */ | 163 | TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven), |
201 | { .gpio = TEGRA_GPIO_PX0, .enable = true }, | 164 | TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven), |
202 | /* ext_mic_en */ | 165 | TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven), |
203 | { .gpio = TEGRA_GPIO_PX1, .enable = true }, | 166 | TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), |
167 | TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), | ||
168 | TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven), | ||
169 | TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate), | ||
170 | TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate), | ||
171 | TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate), | ||
204 | }; | 172 | }; |
205 | 173 | ||
206 | static struct tegra_board_pinmux_conf common_conf = { | 174 | static struct tegra_board_pinmux_conf common_conf = { |
207 | .pgs = common_pinmux, | 175 | .maps = common_map, |
208 | .pg_count = ARRAY_SIZE(common_pinmux), | 176 | .map_count = ARRAY_SIZE(common_map), |
209 | .gpios = common_gpio_table, | ||
210 | .gpio_count = ARRAY_SIZE(common_gpio_table), | ||
211 | }; | 177 | }; |
212 | 178 | ||
213 | static struct tegra_board_pinmux_conf seaboard_conf = { | 179 | static struct tegra_board_pinmux_conf seaboard_conf = { |
214 | .pgs = seaboard_pinmux, | 180 | .maps = seaboard_map, |
215 | .pg_count = ARRAY_SIZE(seaboard_pinmux), | 181 | .map_count = ARRAY_SIZE(seaboard_map), |
216 | .drives = seaboard_drive_pinmux, | ||
217 | .drive_count = ARRAY_SIZE(seaboard_drive_pinmux), | ||
218 | .gpios = seaboard_gpio_table, | ||
219 | .gpio_count = ARRAY_SIZE(seaboard_gpio_table), | ||
220 | }; | 182 | }; |
221 | 183 | ||
222 | static struct tegra_board_pinmux_conf ventana_conf = { | 184 | static struct tegra_board_pinmux_conf ventana_conf = { |
223 | .pgs = ventana_pinmux, | 185 | .maps = ventana_map, |
224 | .pg_count = ARRAY_SIZE(ventana_pinmux), | 186 | .map_count = ARRAY_SIZE(ventana_map), |
225 | .gpios = ventana_gpio_table, | ||
226 | .gpio_count = ARRAY_SIZE(ventana_gpio_table), | ||
227 | }; | 187 | }; |
228 | 188 | ||
229 | void seaboard_pinmux_init(void) | 189 | void seaboard_pinmux_init(void) |