aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorGreg Kroah-Hartman <gregkh@suse.de>2009-09-19 13:50:02 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-10-09 16:47:23 -0400
commit7d230df37a7c08f01e57e1623e0706b3949751a2 (patch)
tree9e621ce8908c502c52df59808a62ede7848c243d
parent029214841ba8a1fae48a4a108d138b302d8a1afb (diff)
Staging: remove agnx driver
The agnx driver in the staging tree is broken, does not work, and development is dead. The developers have asked for it to be removed so it now is. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/agnx/Kconfig5
-rw-r--r--drivers/staging/agnx/Makefile8
-rw-r--r--drivers/staging/agnx/TODO22
-rw-r--r--drivers/staging/agnx/agnx.h156
-rw-r--r--drivers/staging/agnx/debug.h416
-rw-r--r--drivers/staging/agnx/pci.c635
-rw-r--r--drivers/staging/agnx/phy.c960
-rw-r--r--drivers/staging/agnx/phy.h409
-rw-r--r--drivers/staging/agnx/rf.c893
-rw-r--r--drivers/staging/agnx/sta.c218
-rw-r--r--drivers/staging/agnx/sta.h222
-rw-r--r--drivers/staging/agnx/table.c168
-rw-r--r--drivers/staging/agnx/table.h10
-rw-r--r--drivers/staging/agnx/xmit.c836
-rw-r--r--drivers/staging/agnx/xmit.h250
17 files changed, 0 insertions, 5211 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 9a4dd5992f6..ab64971d3fe 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -59,8 +59,6 @@ source "drivers/staging/echo/Kconfig"
59 59
60source "drivers/staging/poch/Kconfig" 60source "drivers/staging/poch/Kconfig"
61 61
62source "drivers/staging/agnx/Kconfig"
63
64source "drivers/staging/otus/Kconfig" 62source "drivers/staging/otus/Kconfig"
65 63
66source "drivers/staging/rt2860/Kconfig" 64source "drivers/staging/rt2860/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 104f2f8897e..baffd0e9647 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_W35UND) += winbond/
12obj-$(CONFIG_PRISM2_USB) += wlan-ng/ 12obj-$(CONFIG_PRISM2_USB) += wlan-ng/
13obj-$(CONFIG_ECHO) += echo/ 13obj-$(CONFIG_ECHO) += echo/
14obj-$(CONFIG_POCH) += poch/ 14obj-$(CONFIG_POCH) += poch/
15obj-$(CONFIG_AGNX) += agnx/
16obj-$(CONFIG_OTUS) += otus/ 15obj-$(CONFIG_OTUS) += otus/
17obj-$(CONFIG_RT2860) += rt2860/ 16obj-$(CONFIG_RT2860) += rt2860/
18obj-$(CONFIG_RT2870) += rt2870/ 17obj-$(CONFIG_RT2870) += rt2870/
diff --git a/drivers/staging/agnx/Kconfig b/drivers/staging/agnx/Kconfig
deleted file mode 100644
index 7f43549e36d..00000000000
--- a/drivers/staging/agnx/Kconfig
+++ /dev/null
@@ -1,5 +0,0 @@
1config AGNX
2 tristate "Wireless Airgo AGNX support"
3 depends on WLAN_80211 && MAC80211
4 ---help---
5 This is an experimental driver for Airgo AGNX00 wireless chip.
diff --git a/drivers/staging/agnx/Makefile b/drivers/staging/agnx/Makefile
deleted file mode 100644
index 1216564a312..00000000000
--- a/drivers/staging/agnx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1obj-$(CONFIG_AGNX) += agnx.o
2
3agnx-objs := rf.o \
4 pci.o \
5 xmit.o \
6 table.o \
7 sta.o \
8 phy.o
diff --git a/drivers/staging/agnx/TODO b/drivers/staging/agnx/TODO
deleted file mode 100644
index 89bec74318a..00000000000
--- a/drivers/staging/agnx/TODO
+++ /dev/null
@@ -1,22 +0,0 @@
12008 7/18
2
3The RX has can't receive OFDM packet correctly,
4Guess it need be do RX calibrate.
5
6
7before 2008 3/1
8
91: The RX get too much "CRC failed" pakets, it make the card work very unstable,
102: After running a while, the card will get infinity "RX Frame" and "Error"
11interrupt, not know the root reason so far, try to fix it
123: Using two tx queue txd and txm but not only txm.
134: Set the hdr correctly.
145: Try to do recalibrate correvtly
156: To support G mode in future
167: Fix the mac address can't be readed and set correctly in BE machine.
178: Fix include and exclude FCS in promisous mode and manage mode
189: Using sta_notify to notice sta change
1910: Turn on frame reception at the end of start
2011: Guess the card support HW_MULTICAST_FILTER
2112: The tx process should be implment atomic?
2213: Using mac80211 function to control the TX&RX LED.
diff --git a/drivers/staging/agnx/agnx.h b/drivers/staging/agnx/agnx.h
deleted file mode 100644
index 3963d2597a1..00000000000
--- a/drivers/staging/agnx/agnx.h
+++ /dev/null
@@ -1,156 +0,0 @@
1#ifndef AGNX_H_
2#define AGNX_H_
3
4#include <linux/io.h>
5
6#include "xmit.h"
7
8#define PFX KBUILD_MODNAME ": "
9
10static inline u32 agnx_read32(void __iomem *mem_region, u32 offset)
11{
12 return ioread32(mem_region + offset);
13}
14
15static inline void agnx_write32(void __iomem *mem_region, u32 offset, u32 val)
16{
17 iowrite32(val, mem_region + offset);
18}
19
20/* static const struct ieee80211_rate agnx_rates_80211b[] = { */
21/* { .rate = 10, */
22/* .val = 0xa, */
23/* .flags = IEEE80211_RATE_CCK }, */
24/* { .rate = 20, */
25/* .val = 0x14, */
26/* .hw_value = -0x14, */
27/* .flags = IEEE80211_RATE_CCK_2 }, */
28/* { .rate = 55, */
29/* .val = 0x37, */
30/* .val2 = -0x37, */
31/* .flags = IEEE80211_RATE_CCK_2 }, */
32/* { .rate = 110, */
33/* .val = 0x6e, */
34/* .val2 = -0x6e, */
35/* .flags = IEEE80211_RATE_CCK_2 } */
36/* }; */
37
38
39static const struct ieee80211_rate agnx_rates_80211g[] = {
40/* { .bitrate = 10, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
41/* { .bitrate = 20, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
42/* { .bitrate = 55, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
43/* { .bitrate = 110, .hw_value = 4, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
44 { .bitrate = 10, .hw_value = 1, },
45 { .bitrate = 20, .hw_value = 2, },
46 { .bitrate = 55, .hw_value = 3, },
47 { .bitrate = 110, .hw_value = 4,},
48
49 { .bitrate = 60, .hw_value = 0xB, },
50 { .bitrate = 90, .hw_value = 0xF, },
51 { .bitrate = 120, .hw_value = 0xA },
52 { .bitrate = 180, .hw_value = 0xE, },
53/* { .bitrate = 240, .hw_value = 0xd, }, */
54 { .bitrate = 360, .hw_value = 0xD, },
55 { .bitrate = 480, .hw_value = 0x8, },
56 { .bitrate = 540, .hw_value = 0xC, },
57};
58
59static const struct ieee80211_channel agnx_channels[] = {
60 { .center_freq = 2412, .hw_value = 1, },
61 { .center_freq = 2417, .hw_value = 2, },
62 { .center_freq = 2422, .hw_value = 3, },
63 { .center_freq = 2427, .hw_value = 4, },
64 { .center_freq = 2432, .hw_value = 5, },
65 { .center_freq = 2437, .hw_value = 6, },
66 { .center_freq = 2442, .hw_value = 7, },
67 { .center_freq = 2447, .hw_value = 8, },
68 { .center_freq = 2452, .hw_value = 9, },
69 { .center_freq = 2457, .hw_value = 10, },
70 { .center_freq = 2462, .hw_value = 11, },
71 { .center_freq = 2467, .hw_value = 12, },
72 { .center_freq = 2472, .hw_value = 13, },
73 { .center_freq = 2484, .hw_value = 14, },
74};
75
76#define NUM_DRIVE_MODES 2
77/* Agnx operate mode */
78enum {
79 AGNX_MODE_80211A,
80 AGNX_MODE_80211A_OOB,
81 AGNX_MODE_80211A_MIMO,
82 AGNX_MODE_80211B_SHORT,
83 AGNX_MODE_80211B_LONG,
84 AGNX_MODE_80211G,
85 AGNX_MODE_80211G_OOB,
86 AGNX_MODE_80211G_MIMO,
87};
88
89enum {
90 AGNX_UNINIT,
91 AGNX_START,
92 AGNX_STOP,
93};
94
95struct agnx_priv {
96 struct pci_dev *pdev;
97 struct ieee80211_hw *hw;
98
99 spinlock_t lock;
100 struct mutex mutex;
101 unsigned int init_status;
102
103 void __iomem *ctl; /* pointer to base ram address */
104 void __iomem *data; /* pointer to mem region #2 */
105
106 struct agnx_ring rx;
107 struct agnx_ring txm;
108 struct agnx_ring txd;
109
110 /* Need volatile? */
111 u32 irq_status;
112
113 struct delayed_work periodic_work; /* Periodic tasks like recalibrate */
114 struct ieee80211_low_level_stats stats;
115
116 /* unsigned int phymode; */
117 int mode;
118 int channel;
119 u8 bssid[ETH_ALEN];
120
121 u8 mac_addr[ETH_ALEN];
122 u8 revid;
123
124 struct ieee80211_supported_band band;
125};
126
127
128#define AGNX_CHAINS_MAX 6
129#define AGNX_PERIODIC_DELAY 60000 /* unit: ms */
130#define LOCAL_STAID 0 /* the station entry for the card itself */
131#define BSSID_STAID 1 /* the station entry for the bsssid AP */
132#define spi_delay() udelay(40)
133#define eeprom_delay() udelay(40)
134#define routing_table_delay() udelay(50)
135
136/* PDU pool MEM region #2 */
137#define AGNX_PDUPOOL 0x40000 /* PDU pool */
138#define AGNX_PDUPOOL_SIZE 0x8000 /* PDU pool size*/
139#define AGNX_PDU_TX_WQ 0x41000 /* PDU list TX workqueue */
140#define AGNX_PDU_FREE 0x41800 /* Free Pool */
141#define PDU_SIZE 0x80 /* Free Pool node size */
142#define PDU_FREE_CNT 0xd0 /* Free pool node count */
143
144
145/* RF stuffs */
146extern void rf_chips_init(struct agnx_priv *priv);
147extern void spi_rc_write(void __iomem *mem_region, u32 chip_ids, u32 sw);
148extern void calibrate_oscillator(struct agnx_priv *priv);
149extern void do_calibration(struct agnx_priv *priv);
150extern void antenna_calibrate(struct agnx_priv *priv);
151extern void __antenna_calibrate(struct agnx_priv *priv);
152extern void print_offsets(struct agnx_priv *priv);
153extern int agnx_set_channel(struct agnx_priv *priv, unsigned int channel);
154
155
156#endif /* AGNX_H_ */
diff --git a/drivers/staging/agnx/debug.h b/drivers/staging/agnx/debug.h
deleted file mode 100644
index 7947f327a21..00000000000
--- a/drivers/staging/agnx/debug.h
+++ /dev/null
@@ -1,416 +0,0 @@
1#ifndef AGNX_DEBUG_H_
2#define AGNX_DEBUG_H_
3
4#include "agnx.h"
5#include "phy.h"
6#include "sta.h"
7#include "xmit.h"
8
9#define AGNX_TRACE printk(KERN_ERR PFX "function:%s line:%d\n", __func__, __LINE__)
10
11#define PRINTK_LE16(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.4x\n", le16_to_cpu(var))
12#define PRINTK_LE32(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.8x\n", le32_to_cpu(var))
13#define PRINTK_U8(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.2x\n", var)
14#define PRINTK_BE16(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.4x\n", be16_to_cpu(var))
15#define PRINTK_BE32(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.8x\n", be32_to_cpu(var))
16#define PRINTK_BITS(prefix, field) printk(KERN_DEBUG PFX #prefix ": " #field ": 0x%x\n", (reg & field) >> field##_SHIFT)
17
18static inline void agnx_bug(char *reason)
19{
20 printk(KERN_ERR PFX "%s\n", reason);
21 BUG();
22}
23
24static inline void agnx_print_desc(struct agnx_desc *desc)
25{
26 u32 reg = be32_to_cpu(desc->frag);
27
28 PRINTK_BITS(DESC, PACKET_LEN);
29
30 if (reg & FIRST_FRAG) {
31 PRINTK_BITS(DESC, FIRST_PACKET_MASK);
32 PRINTK_BITS(DESC, FIRST_RESERV2);
33 PRINTK_BITS(DESC, FIRST_TKIP_ERROR);
34 PRINTK_BITS(DESC, FIRST_TKIP_PACKET);
35 PRINTK_BITS(DESC, FIRST_RESERV1);
36 PRINTK_BITS(DESC, FIRST_FRAG_LEN);
37 } else {
38 PRINTK_BITS(DESC, SUB_RESERV2);
39 PRINTK_BITS(DESC, SUB_TKIP_ERROR);
40 PRINTK_BITS(DESC, SUB_TKIP_PACKET);
41 PRINTK_BITS(DESC, SUB_RESERV1);
42 PRINTK_BITS(DESC, SUB_FRAG_LEN);
43 }
44
45 PRINTK_BITS(DESC, FIRST_FRAG);
46 PRINTK_BITS(DESC, LAST_FRAG);
47 PRINTK_BITS(DESC, OWNER);
48}
49
50
51static inline void dump_ieee80211b_phy_hdr(__be32 _11b0, __be32 _11b1)
52{
53
54}
55
56static inline void agnx_print_hdr(struct agnx_hdr *hdr)
57{
58 u32 reg;
59 int i;
60
61 reg = be32_to_cpu(hdr->reg0);
62 PRINTK_BITS(HDR, RTS);
63 PRINTK_BITS(HDR, MULTICAST);
64 PRINTK_BITS(HDR, ACK);
65 PRINTK_BITS(HDR, TM);
66 PRINTK_BITS(HDR, RELAY);
67 PRINTK_BITS(HDR, REVISED_FCS);
68 PRINTK_BITS(HDR, NEXT_BUFFER_ADDR);
69
70 reg = be32_to_cpu(hdr->reg1);
71 PRINTK_BITS(HDR, MAC_HDR_LEN);
72 PRINTK_BITS(HDR, DURATION_OVERIDE);
73 PRINTK_BITS(HDR, PHY_HDR_OVERIDE);
74 PRINTK_BITS(HDR, CRC_FAIL);
75 PRINTK_BITS(HDR, SEQUENCE_NUMBER);
76 PRINTK_BITS(HDR, BUFF_HEAD_ADDR);
77
78 reg = be32_to_cpu(hdr->reg2);
79 PRINTK_BITS(HDR, PDU_COUNT);
80 PRINTK_BITS(HDR, WEP_KEY);
81 PRINTK_BITS(HDR, USES_WEP_KEY);
82 PRINTK_BITS(HDR, KEEP_ALIVE);
83 PRINTK_BITS(HDR, BUFF_TAIL_ADDR);
84
85 reg = be32_to_cpu(hdr->reg3);
86 PRINTK_BITS(HDR, CTS_11G);
87 PRINTK_BITS(HDR, RTS_11G);
88 PRINTK_BITS(HDR, FRAG_SIZE);
89 PRINTK_BITS(HDR, PAYLOAD_LEN);
90 PRINTK_BITS(HDR, FRAG_NUM);
91
92 reg = be32_to_cpu(hdr->reg4);
93 PRINTK_BITS(HDR, RELAY_STAID);
94 PRINTK_BITS(HDR, STATION_ID);
95 PRINTK_BITS(HDR, WORKQUEUE_ID);
96
97 reg = be32_to_cpu(hdr->reg5);
98 /* printf the route flag */
99 PRINTK_BITS(HDR, ROUTE_HOST);
100 PRINTK_BITS(HDR, ROUTE_CARD_CPU);
101 PRINTK_BITS(HDR, ROUTE_ENCRYPTION);
102 PRINTK_BITS(HDR, ROUTE_TX);
103 PRINTK_BITS(HDR, ROUTE_RX1);
104 PRINTK_BITS(HDR, ROUTE_RX2);
105 PRINTK_BITS(HDR, ROUTE_COMPRESSION);
106
107 PRINTK_BE32(HDR, hdr->_11g0);
108 PRINTK_BE32(HDR, hdr->_11g1);
109 PRINTK_BE32(HDR, hdr->_11b0);
110 PRINTK_BE32(HDR, hdr->_11b1);
111
112 dump_ieee80211b_phy_hdr(hdr->_11b0, hdr->_11b1);
113
114 /* Fixme */
115 for (i = 0; i < ARRAY_SIZE(hdr->mac_hdr); i++) {
116 if (i == 0)
117 printk(KERN_DEBUG PFX "IEEE80211 HDR: ");
118 printk("%.2x ", hdr->mac_hdr[i]);
119 if (i + 1 == ARRAY_SIZE(hdr->mac_hdr))
120 printk("\n");
121 }
122
123 PRINTK_BE16(HDR, hdr->rts_duration);
124 PRINTK_BE16(HDR, hdr->last_duration);
125 PRINTK_BE16(HDR, hdr->sec_last_duration);
126 PRINTK_BE16(HDR, hdr->other_duration);
127 PRINTK_BE16(HDR, hdr->tx_other_duration);
128 PRINTK_BE16(HDR, hdr->last_11g_len);
129 PRINTK_BE16(HDR, hdr->other_11g_len);
130 PRINTK_BE16(HDR, hdr->last_11b_len);
131 PRINTK_BE16(HDR, hdr->other_11b_len);
132
133 /* FIXME */
134 reg = be16_to_cpu(hdr->reg6);
135 PRINTK_BITS(HDR, MBF);
136 PRINTK_BITS(HDR, RSVD4);
137
138 PRINTK_BE16(HDR, hdr->rx_frag_stat);
139
140 PRINTK_BE32(HDR, hdr->time_stamp);
141 PRINTK_BE32(HDR, hdr->phy_stats_hi);
142 PRINTK_BE32(HDR, hdr->phy_stats_lo);
143 PRINTK_BE32(HDR, hdr->mic_key0);
144 PRINTK_BE32(HDR, hdr->mic_key1);
145} /* agnx_print_hdr */
146
147
148static inline void agnx_print_rx_hdr(struct agnx_hdr *hdr)
149{
150 agnx_print_hdr(hdr);
151
152 PRINTK_BE16(HDR, hdr->rx.rx_packet_duration);
153 PRINTK_BE16(HDR, hdr->rx.replay_cnt);
154
155 PRINTK_U8(HDR, hdr->rx_channel);
156}
157
158static inline void agnx_print_tx_hdr(struct agnx_hdr *hdr)
159{
160 agnx_print_hdr(hdr);
161
162 PRINTK_U8(HDR, hdr->tx.long_retry_limit);
163 PRINTK_U8(HDR, hdr->tx.short_retry_limit);
164 PRINTK_U8(HDR, hdr->tx.long_retry_cnt);
165 PRINTK_U8(HDR, hdr->tx.short_retry_cnt);
166
167 PRINTK_U8(HDR, hdr->rx_channel);
168}
169
170static inline void
171agnx_print_sta_power(struct agnx_priv *priv, unsigned int sta_idx)
172{
173 struct agnx_sta_power power;
174 u32 reg;
175
176 get_sta_power(priv, &power, sta_idx);
177
178 reg = le32_to_cpu(power.reg);
179 PRINTK_BITS(STA_POWER, SIGNAL);
180 PRINTK_BITS(STA_POWER, RATE);
181 PRINTK_BITS(STA_POWER, TIFS);
182 PRINTK_BITS(STA_POWER, EDCF);
183 PRINTK_BITS(STA_POWER, CHANNEL_BOND);
184 PRINTK_BITS(STA_POWER, PHY_MODE);
185 PRINTK_BITS(STA_POWER, POWER_LEVEL);
186 PRINTK_BITS(STA_POWER, NUM_TRANSMITTERS);
187}
188
189static inline void
190agnx_print_sta_tx_wq(struct agnx_priv *priv, unsigned int sta_idx, unsigned int wq_idx)
191{
192 struct agnx_sta_tx_wq tx_wq;
193 u32 reg;
194
195 get_sta_tx_wq(priv, &tx_wq, sta_idx, wq_idx);
196
197 reg = le32_to_cpu(tx_wq.reg0);
198 PRINTK_BITS(STA_TX_WQ, TAIL_POINTER);
199 PRINTK_BITS(STA_TX_WQ, HEAD_POINTER_LOW);
200
201 reg = le32_to_cpu(tx_wq.reg3);
202 PRINTK_BITS(STA_TX_WQ, HEAD_POINTER_HIGH);
203 PRINTK_BITS(STA_TX_WQ, ACK_POINTER_LOW);
204
205 reg = le32_to_cpu(tx_wq.reg1);
206 PRINTK_BITS(STA_TX_WQ, ACK_POINTER_HIGH);
207 PRINTK_BITS(STA_TX_WQ, HEAD_TIMOUT_TAIL_PACK_CNT);
208 PRINTK_BITS(STA_TX_WQ, ACK_TIMOUT_TAIL_PACK_CNT);
209
210 reg = le32_to_cpu(tx_wq.reg2);
211 PRINTK_BITS(STA_TX_WQ, HEAD_TIMOUT_WIN_LIM_BYTE_CNT);
212 PRINTK_BITS(STA_TX_WQ, HEAD_TIMOUT_WIN_LIM_FRAG_CNT);
213 PRINTK_BITS(STA_TX_WQ, WORK_QUEUE_ACK_TYPE);
214 PRINTK_BITS(STA_TX_WQ, WORK_QUEUE_VALID);
215}
216
217static inline void agnx_print_sta_traffic(struct agnx_sta_traffic *traffic)
218{
219 u32 reg;
220
221 reg = le32_to_cpu(traffic->reg0);
222 PRINTK_BITS(STA_TRAFFIC, ACK_TIMOUT_CNT);
223 PRINTK_BITS(STA_TRAFFIC, TRAFFIC_ACK_TYPE);
224 PRINTK_BITS(STA_TRAFFIC, NEW_PACKET);
225 PRINTK_BITS(STA_TRAFFIC, TRAFFIC_VALID);
226 PRINTK_BITS(STA_TRAFFIC, RX_HDR_DESC_POINTER);
227
228 reg = le32_to_cpu(traffic->reg1);
229 PRINTK_BITS(STA_TRAFFIC, RX_PACKET_TIMESTAMP);
230 PRINTK_BITS(STA_TRAFFIC, TRAFFIC_RESERVED);
231 PRINTK_BITS(STA_TRAFFIC, SV);
232 PRINTK_BITS(STA_TRAFFIC, RX_SEQUENCE_NUM);
233
234 PRINTK_LE32(STA_TRAFFIC, traffic->tx_replay_cnt_low);
235
236 PRINTK_LE16(STA_TRAFFIC, traffic->tx_replay_cnt_high);
237 PRINTK_LE16(STA_TRAFFIC, traffic->rx_replay_cnt_high);
238
239 PRINTK_LE32(STA_TRAFFIC, traffic->rx_replay_cnt_low);
240}
241
242static inline void agnx_print_sta(struct agnx_priv *priv, unsigned int sta_idx)
243{
244 struct agnx_sta station;
245 struct agnx_sta *sta = &station;
246 u32 reg;
247 unsigned int i;
248
249 get_sta(priv, sta, sta_idx);
250
251 for (i = 0; i < 4; i++)
252 PRINTK_LE32(STA, sta->tx_session_keys[i]);
253 for (i = 0; i < 4; i++)
254 PRINTK_LE32(STA, sta->rx_session_keys[i]);
255
256 reg = le32_to_cpu(sta->reg);
257 PRINTK_BITS(STA, ID_1);
258 PRINTK_BITS(STA, ID_0);
259 PRINTK_BITS(STA, ENABLE_CONCATENATION);
260 PRINTK_BITS(STA, ENABLE_DECOMPRESSION);
261 PRINTK_BITS(STA, STA_RESERVED);
262 PRINTK_BITS(STA, EAP);
263 PRINTK_BITS(STA, ED_NULL);
264 PRINTK_BITS(STA, ENCRYPTION_POLICY);
265 PRINTK_BITS(STA, DEFINED_KEY_ID);
266 PRINTK_BITS(STA, FIXED_KEY);
267 PRINTK_BITS(STA, KEY_VALID);
268 PRINTK_BITS(STA, STATION_VALID);
269
270 PRINTK_LE32(STA, sta->tx_aes_blks_unicast);
271 PRINTK_LE32(STA, sta->rx_aes_blks_unicast);
272
273 PRINTK_LE16(STA, sta->aes_format_err_unicast_cnt);
274 PRINTK_LE16(STA, sta->aes_replay_unicast);
275
276 PRINTK_LE16(STA, sta->aes_decrypt_err_unicast);
277 PRINTK_LE16(STA, sta->aes_decrypt_err_default);
278
279 PRINTK_LE16(STA, sta->single_retry_packets);
280 PRINTK_LE16(STA, sta->failed_tx_packets);
281
282 PRINTK_LE16(STA, sta->muti_retry_packets);
283 PRINTK_LE16(STA, sta->ack_timeouts);
284
285 PRINTK_LE16(STA, sta->frag_tx_cnt);
286 PRINTK_LE16(STA, sta->rts_brq_sent);
287
288 PRINTK_LE16(STA, sta->tx_packets);
289 PRINTK_LE16(STA, sta->cts_back_timeout);
290
291 PRINTK_LE32(STA, sta->phy_stats_high);
292 PRINTK_LE32(STA, sta->phy_stats_low);
293
294 /* for (i = 0; i < 8; i++) */
295 agnx_print_sta_traffic(sta->traffic + 0);
296
297 PRINTK_LE16(STA, sta->traffic_class0_frag_success);
298 PRINTK_LE16(STA, sta->traffic_class1_frag_success);
299 PRINTK_LE16(STA, sta->traffic_class2_frag_success);
300 PRINTK_LE16(STA, sta->traffic_class3_frag_success);
301 PRINTK_LE16(STA, sta->traffic_class4_frag_success);
302 PRINTK_LE16(STA, sta->traffic_class5_frag_success);
303 PRINTK_LE16(STA, sta->traffic_class6_frag_success);
304 PRINTK_LE16(STA, sta->traffic_class7_frag_success);
305
306 PRINTK_LE16(STA, sta->num_frag_non_prime_rates);
307 PRINTK_LE16(STA, sta->ack_timeout_non_prime_rates);
308}
309
310
311static inline void dump_ieee80211_hdr(struct ieee80211_hdr *hdr, char *tag)
312{
313 u16 fctl;
314 int hdrlen;
315
316 fctl = le16_to_cpu(hdr->frame_control);
317 switch (fctl & IEEE80211_FCTL_FTYPE) {
318 case IEEE80211_FTYPE_DATA:
319 printk(PFX "%s DATA ", tag);
320 break;
321 case IEEE80211_FTYPE_CTL:
322 printk(PFX "%s CTL ", tag);
323 break;
324 case IEEE80211_FTYPE_MGMT:
325 printk(PFX "%s MGMT ", tag);
326 switch (fctl & IEEE80211_FCTL_STYPE) {
327 case IEEE80211_STYPE_ASSOC_REQ:
328 printk("SubType: ASSOC_REQ ");
329 break;
330 case IEEE80211_STYPE_ASSOC_RESP:
331 printk("SubType: ASSOC_RESP ");
332 break;
333 case IEEE80211_STYPE_REASSOC_REQ:
334 printk("SubType: REASSOC_REQ ");
335 break;
336 case IEEE80211_STYPE_REASSOC_RESP:
337 printk("SubType: REASSOC_RESP ");
338 break;
339 case IEEE80211_STYPE_PROBE_REQ:
340 printk("SubType: PROBE_REQ ");
341 break;
342 case IEEE80211_STYPE_PROBE_RESP:
343 printk("SubType: PROBE_RESP ");
344 break;
345 case IEEE80211_STYPE_BEACON:
346 printk("SubType: BEACON ");
347 break;
348 case IEEE80211_STYPE_ATIM:
349 printk("SubType: ATIM ");
350 break;
351 case IEEE80211_STYPE_DISASSOC:
352 printk("SubType: DISASSOC ");
353 break;
354 case IEEE80211_STYPE_AUTH:
355 printk("SubType: AUTH ");
356 break;
357 case IEEE80211_STYPE_DEAUTH:
358 printk("SubType: DEAUTH ");
359 break;
360 case IEEE80211_STYPE_ACTION:
361 printk("SubType: ACTION ");
362 break;
363 default:
364 printk("SubType: Unknow\n");
365 }
366 break;
367 default:
368 printk(PFX "%s Packet type: Unknow\n", tag);
369 }
370
371 hdrlen = ieee80211_hdrlen(fctl);
372
373 if (hdrlen >= 4)
374 printk("FC=0x%04x DUR=0x%04x",
375 fctl, le16_to_cpu(hdr->duration_id));
376 if (hdrlen >= 10)
377 printk(" A1=%pM", hdr->addr1);
378 if (hdrlen >= 16)
379 printk(" A2=%pM", hdr->addr2);
380 if (hdrlen >= 24)
381 printk(" A3=%pM", hdr->addr3);
382 if (hdrlen >= 30)
383 printk(" A4=%pM", hdr->addr4);
384 printk("\n");
385}
386
387static inline void dump_txm_registers(struct agnx_priv *priv)
388{
389 void __iomem *ctl = priv->ctl;
390 int i;
391 for (i = 0; i <= 0x1e8; i += 4)
392 printk(KERN_DEBUG PFX "TXM: %x---> 0x%.8x\n", i, ioread32(ctl + i));
393}
394static inline void dump_rxm_registers(struct agnx_priv *priv)
395{
396 void __iomem *ctl = priv->ctl;
397 int i;
398 for (i = 0; i <= 0x108; i += 4)
399 printk(KERN_DEBUG PFX "RXM: %x---> 0x%.8x\n", i, ioread32(ctl + 0x2000 + i));
400}
401static inline void dump_bm_registers(struct agnx_priv *priv)
402{
403 void __iomem *ctl = priv->ctl;
404 int i;
405 for (i = 0; i <= 0x90; i += 4)
406 printk(KERN_DEBUG PFX "BM: %x---> 0x%.8x\n", i, ioread32(ctl + 0x2c00 + i));
407}
408static inline void dump_cir_registers(struct agnx_priv *priv)
409{
410 void __iomem *ctl = priv->ctl;
411 int i;
412 for (i = 0; i <= 0xb8; i += 4)
413 printk(KERN_DEBUG PFX "CIR: %x---> 0x%.8x\n", i, ioread32(ctl + 0x3000 + i));
414}
415
416#endif /* AGNX_DEBUG_H_ */
diff --git a/drivers/staging/agnx/pci.c b/drivers/staging/agnx/pci.c
deleted file mode 100644
index 32b5489456a..00000000000
--- a/drivers/staging/agnx/pci.c
+++ /dev/null
@@ -1,635 +0,0 @@
1/**
2 * Airgo MIMO wireless driver
3 *
4 * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
5
6 * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
7 * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
8
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18
19#include "agnx.h"
20#include "debug.h"
21#include "xmit.h"
22#include "phy.h"
23
24MODULE_AUTHOR("Li YanBo <dreamfly281@gmail.com>");
25MODULE_DESCRIPTION("Airgo MIMO PCI wireless driver");
26MODULE_LICENSE("GPL");
27
28static struct pci_device_id agnx_pci_id_tbl[] __devinitdata = {
29 { PCI_DEVICE(0x17cb, 0x0001) }, /* Beklin F5d8010, Netgear WGM511 etc */
30 { PCI_DEVICE(0x17cb, 0x0002) }, /* Netgear Wpnt511 */
31 { 0 }
32};
33
34MODULE_DEVICE_TABLE(pci, agnx_pci_id_tbl);
35
36
37static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason)
38{
39 void __iomem *ctl = priv->ctl;
40 u32 reg;
41
42 if (*reason & AGNX_STAT_RX) {
43 /* Mark complete RX */
44 reg = ioread32(ctl + AGNX_CIR_RXCTL);
45 reg |= 0x4;
46 iowrite32(reg, ctl + AGNX_CIR_RXCTL);
47 /* disable Rx interrupt */
48 }
49 if (*reason & AGNX_STAT_TX) {
50 reg = ioread32(ctl + AGNX_CIR_TXDCTL);
51 if (reg & 0x4) {
52 iowrite32(reg, ctl + AGNX_CIR_TXDCTL);
53 *reason |= AGNX_STAT_TXD;
54 }
55 reg = ioread32(ctl + AGNX_CIR_TXMCTL);
56 if (reg & 0x4) {
57 iowrite32(reg, ctl + AGNX_CIR_TXMCTL);
58 *reason |= AGNX_STAT_TXM;
59 }
60 }
61#if 0
62 if (*reason & AGNX_STAT_X) {
63 reg = ioread32(ctl + AGNX_INT_STAT);
64 iowrite32(reg, ctl + AGNX_INT_STAT);
65 /* FIXME reinit interrupt mask */
66 reg = 0xc390bf9 & ~IRQ_TX_BEACON;
67 reg &= ~IRQ_TX_DISABLE;
68 iowrite32(reg, ctl + AGNX_INT_MASK);
69 iowrite32(0x800, ctl + AGNX_CIR_BLKCTL);
70 }
71#endif
72} /* agnx_interrupt_ack */
73
74static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
75{
76 struct ieee80211_hw *dev = dev_id;
77 struct agnx_priv *priv = dev->priv;
78 void __iomem *ctl = priv->ctl;
79 irqreturn_t ret = IRQ_NONE;
80 u32 irq_reason;
81
82 spin_lock(&priv->lock);
83
84/* printk(KERN_ERR PFX "Get a interrupt %s\n", __func__); */
85
86 if (priv->init_status != AGNX_START)
87 goto out;
88
89 /* FiXME Here has no lock, Is this will lead to race? */
90 irq_reason = ioread32(ctl + AGNX_CIR_BLKCTL);
91 if (!(irq_reason & 0x7))
92 goto out;
93
94 ret = IRQ_HANDLED;
95 priv->irq_status = ioread32(ctl + AGNX_INT_STAT);
96
97/* printk(PFX "Interrupt reason is 0x%x\n", irq_reason); */
98 /* Make sure the txm and txd flags don't conflict with other unknown
99 interrupt flag, maybe is not necessary */
100 irq_reason &= 0xF;
101
102 disable_rx_interrupt(priv);
103 /* TODO Make sure the card finished initialized */
104 agnx_interrupt_ack(priv, &irq_reason);
105
106 if (irq_reason & AGNX_STAT_RX)
107 handle_rx_irq(priv);
108 if (irq_reason & AGNX_STAT_TXD)
109 handle_txd_irq(priv);
110 if (irq_reason & AGNX_STAT_TXM)
111 handle_txm_irq(priv);
112 if (irq_reason & AGNX_STAT_X)
113 handle_other_irq(priv);
114
115 enable_rx_interrupt(priv);
116out:
117 spin_unlock(&priv->lock);
118 return ret;
119} /* agnx_interrupt_handler */
120
121
122/* FIXME */
123static int agnx_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
124{
125 AGNX_TRACE;
126 return _agnx_tx(dev->priv, skb);
127} /* agnx_tx */
128
129
130static int agnx_get_mac_address(struct agnx_priv *priv)
131{
132 void __iomem *ctl = priv->ctl;
133 u32 reg;
134 AGNX_TRACE;
135
136 /* Attention! directly read the MAC or other date from EEPROM will
137 lead to cardbus(WGM511) lock up when write to PM PLL register */
138 reg = agnx_read32(ctl, 0x3544);
139 udelay(40);
140 reg = agnx_read32(ctl, 0x354c);
141 udelay(50);
142 /* Get the mac address */
143 reg = agnx_read32(ctl, 0x3544);
144 udelay(40);
145
146 /* HACK */
147 reg = cpu_to_le32(reg);
148 priv->mac_addr[0] = ((u8 *)&reg)[2];
149 priv->mac_addr[1] = ((u8 *)&reg)[3];
150 reg = agnx_read32(ctl, 0x3548);
151 udelay(50);
152 *((u32 *)(priv->mac_addr + 2)) = cpu_to_le32(reg);
153
154 if (!is_valid_ether_addr(priv->mac_addr)) {
155 printk(KERN_WARNING PFX "read mac %pM\n", priv->mac_addr);
156 printk(KERN_WARNING PFX "Invalid hwaddr! Using random hwaddr\n");
157 random_ether_addr(priv->mac_addr);
158 }
159
160 return 0;
161} /* agnx_get_mac_address */
162
163static int agnx_alloc_rings(struct agnx_priv *priv)
164{
165 unsigned int len;
166 AGNX_TRACE;
167
168 /* Allocate RX/TXM/TXD rings info */
169 priv->rx.size = AGNX_RX_RING_SIZE;
170 priv->txm.size = AGNX_TXM_RING_SIZE;
171 priv->txd.size = AGNX_TXD_RING_SIZE;
172
173 len = priv->rx.size + priv->txm.size + priv->txd.size;
174
175/* priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL); */
176 priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC);
177 if (!priv->rx.info)
178 return -ENOMEM;
179 priv->txm.info = priv->rx.info + priv->rx.size;
180 priv->txd.info = priv->txm.info + priv->txm.size;
181
182 /* Allocate RX/TXM/TXD descriptors */
183 priv->rx.desc = pci_alloc_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
184 &priv->rx.dma);
185 if (!priv->rx.desc) {
186 kfree(priv->rx.info);
187 return -ENOMEM;
188 }
189
190 priv->txm.desc = priv->rx.desc + priv->rx.size;
191 priv->txm.dma = priv->rx.dma + sizeof(struct agnx_desc) * priv->rx.size;
192 priv->txd.desc = priv->txm.desc + priv->txm.size;
193 priv->txd.dma = priv->txm.dma + sizeof(struct agnx_desc) * priv->txm.size;
194
195 return 0;
196} /* agnx_alloc_rings */
197
198static void rings_free(struct agnx_priv *priv)
199{
200 unsigned int len = priv->rx.size + priv->txm.size + priv->txd.size;
201 unsigned long flags;
202 AGNX_TRACE;
203
204 spin_lock_irqsave(&priv->lock, flags);
205 kfree(priv->rx.info);
206 pci_free_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
207 priv->rx.desc, priv->rx.dma);
208 spin_unlock_irqrestore(&priv->lock, flags);
209}
210
211#if 0
212static void agnx_periodic_work_handler(struct work_struct *work)
213{
214 struct agnx_priv *priv = container_of(work, struct agnx_priv, periodic_work.work);
215/* unsigned long flags; */
216 unsigned long delay;
217
218 /* fixme: using mutex?? */
219/* spin_lock_irqsave(&priv->lock, flags); */
220
221 /* TODO Recalibrate*/
222/* calibrate_oscillator(priv); */
223/* antenna_calibrate(priv); */
224/* agnx_send_packet(priv, 997); */
225 /* FIXME */
226/* if (debug == 3) */
227/* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
228/* else */
229 delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY);
230/* delay = round_jiffies(HZ * 15); */
231
232 queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay);
233
234/* spin_unlock_irqrestore(&priv->lock, flags); */
235}
236#endif
237
238static int agnx_start(struct ieee80211_hw *dev)
239{
240 struct agnx_priv *priv = dev->priv;
241 /* unsigned long delay; */
242 int err = 0;
243 AGNX_TRACE;
244
245 err = agnx_alloc_rings(priv);
246 if (err) {
247 printk(KERN_ERR PFX "Can't alloc RX/TXM/TXD rings\n");
248 goto out;
249 }
250 err = request_irq(priv->pdev->irq, &agnx_interrupt_handler,
251 IRQF_SHARED, "agnx_pci", dev);
252 if (err) {
253 printk(KERN_ERR PFX "Failed to register IRQ handler\n");
254 rings_free(priv);
255 goto out;
256 }
257
258/* mdelay(500); */
259
260 might_sleep();
261 agnx_hw_init(priv);
262
263/* mdelay(500); */
264 might_sleep();
265
266 priv->init_status = AGNX_START;
267/* INIT_DELAYED_WORK(&priv->periodic_work, agnx_periodic_work_handler); */
268/* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
269/* queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay); */
270out:
271 return err;
272} /* agnx_start */
273
274static void agnx_stop(struct ieee80211_hw *dev)
275{
276 struct agnx_priv *priv = dev->priv;
277 AGNX_TRACE;
278
279 priv->init_status = AGNX_STOP;
280 /* make sure hardware will not generate irq */
281 agnx_hw_reset(priv);
282 free_irq(priv->pdev->irq, dev);
283/* flush_workqueue(priv->hw->workqueue); */
284/* cancel_delayed_work_sync(&priv->periodic_work); */
285 unfill_rings(priv);
286 rings_free(priv);
287}
288
289static int agnx_config(struct ieee80211_hw *dev, u32 changed)
290{
291 struct agnx_priv *priv = dev->priv;
292 struct ieee80211_conf *conf = &dev->conf;
293 int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
294 AGNX_TRACE;
295
296 spin_lock(&priv->lock);
297 /* FIXME need priv lock? */
298 if (channel != priv->channel) {
299 priv->channel = channel;
300 agnx_set_channel(priv, priv->channel);
301 }
302
303 spin_unlock(&priv->lock);
304 return 0;
305}
306
307static void agnx_bss_info_changed(struct ieee80211_hw *dev,
308 struct ieee80211_vif *vif,
309 struct ieee80211_bss_conf *conf,
310 u32 changed)
311{
312 struct agnx_priv *priv = dev->priv;
313 void __iomem *ctl = priv->ctl;
314 AGNX_TRACE;
315
316 if (!(changed & BSS_CHANGED_BSSID))
317 return;
318
319 spin_lock(&priv->lock);
320
321 if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
322 agnx_set_bssid(priv, conf->bssid);
323 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
324 hash_write(priv, conf->bssid, BSSID_STAID);
325 sta_init(priv, BSSID_STAID);
326 /* FIXME needed? */
327 sta_power_init(priv, BSSID_STAID);
328 agnx_write32(ctl, AGNX_BM_MTSM, 0xff & ~0x1);
329 }
330 spin_unlock(&priv->lock);
331} /* agnx_bss_info_changed */
332
333
334static void agnx_configure_filter(struct ieee80211_hw *dev,
335 unsigned int changed_flags,
336 unsigned int *total_flags,
337 int mc_count, struct dev_mc_list *mclist)
338{
339 unsigned int new_flags = 0;
340
341 *total_flags = new_flags;
342 /* TODO */
343}
344
345static int agnx_add_interface(struct ieee80211_hw *dev,
346 struct ieee80211_if_init_conf *conf)
347{
348 struct agnx_priv *priv = dev->priv;
349 AGNX_TRACE;
350
351 spin_lock(&priv->lock);
352 /* FIXME */
353 if (priv->mode != NL80211_IFTYPE_MONITOR)
354 return -EOPNOTSUPP;
355
356 switch (conf->type) {
357 case NL80211_IFTYPE_STATION:
358 priv->mode = conf->type;
359 break;
360 default:
361 return -EOPNOTSUPP;
362 }
363
364 spin_unlock(&priv->lock);
365
366 return 0;
367}
368
369static void agnx_remove_interface(struct ieee80211_hw *dev,
370 struct ieee80211_if_init_conf *conf)
371{
372 struct agnx_priv *priv = dev->priv;
373 AGNX_TRACE;
374
375 /* TODO */
376 priv->mode = NL80211_IFTYPE_MONITOR;
377}
378
379static int agnx_get_stats(struct ieee80211_hw *dev,
380 struct ieee80211_low_level_stats *stats)
381{
382 struct agnx_priv *priv = dev->priv;
383 AGNX_TRACE;
384 spin_lock(&priv->lock);
385 /* TODO !! */
386 memcpy(stats, &priv->stats, sizeof(*stats));
387 spin_unlock(&priv->lock);
388
389 return 0;
390}
391
392static u64 agnx_get_tsft(struct ieee80211_hw *dev)
393{
394 void __iomem *ctl = ((struct agnx_priv *)dev->priv)->ctl;
395 u32 tsftl;
396 u64 tsft;
397 AGNX_TRACE;
398
399 /* FIXME */
400 tsftl = ioread32(ctl + AGNX_TXM_TIMESTAMPLO);
401 tsft = ioread32(ctl + AGNX_TXM_TIMESTAMPHI);
402 tsft <<= 32;
403 tsft |= tsftl;
404
405 return tsft;
406}
407
408static int agnx_get_tx_stats(struct ieee80211_hw *dev,
409 struct ieee80211_tx_queue_stats *stats)
410{
411 struct agnx_priv *priv = dev->priv;
412 AGNX_TRACE;
413
414 /* FIXME now we just using txd queue, but should using txm queue too */
415 stats[0].len = (priv->txd.idx - priv->txd.idx_sent) / 2;
416 stats[0].limit = priv->txd.size - 2;
417 stats[0].count = priv->txd.idx / 2;
418
419 return 0;
420}
421
422static struct ieee80211_ops agnx_ops = {
423 .tx = agnx_tx,
424 .start = agnx_start,
425 .stop = agnx_stop,
426 .add_interface = agnx_add_interface,
427 .remove_interface = agnx_remove_interface,
428 .config = agnx_config,
429 .bss_info_changed = agnx_bss_info_changed,
430 .configure_filter = agnx_configure_filter,
431 .get_stats = agnx_get_stats,
432 .get_tx_stats = agnx_get_tx_stats,
433 .get_tsf = agnx_get_tsft
434};
435
436static void __devexit agnx_pci_remove(struct pci_dev *pdev)
437{
438 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
439 struct agnx_priv *priv;
440 AGNX_TRACE;
441
442 if (!dev)
443 return;
444 priv = dev->priv;
445 ieee80211_unregister_hw(dev);
446 pci_iounmap(pdev, priv->ctl);
447 pci_iounmap(pdev, priv->data);
448 pci_release_regions(pdev);
449 pci_disable_device(pdev);
450
451 ieee80211_free_hw(dev);
452}
453
454static int __devinit agnx_pci_probe(struct pci_dev *pdev,
455 const struct pci_device_id *id)
456{
457 struct ieee80211_hw *dev;
458 struct agnx_priv *priv;
459 int err;
460
461 err = pci_enable_device(pdev);
462 if (err) {
463 dev_err(&pdev->dev, "can't enable pci device\n");
464 return err;
465 }
466
467 err = pci_request_regions(pdev, "agnx-pci");
468 if (err) {
469 dev_err(&pdev->dev, "can't reserve PCI resources\n");
470 return err;
471 }
472
473 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
474 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
475 dev_err(&pdev->dev, "no suitable DMA available\n");
476 err = -EIO;
477 goto err_free_reg;
478 }
479
480 pci_set_master(pdev);
481
482 dev = ieee80211_alloc_hw(sizeof(*priv), &agnx_ops);
483 if (!dev) {
484 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
485 err = -ENOMEM;
486 goto err_free_reg;
487 }
488 priv = dev->priv;
489 memset(priv, 0, sizeof(*priv));
490 priv->mode = NL80211_IFTYPE_MONITOR;
491 priv->pdev = pdev;
492 priv->hw = dev;
493 spin_lock_init(&priv->lock);
494 priv->init_status = AGNX_UNINIT;
495
496 priv->ctl = pci_iomap(pdev, 0, 0);
497/* dev_dbg(&pdev->dev, "MEM1 mapped address is 0x%p\n", priv->ctl); */
498 if (!priv->ctl) {
499 dev_err(&pdev->dev, "can't map device memory\n");
500 err = -ENOMEM;
501 goto err_free_dev;
502 }
503 priv->data = pci_iomap(pdev, 1, 0);
504 if (!priv->data) {
505 dev_err(&pdev->dev, "can't map device memory\n");
506 err = -ENOMEM;
507 goto err_iounmap2;
508 }
509
510 pci_read_config_byte(pdev, PCI_REVISION_ID, &priv->revid);
511
512 priv->band.channels = (struct ieee80211_channel *)agnx_channels;
513 priv->band.n_channels = ARRAY_SIZE(agnx_channels);
514 priv->band.bitrates = (struct ieee80211_rate *)agnx_rates_80211g;
515 priv->band.n_bitrates = ARRAY_SIZE(agnx_rates_80211g);
516
517 /* Init ieee802.11 dev */
518 SET_IEEE80211_DEV(dev, &pdev->dev);
519 pci_set_drvdata(pdev, dev);
520 dev->extra_tx_headroom = sizeof(struct agnx_hdr);
521
522 /* FIXME It only include FCS in promious mode but not manage mode */
523/* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS; */
524 dev->channel_change_time = 5000;
525 dev->max_signal = 100;
526 /* FIXME */
527 dev->queues = 1;
528
529 agnx_get_mac_address(priv);
530
531 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
532
533/* /\* FIXME *\/ */
534/* for (i = 1; i < NUM_DRIVE_MODES; i++) { */
535/* err = ieee80211_register_hwmode(dev, &priv->modes[i]); */
536/* if (err) { */
537/* printk(KERN_ERR PFX "Can't register hwmode\n"); */
538/* goto err_iounmap; */
539/* } */
540/* } */
541
542 priv->channel = 1;
543 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
544
545 err = ieee80211_register_hw(dev);
546 if (err) {
547 dev_err(&pdev->dev, "can't register hardware\n");
548 goto err_iounmap;
549 }
550
551 agnx_hw_reset(priv);
552
553 dev_info(&pdev->dev, "%s: hwaddr %pM, Rev 0x%02x\n",
554 wiphy_name(dev->wiphy),
555 dev->wiphy->perm_addr, priv->revid);
556 return 0;
557
558 err_iounmap:
559 pci_iounmap(pdev, priv->data);
560
561 err_iounmap2:
562 pci_iounmap(pdev, priv->ctl);
563
564 err_free_dev:
565 pci_set_drvdata(pdev, NULL);
566 ieee80211_free_hw(dev);
567
568 err_free_reg:
569 pci_release_regions(pdev);
570
571 pci_disable_device(pdev);
572 return err;
573} /* agnx_pci_probe*/
574
575#ifdef CONFIG_PM
576
577static int agnx_pci_suspend(struct pci_dev *pdev, pm_message_t state)
578{
579 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
580 AGNX_TRACE;
581
582 ieee80211_stop_queues(dev);
583 agnx_stop(dev);
584
585 pci_save_state(pdev);
586 pci_set_power_state(pdev, pci_choose_state(pdev, state));
587 return 0;
588}
589
590static int agnx_pci_resume(struct pci_dev *pdev)
591{
592 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
593 AGNX_TRACE;
594
595 pci_set_power_state(pdev, PCI_D0);
596 pci_restore_state(pdev);
597
598 agnx_start(dev);
599 ieee80211_wake_queues(dev);
600
601 return 0;
602}
603
604#else
605
606#define agnx_pci_suspend NULL
607#define agnx_pci_resume NULL
608
609#endif /* CONFIG_PM */
610
611
612static struct pci_driver agnx_pci_driver = {
613 .name = "agnx-pci",
614 .id_table = agnx_pci_id_tbl,
615 .probe = agnx_pci_probe,
616 .remove = __devexit_p(agnx_pci_remove),
617 .suspend = agnx_pci_suspend,
618 .resume = agnx_pci_resume,
619};
620
621static int __init agnx_pci_init(void)
622{
623 AGNX_TRACE;
624 return pci_register_driver(&agnx_pci_driver);
625}
626
627static void __exit agnx_pci_exit(void)
628{
629 AGNX_TRACE;
630 pci_unregister_driver(&agnx_pci_driver);
631}
632
633
634module_init(agnx_pci_init);
635module_exit(agnx_pci_exit);
diff --git a/drivers/staging/agnx/phy.c b/drivers/staging/agnx/phy.c
deleted file mode 100644
index ec1ca86fa0c..00000000000
--- a/drivers/staging/agnx/phy.c
+++ /dev/null
@@ -1,960 +0,0 @@
1/**
2 * Airgo MIMO wireless driver
3 *
4 * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
5
6 * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
7 * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
8
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include "agnx.h"
19#include "debug.h"
20#include "phy.h"
21#include "table.h"
22#include "sta.h"
23#include "xmit.h"
24
25u8 read_from_eeprom(struct agnx_priv *priv, u16 address)
26{
27 void __iomem *ctl = priv->ctl;
28 struct agnx_eeprom cmd;
29 u32 reg;
30
31 memset(&cmd, 0, sizeof(cmd));
32 cmd.cmd = EEPROM_CMD_READ << AGNX_EEPROM_COMMAND_SHIFT;
33 cmd.address = address;
34 /* Verify that the Status bit is clear */
35 /* Read Command and Address are written to the Serial Interface */
36 iowrite32(*(__le32 *)&cmd, ctl + AGNX_CIR_SERIALITF);
37 /* Wait for the Status bit to clear again */
38 eeprom_delay();
39 /* Read from Data */
40 reg = ioread32(ctl + AGNX_CIR_SERIALITF);
41
42 cmd = *(struct agnx_eeprom *)&reg;
43
44 return cmd.data;
45}
46
47static int card_full_reset(struct agnx_priv *priv)
48{
49 void __iomem *ctl = priv->ctl;
50 u32 reg;
51 AGNX_TRACE;
52
53 reg = agnx_read32(ctl, AGNX_CIR_BLKCTL);
54 agnx_write32(ctl, AGNX_CIR_BLKCTL, 0x80);
55 reg = agnx_read32(ctl, AGNX_CIR_BLKCTL);
56 return 0;
57}
58
59inline void enable_power_saving(struct agnx_priv *priv)
60{
61 void __iomem *ctl = priv->ctl;
62 u32 reg;
63
64 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
65 reg &= ~0x8;
66 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
67}
68
69inline void disable_power_saving(struct agnx_priv *priv)
70{
71 void __iomem *ctl = priv->ctl;
72 u32 reg;
73
74 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
75 reg |= 0x8;
76 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
77}
78
79
80void disable_receiver(struct agnx_priv *priv)
81{
82 void __iomem *ctl = priv->ctl;
83 AGNX_TRACE;
84
85 /* FIXME Disable the receiver */
86 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x0);
87 /* Set gain control reset */
88 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
89 /* Reset gain control reset */
90 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
91}
92
93
94/* Fixme this shoule be disable RX, above is enable RX */
95void enable_receiver(struct agnx_priv *priv)
96{
97 void __iomem *ctl = priv->ctl;
98 AGNX_TRACE;
99
100 /* Set adaptive gain control discovery mode */
101 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
102 /* Set gain control reset */
103 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
104 /* Clear gain control reset */
105 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
106}
107
108static void mac_address_set(struct agnx_priv *priv)
109{
110 void __iomem *ctl = priv->ctl;
111 u8 *mac_addr = priv->mac_addr;
112 u32 reg;
113
114 /* FIXME */
115 reg = (mac_addr[0] << 24) | (mac_addr[1] << 16) | mac_addr[2] << 8 | mac_addr[3];
116 iowrite32(reg, ctl + AGNX_RXM_MACHI);
117 reg = (mac_addr[4] << 8) | mac_addr[5];
118 iowrite32(reg, ctl + AGNX_RXM_MACLO);
119}
120
121static void receiver_bssid_set(struct agnx_priv *priv, const u8 *bssid)
122{
123 void __iomem *ctl = priv->ctl;
124 u32 reg;
125
126 disable_receiver(priv);
127 /* FIXME */
128 reg = bssid[0] << 24 | (bssid[1] << 16) | (bssid[2] << 8) | bssid[3];
129 iowrite32(reg, ctl + AGNX_RXM_BSSIDHI);
130 reg = (bssid[4] << 8) | bssid[5];
131 iowrite32(reg, ctl + AGNX_RXM_BSSIDLO);
132
133 /* Enable the receiver */
134 enable_receiver(priv);
135
136 /* Clear the TSF */
137/* agnx_write32(ctl, AGNX_TXM_TSFLO, 0x0); */
138/* agnx_write32(ctl, AGNX_TXM_TSFHI, 0x0); */
139 /* Clear the TBTT */
140 agnx_write32(ctl, AGNX_TXM_TBTTLO, 0x0);
141 agnx_write32(ctl, AGNX_TXM_TBTTHI, 0x0);
142 disable_receiver(priv);
143} /* receiver_bssid_set */
144
145static void band_management_init(struct agnx_priv *priv)
146{
147 void __iomem *ctl = priv->ctl;
148 void __iomem *data = priv->data;
149 u32 reg;
150 int i;
151 AGNX_TRACE;
152
153 agnx_write32(ctl, AGNX_BM_TXWADDR, AGNX_PDU_TX_WQ);
154 agnx_write32(ctl, AGNX_CIR_ADDRWIN, 0x0);
155 memset_io(data + AGNX_PDUPOOL, 0x0, AGNX_PDUPOOL_SIZE);
156 agnx_write32(ctl, AGNX_BM_BMCTL, 0x200);
157
158 agnx_write32(ctl, AGNX_BM_CIPDUWCNT, 0x40);
159 agnx_write32(ctl, AGNX_BM_SPPDUWCNT, 0x2);
160 agnx_write32(ctl, AGNX_BM_RFPPDUWCNT, 0x0);
161 agnx_write32(ctl, AGNX_BM_RHPPDUWCNT, 0x22);
162
163 /* FIXME Initialize the Free Pool Linked List */
164 /* 1. Write the Address of the Next Node ((0x41800 + node*size)/size)
165 to the first word of each node. */
166 for (i = 0; i < PDU_FREE_CNT; i++) {
167 iowrite32((AGNX_PDU_FREE + (i+1)*PDU_SIZE)/PDU_SIZE,
168 data + AGNX_PDU_FREE + (PDU_SIZE * i));
169 /* The last node should be set to 0x0 */
170 if ((i + 1) == PDU_FREE_CNT)
171 memset_io(data + AGNX_PDU_FREE + (PDU_SIZE * i),
172 0x0, PDU_SIZE);
173 }
174
175 /* Head is First Pool address (0x41800) / size (0x80) */
176 agnx_write32(ctl, AGNX_BM_FPLHP, AGNX_PDU_FREE/PDU_SIZE);
177 /* Tail is Last Pool Address (0x47f80) / size (0x80) */
178 agnx_write32(ctl, AGNX_BM_FPLTP, 0x47f80/PDU_SIZE);
179 /* Count is Number of Nodes in the Pool (0xd0) */
180 agnx_write32(ctl, AGNX_BM_FPCNT, PDU_FREE_CNT);
181
182 /* Start all workqueue */
183 agnx_write32(ctl, AGNX_BM_CIWQCTL, 0x80000);
184 agnx_write32(ctl, AGNX_BM_CPULWCTL, 0x80000);
185 agnx_write32(ctl, AGNX_BM_CPUHWCTL, 0x80000);
186 agnx_write32(ctl, AGNX_BM_CPUTXWCTL, 0x80000);
187 agnx_write32(ctl, AGNX_BM_CPURXWCTL, 0x80000);
188 agnx_write32(ctl, AGNX_BM_SPRXWCTL, 0x80000);
189 agnx_write32(ctl, AGNX_BM_SPTXWCTL, 0x80000);
190 agnx_write32(ctl, AGNX_BM_RFPWCTL, 0x80000);
191
192 /* Enable the Band Management */
193 reg = agnx_read32(ctl, AGNX_BM_BMCTL);
194 reg |= 0x1;
195 agnx_write32(ctl, AGNX_BM_BMCTL, reg);
196} /* band_managment_init */
197
198
199static void system_itf_init(struct agnx_priv *priv)
200{
201 void __iomem *ctl = priv->ctl;
202 u32 reg;
203 AGNX_TRACE;
204
205 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, 0x0);
206 agnx_write32(ctl, AGNX_PM_TESTPHY, 0x11e143a);
207
208 if (priv->revid == 0) {
209 reg = agnx_read32(ctl, AGNX_SYSITF_SYSMODE);
210 reg |= 0x11;
211 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, reg);
212 }
213 /* ??? What is that means? it should difference for differice type
214 of cards */
215 agnx_write32(ctl, AGNX_CIR_SERIALITF, 0xfff81006);
216
217 agnx_write32(ctl, AGNX_SYSITF_GPIOIN, 0x1f0000);
218 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, 0x5);
219 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOIN);
220}
221
222static void encryption_init(struct agnx_priv *priv)
223{
224 void __iomem *ctl = priv->ctl;
225 AGNX_TRACE;
226
227 agnx_write32(ctl, AGNX_ENCRY_WEPKEY0, 0x0);
228 agnx_write32(ctl, AGNX_ENCRY_WEPKEY1, 0x0);
229 agnx_write32(ctl, AGNX_ENCRY_WEPKEY2, 0x0);
230 agnx_write32(ctl, AGNX_ENCRY_WEPKEY3, 0x0);
231 agnx_write32(ctl, AGNX_ENCRY_CCMRECTL, 0x8);
232}
233
234static void tx_management_init(struct agnx_priv *priv)
235{
236 void __iomem *ctl = priv->ctl;
237 void __iomem *data = priv->data;
238 u32 reg;
239 AGNX_TRACE;
240
241 /* Fill out the ComputationalEngineLookupTable
242 * starting at memory #2 offset 0x800
243 */
244 tx_engine_lookup_tbl_init(priv);
245 memset_io(data + 0x1000, 0, 0xfe0);
246 /* Enable Transmission Management Functions */
247 agnx_write32(ctl, AGNX_TXM_ETMF, 0x3ff);
248 /* Write 0x3f to Transmission Template */
249 agnx_write32(ctl, AGNX_TXM_TXTEMP, 0x3f);
250
251 if (priv->revid >= 2)
252 agnx_write32(ctl, AGNX_TXM_SIFSPIFS, 0x1e140a0b);
253 else
254 agnx_write32(ctl, AGNX_TXM_SIFSPIFS, 0x1e190a0b);
255
256 reg = agnx_read32(ctl, AGNX_TXM_TIFSEIFS);
257 reg &= 0xff00;
258 reg |= 0xb;
259 agnx_write32(ctl, AGNX_TXM_TIFSEIFS, reg);
260 reg = agnx_read32(ctl, AGNX_TXM_TIFSEIFS);
261 reg &= 0xffff00ff;
262 reg |= 0xa00;
263 agnx_write32(ctl, AGNX_TXM_TIFSEIFS, reg);
264 /* Enable TIFS */
265 agnx_write32(ctl, AGNX_TXM_CTL, 0x40000);
266
267 reg = agnx_read32(ctl, AGNX_TXM_TIFSEIFS);
268 reg &= 0xff00ffff;
269 reg |= 0x510000;
270 agnx_write32(ctl, AGNX_TXM_TIFSEIFS, reg);
271 reg = agnx_read32(ctl, AGNX_TXM_PROBDELAY);
272 reg &= 0xff00ffff;
273 agnx_write32(ctl, AGNX_TXM_PROBDELAY, reg);
274 reg = agnx_read32(ctl, AGNX_TXM_TIFSEIFS);
275 reg &= 0x00ffffff;
276 reg |= 0x1c000000;
277 agnx_write32(ctl, AGNX_TXM_TIFSEIFS, reg);
278 reg = agnx_read32(ctl, AGNX_TXM_PROBDELAY);
279 reg &= 0x00ffffff;
280 reg |= 0x01000000;
281 agnx_write32(ctl, AGNX_TXM_PROBDELAY, reg);
282
283 /* # Set DIF 0-1,2-3,4-5,6-7 to defaults */
284 agnx_write32(ctl, AGNX_TXM_DIF01, 0x321d321d);
285 agnx_write32(ctl, AGNX_TXM_DIF23, 0x321d321d);
286 agnx_write32(ctl, AGNX_TXM_DIF45, 0x321d321d);
287 agnx_write32(ctl, AGNX_TXM_DIF67, 0x321d321d);
288
289 /* Max Ack timeout limit */
290 agnx_write32(ctl, AGNX_TXM_MAXACKTIM, 0x1e19);
291 /* Max RX Data Timeout count, */
292 reg = agnx_read32(ctl, AGNX_TXM_MAXRXTIME);
293 reg &= 0xffff0000;
294 reg |= 0xff;
295 agnx_write32(ctl, AGNX_TXM_MAXRXTIME, reg);
296
297 /* CF poll RX Timeout count */
298 reg = agnx_read32(ctl, AGNX_TXM_CFPOLLRXTIM);
299 reg &= 0xffff;
300 reg |= 0xff0000;
301 agnx_write32(ctl, AGNX_TXM_CFPOLLRXTIM, reg);
302
303 /* Max Timeout Exceeded count, */
304 reg = agnx_read32(ctl, AGNX_TXM_MAXTIMOUT);
305 reg &= 0xff00ffff;
306 reg |= 0x190000;
307 agnx_write32(ctl, AGNX_TXM_MAXTIMOUT, reg);
308
309 /* CF ack timeout limit for 11b */
310 reg = agnx_read32(ctl, AGNX_TXM_CFACKT11B);
311 reg &= 0xff00;
312 reg |= 0x1e;
313 agnx_write32(ctl, AGNX_TXM_CFACKT11B, reg);
314
315 /* Max CF Poll Timeout Count */
316 reg = agnx_read32(ctl, AGNX_TXM_CFPOLLRXTIM);
317 reg &= 0xffff0000;
318 reg |= 0x19;
319 agnx_write32(ctl, AGNX_TXM_CFPOLLRXTIM, reg);
320 /* CF Poll RX Timeout Count */
321 reg = agnx_read32(ctl, AGNX_TXM_CFPOLLRXTIM);
322 reg &= 0xffff0000;
323 reg |= 0x1e;
324 agnx_write32(ctl, AGNX_TXM_CFPOLLRXTIM, reg);
325
326 /* # write default to */
327 /* 1. Schedule Empty Count */
328 agnx_write32(ctl, AGNX_TXM_SCHEMPCNT, 0x5);
329 /* 2. CFP Period Count */
330 agnx_write32(ctl, AGNX_TXM_CFPERCNT, 0x1);
331 /* 3. CFP MDV */
332 agnx_write32(ctl, AGNX_TXM_CFPMDV, 0x10000);
333
334 /* Probe Delay */
335 reg = agnx_read32(ctl, AGNX_TXM_PROBDELAY);
336 reg &= 0xffff0000;
337 reg |= 0x400;
338 agnx_write32(ctl, AGNX_TXM_PROBDELAY, reg);
339
340 /* Max CCA count Slot */
341 reg = agnx_read32(ctl, AGNX_TXM_MAXCCACNTSLOT);
342 reg &= 0xffff00ff;
343 reg |= 0x900;
344 agnx_write32(ctl, AGNX_TXM_MAXCCACNTSLOT, reg);
345
346 /* Slot limit/1 msec Limit */
347 reg = agnx_read32(ctl, AGNX_TXM_SLOTLIMIT);
348 reg &= 0xff00ffff;
349 reg |= 0x140077;
350 agnx_write32(ctl, AGNX_TXM_SLOTLIMIT, reg);
351
352 /* # Set CW #(0-7) to default */
353 agnx_write32(ctl, AGNX_TXM_CW0, 0xff0007);
354 agnx_write32(ctl, AGNX_TXM_CW1, 0xff0007);
355 agnx_write32(ctl, AGNX_TXM_CW2, 0xff0007);
356 agnx_write32(ctl, AGNX_TXM_CW3, 0xff0007);
357 agnx_write32(ctl, AGNX_TXM_CW4, 0xff0007);
358 agnx_write32(ctl, AGNX_TXM_CW5, 0xff0007);
359 agnx_write32(ctl, AGNX_TXM_CW6, 0xff0007);
360 agnx_write32(ctl, AGNX_TXM_CW7, 0xff0007);
361
362 /* # Set Short/Long limit #(0-7) to default */
363 agnx_write32(ctl, AGNX_TXM_SLBEALIM0, 0xa000a);
364 agnx_write32(ctl, AGNX_TXM_SLBEALIM1, 0xa000a);
365 agnx_write32(ctl, AGNX_TXM_SLBEALIM2, 0xa000a);
366 agnx_write32(ctl, AGNX_TXM_SLBEALIM3, 0xa000a);
367 agnx_write32(ctl, AGNX_TXM_SLBEALIM4, 0xa000a);
368 agnx_write32(ctl, AGNX_TXM_SLBEALIM5, 0xa000a);
369 agnx_write32(ctl, AGNX_TXM_SLBEALIM6, 0xa000a);
370 agnx_write32(ctl, AGNX_TXM_SLBEALIM7, 0xa000a);
371
372 reg = agnx_read32(ctl, AGNX_TXM_CTL);
373 reg |= 0x1400;
374 agnx_write32(ctl, AGNX_TXM_CTL, reg);
375 /* Wait for bit 0 in Control Reg to clear */
376 udelay(80);
377 reg = agnx_read32(ctl, AGNX_TXM_CTL);
378 /* Or 0x18000 to Control reg */
379 reg = agnx_read32(ctl, AGNX_TXM_CTL);
380 reg |= 0x18000;
381 agnx_write32(ctl, AGNX_TXM_CTL, reg);
382 /* Wait for bit 0 in Control Reg to clear */
383 udelay(80);
384 reg = agnx_read32(ctl, AGNX_TXM_CTL);
385
386 /* Set Listen Interval Count to default */
387 agnx_write32(ctl, AGNX_TXM_LISINTERCNT, 0x1);
388 /* Set DTIM period count to default */
389 agnx_write32(ctl, AGNX_TXM_DTIMPERICNT, 0x2000);
390} /* tx_management_init */
391
392static void rx_management_init(struct agnx_priv *priv)
393{
394 void __iomem *ctl = priv->ctl;
395 AGNX_TRACE;
396
397 /* Initialize the Routing Table */
398 routing_table_init(priv);
399
400 if (priv->revid >= 3) {
401 agnx_write32(ctl, 0x2074, 0x1f171710);
402 agnx_write32(ctl, 0x2078, 0x10100d0d);
403 agnx_write32(ctl, 0x207c, 0x11111010);
404 } else {
405 agnx_write32(ctl, AGNX_RXM_DELAY11, 0x0);
406 }
407 agnx_write32(ctl, AGNX_RXM_REQRATE, 0x8195e00);
408}
409
410
411static void agnx_timer_init(struct agnx_priv *priv)
412{
413 void __iomem *ctl = priv->ctl;
414 AGNX_TRACE;
415
416/* /\* Write 0x249f00 (tick duration?) to Timer 1 *\/ */
417/* agnx_write32(ctl, AGNX_TIMCTL_TIMER1, 0x249f00); */
418/* /\* Write 0xe2 to Timer 1 Control *\/ */
419/* agnx_write32(ctl, AGNX_TIMCTL_TIM1CTL, 0xe2); */
420
421 /* Write 0x249f00 (tick duration?) to Timer 1 */
422 agnx_write32(ctl, AGNX_TIMCTL_TIMER1, 0x0);
423 /* Write 0xe2 to Timer 1 Control */
424 agnx_write32(ctl, AGNX_TIMCTL_TIM1CTL, 0x0);
425
426 iowrite32(0xFFFFFFFF, priv->ctl + AGNX_TXM_BEACON_CTL);
427}
428
429static void power_manage_init(struct agnx_priv *priv)
430{
431 void __iomem *ctl = priv->ctl;
432 u32 reg;
433 AGNX_TRACE;
434
435 agnx_write32(ctl, AGNX_PM_MACMSW, 0x1f);
436 agnx_write32(ctl, AGNX_PM_RFCTL, 0x1f);
437
438 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
439 reg &= 0xf00f;
440 reg |= 0xa0;
441 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
442
443 if (priv->revid >= 3) {
444 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
445 reg |= 0x18;
446 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
447 }
448} /* power_manage_init */
449
450
451static void gain_ctlcnt_init(struct agnx_priv *priv)
452{
453 void __iomem *ctl = priv->ctl;
454 u32 reg;
455 AGNX_TRACE;
456
457 agnx_write32(ctl, AGNX_GCR_TRACNT5, 0x119);
458 agnx_write32(ctl, AGNX_GCR_TRACNT6, 0x118);
459 agnx_write32(ctl, AGNX_GCR_TRACNT7, 0x117);
460
461 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
462 reg |= 0x8;
463 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
464
465 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
466 reg &= ~0x8;
467 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
468
469 agnx_write32(ctl, AGNX_CIR_ADDRWIN, 0x0);
470
471 /* FIXME Write the initial Station Descriptor for the card */
472 sta_init(priv, LOCAL_STAID);
473 sta_init(priv, BSSID_STAID);
474
475 /* Enable staion 0 and 1 can do TX */
476 /* It seemed if we set other bit to 1 the bit 0 will
477 be auto change to 0 */
478 agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x2 | 0x1);
479/* agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x1); */
480} /* gain_ctlcnt_init */
481
482
483static void phy_init(struct agnx_priv *priv)
484{
485 void __iomem *ctl = priv->ctl;
486 void __iomem *data = priv->data;
487 u32 reg;
488 AGNX_TRACE;
489
490 /* Load InitialGainTable */
491 gain_table_init(priv);
492
493 agnx_write32(ctl, AGNX_CIR_ADDRWIN, 0x2000000);
494
495 /* Clear the following offsets in Memory Range #2: */
496 memset_io(data + 0x5040, 0, 0xa * 4);
497 memset_io(data + 0x5080, 0, 0xa * 4);
498 memset_io(data + 0x50c0, 0, 0xa * 4);
499 memset_io(data + 0x5400, 0, 0x80 * 4);
500 memset_io(data + 0x6000, 0, 0x280 * 4);
501 memset_io(data + 0x7000, 0, 0x280 * 4);
502 memset_io(data + 0x8000, 0, 0x280 * 4);
503
504 /* Initialize the Following Registers According to PCI Revision ID */
505 if (priv->revid == 0) {
506 /* fixme the part hasn't been update but below has been update
507 based on WGM511 */
508 agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
509 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x1d);
510 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x3);
511 agnx_write32(ctl, AGNX_ACI_AICCHA0OVE, 0x11);
512 agnx_write32(ctl, AGNX_ACI_AICCHA1OVE, 0x0);
513 agnx_write32(ctl, AGNX_GCR_THD0A, 0x64);
514 agnx_write32(ctl, AGNX_GCR_THD0AL, 0x4b);
515 agnx_write32(ctl, AGNX_GCR_THD0B, 0x4b);
516 agnx_write32(ctl, AGNX_GCR_DUNSAT, 0x14);
517 agnx_write32(ctl, AGNX_GCR_DSAT, 0x24);
518 agnx_write32(ctl, AGNX_GCR_DFIRCAL, 0x8);
519 agnx_write32(ctl, AGNX_GCR_DGCTL11A, 0x1a);
520 agnx_write32(ctl, AGNX_GCR_DGCTL11B, 0x3);
521 agnx_write32(ctl, AGNX_GCR_GAININIT, 0xd);
522 agnx_write32(ctl, AGNX_GCR_THNOSIG, 0x1);
523 agnx_write32(ctl, AGNX_GCR_COARSTEP, 0x7);
524 agnx_write32(ctl, AGNX_GCR_SIFST11A, 0x28);
525 agnx_write32(ctl, AGNX_GCR_SIFST11B, 0x28);
526 reg = agnx_read32(ctl, AGNX_GCR_CWDETEC);
527 reg |= 0x1;
528 agnx_write32(ctl, AGNX_GCR_CWDETEC, reg);
529 agnx_write32(ctl, AGNX_GCR_0X38, 0x1e);
530 agnx_write32(ctl, AGNX_GCR_BOACT, 0x26);
531 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
532 agnx_write32(ctl, AGNX_GCR_NLISTANT, 0x3);
533 agnx_write32(ctl, AGNX_GCR_NACTIANT, 0x3);
534 agnx_write32(ctl, AGNX_GCR_NMEASANT, 0x3);
535 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 0x3);
536 agnx_write32(ctl, AGNX_GCR_THCAP11A, 0x0);
537 agnx_write32(ctl, AGNX_GCR_THCAP11B, 0x0);
538 agnx_write32(ctl, AGNX_GCR_THCAPRX11A, 0x0);
539 agnx_write32(ctl, AGNX_GCR_THCAPRX11B, 0x0);
540 agnx_write32(ctl, AGNX_GCR_THLEVDRO, 0x10);
541 agnx_write32(ctl, AGNX_GCR_MAXRXTIME11A, 0x1);
542 agnx_write32(ctl, AGNX_GCR_MAXRXTIME11B, 0x1);
543 agnx_write32(ctl, AGNX_GCR_CORRTIME, 0x190);
544 agnx_write32(ctl, AGNX_GCR_SIGHTH, 0x78);
545 agnx_write32(ctl, AGNX_GCR_SIGLTH, 0x1c);
546 agnx_write32(ctl, AGNX_GCR_CORRDROP, 0x0);
547 agnx_write32(ctl, AGNX_GCR_THCD, 0x0);
548 agnx_write32(ctl, AGNX_GCR_MAXPOWDIFF, 0x1);
549 agnx_write32(ctl, AGNX_GCR_TESTBUS, 0x0);
550 agnx_write32(ctl, AGNX_GCR_ANTCFG, 0x1f);
551 agnx_write32(ctl, AGNX_GCR_THJUMP, 0x14);
552 agnx_write32(ctl, AGNX_GCR_THPOWER, 0x0);
553 agnx_write32(ctl, AGNX_GCR_THPOWCLIP, 0x30);
554 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 0x32);
555 agnx_write32(ctl, AGNX_GCR_THRX11BPOWMIN, 0x19);
556 agnx_write32(ctl, AGNX_GCR_0X14c, 0x0);
557 agnx_write32(ctl, AGNX_GCR_0X150, 0x0);
558 agnx_write32(ctl, 0x9400, 0x0);
559 agnx_write32(ctl, 0x940c, 0x6ff);
560 agnx_write32(ctl, 0x9428, 0xa0);
561 agnx_write32(ctl, 0x9434, 0x0);
562 agnx_write32(ctl, 0x9c04, 0x15);
563 agnx_write32(ctl, 0x9c0c, 0x7f);
564 agnx_write32(ctl, 0x9c34, 0x0);
565 agnx_write32(ctl, 0xc000, 0x38d);
566 agnx_write32(ctl, 0x14018, 0x0);
567 agnx_write32(ctl, 0x16000, 0x1);
568 agnx_write32(ctl, 0x11004, 0x0);
569 agnx_write32(ctl, 0xec54, 0xa);
570 agnx_write32(ctl, 0xec1c, 0x5);
571 } else if (priv->revid > 0) {
572 agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
573 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
574 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
575 agnx_write32(ctl, AGNX_ACI_AICCHA0OVE, 0x11);
576 agnx_write32(ctl, AGNX_ACI_AICCHA1OVE, 0x0);
577 agnx_write32(ctl, AGNX_GCR_DUNSAT, 0x14);
578 agnx_write32(ctl, AGNX_GCR_DSAT, 0x24);
579 agnx_write32(ctl, AGNX_GCR_DFIRCAL, 0x8);
580 agnx_write32(ctl, AGNX_GCR_DGCTL11A, 0x1a);
581 agnx_write32(ctl, AGNX_GCR_DGCTL11B, 0x3);
582 agnx_write32(ctl, AGNX_GCR_GAININIT, 0xd);
583 agnx_write32(ctl, AGNX_GCR_THNOSIG, 0x1);
584 agnx_write32(ctl, AGNX_GCR_COARSTEP, 0x7);
585 agnx_write32(ctl, AGNX_GCR_SIFST11A, 0x28);
586 agnx_write32(ctl, AGNX_GCR_SIFST11B, 0x28);
587 agnx_write32(ctl, AGNX_GCR_CWDETEC, 0x0);
588 agnx_write32(ctl, AGNX_GCR_0X38, 0x1e);
589/* agnx_write32(ctl, AGNX_GCR_BOACT, 0x26);*/
590 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
591
592 agnx_write32(ctl, AGNX_GCR_THCAP11A, 0x32);
593 agnx_write32(ctl, AGNX_GCR_THCAP11B, 0x32);
594 agnx_write32(ctl, AGNX_GCR_THCAPRX11A, 0x32);
595 agnx_write32(ctl, AGNX_GCR_THCAPRX11B, 0x32);
596 agnx_write32(ctl, AGNX_GCR_THLEVDRO, 0x10);
597 agnx_write32(ctl, AGNX_GCR_MAXRXTIME11A, 0x1ad);
598 agnx_write32(ctl, AGNX_GCR_MAXRXTIME11B, 0xa10);
599 agnx_write32(ctl, AGNX_GCR_CORRTIME, 0x190);
600 agnx_write32(ctl, AGNX_GCR_CORRDROP, 0x0);
601 agnx_write32(ctl, AGNX_GCR_THCD, 0x0);
602 agnx_write32(ctl, AGNX_GCR_THCS, 0x0);
603 agnx_write32(ctl, AGNX_GCR_MAXPOWDIFF, 0x4);
604 agnx_write32(ctl, AGNX_GCR_TESTBUS, 0x0);
605 agnx_write32(ctl, AGNX_GCR_THJUMP, 0x1e);
606 agnx_write32(ctl, AGNX_GCR_THPOWER, 0x0);
607 agnx_write32(ctl, AGNX_GCR_THPOWCLIP, 0x2a);
608 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 0x3c);
609 agnx_write32(ctl, AGNX_GCR_THRX11BPOWMIN, 0x19);
610 agnx_write32(ctl, AGNX_GCR_0X14c, 0x0);
611 agnx_write32(ctl, AGNX_GCR_0X150, 0x0);
612 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
613 agnx_write32(ctl, AGNX_GCR_WATCHDOG, 0x37);
614 agnx_write32(ctl, 0x9400, 0x0);
615 agnx_write32(ctl, 0x940c, 0x6ff);
616 agnx_write32(ctl, 0x9428, 0xa0);
617 agnx_write32(ctl, 0x9434, 0x0);
618 agnx_write32(ctl, 0x9c04, 0x15);
619 agnx_write32(ctl, 0x9c0c, 0x7f);
620 agnx_write32(ctl, 0x9c34, 0x0);
621 agnx_write32(ctl, 0xc000, 0x38d);
622 agnx_write32(ctl, 0x14014, 0x1000);
623 agnx_write32(ctl, 0x14018, 0x0);
624 agnx_write32(ctl, 0x16000, 0x1);
625 agnx_write32(ctl, 0x11004, 0x0);
626 agnx_write32(ctl, 0xec54, 0xa);
627 agnx_write32(ctl, 0xec1c, 0x50);
628 } else if (priv->revid > 1) {
629 reg = agnx_read32(ctl, 0xec18);
630 reg |= 0x8;
631 agnx_write32(ctl, 0xec18, reg);
632 }
633
634 /* Write the TX Fir Coefficient Table */
635 tx_fir_table_init(priv);
636
637 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
638 reg &= ~0x8;
639 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
640 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
641 reg |= 0x1;
642 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
643
644/* reg = agnx_read32(ctl, 0x1a030); */
645/* reg &= ~0x4; */
646/* agnx_write32(ctl, 0x1a030, reg); */
647
648 agnx_write32(ctl, AGNX_GCR_TRACNT4, 0x113);
649} /* phy_init */
650
651static void chip_init(struct agnx_priv *priv)
652{
653 void __iomem *ctl = priv->ctl;
654 u32 reg;
655 AGNX_TRACE;
656
657 band_management_init(priv);
658
659 rf_chips_init(priv);
660
661 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
662 reg |= 0x8;
663 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
664
665 /* Initialize the PHY */
666 phy_init(priv);
667
668 encryption_init(priv);
669
670 tx_management_init(priv);
671
672 rx_management_init(priv);
673
674 power_manage_init(priv);
675
676 /* Initialize the Timers */
677 agnx_timer_init(priv);
678
679 /* Write 0xc390bf9 to Interrupt Mask (Disable TX) */
680 reg = 0xc390bf9 & ~IRQ_TX_BEACON;
681 reg &= ~IRQ_TX_DISABLE;
682 agnx_write32(ctl, AGNX_INT_MASK, reg);
683
684 reg = agnx_read32(ctl, AGNX_CIR_BLKCTL);
685 reg |= 0x800;
686 agnx_write32(ctl, AGNX_CIR_BLKCTL, reg);
687
688 /* set it when need get multicast enable? */
689 agnx_write32(ctl, AGNX_BM_MTSM, 0xff);
690} /* chip_init */
691
692
693static inline void set_promis_and_managed(struct agnx_priv *priv)
694{
695 void __iomem *ctl = priv->ctl;
696 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x10 | 0x2);
697 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x10 | 0x2);
698}
699static inline void set_learn_mode(struct agnx_priv *priv)
700{
701 void __iomem *ctl = priv->ctl;
702 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x8);
703}
704static inline void set_scan_mode(struct agnx_priv *priv)
705{
706 void __iomem *ctl = priv->ctl;
707 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x20);
708}
709static inline void set_promiscuous_mode(struct agnx_priv *priv)
710{
711 void __iomem *ctl = priv->ctl;
712 /* agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x210);*/
713 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x10);
714}
715static inline void set_managed_mode(struct agnx_priv *priv)
716{
717 void __iomem *ctl = priv->ctl;
718 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x2);
719}
720static inline void set_adhoc_mode(struct agnx_priv *priv)
721{
722 void __iomem *ctl = priv->ctl;
723 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, 0x0);
724}
725
726#if 0
727static void unknow_register_write(struct agnx_priv *priv)
728{
729 void __iomem *ctl = priv->ctl;
730
731 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x0, 0x3e);
732 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x4, 0xb2);
733 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x8, 0x140);
734 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0xc, 0x1C0);
735 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x10, 0x1FF);
736 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x14, 0x1DD);
737 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x18, 0x15F);
738 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x1c, 0xA1);
739 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x20, 0x3E7);
740 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x24, 0x36B);
741 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x28, 0x348);
742 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x2c, 0x37D);
743 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x30, 0x3DE);
744 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x34, 0x36);
745 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x38, 0x64);
746 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x3c, 0x57);
747 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x40, 0x23);
748 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x44, 0x3ED);
749 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x48, 0x3C9);
750 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x4c, 0x3CA);
751 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x50, 0x3E7);
752 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x54, 0x8);
753 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x58, 0x1F);
754 agnx_write32(ctl, AGNX_UNKNOWN_BASE + 0x5c, 0x1a);
755}
756#endif
757
758static void card_interface_init(struct agnx_priv *priv)
759{
760 void __iomem *ctl = priv->ctl;
761 u8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
762 u32 reg;
763 unsigned int i;
764 AGNX_TRACE;
765
766 might_sleep();
767 /* Clear RX Control and Enable RX queues */
768 agnx_write32(ctl, AGNX_CIR_RXCTL, 0x8);
769
770 might_sleep();
771 /* Do a full reset of the card */
772 card_full_reset(priv);
773 might_sleep();
774
775 /* Check and set Card Endianness */
776 reg = ioread32(priv->ctl + AGNX_CIR_ENDIAN);
777 /* TODO If not 0xB3B2B1B0 set to 0xB3B2B1B0 */
778 printk(KERN_INFO PFX "CIR_ENDIAN is %x\n", reg);
779
780
781 /* Config the eeprom */
782 agnx_write32(ctl, AGNX_CIR_SERIALITF, 0x7000086);
783 udelay(10);
784 reg = agnx_read32(ctl, AGNX_CIR_SERIALITF);
785
786
787 agnx_write32(ctl, AGNX_PM_SOFTRST, 0x80000033);
788 reg = agnx_read32(ctl, 0xec50);
789 reg |= 0xf;
790 agnx_write32(ctl, 0xec50, reg);
791 agnx_write32(ctl, AGNX_PM_SOFTRST, 0x0);
792
793
794 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOIN);
795 udelay(10);
796 reg = agnx_read32(ctl, AGNX_CIR_SERIALITF);
797
798 /* Dump the eeprom */
799 do {
800 char eeprom[0x100000/0x100];
801
802 for (i = 0; i < 0x100000; i += 0x100) {
803 agnx_write32(ctl, AGNX_CIR_SERIALITF, 0x3000000 + i);
804 udelay(13);
805 reg = agnx_read32(ctl, AGNX_CIR_SERIALITF);
806 udelay(70);
807 reg = agnx_read32(ctl, AGNX_CIR_SERIALITF);
808 eeprom[i/0x100] = reg & 0xFF;
809 udelay(10);
810 }
811 print_hex_dump_bytes(PFX "EEPROM: ", DUMP_PREFIX_NONE, eeprom,
812 ARRAY_SIZE(eeprom));
813 } while (0);
814
815 spi_rc_write(ctl, RF_CHIP0, 0x26);
816 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
817
818 /* Initialize the system interface */
819 system_itf_init(priv);
820
821 might_sleep();
822 /* Chip Initialization (Polaris) */
823 chip_init(priv);
824 might_sleep();
825
826 /* Calibrate the antennae */
827 antenna_calibrate(priv);
828
829 reg = agnx_read32(ctl, 0xec50);
830 reg &= ~0x40;
831 agnx_write32(ctl, 0xec50, reg);
832 agnx_write32(ctl, AGNX_PM_SOFTRST, 0x0);
833 agnx_write32(ctl, AGNX_PM_PLLCTL, 0x1);
834
835 reg = agnx_read32(ctl, AGNX_BM_BMCTL);
836 reg |= 0x8000;
837 agnx_write32(ctl, AGNX_BM_BMCTL, reg);
838 enable_receiver(priv);
839 reg = agnx_read32(ctl, AGNX_SYSITF_SYSMODE);
840 reg |= 0x200;
841 agnx_write32(ctl, AGNX_SYSITF_SYSMODE, reg);
842 enable_receiver(priv);
843
844 might_sleep();
845 /* Initialize Gain Control Counts */
846 gain_ctlcnt_init(priv);
847
848 /* Write Initial Station Power Template for this station(#0) */
849 sta_power_init(priv, LOCAL_STAID);
850
851 might_sleep();
852 /* Initialize the rx,td,tm rings, for each node in the ring */
853 fill_rings(priv);
854
855 might_sleep();
856
857
858 agnx_write32(ctl, AGNX_PM_SOFTRST, 0x80000033);
859 agnx_write32(ctl, 0xec50, 0xc);
860 agnx_write32(ctl, AGNX_PM_SOFTRST, 0x0);
861
862 /* FIXME Initialize the transmit control register */
863 agnx_write32(ctl, AGNX_TXM_CTL, 0x194c1);
864
865 enable_receiver(priv);
866
867 might_sleep();
868 /* FIXME Set the Receive Control Mac Address to card address */
869 mac_address_set(priv);
870 enable_receiver(priv);
871 might_sleep();
872
873 /* Set the recieve request rate */
874 /* FIXME Enable the request */
875 /* Check packet length */
876 /* Set maximum packet length */
877/* agnx_write32(ctl, AGNX_RXM_REQRATE, 0x88195e00); */
878/* enable_receiver(priv); */
879
880 /* Set the Receiver BSSID */
881 receiver_bssid_set(priv, bssid);
882
883 /* FIXME Set to managed mode */
884 set_managed_mode(priv);
885/* set_promiscuous_mode(priv); */
886/* set_scan_mode(priv); */
887/* set_learn_mode(priv); */
888/* set_promis_and_managed(priv); */
889/* set_adhoc_mode(priv); */
890
891 /* Set the recieve request rate */
892 /* Check packet length */
893 agnx_write32(ctl, AGNX_RXM_REQRATE, 0x08000000);
894 reg = agnx_read32(ctl, AGNX_RXM_REQRATE);
895 /* Set maximum packet length */
896 reg |= 0x00195e00;
897 agnx_write32(ctl, AGNX_RXM_REQRATE, reg);
898
899 /* Configure the RX and TX interrupt */
900 reg = ENABLE_RX_INTERRUPT | RX_CACHE_LINE | FRAG_LEN_2048 | FRAG_BE;
901 agnx_write32(ctl, AGNX_CIR_RXCFG, reg);
902 /* FIXME */
903 reg = ENABLE_TX_INTERRUPT | TX_CACHE_LINE | FRAG_LEN_2048 | FRAG_BE;
904 agnx_write32(ctl, AGNX_CIR_TXCFG, reg);
905
906 /* Enable RX TX Interrupts */
907 agnx_write32(ctl, AGNX_CIR_RXCTL, 0x80);
908 agnx_write32(ctl, AGNX_CIR_TXMCTL, 0x80);
909 agnx_write32(ctl, AGNX_CIR_TXDCTL, 0x80);
910
911 /* FIXME Set the master control interrupt in block control */
912 agnx_write32(ctl, AGNX_CIR_BLKCTL, 0x800);
913
914 /* Enable RX and TX queues */
915 reg = agnx_read32(ctl, AGNX_CIR_RXCTL);
916 reg |= 0x8;
917 agnx_write32(ctl, AGNX_CIR_RXCTL, reg);
918 reg = agnx_read32(ctl, AGNX_CIR_TXMCTL);
919 reg |= 0x8;
920 agnx_write32(ctl, AGNX_CIR_TXMCTL, reg);
921 reg = agnx_read32(ctl, AGNX_CIR_TXDCTL);
922 reg |= 0x8;
923 agnx_write32(ctl, AGNX_CIR_TXDCTL, reg);
924
925 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, 0x5);
926 /* FIXME */
927 /* unknow_register_write(priv); */
928 /* Update local card hash entry */
929 hash_write(priv, priv->mac_addr, LOCAL_STAID);
930
931 might_sleep();
932
933 /* FIXME */
934 agnx_set_channel(priv, 1);
935 might_sleep();
936} /* agnx_card_interface_init */
937
938
939void agnx_hw_init(struct agnx_priv *priv)
940{
941 AGNX_TRACE;
942 might_sleep();
943 card_interface_init(priv);
944}
945
946int agnx_hw_reset(struct agnx_priv *priv)
947{
948 return card_full_reset(priv);
949}
950
951int agnx_set_ssid(struct agnx_priv *priv, u8 *ssid, size_t ssid_len)
952{
953 AGNX_TRACE;
954 return 0;
955}
956
957void agnx_set_bssid(struct agnx_priv *priv, const u8 *bssid)
958{
959 receiver_bssid_set(priv, bssid);
960}
diff --git a/drivers/staging/agnx/phy.h b/drivers/staging/agnx/phy.h
deleted file mode 100644
index a955f05361e..00000000000
--- a/drivers/staging/agnx/phy.h
+++ /dev/null
@@ -1,409 +0,0 @@
1#ifndef AGNX_PHY_H_
2#define AGNX_PHY_H_
3
4#include "agnx.h"
5
6/* Transmission Managment Registers */
7#define AGNX_TXM_BASE 0x0000
8#define AGNX_TXM_CTL 0x0000 /* control register */
9#define AGNX_TXM_ETMF 0x0004 /* enable transmission management functions */
10#define AGNX_TXM_TXTEMP 0x0008 /* transmission template */
11#define AGNX_TXM_RETRYSTAID 0x000c /* Retry Station ID */
12#define AGNX_TXM_TIMESTAMPLO 0x0010 /* Timestamp Lo */
13#define AGNX_TXM_TIMESTAMPHI 0x0014 /* Timestamp Hi */
14#define AGNX_TXM_TXDELAY 0x0018 /* tx delay */
15#define AGNX_TXM_TBTTLO 0x0020 /* tbtt Lo */
16#define AGNX_TXM_TBTTHI 0x0024 /* tbtt Hi */
17#define AGNX_TXM_BEAINTER 0x0028 /* Beacon Interval */
18#define AGNX_TXM_NAV 0x0030 /* NAV */
19#define AGNX_TXM_CFPMDV 0x0034 /* CFP MDV */
20#define AGNX_TXM_CFPERCNT 0x0038 /* CFP period count */
21#define AGNX_TXM_PROBDELAY 0x003c /* probe delay */
22#define AGNX_TXM_LISINTERCNT 0x0040 /* listen interval count */
23#define AGNX_TXM_DTIMPERICNT 0x004c /* DTIM period count */
24
25#define AGNX_TXM_BEACON_CTL 0x005c /* beacon control */
26
27#define AGNX_TXM_SCHEMPCNT 0x007c /* schedule empty count */
28#define AGNX_TXM_MAXTIMOUT 0x0084 /* max timeout exceed count */
29#define AGNX_TXM_MAXCFPTIM 0x0088 /* max CF poll timeout count */
30#define AGNX_TXM_MAXRXTIME 0x008c /* max RX timeout count */
31#define AGNX_TXM_MAXACKTIM 0x0090 /* max ACK timeout count */
32#define AGNX_TXM_DIF01 0x00a0 /* DIF 0-1 */
33#define AGNX_TXM_DIF23 0x00a4 /* DIF 2-3 */
34#define AGNX_TXM_DIF45 0x00a8 /* DIF 4-5 */
35#define AGNX_TXM_DIF67 0x00ac /* DIF 6-7 */
36#define AGNX_TXM_SIFSPIFS 0x00b0 /* SIFS/PIFS */
37#define AGNX_TXM_TIFSEIFS 0x00b4 /* TIFS/EIFS */
38#define AGNX_TXM_MAXCCACNTSLOT 0x00b8 /* max CCA count slot */
39#define AGNX_TXM_SLOTLIMIT 0x00bc /* slot limit/1 msec limit */
40#define AGNX_TXM_CFPOLLRXTIM 0x00f0 /* CF poll RX timeout count */
41#define AGNX_TXM_CFACKT11B 0x00f4 /* CF ack timeout limit for 11b */
42#define AGNX_TXM_CW0 0x0100 /* CW 0 */
43#define AGNX_TXM_SLBEALIM0 0x0108 /* short/long beacon limit 0 */
44#define AGNX_TXM_CW1 0x0120 /* CW 1 */
45#define AGNX_TXM_SLBEALIM1 0x0128 /* short/long beacon limit 1 */
46#define AGNX_TXM_CW2 0x0140 /* CW 2 */
47#define AGNX_TXM_SLBEALIM2 0x0148 /* short/long beacon limit 2 */
48#define AGNX_TXM_CW3 0x0160 /* CW 3 */
49#define AGNX_TXM_SLBEALIM3 0x0168 /* short/long beacon limit 3 */
50#define AGNX_TXM_CW4 0x0180 /* CW 4 */
51#define AGNX_TXM_SLBEALIM4 0x0188 /* short/long beacon limit 4 */
52#define AGNX_TXM_CW5 0x01a0 /* CW 5 */
53#define AGNX_TXM_SLBEALIM5 0x01a8 /* short/long beacon limit 5 */
54#define AGNX_TXM_CW6 0x01c0 /* CW 6 */
55#define AGNX_TXM_SLBEALIM6 0x01c8 /* short/long beacon limit 6 */
56#define AGNX_TXM_CW7 0x01e0 /* CW 7 */
57#define AGNX_TXM_SLBEALIM7 0x01e8 /* short/long beacon limit 7 */
58#define AGNX_TXM_BEACONTEMP 0x1000 /* beacon template */
59#define AGNX_TXM_STAPOWTEMP 0x1a00 /* Station Power Template */
60
61/* Receive Management Control Registers */
62#define AGNX_RXM_BASE 0x2000
63#define AGNX_RXM_REQRATE 0x2000 /* requested rate */
64#define AGNX_RXM_MACHI 0x2004 /* first 4 bytes of mac address */
65#define AGNX_RXM_MACLO 0x2008 /* last 2 bytes of mac address */
66#define AGNX_RXM_BSSIDHI 0x200c /* bssid hi */
67#define AGNX_RXM_BSSIDLO 0x2010 /* bssid lo */
68#define AGNX_RXM_HASH_CMD_FLAG 0x2014 /* Flags for the RX Hash Command Default:0 */
69#define AGNX_RXM_HASH_CMD_HIGH 0x2018 /* The High half of the Hash Command */
70#define AGNX_RXM_HASH_CMD_LOW 0x201c /* The Low half of the Hash Command */
71#define AGNX_RXM_ROUTAB 0x2020 /* routing table */
72#define ROUTAB_SUBTYPE_SHIFT 24
73#define ROUTAB_TYPE_SHIFT 28
74#define ROUTAB_STATUS_SHIFT 30
75#define ROUTAB_RW_SHIFT 31
76#define ROUTAB_ROUTE_DROP 0xf00000 /* Drop */
77#define ROUTAB_ROUTE_CPU 0x400000 /* CPU */
78#define ROUTAB_ROUTE_ENCRY 0x500800 /* Encryption */
79#define ROUTAB_ROUTE_RFP 0x800000 /* RFP */
80
81#define ROUTAB_TYPE_MANAG 0x0 /* Management */
82#define ROUTAB_TYPE_CTL 0x1 /* Control */
83#define ROUTAB_TYPE_DATA 0x2 /* Data */
84
85#define ROUTAB_SUBTYPE_DATA 0x0
86#define ROUTAB_SUBTYPE_DATAACK 0x1
87#define ROUTAB_SUBTYPE_DATAPOLL 0x2
88#define ROUTAB_SUBTYPE_DATAPOLLACK 0x3
89#define ROUTAB_SUBTYPE_NULL 0x4 /* NULL */
90#define ROUTAB_SUBTYPE_NULLACK 0x5
91#define ROUTAB_SUBTYPE_NULLPOLL 0x6
92#define ROUTAB_SUBTYPE_NULLPOLLACK 0x7
93#define ROUTAB_SUBTYPE_QOSDATA 0x8 /* QOS DATA */
94#define ROUTAB_SUBTYPE_QOSDATAACK 0x9
95#define ROUTAB_SUBTYPE_QOSDATAPOLL 0xa
96#define ROUTAB_SUBTYPE_QOSDATAACKPOLL 0xb
97#define ROUTAB_SUBTYPE_QOSNULL 0xc
98#define ROUTAB_SUBTYPE_QOSNULLACK 0xd
99#define ROUTAB_SUBTYPE_QOSNULLPOLL 0xe
100#define ROUTAB_SUBTYPE_QOSNULLPOLLACK 0xf
101#define AGNX_RXM_DELAY11 0x2024 /* delay 11(AB) */
102#define AGNX_RXM_SOF_CNT 0x2028 /* SOF Count */
103#define AGNX_RXM_FRAG_CNT 0x202c /* Fragment Count*/
104#define AGNX_RXM_FCS_CNT 0x2030 /* FCS Count */
105#define AGNX_RXM_BSSID_MISS_CNT 0x2034 /* BSSID Miss Count */
106#define AGNX_RXM_PDU_ERR_CNT 0x2038 /* PDU Error Count */
107#define AGNX_RXM_DEST_MISS_CNT 0x203C /* Destination Miss Count */
108#define AGNX_RXM_DROP_CNT 0x2040 /* Drop Count */
109#define AGNX_RXM_ABORT_CNT 0x2044 /* Abort Count */
110#define AGNX_RXM_RELAY_CNT 0x2048 /* Relay Count */
111#define AGNX_RXM_HASH_MISS_CNT 0x204c /* Hash Miss Count */
112#define AGNX_RXM_SA_HI 0x2050 /* Address of received packet Hi */
113#define AGNX_RXM_SA_LO 0x2054 /* Address of received packet Lo */
114#define AGNX_RXM_HASH_DUMP_LST 0x2100 /* Contains Hash Data */
115#define AGNX_RXM_HASH_DUMP_MST 0x2104 /* Contains Hash Data */
116#define AGNX_RXM_HASH_DUMP_DATA 0x2108 /* The Station ID to dump */
117
118
119/* Encryption Managment */
120#define AGNX_ENCRY_BASE 0x2400
121#define AGNX_ENCRY_WEPKEY0 0x2440 /* wep key #0 */
122#define AGNX_ENCRY_WEPKEY1 0x2444 /* wep key #1 */
123#define AGNX_ENCRY_WEPKEY2 0x2448 /* wep key #2 */
124#define AGNX_ENCRY_WEPKEY3 0x244c /* wep key #3 */
125#define AGNX_ENCRY_CCMRECTL 0x2460 /* ccm replay control */
126
127
128/* Band Management Registers */
129#define AGNX_BM_BASE 0x2c00
130#define AGNX_BM_BMCTL 0x2c00 /* band management control */
131#define AGNX_BM_TXWADDR 0x2c18 /* tx workqueue address start */
132#define AGNX_BM_TXTOPEER 0x2c24 /* transmit to peers */
133#define AGNX_BM_FPLHP 0x2c2c /* free pool list head pointer */
134#define AGNX_BM_FPLTP 0x2c30 /* free pool list tail pointer */
135#define AGNX_BM_FPCNT 0x2c34 /* free pool count */
136#define AGNX_BM_CIPDUWCNT 0x2c38 /* card interface pdu workqueue count */
137#define AGNX_BM_SPPDUWCNT 0x2c3c /* sp pdu workqueue count */
138#define AGNX_BM_RFPPDUWCNT 0x2c40 /* rfp pdu workqueue count */
139#define AGNX_BM_RHPPDUWCNT 0x2c44 /* rhp pdu workqueue count */
140#define AGNX_BM_CIWQCTL 0x2c48 /* Card Interface WorkQueue Control */
141#define AGNX_BM_CPUTXWCTL 0x2c50 /* cpu tx workqueue control */
142#define AGNX_BM_CPURXWCTL 0x2c58 /* cpu rx workqueue control */
143#define AGNX_BM_CPULWCTL 0x2c60 /* cpu low workqueue control */
144#define AGNX_BM_CPUHWCTL 0x2c68 /* cpu high workqueue control */
145#define AGNX_BM_SPTXWCTL 0x2c70 /* sp tx workqueue control */
146#define AGNX_BM_SPRXWCTL 0x2c78 /* sp rx workqueue control */
147#define AGNX_BM_RFPWCTL 0x2c80 /* RFP workqueue control */
148#define AGNX_BM_MTSM 0x2c90 /* Multicast Transmit Station Mask */
149
150/* Card Interface Registers (32bits) */
151#define AGNX_CIR_BASE 0x3000
152#define AGNX_CIR_BLKCTL 0x3000 /* block control*/
153#define AGNX_STAT_TX 0x1
154#define AGNX_STAT_RX 0x2
155#define AGNX_STAT_X 0x4
156/* Below two interrupt flags will be set by our but not CPU or the card */
157#define AGNX_STAT_TXD 0x10
158#define AGNX_STAT_TXM 0x20
159
160#define AGNX_CIR_ADDRWIN 0x3004 /* Addressable Windows*/
161#define AGNX_CIR_ENDIAN 0x3008 /* card endianness */
162#define AGNX_CIR_SERIALITF 0x3020 /* serial interface */
163#define AGNX_CIR_RXCFG 0x3040 /* receive config */
164#define ENABLE_RX_INTERRUPT 0x20
165#define RX_CACHE_LINE 0x8
166/* the RX fragment length */
167#define FRAG_LEN_256 0x0 /* 256B */
168#define FRAG_LEN_512 0x1
169#define FRAG_LEN_1024 0x2
170#define FRAG_LEN_2048 0x3
171#define FRAG_BE 0x10
172#define AGNX_CIR_RXCTL 0x3050 /* receive control */
173/* memory address, chipside */
174#define AGNX_CIR_RXCMSTART 0x3054 /* receive client memory start */
175#define AGNX_CIR_RXCMEND 0x3058 /* receive client memory end */
176/* memory address, pci */
177#define AGNX_CIR_RXHOSTADDR 0x3060 /* receive hostside address */
178/* memory address, chipside */
179#define AGNX_CIR_RXCLIADDR 0x3064 /* receive clientside address */
180#define AGNX_CIR_RXDMACTL 0x3068 /* receive dma control */
181#define AGNX_CIR_TXCFG 0x3080 /* transmit config */
182#define AGNX_CIR_TXMCTL 0x3090 /* Transmit Management Control */
183#define ENABLE_TX_INTERRUPT 0x20
184#define TX_CACHE_LINE 0x8
185#define AGNX_CIR_TXMSTART 0x3094 /* Transmit Management Start */
186#define AGNX_CIR_TXMEND 0x3098 /* Transmit Management End */
187#define AGNX_CIR_TXDCTL 0x30a0 /* transmit data control */
188/* memeory address, chipset */
189#define AGNX_CIR_TXDSTART 0x30a4 /* transmit data start */
190#define AGNX_CIR_TXDEND 0x30a8 /* transmit data end */
191#define AGNX_CIR_TXMHADDR 0x30b0 /* Transmit Management Hostside Address */
192#define AGNX_CIR_TXMCADDR 0x30b4 /* Transmit Management Clientside Address */
193#define AGNX_CIR_TXDMACTL 0x30b8 /* transmit dma control */
194
195
196/* Power Managment Unit */
197#define AGNX_PM_BASE 0x3c00
198#define AGNX_PM_PMCTL 0x3c00 /* PM Control*/
199#define AGNX_PM_MACMSW 0x3c08 /* MAC Manual Slow Work Enable */
200#define AGNX_PM_RFCTL 0x3c0c /* RF Control */
201#define AGNX_PM_PHYMW 0x3c14 /* Phy Mannal Work */
202#define AGNX_PM_SOFTRST 0x3c18 /* PMU Soft Reset */
203#define AGNX_PM_PLLCTL 0x3c1c /* PMU PLL control*/
204#define AGNX_PM_TESTPHY 0x3c24 /* PMU Test Phy */
205
206
207/* Interrupt Control interface */
208#define AGNX_INT_BASE 0x4000
209#define AGNX_INT_STAT 0x4000 /* interrupt status */
210#define AGNX_INT_MASK 0x400c /* interrupt mask */
211/* FIXME */
212#define IRQ_TX_BEACON 0x1 /* TX Beacon */
213#define IRQ_TX_RETRY 0x8 /* TX Retry Interrupt */
214#define IRQ_TX_ACTIVITY 0x10 /* TX Activity */
215#define IRQ_RX_ACTIVITY 0x20 /* RX Activity */
216/* FIXME I guess that instead RX a none exist staion's packet or
217 the station hasn't been init */
218#define IRQ_RX_X 0x40
219#define IRQ_RX_Y 0x80 /* RX ? */
220#define IRQ_RX_HASHHIT 0x100 /* RX Hash Hit */
221#define IRQ_RX_FRAME 0x200 /* RX Frame */
222#define IRQ_ERR_INT 0x400 /* Error Interrupt */
223#define IRQ_TX_QUE_FULL 0x800 /* TX Workqueue Full */
224#define IRQ_BANDMAN_ERR 0x10000 /* Bandwidth Management Error */
225#define IRQ_TX_DISABLE 0x20000 /* TX Disable */
226#define IRQ_RX_IVASESKEY 0x80000 /* RX Invalid Session Key */
227#define IRQ_RX_KEYIDMIS 0x100000 /* RX key ID Mismatch */
228#define IRQ_REP_THHIT 0x200000 /* Replay Threshold Hit */
229#define IRQ_TIMER1 0x4000000 /* Timer1 */
230#define IRQ_TIMER_CNT 0x10000000 /* Timer Count */
231#define IRQ_PHY_FASTINT 0x20000000 /* Phy Fast Interrupt */
232#define IRQ_PHY_SLOWINT 0x40000000 /* Phy Slow Interrupt */
233#define IRQ_OTHER 0x80000000 /* Unknow interrupt */
234#define AGNX_IRQ_ALL 0xffffffff
235
236/* System Interface */
237#define AGNX_SYSITF_BASE 0x4400
238#define AGNX_SYSITF_SYSMODE 0x4400 /* system mode */
239#define AGNX_SYSITF_GPIOIN 0x4410 /* GPIO In */
240/* PIN lines for leds? */
241#define AGNX_SYSITF_GPIOUT 0x4414 /* GPIO Out */
242
243/* Timer Control */
244#define AGNX_TIMCTL_TIMER1 0x4800 /* Timer 1 */
245#define AGNX_TIMCTL_TIM1CTL 0x4808 /* Timer 1 Control */
246
247
248/* Antenna Calibration Interface */
249#define AGNX_ACI_BASE 0x5000
250#define AGNX_ACI_MODE 0x5000 /* Mode */
251#define AGNX_ACI_MEASURE 0x5004 /* Measure */
252#define AGNX_ACI_SELCHAIN 0x5008 /* Select Chain */
253#define AGNX_ACI_LEN 0x500c /* Length */
254#define AGNX_ACI_TIMER1 0x5018 /* Timer 1 */
255#define AGNX_ACI_TIMER2 0x501c /* Timer 2 */
256#define AGNX_ACI_OFFSET 0x5020 /* Offset */
257#define AGNX_ACI_STATUS 0x5030 /* Status */
258#define CALI_IDLE 0x0
259#define CALI_DONE 0x1
260#define CALI_BUSY 0x2
261#define CALI_ERR 0x3
262#define AGNX_ACI_AICCHA0OVE 0x5034 /* AIC Channel 0 Override */
263#define AGNX_ACI_AICCHA1OVE 0x5038 /* AIC Channel 1 Override */
264
265/* Gain Control Registers */
266#define AGNX_GCR_BASE 0x9000
267/* threshold of primary antenna */
268#define AGNX_GCR_THD0A 0x9000 /* threshold? D0 A */
269/* low threshold of primary antenna */
270#define AGNX_GCR_THD0AL 0x9004 /* threshold? D0 A low */
271/* threshold of secondary antenna */
272#define AGNX_GCR_THD0B 0x9008 /* threshold? D0_B */
273#define AGNX_GCR_DUNSAT 0x900c /* d unsaturated */
274#define AGNX_GCR_DSAT 0x9010 /* d saturated */
275#define AGNX_GCR_DFIRCAL 0x9014 /* D Fir/Cal */
276#define AGNX_GCR_DGCTL11A 0x9018 /* d gain control 11a */
277#define AGNX_GCR_DGCTL11B 0x901c /* d gain control 11b */
278/* strength of gain */
279#define AGNX_GCR_GAININIT 0x9020 /* gain initialization */
280#define AGNX_GCR_THNOSIG 0x9024 /* threhold no signal */
281#define AGNX_GCR_COARSTEP 0x9028 /* coarse stepping */
282#define AGNX_GCR_SIFST11A 0x902c /* sifx time 11a */
283#define AGNX_GCR_SIFST11B 0x9030 /* sifx time 11b */
284#define AGNX_GCR_CWDETEC 0x9034 /* cw detection */
285#define AGNX_GCR_0X38 0x9038 /* ???? */
286#define AGNX_GCR_BOACT 0x903c /* BO Active */
287#define AGNX_GCR_BOINACT 0x9040 /* BO Inactive */
288#define AGNX_GCR_BODYNA 0x9044 /* BO dynamic */
289/* 802.11 mode(a,b,g) */
290#define AGNX_GCR_DISCOVMOD 0x9048 /* discovery mode */
291#define AGNX_GCR_NLISTANT 0x904c /* number of listening antenna */
292#define AGNX_GCR_NACTIANT 0x9050 /* number of active antenna */
293#define AGNX_GCR_NMEASANT 0x9054 /* number of measuring antenna */
294#define AGNX_GCR_NCAPTANT 0x9058 /* number of capture antenna */
295#define AGNX_GCR_THCAP11A 0x905c /* threshold capture 11a */
296#define AGNX_GCR_THCAP11B 0x9060 /* threshold capture 11b */
297#define AGNX_GCR_THCAPRX11A 0x9064 /* threshold capture rx 11a */
298#define AGNX_GCR_THCAPRX11B 0x9068 /* threshold capture rx 11b */
299#define AGNX_GCR_THLEVDRO 0x906c /* threshold level drop */
300#define AGNX_GCR_GAINSET0 0x9070 /* Gainset 0 */
301#define AGNX_GCR_GAINSET1 0x9074 /* Gainset 1 */
302#define AGNX_GCR_GAINSET2 0x9078 /* Gainset 2 */
303#define AGNX_GCR_MAXRXTIME11A 0x907c /* maximum rx time 11a */
304#define AGNX_GCR_MAXRXTIME11B 0x9080 /* maximum rx time 11b */
305#define AGNX_GCR_CORRTIME 0x9084 /* correction time */
306/* reset the subsystem, 0 = disable, 1 = enable */
307#define AGNX_GCR_RSTGCTL 0x9088 /* reset gain control */
308/* channel receiving */
309#define AGNX_GCR_RXCHANEL 0x908c /* receive channel */
310#define AGNX_GCR_NOISE0 0x9090 /* Noise 0 */
311#define AGNX_GCR_NOISE1 0x9094 /* Noise 1 */
312#define AGNX_GCR_NOISE2 0x9098 /* Noise 2 */
313#define AGNX_GCR_SIGHTH 0x909c /* Signal High Threshold */
314#define AGNX_GCR_SIGLTH 0x90a0 /* Signal Low Threshold */
315#define AGNX_GCR_CORRDROP 0x90a4 /* correction drop */
316/* threshold of tertiay antenna */
317#define AGNX_GCR_THCD 0x90a8 /* threshold? CD */
318#define AGNX_GCR_THCS 0x90ac /* threshold? CS */
319#define AGNX_GCR_MAXPOWDIFF 0x90b8 /* maximum power difference */
320#define AGNX_GCR_TRACNT4 0x90ec /* Transition Count 4 */
321#define AGNX_GCR_TRACNT5 0x90f0 /* transition count 5 */
322#define AGNX_GCR_TRACNT6 0x90f4 /* transition count 6 */
323#define AGNX_GCR_TRACNT7 0x90f8 /* transition coutn 7 */
324#define AGNX_GCR_TESTBUS 0x911c /* test bus */
325#define AGNX_GCR_CHAINNUM 0x9120 /* Number of Chains */
326#define AGNX_GCR_ANTCFG 0x9124 /* Antenna Config */
327#define AGNX_GCR_THJUMP 0x912c /* threhold jump */
328#define AGNX_GCR_THPOWER 0x9130 /* threshold power */
329#define AGNX_GCR_THPOWCLIP 0x9134 /* threshold power clip*/
330#define AGNX_GCR_FORCECTLCLK 0x9138 /* Force Gain Control Clock */
331#define AGNX_GCR_GAINSETWRITE 0x913c /* Gainset Write */
332#define AGNX_GCR_THD0BTFEST 0x9140 /* threshold d0 b tf estimate */
333#define AGNX_GCR_THRX11BPOWMIN 0x9144 /* threshold rx 11b power minimum */
334#define AGNX_GCR_0X14c 0x914c /* ?? */
335#define AGNX_GCR_0X150 0x9150 /* ?? */
336#define AGNX_GCR_RXOVERIDE 0x9194 /* recieve override */
337#define AGNX_GCR_WATCHDOG 0x91b0 /* watchdog timeout */
338
339
340/* Spi Interface */
341#define AGNX_SPI_BASE 0xdc00
342#define AGNX_SPI_CFG 0xdc00 /* spi configuration */
343/* Only accept 16 bits */
344#define AGNX_SPI_WMSW 0xdc04 /* write most significant word */
345/* Only accept 16 bits */
346#define AGNX_SPI_WLSW 0xdc08 /* write least significant word */
347#define AGNX_SPI_CTL 0xdc0c /* spi control */
348#define AGNX_SPI_RMSW 0xdc10 /* read most significant word */
349#define AGNX_SPI_RLSW 0xdc14 /* read least significant word */
350/* SPI Control Mask */
351#define SPI_READ_CTL 0x4000 /* read control */
352#define SPI_BUSY_CTL 0x8000 /* busy control */
353/* RF and synth chips in spi */
354#define RF_CHIP0 0x400
355#define RF_CHIP1 0x800
356#define RF_CHIP2 0x1000
357#define SYNTH_CHIP 0x2000
358
359/* Unknown register */
360#define AGNX_UNKNOWN_BASE 0x7800
361
362/* FIXME MonitorGain */
363#define AGNX_MONGCR_BASE 0x12000
364
365/* Gain Table */
366#define AGNX_GAIN_TABLE 0x12400
367
368/* The initial FIR coefficient table */
369#define AGNX_FIR_BASE 0x19804
370
371#define AGNX_ENGINE_LOOKUP_TBL 0x800
372
373/* eeprom commands */
374#define EEPROM_CMD_NULL 0x0 /* NULL */
375#define EEPROM_CMD_WRITE 0x2 /* write */
376#define EEPROM_CMD_READ 0x3 /* read */
377#define EEPROM_CMD_STATUSREAD 0x5 /* status register read */
378#define EEPROM_CMD_WRITEENABLE 0x6 /* write enable */
379#define EEPROM_CMD_CONFIGURE 0x7 /* configure */
380
381#define EEPROM_DATAFORCOFIGURE 0x6 /* ??? */
382
383/* eeprom address */
384#define EEPROM_ADDR_SUBVID 0x0 /* Sub Vendor ID */
385#define EEPROM_ADDR_SUBSID 0x2 /* Sub System ID */
386#define EEPROM_ADDR_MACADDR 0x146 /* MAC Address */
387#define EEPROM_ADDR_LOTYPE 0x14f /* LO type */
388
389struct agnx_eeprom {
390 u8 data; /* date */
391 u16 address; /* address in EEPROM */
392 u8 cmd; /* command, unknown, status */
393} __attribute__((__packed__));
394
395#define AGNX_EEPROM_COMMAND_SHIFT 5
396#define AGNX_EEPROM_COMMAND_STAT 0x01
397
398void disable_receiver(struct agnx_priv *priv);
399void enable_receiver(struct agnx_priv *priv);
400u8 read_from_eeprom(struct agnx_priv *priv, u16 address);
401void agnx_hw_init(struct agnx_priv *priv);
402int agnx_hw_reset(struct agnx_priv *priv);
403int agnx_set_ssid(struct agnx_priv *priv, u8 *ssid, size_t ssid_len);
404void agnx_set_bssid(struct agnx_priv *priv, const u8 *bssid);
405void enable_power_saving(struct agnx_priv *priv);
406void disable_power_saving(struct agnx_priv *priv);
407void calibrate_antenna_period(unsigned long data);
408
409#endif /* AGNX_PHY_H_ */
diff --git a/drivers/staging/agnx/rf.c b/drivers/staging/agnx/rf.c
deleted file mode 100644
index 42e457a1844..00000000000
--- a/drivers/staging/agnx/rf.c
+++ /dev/null
@@ -1,893 +0,0 @@
1/**
2 * Airgo MIMO wireless driver
3 *
4 * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
5
6 * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
7 * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
8
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation;
12 */
13
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include "agnx.h"
17#include "debug.h"
18#include "phy.h"
19#include "table.h"
20
21/* FIXME! */
22static inline void spi_write(void __iomem *region, u32 chip_ids, u32 sw,
23 u16 size, u32 control)
24{
25 u32 reg;
26 u32 lsw = sw & 0xffff; /* lower 16 bits of sw*/
27 u32 msw = sw >> 16; /* high 16 bits of sw */
28
29 /* FIXME Write Most Significant Word of the 32bit data to MSW */
30 /* FIXME And Least Significant Word to LSW */
31 iowrite32((lsw), region + AGNX_SPI_WLSW);
32 iowrite32((msw), region + AGNX_SPI_WMSW);
33 reg = chip_ids | size | control;
34 /* Write chip id(s), write size and busy control to Control Register */
35 iowrite32((reg), region + AGNX_SPI_CTL);
36 /* Wait for Busy control to clear */
37 spi_delay();
38}
39
40/*
41 * Write to SPI Synth register
42 */
43static inline void spi_sy_write(void __iomem *region, u32 chip_ids, u32 sw)
44{
45 /* FIXME the size 0x15 is a magic value*/
46 spi_write(region, chip_ids, sw, 0x15, SPI_BUSY_CTL);
47}
48
49/*
50 * Write to SPI RF register
51 */
52static inline void spi_rf_write(void __iomem *region, u32 chip_ids, u32 sw)
53{
54 /* FIXME the size 0xd is a magic value*/
55 spi_write(region, chip_ids, sw, 0xd, SPI_BUSY_CTL);
56} /* spi_rf_write */
57
58/*
59 * Write to SPI with Read Control bit set
60 */
61inline void spi_rc_write(void __iomem *region, u32 chip_ids, u32 sw)
62{
63 /* FIXME the size 0xe5 is a magic value */
64 spi_write(region, chip_ids, sw, 0xe5, SPI_BUSY_CTL|SPI_READ_CTL);
65}
66
67/* Get the active chains's count */
68static int get_active_chains(struct agnx_priv *priv)
69{
70 void __iomem *ctl = priv->ctl;
71 int num = 0;
72 u32 reg;
73 AGNX_TRACE;
74
75 spi_rc_write(ctl, RF_CHIP0, 0x21);
76 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
77 if (reg == 1)
78 num++;
79
80 spi_rc_write(ctl, RF_CHIP1, 0x21);
81 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
82 if (reg == 1)
83 num++;
84
85 spi_rc_write(ctl, RF_CHIP2, 0x21);
86 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
87 if (reg == 1)
88 num++;
89
90 spi_rc_write(ctl, RF_CHIP0, 0x26);
91 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
92 if (0x33 != reg)
93 printk(KERN_WARNING PFX "Unmatched rf chips result\n");
94
95 return num;
96} /* get_active_chains */
97
98void rf_chips_init(struct agnx_priv *priv)
99{
100 void __iomem *ctl = priv->ctl;
101 u32 reg;
102 int num;
103 AGNX_TRACE;
104
105 if (priv->revid == 1) {
106 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
107 reg |= 0x8;
108 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);
109 }
110
111 /* Set SPI clock speed to 200NS */
112 reg = agnx_read32(ctl, AGNX_SPI_CFG);
113 reg &= ~0xF;
114 reg |= 0x3;
115 agnx_write32(ctl, AGNX_SPI_CFG, reg);
116
117 /* Set SPI clock speed to 50NS */
118 reg = agnx_read32(ctl, AGNX_SPI_CFG);
119 reg &= ~0xF;
120 reg |= 0x1;
121 agnx_write32(ctl, AGNX_SPI_CFG, reg);
122
123 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1101);
124
125 num = get_active_chains(priv);
126 printk(KERN_INFO PFX "Active chains are %d\n", num);
127
128 reg = agnx_read32(ctl, AGNX_SPI_CFG);
129 reg &= ~0xF;
130 agnx_write32(ctl, AGNX_SPI_CFG, reg);
131
132 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1908);
133} /* rf_chips_init */
134
135
136static u32 channel_tbl[15][9] = {
137 {0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
138 {1, 0x00, 0x00, 0x624, 0x00, 0x1a4, 0x28, 0x00, 0x1e},
139 {2, 0x00, 0x00, 0x615, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
140 {3, 0x00, 0x00, 0x61a, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
141 {4, 0x00, 0x00, 0x61f, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
142 {5, 0x00, 0x00, 0x624, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
143 {6, 0x00, 0x00, 0x61f, 0x00, 0x1b3, 0x28, 0x00, 0x1e},
144 {7, 0x00, 0x00, 0x624, 0x00, 0x1b3, 0x28, 0x00, 0x1e},
145 {8, 0x00, 0x00, 0x629, 0x00, 0x1b3, 0x28, 0x00, 0x1e},
146 {9, 0x00, 0x00, 0x624, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
147 {10, 0x00, 0x00, 0x629, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
148 {11, 0x00, 0x00, 0x62e, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
149 {12, 0x00, 0x00, 0x633, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
150 {13, 0x00, 0x00, 0x628, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
151 {14, 0x00, 0x00, 0x644, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
152};
153
154
155static inline void
156channel_tbl_write(struct agnx_priv *priv, unsigned int channel, unsigned int reg_num)
157{
158 void __iomem *ctl = priv->ctl;
159 u32 reg;
160
161 reg = channel_tbl[channel][reg_num];
162 reg <<= 4;
163 reg |= reg_num;
164 spi_sy_write(ctl, SYNTH_CHIP, reg);
165}
166
167static void synth_freq_set(struct agnx_priv *priv, unsigned int channel)
168{
169 void __iomem *ctl = priv->ctl;
170 u32 reg;
171 AGNX_TRACE;
172
173 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
174
175 /* Set the Clock bits to 50NS */
176 reg = agnx_read32(ctl, AGNX_SPI_CFG);
177 reg &= ~0xF;
178 reg |= 0x1;
179 agnx_write32(ctl, AGNX_SPI_CFG, reg);
180
181 /* Write 0x00c0 to LSW and 0x3 to MSW of Synth Chip */
182 spi_sy_write(ctl, SYNTH_CHIP, 0x300c0);
183
184 spi_sy_write(ctl, SYNTH_CHIP, 0x32);
185
186 /* # Write to Register 1 on the Synth Chip */
187 channel_tbl_write(priv, channel, 1);
188 /* # Write to Register 3 on the Synth Chip */
189 channel_tbl_write(priv, channel, 3);
190 /* # Write to Register 6 on the Synth Chip */
191 channel_tbl_write(priv, channel, 6);
192 /* # Write to Register 5 on the Synth Chip */
193 channel_tbl_write(priv, channel, 5);
194 /* # Write to register 8 on the Synth Chip */
195 channel_tbl_write(priv, channel, 8);
196
197 /* FIXME Clear the clock bits */
198 reg = agnx_read32(ctl, AGNX_SPI_CFG);
199 reg &= ~0xf;
200 agnx_write32(ctl, AGNX_SPI_CFG, reg);
201} /* synth_chip_init */
202
203
204static void antenna_init(struct agnx_priv *priv, int num_antenna)
205{
206 void __iomem *ctl = priv->ctl;
207
208 switch (num_antenna) {
209 case 1:
210 agnx_write32(ctl, AGNX_GCR_NLISTANT, 1);
211 agnx_write32(ctl, AGNX_GCR_NMEASANT, 1);
212 agnx_write32(ctl, AGNX_GCR_NACTIANT, 1);
213 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 1);
214
215 agnx_write32(ctl, AGNX_GCR_ANTCFG, 7);
216 agnx_write32(ctl, AGNX_GCR_BOACT, 34);
217 agnx_write32(ctl, AGNX_GCR_BOINACT, 34);
218 agnx_write32(ctl, AGNX_GCR_BODYNA, 30);
219
220 agnx_write32(ctl, AGNX_GCR_THD0A, 125);
221 agnx_write32(ctl, AGNX_GCR_THD0AL, 100);
222 agnx_write32(ctl, AGNX_GCR_THD0B, 90);
223
224 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 80);
225 agnx_write32(ctl, AGNX_GCR_SIGHTH, 100);
226 agnx_write32(ctl, AGNX_GCR_SIGLTH, 16);
227 break;
228 case 2:
229 agnx_write32(ctl, AGNX_GCR_NLISTANT, 2);
230 agnx_write32(ctl, AGNX_GCR_NMEASANT, 2);
231 agnx_write32(ctl, AGNX_GCR_NACTIANT, 2);
232 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 2);
233 agnx_write32(ctl, AGNX_GCR_ANTCFG, 15);
234 agnx_write32(ctl, AGNX_GCR_BOACT, 36);
235 agnx_write32(ctl, AGNX_GCR_BOINACT, 36);
236 agnx_write32(ctl, AGNX_GCR_BODYNA, 32);
237 agnx_write32(ctl, AGNX_GCR_THD0A, 120);
238 agnx_write32(ctl, AGNX_GCR_THD0AL, 100);
239 agnx_write32(ctl, AGNX_GCR_THD0B, 80);
240 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 70);
241 agnx_write32(ctl, AGNX_GCR_SIGHTH, 100);
242 agnx_write32(ctl, AGNX_GCR_SIGLTH, 32);
243 break;
244 case 3:
245 agnx_write32(ctl, AGNX_GCR_NLISTANT, 3);
246 agnx_write32(ctl, AGNX_GCR_NMEASANT, 3);
247 agnx_write32(ctl, AGNX_GCR_NACTIANT, 3);
248 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 3);
249 agnx_write32(ctl, AGNX_GCR_ANTCFG, 31);
250 agnx_write32(ctl, AGNX_GCR_BOACT, 36);
251 agnx_write32(ctl, AGNX_GCR_BOINACT, 36);
252 agnx_write32(ctl, AGNX_GCR_BODYNA, 32);
253 agnx_write32(ctl, AGNX_GCR_THD0A, 100);
254 agnx_write32(ctl, AGNX_GCR_THD0AL, 100);
255 agnx_write32(ctl, AGNX_GCR_THD0B, 70);
256 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 70);
257 agnx_write32(ctl, AGNX_GCR_SIGHTH, 100);
258 agnx_write32(ctl, AGNX_GCR_SIGLTH, 48);
259/* agnx_write32(ctl, AGNX_GCR_SIGLTH, 16); */
260 break;
261 default:
262 printk(KERN_WARNING PFX "Unknow antenna number\n");
263 }
264} /* antenna_init */
265
266static void chain_update(struct agnx_priv *priv, u32 chain)
267{
268 void __iomem *ctl = priv->ctl;
269 u32 reg;
270 AGNX_TRACE;
271
272 spi_rc_write(ctl, RF_CHIP0, 0x20);
273 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
274
275 if (reg == 0x4)
276 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, reg|0x1000);
277 else if (reg != 0x0)
278 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000);
279 else {
280 if (chain == 3 || chain == 6) {
281 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000);
282 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
283 } else if (chain == 2 || chain == 4) {
284 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, reg|0x1000);
285 spi_rf_write(ctl, RF_CHIP2, 0x1005);
286 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x824);
287 } else if (chain == 1) {
288 spi_rf_write(ctl, RF_CHIP0, reg|0x1000);
289 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1004);
290 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xc36);
291 }
292 }
293
294 spi_rc_write(ctl, RF_CHIP0, 0x22);
295 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
296
297 switch (reg) {
298 case 0:
299 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1005);
300 break;
301 case 1:
302 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
303 break;
304 case 2:
305 if (chain == 6 || chain == 4) {
306 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1202);
307 spi_rf_write(ctl, RF_CHIP2, 0x1005);
308 } else if (chain < 3) {
309 spi_rf_write(ctl, RF_CHIP0, 0x1202);
310 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1005);
311 }
312 break;
313 default:
314 if (chain == 3) {
315 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
316 spi_rf_write(ctl, RF_CHIP2, 0x1201);
317 } else if (chain == 2) {
318 spi_rf_write(ctl, RF_CHIP0, 0x1203);
319 spi_rf_write(ctl, RF_CHIP2, 0x1200);
320 spi_rf_write(ctl, RF_CHIP1, 0x1201);
321 } else if (chain == 1) {
322 spi_rf_write(ctl, RF_CHIP0, 0x1203);
323 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1200);
324 } else if (chain == 4) {
325 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
326 spi_rf_write(ctl, RF_CHIP2, 0x1201);
327 } else {
328 spi_rf_write(ctl, RF_CHIP0, 0x1203);
329 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1201);
330 }
331 }
332} /* chain_update */
333
334static void antenna_config(struct agnx_priv *priv)
335{
336 void __iomem *ctl = priv->ctl;
337 u32 reg;
338 AGNX_TRACE;
339
340 /* Write 0x0 to the TX Management Control Register Enable bit */
341 reg = agnx_read32(ctl, AGNX_TXM_CTL);
342 reg &= ~0x1;
343 agnx_write32(ctl, AGNX_TXM_CTL, reg);
344
345 /* FIXME */
346 /* Set initial value based on number of Antennae */
347 antenna_init(priv, 3);
348
349 /* FIXME Update Power Templates for current valid Stations */
350 /* sta_power_init(priv, 0);*/
351
352 /* FIXME the number of chains should get from eeprom*/
353 chain_update(priv, AGNX_CHAINS_MAX);
354} /* antenna_config */
355
356void calibrate_oscillator(struct agnx_priv *priv)
357{
358 void __iomem *ctl = priv->ctl;
359 u32 reg;
360 AGNX_TRACE;
361
362 spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
363 reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
364 reg |= 0x10;
365 agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
366
367 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 1);
368 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 1);
369
370 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
371
372 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
373 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
374 /* (Residual DC Calibration) to Calibration Mode */
375 agnx_write32(ctl, AGNX_ACI_MODE, 0x2);
376
377 spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x1004);
378 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
379 /* (TX LO Calibration) to Calibration Mode */
380 agnx_write32(ctl, AGNX_ACI_MODE, 0x4);
381
382 do {
383 u32 reg1, reg2, reg3;
384 /* Enable Power Saving Control */
385 enable_power_saving(priv);
386 /* Save the following registers to restore */
387 reg1 = ioread32(ctl + 0x11000);
388 reg2 = ioread32(ctl + 0xec50);
389 reg3 = ioread32(ctl + 0xec54);
390 wmb();
391
392 agnx_write32(ctl, 0x11000, 0xcfdf);
393 agnx_write32(ctl, 0xec50, 0x70);
394 /* Restore the registers */
395 agnx_write32(ctl, 0x11000, reg1);
396 agnx_write32(ctl, 0xec50, reg2);
397 agnx_write32(ctl, 0xec54, reg3);
398 /* Disable Power Saving Control */
399 disable_power_saving(priv);
400 } while (0);
401
402 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0);
403} /* calibrate_oscillator */
404
405
406static void radio_channel_set(struct agnx_priv *priv, unsigned int channel)
407{
408 void __iomem *ctl = priv->ctl;
409 unsigned int freq = priv->band.channels[channel - 1].center_freq;
410 u32 reg;
411 AGNX_TRACE;
412
413 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
414 /* Set SPI Clock to 50 Ns */
415 reg = agnx_read32(ctl, AGNX_SPI_CFG);
416 reg &= ~0xF;
417 reg |= 0x1;
418 agnx_write32(ctl, AGNX_SPI_CFG, reg);
419
420 /* Clear the Disable Tx interrupt bit in Interrupt Mask */
421/* reg = agnx_read32(ctl, AGNX_INT_MASK); */
422/* reg &= ~IRQ_TX_DISABLE; */
423/* agnx_write32(ctl, AGNX_INT_MASK, reg); */
424
425 /* Band Selection */
426 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
427 reg |= 0x8;
428 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);
429
430 /* FIXME Set the SiLabs Chip Frequency */
431 synth_freq_set(priv, channel);
432
433 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
434 reg |= 0x80100030;
435 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
436 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
437 reg |= 0x20009;
438 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
439
440 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, 0x5);
441
442 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1100);
443
444 /* Load the MonitorGain Table */
445 monitor_gain_table_init(priv);
446
447 /* Load the TX Fir table */
448 tx_fir_table_init(priv);
449
450 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
451 reg |= 0x8;
452 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
453
454 spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x22);
455 udelay(80);
456 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
457
458
459 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xff);
460 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
461
462 reg = agnx_read32(ctl, 0xec50);
463 reg |= 0x4f;
464 agnx_write32(ctl, 0xec50, reg);
465
466 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
467 agnx_write32(ctl, 0x11008, 0x1);
468 agnx_write32(ctl, 0x1100c, 0x0);
469 agnx_write32(ctl, 0x11008, 0x0);
470 agnx_write32(ctl, 0xec50, 0xc);
471
472 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
473 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
474 agnx_write32(ctl, 0x11010, 0x6e);
475 agnx_write32(ctl, 0x11014, 0x6c);
476
477 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
478
479 /* Calibrate the Antenna */
480 /* antenna_calibrate(priv); */
481 /* Calibrate the TxLocalOscillator */
482 calibrate_oscillator(priv);
483
484 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
485 reg &= ~0x8;
486 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
487 agnx_write32(ctl, AGNX_GCR_GAININIT, 0xa);
488 agnx_write32(ctl, AGNX_GCR_THCD, 0x0);
489
490 agnx_write32(ctl, 0x11018, 0xb);
491 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x0);
492
493 /* Write Frequency to Gain Control Channel */
494 agnx_write32(ctl, AGNX_GCR_RXCHANEL, freq);
495 /* Write 0x140000/Freq to 0x9c08 */
496 reg = 0x140000/freq;
497 agnx_write32(ctl, 0x9c08, reg);
498
499 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
500 reg &= ~0x80100030;
501 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
502
503 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
504 reg &= ~0x20009;
505 reg |= 0x1;
506 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
507
508 agnx_write32(ctl, AGNX_ACI_MODE, 0x0);
509
510/* FIXME According to Number of Chains: */
511
512/* 1. 1: */
513/* 1. Write 0x1203 to RF Chip 0 */
514/* 2. Write 0x1200 to RF Chips 1 +2 */
515/* 2. 2: */
516/* 1. Write 0x1203 to RF Chip 0 */
517/* 2. Write 0x1200 to RF Chip 2 */
518/* 3. Write 0x1201 to RF Chip 1 */
519/* 3. 3: */
520/* 1. Write 0x1203 to RF Chip 0 */
521/* 2. Write 0x1201 to RF Chip 1 + 2 */
522/* 4. 4: */
523/* 1. Write 0x1203 to RF Chip 0 + 1 */
524/* 2. Write 0x1200 to RF Chip 2 */
525
526/* 5. 6: */
527 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
528 spi_rf_write(ctl, RF_CHIP2, 0x1201);
529
530 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1000);
531 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
532
533 /* FIXME Set the Disable Tx interrupt bit in Interrupt Mask
534 (Or 0x20000 to Interrupt Mask) */
535/* reg = agnx_read32(ctl, AGNX_INT_MASK); */
536/* reg |= IRQ_TX_DISABLE; */
537/* agnx_write32(ctl, AGNX_INT_MASK, reg); */
538
539 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
540 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
541
542 /* Configure the Antenna */
543 antenna_config(priv);
544
545 /* Write 0x0 to Discovery Mode Enable detect G, B, A packet? */
546 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0);
547
548 reg = agnx_read32(ctl, AGNX_RXM_REQRATE);
549 reg |= 0x80000000;
550 agnx_write32(ctl, AGNX_RXM_REQRATE, reg);
551 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
552 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
553
554 /* enable radio on and the power LED */
555 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
556 reg &= ~0x1;
557 reg |= 0x2;
558 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);
559
560 reg = agnx_read32(ctl, AGNX_TXM_CTL);
561 reg |= 0x1;
562 agnx_write32(ctl, AGNX_TXM_CTL, reg);
563} /* radio_channel_set */
564
565static void base_band_filter_calibrate(struct agnx_priv *priv)
566{
567 void __iomem *ctl = priv->ctl;
568
569 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1700);
570 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1001);
571 agnx_write32(ctl, AGNX_GCR_FORCECTLCLK, 0x0);
572 spi_rc_write(ctl, RF_CHIP0, 0x27);
573 spi_rc_write(ctl, RF_CHIP1, 0x27);
574 spi_rc_write(ctl, RF_CHIP2, 0x27);
575 agnx_write32(ctl, AGNX_GCR_FORCECTLCLK, 0x1);
576}
577
578static void print_offset(struct agnx_priv *priv, u32 chain)
579{
580 void __iomem *ctl = priv->ctl;
581 u32 offset;
582
583 iowrite32((chain), ctl + AGNX_ACI_SELCHAIN);
584 udelay(10);
585 offset = (ioread32(ctl + AGNX_ACI_OFFSET));
586 printk(PFX "Chain is 0x%x, Offset is 0x%x\n", chain, offset);
587}
588
589void print_offsets(struct agnx_priv *priv)
590{
591 print_offset(priv, 0);
592 print_offset(priv, 4);
593 print_offset(priv, 1);
594 print_offset(priv, 5);
595 print_offset(priv, 2);
596 print_offset(priv, 6);
597}
598
599
600struct chains {
601 u32 cali; /* calibrate value*/
602
603#define NEED_CALIBRATE 0
604#define SUCCESS_CALIBRATE 1
605 int status;
606};
607
608static void chain_calibrate(struct agnx_priv *priv, struct chains *chains,
609 unsigned int num)
610{
611 void __iomem *ctl = priv->ctl;
612 u32 calibra = chains[num].cali;
613
614 if (num < 3)
615 calibra |= 0x1400;
616 else
617 calibra |= 0x1500;
618
619 switch (num) {
620 case 0:
621 case 4:
622 spi_rf_write(ctl, RF_CHIP0, calibra);
623 break;
624 case 1:
625 case 5:
626 spi_rf_write(ctl, RF_CHIP1, calibra);
627 break;
628 case 2:
629 case 6:
630 spi_rf_write(ctl, RF_CHIP2, calibra);
631 break;
632 default:
633 BUG();
634 }
635} /* chain_calibrate */
636
637static inline void get_calibrete_value(struct agnx_priv *priv, struct chains *chains,
638 unsigned int num)
639{
640 void __iomem *ctl = priv->ctl;
641 u32 offset;
642
643 iowrite32((num), ctl + AGNX_ACI_SELCHAIN);
644 /* FIXME */
645 udelay(10);
646 offset = (ioread32(ctl + AGNX_ACI_OFFSET));
647
648 if (offset < 0xf) {
649 chains[num].status = SUCCESS_CALIBRATE;
650 return;
651 }
652
653 if (num == 0 || num == 1 || num == 2) {
654 if (0 == chains[num].cali)
655 chains[num].cali = 0xff;
656 else
657 chains[num].cali--;
658 } else
659 chains[num].cali++;
660
661 chains[num].status = NEED_CALIBRATE;
662}
663
664static inline void calibra_delay(struct agnx_priv *priv)
665{
666 void __iomem *ctl = priv->ctl;
667 u32 reg;
668 unsigned int i = 100;
669
670 wmb();
671 while (--i) {
672 reg = (ioread32(ctl + AGNX_ACI_STATUS));
673 if (reg == 0x4000)
674 break;
675 udelay(10);
676 }
677 if (!i)
678 printk(PFX "calibration failed\n");
679}
680
681void do_calibration(struct agnx_priv *priv)
682{
683 void __iomem *ctl = priv->ctl;
684 struct chains chains[7];
685 unsigned int i, j;
686 AGNX_TRACE;
687
688 for (i = 0; i < 7; i++) {
689 if (i == 3)
690 continue;
691
692 chains[i].cali = 0x7f;
693 chains[i].status = NEED_CALIBRATE;
694 }
695
696 /* FIXME 0x300 is a magic number */
697 for (j = 0; j < 0x300; j++) {
698 if (chains[0].status == SUCCESS_CALIBRATE &&
699 chains[1].status == SUCCESS_CALIBRATE &&
700 chains[2].status == SUCCESS_CALIBRATE &&
701 chains[4].status == SUCCESS_CALIBRATE &&
702 chains[5].status == SUCCESS_CALIBRATE &&
703 chains[6].status == SUCCESS_CALIBRATE)
704 break;
705
706 /* Attention, there is no chain 3 */
707 for (i = 0; i < 7; i++) {
708 if (i == 3)
709 continue;
710 if (chains[i].status == NEED_CALIBRATE)
711 chain_calibrate(priv, chains, i);
712 }
713 /* Write 0x1 to Calibration Measure */
714 iowrite32((0x1), ctl + AGNX_ACI_MEASURE);
715 calibra_delay(priv);
716
717 for (i = 0; i < 7; i++) {
718 if (i == 3)
719 continue;
720
721 get_calibrete_value(priv, chains, i);
722 }
723 }
724 printk(PFX "Clibrate times is %d\n", j);
725 print_offsets(priv);
726} /* do_calibration */
727
728void antenna_calibrate(struct agnx_priv *priv)
729{
730 void __iomem *ctl = priv->ctl;
731 u32 reg;
732 AGNX_TRACE;
733
734 agnx_write32(ctl, AGNX_GCR_NLISTANT, 0x3);
735 agnx_write32(ctl, AGNX_GCR_NMEASANT, 0x3);
736 agnx_write32(ctl, AGNX_GCR_NACTIANT, 0x3);
737 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 0x3);
738
739 agnx_write32(ctl, AGNX_GCR_ANTCFG, 0x1f);
740 agnx_write32(ctl, AGNX_GCR_BOACT, 0x24);
741 agnx_write32(ctl, AGNX_GCR_BOINACT, 0x24);
742 agnx_write32(ctl, AGNX_GCR_BODYNA, 0x20);
743 agnx_write32(ctl, AGNX_GCR_THD0A, 0x64);
744 agnx_write32(ctl, AGNX_GCR_THD0AL, 0x64);
745 agnx_write32(ctl, AGNX_GCR_THD0B, 0x46);
746 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 0x3c);
747 agnx_write32(ctl, AGNX_GCR_SIGHTH, 0x64);
748 agnx_write32(ctl, AGNX_GCR_SIGLTH, 0x30);
749
750 spi_rc_write(ctl, RF_CHIP0, 0x20);
751 /* Fixme */
752 udelay(80);
753 /* 1. Should read 0x0 */
754 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
755 if (0x0 != reg)
756 printk(KERN_WARNING PFX "Unmatched rf chips result\n");
757 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1000);
758
759 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
760
761 spi_rc_write(ctl, RF_CHIP0, 0x22);
762 udelay(80);
763 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
764 if (0x0 != reg)
765 printk(KERN_WARNING PFX "Unmatched rf chips result\n");
766 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1005);
767
768 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
769 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
770
771 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
772 reg |= 0x1c000032;
773 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
774 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
775 reg |= 0x0003f07;
776 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
777
778 reg = agnx_read32(ctl, 0xec50);
779 reg |= 0x40;
780 agnx_write32(ctl, 0xec50, reg);
781
782 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xff8);
783 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
784
785 agnx_write32(ctl, AGNX_GCR_CHAINNUM, 0x6);
786 agnx_write32(ctl, 0x19874, 0x0);
787 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1700);
788
789 /* Calibrate the BaseBandFilter */
790 base_band_filter_calibrate(priv);
791
792 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002);
793
794 agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
795 agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
796 agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);
797 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);
798
799 agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
800 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
801
802 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
803 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
804
805 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400);
806 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500);
807
808 /* Measure Calibration */
809 agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
810 calibra_delay(priv);
811
812 /* do calibration */
813 do_calibration(priv);
814
815 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
816 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
817 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
818 agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
819
820 reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
821 reg &= 0xf;
822 agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
823 reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
824 reg &= 0xf;
825 agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
826 reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
827 reg &= 0xf;
828 agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);
829
830 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);
831 disable_receiver(priv);
832} /* antenna_calibrate */
833
834void __antenna_calibrate(struct agnx_priv *priv)
835{
836 void __iomem *ctl = priv->ctl;
837 u32 reg;
838
839 /* Calibrate the BaseBandFilter */
840 /* base_band_filter_calibrate(priv); */
841 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002);
842
843
844 agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
845 agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
846 agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);
847
848 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);
849
850 agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
851 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
852
853
854 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
855 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
856 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400);
857 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500);
858 /* Measure Calibration */
859 agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
860 calibra_delay(priv);
861 do_calibration(priv);
862 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
863
864 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
865 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
866
867 agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
868
869 reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
870 reg &= 0xf;
871 agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
872 reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
873 reg &= 0xf;
874 agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
875 reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
876 reg &= 0xf;
877 agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);
878
879
880 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);
881
882 /* Write 0x3 Gain Control Discovery Mode */
883 enable_receiver(priv);
884}
885
886int agnx_set_channel(struct agnx_priv *priv, unsigned int channel)
887{
888 AGNX_TRACE;
889
890 printk(KERN_ERR PFX "Channel is %d %s\n", channel, __func__);
891 radio_channel_set(priv, channel);
892 return 0;
893}
diff --git a/drivers/staging/agnx/sta.c b/drivers/staging/agnx/sta.c
deleted file mode 100644
index 3e7db5e2811..00000000000
--- a/drivers/staging/agnx/sta.c
+++ /dev/null
@@ -1,218 +0,0 @@
1#include <linux/delay.h>
2#include <linux/etherdevice.h>
3#include "phy.h"
4#include "sta.h"
5#include "debug.h"
6
7void hash_read(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id)
8{
9 void __iomem *ctl = priv->ctl;
10
11 reglo &= 0xFFFF;
12 reglo |= 0x30000000;
13 reglo |= 0x40000000; /* Set status busy */
14 reglo |= sta_id << 16;
15
16 iowrite32(0, ctl + AGNX_RXM_HASH_CMD_FLAG);
17 iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH);
18 iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
19
20 reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH);
21 reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
22 printk(PFX "RX hash cmd are : %.8x%.8x\n", reghi, reglo);
23}
24
25void hash_write(struct agnx_priv *priv, const u8 *mac_addr, u8 sta_id)
26{
27 void __iomem *ctl = priv->ctl;
28 u32 reghi, reglo;
29
30 if (!is_valid_ether_addr(mac_addr))
31 printk(KERN_WARNING PFX "Update hash table: Invalid hwaddr!\n");
32
33 reghi = mac_addr[0] << 24 | mac_addr[1] << 16 | mac_addr[2] << 8 | mac_addr[3];
34 reglo = mac_addr[4] << 8 | mac_addr[5];
35 reglo |= 0x10000000; /* Set hash commmand */
36 reglo |= 0x40000000; /* Set status busy */
37 reglo |= sta_id << 16;
38
39 iowrite32(0, ctl + AGNX_RXM_HASH_CMD_FLAG);
40 iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH);
41 iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
42
43 reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
44 if (!(reglo & 0x80000000))
45 printk(KERN_WARNING PFX "Update hash table failed\n");
46}
47
48void hash_delete(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id)
49{
50 void __iomem *ctl = priv->ctl;
51
52 reglo &= 0xFFFF;
53 reglo |= 0x20000000;
54 reglo |= 0x40000000; /* Set status busy */
55 reglo |= sta_id << 16;
56
57 iowrite32(0, ctl + AGNX_RXM_HASH_CMD_FLAG);
58 iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH);
59 iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
60 reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH);
61
62 reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
63 printk(PFX "RX hash cmd are : %.8x%.8x\n", reghi, reglo);
64
65}
66
67void hash_dump(struct agnx_priv *priv, u8 sta_id)
68{
69 void __iomem *ctl = priv->ctl;
70 u32 reghi, reglo;
71
72 reglo = 0x40000000; /* status bit */
73 iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
74 iowrite32(sta_id << 16, ctl + AGNX_RXM_HASH_DUMP_DATA);
75
76 udelay(80);
77
78 reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH);
79 reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
80 printk(PFX "hash cmd are : %.8x%.8x\n", reghi, reglo);
81 reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_FLAG);
82 printk(PFX "hash flag is : %.8x\n", reghi);
83 reghi = ioread32(ctl + AGNX_RXM_HASH_DUMP_MST);
84 reglo = ioread32(ctl + AGNX_RXM_HASH_DUMP_LST);
85 printk(PFX "hash dump mst lst: %.8x%.8x\n", reghi, reglo);
86 reghi = ioread32(ctl + AGNX_RXM_HASH_DUMP_DATA);
87 printk(PFX "hash dump data: %.8x\n", reghi);
88}
89
90void get_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx)
91{
92 void __iomem *ctl = priv->ctl;
93 memcpy_fromio(power, ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx,
94 sizeof(*power));
95}
96
97inline void
98set_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx)
99{
100 void __iomem *ctl = priv->ctl;
101 /* FIXME 2. Write Template to offset + station number */
102 memcpy_toio(ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx,
103 power, sizeof(*power));
104}
105
106
107void get_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
108 unsigned int sta_idx, unsigned int wq_idx)
109{
110 void __iomem *data = priv->data;
111 memcpy_fromio(tx_wq, data + AGNX_PDU_TX_WQ + sizeof(*tx_wq) * STA_TX_WQ_NUM * sta_idx +
112 sizeof(*tx_wq) * wq_idx, sizeof(*tx_wq));
113
114}
115
116inline void set_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
117 unsigned int sta_idx, unsigned int wq_idx)
118{
119 void __iomem *data = priv->data;
120 memcpy_toio(data + AGNX_PDU_TX_WQ + sizeof(*tx_wq) * STA_TX_WQ_NUM * sta_idx +
121 sizeof(*tx_wq) * wq_idx, tx_wq, sizeof(*tx_wq));
122}
123
124
125void get_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx)
126{
127 void __iomem *data = priv->data;
128
129 memcpy_fromio(sta, data + AGNX_PDUPOOL + sizeof(*sta) * sta_idx,
130 sizeof(*sta));
131}
132
133inline void set_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx)
134{
135 void __iomem *data = priv->data;
136
137 memcpy_toio(data + AGNX_PDUPOOL + sizeof(*sta) * sta_idx,
138 sta, sizeof(*sta));
139}
140
141/* FIXME */
142void sta_power_init(struct agnx_priv *priv, unsigned int sta_idx)
143{
144 struct agnx_sta_power power;
145 u32 reg;
146 AGNX_TRACE;
147
148 memset(&power, 0, sizeof(power));
149 reg = agnx_set_bits(EDCF, EDCF_SHIFT, 0x1);
150 power.reg = cpu_to_le32(reg);
151 set_sta_power(priv, &power, sta_idx);
152 udelay(40);
153} /* add_power_template */
154
155
156/* @num: The #number of station that is visible to the card */
157static void sta_tx_workqueue_init(struct agnx_priv *priv, unsigned int sta_idx)
158{
159 struct agnx_sta_tx_wq tx_wq;
160 u32 reg;
161 unsigned int i;
162
163 memset(&tx_wq, 0, sizeof(tx_wq));
164
165 reg = agnx_set_bits(WORK_QUEUE_VALID, WORK_QUEUE_VALID_SHIFT, 1);
166 reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 1);
167/* reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 0); */
168 tx_wq.reg2 |= cpu_to_le32(reg);
169
170 /* Suppose all 8 traffic class are used */
171 for (i = 0; i < STA_TX_WQ_NUM; i++)
172 set_sta_tx_wq(priv, &tx_wq, sta_idx, i);
173} /* sta_tx_workqueue_init */
174
175
176static void sta_traffic_init(struct agnx_sta_traffic *traffic)
177{
178 u32 reg;
179 memset(traffic, 0, sizeof(*traffic));
180
181 reg = agnx_set_bits(NEW_PACKET, NEW_PACKET_SHIFT, 1);
182 reg |= agnx_set_bits(TRAFFIC_VALID, TRAFFIC_VALID_SHIFT, 1);
183/* reg |= agnx_set_bits(TRAFFIC_ACK_TYPE, TRAFFIC_ACK_TYPE_SHIFT, 1); */
184 traffic->reg0 = cpu_to_le32(reg);
185
186 /* 3. setting RX Sequence Number to 4095 */
187 reg = agnx_set_bits(RX_SEQUENCE_NUM, RX_SEQUENCE_NUM_SHIFT, 4095);
188 traffic->reg1 = cpu_to_le32(reg);
189}
190
191
192/* @num: The #number of station that is visible to the card */
193void sta_init(struct agnx_priv *priv, unsigned int sta_idx)
194{
195 /* FIXME the length of sta is 256 bytes Is that
196 * dangerous to stack overflow? */
197 struct agnx_sta sta;
198 u32 reg;
199 int i;
200
201 memset(&sta, 0, sizeof(sta));
202 /* Set valid to 1 */
203 reg = agnx_set_bits(STATION_VALID, STATION_VALID_SHIFT, 1);
204 /* Set Enable Concatenation to 0 (?) */
205 reg |= agnx_set_bits(ENABLE_CONCATENATION, ENABLE_CONCATENATION_SHIFT, 0);
206 /* Set Enable Decompression to 0 (?) */
207 reg |= agnx_set_bits(ENABLE_DECOMPRESSION, ENABLE_DECOMPRESSION_SHIFT, 0);
208 sta.reg = cpu_to_le32(reg);
209
210 /* Initialize each of the Traffic Class Structures by: */
211 for (i = 0; i < 8; i++)
212 sta_traffic_init(sta.traffic + i);
213
214 set_sta(priv, &sta, sta_idx);
215 sta_tx_workqueue_init(priv, sta_idx);
216} /* sta_descriptor_init */
217
218
diff --git a/drivers/staging/agnx/sta.h b/drivers/staging/agnx/sta.h
deleted file mode 100644
index fd504e3f387..00000000000
--- a/drivers/staging/agnx/sta.h
+++ /dev/null
@@ -1,222 +0,0 @@
1#ifndef AGNX_STA_H_
2#define AGNX_STA_H_
3
4#define STA_TX_WQ_NUM 8 /* The number of TX workqueue one STA has */
5
6struct agnx_hash_cmd {
7 __be32 cmdhi;
8#define MACLO 0xFFFF0000
9#define MACLO_SHIFT 16
10#define STA_ID 0x0000FFF0
11#define STA_ID_SHIFT 4
12#define CMD 0x0000000C
13#define CMD_SHIFT 2
14#define STATUS 0x00000002
15#define STATUS_SHIFT 1
16#define PASS 0x00000001
17#define PASS_SHIFT 1
18 __be32 cmdlo;
19} __attribute__((__packed__));
20
21
22/*
23 * Station Power Template
24 * FIXME Just for agn100 yet
25 */
26struct agnx_sta_power {
27 __le32 reg;
28#define SIGNAL 0x000000FF /* signal */
29#define SIGNAL_SHIFT 0
30#define RATE 0x00000F00
31#define RATE_SHIFT 8
32#define TIFS 0x00001000
33#define TIFS_SHIFT 12
34#define EDCF 0x00002000
35#define EDCF_SHIFT 13
36#define CHANNEL_BOND 0x00004000
37#define CHANNEL_BOND_SHIFT 14
38#define PHY_MODE 0x00038000
39#define PHY_MODE_SHIFT 15
40#define POWER_LEVEL 0x007C0000
41#define POWER_LEVEL_SHIFT 18
42#define NUM_TRANSMITTERS 0x00800000
43#define NUM_TRANSMITTERS_SHIFT 23
44} __attribute__((__packed__));
45
46/*
47 * TX Workqueue Descriptor
48 */
49struct agnx_sta_tx_wq {
50 __le32 reg0;
51#define HEAD_POINTER_LOW 0xFF000000 /* Head pointer low */
52#define HEAD_POINTER_LOW_SHIFT 24
53#define TAIL_POINTER 0x00FFFFFF /* Tail pointer */
54#define TAIL_POINTER_SHIFT 0
55
56 __le32 reg3;
57#define ACK_POINTER_LOW 0xFFFF0000 /* ACK pointer low */
58#define ACK_POINTER_LOW_SHIFT 16
59#define HEAD_POINTER_HIGH 0x0000FFFF /* Head pointer high */
60#define HEAD_POINTER_HIGH_SHIFT 0
61
62 __le32 reg1;
63/* ACK timeout tail packet count */
64#define ACK_TIMOUT_TAIL_PACK_CNT 0xFFF00000
65#define ACK_TIMOUT_TAIL_PACK_CNT_SHIFT 20
66/* Head timeout tail packet count */
67#define HEAD_TIMOUT_TAIL_PACK_CNT 0x000FFF00
68#define HEAD_TIMOUT_TAIL_PACK_CNT_SHIFT 8
69#define ACK_POINTER_HIGH 0x000000FF /* ACK pointer high */
70#define ACK_POINTER_HIGH_SHIFT 0
71
72 __le32 reg2;
73#define WORK_QUEUE_VALID 0x80000000 /* valid */
74#define WORK_QUEUE_VALID_SHIFT 31
75#define WORK_QUEUE_ACK_TYPE 0x40000000 /* ACK type */
76#define WORK_QUEUE_ACK_TYPE_SHIFT 30
77/* Head timeout window limit fragmentation count */
78#define HEAD_TIMOUT_WIN_LIM_FRAG_CNT 0x3FFF0000
79#define HEAD_TIMOUT_WIN_LIM_FRAG_CNT_SHIFT 16
80/* Head timeout window limit byte count */
81#define HEAD_TIMOUT_WIN_LIM_BYTE_CNT 0x0000FFFF
82#define HEAD_TIMOUT_WIN_LIM_BYTE_CNT_SHIFT 0
83} __attribute__((__packed__));
84
85
86/*
87 * Traffic Class Structure
88 */
89struct agnx_sta_traffic {
90 __le32 reg0;
91#define ACK_TIMOUT_CNT 0xFF800000 /* ACK Timeout Counts */
92#define ACK_TIMOUT_CNT_SHIFT 23
93#define TRAFFIC_ACK_TYPE 0x00600000 /* ACK Type */
94#define TRAFFIC_ACK_TYPE_SHIFT 21
95#define NEW_PACKET 0x00100000 /* New Packet */
96#define NEW_PACKET_SHIFT 20
97#define TRAFFIC_VALID 0x00080000 /* Valid */
98#define TRAFFIC_VALID_SHIFT 19
99#define RX_HDR_DESC_POINTER 0x0007FFFF /* RX Header Descripter pointer */
100#define RX_HDR_DESC_POINTER_SHIFT 0
101
102 __le32 reg1;
103#define RX_PACKET_TIMESTAMP 0xFFFF0000 /* RX Packet Timestamp */
104#define RX_PACKET_TIMESTAMP_SHIFT 16
105#define TRAFFIC_RESERVED 0x0000E000 /* Reserved */
106#define TRAFFIC_RESERVED_SHIFT 13
107#define SV 0x00001000 /* sv */
108#define SV_SHIFT 12
109#define RX_SEQUENCE_NUM 0x00000FFF /* RX Sequence Number */
110#define RX_SEQUENCE_NUM_SHIFT 0
111
112 __le32 tx_replay_cnt_low; /* TX Replay Counter Low */
113
114 __le16 tx_replay_cnt_high; /* TX Replay Counter High */
115 __le16 rx_replay_cnt_high; /* RX Replay Counter High */
116
117 __be32 rx_replay_cnt_low; /* RX Replay Counter Low */
118} __attribute__((__packed__));
119
120/*
121 * Station Descriptors
122 */
123struct agnx_sta {
124 __le32 tx_session_keys[4]; /* Transmit Session Key (0-3) */
125 __le32 rx_session_keys[4]; /* Receive Session Key (0-3) */
126
127 __le32 reg;
128#define ID_1 0xC0000000 /* id 1 */
129#define ID_1_SHIFT 30
130#define ID_0 0x30000000 /* id 0 */
131#define ID_0_SHIFT 28
132#define ENABLE_CONCATENATION 0x0FF00000 /* Enable concatenation */
133#define ENABLE_CONCATENATION_SHIFT 20
134#define ENABLE_DECOMPRESSION 0x000FF000 /* Enable decompression */
135#define ENABLE_DECOMPRESSION_SHIFT 12
136#define STA_RESERVED 0x00000C00 /* Reserved */
137#define STA_RESERVED_SHIFT 10
138#define EAP 0x00000200 /* EAP */
139#define EAP_SHIFT 9
140#define ED_NULL 0x00000100 /* ED NULL */
141#define ED_NULL_SHIFT 8
142#define ENCRYPTION_POLICY 0x000000E0 /* Encryption Policy */
143#define ENCRYPTION_POLICY_SHIFT 5
144#define DEFINED_KEY_ID 0x00000018 /* Defined Key ID */
145#define DEFINED_KEY_ID_SHIFT 3
146#define FIXED_KEY 0x00000004 /* Fixed Key */
147#define FIXED_KEY_SHIFT 2
148#define KEY_VALID 0x00000002 /* Key Valid */
149#define KEY_VALID_SHIFT 1
150#define STATION_VALID 0x00000001 /* Station Valid */
151#define STATION_VALID_SHIFT 0
152
153 __le32 tx_aes_blks_unicast; /* TX AES Blks Unicast */
154 __le32 rx_aes_blks_unicast; /* RX AES Blks Unicast */
155
156 __le16 aes_format_err_unicast_cnt; /* AES Format Error Unicast Counts */
157 __le16 aes_replay_unicast; /* AES Replay Unicast */
158
159 __le16 aes_decrypt_err_unicast; /* AES Decrypt Error Unicast */
160 __le16 aes_decrypt_err_default; /* AES Decrypt Error default */
161
162 __le16 single_retry_packets; /* Single Retry Packets */
163 __le16 failed_tx_packets; /* Failed Tx Packets */
164
165 __le16 muti_retry_packets; /* Multiple Retry Packets */
166 __le16 ack_timeouts; /* ACK Timeouts */
167
168 __le16 frag_tx_cnt; /* Fragment TX Counts */
169 __le16 rts_brq_sent; /* RTS Brq Sent */
170
171 __le16 tx_packets; /* TX Packets */
172 __le16 cts_back_timeout; /* CTS Back Timeout */
173
174 __le32 phy_stats_high; /* PHY Stats High */
175 __le32 phy_stats_low; /* PHY Stats Low */
176
177 struct agnx_sta_traffic traffic[8]; /* Traffic Class Structure (8) */
178
179 __le16 traffic_class0_frag_success; /* Traffic Class 0 Fragment Success */
180 __le16 traffic_class1_frag_success; /* Traffic Class 1 Fragment Success */
181 __le16 traffic_class2_frag_success; /* Traffic Class 2 Fragment Success */
182 __le16 traffic_class3_frag_success; /* Traffic Class 3 Fragment Success */
183 __le16 traffic_class4_frag_success; /* Traffic Class 4 Fragment Success */
184 __le16 traffic_class5_frag_success; /* Traffic Class 5 Fragment Success */
185 __le16 traffic_class6_frag_success; /* Traffic Class 6 Fragment Success */
186 __le16 traffic_class7_frag_success; /* Traffic Class 7 Fragment Success */
187
188 __le16 num_frag_non_prime_rates; /* number of Fragments for non-prime rates */
189 __le16 ack_timeout_non_prime_rates; /* ACK Timeout for non-prime rates */
190
191} __attribute__((__packed__));
192
193
194struct agnx_beacon_hdr {
195 struct agnx_sta_power power; /* Tx Station Power Template */
196 u8 phy_hdr[6]; /* PHY Hdr */
197 u8 frame_len_lo; /* Frame Length Lo */
198 u8 frame_len_hi; /* Frame Length Hi */
199 u8 mac_hdr[24]; /* MAC Header */
200 /* FIXME */
201 /* 802.11(abg) beacon */
202} __attribute__((__packed__));
203
204void hash_write(struct agnx_priv *priv, const u8 *mac_addr, u8 sta_id);
205void hash_dump(struct agnx_priv *priv, u8 sta_id);
206void hash_read(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id);
207void hash_delete(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id);
208
209void get_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx);
210void set_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power,
211 unsigned int sta_idx);
212void get_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
213 unsigned int sta_idx, unsigned int wq_idx);
214void set_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
215 unsigned int sta_idx, unsigned int wq_idx);
216void get_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx);
217void set_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx);
218
219void sta_power_init(struct agnx_priv *priv, unsigned int num);
220void sta_init(struct agnx_priv *priv, unsigned int num);
221
222#endif /* AGNX_STA_H_ */
diff --git a/drivers/staging/agnx/table.c b/drivers/staging/agnx/table.c
deleted file mode 100644
index b52fef9db0e..00000000000
--- a/drivers/staging/agnx/table.c
+++ /dev/null
@@ -1,168 +0,0 @@
1#include <linux/pci.h>
2#include <linux/delay.h>
3#include "agnx.h"
4#include "debug.h"
5#include "phy.h"
6
7static const u32
8tx_fir_table[] = { 0x19, 0x5d, 0xce, 0x151, 0x1c3, 0x1ff, 0x1ea, 0x17c, 0xcf,
9 0x19, 0x38e, 0x350, 0x362, 0x3ad, 0x5, 0x44, 0x59, 0x49,
10 0x21, 0x3f7, 0x3e0, 0x3e3, 0x3f3, 0x0 };
11
12void tx_fir_table_init(struct agnx_priv *priv)
13{
14 void __iomem *ctl = priv->ctl;
15 int i;
16
17 for (i = 0; i < ARRAY_SIZE(tx_fir_table); i++)
18 iowrite32(tx_fir_table[i], ctl + AGNX_FIR_BASE + i*4);
19} /* fir_table_setup */
20
21
22static const u32
23gain_table[] = { 0x8, 0x8, 0xf, 0x13, 0x17, 0x1b, 0x1f, 0x23, 0x27, 0x2b,
24 0x2f, 0x33, 0x37, 0x3b, 0x3f, 0x43, 0x47, 0x4b, 0x4f,
25 0x53, 0x57, 0x5b, 0x5f, 0x5f, 0x5f, 0x5f, 0x5f, 0x5f,
26 0x5f, 0x5f, 0x5f, 0x5f };
27
28void gain_table_init(struct agnx_priv *priv)
29{
30 void __iomem *ctl = priv->ctl;
31 int i;
32
33 for (i = 0; i < ARRAY_SIZE(gain_table); i++) {
34 iowrite32(gain_table[i], ctl + AGNX_GAIN_TABLE + i*4);
35 iowrite32(gain_table[i], ctl + AGNX_GAIN_TABLE + i*4 + 0x80);
36 }
37} /* gain_table_init */
38
39void monitor_gain_table_init(struct agnx_priv *priv)
40{
41 void __iomem *ctl = priv->ctl;
42 unsigned int i;
43
44 for (i = 0; i < 0x44; i += 4) {
45 iowrite32(0x61, ctl + AGNX_MONGCR_BASE + i);
46 iowrite32(0x61, ctl + AGNX_MONGCR_BASE + 0x200 + i);
47 }
48 for (i = 0x44; i < 0x64; i += 4) {
49 iowrite32(0x6e, ctl + AGNX_MONGCR_BASE + i);
50 iowrite32(0x6e, ctl + AGNX_MONGCR_BASE + 0x200 + i);
51 }
52 for (i = 0x64; i < 0x94; i += 4) {
53 iowrite32(0x7a, ctl + AGNX_MONGCR_BASE + i);
54 iowrite32(0x7a, ctl + AGNX_MONGCR_BASE + 0x200 + i);
55 }
56 for (i = 0x94; i < 0xdc; i += 4) {
57 iowrite32(0x87, ctl + AGNX_MONGCR_BASE + i);
58 iowrite32(0x87, ctl + AGNX_MONGCR_BASE + 0x200 + i);
59 }
60 for (i = 0xdc; i < 0x148; i += 4) {
61 iowrite32(0x95, ctl + AGNX_MONGCR_BASE + i);
62 iowrite32(0x95, ctl + AGNX_MONGCR_BASE + 0x200 + i);
63 }
64 for (i = 0x148; i < 0x1e8; i += 4) {
65 iowrite32(0xa2, ctl + AGNX_MONGCR_BASE + i);
66 iowrite32(0xa2, ctl + AGNX_MONGCR_BASE + 0x200 + i);
67 }
68 for (i = 0x1e8; i <= 0x1fc; i += 4) {
69 iowrite32(0xb0, ctl + AGNX_MONGCR_BASE + i);
70 iowrite32(0xb0, ctl + AGNX_MONGCR_BASE + 0x200 + i);
71 }
72} /* monitor_gain_table_init */
73
74
75void routing_table_init(struct agnx_priv *priv)
76{
77 void __iomem *ctl = priv->ctl;
78 unsigned int type, subtype;
79 u32 reg;
80
81 disable_receiver(priv);
82
83 for (type = 0; type < 0x3; type++) {
84 for (subtype = 0; subtype < 0x10; subtype++) {
85 /* 1. Set Routing table to R/W and to Return status on Read */
86 reg = (type << ROUTAB_TYPE_SHIFT) |
87 (subtype << ROUTAB_SUBTYPE_SHIFT);
88 reg |= (1 << ROUTAB_RW_SHIFT) | (1 << ROUTAB_STATUS_SHIFT);
89 if (type == ROUTAB_TYPE_DATA) {
90 /* NULL goes to RFP */
91 if (subtype == ROUTAB_SUBTYPE_NULL)
92/* reg |= ROUTAB_ROUTE_RFP; */
93 reg |= ROUTAB_ROUTE_CPU;
94 /* QOS NULL goes to CPU */
95 else if (subtype == ROUTAB_SUBTYPE_QOSNULL)
96 reg |= ROUTAB_ROUTE_CPU;
97 /* All Data and QOS data subtypes go to Encryption */
98 else if ((subtype == ROUTAB_SUBTYPE_DATA) ||
99 (subtype == ROUTAB_SUBTYPE_DATAACK) ||
100 (subtype == ROUTAB_SUBTYPE_DATAPOLL) ||
101 (subtype == ROUTAB_SUBTYPE_DATAPOLLACK) ||
102 (subtype == ROUTAB_SUBTYPE_QOSDATA) ||
103 (subtype == ROUTAB_SUBTYPE_QOSDATAACK) ||
104 (subtype == ROUTAB_SUBTYPE_QOSDATAPOLL) ||
105 (subtype == ROUTAB_SUBTYPE_QOSDATAACKPOLL))
106 reg |= ROUTAB_ROUTE_ENCRY;
107/* reg |= ROUTAB_ROUTE_CPU; */
108 /*Drop NULL and QOS NULL ack, poll and poll ack*/
109 else if ((subtype == ROUTAB_SUBTYPE_NULLACK) ||
110 (subtype == ROUTAB_SUBTYPE_QOSNULLACK) ||
111 (subtype == ROUTAB_SUBTYPE_NULLPOLL) ||
112 (subtype == ROUTAB_SUBTYPE_QOSNULLPOLL) ||
113 (subtype == ROUTAB_SUBTYPE_NULLPOLLACK) ||
114 (subtype == ROUTAB_SUBTYPE_QOSNULLPOLLACK))
115/* reg |= ROUTAB_ROUTE_DROP; */
116 reg |= ROUTAB_ROUTE_CPU;
117 } else {
118 reg |= (ROUTAB_ROUTE_CPU);
119 }
120 iowrite32(reg, ctl + AGNX_RXM_ROUTAB);
121 /* Check to verify that the status bit cleared */
122 routing_table_delay();
123 }
124 }
125 enable_receiver(priv);
126} /* routing_table_init */
127
128void tx_engine_lookup_tbl_init(struct agnx_priv *priv)
129{
130 void __iomem *data = priv->data;
131 unsigned int i;
132
133 for (i = 0; i <= 28; i += 4)
134 iowrite32(0xb00c, data + AGNX_ENGINE_LOOKUP_TBL + i);
135 for (i = 32; i <= 120; i += 8) {
136 iowrite32(0x1e58, data + AGNX_ENGINE_LOOKUP_TBL + i);
137 iowrite32(0xb00c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
138 }
139
140 for (i = 128; i <= 156; i += 4)
141 iowrite32(0x980c, data + AGNX_ENGINE_LOOKUP_TBL + i);
142 for (i = 160; i <= 248; i += 8) {
143 iowrite32(0x1858, data + AGNX_ENGINE_LOOKUP_TBL + i);
144 iowrite32(0x980c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
145 }
146
147 for (i = 256; i <= 284; i += 4)
148 iowrite32(0x980c, data + AGNX_ENGINE_LOOKUP_TBL + i);
149 for (i = 288; i <= 376; i += 8) {
150 iowrite32(0x1a58, data + AGNX_ENGINE_LOOKUP_TBL + i);
151 iowrite32(0x1858, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
152 }
153
154 for (i = 512; i <= 540; i += 4)
155 iowrite32(0xc00c, data + AGNX_ENGINE_LOOKUP_TBL + i);
156 for (i = 544; i <= 632; i += 8) {
157 iowrite32(0x2058, data + AGNX_ENGINE_LOOKUP_TBL + i);
158 iowrite32(0xc00c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
159 }
160
161 for (i = 640; i <= 668; i += 4)
162 iowrite32(0xc80c, data + AGNX_ENGINE_LOOKUP_TBL + i);
163 for (i = 672; i <= 764; i += 8) {
164 iowrite32(0x2258, data + AGNX_ENGINE_LOOKUP_TBL + i);
165 iowrite32(0xc80c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
166 }
167}
168
diff --git a/drivers/staging/agnx/table.h b/drivers/staging/agnx/table.h
deleted file mode 100644
index f0626b5ee86..00000000000
--- a/drivers/staging/agnx/table.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef AGNX_TABLE_H_
2#define AGNX_TABLE_H_
3
4void tx_fir_table_init(struct agnx_priv *priv);
5void gain_table_init(struct agnx_priv *priv);
6void monitor_gain_table_init(struct agnx_priv *priv);
7void routing_table_init(struct agnx_priv *priv);
8void tx_engine_lookup_tbl_init(struct agnx_priv *priv);
9
10#endif /* AGNX_TABLE_H_ */
diff --git a/drivers/staging/agnx/xmit.c b/drivers/staging/agnx/xmit.c
deleted file mode 100644
index 42db41070cf..00000000000
--- a/drivers/staging/agnx/xmit.c
+++ /dev/null
@@ -1,836 +0,0 @@
1/**
2 * Airgo MIMO wireless driver
3 *
4 * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
5
6 * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
7 * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
8
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include "agnx.h"
17#include "debug.h"
18#include "phy.h"
19
20unsigned int rx_frame_cnt;
21/* unsigned int local_tx_sent_cnt = 0; */
22
23static inline void disable_rx_engine(struct agnx_priv *priv)
24{
25 void __iomem *ctl = priv->ctl;
26 iowrite32(0x100, ctl + AGNX_CIR_RXCTL);
27 /* Wait for RX Control to have the Disable Rx Interrupt (0x100) set */
28 ioread32(ctl + AGNX_CIR_RXCTL);
29}
30
31static inline void enable_rx_engine(struct agnx_priv *priv)
32{
33 void __iomem *ctl = priv->ctl;
34 iowrite32(0x80, ctl + AGNX_CIR_RXCTL);
35 ioread32(ctl + AGNX_CIR_RXCTL);
36}
37
38inline void disable_rx_interrupt(struct agnx_priv *priv)
39{
40 void __iomem *ctl = priv->ctl;
41 u32 reg;
42
43 disable_rx_engine(priv);
44 reg = ioread32(ctl + AGNX_CIR_RXCFG);
45 reg &= ~0x20;
46 iowrite32(reg, ctl + AGNX_CIR_RXCFG);
47 ioread32(ctl + AGNX_CIR_RXCFG);
48}
49
50inline void enable_rx_interrupt(struct agnx_priv *priv)
51{
52 void __iomem *ctl = priv->ctl;
53 u32 reg;
54
55 reg = ioread32(ctl + AGNX_CIR_RXCFG);
56 reg |= 0x20;
57 iowrite32(reg, ctl + AGNX_CIR_RXCFG);
58 ioread32(ctl + AGNX_CIR_RXCFG);
59 enable_rx_engine(priv);
60}
61
62static inline void rx_desc_init(struct agnx_priv *priv, unsigned int idx)
63{
64 struct agnx_desc *desc = priv->rx.desc + idx;
65 struct agnx_info *info = priv->rx.info + idx;
66
67 memset(info, 0, sizeof(*info));
68
69 info->dma_len = IEEE80211_MAX_RTS_THRESHOLD + sizeof(struct agnx_hdr);
70 info->skb = dev_alloc_skb(info->dma_len);
71 if (info->skb == NULL)
72 agnx_bug("refill err");
73
74 info->mapping = pci_map_single(priv->pdev, skb_tail_pointer(info->skb),
75 info->dma_len, PCI_DMA_FROMDEVICE);
76 memset(desc, 0, sizeof(*desc));
77 desc->dma_addr = cpu_to_be32(info->mapping);
78 /* Set the owner to the card */
79 desc->frag = cpu_to_be32(be32_to_cpu(desc->frag) | OWNER);
80}
81
82static inline void rx_desc_reinit(struct agnx_priv *priv, unsigned int idx)
83{
84 struct agnx_info *info = priv->rx.info + idx;
85
86 /* Cause ieee80211 will free the skb buffer, so we needn't to free it again?! */
87 pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_FROMDEVICE);
88 rx_desc_init(priv, idx);
89}
90
91static inline void rx_desc_reusing(struct agnx_priv *priv, unsigned int idx)
92{
93 struct agnx_desc *desc = priv->rx.desc + idx;
94 struct agnx_info *info = priv->rx.info + idx;
95
96 memset(desc, 0, sizeof(*desc));
97 desc->dma_addr = cpu_to_be32(info->mapping);
98 /* Set the owner to the card */
99 desc->frag = cpu_to_be32(be32_to_cpu(desc->frag) | OWNER);
100}
101
102static void rx_desc_free(struct agnx_priv *priv, unsigned int idx)
103{
104 struct agnx_desc *desc = priv->rx.desc + idx;
105 struct agnx_info *info = priv->rx.info + idx;
106
107 BUG_ON(!desc || !info);
108 if (info->mapping)
109 pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_FROMDEVICE);
110 if (info->skb)
111 dev_kfree_skb(info->skb);
112 memset(info, 0, sizeof(*info));
113 memset(desc, 0, sizeof(*desc));
114}
115
116static inline void __tx_desc_free(struct agnx_priv *priv,
117 struct agnx_desc *desc, struct agnx_info *info)
118{
119 BUG_ON(!desc || !info);
120 /* TODO make sure mapping, skb and len are consistency */
121 if (info->mapping)
122 pci_unmap_single(priv->pdev, info->mapping,
123 info->dma_len, PCI_DMA_TODEVICE);
124 if (info->type == PACKET)
125 dev_kfree_skb(info->skb);
126
127 memset(info, 0, sizeof(*info));
128 memset(desc, 0, sizeof(*desc));
129}
130
131static void txm_desc_free(struct agnx_priv *priv, unsigned int idx)
132{
133 struct agnx_desc *desc = priv->txm.desc + idx;
134 struct agnx_info *info = priv->txm.info + idx;
135
136 __tx_desc_free(priv, desc, info);
137}
138
139static void txd_desc_free(struct agnx_priv *priv, unsigned int idx)
140{
141 struct agnx_desc *desc = priv->txd.desc + idx;
142 struct agnx_info *info = priv->txd.info + idx;
143
144 __tx_desc_free(priv, desc, info);
145}
146
147int fill_rings(struct agnx_priv *priv)
148{
149 void __iomem *ctl = priv->ctl;
150 unsigned int i;
151 u32 reg;
152 AGNX_TRACE;
153
154 priv->txd.idx_sent = priv->txm.idx_sent = 0;
155 priv->rx.idx = priv->txm.idx = priv->txd.idx = 0;
156
157 for (i = 0; i < priv->rx.size; i++)
158 rx_desc_init(priv, i);
159 for (i = 0; i < priv->txm.size; i++) {
160 memset(priv->txm.desc + i, 0, sizeof(struct agnx_desc));
161 memset(priv->txm.info + i, 0, sizeof(struct agnx_info));
162 }
163 for (i = 0; i < priv->txd.size; i++) {
164 memset(priv->txd.desc + i, 0, sizeof(struct agnx_desc));
165 memset(priv->txd.info + i, 0, sizeof(struct agnx_info));
166 }
167
168 /* FIXME Set the card RX TXM and TXD address */
169 agnx_write32(ctl, AGNX_CIR_RXCMSTART, priv->rx.dma);
170 agnx_write32(ctl, AGNX_CIR_RXCMEND, priv->txm.dma);
171
172 agnx_write32(ctl, AGNX_CIR_TXMSTART, priv->txm.dma);
173 agnx_write32(ctl, AGNX_CIR_TXMEND, priv->txd.dma);
174
175 agnx_write32(ctl, AGNX_CIR_TXDSTART, priv->txd.dma);
176 agnx_write32(ctl, AGNX_CIR_TXDEND, priv->txd.dma +
177 sizeof(struct agnx_desc) * priv->txd.size);
178
179 /* FIXME Relinquish control of rings to card */
180 reg = agnx_read32(ctl, AGNX_CIR_BLKCTL);
181 reg &= ~0x800;
182 agnx_write32(ctl, AGNX_CIR_BLKCTL, reg);
183 return 0;
184} /* fill_rings */
185
186void unfill_rings(struct agnx_priv *priv)
187{
188 unsigned long flags;
189 unsigned int i;
190 AGNX_TRACE;
191
192 spin_lock_irqsave(&priv->lock, flags);
193
194 for (i = 0; i < priv->rx.size; i++)
195 rx_desc_free(priv, i);
196 for (i = 0; i < priv->txm.size; i++)
197 txm_desc_free(priv, i);
198 for (i = 0; i < priv->txd.size; i++)
199 txd_desc_free(priv, i);
200
201 spin_unlock_irqrestore(&priv->lock, flags);
202}
203
204/* Extract the bitrate out of a CCK PLCP header.
205 copy from bcm43xx driver */
206static inline u8 agnx_plcp_get_bitrate_cck(__be32 *phyhdr_11b)
207{
208 /* FIXME */
209 switch (*(u8 *)phyhdr_11b) {
210 case 0x0A:
211 return 0;
212 case 0x14:
213 return 1;
214 case 0x37:
215 return 2;
216 case 0x6E:
217 return 3;
218 }
219 agnx_bug("Wrong plcp rate");
220 return 0;
221}
222
223/* FIXME */
224static inline u8 agnx_plcp_get_bitrate_ofdm(__be32 *phyhdr_11g)
225{
226 u8 rate = *(u8 *)phyhdr_11g & 0xF;
227
228 printk(PFX "G mode rate is 0x%x\n", rate);
229 return rate;
230}
231
232/* FIXME */
233static void get_rx_stats(struct agnx_priv *priv, struct agnx_hdr *hdr,
234 struct ieee80211_rx_status *stat)
235{
236 void __iomem *ctl = priv->ctl;
237 u8 *rssi;
238 u32 noise;
239 /* FIXME just for test */
240 int snr = 40; /* signal-to-noise ratio */
241
242 memset(stat, 0, sizeof(*stat));
243 /* RSSI */
244 rssi = (u8 *)&hdr->phy_stats_lo;
245/* stat->ssi = (rssi[0] + rssi[1] + rssi[2]) / 3; */
246 /* Noise */
247 noise = ioread32(ctl + AGNX_GCR_NOISE0);
248 noise += ioread32(ctl + AGNX_GCR_NOISE1);
249 noise += ioread32(ctl + AGNX_GCR_NOISE2);
250 stat->noise = noise / 3;
251 /* Signal quality */
252/* snr = stat->ssi - stat->noise; */
253 if (snr >= 0 && snr < 40)
254 stat->signal = 5 * snr / 2;
255 else if (snr >= 40)
256 stat->signal = 100;
257 else
258 stat->signal = 0;
259
260
261 if (hdr->_11b0 && !hdr->_11g0) {
262 stat->rate_idx = agnx_plcp_get_bitrate_cck(&hdr->_11b0);
263 } else if (!hdr->_11b0 && hdr->_11g0) {
264 printk(PFX "RX: Found G mode packet\n");
265 stat->rate_idx = agnx_plcp_get_bitrate_ofdm(&hdr->_11g0);
266 } else
267 agnx_bug("Unknown packets type");
268
269
270 stat->band = IEEE80211_BAND_2GHZ;
271 stat->freq = agnx_channels[priv->channel - 1].center_freq;
272/* stat->antenna = 3;
273 stat->mactime = be32_to_cpu(hdr->time_stamp);
274 stat->channel = priv->channel; */
275}
276
277static inline void combine_hdr_frag(struct ieee80211_hdr *ieeehdr,
278 struct sk_buff *skb)
279{
280 u16 fctl;
281 unsigned int hdrlen;
282
283 fctl = le16_to_cpu(ieeehdr->frame_control);
284 hdrlen = ieee80211_hdrlen(fctl);
285 /* FIXME */
286 if (hdrlen < (2+2+6)/*minimum hdr*/ ||
287 hdrlen > sizeof(struct ieee80211_mgmt)) {
288 printk(KERN_ERR PFX "hdr len is %d\n", hdrlen);
289 agnx_bug("Wrong ieee80211 hdr detected");
290 }
291 skb_push(skb, hdrlen);
292 memcpy(skb->data, ieeehdr, hdrlen);
293} /* combine_hdr_frag */
294
295static inline int agnx_packet_check(struct agnx_priv *priv, struct agnx_hdr *agnxhdr,
296 unsigned packet_len)
297{
298 if (agnx_get_bits(CRC_FAIL, CRC_FAIL_SHIFT, be32_to_cpu(agnxhdr->reg1)) == 1) {
299 printk(PFX "RX: CRC check fail\n");
300 goto drop;
301 }
302 if (packet_len > 2048) {
303 printk(PFX "RX: Too long packet detected\n");
304 goto drop;
305 }
306
307 /* FIXME Just usable for Promious Mode, for Manage mode exclude FCS */
308/* if (packet_len - sizeof(*agnxhdr) < FCS_LEN) { */
309/* printk(PFX "RX: Too short packet detected\n"); */
310/* goto drop; */
311/* } */
312 return 0;
313drop:
314 priv->stats.dot11FCSErrorCount++;
315 return -1;
316}
317
318void handle_rx_irq(struct agnx_priv *priv)
319{
320 struct ieee80211_rx_status status;
321 unsigned int len;
322/* AGNX_TRACE; */
323
324 do {
325 struct agnx_desc *desc;
326 u32 frag;
327 struct agnx_info *info;
328 struct agnx_hdr *hdr;
329 struct sk_buff *skb;
330 unsigned int i = priv->rx.idx % priv->rx.size;
331
332 desc = priv->rx.desc + i;
333 frag = be32_to_cpu(desc->frag);
334 if (frag & OWNER)
335 break;
336
337 info = priv->rx.info + i;
338 skb = info->skb;
339 hdr = (struct agnx_hdr *)(skb->data);
340
341 len = (frag & PACKET_LEN) >> PACKET_LEN_SHIFT;
342 if (agnx_packet_check(priv, hdr, len) == -1) {
343 rx_desc_reusing(priv, i);
344 continue;
345 }
346 skb_put(skb, len);
347
348 do {
349 u16 fctl;
350 fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr)->frame_control);
351 if ((fctl & IEEE80211_FCTL_STYPE) != IEEE80211_STYPE_BEACON)/* && !(fctl & IEEE80211_STYPE_BEACON)) */
352 dump_ieee80211_hdr((struct ieee80211_hdr *)hdr->mac_hdr, "RX");
353 } while (0);
354
355 if (hdr->_11b0 && !hdr->_11g0) {
356/* int j;
357 u16 fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr)
358 ->frame_control);
359 if ( (fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) {
360 agnx_print_rx_hdr(hdr);
361 agnx_print_sta(priv, BSSID_STAID);
362 for (j = 0; j < 8; j++)
363 agnx_print_sta_tx_wq(priv, BSSID_STAID, j);
364 } */
365
366 get_rx_stats(priv, hdr, &status);
367 skb_pull(skb, sizeof(*hdr));
368 combine_hdr_frag((struct ieee80211_hdr *)hdr->mac_hdr, skb);
369 } else if (!hdr->_11b0 && hdr->_11g0) {
370/* int j; */
371 agnx_print_rx_hdr(hdr);
372 agnx_print_sta(priv, BSSID_STAID);
373/* for (j = 0; j < 8; j++) */
374 agnx_print_sta_tx_wq(priv, BSSID_STAID, 0);
375
376 print_hex_dump_bytes("agnx: RX_PACKET: ", DUMP_PREFIX_NONE,
377 skb->data, skb->len + 8);
378
379/* if (agnx_plcp_get_bitrate_ofdm(&hdr->_11g0) == 0) */
380 get_rx_stats(priv, hdr, &status);
381 skb_pull(skb, sizeof(*hdr));
382 combine_hdr_frag((struct ieee80211_hdr *)
383 ((void *)&hdr->mac_hdr), skb);
384/* dump_ieee80211_hdr((struct ieee80211_hdr *)skb->data, "RX G"); */
385 } else
386 agnx_bug("Unknown packets type");
387 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
388 ieee80211_rx_irqsafe(priv->hw, skb);
389 rx_desc_reinit(priv, i);
390
391 } while (priv->rx.idx++);
392} /* handle_rx_irq */
393
394static inline void handle_tx_irq(struct agnx_priv *priv, struct agnx_ring *ring)
395{
396 struct agnx_desc *desc;
397 struct agnx_info *info;
398 unsigned int idx;
399
400 for (idx = ring->idx_sent; idx < ring->idx; idx++) {
401 unsigned int i = idx % ring->size;
402 u32 frag;
403
404 desc = ring->desc + i;
405 info = ring->info + i;
406
407 frag = be32_to_cpu(desc->frag);
408 if (frag & OWNER) {
409 if (info->type == HEADER)
410 break;
411 else
412 agnx_bug("TX error");
413 }
414
415 pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_TODEVICE);
416
417 do {
418/* int j; */
419 size_t len;
420 len = info->skb->len - sizeof(struct agnx_hdr) + info->hdr_len;
421/* if (len == 614) { */
422/* agnx_print_desc(desc); */
423 if (info->type == PACKET) {
424/* agnx_print_tx_hdr((struct agnx_hdr *)info->skb->data); */
425/* agnx_print_sta_power(priv, LOCAL_STAID); */
426/* agnx_print_sta(priv, LOCAL_STAID); */
427/* for (j = 0; j < 8; j++) */
428/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, 0); */
429/* agnx_print_sta_power(priv, BSSID_STAID); */
430/* agnx_print_sta(priv, BSSID_STAID); */
431/* for (j = 0; j < 8; j++) */
432/* agnx_print_sta_tx_wq(priv, BSSID_STAID, 0); */
433 }
434/* } */
435 } while (0);
436
437 if (info->type == PACKET) {
438/* dump_txm_registers(priv);
439 dump_rxm_registers(priv);
440 dump_bm_registers(priv);
441 dump_cir_registers(priv); */
442 }
443
444 if (info->type == PACKET) {
445/* struct ieee80211_hdr *hdr; */
446 struct ieee80211_tx_info *txi = IEEE80211_SKB_CB(info->skb);
447
448 skb_pull(info->skb, sizeof(struct agnx_hdr));
449 memcpy(skb_push(info->skb, info->hdr_len), &info->hdr, info->hdr_len);
450
451/* dump_ieee80211_hdr((struct ieee80211_hdr *)info->skb->data, "TX_HANDLE"); */
452/* print_hex_dump_bytes("agnx: TX_HANDLE: ", DUMP_PREFIX_NONE, */
453/* info->skb->data, info->skb->len); */
454
455 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK))
456 txi->flags |= IEEE80211_TX_STAT_ACK;
457
458 ieee80211_tx_status_irqsafe(priv->hw, info->skb);
459
460
461/* info->tx_status.queue_number = (ring->size - i) / 2; */
462/* ieee80211_tx_status_irqsafe(priv->hw, info->skb, &(info->tx_status)); */
463/* } else */
464/* dev_kfree_skb_irq(info->skb); */
465 }
466 memset(desc, 0, sizeof(*desc));
467 memset(info, 0, sizeof(*info));
468 }
469
470 ring->idx_sent = idx;
471 /* TODO fill the priv->low_level_stats */
472
473 /* ieee80211_wake_queue(priv->hw, 0); */
474}
475
476void handle_txm_irq(struct agnx_priv *priv)
477{
478 handle_tx_irq(priv, &priv->txm);
479}
480
481void handle_txd_irq(struct agnx_priv *priv)
482{
483 handle_tx_irq(priv, &priv->txd);
484}
485
486void handle_other_irq(struct agnx_priv *priv)
487{
488/* void __iomem *ctl = priv->ctl; */
489 u32 status = priv->irq_status;
490 void __iomem *ctl = priv->ctl;
491 u32 reg;
492
493 if (status & IRQ_TX_BEACON) {
494 iowrite32(IRQ_TX_BEACON, ctl + AGNX_INT_STAT);
495 printk(PFX "IRQ: TX Beacon control is 0X%.8X\n", ioread32(ctl + AGNX_TXM_BEACON_CTL));
496 printk(PFX "IRQ: TX Beacon rx frame num: %d\n", rx_frame_cnt);
497 }
498 if (status & IRQ_TX_RETRY) {
499 reg = ioread32(ctl + AGNX_TXM_RETRYSTAID);
500 printk(PFX "IRQ: TX Retry, RETRY STA ID is %x\n", reg);
501 }
502 if (status & IRQ_TX_ACTIVITY)
503 printk(PFX "IRQ: TX Activity\n");
504 if (status & IRQ_RX_ACTIVITY)
505 printk(PFX "IRQ: RX Activity\n");
506 if (status & IRQ_RX_X)
507 printk(PFX "IRQ: RX X\n");
508 if (status & IRQ_RX_Y) {
509 reg = ioread32(ctl + AGNX_INT_MASK);
510 reg &= ~IRQ_RX_Y;
511 iowrite32(reg, ctl + AGNX_INT_MASK);
512 iowrite32(IRQ_RX_Y, ctl + AGNX_INT_STAT);
513 printk(PFX "IRQ: RX Y\n");
514 }
515 if (status & IRQ_RX_HASHHIT) {
516 reg = ioread32(ctl + AGNX_INT_MASK);
517 reg &= ~IRQ_RX_HASHHIT;
518 iowrite32(reg, ctl + AGNX_INT_MASK);
519 iowrite32(IRQ_RX_HASHHIT, ctl + AGNX_INT_STAT);
520 printk(PFX "IRQ: RX Hash Hit\n");
521
522 }
523 if (status & IRQ_RX_FRAME) {
524 reg = ioread32(ctl + AGNX_INT_MASK);
525 reg &= ~IRQ_RX_FRAME;
526 iowrite32(reg, ctl + AGNX_INT_MASK);
527 iowrite32(IRQ_RX_FRAME, ctl + AGNX_INT_STAT);
528 printk(PFX "IRQ: RX Frame\n");
529 rx_frame_cnt++;
530 }
531 if (status & IRQ_ERR_INT) {
532 iowrite32(IRQ_ERR_INT, ctl + AGNX_INT_STAT);
533/* agnx_hw_reset(priv); */
534 printk(PFX "IRQ: Error Interrupt\n");
535 }
536 if (status & IRQ_TX_QUE_FULL)
537 printk(PFX "IRQ: TX Workqueue Full\n");
538 if (status & IRQ_BANDMAN_ERR)
539 printk(PFX "IRQ: Bandwidth Management Error\n");
540 if (status & IRQ_TX_DISABLE)
541 printk(PFX "IRQ: TX Disable\n");
542 if (status & IRQ_RX_IVASESKEY)
543 printk(PFX "IRQ: RX Invalid Session Key\n");
544 if (status & IRQ_REP_THHIT)
545 printk(PFX "IRQ: Replay Threshold Hit\n");
546 if (status & IRQ_TIMER1)
547 printk(PFX "IRQ: Timer1\n");
548 if (status & IRQ_TIMER_CNT)
549 printk(PFX "IRQ: Timer Count\n");
550 if (status & IRQ_PHY_FASTINT)
551 printk(PFX "IRQ: Phy Fast Interrupt\n");
552 if (status & IRQ_PHY_SLOWINT)
553 printk(PFX "IRQ: Phy Slow Interrupt\n");
554 if (status & IRQ_OTHER)
555 printk(PFX "IRQ: 0x80000000\n");
556} /* handle_other_irq */
557
558
559static inline void route_flag_set(struct agnx_hdr *txhdr)
560{
561/* u32 reg = 0; */
562
563 /* FIXME */
564/* reg = (0x7 << ROUTE_COMPRESSION_SHIFT) & ROUTE_COMPRESSION; */
565/* txhdr->reg5 = cpu_to_be32(reg); */
566 txhdr->reg5 = (0xa << 0x0) | (0x7 << 0x18);
567/* txhdr->reg5 = cpu_to_be32((0xa << 0x0) | (0x7 << 0x18)); */
568/* txhdr->reg5 = cpu_to_be32(0x7 << 0x0); */
569}
570
571/* Return 0 if no match */
572static inline unsigned int get_power_level(unsigned int rate, unsigned int antennas_num)
573{
574 unsigned int power_level;
575
576 switch (rate) {
577 case 10:
578 case 20:
579 case 55:
580 case 60:
581 case 90:
582 case 120:
583 power_level = 22;
584 break;
585
586 case 180:
587 power_level = 19;
588 break;
589
590 case 240:
591 power_level = 18;
592 break;
593
594 case 360:
595 power_level = 16;
596 break;
597
598 case 480:
599 power_level = 15;
600 break;
601
602 case 540:
603 power_level = 14;
604 break;
605 default:
606 agnx_bug("Error rate setting\n");
607 }
608
609 if (power_level && (antennas_num == 2))
610 power_level -= 3;
611
612 return power_level;
613}
614
615static inline void fill_agnx_hdr(struct agnx_priv *priv, struct agnx_info *tx_info)
616{
617 struct agnx_hdr *txhdr = (struct agnx_hdr *)tx_info->skb->data;
618 size_t len;
619 u16 fc = le16_to_cpu(*(__le16 *)&tx_info->hdr);
620 u32 reg;
621
622 memset(txhdr, 0, sizeof(*txhdr));
623
624/* reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, LOCAL_STAID); */
625 reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, BSSID_STAID);
626 reg |= agnx_set_bits(WORKQUEUE_ID, WORKQUEUE_ID_SHIFT, 0);
627 txhdr->reg4 = cpu_to_be32(reg);
628
629 /* Set the Hardware Sequence Number to 1? */
630 reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 0);
631/* reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 1); */
632 reg |= agnx_set_bits(MAC_HDR_LEN, MAC_HDR_LEN_SHIFT, tx_info->hdr_len);
633 txhdr->reg1 = cpu_to_be32(reg);
634 /* Set the agnx_hdr's MAC header */
635 memcpy(txhdr->mac_hdr, &tx_info->hdr, tx_info->hdr_len);
636
637 reg = agnx_set_bits(ACK, ACK_SHIFT, 1);
638/* reg = agnx_set_bits(ACK, ACK_SHIFT, 0); */
639 reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 0);
640/* reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 1); */
641 reg |= agnx_set_bits(RELAY, RELAY_SHIFT, 0);
642 reg |= agnx_set_bits(TM, TM_SHIFT, 0);
643 txhdr->reg0 = cpu_to_be32(reg);
644
645 /* Set the long and short retry limits */
646 txhdr->tx.short_retry_limit = tx_info->txi->control.rates[0].count;
647 txhdr->tx.long_retry_limit = tx_info->txi->control.rates[0].count;
648
649 /* FIXME */
650 len = tx_info->skb->len - sizeof(*txhdr) + tx_info->hdr_len + FCS_LEN;
651 if (fc & IEEE80211_FCTL_PROTECTED)
652 len += 8;
653 len = 2398;
654 reg = agnx_set_bits(FRAG_SIZE, FRAG_SIZE_SHIFT, len);
655 len = tx_info->skb->len - sizeof(*txhdr);
656 reg |= agnx_set_bits(PAYLOAD_LEN, PAYLOAD_LEN_SHIFT, len);
657 txhdr->reg3 = cpu_to_be32(reg);
658
659 route_flag_set(txhdr);
660} /* fill_hdr */
661
662static void txm_power_set(struct agnx_priv *priv,
663 struct ieee80211_tx_info *txi)
664{
665 struct agnx_sta_power power;
666 u32 reg;
667
668 /* FIXME */
669 if (txi->control.rates[0].idx < 0) {
670 /* For B mode Short Preamble */
671 reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_SHORT);
672/* control->tx_rate = -control->tx_rate; */
673 } else
674 reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211G);
675/* reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_LONG); */
676 reg |= agnx_set_bits(SIGNAL, SIGNAL_SHIFT, 0xB);
677 reg |= agnx_set_bits(RATE, RATE_SHIFT, 0xB);
678/* reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 15); */
679 reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 20);
680 /* if rate < 11M set it to 0 */
681 reg |= agnx_set_bits(NUM_TRANSMITTERS, NUM_TRANSMITTERS_SHIFT, 1);
682/* reg |= agnx_set_bits(EDCF, EDCF_SHIFT, 1); */
683/* reg |= agnx_set_bits(TIFS, TIFS_SHIFT, 1); */
684
685 power.reg = reg;
686/* power.reg = cpu_to_le32(reg); */
687
688/* set_sta_power(priv, &power, LOCAL_STAID); */
689 set_sta_power(priv, &power, BSSID_STAID);
690}
691
692static inline int tx_packet_check(struct sk_buff *skb)
693{
694 unsigned int ieee_len = ieee80211_get_hdrlen_from_skb(skb);
695 if (skb->len > 2048) {
696 printk(KERN_ERR PFX "length is %d\n", skb->len);
697 agnx_bug("Too long TX skb");
698 return -1;
699 }
700 /* FIXME */
701 if (skb->len == ieee_len) {
702 printk(PFX "A strange TX packet\n");
703 return -1;
704 /* tx_faile_irqsafe(); */
705 }
706 return 0;
707}
708
709static int __agnx_tx(struct agnx_priv *priv, struct sk_buff *skb,
710 struct agnx_ring *ring)
711{
712 struct agnx_desc *hdr_desc, *frag_desc;
713 struct agnx_info *hdr_info, *frag_info;
714 struct ieee80211_tx_info *txi = IEEE80211_SKB_CB(skb);
715 unsigned long flags;
716 unsigned int i;
717
718 spin_lock_irqsave(&priv->lock, flags);
719
720 /* The RX interrupt need be Disable until this TX packet
721 is handled in the next tx interrupt */
722 disable_rx_interrupt(priv);
723
724 i = ring->idx;
725 ring->idx += 2;
726/* if (priv->txm_idx - priv->txm_idx_sent == AGNX_TXM_RING_SIZE - 2) */
727/* ieee80211_stop_queue(priv->hw, 0); */
728
729 /* Set agnx header's info and desc */
730 i %= ring->size;
731 hdr_desc = ring->desc + i;
732 hdr_info = ring->info + i;
733 hdr_info->hdr_len = ieee80211_get_hdrlen_from_skb(skb);
734 memcpy(&hdr_info->hdr, skb->data, hdr_info->hdr_len);
735
736 /* Add the agnx header to the front of the SKB */
737 skb_push(skb, sizeof(struct agnx_hdr) - hdr_info->hdr_len);
738
739 hdr_info->txi = txi;
740 hdr_info->dma_len = sizeof(struct agnx_hdr);
741 hdr_info->skb = skb;
742 hdr_info->type = HEADER;
743 fill_agnx_hdr(priv, hdr_info);
744 hdr_info->mapping = pci_map_single(priv->pdev, skb->data,
745 hdr_info->dma_len, PCI_DMA_TODEVICE);
746 do {
747 u32 frag = 0;
748 frag |= agnx_set_bits(FIRST_FRAG, FIRST_FRAG_SHIFT, 1);
749 frag |= agnx_set_bits(LAST_FRAG, LAST_FRAG_SHIFT, 0);
750 frag |= agnx_set_bits(PACKET_LEN, PACKET_LEN_SHIFT, skb->len);
751 frag |= agnx_set_bits(FIRST_FRAG_LEN, FIRST_FRAG_LEN_SHIFT, 1);
752 frag |= agnx_set_bits(OWNER, OWNER_SHIFT, 1);
753 hdr_desc->frag = cpu_to_be32(frag);
754 } while (0);
755 hdr_desc->dma_addr = cpu_to_be32(hdr_info->mapping);
756
757
758 /* Set Frag's info and desc */
759 i = (i + 1) % ring->size;
760 frag_desc = ring->desc + i;
761 frag_info = ring->info + i;
762 memcpy(frag_info, hdr_info, sizeof(struct agnx_info));
763 frag_info->type = PACKET;
764 frag_info->dma_len = skb->len - hdr_info->dma_len;
765 frag_info->mapping = pci_map_single(priv->pdev, skb->data + hdr_info->dma_len,
766 frag_info->dma_len, PCI_DMA_TODEVICE);
767 do {
768 u32 frag = 0;
769 frag |= agnx_set_bits(FIRST_FRAG, FIRST_FRAG_SHIFT, 0);
770 frag |= agnx_set_bits(LAST_FRAG, LAST_FRAG_SHIFT, 1);
771 frag |= agnx_set_bits(PACKET_LEN, PACKET_LEN_SHIFT, skb->len);
772 frag |= agnx_set_bits(SUB_FRAG_LEN, SUB_FRAG_LEN_SHIFT, frag_info->dma_len);
773 frag_desc->frag = cpu_to_be32(frag);
774 } while (0);
775 frag_desc->dma_addr = cpu_to_be32(frag_info->mapping);
776
777 txm_power_set(priv, txi);
778
779/* do { */
780/* int j; */
781/* size_t len; */
782/* len = skb->len - hdr_info->dma_len + hdr_info->hdr_len; */
783/* if (len == 614) { */
784/* agnx_print_desc(hdr_desc); */
785/* agnx_print_desc(frag_desc); */
786/* agnx_print_tx_hdr((struct agnx_hdr *)skb->data); */
787/* agnx_print_sta_power(priv, LOCAL_STAID); */
788/* agnx_print_sta(priv, LOCAL_STAID); */
789/* for (j = 0; j < 8; j++) */
790/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, j); */
791/* agnx_print_sta_power(priv, BSSID_STAID); */
792/* agnx_print_sta(priv, BSSID_STAID); */
793/* for (j = 0; j < 8; j++) */
794/* agnx_print_sta_tx_wq(priv, BSSID_STAID, j); */
795/* } */
796/* } while (0); */
797
798 spin_unlock_irqrestore(&priv->lock, flags);
799
800 /* FIXME ugly code */
801 /* Trigger TXM */
802 do {
803 u32 reg;
804 reg = (ioread32(priv->ctl + AGNX_CIR_TXMCTL));
805 reg |= 0x8;
806 iowrite32((reg), priv->ctl + AGNX_CIR_TXMCTL);
807 } while (0);
808
809 /* Trigger TXD */
810 do {
811 u32 reg;
812 reg = (ioread32(priv->ctl + AGNX_CIR_TXDCTL));
813 reg |= 0x8;
814 iowrite32((reg), priv->ctl + AGNX_CIR_TXDCTL);
815 } while (0);
816
817 return 0;
818}
819
820int _agnx_tx(struct agnx_priv *priv, struct sk_buff *skb)
821{
822 u16 fctl;
823
824 if (tx_packet_check(skb))
825 return 0;
826
827/* print_hex_dump_bytes("agnx: TX_PACKET: ", DUMP_PREFIX_NONE, */
828/* skb->data, skb->len); */
829
830 fctl = le16_to_cpu(*((__le16 *)skb->data));
831
832 if ((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)
833 return __agnx_tx(priv, skb, &priv->txd);
834 else
835 return __agnx_tx(priv, skb, &priv->txm);
836}
diff --git a/drivers/staging/agnx/xmit.h b/drivers/staging/agnx/xmit.h
deleted file mode 100644
index 93ac4157e69..00000000000
--- a/drivers/staging/agnx/xmit.h
+++ /dev/null
@@ -1,250 +0,0 @@
1#ifndef AGNX_XMIT_H_
2#define AGNX_XMIT_H_
3
4#include <net/mac80211.h>
5
6struct agnx_priv;
7
8static inline u32 agnx_set_bits(u32 mask, u8 shift, u32 value)
9{
10 return (value << shift) & mask;
11}
12
13static inline u32 agnx_get_bits(u32 mask, u8 shift, u32 value)
14{
15 return (value & mask) >> shift;
16}
17
18
19struct agnx_rx {
20 __be16 rx_packet_duration; /* RX Packet Duration */
21 __be16 replay_cnt; /* Replay Count */
22} __attribute__((__packed__));
23
24
25struct agnx_tx {
26 u8 long_retry_limit; /* Long Retry Limit */
27 u8 short_retry_limit; /* Short Retry Limit */
28 u8 long_retry_cnt; /* Long Retry Count */
29 u8 short_retry_cnt; /* Short Retry Count */
30} __attribute__((__packed__));
31
32
33/* Copy from bcm43xx */
34#define P4D_BYT3S(magic, nr_bytes) u8 __p4dding##magic[nr_bytes]
35#define P4D_BYTES(line, nr_bytes) P4D_BYT3S(line, nr_bytes)
36#define PAD_BYTES(nr_bytes) P4D_BYTES(__LINE__, nr_bytes)
37
38#define P4D_BIT3S(magic, nr_bits) __be32 __padding##magic:nr_bits
39#define P4D_BITS(line, nr_bits) P4D_BIT3S(line, nr_bits)
40#define PAD_BITS(nr_bits) P4D_BITS(__LINE__, nr_bits)
41
42
43struct agnx_hdr {
44 __be32 reg0;
45#define RTS 0x80000000 /* RTS */
46#define RTS_SHIFT 31
47#define MULTICAST 0x40000000 /* multicast */
48#define MULTICAST_SHIFT 30
49#define ACK 0x30000000 /* ACK */
50#define ACK_SHIFT 28
51#define TM 0x08000000 /* TM */
52#define TM_SHIFT 27
53#define RELAY 0x04000000 /* Relay */
54#define RELAY_SHIFT 26
55/* PAD_BITS(4); */
56#define REVISED_FCS 0x00380000 /* revised FCS */
57#define REVISED_FCS_SHIFT 19
58#define NEXT_BUFFER_ADDR 0x0007FFFF /* Next Buffer Address */
59#define NEXT_BUFFER_ADDR_SHIFT 0
60
61 __be32 reg1;
62#define MAC_HDR_LEN 0xFC000000 /* MAC Header Length */
63#define MAC_HDR_LEN_SHIFT 26
64#define DURATION_OVERIDE 0x02000000 /* Duration Override */
65#define DURATION_OVERIDE_SHIFT 25
66#define PHY_HDR_OVERIDE 0x01000000 /* PHY Header Override */
67#define PHY_HDR_OVERIDE_SHIFT 24
68#define CRC_FAIL 0x00800000 /* CRC fail */
69#define CRC_FAIL_SHIFT 23
70/* PAD_BITS(1); */
71#define SEQUENCE_NUMBER 0x00200000 /* Sequence Number */
72#define SEQUENCE_NUMBER_SHIFT 21
73/* PAD_BITS(2); */
74#define BUFF_HEAD_ADDR 0x0007FFFF /* Buffer Head Address */
75#define BUFF_HEAD_ADDR_SHIFT 0
76
77 __be32 reg2;
78#define PDU_COUNT 0xFC000000 /* PDU Count */
79#define PDU_COUNT_SHIFT 26
80/* PAD_BITS(3); */
81#define WEP_KEY 0x00600000 /* WEP Key # */
82#define WEP_KEY_SHIFT 21
83#define USES_WEP_KEY 0x00100000 /* Uses WEP Key */
84#define USES_WEP_KEY_SHIFT 20
85#define KEEP_ALIVE 0x00080000 /* Keep alive */
86#define KEEP_ALIVE_SHIFT 19
87#define BUFF_TAIL_ADDR 0x0007FFFF /* Buffer Tail Address */
88#define BUFF_TAIL_ADDR_SHIFT 0
89
90 __be32 reg3;
91#define CTS_11G 0x80000000 /* CTS in 11g */
92#define CTS_11G_SHIFT 31
93#define RTS_11G 0x40000000 /* RTS in 11g */
94#define RTS_11G_SHIFT 30
95/* PAD_BITS(2); */
96#define FRAG_SIZE 0x0FFF0000 /* fragment size */
97#define FRAG_SIZE_SHIFT 16
98#define PAYLOAD_LEN 0x0000FFF0 /* payload length */
99#define PAYLOAD_LEN_SHIFT 4
100#define FRAG_NUM 0x0000000F /* number of frags */
101#define FRAG_NUM_SHIFT 0
102
103 __be32 reg4;
104/* PAD_BITS(4); */
105#define RELAY_STAID 0x0FFF0000 /* relayStald */
106#define RELAY_STAID_SHIFT 16
107#define STATION_ID 0x0000FFF0 /* Station ID */
108#define STATION_ID_SHIFT 4
109#define WORKQUEUE_ID 0x0000000F /* Workqueue ID */
110#define WORKQUEUE_ID_SHIFT 0
111
112 /* FIXME this register maybe is LE? */
113 __be32 reg5;
114/* PAD_BITS(4); */
115#define ROUTE_HOST 0x0F000000
116#define ROUTE_HOST_SHIFT 24
117#define ROUTE_CARD_CPU 0x00F00000
118#define ROUTE_CARD_CPU_SHIFT 20
119#define ROUTE_ENCRYPTION 0x000F0000
120#define ROUTE_ENCRYPTION_SHIFT 16
121#define ROUTE_TX 0x0000F000
122#define ROUTE_TX_SHIFT 12
123#define ROUTE_RX1 0x00000F00
124#define ROUTE_RX1_SHIFT 8
125#define ROUTE_RX2 0x000000F0
126#define ROUTE_RX2_SHIFT 4
127#define ROUTE_COMPRESSION 0x0000000F
128#define ROUTE_COMPRESSION_SHIFT 0
129
130 __be32 _11g0; /* 11g */
131 __be32 _11g1; /* 11g */
132 __be32 _11b0; /* 11b */
133 __be32 _11b1; /* 11b */
134 u8 mac_hdr[32]; /* MAC header */
135
136 __be16 rts_duration; /* RTS duration */
137 __be16 last_duration; /* Last duration */
138 __be16 sec_last_duration; /* Second to Last duration */
139 __be16 other_duration; /* Other duration */
140 __be16 tx_last_duration; /* TX Last duration */
141 __be16 tx_other_duration; /* TX Other Duration */
142 __be16 last_11g_len; /* Length of last 11g */
143 __be16 other_11g_len; /* Lenght of other 11g */
144
145 __be16 last_11b_len; /* Length of last 11b */
146 __be16 other_11b_len; /* Lenght of other 11b */
147
148
149 __be16 reg6;
150#define MBF 0xF000 /* mbf */
151#define MBF_SHIFT 12
152#define RSVD4 0x0FFF /* rsvd4 */
153#define RSVD4_SHIFT 0
154
155 __be16 rx_frag_stat; /* RX fragmentation status */
156
157 __be32 time_stamp; /* TimeStamp */
158 __be32 phy_stats_hi; /* PHY stats hi */
159 __be32 phy_stats_lo; /* PHY stats lo */
160 __be32 mic_key0; /* MIC key 0 */
161 __be32 mic_key1; /* MIC key 1 */
162
163 union { /* RX/TX Union */
164 struct agnx_rx rx;
165 struct agnx_tx tx;
166 };
167
168 u8 rx_channel; /* Recieve Channel */
169 PAD_BYTES(3);
170
171 u8 reserved[4];
172} __attribute__((__packed__));
173
174
175struct agnx_desc {
176#define PACKET_LEN 0xFFF00000
177#define PACKET_LEN_SHIFT 20
178/* ------------------------------------------------ */
179#define FIRST_PACKET_MASK 0x00080000
180#define FIRST_PACKET_MASK_SHIFT 19
181#define FIRST_RESERV2 0x00040000
182#define FIRST_RESERV2_SHIFT 18
183#define FIRST_TKIP_ERROR 0x00020000
184#define FIRST_TKIP_ERROR_SHIFT 17
185#define FIRST_TKIP_PACKET 0x00010000
186#define FIRST_TKIP_PACKET_SHIFT 16
187#define FIRST_RESERV1 0x0000F000
188#define FIRST_RESERV1_SHIFT 12
189#define FIRST_FRAG_LEN 0x00000FF8
190#define FIRST_FRAG_LEN_SHIFT 3
191/* ------------------------------------------------ */
192#define SUB_RESERV2 0x000c0000
193#define SUB_RESERV2_SHIFT 18
194#define SUB_TKIP_ERROR 0x00020000
195#define SUB_TKIP_ERROR_SHIFT 17
196#define SUB_TKIP_PACKET 0x00010000
197#define SUB_TKIP_PACKET_SHIFT 16
198#define SUB_RESERV1 0x00008000
199#define SUB_RESERV1_SHIFT 15
200#define SUB_FRAG_LEN 0x00007FF8
201#define SUB_FRAG_LEN_SHIFT 3
202/* ------------------------------------------------ */
203#define FIRST_FRAG 0x00000004
204#define FIRST_FRAG_SHIFT 2
205#define LAST_FRAG 0x00000002
206#define LAST_FRAG_SHIFT 1
207#define OWNER 0x00000001
208#define OWNER_SHIFT 0
209 __be32 frag;
210 __be32 dma_addr;
211} __attribute__((__packed__));
212
213enum {HEADER, PACKET};
214
215struct agnx_info {
216 struct sk_buff *skb;
217 dma_addr_t mapping;
218 u32 dma_len; /* dma buffer len */
219 /* Below fields only usful for tx */
220 u32 hdr_len; /* ieee80211 header length */
221 unsigned int type;
222 struct ieee80211_tx_info *txi;
223 struct ieee80211_hdr hdr;
224};
225
226
227struct agnx_ring {
228 struct agnx_desc *desc;
229 dma_addr_t dma;
230 struct agnx_info *info;
231 /* Will lead to overflow when sent packet number enough? */
232 unsigned int idx;
233 unsigned int idx_sent; /* only usful for txd and txm */
234 unsigned int size;
235};
236
237#define AGNX_RX_RING_SIZE 128
238#define AGNX_TXD_RING_SIZE 256
239#define AGNX_TXM_RING_SIZE 128
240
241void disable_rx_interrupt(struct agnx_priv *priv);
242void enable_rx_interrupt(struct agnx_priv *priv);
243int fill_rings(struct agnx_priv *priv);
244void unfill_rings(struct agnx_priv *priv);
245void handle_rx_irq(struct agnx_priv *priv);
246void handle_txd_irq(struct agnx_priv *priv);
247void handle_txm_irq(struct agnx_priv *priv);
248void handle_other_irq(struct agnx_priv *priv);
249int _agnx_tx(struct agnx_priv *priv, struct sk_buff *skb);
250#endif /* AGNX_XMIT_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 08:46:16 -0400