diff options
Diffstat (limited to 'drivers/staging/agnx/agnx.h')
-rw-r--r-- | drivers/staging/agnx/agnx.h | 156 |
1 files changed, 0 insertions, 156 deletions
diff --git a/drivers/staging/agnx/agnx.h b/drivers/staging/agnx/agnx.h deleted file mode 100644 index 3963d2597a1..00000000000 --- a/drivers/staging/agnx/agnx.h +++ /dev/null | |||
@@ -1,156 +0,0 @@ | |||
1 | #ifndef AGNX_H_ | ||
2 | #define AGNX_H_ | ||
3 | |||
4 | #include <linux/io.h> | ||
5 | |||
6 | #include "xmit.h" | ||
7 | |||
8 | #define PFX KBUILD_MODNAME ": " | ||
9 | |||
10 | static inline u32 agnx_read32(void __iomem *mem_region, u32 offset) | ||
11 | { | ||
12 | return ioread32(mem_region + offset); | ||
13 | } | ||
14 | |||
15 | static inline void agnx_write32(void __iomem *mem_region, u32 offset, u32 val) | ||
16 | { | ||
17 | iowrite32(val, mem_region + offset); | ||
18 | } | ||
19 | |||
20 | /* static const struct ieee80211_rate agnx_rates_80211b[] = { */ | ||
21 | /* { .rate = 10, */ | ||
22 | /* .val = 0xa, */ | ||
23 | /* .flags = IEEE80211_RATE_CCK }, */ | ||
24 | /* { .rate = 20, */ | ||
25 | /* .val = 0x14, */ | ||
26 | /* .hw_value = -0x14, */ | ||
27 | /* .flags = IEEE80211_RATE_CCK_2 }, */ | ||
28 | /* { .rate = 55, */ | ||
29 | /* .val = 0x37, */ | ||
30 | /* .val2 = -0x37, */ | ||
31 | /* .flags = IEEE80211_RATE_CCK_2 }, */ | ||
32 | /* { .rate = 110, */ | ||
33 | /* .val = 0x6e, */ | ||
34 | /* .val2 = -0x6e, */ | ||
35 | /* .flags = IEEE80211_RATE_CCK_2 } */ | ||
36 | /* }; */ | ||
37 | |||
38 | |||
39 | static const struct ieee80211_rate agnx_rates_80211g[] = { | ||
40 | /* { .bitrate = 10, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ | ||
41 | /* { .bitrate = 20, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ | ||
42 | /* { .bitrate = 55, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ | ||
43 | /* { .bitrate = 110, .hw_value = 4, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ | ||
44 | { .bitrate = 10, .hw_value = 1, }, | ||
45 | { .bitrate = 20, .hw_value = 2, }, | ||
46 | { .bitrate = 55, .hw_value = 3, }, | ||
47 | { .bitrate = 110, .hw_value = 4,}, | ||
48 | |||
49 | { .bitrate = 60, .hw_value = 0xB, }, | ||
50 | { .bitrate = 90, .hw_value = 0xF, }, | ||
51 | { .bitrate = 120, .hw_value = 0xA }, | ||
52 | { .bitrate = 180, .hw_value = 0xE, }, | ||
53 | /* { .bitrate = 240, .hw_value = 0xd, }, */ | ||
54 | { .bitrate = 360, .hw_value = 0xD, }, | ||
55 | { .bitrate = 480, .hw_value = 0x8, }, | ||
56 | { .bitrate = 540, .hw_value = 0xC, }, | ||
57 | }; | ||
58 | |||
59 | static const struct ieee80211_channel agnx_channels[] = { | ||
60 | { .center_freq = 2412, .hw_value = 1, }, | ||
61 | { .center_freq = 2417, .hw_value = 2, }, | ||
62 | { .center_freq = 2422, .hw_value = 3, }, | ||
63 | { .center_freq = 2427, .hw_value = 4, }, | ||
64 | { .center_freq = 2432, .hw_value = 5, }, | ||
65 | { .center_freq = 2437, .hw_value = 6, }, | ||
66 | { .center_freq = 2442, .hw_value = 7, }, | ||
67 | { .center_freq = 2447, .hw_value = 8, }, | ||
68 | { .center_freq = 2452, .hw_value = 9, }, | ||
69 | { .center_freq = 2457, .hw_value = 10, }, | ||
70 | { .center_freq = 2462, .hw_value = 11, }, | ||
71 | { .center_freq = 2467, .hw_value = 12, }, | ||
72 | { .center_freq = 2472, .hw_value = 13, }, | ||
73 | { .center_freq = 2484, .hw_value = 14, }, | ||
74 | }; | ||
75 | |||
76 | #define NUM_DRIVE_MODES 2 | ||
77 | /* Agnx operate mode */ | ||
78 | enum { | ||
79 | AGNX_MODE_80211A, | ||
80 | AGNX_MODE_80211A_OOB, | ||
81 | AGNX_MODE_80211A_MIMO, | ||
82 | AGNX_MODE_80211B_SHORT, | ||
83 | AGNX_MODE_80211B_LONG, | ||
84 | AGNX_MODE_80211G, | ||
85 | AGNX_MODE_80211G_OOB, | ||
86 | AGNX_MODE_80211G_MIMO, | ||
87 | }; | ||
88 | |||
89 | enum { | ||
90 | AGNX_UNINIT, | ||
91 | AGNX_START, | ||
92 | AGNX_STOP, | ||
93 | }; | ||
94 | |||
95 | struct agnx_priv { | ||
96 | struct pci_dev *pdev; | ||
97 | struct ieee80211_hw *hw; | ||
98 | |||
99 | spinlock_t lock; | ||
100 | struct mutex mutex; | ||
101 | unsigned int init_status; | ||
102 | |||
103 | void __iomem *ctl; /* pointer to base ram address */ | ||
104 | void __iomem *data; /* pointer to mem region #2 */ | ||
105 | |||
106 | struct agnx_ring rx; | ||
107 | struct agnx_ring txm; | ||
108 | struct agnx_ring txd; | ||
109 | |||
110 | /* Need volatile? */ | ||
111 | u32 irq_status; | ||
112 | |||
113 | struct delayed_work periodic_work; /* Periodic tasks like recalibrate */ | ||
114 | struct ieee80211_low_level_stats stats; | ||
115 | |||
116 | /* unsigned int phymode; */ | ||
117 | int mode; | ||
118 | int channel; | ||
119 | u8 bssid[ETH_ALEN]; | ||
120 | |||
121 | u8 mac_addr[ETH_ALEN]; | ||
122 | u8 revid; | ||
123 | |||
124 | struct ieee80211_supported_band band; | ||
125 | }; | ||
126 | |||
127 | |||
128 | #define AGNX_CHAINS_MAX 6 | ||
129 | #define AGNX_PERIODIC_DELAY 60000 /* unit: ms */ | ||
130 | #define LOCAL_STAID 0 /* the station entry for the card itself */ | ||
131 | #define BSSID_STAID 1 /* the station entry for the bsssid AP */ | ||
132 | #define spi_delay() udelay(40) | ||
133 | #define eeprom_delay() udelay(40) | ||
134 | #define routing_table_delay() udelay(50) | ||
135 | |||
136 | /* PDU pool MEM region #2 */ | ||
137 | #define AGNX_PDUPOOL 0x40000 /* PDU pool */ | ||
138 | #define AGNX_PDUPOOL_SIZE 0x8000 /* PDU pool size*/ | ||
139 | #define AGNX_PDU_TX_WQ 0x41000 /* PDU list TX workqueue */ | ||
140 | #define AGNX_PDU_FREE 0x41800 /* Free Pool */ | ||
141 | #define PDU_SIZE 0x80 /* Free Pool node size */ | ||
142 | #define PDU_FREE_CNT 0xd0 /* Free pool node count */ | ||
143 | |||
144 | |||
145 | /* RF stuffs */ | ||
146 | extern void rf_chips_init(struct agnx_priv *priv); | ||
147 | extern void spi_rc_write(void __iomem *mem_region, u32 chip_ids, u32 sw); | ||
148 | extern void calibrate_oscillator(struct agnx_priv *priv); | ||
149 | extern void do_calibration(struct agnx_priv *priv); | ||
150 | extern void antenna_calibrate(struct agnx_priv *priv); | ||
151 | extern void __antenna_calibrate(struct agnx_priv *priv); | ||
152 | extern void print_offsets(struct agnx_priv *priv); | ||
153 | extern int agnx_set_channel(struct agnx_priv *priv, unsigned int channel); | ||
154 | |||
155 | |||
156 | #endif /* AGNX_H_ */ | ||