Merge branch 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm

* 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm: (46 commits)
  msm: scm: Check for interruption immediately
  msm: scm: Fix improper register assignment
  msm: scm: Mark inline asm as volatile
  msm: iommu: Enable HTW L2 redirection on MSM8960
  msm: iommu: Don't read from write-only registers
  msm: iommu: Remove dependency on IDR
  msm: iommu: Use ASID tagging instead of VMID tagging
  msm: iommu: Rework clock logic and add IOMMU bus clock control
  msm: iommu: Clock control for the IOMMU driver
  msm: mdp: Set the correct pack pattern for XRGB/ARGB
  msm_fb: Fix framebuffer console
  msm: mdp: Add support for RGBX 8888 image format.
  video: msmfb: Put the partial update magic value into the fix_screen struct.
  msm: clock: Migrate to clkdev
  msm: clock: Remove references to clk_ops_pcom
  msm: headsmp.S: Fix section mismatch
  msm: Use explicit GPLv2 licenses
  msm: iommu: Enable IOMMU support for MSM8960
  msm: iommu: Generalize platform data for multiple targets
  msm: iommu: Create a Kconfig item for the IOMMU driver
  ...

57 files changed, 1641 insertions, 961 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b70fe202c00..599e1634840 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -626,6 +626,7 @@ config ARCH_MSM
         select HAVE_CLK
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
         help
           Support for Qualcomm MSM/QSD based systems.  This runs on the
           apps processor of the MSM/QSD and depends on a shared memory
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 5d3d9ade12f..1516896e8d1 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -45,7 +45,16 @@ config ARCH_MSM8X60
         select CPU_V7
         select MSM_V2_TLMM
         select MSM_GPIOMUX
-        select IOMMU_API
+        select MSM_SCM if SMP
+
+config ARCH_MSM8960
+        bool "MSM8960"
+        select ARCH_MSM_SCORPIONMP
+        select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
+        select ARM_GIC
+        select CPU_V7
+        select MSM_V2_TLMM
+        select MSM_GPIOMUX
         select MSM_SCM if SMP
 
 endchoice
@@ -125,11 +134,35 @@ config MACH_MSM8X60_FFA
         help
           Support for the Qualcomm MSM8x60 FFA eval board.
 
+config MACH_MSM8960_SIM
+        depends on ARCH_MSM8960
+        bool "MSM8960 Simulator"
+        help
+          Support for the Qualcomm MSM8960 simulator.
+
+config MACH_MSM8960_RUMI3
+        depends on ARCH_MSM8960
+        bool "MSM8960 RUMI3"
+        help
+          Support for the Qualcomm MSM8960 RUMI3 emulator.
+
 endmenu
 
+config MSM_IOMMU
+        bool "MSM IOMMU Support"
+        depends on ARCH_MSM8X60 || ARCH_MSM8960
+        select IOMMU_API
+        default n
+        help
+          Support for the IOMMUs found on certain Qualcomm SOCs.
+          These IOMMUs allow virtualization of the address space used by most
+          cores within the multimedia subsystem.
+
+          If unsure, say N here.
+
 config IOMMU_PGTABLES_L2
         def_bool y
-        depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n
+        depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n
 
 config MSM_DEBUG_UART
         int
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 94195c190e1..9519fd28a02 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,21 +1,16 @@
 obj-y += io.o idle.o timer.o
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += acpuclock-arm11.o
-obj-y += dma.o
-endif
+obj-y += clock.o
+obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
-ifdef CONFIG_MSM_VIC
-obj-y += irq-vic.o
-else
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += irq.o
-endif
-endif
+obj-$(CONFIG_MSM_VIC) += irq-vic.o
+obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o
+
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 
-obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
-obj-$(CONFIG_MSM_PROC_COMM) += clock.o
-obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
+
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
@@ -29,12 +24,16 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
+obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
 
-obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
+obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
 ifdef CONFIG_MSM_V2_TLMM
+ifndef CONFIG_ARCH_MSM8960
+# TODO: TLMM Mapping issues need to be resolved
 obj-y   += gpio-v2.o
+endif
 else
 obj-y   += gpio.o
 endif
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 75dabb16c80..18a3c97bc86 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -93,8 +93,6 @@ static void __init halibut_map_io(void)
 }
 
 MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = 0x10000100,
         .fixup          = halibut_fixup,
         .map_io         = halibut_map_io,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index ef3ebf2f763..7a9a03eb189 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -74,8 +74,6 @@ static void __init mahimahi_map_io(void)
 extern struct sys_timer msm_timer;
 
 MACHINE_START(MAHIMAHI, "mahimahi")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = 0x20000100,
         .fixup          = mahimahi_fixup,
         .map_io         = mahimahi_map_io,
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index 08fcd40a8cb..c03f269e2e4 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -130,8 +130,6 @@ static void __init msm7x2x_map_io(void)
 }
 
 MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = PLAT_PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
@@ -140,8 +138,6 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = PLAT_PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
@@ -150,8 +146,6 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
 MACHINE_END
 
 MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = PLAT_PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
@@ -160,8 +154,6 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = PLAT_PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 25db8fd71a7..b7a84966b71 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/usb/msm_hsusb.h>
+#include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -36,6 +37,7 @@
 
 #include <mach/vreg.h>
 #include "devices.h"
+#include "gpiomux.h"
 #include "proc_comm.h"
 
 extern struct sys_timer msm_timer;
@@ -52,6 +54,27 @@ static struct msm_otg_platform_data msm_otg_pdata = {
         .otg_control            = OTG_PHY_CONTROL,
 };
 
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
+#ifdef CONFIG_SERIAL_MSM_CONSOLE
+        [49] = { /* UART2 RFR */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [50] = { /* UART2 CTS */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [51] = { /* UART2 RX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [52] = { /* UART2 TX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+#endif
+};
+
 static struct platform_device *devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
@@ -83,8 +106,6 @@ static void __init msm7x30_map_io(void)
 }
 
 MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params = PLAT_PHYS_OFFSET + 0x100,
         .map_io = msm7x30_map_io,
         .init_irq = msm7x30_init_irq,
@@ -93,8 +114,6 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params = PLAT_PHYS_OFFSET + 0x100,
         .map_io = msm7x30_map_io,
         .init_irq = msm7x30_init_irq,
@@ -103,8 +122,6 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
 MACHINE_END
 
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params = PLAT_PHYS_OFFSET + 0x100,
         .map_io = msm7x30_map_io,
         .init_irq = msm7x30_init_irq,
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
new file mode 100644
index 00000000000..1993721d472
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -0,0 +1,91 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/clkdev.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+#include "devices.h"
+
+static void __init msm8960_map_io(void)
+{
+        msm_map_msm8960_io();
+}
+
+static void __init msm8960_init_irq(void)
+{
+        unsigned int i;
+        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                 (void *)MSM_QGIC_CPU_BASE);
+
+        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+        if (machine_is_msm8960_rumi3())
+                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
+        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+         * as they are configured as level, which does not play nice with
+         * handle_percpu_irq.
+         */
+        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+                        set_irq_handler(i, handle_percpu_irq);
+        }
+}
+
+static struct platform_device *sim_devices[] __initdata = {
+        &msm8960_device_uart_gsbi2,
+};
+
+static struct platform_device *rumi3_devices[] __initdata = {
+        &msm8960_device_uart_gsbi5,
+};
+
+static void __init msm8960_sim_init(void)
+{
+        platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
+}
+
+static void __init msm8960_rumi3_init(void)
+{
+        platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
+}
+
+MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
+        .map_io = msm8960_map_io,
+        .init_irq = msm8960_init_irq,
+        .timer = &msm_timer,
+        .init_machine = msm8960_sim_init,
+MACHINE_END
+
+MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
+        .map_io = msm8960_map_io,
+        .init_irq = msm8960_init_irq,
+        .timer = &msm_timer,
+        .init_machine = msm8960_rumi3_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 9b5eb2b4ae1..b3c55f138fc 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -28,10 +28,6 @@
 #include <mach/board.h>
 #include <mach/msm_iomap.h>
 
-unsigned long clk_get_max_axi_khz(void)
-{
-        return 0;
-}
 
 static void __init msm8x60_map_io(void)
 {
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 15c2bbd2ef8..7f568611547 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -21,6 +21,8 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/usb/msm_hsusb.h>
+#include <linux/err.h>
+#include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -31,6 +33,8 @@
 #include <mach/irqs.h>
 #include <mach/sirc.h>
 #include <mach/gpio.h>
+#include <mach/vreg.h>
+#include <mach/mmc.h>
 
 #include "devices.h"
 
@@ -95,6 +99,81 @@ static struct platform_device *devices[] __initdata = {
         &msm_device_hsusb_host,
 };
 
+static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
+        {51, "sdc1_dat_3"},
+        {52, "sdc1_dat_2"},
+        {53, "sdc1_dat_1"},
+        {54, "sdc1_dat_0"},
+        {55, "sdc1_cmd"},
+        {56, "sdc1_clk"}
+};
+
+static struct vreg *vreg_mmc;
+static unsigned long vreg_sts;
+
+static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
+{
+        int rc = 0;
+        struct platform_device *pdev;
+
+        pdev = container_of(dv, struct platform_device, dev);
+
+        if (vdd == 0) {
+                if (!vreg_sts)
+                        return 0;
+
+                clear_bit(pdev->id, &vreg_sts);
+
+                if (!vreg_sts) {
+                        rc = vreg_disable(vreg_mmc);
+                        if (rc)
+                                pr_err("vreg_mmc disable failed for slot "
+                                                "%d: %d\n", pdev->id, rc);
+                }
+                return 0;
+        }
+
+        if (!vreg_sts) {
+                rc = vreg_set_level(vreg_mmc, 2900);
+                if (rc)
+                        pr_err("vreg_mmc set level failed for slot %d: %d\n",
+                                        pdev->id, rc);
+                rc = vreg_enable(vreg_mmc);
+                if (rc)
+                        pr_err("vreg_mmc enable failed for slot %d: %d\n",
+                                        pdev->id, rc);
+        }
+        set_bit(pdev->id, &vreg_sts);
+        return 0;
+}
+
+static struct msm_mmc_gpio_data sdc1_gpio = {
+        .gpio = sdc1_gpio_cfg,
+        .size = ARRAY_SIZE(sdc1_gpio_cfg),
+};
+
+static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
+        .ocr_mask       = MMC_VDD_27_28 | MMC_VDD_28_29,
+        .translate_vdd  = msm_sdcc_setup_power,
+        .gpio_data = &sdc1_gpio,
+};
+
+static void __init qsd8x50_init_mmc(void)
+{
+        if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa())
+                vreg_mmc = vreg_get(NULL, "gp6");
+        else
+                vreg_mmc = vreg_get(NULL, "gp5");
+
+        if (IS_ERR(vreg_mmc)) {
+                pr_err("vreg get for vreg_mmc failed (%ld)\n",
+                                PTR_ERR(vreg_mmc));
+                return;
+        }
+
+        msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
+}
+
 static void __init qsd8x50_map_io(void)
 {
         msm_map_qsd8x50_io();
@@ -113,11 +192,10 @@ static void __init qsd8x50_init(void)
         msm_device_hsusb.dev.parent = &msm_device_otg.dev;
         msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        qsd8x50_init_mmc();
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params = PLAT_PHYS_OFFSET + 0x100,
         .map_io = qsd8x50_map_io,
         .init_irq = qsd8x50_init_irq,
@@ -126,8 +204,6 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
 MACHINE_END
 
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params = PLAT_PHYS_OFFSET + 0x100,
         .map_io = qsd8x50_map_io,
         .init_irq = qsd8x50_init_irq,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 83604f526f0..68f930f07d7 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -105,8 +105,6 @@ static void __init sapphire_map_io(void)
 
 MACHINE_START(SAPPHIRE, "sapphire")
 /* Maintainer: Brian Swetland <swetland@google.com> */
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = PLAT_PHYS_OFFSET + 0x100,
         .fixup          = sapphire_fixup,
         .map_io         = sapphire_map_io,
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index a604ec1e44b..31117a4499c 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -74,8 +74,6 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
 
 static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
-
         return TROUT_GPIO_TO_INT(offset + chip->base);
 }
 
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 73f14606654..814386772c6 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -92,8 +93,6 @@ static void __init trout_map_io(void)
 }
 
 MACHINE_START(TROUT, "HTC Dream")
-#ifdef CONFIG_MSM_DEBUG_UART
-#endif
         .boot_params    = 0x10000100,
         .fixup          = trout_fixup,
         .map_io         = trout_map_io,
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
index e16f72f3282..14104453688 100644
--- a/arch/arm/mach-msm/clock-7x30.h
+++ b/arch/arm/mach-msm/clock-7x30.h
@@ -1,30 +1,13 @@
 /* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
@@ -147,22 +130,26 @@ void pll_disable(uint32_t pll);
 extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
 
 #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .name = clk_name, \
-        .id = L_7X30_##clk_id, \
-        .remote_id = P_##clk_id, \
-        .flags = clk_flags, \
-        .dev = clk_dev, \
-        .dbg_name = #clk_id, \
+        .con_id = clk_name, \
+        .dev_id = clk_dev, \
+        .clk = &(struct clk){ \
+                .id = L_7X30_##clk_id, \
+                .remote_id = P_##clk_id, \
+                .flags = clk_flags, \
+                .dbg_name = #clk_id, \
+        }, \
         }
 
 #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) {   \
-        .name = clk_name, \
-        .id = L_7X30_##l_id, \
-        .remote_id = P_##r_id, \
-        .flags = clk_flags, \
-        .dev = clk_dev, \
-        .dbg_name = #l_id, \
+        .con_id = clk_name, \
+        .dev_id = clk_dev, \
+        .clk = &(struct clk){ \
+                .id = L_7X30_##l_id, \
+                .remote_id = P_##r_id, \
+                .flags = clk_flags, \
+                .dbg_name = #l_id, \
+                .ops = &clk_ops_pcom, \
+        }, \
         }
 
 #endif
-
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
new file mode 100644
index 00000000000..4886404d42f
--- /dev/null
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/ctype.h>
+#include <linux/debugfs.h>
+#include <linux/clk.h>
+#include "clock.h"
+
+static int clock_debug_rate_set(void *data, u64 val)
+{
+        struct clk *clock = data;
+        int ret;
+
+        /* Only increases to max rate will succeed, but that's actually good
+         * for debugging purposes so we don't check for error. */
+        if (clock->flags & CLK_MAX)
+                clk_set_max_rate(clock, val);
+        if (clock->flags & CLK_MIN)
+                ret = clk_set_min_rate(clock, val);
+        else
+                ret = clk_set_rate(clock, val);
+        if (ret != 0)
+                printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
+                        (clock->flags & CLK_MIN) ? "_min" : "", ret);
+        return ret;
+}
+
+static int clock_debug_rate_get(void *data, u64 *val)
+{
+        struct clk *clock = data;
+        *val = clk_get_rate(clock);
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
+                        clock_debug_rate_set, "%llu\n");
+
+static int clock_debug_enable_set(void *data, u64 val)
+{
+        struct clk *clock = data;
+        int rc = 0;
+
+        if (val)
+                rc = clock->ops->enable(clock->id);
+        else
+                clock->ops->disable(clock->id);
+
+        return rc;
+}
+
+static int clock_debug_enable_get(void *data, u64 *val)
+{
+        struct clk *clock = data;
+
+        *val = clock->ops->is_enabled(clock->id);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
+                        clock_debug_enable_set, "%llu\n");
+
+static int clock_debug_local_get(void *data, u64 *val)
+{
+        struct clk *clock = data;
+
+        *val = clock->ops->is_local(clock->id);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get,
+                        NULL, "%llu\n");
+
+static struct dentry *debugfs_base;
+
+int __init clock_debug_init(void)
+{
+        debugfs_base = debugfs_create_dir("clk", NULL);
+        if (!debugfs_base)
+                return -ENOMEM;
+        return 0;
+}
+
+int __init clock_debug_add(struct clk *clock)
+{
+        char temp[50], *ptr;
+        struct dentry *clk_dir;
+
+        if (!debugfs_base)
+                return -ENOMEM;
+
+        strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
+        for (ptr = temp; *ptr; ptr++)
+                *ptr = tolower(*ptr);
+
+        clk_dir = debugfs_create_dir(temp, debugfs_base);
+        if (!clk_dir)
+                return -ENOMEM;
+
+        if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir,
+                                clock, &clock_rate_fops))
+                goto error;
+
+        if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir,
+                                clock, &clock_enable_fops))
+                goto error;
+
+        if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock,
+                                &clock_local_fops))
+                goto error;
+        return 0;
+error:
+        debugfs_remove_recursive(clk_dir);
+        return -ENOMEM;
+}
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c
deleted file mode 100644
index 1250d22082e..00000000000
--- a/arch/arm/mach-msm/clock-dummy.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
- */
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/module.h>
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-        return -ENOENT;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return 0;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        return -ENOENT;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index a3b45627eb4..63b71131108 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -20,6 +20,7 @@
 
 #include "proc_comm.h"
 #include "clock.h"
+#include "clock-pcom.h"
 
 /*
  * glue for the proc_comm interface
@@ -116,6 +117,11 @@ long pc_clk_round_rate(unsigned id, unsigned rate)
         return rate;
 }
 
+static bool pc_clk_is_local(unsigned id)
+{
+        return false;
+}
+
 struct clk_ops clk_ops_pcom = {
         .enable = pc_clk_enable,
         .disable = pc_clk_disable,
@@ -128,4 +134,5 @@ struct clk_ops clk_ops_pcom = {
         .get_rate = pc_clk_get_rate,
         .is_enabled = pc_clk_is_enabled,
         .round_rate = pc_clk_round_rate,
+        .is_local = pc_clk_is_local,
 };
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 17d027b2350..974d0032f3a 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -1,30 +1,13 @@
 /* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
@@ -132,8 +115,10 @@
 #define P_CSI1_P_CLK            97
 #define P_GSBI_CLK              98
 #define P_GSBI_P_CLK            99
+#define P_CE_CLK                100 /* Crypto engine */
+#define P_CODEC_SSBI_CLK        101
 
-#define P_NR_CLKS               100
+#define P_NR_CLKS               102
 
 struct clk_ops;
 extern struct clk_ops clk_ops_pcom;
@@ -141,13 +126,15 @@ extern struct clk_ops clk_ops_pcom;
 int pc_clk_reset(unsigned id, enum clk_reset_action action);
 
 #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .name = clk_name, \
-        .id = P_##clk_id, \
-        .remote_id = P_##clk_id, \
-        .ops = &clk_ops_pcom, \
-        .flags = clk_flags, \
-        .dev = clk_dev, \
-        .dbg_name = #clk_id, \
+        .con_id = clk_name, \
+        .dev_id = clk_dev, \
+        .clk = &(struct clk){ \
+                .id = P_##clk_id, \
+                .remote_id = P_##clk_id, \
+                .ops = &clk_ops_pcom, \
+                .flags = clk_flags, \
+                .dbg_name = #clk_id, \
+        }, \
         }
 
 #endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 2069bfaa3a2..22a53766962 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -15,74 +15,32 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
 #include <linux/list.h>
 #include <linux/err.h>
-#include <linux/clk.h>
 #include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/ctype.h>
 #include <linux/pm_qos_params.h>
-#include <mach/clk.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
 
 #include "clock.h"
-#include "proc_comm.h"
-#include "clock-7x30.h"
 
 static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clocks_lock);
 static LIST_HEAD(clocks);
-struct clk *msm_clocks;
-unsigned msm_num_clocks;
-
-/*
- * Bitmap of enabled clocks, excluding ACPU which is always
- * enabled
- */
-static DECLARE_BITMAP(clock_map_enabled, NR_CLKS);
-static DEFINE_SPINLOCK(clock_map_lock);
 
 /*
  * Standard clock functions defined in include/linux/clk.h
  */
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *clk;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(clk, &clocks, list)
-                if (!strcmp(id, clk->name) && clk->dev == dev)
-                        goto found_it;
-
-        list_for_each_entry(clk, &clocks, list)
-                if (!strcmp(id, clk->name) && clk->dev == NULL)
-                        goto found_it;
-
-        clk = ERR_PTR(-ENOENT);
-found_it:
-        mutex_unlock(&clocks_mutex);
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
         spin_lock_irqsave(&clocks_lock, flags);
         clk->count++;
-        if (clk->count == 1) {
+        if (clk->count == 1)
                 clk->ops->enable(clk->id);
-                spin_lock(&clock_map_lock);
-                clock_map_enabled[BIT_WORD(clk->id)] |= BIT_MASK(clk->id);
-                spin_unlock(&clock_map_lock);
-        }
         spin_unlock_irqrestore(&clocks_lock, flags);
         return 0;
 }
@@ -94,20 +52,14 @@ void clk_disable(struct clk *clk)
         spin_lock_irqsave(&clocks_lock, flags);
         BUG_ON(clk->count == 0);
         clk->count--;
-        if (clk->count == 0) {
+        if (clk->count == 0)
                 clk->ops->disable(clk->id);
-                spin_lock(&clock_map_lock);
-                clock_map_enabled[BIT_WORD(clk->id)] &= ~BIT_MASK(clk->id);
-                spin_unlock(&clock_map_lock);
-        }
         spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
 int clk_reset(struct clk *clk, enum clk_reset_action action)
 {
-        if (!clk->ops->reset)
-                clk->ops->reset = &pc_clk_reset;
         return clk->ops->reset(clk->remote_id, action);
 }
 EXPORT_SYMBOL(clk_reset);
@@ -184,25 +136,14 @@ EXPORT_SYMBOL(clk_set_flags);
  */
 static struct clk *ebi1_clk;
 
-static void __init set_clock_ops(struct clk *clk)
-{
-        if (!clk->ops) {
-                clk->ops = &clk_ops_pcom;
-                clk->id = clk->remote_id;
-        }
-}
-
-void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks)
+void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
 {
         unsigned n;
 
-        spin_lock_init(&clocks_lock);
         mutex_lock(&clocks_mutex);
-        msm_clocks = clock_tbl;
-        msm_num_clocks = num_clocks;
-        for (n = 0; n < msm_num_clocks; n++) {
-                set_clock_ops(&msm_clocks[n]);
-                list_add_tail(&msm_clocks[n].list, &clocks);
+        for (n = 0; n < num_clocks; n++) {
+                clkdev_add(&clock_tbl[n]);
+                list_add_tail(&clock_tbl[n].clk->list, &clocks);
         }
         mutex_unlock(&clocks_mutex);
 
@@ -211,115 +152,6 @@ void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks)
 
 }
 
-#if defined(CONFIG_DEBUG_FS)
-static struct clk *msm_clock_get_nth(unsigned index)
-{
-        if (index < msm_num_clocks)
-                return msm_clocks + index;
-        else
-                return 0;
-}
-
-static int clock_debug_rate_set(void *data, u64 val)
-{
-        struct clk *clock = data;
-        int ret;
-
-        /* Only increases to max rate will succeed, but that's actually good
-         * for debugging purposes. So we don't check for error. */
-        if (clock->flags & CLK_MAX)
-                clk_set_max_rate(clock, val);
-        if (clock->flags & CLK_MIN)
-                ret = clk_set_min_rate(clock, val);
-        else
-                ret = clk_set_rate(clock, val);
-        if (ret != 0)
-                printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
-                        (clock->flags & CLK_MIN) ? "_min" : "", ret);
-        return ret;
-}
-
-static int clock_debug_rate_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-        *val = clk_get_rate(clock);
-        return 0;
-}
-
-static int clock_debug_enable_set(void *data, u64 val)
-{
-        struct clk *clock = data;
-        int rc = 0;
-
-        if (val)
-                rc = clock->ops->enable(clock->id);
-        else
-                clock->ops->disable(clock->id);
-
-        return rc;
-}
-
-static int clock_debug_enable_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-
-        *val = clock->ops->is_enabled(clock->id);
-
-        return 0;
-}
-
-static int clock_debug_local_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-
-        *val = clock->ops != &clk_ops_pcom;
-
-        return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
-                        clock_debug_rate_set, "%llu\n");
-DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
-                        clock_debug_enable_set, "%llu\n");
-DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get,
-                        NULL, "%llu\n");
-
-static int __init clock_debug_init(void)
-{
-        struct dentry *dent_rate, *dent_enable, *dent_local;
-        struct clk *clock;
-        unsigned n = 0;
-        char temp[50], *ptr;
-
-        dent_rate = debugfs_create_dir("clk_rate", 0);
-        if (IS_ERR(dent_rate))
-                return PTR_ERR(dent_rate);
-
-        dent_enable = debugfs_create_dir("clk_enable", 0);
-        if (IS_ERR(dent_enable))
-                return PTR_ERR(dent_enable);
-
-        dent_local = debugfs_create_dir("clk_local", NULL);
-        if (IS_ERR(dent_local))
-                return PTR_ERR(dent_local);
-
-        while ((clock = msm_clock_get_nth(n++)) != 0) {
-                strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
-                for (ptr = temp; *ptr; ptr++)
-                        *ptr = tolower(*ptr);
-                debugfs_create_file(temp, 0644, dent_rate,
-                                    clock, &clock_rate_fops);
-                debugfs_create_file(temp, 0644, dent_enable,
-                                    clock, &clock_enable_fops);
-                debugfs_create_file(temp, S_IRUGO, dent_local,
-                                    clock, &clock_local_fops);
-        }
-        return 0;
-}
-
-device_initcall(clock_debug_init);
-#endif
-
 /* The bootloader and/or AMSS may have left various clocks enabled.
  * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
  * not been explicitly enabled by a clk_enable() call.
@@ -330,8 +162,10 @@ static int __init clock_late_init(void)
         struct clk *clk;
         unsigned count = 0;
 
+        clock_debug_init();
         mutex_lock(&clocks_mutex);
         list_for_each_entry(clk, &clocks, list) {
+                clock_debug_add(clk);
                 if (clk->flags & CLKFLAG_AUTO_OFF) {
                         spin_lock_irqsave(&clocks_lock, flags);
                         if (!clk->count) {
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index c270b552ed1..2c007f606d2 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -17,12 +17,10 @@
 #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
 #define __ARCH_ARM_MACH_MSM_CLOCK_H
 
+#include <linux/init.h>
 #include <linux/list.h>
 #include <mach/clk.h>
 
-#include "clock-pcom.h"
-#include "clock-7x30.h"
-
 #define CLKFLAG_INVERT                  0x00000001
 #define CLKFLAG_NOINVERT                0x00000002
 #define CLKFLAG_NONEST                  0x00000004
@@ -45,6 +43,7 @@ struct clk_ops {
         unsigned (*get_rate)(unsigned id);
         unsigned (*is_enabled)(unsigned id);
         long (*round_rate)(unsigned id, unsigned rate);
+        bool (*is_local)(unsigned id);
 };
 
 struct clk {
@@ -52,58 +51,22 @@ struct clk {
         uint32_t remote_id;
         uint32_t count;
         uint32_t flags;
-        const char *name;
         struct clk_ops *ops;
         const char *dbg_name;
         struct list_head list;
-        struct device *dev;
 };
 
-#define A11S_CLK_CNTL_ADDR              (MSM_CSR_BASE + 0x100)
-#define A11S_CLK_SEL_ADDR               (MSM_CSR_BASE + 0x104)
-#define A11S_VDD_SVS_PLEVEL_ADDR        (MSM_CSR_BASE + 0x124)
-
-#ifdef CONFIG_DEBUG_FS
-#define CLOCK_DBG_NAME(x) .dbg_name = x,
-#else
-#define CLOCK_DBG_NAME(x)
-#endif
-
-#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) {   \
-        .name = clk_name, \
-        .id = clk_id, \
-        .flags = clk_flags, \
-        .dev = clk_dev, \
-         CLOCK_DBG_NAME(#clk_id) \
-        }
-
 #define OFF CLKFLAG_AUTO_OFF
 #define CLK_MIN CLKFLAG_MIN
 #define CLK_MAX CLKFLAG_MAX
 #define CLK_MINMAX (CLK_MIN | CLK_MAX)
-#define NR_CLKS P_NR_CLKS
-
-enum {
-        PLL_0 = 0,
-        PLL_1,
-        PLL_2,
-        PLL_3,
-        PLL_4,
-        PLL_5,
-        PLL_6,
-        NUM_PLL
-};
-
-enum clkvote_client {
-        CLKVOTE_ACPUCLK = 0,
-        CLKVOTE_PMQOS,
-        CLKVOTE_MAX,
-};
-
-int msm_clock_require_tcxo(unsigned long *reason, int nbits);
-int msm_clock_get_name(uint32_t id, char *name, uint32_t size);
-int ebi1_clk_set_min_rate(enum clkvote_client client, unsigned long rate);
-unsigned long clk_get_max_axi_khz(void);
 
+#ifdef CONFIG_DEBUG_FS
+int __init clock_debug_init(void);
+int __init clock_debug_add(struct clk *clock);
+#else
+static inline int __init clock_debug_init(void) { return 0; }
+static inline int __init clock_debug_add(struct clk *clock) { return 0; }
 #endif
 
+#endif
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index f9e7bd34ec5..24030d0da6e 100644
--- a/arch/arm/mach-msm/devices-msm8x60-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -18,15 +18,13 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/bootmem.h>
-
-#include <mach/msm_iomap-8x60.h>
-#include <mach/irqs-8x60.h>
+#include <mach/irqs.h>
 #include <mach/iommu.h>
 
 static struct resource msm_iommu_jpegd_resources[] = {
         {
-                .start = MSM_IOMMU_JPEGD_PHYS,
-                .end   = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
+                .start = 0x07300000,
+                .end   = 0x07300000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -46,8 +44,8 @@ static struct resource msm_iommu_jpegd_resources[] = {
 
 static struct resource msm_iommu_vpe_resources[] = {
         {
-                .start = MSM_IOMMU_VPE_PHYS,
-                .end   = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
+                .start = 0x07400000,
+                .end   = 0x07400000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -67,8 +65,8 @@ static struct resource msm_iommu_vpe_resources[] = {
 
 static struct resource msm_iommu_mdp0_resources[] = {
         {
-                .start = MSM_IOMMU_MDP0_PHYS,
-                .end   = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
+                .start = 0x07500000,
+                .end   = 0x07500000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -88,8 +86,8 @@ static struct resource msm_iommu_mdp0_resources[] = {
 
 static struct resource msm_iommu_mdp1_resources[] = {
         {
-                .start = MSM_IOMMU_MDP1_PHYS,
-                .end   = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
+                .start = 0x07600000,
+                .end   = 0x07600000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -109,8 +107,8 @@ static struct resource msm_iommu_mdp1_resources[] = {
 
 static struct resource msm_iommu_rot_resources[] = {
         {
-                .start = MSM_IOMMU_ROT_PHYS,
-                .end   = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
+                .start = 0x07700000,
+                .end   = 0x07700000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -130,8 +128,8 @@ static struct resource msm_iommu_rot_resources[] = {
 
 static struct resource msm_iommu_ijpeg_resources[] = {
         {
-                .start = MSM_IOMMU_IJPEG_PHYS,
-                .end   = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
+                .start = 0x07800000,
+                .end   = 0x07800000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -151,8 +149,8 @@ static struct resource msm_iommu_ijpeg_resources[] = {
 
 static struct resource msm_iommu_vfe_resources[] = {
         {
-                .start = MSM_IOMMU_VFE_PHYS,
-                .end   = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
+                .start = 0x07900000,
+                .end   = 0x07900000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -172,8 +170,8 @@ static struct resource msm_iommu_vfe_resources[] = {
 
 static struct resource msm_iommu_vcodec_a_resources[] = {
         {
-                .start = MSM_IOMMU_VCODEC_A_PHYS,
-                .end   = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
+                .start = 0x07A00000,
+                .end   = 0x07A00000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -193,8 +191,8 @@ static struct resource msm_iommu_vcodec_a_resources[] = {
 
 static struct resource msm_iommu_vcodec_b_resources[] = {
         {
-                .start = MSM_IOMMU_VCODEC_B_PHYS,
-                .end   = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
+                .start = 0x07B00000,
+                .end   = 0x07B00000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -214,8 +212,8 @@ static struct resource msm_iommu_vcodec_b_resources[] = {
 
 static struct resource msm_iommu_gfx3d_resources[] = {
         {
-                .start = MSM_IOMMU_GFX3D_PHYS,
-                .end   = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
+                .start = 0x07C00000,
+                .end   = 0x07C00000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -235,8 +233,8 @@ static struct resource msm_iommu_gfx3d_resources[] = {
 
 static struct resource msm_iommu_gfx2d0_resources[] = {
         {
-                .start = MSM_IOMMU_GFX2D0_PHYS,
-                .end   = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
+                .start = 0x07D00000,
+                .end   = 0x07D00000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -256,8 +254,8 @@ static struct resource msm_iommu_gfx2d0_resources[] = {
 
 static struct resource msm_iommu_gfx2d1_resources[] = {
         {
-                .start = MSM_IOMMU_GFX2D1_PHYS,
-                .end   = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1,
+                .start = 0x07E00000,
+                .end   = 0x07E00000 + SZ_1M - 1,
                 .name  = "physbase",
                 .flags = IORESOURCE_MEM,
         },
@@ -282,55 +280,62 @@ static struct platform_device msm_root_iommu_dev = {
 
 static struct msm_iommu_dev jpegd_iommu = {
         .name = "jpegd",
-        .clk_rate = -1
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev vpe_iommu = {
-        .name = "vpe"
+        .name = "vpe",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev mdp0_iommu = {
-        .name = "mdp0"
+        .name = "mdp0",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev mdp1_iommu = {
-        .name = "mdp1"
+        .name = "mdp1",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev rot_iommu = {
-        .name = "rot"
+        .name = "rot",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev ijpeg_iommu = {
-        .name = "ijpeg"
+        .name = "ijpeg",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev vfe_iommu = {
         .name = "vfe",
-        .clk_rate = -1
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev vcodec_a_iommu = {
-        .name = "vcodec_a"
+        .name = "vcodec_a",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev vcodec_b_iommu = {
-        .name = "vcodec_b"
+        .name = "vcodec_b",
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev gfx3d_iommu = {
         .name = "gfx3d",
-        .clk_rate = 27000000
+        .ncb = 3,
 };
 
 static struct msm_iommu_dev gfx2d0_iommu = {
         .name = "gfx2d0",
-        .clk_rate = 27000000
+        .ncb = 2,
 };
 
 static struct msm_iommu_dev gfx2d1_iommu = {
         .name = "gfx2d1",
-        .clk_rate = 27000000
+        .ncb = 2,
 };
 
 static struct platform_device msm_device_iommu_jpegd = {
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index fb548a8a21d..c4f5e26feb4 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -15,6 +15,7 @@
 
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/clkdev.h>
 
 #include <mach/irqs.h>
 #include <mach/msm_iomap.h>
@@ -24,8 +25,8 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
-
 #include "clock.h"
+#include "clock-pcom.h"
 #include <mach/mmc.h>
 
 static struct resource resources_uart1[] = {
@@ -38,6 +39,7 @@ static struct resource resources_uart1[] = {
                 .start  = MSM_UART1_PHYS,
                 .end    = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
+                .name  = "uart_resource"
         },
 };
 
@@ -51,6 +53,7 @@ static struct resource resources_uart2[] = {
                 .start  = MSM_UART2_PHYS,
                 .end    = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
+                .name  = "uart_resource"
         },
 };
 
@@ -64,6 +67,7 @@ static struct resource resources_uart3[] = {
                 .start  = MSM_UART3_PHYS,
                 .end    = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
+                .name  = "uart_resource"
         },
 };
 
@@ -414,7 +418,7 @@ struct platform_device msm_device_mdp = {
         .resource = resources_mdp,
 };
 
-struct clk msm_clocks_7x01a[] = {
+struct clk_lookup msm_clocks_7x01a[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, 0),
@@ -423,7 +427,7 @@ struct clk msm_clocks_7x01a[] = {
         CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF),
         CLK_PCOM("gp_clk",              GP_CLK,         NULL, 0),
         CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, OFF),
-        CLK_PCOM("i2c_clk",     I2C_CLK,        &msm_device_i2c.dev, 0),
+        CLK_PCOM("i2c_clk",     I2C_CLK,        "msm_i2c.0", 0),
         CLK_PCOM("icodec_rx_clk",       ICODEC_RX_CLK,  NULL, 0),
         CLK_PCOM("icodec_tx_clk",       ICODEC_TX_CLK,  NULL, 0),
         CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
@@ -433,25 +437,25 @@ struct clk msm_clocks_7x01a[] = {
         CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
         CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
-        CLK_PCOM("sdc_clk",     SDC1_CLK,       &msm_device_sdc1.dev, OFF),
-        CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     &msm_device_sdc1.dev, OFF),
-        CLK_PCOM("sdc_clk",     SDC2_CLK,       &msm_device_sdc2.dev, OFF),
-        CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     &msm_device_sdc2.dev, OFF),
-        CLK_PCOM("sdc_clk",     SDC3_CLK,       &msm_device_sdc3.dev, OFF),
-        CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     &msm_device_sdc3.dev, OFF),
-        CLK_PCOM("sdc_clk",     SDC4_CLK,       &msm_device_sdc4.dev, OFF),
-        CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     &msm_device_sdc4.dev, OFF),
+        CLK_PCOM("sdc_clk",     SDC1_CLK,       "msm_sdcc.1", OFF),
+        CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     "msm_sdcc.1", OFF),
+        CLK_PCOM("sdc_clk",     SDC2_CLK,       "msm_sdcc.2", OFF),
+        CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     "msm_sdcc.2", OFF),
+        CLK_PCOM("sdc_clk",     SDC3_CLK,       "msm_sdcc.3", OFF),
+        CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     "msm_sdcc.3", OFF),
+        CLK_PCOM("sdc_clk",     SDC4_CLK,       "msm_sdcc.4", OFF),
+        CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     "msm_sdcc.4", OFF),
         CLK_PCOM("tsif_clk",    TSIF_CLK,       NULL, 0),
         CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-        CLK_PCOM("uart_clk",    UART1_CLK,      &msm_device_uart1.dev, OFF),
-        CLK_PCOM("uart_clk",    UART2_CLK,      &msm_device_uart2.dev, 0),
-        CLK_PCOM("uart_clk",    UART3_CLK,      &msm_device_uart3.dev, OFF),
+        CLK_PCOM("uart_clk",    UART1_CLK,      "msm_serial.0", OFF),
+        CLK_PCOM("uart_clk",    UART2_CLK,      "msm_serial.1", 0),
+        CLK_PCOM("uart_clk",    UART3_CLK,      "msm_serial.2", OFF),
         CLK_PCOM("uart1dm_clk", UART1DM_CLK,    NULL, OFF),
         CLK_PCOM("uart2dm_clk", UART2DM_CLK,    NULL, 0),
-        CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     &msm_device_hsusb.dev, OFF),
-        CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   &msm_device_hsusb.dev, OFF),
+        CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     "msm_hsusb", OFF),
+        CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   "msm_hsusb", OFF),
         CLK_PCOM("usb_otg_clk", USB_OTG_CLK,    NULL, 0),
         CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF ),
         CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 4e9a0ab3e93..09b4f140382 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,6 +17,7 @@
 #include <linux/platform_device.h>
 
 #include <linux/dma-mapping.h>
+#include <linux/clkdev.h>
 #include <mach/irqs.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
@@ -28,6 +29,7 @@
 #include <asm/mach/flash.h>
 
 #include "clock-pcom.h"
+#include "clock-7x30.h"
 
 #include <mach/mmc.h>
 
@@ -41,6 +43,7 @@ static struct resource resources_uart2[] = {
                 .start  = MSM_UART2_PHYS,
                 .end    = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
+                .name  = "uart_resource"
         },
 };
 
@@ -127,11 +130,13 @@ struct platform_device msm_device_hsusb_host = {
         },
 };
 
-struct clk msm_clocks_7x30[] = {
+struct clk_lookup msm_clocks_7x30[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
         CLK_PCOM("cam_m_clk",   CAM_M_CLK,      NULL, 0),
         CLK_PCOM("camif_pad_pclk",      CAMIF_PAD_P_CLK,        NULL, OFF),
+        CLK_PCOM("ce_clk",      CE_CLK, NULL, 0),
+        CLK_PCOM("codec_ssbi_clk",      CODEC_SSBI_CLK, NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
         CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
         CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
@@ -177,7 +182,7 @@ struct clk msm_clocks_7x30[] = {
         CLK_7X30S("tv_src_clk", TV_CLK,         TV_ENC_CLK,     NULL, 0),
         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-        CLK_PCOM("uart_clk",    UART2_CLK,      &msm_device_uart2.dev, 0),
+        CLK_PCOM("uart_clk",    UART2_CLK,      "msm_serial.1", 0),
         CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
         CLK_PCOM("usb_hs_clk",          USB_HS_CLK,             NULL, OFF),
         CLK_PCOM("usb_hs_pclk",         USB_HS_P_CLK,           NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c
new file mode 100644
index 00000000000..d9e1f26475d
--- /dev/null
+++ b/arch/arm/mach-msm/devices-msm8960.c
@@ -0,0 +1,85 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <linux/dma-mapping.h>
+#include <mach/irqs-8960.h>
+#include <mach/board.h>
+
+#include "devices.h"
+
+#define MSM_GSBI2_PHYS          0x16100000
+#define MSM_UART2DM_PHYS        (MSM_GSBI2_PHYS + 0x40000)
+
+#define MSM_GSBI5_PHYS          0x16400000
+#define MSM_UART5DM_PHYS        (MSM_GSBI5_PHYS + 0x40000)
+
+static struct resource resources_uart_gsbi2[] = {
+        {
+                .start  = GSBI2_UARTDM_IRQ,
+                .end    = GSBI2_UARTDM_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = MSM_UART2DM_PHYS,
+                .end    = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
+                .name   = "uart_resource",
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MSM_GSBI2_PHYS,
+                .end    = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
+                .name   = "gsbi_resource",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device msm8960_device_uart_gsbi2 = {
+        .name   = "msm_serial",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(resources_uart_gsbi2),
+        .resource       = resources_uart_gsbi2,
+};
+
+static struct resource resources_uart_gsbi5[] = {
+        {
+                .start  = GSBI5_UARTDM_IRQ,
+                .end    = GSBI5_UARTDM_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = MSM_UART5DM_PHYS,
+                .end    = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
+                .name   = "uart_resource",
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MSM_GSBI5_PHYS,
+                .end    = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
+                .name   = "gsbi_resource",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device msm8960_device_uart_gsbi5 = {
+        .name   = "msm_serial",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(resources_uart_gsbi5),
+        .resource       = resources_uart_gsbi5,
+};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index a4b798f20cc..12d8deb78d9 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,8 +15,9 @@
 
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
-
+#include <linux/clkdev.h>
 #include <linux/dma-mapping.h>
+
 #include <mach/irqs.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
@@ -27,6 +28,7 @@
 #include <asm/mach/flash.h>
 
 #include <mach/mmc.h>
+#include "clock-pcom.h"
 
 static struct resource resources_uart3[] = {
         {
@@ -38,6 +40,7 @@ static struct resource resources_uart3[] = {
                 .start  = MSM_UART3_PHYS,
                 .end    = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
+                .name  = "uart_resource"
         },
 };
 
@@ -124,14 +127,204 @@ struct platform_device msm_device_hsusb_host = {
         },
 };
 
-struct clk msm_clocks_8x50[] = {
+static struct resource resources_sdc1[] = {
+        {
+                .start  = MSM_SDC1_PHYS,
+                .end    = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_SDC1_0,
+                .end    = INT_SDC1_0,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "cmd_irq",
+        },
+        {
+                .start  = INT_SDC1_1,
+                .end    = INT_SDC1_1,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "pio_irq",
+        },
+        {
+                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
+                .name   = "status_irq"
+        },
+        {
+                .start  = 8,
+                .end    = 8,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource resources_sdc2[] = {
+        {
+                .start  = MSM_SDC2_PHYS,
+                .end    = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_SDC2_0,
+                .end    = INT_SDC2_0,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "cmd_irq",
+        },
+                {
+                .start  = INT_SDC2_1,
+                .end    = INT_SDC2_1,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "pio_irq",
+        },
+        {
+                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
+                .name   = "status_irq"
+        },
+        {
+                .start  = 8,
+                .end    = 8,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource resources_sdc3[] = {
+        {
+                .start  = MSM_SDC3_PHYS,
+                .end    = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_SDC3_0,
+                .end    = INT_SDC3_0,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "cmd_irq",
+        },
+                {
+                .start  = INT_SDC3_1,
+                .end    = INT_SDC3_1,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "pio_irq",
+        },
+        {
+                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
+                .name   = "status_irq"
+        },
+        {
+                .start  = 8,
+                .end    = 8,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource resources_sdc4[] = {
+        {
+                .start  = MSM_SDC4_PHYS,
+                .end    = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_SDC4_0,
+                .end    = INT_SDC4_0,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "cmd_irq",
+        },
+                {
+                .start  = INT_SDC4_1,
+                .end    = INT_SDC4_1,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "pio_irq",
+        },
+        {
+                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
+                .name   = "status_irq"
+        },
+        {
+                .start  = 8,
+                .end    = 8,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device msm_device_sdc1 = {
+        .name           = "msm_sdcc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(resources_sdc1),
+        .resource       = resources_sdc1,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+struct platform_device msm_device_sdc2 = {
+        .name           = "msm_sdcc",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(resources_sdc2),
+        .resource       = resources_sdc2,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+struct platform_device msm_device_sdc3 = {
+        .name           = "msm_sdcc",
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(resources_sdc3),
+        .resource       = resources_sdc3,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+struct platform_device msm_device_sdc4 = {
+        .name           = "msm_sdcc",
+        .id             = 4,
+        .num_resources  = ARRAY_SIZE(resources_sdc4),
+        .resource       = resources_sdc4,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+static struct platform_device *msm_sdcc_devices[] __initdata = {
+        &msm_device_sdc1,
+        &msm_device_sdc2,
+        &msm_device_sdc3,
+        &msm_device_sdc4,
+};
+
+int __init msm_add_sdcc(unsigned int controller,
+                        struct msm_mmc_platform_data *plat,
+                        unsigned int stat_irq, unsigned long stat_irq_flags)
+{
+        struct platform_device  *pdev;
+        struct resource *res;
+
+        if (controller < 1 || controller > 4)
+                return -EINVAL;
+
+        pdev = msm_sdcc_devices[controller-1];
+        pdev->dev.platform_data = plat;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
+        if (!res)
+                return -EINVAL;
+        else if (stat_irq) {
+                res->start = res->end = stat_irq;
+                res->flags &= ~IORESOURCE_DISABLED;
+                res->flags |= stat_irq_flags;
+        }
+
+        return platform_device_register(pdev);
+}
+
+struct clk_lookup msm_clocks_8x50[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
+        CLK_PCOM("ce_clk",      CE_CLK,         NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
         CLK_PCOM("ebi2_clk",    EBI2_CLK,       NULL, 0),
         CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
         CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
         CLK_PCOM("gp_clk",      GP_CLK,         NULL, 0),
         CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
+        CLK_PCOM("i2c_clk",     I2C_CLK,        NULL, 0),
         CLK_PCOM("icodec_rx_clk",       ICODEC_RX_CLK,  NULL, 0),
         CLK_PCOM("icodec_tx_clk",       ICODEC_TX_CLK,  NULL, 0),
         CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
@@ -144,12 +337,24 @@ struct clk msm_clocks_8x50[] = {
         CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, CLK_MIN),
         CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
+        CLK_PCOM("sdc_clk",     SDC1_CLK,       "msm_sdcc.1", OFF),
+        CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     "msm_sdcc.1", OFF),
+        CLK_PCOM("sdc_clk",     SDC2_CLK,       "msm_sdcc.2", OFF),
+        CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     "msm_sdcc.2", OFF),
+        CLK_PCOM("sdc_clk",     SDC3_CLK,       "msm_sdcc.3", OFF),
+        CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     "msm_sdcc.3", OFF),
+        CLK_PCOM("sdc_clk",     SDC4_CLK,       "msm_sdcc.4", OFF),
+        CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     "msm_sdcc.4", OFF),
         CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
         CLK_PCOM("tsif_clk",    TSIF_CLK,       NULL, 0),
         CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-        CLK_PCOM("uart_clk",    UART3_CLK,      &msm_device_uart3.dev, OFF),
+        CLK_PCOM("uart_clk",    UART1_CLK,      NULL, OFF),
+        CLK_PCOM("uart_clk",    UART2_CLK,      NULL, 0),
+        CLK_PCOM("uart_clk",    UART3_CLK,      "msm_serial.2", OFF),
+        CLK_PCOM("uartdm_clk",  UART1DM_CLK,    NULL, OFF),
+        CLK_PCOM("uartdm_clk",  UART2DM_CLK,    NULL, 0),
         CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     NULL, OFF),
         CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   NULL, OFF),
         CLK_PCOM("usb_otg_clk", USB_OTG_CLK,    NULL, 0),
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 87c70bfce2b..9545c196c6e 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -16,12 +16,17 @@
 #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
 #define __ARCH_ARM_MACH_MSM_DEVICES_H
 
+#include <linux/clkdev.h>
+
 #include "clock.h"
 
 extern struct platform_device msm_device_uart1;
 extern struct platform_device msm_device_uart2;
 extern struct platform_device msm_device_uart3;
 
+extern struct platform_device msm8960_device_uart_gsbi2;
+extern struct platform_device msm8960_device_uart_gsbi5;
+
 extern struct platform_device msm_device_sdc1;
 extern struct platform_device msm_device_sdc2;
 extern struct platform_device msm_device_sdc3;
@@ -41,13 +46,13 @@ extern struct platform_device msm_device_mddi0;
 extern struct platform_device msm_device_mddi1;
 extern struct platform_device msm_device_mdp;
 
-extern struct clk msm_clocks_7x01a[];
+extern struct clk_lookup msm_clocks_7x01a[];
 extern unsigned msm_num_clocks_7x01a;
 
-extern struct clk msm_clocks_7x30[];
+extern struct clk_lookup msm_clocks_7x30[];
 extern unsigned msm_num_clocks_7x30;
 
-extern struct clk msm_clocks_8x50[];
+extern struct clk_lookup msm_clocks_8x50[];
 extern unsigned msm_num_clocks_8x50;
 
 #endif
diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c
deleted file mode 100644
index 6ce41c5241a..00000000000
--- a/arch/arm/mach-msm/gpiomux-7x30.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include "gpiomux.h"
-
-struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
-#ifdef CONFIG_SERIAL_MSM_CONSOLE
-        [49] = { /* UART2 RFR */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-        [50] = { /* UART2 CTS */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-        [51] = { /* UART2 RX */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-        [52] = { /* UART2 TX */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-#endif
-};
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
index 4406e0f4ae9..f7a4ea593c9 100644
--- a/arch/arm/mach-msm/gpiomux-8x50.c
+++ b/arch/arm/mach-msm/gpiomux-8x50.c
@@ -16,6 +16,19 @@
  */
 #include "gpiomux.h"
 
+#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
+        #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
+                                        | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
+        #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
+                                        | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
+#else
+        #define SDCC_DAT_0_3_CMD_ACTV_CFG 0
+        #define SDCC_CLK_ACTV_CFG 0
+#endif
+
+#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
+                                | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
+
 struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
         [86] = { /* UART3 RX */
                 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
@@ -25,4 +38,14 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
                 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
                              GPIOMUX_FUNC_1 | GPIOMUX_VALID,
         },
+        /* SDC1 data[3:0] & CMD */
+        [51 ... 55] = {
+                .active = SDCC_DAT_0_3_CMD_ACTV_CFG,
+                .suspended = SDC1_SUSPEND_CONFIG
+        },
+        /* SDC1 CLK */
+        [56] = {
+                .active = SDCC_CLK_ACTV_CFG,
+                .suspended = SDC1_SUSPEND_CONFIG
+        },
 };
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
index d0c214338df..0c631a9f864 100644
--- a/arch/arm/mach-msm/headsmp.S
+++ b/arch/arm/mach-msm/headsmp.S
@@ -11,7 +11,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-        __INIT
+        __CPUINIT
 
 /*
  * MSM specific entry point for secondary CPUs.  This provides
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 6abf4a6eadc..2ce8f1f2fc4 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -31,7 +31,7 @@ struct msm_acpu_clock_platform_data
         unsigned long wait_for_irq_khz;
 };
 
-struct clk;
+struct clk_lookup;
 
 extern struct sys_timer msm_timer;
 
@@ -41,7 +41,7 @@ void __init msm_add_devices(void);
 void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
-void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks);
+void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
 void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
 int __init msm_add_sdcc(unsigned int controller,
                         struct msm_mmc_platform_data *plat,
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
index c05ca40478c..e8d38428d81 100644
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -1,30 +1,13 @@
 /* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 #ifndef __MACH_CLK_H
 #define __MACH_CLK_H
diff --git a/arch/arm/mach-msm/include/mach/clkdev.h b/arch/arm/mach-msm/include/mach/clkdev.h
new file mode 100644
index 00000000000..f87a57b5953
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_MSM_CLKDEV_H
+#define __ASM_ARCH_MSM_CLKDEV_H
+
+struct clk;
+
+static inline int __clk_get(struct clk *clk) { return 1; }
+static inline void __clk_put(struct clk *clk) { }
+#endif
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
new file mode 100644
index 00000000000..a9481b08d5c
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -0,0 +1,54 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
+#define __ARCH_ARM_MACH_MSM_CPU_H__
+
+/* TODO: For now, only one CPU can be compiled at a time. */
+
+#define cpu_is_msm7x01()        0
+#define cpu_is_msm7x30()        0
+#define cpu_is_qsd8x50()        0
+#define cpu_is_msm8x60()        0
+#define cpu_is_msm8960()        0
+
+#ifdef CONFIG_ARCH_MSM7X00A
+# undef cpu_is_msm7x01
+# define cpu_is_msm7x01()       1
+#endif
+
+#ifdef CONFIG_ARCH_MSM7X30
+# undef cpu_is_msm7x30
+# define cpu_is_msm7x30()       1
+#endif
+
+#ifdef CONFIG_ARCH_QSD8X50
+# undef cpu_is_qsd8x50
+# define cpu_is_qsd8x50()       1
+#endif
+
+#ifdef CONFIG_ARCH_MSM8X60
+# undef cpu_is_msm8x60
+# define cpu_is_msm8x60()       1
+#endif
+
+#ifdef CONFIG_ARCH_MSM8960
+# undef cpu_is_msm8960
+# define cpu_is_msm8960()       1
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e732baa..dc1b928745e 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 void msm_map_msm8x60_io(void);
+void msm_map_msm8960_io(void);
 
 extern unsigned int msm_shared_ram_phys;
 
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 296c0f10f23..5c7c955e6d2 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,7 @@
 #define MSM_IOMMU_H
 
 #include <linux/interrupt.h>
+#include <linux/clk.h>
 
 /* Sharability attributes of MSM IOMMU mappings */
 #define MSM_IOMMU_ATTR_NON_SH           0x0
@@ -44,14 +45,11 @@
 /**
  * struct msm_iommu_dev - a single IOMMU hardware instance
  * name         Human-readable name given to this IOMMU HW instance
- * clk_rate     Rate to set for this IOMMU's clock, if applicable to this
- *              particular IOMMU. 0 means don't set a rate.
- *              -1 means it is an AXI clock with no valid rate
- *
+ * ncb          Number of context banks present on this IOMMU HW instance
  */
 struct msm_iommu_dev {
         const char *name;
-        int clk_rate;
+        int ncb;
 };
 
 /**
@@ -73,14 +71,20 @@ struct msm_iommu_ctx_dev {
 /**
  * struct msm_iommu_drvdata - A single IOMMU hardware instance
  * @base:       IOMMU config port base address (VA)
+ * @ncb         The number of contexts on this IOMMU
  * @irq:        Interrupt number
-  *
+ * @clk:        The bus clock for this IOMMU hardware instance
+ * @pclk:       The clock for the IOMMU bus interconnect
+ *
  * A msm_iommu_drvdata holds the global driver data about a single piece
  * of an IOMMU hardware instance.
  */
 struct msm_iommu_drvdata {
         void __iomem *base;
         int irq;
+        int ncb;
+        struct clk *clk;
+        struct clk *pclk;
 };
 
 /**
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
index c2c3da9444f..fc160101dea 100644
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -68,6 +68,7 @@ do { \
 #define FL_CACHEABLE            (1 << 3)
 #define FL_TEX0                 (1 << 12)
 #define FL_OFFSET(va)           (((va) & 0xFFF00000) >> 20)
+#define FL_NG                   (1 << 17)
 
 /* Second-level page table bits */
 #define SL_BASE_MASK_LARGE      0xFFFF0000
@@ -81,6 +82,7 @@ do { \
 #define SL_CACHEABLE            (1 << 3)
 #define SL_TEX0                 (1 << 6)
 #define SL_OFFSET(va)           (((va) & 0xFF000) >> 12)
+#define SL_NG                   (1 << 11)
 
 /* Memory type and cache policy attributes */
 #define MT_SO                   0
@@ -623,20 +625,6 @@ do { \
 #define SET_INDEX(b, c, v)       SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
 
 
-/* V2Pxx UW UR PW PR */
-#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
-#define SET_V2PUW_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
-
-#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
-#define SET_V2PUR_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
-
-#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
-#define SET_V2PPW_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
-
-#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
-#define SET_V2PPR_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
-
-
 /* Context Register getters */
 /* ACTLR */
 #define GET_CFERE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
@@ -824,20 +812,6 @@ do { \
 #define GET_INDEX(b, c)         GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
 
 
-/* V2Pxx UW UR PW PR */
-#define GET_V2PUW_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
-#define GET_V2PUW_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
-
-#define GET_V2PUR_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
-#define GET_V2PUR_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
-
-#define GET_V2PPW_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
-#define GET_V2PPW_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
-
-#define GET_V2PPR_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
-#define GET_V2PPR_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
-
-
 /* Global Registers */
 #define M2VCBR_N        (0xFF000)
 #define CBACR_N         (0xFF800)
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h
index 67c5396514f..1f15902655f 100644
--- a/arch/arm/mach-msm/include/mach/irqs-7x30.h
+++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h
@@ -1,30 +1,13 @@
 /* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #ifndef __ASM_ARCH_MSM_IRQS_7X30_H
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 00000000000..81ab2a6792b
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,277 @@
+/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8960_H
+#define __ASM_ARCH_MSM_IRQS_8960_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+   16-31: PPI (private peripheral interrupts)
+   32+:   SPI (shared peripheral interrupts) */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC                                (GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP                     (GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP                        (GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP                       (GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT                   (GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT                   (GIC_PPI_START + 5)
+#define AVS_SVICINT                             (GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE                       (GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL                   (GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY                  (GIC_PPI_START + 9)
+#define CPU_SICCPUXPERFMONIRPTREQ               (GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN                          (GIC_PPI_START + 11)
+#define SC_AVSCPUXUP                            (GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ                    (GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ               (GIC_PPI_START + 14)
+/* PPI 15 is unused */
+
+#define SC_SICMPUIRPTREQ                        (GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ                         (GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ                  (GIC_SPI_START + 2)
+#define SC_SICAGCIRPTREQ                        (GIC_SPI_START + 3)
+#define TLMM_APCC_DIR_CONN_IRQ_0                (GIC_SPI_START + 4)
+#define TLMM_APCC_DIR_CONN_IRQ_1                (GIC_SPI_START + 5)
+#define TLMM_APCC_DIR_CONN_IRQ_2                (GIC_SPI_START + 6)
+#define TLMM_APCC_DIR_CONN_IRQ_3                (GIC_SPI_START + 7)
+#define TLMM_APCC_DIR_CONN_IRQ_4                (GIC_SPI_START + 8)
+#define TLMM_APCC_DIR_CONN_IRQ_5                (GIC_SPI_START + 9)
+#define TLMM_APCC_DIR_CONN_IRQ_6                (GIC_SPI_START + 10)
+#define TLMM_APCC_DIR_CONN_IRQ_7                (GIC_SPI_START + 11)
+#define TLMM_APCC_DIR_CONN_IRQ_8                (GIC_SPI_START + 12)
+#define TLMM_APCC_DIR_CONN_IRQ_9                (GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103                      (GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106                      (GIC_SPI_START + 15)
+#define TLMM_APCC_SUMMARY_IRQ                   (GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ                           (GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ                           (GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ               (GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ             (GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ                (GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ               (GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ               (GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ             (GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ                (GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ               (GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ              (GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ          (GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ              (GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ          (GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ                      (GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ                      (GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ                   (GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ                    (GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ                   (GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ                   (GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0                       (GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1                       (GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2                       (GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3                       (GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4                       (GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5                       (GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6                       (GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7                       (GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8                       (GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9                       (GIC_SPI_START + 46)
+#define VPE_IRQ                                 (GIC_SPI_START + 47)
+#define VFE_IRQ                                 (GIC_SPI_START + 48)
+#define VCODEC_IRQ                              (GIC_SPI_START + 49)
+#define TV_ENC_IRQ                              (GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ          (GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ          (GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ               (GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ              (GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ              (GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ             (GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ             (GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ             (GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ            (GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 72)
+#define ROT_IRQ                                 (GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ                         (GIC_SPI_START + 74)
+#define MDP_IRQ                                 (GIC_SPI_START + 75)
+#define JPEGD_IRQ                               (GIC_SPI_START + 76)
+#define JPEG_IRQ                                (GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ                           (GIC_SPI_START + 78)
+#define HDMI_IRQ                                (GIC_SPI_START + 79)
+#define GFX3D_IRQ                               (GIC_SPI_START + 80)
+#define GFX2D0_IRQ                              (GIC_SPI_START + 81)
+#define DSI1_IRQ                                (GIC_SPI_START + 82)
+#define CSI_1_IRQ                               (GIC_SPI_START + 83)
+#define CSI_0_IRQ                               (GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ            (GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ                     (GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED                 (GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ                   (GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ                (GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ                  (GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ                            (GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ                          (GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ                         (GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ                         (GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ                            (GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ                            (GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ                            (GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ                            (GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ                          (GIC_SPI_START + 99)
+#define USB1_HS_IRQ                             (GIC_SPI_START + 100)
+#define SDC4_IRQ_0                              (GIC_SPI_START + 101)
+#define SDC3_IRQ_0                              (GIC_SPI_START + 102)
+#define SDC2_IRQ_0                              (GIC_SPI_START + 103)
+#define SDC1_IRQ_0                              (GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ                         (GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ                        (GIC_SPI_START + 106)
+#define SPS_MTI_0                               (GIC_SPI_START + 107)
+#define SPS_MTI_1                               (GIC_SPI_START + 108)
+#define SPS_MTI_2                               (GIC_SPI_START + 109)
+#define SPS_MTI_3                               (GIC_SPI_START + 110)
+#define SPS_MTI_4                               (GIC_SPI_START + 111)
+#define SPS_MTI_5                               (GIC_SPI_START + 112)
+#define SPS_MTI_6                               (GIC_SPI_START + 113)
+#define SPS_MTI_7                               (GIC_SPI_START + 114)
+#define SPS_MTI_8                               (GIC_SPI_START + 115)
+#define SPS_MTI_9                               (GIC_SPI_START + 116)
+#define SPS_MTI_10                              (GIC_SPI_START + 117)
+#define SPS_MTI_11                              (GIC_SPI_START + 118)
+#define SPS_MTI_12                              (GIC_SPI_START + 119)
+#define SPS_MTI_13                              (GIC_SPI_START + 120)
+#define SPS_MTI_14                              (GIC_SPI_START + 121)
+#define SPS_MTI_15                              (GIC_SPI_START + 122)
+#define SPS_MTI_16                              (GIC_SPI_START + 123)
+#define SPS_MTI_17                              (GIC_SPI_START + 124)
+#define SPS_MTI_18                              (GIC_SPI_START + 125)
+#define SPS_MTI_19                              (GIC_SPI_START + 126)
+#define SPS_MTI_20                              (GIC_SPI_START + 127)
+#define SPS_MTI_21                              (GIC_SPI_START + 128)
+#define SPS_MTI_22                              (GIC_SPI_START + 129)
+#define SPS_MTI_23                              (GIC_SPI_START + 130)
+#define SPS_MTI_24                              (GIC_SPI_START + 131)
+#define SPS_MTI_25                              (GIC_SPI_START + 132)
+#define SPS_MTI_26                              (GIC_SPI_START + 133)
+#define SPS_MTI_27                              (GIC_SPI_START + 134)
+#define SPS_MTI_28                              (GIC_SPI_START + 135)
+#define SPS_MTI_29                              (GIC_SPI_START + 136)
+#define SPS_MTI_30                              (GIC_SPI_START + 137)
+#define SPS_MTI_31                              (GIC_SPI_START + 138)
+#define CSIPHY_4LN_IRQ                          (GIC_SPI_START + 139)
+#define CSIPHY_2LN_IRQ                          (GIC_SPI_START + 140)
+#define USB2_IRQ                                (GIC_SPI_START + 141)
+#define USB1_IRQ                                (GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ                           (GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ                         (GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ                          (GIC_SPI_START + 145)
+#define GSBI1_UARTDM_IRQ                        (GIC_SPI_START + 146)
+#define GSBI1_QUP_IRQ                           (GIC_SPI_START + 147)
+#define GSBI2_UARTDM_IRQ                        (GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ                           (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ                        (GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ                           (GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ                        (GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ                           (GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ                        (GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ                           (GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ                        (GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ                           (GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ                        (GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ                           (GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ                        (GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ                           (GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ                           (GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ                            (GIC_SPI_START + 163)
+#define TSIF2_IRQ                               (GIC_SPI_START + 164)
+#define TSIF1_IRQ                               (GIC_SPI_START + 165)
+#define DSI2_IRQ                                (GIC_SPI_START + 166)
+#define ISPIF_IRQ                               (GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ                     (GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ               (GIC_SPI_START + 169)
+#define INT_ADM0_SCSS_0_IRQ                     (GIC_SPI_START + 170)
+#define INT_ADM0_SCSS_1_IRQ                     (GIC_SPI_START + 171)
+#define INT_ADM0_SCSS_2_IRQ                     (GIC_SPI_START + 172)
+#define INT_ADM0_SCSS_3_IRQ                     (GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED             (GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED             (GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED             (GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED             (GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT                   (GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT              (GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT              (GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ                         (GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ               (GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ                      (GIC_SPI_START + 185)
+#define HSDDRX_EBI1CH1_IRQ                      (GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ                            (GIC_SPI_START + 187)
+#define SDC5_IRQ_0                              (GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ                        (GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ                           (GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ                       (GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ                          (GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ                       (GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ                          (GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ                       (GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ                          (GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ                   (GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ                     (GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ       (GIC_SPI_START + 199)
+#define RIVA_ASS_RESET_DONE_IRQ                 (GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ                      (GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ        (GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ       (GIC_SPI_START + 203)
+#define RIVA_APPS_WLAM_SMSM_IRQ                 (GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ                  (GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ                   (GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ                       (GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ                 (GIC_SPI_START + 208)
+#define A2_BAM_IRQ                              (GIC_SPI_START + 209)
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ            (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 211)
+#define GFX2D1_IRQ                              (GIC_SPI_START + 212)
+#define PPSS_WDOG_TIMER_IRQ                     (GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ                (GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ                 (GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ                            (GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ                  (GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ                  (GIC_SPI_START + 218)
+#define TLMM_APCC_DIR_CONN_IRQ_16               (GIC_SPI_START + 219)
+#define TLMM_APCC_DIR_CONN_IRQ_17               (GIC_SPI_START + 220)
+#define TLMM_APCC_DIR_CONN_IRQ_18               (GIC_SPI_START + 221)
+#define TLMM_APCC_DIR_CONN_IRQ_19               (GIC_SPI_START + 222)
+#define TLMM_APCC_DIR_CONN_IRQ_20               (GIC_SPI_START + 223)
+#define TLMM_APCC_DIR_CONN_IRQ_21               (GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104                      (GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107                      (GIC_SPI_START + 226)
+
+/* For now, use the maximum number of interrupts until a pending GIC issue
+ * is sorted out */
+#define NR_MSM_IRQS 1020
+#define NR_BOARD_IRQS 0
+#define NR_GPIO_IRQS 0
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h
index de3d8fe24e4..26adbe0e940 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x50.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h
@@ -1,30 +1,13 @@
 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a456474..3cd78b165ab 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
 #include "sirc.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "irqs-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+/* TODO: Make these not generic. */
+#include "irqs-8960.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 176875df241..f2f8d299ba9 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
 #define PLAT_PHYS_OFFSET                UL(0x00200000)
 #elif defined(CONFIG_ARCH_MSM8X60)
 #define PLAT_PHYS_OFFSET                UL(0x40200000)
+#elif defined(CONFIG_ARCH_MSM8960)
+#define PLAT_PHYS_OFFSET                UL(0x40200000)
 #else
 #define PLAT_PHYS_OFFSET                UL(0x10000000)
 #endif
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h
index d54b6b086cf..5631b51cec4 100644
--- a/arch/arm/mach-msm/include/mach/mmc.h
+++ b/arch/arm/mach-msm/include/mach/mmc.h
@@ -15,12 +15,23 @@ struct embedded_sdio_data {
         int num_funcs;
 };
 
+struct msm_mmc_gpio {
+        unsigned no;
+        const char *name;
+};
+
+struct msm_mmc_gpio_data {
+        struct msm_mmc_gpio *gpio;
+        u8 size;
+};
+
 struct msm_mmc_platform_data {
         unsigned int ocr_mask;                  /* available voltages */
         u32 (*translate_vdd)(struct device *, unsigned int);
         unsigned int (*status)(struct device *);
         struct embedded_sdio_data *embedded_sdio;
         int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
+        struct msm_mmc_gpio_data *gpio_data;
 };
 
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index cfff0e74f12..8f99d97615a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -1,6 +1,7 @@
 /* arch/arm/mach-msm/include/mach/msm_iomap.h
  *
  * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -47,13 +48,8 @@
 #define MSM_VIC_PHYS          0xC0000000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_GPT_PHYS          MSM_CSR_PHYS
-#define MSM_GPT_BASE          MSM_CSR_BASE
-#define MSM_GPT_SIZE          SZ_4K
+#define MSM7X00_CSR_PHYS      0xC0100000
+#define MSM7X00_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xA9700000
@@ -130,10 +126,4 @@
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
 
-#if defined(CONFIG_ARCH_MSM7X30)
-#define MSM_GCC_BASE          IOMEM(0xF8009000)
-#define MSM_GCC_PHYS          0xC0182000
-#define MSM_GCC_SIZE          SZ_4K
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 0fd7b68ca11..4d84be15955 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
 #define MSM_VIC_PHYS          0xC0080000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
-
-#define MSM_GPT_BASE          (MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE          (MSM_TMR_BASE + 0x24)
+#define MSM7X30_CSR_PHYS      0xC0100000
+#define MSM7X30_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xAC400000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 00000000000..3c9d9602a31
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
+#define __ASM_ARCH_MSM_IOMAP_8960_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+
+#define MSM8960_QGIC_DIST_PHYS  0x02000000
+#define MSM8960_QGIC_DIST_SIZE  SZ_4K
+
+#define MSM8960_QGIC_CPU_PHYS   0x02002000
+#define MSM8960_QGIC_CPU_SIZE   SZ_4K
+
+#define MSM8960_TMR_PHYS        0x0200A000
+#define MSM8960_TMR_SIZE        SZ_4K
+
+#define MSM8960_TMR0_PHYS       0x0208A000
+#define MSM8960_TMR0_SIZE       SZ_4K
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index acc819eb76e..d4143201999 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
 #define MSM_VIC_PHYS          0xAC000000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xAC100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
-
-#define MSM_GPT_BASE          MSM_TMR_BASE
-#define MSM_DGT_BASE          (MSM_TMR_BASE + 0x10)
+#define QSD8X50_CSR_PHYS      0xAC100000
+#define QSD8X50_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xA9700000
@@ -132,16 +124,16 @@
 #define MSM_UART2DM_PHYS      0xA0900000
 
 
-#define MSM_SDC1_PHYS          0xA0400000
+#define MSM_SDC1_PHYS          0xA0300000
 #define MSM_SDC1_SIZE          SZ_4K
 
-#define MSM_SDC2_PHYS          0xA0500000
+#define MSM_SDC2_PHYS          0xA0400000
 #define MSM_SDC2_SIZE          SZ_4K
 
-#define MSM_SDC3_PHYS          0xA0600000
+#define MSM_SDC3_PHYS          0xA0500000
 #define MSM_SDC3_SIZE           SZ_4K
 
-#define MSM_SDC4_PHYS          0xA0700000
+#define MSM_SDC4_PHYS          0xA0600000
 #define MSM_SDC4_SIZE          SZ_4K
 
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index a54e33b0882..3b19b8f244b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -35,13 +35,11 @@
  *
  */
 
-#define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
-#define MSM_QGIC_DIST_PHYS      0x02080000
-#define MSM_QGIC_DIST_SIZE      SZ_4K
+#define MSM8X60_QGIC_DIST_PHYS  0x02080000
+#define MSM8X60_QGIC_DIST_SIZE  SZ_4K
 
-#define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
-#define MSM_QGIC_CPU_PHYS       0x02081000
-#define MSM_QGIC_CPU_SIZE       SZ_4K
+#define MSM8X60_QGIC_CPU_PHYS   0x02081000
+#define MSM8X60_QGIC_CPU_SIZE   SZ_4K
 
 #define MSM_ACC_BASE            IOMEM(0xF0002000)
 #define MSM_ACC_PHYS            0x02001000
@@ -58,51 +56,10 @@
 #define MSM_SHARED_RAM_BASE     IOMEM(0xF0100000)
 #define MSM_SHARED_RAM_SIZE     SZ_1M
 
-#define MSM_TMR_BASE            IOMEM(0xF0200000)
-#define MSM_TMR_PHYS            0x02000000
-#define MSM_TMR_SIZE            SZ_4K
+#define MSM8X60_TMR_PHYS        0x02000000
+#define MSM8X60_TMR_SIZE        SZ_4K
 
-#define MSM_TMR0_BASE           IOMEM(0xF0201000)
-#define MSM_TMR0_PHYS           0x02040000
-#define MSM_TMR0_SIZE           SZ_4K
-
-#define MSM_GPT_BASE            (MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE            (MSM_TMR_BASE + 0x24)
-
-#define MSM_IOMMU_JPEGD_PHYS    0x07300000
-#define MSM_IOMMU_JPEGD_SIZE    SZ_1M
-
-#define MSM_IOMMU_VPE_PHYS      0x07400000
-#define MSM_IOMMU_VPE_SIZE      SZ_1M
-
-#define MSM_IOMMU_MDP0_PHYS     0x07500000
-#define MSM_IOMMU_MDP0_SIZE     SZ_1M
-
-#define MSM_IOMMU_MDP1_PHYS     0x07600000
-#define MSM_IOMMU_MDP1_SIZE     SZ_1M
-
-#define MSM_IOMMU_ROT_PHYS      0x07700000
-#define MSM_IOMMU_ROT_SIZE      SZ_1M
-
-#define MSM_IOMMU_IJPEG_PHYS    0x07800000
-#define MSM_IOMMU_IJPEG_SIZE    SZ_1M
-
-#define MSM_IOMMU_VFE_PHYS      0x07900000
-#define MSM_IOMMU_VFE_SIZE      SZ_1M
-
-#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
-#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
-
-#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
-#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
-
-#define MSM_IOMMU_GFX3D_PHYS    0x07C00000
-#define MSM_IOMMU_GFX3D_SIZE    SZ_1M
-
-#define MSM_IOMMU_GFX2D0_PHYS   0x07D00000
-#define MSM_IOMMU_GFX2D0_SIZE   SZ_1M
-
-#define MSM_IOMMU_GFX2D1_PHYS   0x07E00000
-#define MSM_IOMMU_GFX2D1_SIZE   SZ_1M
+#define MSM8X60_TMR0_PHYS       0x02040000
+#define MSM8X60_TMR0_SIZE       SZ_4K
 
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd81213..c98c7591f3b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -53,6 +53,13 @@
 #include "msm_iomap-7x00.h"
 #endif
 
+#include "msm_iomap-8960.h"
 
+/* Virtual addressses shared across all MSM targets. */
+#define MSM_CSR_BASE            IOMEM(0xE0001000)
+#define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
+#define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
+#define MSM_TMR_BASE            IOMEM(0xF0200000)
+#define MSM_TMR0_BASE           IOMEM(0xF0201000)
 
 #endif
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
index 7281337ee28..ef55868a5b8 100644
--- a/arch/arm/mach-msm/include/mach/sirc.h
+++ b/arch/arm/mach-msm/include/mach/sirc.h
@@ -1,30 +1,13 @@
 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #ifndef __ASM_ARCH_MSM_SIRC_H
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
index a95f7b9efe3..3c01000ecc8 100644
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -1,29 +1,13 @@
 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Code Aurora nor
- *       the names of its contributors may be used to endorse or promote
- *       products derived from this software without specific prior written
- *       permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #ifndef __ASM_ARCH_MSM_SMP_H
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 1260007a9dd..cec6ed1c91d 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -3,7 +3,7 @@
  * MSM7K, QSD io support
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -28,19 +28,20 @@
 
 #include <mach/board.h>
 
-#define MSM_DEVICE(name) { \
+#define MSM_CHIP_DEVICE(name, chip) {                         \
                 .virtual = (unsigned long) MSM_##name##_BASE, \
-                .pfn = __phys_to_pfn(MSM_##name##_PHYS), \
-                .length = MSM_##name##_SIZE, \
+                .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
+                .length = chip##_##name##_SIZE, \
                 .type = MT_DEVICE_NONSHARED, \
          }
 
+#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
+
 #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
         || defined(CONFIG_ARCH_MSM7X25)
 static struct map_desc msm_io_desc[] __initdata = {
         MSM_DEVICE(VIC),
-        MSM_DEVICE(CSR),
-        MSM_DEVICE(GPT),
+        MSM_CHIP_DEVICE(CSR, MSM7X00),
         MSM_DEVICE(DMOV),
         MSM_DEVICE(GPIO1),
         MSM_DEVICE(GPIO2),
@@ -73,8 +74,7 @@ void __init msm_map_common_io(void)
 #ifdef CONFIG_ARCH_QSD8X50
 static struct map_desc qsd8x50_io_desc[] __initdata = {
         MSM_DEVICE(VIC),
-        MSM_DEVICE(CSR),
-        MSM_DEVICE(TMR),
+        MSM_CHIP_DEVICE(CSR, QSD8X50),
         MSM_DEVICE(DMOV),
         MSM_DEVICE(GPIO1),
         MSM_DEVICE(GPIO2),
@@ -102,10 +102,10 @@ void __init msm_map_qsd8x50_io(void)
 
 #ifdef CONFIG_ARCH_MSM8X60
 static struct map_desc msm8x60_io_desc[] __initdata = {
-        MSM_DEVICE(QGIC_DIST),
-        MSM_DEVICE(QGIC_CPU),
-        MSM_DEVICE(TMR),
-        MSM_DEVICE(TMR0),
+        MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
+        MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
+        MSM_CHIP_DEVICE(TMR, MSM8X60),
+        MSM_CHIP_DEVICE(TMR0, MSM8X60),
         MSM_DEVICE(ACC),
         MSM_DEVICE(GCC),
 };
@@ -116,11 +116,24 @@ void __init msm_map_msm8x60_io(void)
 }
 #endif /* CONFIG_ARCH_MSM8X60 */
 
+#ifdef CONFIG_ARCH_MSM8960
+static struct map_desc msm8960_io_desc[] __initdata = {
+        MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
+        MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
+        MSM_CHIP_DEVICE(TMR, MSM8960),
+        MSM_CHIP_DEVICE(TMR0, MSM8960),
+};
+
+void __init msm_map_msm8960_io(void)
+{
+        iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8960 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
         MSM_DEVICE(VIC),
-        MSM_DEVICE(CSR),
-        MSM_DEVICE(TMR),
+        MSM_CHIP_DEVICE(CSR, MSM7X30),
         MSM_DEVICE(DMOV),
         MSM_DEVICE(GPIO1),
         MSM_DEVICE(GPIO2),
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index e2d58e4cb0d..1a584e077c6 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -26,6 +26,7 @@
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <linux/iommu.h>
+#include <linux/clk.h>
 
 #include <asm/cacheflush.h>
 #include <asm/sizes.h>
@@ -50,6 +51,30 @@ struct msm_priv {
         struct list_head list_attached;
 };
 
+static int __enable_clocks(struct msm_iommu_drvdata *drvdata)
+{
+        int ret;
+
+        ret = clk_enable(drvdata->pclk);
+        if (ret)
+                goto fail;
+
+        if (drvdata->clk) {
+                ret = clk_enable(drvdata->clk);
+                if (ret)
+                        clk_disable(drvdata->pclk);
+        }
+fail:
+        return ret;
+}
+
+static void __disable_clocks(struct msm_iommu_drvdata *drvdata)
+{
+        if (drvdata->clk)
+                clk_disable(drvdata->clk);
+        clk_disable(drvdata->pclk);
+}
+
 static int __flush_iotlb(struct iommu_domain *domain)
 {
         struct msm_priv *priv = domain->priv;
@@ -77,9 +102,16 @@ static int __flush_iotlb(struct iommu_domain *domain)
                         BUG();
 
                 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
+                BUG_ON(!iommu_drvdata);
+
+                ret = __enable_clocks(iommu_drvdata);
+                if (ret)
+                        goto fail;
+
                 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
+                __disable_clocks(iommu_drvdata);
         }
-
+fail:
         return ret;
 }
 
@@ -105,7 +137,6 @@ static void __reset_context(void __iomem *base, int ctx)
         SET_TLBLKCR(base, ctx, 0);
         SET_PRRR(base, ctx, 0);
         SET_NMRR(base, ctx, 0);
-        SET_CONTEXTIDR(base, ctx, 0);
 }
 
 static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
@@ -265,9 +296,14 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
                         goto fail;
                 }
 
+        ret = __enable_clocks(iommu_drvdata);
+        if (ret)
+                goto fail;
+
         __program_context(iommu_drvdata->base, ctx_dev->num,
                           __pa(priv->pgtable));
 
+        __disable_clocks(iommu_drvdata);
         list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
         ret = __flush_iotlb(domain);
 
@@ -303,7 +339,12 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
         if (ret)
                 goto fail;
 
+        ret = __enable_clocks(iommu_drvdata);
+        if (ret)
+                goto fail;
+
         __reset_context(iommu_drvdata->base, ctx_dev->num);
+        __disable_clocks(iommu_drvdata);
         list_del_init(&ctx_drvdata->attached_elm);
 
 fail:
@@ -376,11 +417,11 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
                 for (i = 0; i < 16; i++)
                         *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
                                   FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
-                                  FL_SHARED | pgprot;
+                                  FL_SHARED | FL_NG | pgprot;
         }
 
         if (len == SZ_1M)
-                *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
+                *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG |
                                             FL_TYPE_SECT | FL_SHARED | pgprot;
 
         /* Need a 2nd level table */
@@ -405,7 +446,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
 
 
         if (len == SZ_4K)
-                *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
+                *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG |
                                           SL_SHARED | SL_TYPE_SMALL | pgprot;
 
         if (len == SZ_64K) {
@@ -413,7 +454,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
 
                 for (i = 0; i < 16; i++)
                         *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
-                                SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
+                            SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
         }
 
         ret = __flush_iotlb(domain);
@@ -532,9 +573,13 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
         base = iommu_drvdata->base;
         ctx = ctx_drvdata->num;
 
+        ret = __enable_clocks(iommu_drvdata);
+        if (ret)
+                goto fail;
+
         /* Invalidate context TLB */
         SET_CTX_TLBIALL(base, ctx, 0);
-        SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
+        SET_V2PPR(base, ctx, va & V2Pxx_VA);
 
         par = GET_PAR(base, ctx);
 
@@ -547,6 +592,7 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
         if (GET_FAULT(base, ctx))
                 ret = 0;
 
+        __disable_clocks(iommu_drvdata);
 fail:
         spin_unlock_irqrestore(&msm_iommu_lock, flags);
         return ret;
@@ -590,7 +636,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
         struct msm_iommu_drvdata *drvdata = dev_id;
         void __iomem *base;
         unsigned int fsr;
-        int ncb, i;
+        int i, ret;
 
         spin_lock(&msm_iommu_lock);
 
@@ -604,8 +650,11 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
         pr_err("Unexpected IOMMU page fault!\n");
         pr_err("base = %08x\n", (unsigned int) base);
 
-        ncb = GET_NCB(base)+1;
-        for (i = 0; i < ncb; i++) {
+        ret = __enable_clocks(drvdata);
+        if (ret)
+                goto fail;
+
+        for (i = 0; i < drvdata->ncb; i++) {
                 fsr = GET_FSR(base, i);
                 if (fsr) {
                         pr_err("Fault occurred in context %d.\n", i);
@@ -614,6 +663,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
                         SET_FSR(base, i, 0x4000000F);
                 }
         }
+        __disable_clocks(drvdata);
 fail:
         spin_unlock(&msm_iommu_lock);
         return 0;
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index b83c73b41fd..8e8fb079852 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -29,6 +29,7 @@
 
 #include <mach/iommu_hw-8xxx.h>
 #include <mach/iommu.h>
+#include <mach/clk.h>
 
 struct iommu_ctx_iter_data {
         /* input */
@@ -84,9 +85,9 @@ fail:
 }
 EXPORT_SYMBOL(msm_iommu_get_ctx);
 
-static void msm_iommu_reset(void __iomem *base)
+static void msm_iommu_reset(void __iomem *base, int ncb)
 {
-        int ctx, ncb;
+        int ctx;
 
         SET_RPUE(base, 0);
         SET_RPUEIE(base, 0);
@@ -99,7 +100,6 @@ static void msm_iommu_reset(void __iomem *base)
         SET_GLOBAL_TLBIALL(base, 0);
         SET_RPU_ACR(base, 0);
         SET_TLBLKCRWE(base, 1);
-        ncb = GET_NCB(base)+1;
 
         for (ctx = 0; ctx < ncb; ctx++) {
                 SET_BPRCOSH(base, ctx, 0);
@@ -130,117 +130,140 @@ static int msm_iommu_probe(struct platform_device *pdev)
 {
         struct resource *r, *r2;
         struct clk *iommu_clk;
+        struct clk *iommu_pclk;
         struct msm_iommu_drvdata *drvdata;
         struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
         void __iomem *regs_base;
         resource_size_t len;
-        int ret = 0, ncb, nm2v, irq;
+        int ret, irq, par;
 
-        if (pdev->id != -1) {
-                drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
+        if (pdev->id == -1) {
+                msm_iommu_root_dev = pdev;
+                return 0;
+        }
 
-                if (!drvdata) {
-                        ret = -ENOMEM;
-                        goto fail;
-                }
+        drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
 
-                if (!iommu_dev) {
-                        ret = -ENODEV;
-                        goto fail;
-                }
+        if (!drvdata) {
+                ret = -ENOMEM;
+                goto fail;
+        }
 
-                if (iommu_dev->clk_rate != 0) {
-                        iommu_clk = clk_get(&pdev->dev, "iommu_clk");
-
-                        if (IS_ERR(iommu_clk)) {
-                                ret = -ENODEV;
-                                goto fail;
-                        }
-
-                        if (iommu_dev->clk_rate > 0) {
-                                ret = clk_set_rate(iommu_clk,
-                                                        iommu_dev->clk_rate);
-                                if (ret) {
-                                        clk_put(iommu_clk);
-                                        goto fail;
-                                }
-                        }
-
-                        ret = clk_enable(iommu_clk);
-                        if (ret) {
-                                clk_put(iommu_clk);
-                                goto fail;
-                        }
+        if (!iommu_dev) {
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        iommu_pclk = clk_get(NULL, "smmu_pclk");
+        if (IS_ERR(iommu_pclk)) {
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        ret = clk_enable(iommu_pclk);
+        if (ret)
+                goto fail_enable;
+
+        iommu_clk = clk_get(&pdev->dev, "iommu_clk");
+
+        if (!IS_ERR(iommu_clk)) {
+                if (clk_get_rate(iommu_clk) == 0)
+                        clk_set_min_rate(iommu_clk, 1);
+
+                ret = clk_enable(iommu_clk);
+                if (ret) {
                         clk_put(iommu_clk);
+                        goto fail_pclk;
                 }
+        } else
+                iommu_clk = NULL;
 
-                r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-                                                 "physbase");
-                if (!r) {
-                        ret = -ENODEV;
-                        goto fail;
-                }
+        r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "physbase");
 
-                len = r->end - r->start + 1;
+        if (!r) {
+                ret = -ENODEV;
+                goto fail_clk;
+        }
 
-                r2 = request_mem_region(r->start, len, r->name);
-                if (!r2) {
-                        pr_err("Could not request memory region: "
-                        "start=%p, len=%d\n", (void *) r->start, len);
-                        ret = -EBUSY;
-                        goto fail;
-                }
+        len = resource_size(r);
 
-                regs_base = ioremap(r2->start, len);
+        r2 = request_mem_region(r->start, len, r->name);
+        if (!r2) {
+                pr_err("Could not request memory region: start=%p, len=%d\n",
+                                                        (void *) r->start, len);
+                ret = -EBUSY;
+                goto fail_clk;
+        }
 
-                if (!regs_base) {
-                        pr_err("Could not ioremap: start=%p, len=%d\n",
-                                 (void *) r2->start, len);
-                        ret = -EBUSY;
-                        goto fail_mem;
-                }
+        regs_base = ioremap(r2->start, len);
 
-                irq = platform_get_irq_byname(pdev, "secure_irq");
-                if (irq < 0) {
-                        ret = -ENODEV;
-                        goto fail_io;
-                }
+        if (!regs_base) {
+                pr_err("Could not ioremap: start=%p, len=%d\n",
+                         (void *) r2->start, len);
+                ret = -EBUSY;
+                goto fail_mem;
+        }
 
-                mb();
+        irq = platform_get_irq_byname(pdev, "secure_irq");
+        if (irq < 0) {
+                ret = -ENODEV;
+                goto fail_io;
+        }
 
-                if (GET_IDR(regs_base) == 0) {
-                        pr_err("Invalid IDR value detected\n");
-                        ret = -ENODEV;
-                        goto fail_io;
-                }
+        msm_iommu_reset(regs_base, iommu_dev->ncb);
 
-                ret = request_irq(irq, msm_iommu_fault_handler, 0,
-                                "msm_iommu_secure_irpt_handler", drvdata);
-                if (ret) {
-                        pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
-                        goto fail_io;
-                }
+        SET_M(regs_base, 0, 1);
+        SET_PAR(regs_base, 0, 0);
+        SET_V2PCFG(regs_base, 0, 1);
+        SET_V2PPR(regs_base, 0, 0);
+        par = GET_PAR(regs_base, 0);
+        SET_V2PCFG(regs_base, 0, 0);
+        SET_M(regs_base, 0, 0);
 
-                msm_iommu_reset(regs_base);
-                drvdata->base = regs_base;
-                drvdata->irq = irq;
+        if (!par) {
+                pr_err("%s: Invalid PAR value detected\n", iommu_dev->name);
+                ret = -ENODEV;
+                goto fail_io;
+        }
 
-                nm2v = GET_NM2VCBMT((unsigned long) regs_base);
-                ncb = GET_NCB((unsigned long) regs_base);
+        ret = request_irq(irq, msm_iommu_fault_handler, 0,
+                        "msm_iommu_secure_irpt_handler", drvdata);
+        if (ret) {
+                pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
+                goto fail_io;
+        }
 
-                pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
-                        iommu_dev->name, regs_base, irq, ncb+1);
 
-                platform_set_drvdata(pdev, drvdata);
-        } else
-                msm_iommu_root_dev = pdev;
+        drvdata->pclk = iommu_pclk;
+        drvdata->clk = iommu_clk;
+        drvdata->base = regs_base;
+        drvdata->irq = irq;
+        drvdata->ncb = iommu_dev->ncb;
 
-        return 0;
+        pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
+                iommu_dev->name, regs_base, irq, iommu_dev->ncb);
+
+        platform_set_drvdata(pdev, drvdata);
+
+        if (iommu_clk)
+                clk_disable(iommu_clk);
+
+        clk_disable(iommu_pclk);
 
+        return 0;
 fail_io:
         iounmap(regs_base);
 fail_mem:
         release_mem_region(r->start, len);
+fail_clk:
+        if (iommu_clk) {
+                clk_disable(iommu_clk);
+                clk_put(iommu_clk);
+        }
+fail_pclk:
+        clk_disable(iommu_pclk);
+fail_enable:
+        clk_put(iommu_pclk);
 fail:
         kfree(drvdata);
         return ret;
@@ -252,7 +275,10 @@ static int msm_iommu_remove(struct platform_device *pdev)
 
         drv = platform_get_drvdata(pdev);
         if (drv) {
-                memset(drv, 0, sizeof(struct msm_iommu_drvdata));
+                if (drv->clk)
+                        clk_put(drv->clk);
+                clk_put(drv->pclk);
+                memset(drv, 0, sizeof(*drv));
                 kfree(drv);
                 platform_set_drvdata(pdev, NULL);
         }
@@ -264,7 +290,7 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev)
         struct msm_iommu_ctx_dev *c = pdev->dev.platform_data;
         struct msm_iommu_drvdata *drvdata;
         struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
-        int i, ret = 0;
+        int i, ret;
         if (!c || !pdev->dev.parent) {
                 ret = -EINVAL;
                 goto fail;
@@ -288,6 +314,18 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev)
         INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
         platform_set_drvdata(pdev, ctx_drvdata);
 
+        ret = clk_enable(drvdata->pclk);
+        if (ret)
+                goto fail;
+
+        if (drvdata->clk) {
+                ret = clk_enable(drvdata->clk);
+                if (ret) {
+                        clk_disable(drvdata->pclk);
+                        goto fail;
+                }
+        }
+
         /* Program the M2V tables for this context */
         for (i = 0; i < MAX_NUM_MIDS; i++) {
                 int mid = c->mids[i];
@@ -297,21 +335,27 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev)
                 SET_M2VCBR_N(drvdata->base, mid, 0);
                 SET_CBACR_N(drvdata->base, c->num, 0);
 
-                /* Set VMID = MID */
-                SET_VMID(drvdata->base, mid, mid);
+                /* Set VMID = 0 */
+                SET_VMID(drvdata->base, mid, 0);
 
                 /* Set the context number for that MID to this context */
                 SET_CBNDX(drvdata->base, mid, c->num);
 
-                /* Set MID associated with this context bank */
-                SET_CBVMID(drvdata->base, c->num, mid);
+                /* Set MID associated with this context bank to 0*/
+                SET_CBVMID(drvdata->base, c->num, 0);
+
+                /* Set the ASID for TLB tagging for this context */
+                SET_CONTEXTIDR_ASID(drvdata->base, c->num, c->num);
 
                 /* Set security bit override to be Non-secure */
                 SET_NSCFG(drvdata->base, mid, 3);
         }
 
-        pr_info("context device %s with bank index %d\n", c->name, c->num);
+        if (drvdata->clk)
+                clk_disable(drvdata->clk);
+        clk_disable(drvdata->pclk);
 
+        dev_info(&pdev->dev, "context %s using bank %d\n", c->name, c->num);
         return 0;
 fail:
         kfree(ctx_drvdata);
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h
index 68f9b6153d7..7be32ff5d68 100644
--- a/arch/arm/mach-msm/scm-boot.h
+++ b/arch/arm/mach-msm/scm-boot.h
@@ -1,29 +1,13 @@
 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 #ifndef __MACH_SCM_BOOT_H
 #define __MACH_SCM_BOOT_H
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
index f4b9bc90d6a..cfa808dd489 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-msm/scm.c
@@ -174,15 +174,18 @@ static u32 smc(u32 cmd_addr)
         register u32 r0 asm("r0") = 1;
         register u32 r1 asm("r1") = (u32)&context_id;
         register u32 r2 asm("r2") = cmd_addr;
-        asm(
-                __asmeq("%0", "r0")
-                __asmeq("%1", "r0")
-                __asmeq("%2", "r1")
-                __asmeq("%3", "r2")
-                "smc    #0      @ switch to secure world\n"
-                : "=r" (r0)
-                : "r" (r0), "r" (r1), "r" (r2)
-                : "r3");
+        do {
+                asm volatile(
+                        __asmeq("%0", "r0")
+                        __asmeq("%1", "r0")
+                        __asmeq("%2", "r1")
+                        __asmeq("%3", "r2")
+                        "smc    #0      @ switch to secure world\n"
+                        : "=r" (r0)
+                        : "r" (r0), "r" (r1), "r" (r2)
+                        : "r3");
+        } while (r0 == SCM_INTERRUPTED);
+
         return r0;
 }
 
@@ -197,13 +200,9 @@ static int __scm_call(const struct scm_command *cmd)
          * side in the buffer.
          */
         flush_cache_all();
-        do {
-                ret = smc(cmd_addr);
-                if (ret < 0) {
-                        ret = scm_remap_error(ret);
-                        break;
-                }
-        } while (ret == SCM_INTERRUPTED);
+        ret = smc(cmd_addr);
+        if (ret < 0)
+                ret = scm_remap_error(ret);
 
         return ret;
 }
@@ -264,21 +263,28 @@ u32 scm_get_version(void)
 {
         int context_id;
         static u32 version = -1;
-        register u32 r0 asm("r0") = 0x1 << 8;
-        register u32 r1 asm("r1") = (u32)&context_id;
+        register u32 r0 asm("r0");
+        register u32 r1 asm("r1");
 
         if (version != -1)
                 return version;
 
         mutex_lock(&scm_lock);
-        asm(
-                __asmeq("%0", "r1")
-                __asmeq("%1", "r0")
-                __asmeq("%2", "r1")
-                "smc    #0      @ switch to secure world\n"
-                : "=r" (r1)
-                : "r" (r0), "r" (r1)
-                : "r2", "r3");
+
+        r0 = 0x1 << 8;
+        r1 = (u32)&context_id;
+        do {
+                asm volatile(
+                        __asmeq("%0", "r0")
+                        __asmeq("%1", "r1")
+                        __asmeq("%2", "r0")
+                        __asmeq("%3", "r1")
+                        "smc    #0      @ switch to secure world\n"
+                        : "=r" (r0), "=r" (r1)
+                        : "r" (r0), "r" (r1)
+                        : "r2", "r3");
+        } while (r0 == SCM_INTERRUPTED);
+
         version = r1;
         mutex_unlock(&scm_lock);
 
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h
index 261786be11c..00b31ea58f2 100644
--- a/arch/arm/mach-msm/scm.h
+++ b/arch/arm/mach-msm/scm.h
@@ -1,29 +1,13 @@
 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 #ifndef __MACH_SCM_H
 #define __MACH_SCM_H
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index c105d28b53e..e7f8e5a4d48 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -24,10 +24,7 @@
 
 #include <asm/mach/time.h>
 #include <mach/msm_iomap.h>
-
-#ifndef MSM_DGT_BASE
-#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
-#endif
+#include <mach/cpu.h>
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -52,18 +49,14 @@ enum timer_location {
         GLOBAL_TIMER = 1,
 };
 
-#ifdef MSM_TMR0_BASE
-#define MSM_TMR_GLOBAL          (MSM_TMR0_BASE - MSM_TMR_BASE)
-#else
-#define MSM_TMR_GLOBAL          0
-#endif
-
 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
 
+/* TODO: Remove these ifdefs */
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
+                                      defined(CONFIG_ARCH_MSM8960)
 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
 #define MSM_DGT_SHIFT (0)
 #else
@@ -177,11 +170,7 @@ static struct msm_clock msm_clocks[] = {
                         .dev_id  = &msm_clocks[0].clockevent,
                         .irq     = INT_GP_TIMER_EXP
                 },
-                .regbase = MSM_GPT_BASE,
                 .freq = GPT_HZ,
-                .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL,
-                .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL +
-                        MSM_TMR_GLOBAL,
         },
         [MSM_CLOCK_DGT] = {
                 .clockevent = {
@@ -206,12 +195,8 @@ static struct msm_clock msm_clocks[] = {
                         .dev_id  = &msm_clocks[1].clockevent,
                         .irq     = INT_DEBUG_TIMER_EXP
                 },
-                .regbase = MSM_DGT_BASE,
                 .freq = DGT_HZ >> MSM_DGT_SHIFT,
                 .shift = MSM_DGT_SHIFT,
-                .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL,
-                .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL +
-                        MSM_TMR_GLOBAL,
         }
 };
 
@@ -219,6 +204,25 @@ static void __init msm_timer_init(void)
 {
         int i;
         int res;
+        int global_offset = 0;
+
+        if (cpu_is_msm7x01()) {
+                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+        } else if (cpu_is_msm7x30()) {
+                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
+                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
+        } else if (cpu_is_qsd8x50()) {
+                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+        } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
+                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
+
+                /* Use CPU0's timer as the global timer. */
+                global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
+        } else
+                BUG();
 
 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
@@ -228,6 +232,10 @@ static void __init msm_timer_init(void)
                 struct msm_clock *clock = &msm_clocks[i];
                 struct clock_event_device *ce = &clock->clockevent;
                 struct clocksource *cs = &clock->clocksource;
+
+                clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
+                clock->global_counter = clock->local_counter + global_offset;
+
                 writel(0, clock->regbase + TIMER_ENABLE);
                 writel(0, clock->regbase + TIMER_CLEAR);
                 writel(~0, clock->regbase + TIMER_MATCH_VAL);