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-rw-r--r--arch/arm/mach-msm/devices-iommu.c911
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diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
new file mode 100644
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1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/bootmem.h>
21#include <mach/irqs.h>
22#include <mach/iommu.h>
23
24static struct resource msm_iommu_jpegd_resources[] = {
25 {
26 .start = 0x07300000,
27 .end = 0x07300000 + SZ_1M - 1,
28 .name = "physbase",
29 .flags = IORESOURCE_MEM,
30 },
31 {
32 .name = "nonsecure_irq",
33 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
34 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
35 .flags = IORESOURCE_IRQ,
36 },
37 {
38 .name = "secure_irq",
39 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
40 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
41 .flags = IORESOURCE_IRQ,
42 },
43};
44
45static struct resource msm_iommu_vpe_resources[] = {
46 {
47 .start = 0x07400000,
48 .end = 0x07400000 + SZ_1M - 1,
49 .name = "physbase",
50 .flags = IORESOURCE_MEM,
51 },
52 {
53 .name = "nonsecure_irq",
54 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
55 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
56 .flags = IORESOURCE_IRQ,
57 },
58 {
59 .name = "secure_irq",
60 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
61 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66static struct resource msm_iommu_mdp0_resources[] = {
67 {
68 .start = 0x07500000,
69 .end = 0x07500000 + SZ_1M - 1,
70 .name = "physbase",
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .name = "nonsecure_irq",
75 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
76 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
77 .flags = IORESOURCE_IRQ,
78 },
79 {
80 .name = "secure_irq",
81 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
82 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct resource msm_iommu_mdp1_resources[] = {
88 {
89 .start = 0x07600000,
90 .end = 0x07600000 + SZ_1M - 1,
91 .name = "physbase",
92 .flags = IORESOURCE_MEM,
93 },
94 {
95 .name = "nonsecure_irq",
96 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
97 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
98 .flags = IORESOURCE_IRQ,
99 },
100 {
101 .name = "secure_irq",
102 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
103 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct resource msm_iommu_rot_resources[] = {
109 {
110 .start = 0x07700000,
111 .end = 0x07700000 + SZ_1M - 1,
112 .name = "physbase",
113 .flags = IORESOURCE_MEM,
114 },
115 {
116 .name = "nonsecure_irq",
117 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
118 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
119 .flags = IORESOURCE_IRQ,
120 },
121 {
122 .name = "secure_irq",
123 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
124 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct resource msm_iommu_ijpeg_resources[] = {
130 {
131 .start = 0x07800000,
132 .end = 0x07800000 + SZ_1M - 1,
133 .name = "physbase",
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .name = "nonsecure_irq",
138 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
139 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
140 .flags = IORESOURCE_IRQ,
141 },
142 {
143 .name = "secure_irq",
144 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
145 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
146 .flags = IORESOURCE_IRQ,
147 },
148};
149
150static struct resource msm_iommu_vfe_resources[] = {
151 {
152 .start = 0x07900000,
153 .end = 0x07900000 + SZ_1M - 1,
154 .name = "physbase",
155 .flags = IORESOURCE_MEM,
156 },
157 {
158 .name = "nonsecure_irq",
159 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
160 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
161 .flags = IORESOURCE_IRQ,
162 },
163 {
164 .name = "secure_irq",
165 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
166 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
167 .flags = IORESOURCE_IRQ,
168 },
169};
170
171static struct resource msm_iommu_vcodec_a_resources[] = {
172 {
173 .start = 0x07A00000,
174 .end = 0x07A00000 + SZ_1M - 1,
175 .name = "physbase",
176 .flags = IORESOURCE_MEM,
177 },
178 {
179 .name = "nonsecure_irq",
180 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
181 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
182 .flags = IORESOURCE_IRQ,
183 },
184 {
185 .name = "secure_irq",
186 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
187 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
188 .flags = IORESOURCE_IRQ,
189 },
190};
191
192static struct resource msm_iommu_vcodec_b_resources[] = {
193 {
194 .start = 0x07B00000,
195 .end = 0x07B00000 + SZ_1M - 1,
196 .name = "physbase",
197 .flags = IORESOURCE_MEM,
198 },
199 {
200 .name = "nonsecure_irq",
201 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
202 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .name = "secure_irq",
207 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
208 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
209 .flags = IORESOURCE_IRQ,
210 },
211};
212
213static struct resource msm_iommu_gfx3d_resources[] = {
214 {
215 .start = 0x07C00000,
216 .end = 0x07C00000 + SZ_1M - 1,
217 .name = "physbase",
218 .flags = IORESOURCE_MEM,
219 },
220 {
221 .name = "nonsecure_irq",
222 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
223 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
224 .flags = IORESOURCE_IRQ,
225 },
226 {
227 .name = "secure_irq",
228 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
229 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
230 .flags = IORESOURCE_IRQ,
231 },
232};
233
234static struct resource msm_iommu_gfx2d0_resources[] = {
235 {
236 .start = 0x07D00000,
237 .end = 0x07D00000 + SZ_1M - 1,
238 .name = "physbase",
239 .flags = IORESOURCE_MEM,
240 },
241 {
242 .name = "nonsecure_irq",
243 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
244 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .name = "secure_irq",
249 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
250 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct resource msm_iommu_gfx2d1_resources[] = {
256 {
257 .start = 0x07E00000,
258 .end = 0x07E00000 + SZ_1M - 1,
259 .name = "physbase",
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .name = "nonsecure_irq",
264 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
265 .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
266 .flags = IORESOURCE_IRQ,
267 },
268 {
269 .name = "secure_irq",
270 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
271 .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device msm_root_iommu_dev = {
277 .name = "msm_iommu",
278 .id = -1,
279};
280
281static struct msm_iommu_dev jpegd_iommu = {
282 .name = "jpegd",
283 .ncb = 2,
284};
285
286static struct msm_iommu_dev vpe_iommu = {
287 .name = "vpe",
288 .ncb = 2,
289};
290
291static struct msm_iommu_dev mdp0_iommu = {
292 .name = "mdp0",
293 .ncb = 2,
294};
295
296static struct msm_iommu_dev mdp1_iommu = {
297 .name = "mdp1",
298 .ncb = 2,
299};
300
301static struct msm_iommu_dev rot_iommu = {
302 .name = "rot",
303 .ncb = 2,
304};
305
306static struct msm_iommu_dev ijpeg_iommu = {
307 .name = "ijpeg",
308 .ncb = 2,
309};
310
311static struct msm_iommu_dev vfe_iommu = {
312 .name = "vfe",
313 .ncb = 2,
314};
315
316static struct msm_iommu_dev vcodec_a_iommu = {
317 .name = "vcodec_a",
318 .ncb = 2,
319};
320
321static struct msm_iommu_dev vcodec_b_iommu = {
322 .name = "vcodec_b",
323 .ncb = 2,
324};
325
326static struct msm_iommu_dev gfx3d_iommu = {
327 .name = "gfx3d",
328 .ncb = 3,
329};
330
331static struct msm_iommu_dev gfx2d0_iommu = {
332 .name = "gfx2d0",
333 .ncb = 2,
334};
335
336static struct msm_iommu_dev gfx2d1_iommu = {
337 .name = "gfx2d1",
338 .ncb = 2,
339};
340
341static struct platform_device msm_device_iommu_jpegd = {
342 .name = "msm_iommu",
343 .id = 0,
344 .dev = {
345 .parent = &msm_root_iommu_dev.dev,
346 },
347 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
348 .resource = msm_iommu_jpegd_resources,
349};
350
351static struct platform_device msm_device_iommu_vpe = {
352 .name = "msm_iommu",
353 .id = 1,
354 .dev = {
355 .parent = &msm_root_iommu_dev.dev,
356 },
357 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
358 .resource = msm_iommu_vpe_resources,
359};
360
361static struct platform_device msm_device_iommu_mdp0 = {
362 .name = "msm_iommu",
363 .id = 2,
364 .dev = {
365 .parent = &msm_root_iommu_dev.dev,
366 },
367 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
368 .resource = msm_iommu_mdp0_resources,
369};
370
371static struct platform_device msm_device_iommu_mdp1 = {
372 .name = "msm_iommu",
373 .id = 3,
374 .dev = {
375 .parent = &msm_root_iommu_dev.dev,
376 },
377 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
378 .resource = msm_iommu_mdp1_resources,
379};
380
381static struct platform_device msm_device_iommu_rot = {
382 .name = "msm_iommu",
383 .id = 4,
384 .dev = {
385 .parent = &msm_root_iommu_dev.dev,
386 },
387 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
388 .resource = msm_iommu_rot_resources,
389};
390
391static struct platform_device msm_device_iommu_ijpeg = {
392 .name = "msm_iommu",
393 .id = 5,
394 .dev = {
395 .parent = &msm_root_iommu_dev.dev,
396 },
397 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
398 .resource = msm_iommu_ijpeg_resources,
399};
400
401static struct platform_device msm_device_iommu_vfe = {
402 .name = "msm_iommu",
403 .id = 6,
404 .dev = {
405 .parent = &msm_root_iommu_dev.dev,
406 },
407 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
408 .resource = msm_iommu_vfe_resources,
409};
410
411static struct platform_device msm_device_iommu_vcodec_a = {
412 .name = "msm_iommu",
413 .id = 7,
414 .dev = {
415 .parent = &msm_root_iommu_dev.dev,
416 },
417 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
418 .resource = msm_iommu_vcodec_a_resources,
419};
420
421static struct platform_device msm_device_iommu_vcodec_b = {
422 .name = "msm_iommu",
423 .id = 8,
424 .dev = {
425 .parent = &msm_root_iommu_dev.dev,
426 },
427 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
428 .resource = msm_iommu_vcodec_b_resources,
429};
430
431static struct platform_device msm_device_iommu_gfx3d = {
432 .name = "msm_iommu",
433 .id = 9,
434 .dev = {
435 .parent = &msm_root_iommu_dev.dev,
436 },
437 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
438 .resource = msm_iommu_gfx3d_resources,
439};
440
441static struct platform_device msm_device_iommu_gfx2d0 = {
442 .name = "msm_iommu",
443 .id = 10,
444 .dev = {
445 .parent = &msm_root_iommu_dev.dev,
446 },
447 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
448 .resource = msm_iommu_gfx2d0_resources,
449};
450
451struct platform_device msm_device_iommu_gfx2d1 = {
452 .name = "msm_iommu",
453 .id = 11,
454 .dev = {
455 .parent = &msm_root_iommu_dev.dev,
456 },
457 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
458 .resource = msm_iommu_gfx2d1_resources,
459};
460
461static struct msm_iommu_ctx_dev jpegd_src_ctx = {
462 .name = "jpegd_src",
463 .num = 0,
464 .mids = {0, -1}
465};
466
467static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
468 .name = "jpegd_dst",
469 .num = 1,
470 .mids = {1, -1}
471};
472
473static struct msm_iommu_ctx_dev vpe_src_ctx = {
474 .name = "vpe_src",
475 .num = 0,
476 .mids = {0, -1}
477};
478
479static struct msm_iommu_ctx_dev vpe_dst_ctx = {
480 .name = "vpe_dst",
481 .num = 1,
482 .mids = {1, -1}
483};
484
485static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
486 .name = "mdp_vg1",
487 .num = 0,
488 .mids = {0, 2, -1}
489};
490
491static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
492 .name = "mdp_rgb1",
493 .num = 1,
494 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
495};
496
497static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
498 .name = "mdp_vg2",
499 .num = 0,
500 .mids = {0, 2, -1}
501};
502
503static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
504 .name = "mdp_rgb2",
505 .num = 1,
506 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
507};
508
509static struct msm_iommu_ctx_dev rot_src_ctx = {
510 .name = "rot_src",
511 .num = 0,
512 .mids = {0, -1}
513};
514
515static struct msm_iommu_ctx_dev rot_dst_ctx = {
516 .name = "rot_dst",
517 .num = 1,
518 .mids = {1, -1}
519};
520
521static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
522 .name = "ijpeg_src",
523 .num = 0,
524 .mids = {0, -1}
525};
526
527static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
528 .name = "ijpeg_dst",
529 .num = 1,
530 .mids = {1, -1}
531};
532
533static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
534 .name = "vfe_imgwr",
535 .num = 0,
536 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
537};
538
539static struct msm_iommu_ctx_dev vfe_misc_ctx = {
540 .name = "vfe_misc",
541 .num = 1,
542 .mids = {0, 1, 9, -1}
543};
544
545static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
546 .name = "vcodec_a_stream",
547 .num = 0,
548 .mids = {2, 5, -1}
549};
550
551static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
552 .name = "vcodec_a_mm1",
553 .num = 1,
554 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
555};
556
557static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
558 .name = "vcodec_b_mm2",
559 .num = 0,
560 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
561};
562
563static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
564 .name = "gfx3d_user",
565 .num = 0,
566 .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
567};
568
569static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
570 .name = "gfx3d_priv",
571 .num = 1,
572 .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
573 31, -1}
574};
575
576static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
577 .name = "gfx2d0_2d0",
578 .num = 0,
579 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
580};
581
582static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
583 .name = "gfx2d1_2d1",
584 .num = 0,
585 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
586};
587
588static struct platform_device msm_device_jpegd_src_ctx = {
589 .name = "msm_iommu_ctx",
590 .id = 0,
591 .dev = {
592 .parent = &msm_device_iommu_jpegd.dev,
593 },
594};
595
596static struct platform_device msm_device_jpegd_dst_ctx = {
597 .name = "msm_iommu_ctx",
598 .id = 1,
599 .dev = {
600 .parent = &msm_device_iommu_jpegd.dev,
601 },
602};
603
604static struct platform_device msm_device_vpe_src_ctx = {
605 .name = "msm_iommu_ctx",
606 .id = 2,
607 .dev = {
608 .parent = &msm_device_iommu_vpe.dev,
609 },
610};
611
612static struct platform_device msm_device_vpe_dst_ctx = {
613 .name = "msm_iommu_ctx",
614 .id = 3,
615 .dev = {
616 .parent = &msm_device_iommu_vpe.dev,
617 },
618};
619
620static struct platform_device msm_device_mdp_vg1_ctx = {
621 .name = "msm_iommu_ctx",
622 .id = 4,
623 .dev = {
624 .parent = &msm_device_iommu_mdp0.dev,
625 },
626};
627
628static struct platform_device msm_device_mdp_rgb1_ctx = {
629 .name = "msm_iommu_ctx",
630 .id = 5,
631 .dev = {
632 .parent = &msm_device_iommu_mdp0.dev,
633 },
634};
635
636static struct platform_device msm_device_mdp_vg2_ctx = {
637 .name = "msm_iommu_ctx",
638 .id = 6,
639 .dev = {
640 .parent = &msm_device_iommu_mdp1.dev,
641 },
642};
643
644static struct platform_device msm_device_mdp_rgb2_ctx = {
645 .name = "msm_iommu_ctx",
646 .id = 7,
647 .dev = {
648 .parent = &msm_device_iommu_mdp1.dev,
649 },
650};
651
652static struct platform_device msm_device_rot_src_ctx = {
653 .name = "msm_iommu_ctx",
654 .id = 8,
655 .dev = {
656 .parent = &msm_device_iommu_rot.dev,
657 },
658};
659
660static struct platform_device msm_device_rot_dst_ctx = {
661 .name = "msm_iommu_ctx",
662 .id = 9,
663 .dev = {
664 .parent = &msm_device_iommu_rot.dev,
665 },
666};
667
668static struct platform_device msm_device_ijpeg_src_ctx = {
669 .name = "msm_iommu_ctx",
670 .id = 10,
671 .dev = {
672 .parent = &msm_device_iommu_ijpeg.dev,
673 },
674};
675
676static struct platform_device msm_device_ijpeg_dst_ctx = {
677 .name = "msm_iommu_ctx",
678 .id = 11,
679 .dev = {
680 .parent = &msm_device_iommu_ijpeg.dev,
681 },
682};
683
684static struct platform_device msm_device_vfe_imgwr_ctx = {
685 .name = "msm_iommu_ctx",
686 .id = 12,
687 .dev = {
688 .parent = &msm_device_iommu_vfe.dev,
689 },
690};
691
692static struct platform_device msm_device_vfe_misc_ctx = {
693 .name = "msm_iommu_ctx",
694 .id = 13,
695 .dev = {
696 .parent = &msm_device_iommu_vfe.dev,
697 },
698};
699
700static struct platform_device msm_device_vcodec_a_stream_ctx = {
701 .name = "msm_iommu_ctx",
702 .id = 14,
703 .dev = {
704 .parent = &msm_device_iommu_vcodec_a.dev,
705 },
706};
707
708static struct platform_device msm_device_vcodec_a_mm1_ctx = {
709 .name = "msm_iommu_ctx",
710 .id = 15,
711 .dev = {
712 .parent = &msm_device_iommu_vcodec_a.dev,
713 },
714};
715
716static struct platform_device msm_device_vcodec_b_mm2_ctx = {
717 .name = "msm_iommu_ctx",
718 .id = 16,
719 .dev = {
720 .parent = &msm_device_iommu_vcodec_b.dev,
721 },
722};
723
724static struct platform_device msm_device_gfx3d_user_ctx = {
725 .name = "msm_iommu_ctx",
726 .id = 17,
727 .dev = {
728 .parent = &msm_device_iommu_gfx3d.dev,
729 },
730};
731
732static struct platform_device msm_device_gfx3d_priv_ctx = {
733 .name = "msm_iommu_ctx",
734 .id = 18,
735 .dev = {
736 .parent = &msm_device_iommu_gfx3d.dev,
737 },
738};
739
740static struct platform_device msm_device_gfx2d0_2d0_ctx = {
741 .name = "msm_iommu_ctx",
742 .id = 19,
743 .dev = {
744 .parent = &msm_device_iommu_gfx2d0.dev,
745 },
746};
747
748static struct platform_device msm_device_gfx2d1_2d1_ctx = {
749 .name = "msm_iommu_ctx",
750 .id = 20,
751 .dev = {
752 .parent = &msm_device_iommu_gfx2d1.dev,
753 },
754};
755
756static struct platform_device *msm_iommu_devs[] = {
757 &msm_device_iommu_jpegd,
758 &msm_device_iommu_vpe,
759 &msm_device_iommu_mdp0,
760 &msm_device_iommu_mdp1,
761 &msm_device_iommu_rot,
762 &msm_device_iommu_ijpeg,
763 &msm_device_iommu_vfe,
764 &msm_device_iommu_vcodec_a,
765 &msm_device_iommu_vcodec_b,
766 &msm_device_iommu_gfx3d,
767 &msm_device_iommu_gfx2d0,
768 &msm_device_iommu_gfx2d1,
769};
770
771static struct msm_iommu_dev *msm_iommu_data[] = {
772 &jpegd_iommu,
773 &vpe_iommu,
774 &mdp0_iommu,
775 &mdp1_iommu,
776 &rot_iommu,
777 &ijpeg_iommu,
778 &vfe_iommu,
779 &vcodec_a_iommu,
780 &vcodec_b_iommu,
781 &gfx3d_iommu,
782 &gfx2d0_iommu,
783 &gfx2d1_iommu,
784};
785
786static struct platform_device *msm_iommu_ctx_devs[] = {
787 &msm_device_jpegd_src_ctx,
788 &msm_device_jpegd_dst_ctx,
789 &msm_device_vpe_src_ctx,
790 &msm_device_vpe_dst_ctx,
791 &msm_device_mdp_vg1_ctx,
792 &msm_device_mdp_rgb1_ctx,
793 &msm_device_mdp_vg2_ctx,
794 &msm_device_mdp_rgb2_ctx,
795 &msm_device_rot_src_ctx,
796 &msm_device_rot_dst_ctx,
797 &msm_device_ijpeg_src_ctx,
798 &msm_device_ijpeg_dst_ctx,
799 &msm_device_vfe_imgwr_ctx,
800 &msm_device_vfe_misc_ctx,
801 &msm_device_vcodec_a_stream_ctx,
802 &msm_device_vcodec_a_mm1_ctx,
803 &msm_device_vcodec_b_mm2_ctx,
804 &msm_device_gfx3d_user_ctx,
805 &msm_device_gfx3d_priv_ctx,
806 &msm_device_gfx2d0_2d0_ctx,
807 &msm_device_gfx2d1_2d1_ctx,
808};
809
810static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
811 &jpegd_src_ctx,
812 &jpegd_dst_ctx,
813 &vpe_src_ctx,
814 &vpe_dst_ctx,
815 &mdp_vg1_ctx,
816 &mdp_rgb1_ctx,
817 &mdp_vg2_ctx,
818 &mdp_rgb2_ctx,
819 &rot_src_ctx,
820 &rot_dst_ctx,
821 &ijpeg_src_ctx,
822 &ijpeg_dst_ctx,
823 &vfe_imgwr_ctx,
824 &vfe_misc_ctx,
825 &vcodec_a_stream_ctx,
826 &vcodec_a_mm1_ctx,
827 &vcodec_b_mm2_ctx,
828 &gfx3d_user_ctx,
829 &gfx3d_priv_ctx,
830 &gfx2d0_2d0_ctx,
831 &gfx2d1_2d1_ctx,
832};
833
834static int __init msm8x60_iommu_init(void)
835{
836 int ret, i;
837
838 ret = platform_device_register(&msm_root_iommu_dev);
839 if (ret != 0) {
840 pr_err("Failed to register root IOMMU device!\n");
841 goto failure;
842 }
843
844 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
845 ret = platform_device_add_data(msm_iommu_devs[i],
846 msm_iommu_data[i],
847 sizeof(struct msm_iommu_dev));
848 if (ret != 0) {
849 pr_err("platform_device_add_data failed, "
850 "i = %d\n", i);
851 goto failure_unwind;
852 }
853
854 ret = platform_device_register(msm_iommu_devs[i]);
855
856 if (ret != 0) {
857 pr_err("platform_device_register iommu failed, "
858 "i = %d\n", i);
859 goto failure_unwind;
860 }
861 }
862
863 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
864 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
865 msm_iommu_ctx_data[i],
866 sizeof(*msm_iommu_ctx_devs[i]));
867 if (ret != 0) {
868 pr_err("platform_device_add_data iommu failed, "
869 "i = %d\n", i);
870 goto failure_unwind2;
871 }
872
873 ret = platform_device_register(msm_iommu_ctx_devs[i]);
874 if (ret != 0) {
875 pr_err("platform_device_register ctx failed, "
876 "i = %d\n", i);
877 goto failure_unwind2;
878 }
879 }
880 return 0;
881
882failure_unwind2:
883 while (--i >= 0)
884 platform_device_unregister(msm_iommu_ctx_devs[i]);
885failure_unwind:
886 while (--i >= 0)
887 platform_device_unregister(msm_iommu_devs[i]);
888
889 platform_device_unregister(&msm_root_iommu_dev);
890failure:
891 return ret;
892}
893
894static void __exit msm8x60_iommu_exit(void)
895{
896 int i;
897
898 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
899 platform_device_unregister(msm_iommu_ctx_devs[i]);
900
901 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
902 platform_device_unregister(msm_iommu_devs[i]);
903
904 platform_device_unregister(&msm_root_iommu_dev);
905}
906
907subsys_initcall(msm8x60_iommu_init);
908module_exit(msm8x60_iommu_exit);
909
910MODULE_LICENSE("GPL v2");
911MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 03:33:11 -0400