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-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c231
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c210
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c177
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c279
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c295
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c11
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c176
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c223
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c16
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c21
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c81
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c157
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c74
24 files changed, 1394 insertions, 757 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 2c16df37eda..71291ae201b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25 26
26/* SH7343 registers */ 27/* SH7343 registers */
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -91,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
91}; 86};
92 87
93static struct clk pll_clk = { 88static struct clk pll_clk = {
94 .name = "pll_clk",
95 .id = -1,
96 .ops = &pll_clk_ops, 89 .ops = &pll_clk_ops,
97 .flags = CLK_ENABLE_ON_INIT, 90 .flags = CLK_ENABLE_ON_INIT,
98}; 91};
@@ -121,72 +114,168 @@ static struct clk_div4_table div4_table = {
121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 114enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
122 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 115 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
123 116
124#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
126 119
127struct clk div4_clks[DIV4_NR] = { 120struct clk div4_clks[DIV4_NR] = {
128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
136}; 129};
137 130
138struct clk div6_clks[] = { 131enum { DIV6_V, DIV6_NR };
139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 132
133struct clk div6_clks[DIV6_NR] = {
134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
135};
136
137#define MSTP(_parent, _reg, _bit, _flags) \
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
139
140enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
141 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
142 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
143 MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
144 MSTP109, MSTP108, MSTP100,
145 MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
146 MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
147 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
148 MSTP_NR };
149
150static struct clk mstp_clks[MSTP_NR] = {
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
160 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
161 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
162 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
163 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
164 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
165 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
166 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
167 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
168 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
169 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
170 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
171 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
172 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
173 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
174
175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
177
178 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
179 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
180 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
181 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
182 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
183 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
184 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
185 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
186 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
187 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
188 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
189 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
190 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
191 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
192 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
193 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
194 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
140}; 195};
141 196
142#define MSTP(_str, _parent, _reg, _bit, _flags) \ 197#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
143 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 198
144 199static struct clk_lookup lookups[] = {
145static struct clk mstp_clks[] = { 200 /* main clocks */
146 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 201 CLKDEV_CON_ID("rclk", &r_clk),
147 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 202 CLKDEV_CON_ID("extal", &extal_clk),
148 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 203 CLKDEV_CON_ID("dll_clk", &dll_clk),
149 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 204 CLKDEV_CON_ID("pll_clk", &pll_clk),
150 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 205
151 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 206 /* DIV4 clocks */
152 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
153 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 208 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 209 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 210 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 211 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 212 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 213 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 214 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 215
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 216 /* DIV6 clocks */
162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 217 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 218
164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 219 /* MSTP32 clocks */
165 MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), 220 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
166 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 221 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
167 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 222 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
168 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 223 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
169 224 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
170 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 225 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
171 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), 226 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
172 227 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
173 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), 228 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
174 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 229 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
175 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 230 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
176 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 231 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
177 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), 232 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
178 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 233 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
179 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), 234 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
180 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), 235 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
181 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 236 {
182 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 237 /* SCIF0 */
183 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 238 .dev_id = "sh-sci.0",
184 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 239 .con_id = "sci_fck",
185 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 240 .clk = &mstp_clks[MSTP007],
186 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 241 }, {
187 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 242 /* SCIF1 */
188 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 243 .dev_id = "sh-sci.1",
189 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 244 .con_id = "sci_fck",
245 .clk = &mstp_clks[MSTP006],
246 }, {
247 /* SCIF2 */
248 .dev_id = "sh-sci.2",
249 .con_id = "sci_fck",
250 .clk = &mstp_clks[MSTP005],
251 }, {
252 /* SCIF3 */
253 .dev_id = "sh-sci.3",
254 .con_id = "sci_fck",
255 .clk = &mstp_clks[MSTP004],
256 },
257 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
258 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
259 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
260 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
261 CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
262 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
263 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
264 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
265 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
266 CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
267 CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
268 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
269 CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
270 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
271 CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
272 CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
273 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
274 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
275 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
276 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
277 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
278 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
190}; 279};
191 280
192int __init arch_clk_init(void) 281int __init arch_clk_init(void)
@@ -202,14 +291,16 @@ int __init arch_clk_init(void)
202 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 291 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
203 ret = clk_register(main_clks[k]); 292 ret = clk_register(main_clks[k]);
204 293
294 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
295
205 if (!ret) 296 if (!ret)
206 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 297 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
207 298
208 if (!ret) 299 if (!ret)
209 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 300 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
210 301
211 if (!ret) 302 if (!ret)
212 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 303 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
213 304
214 return ret; 305 return ret;
215} 306}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 91588d280cd..7ce5bbcd408 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25 26
26/* SH7366 registers */ 27/* SH7366 registers */
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
94}; 89};
95 90
96static struct clk pll_clk = { 91static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
101}; 94};
@@ -124,69 +117,154 @@ static struct clk_div4_table div4_table = {
124enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
125 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 118 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
126 119
127#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
128 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
129 122
130struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
131 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
132 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
135 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
136 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
137 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
138 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
139}; 132};
140 133
141struct clk div6_clks[] = { 134enum { DIV6_V, DIV6_NR };
142 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 135
136struct clk div6_clks[DIV6_NR] = {
137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
143}; 138};
144 139
145#define MSTP(_str, _parent, _reg, _bit, _flags) \ 140#define MSTP(_parent, _reg, _bit, _flags) \
146 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
142
143enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
144 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
145 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
146 MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
147 MSTP109, MSTP100,
148 MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
149 MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
150 MSTP_NR };
147 151
148static struct clk mstp_clks[] = { 152static struct clk mstp_clks[MSTP_NR] = {
149 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 153 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
150 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
151 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
152 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
153 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
154 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
155 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
156 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
157 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
158 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
159 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 163 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
160 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 164 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
161 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 165 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
162 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 166 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
163 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 167 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
164 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 168 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
165 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 169 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
166 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 170 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
167 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 171 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
168 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 172 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
169 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 173 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
170 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 174 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
171 175
172 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
173 177
174 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), 178 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
175 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), 179 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
176 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 180 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
177 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), 181 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
178 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), 182 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
179 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 183 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
180 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 184 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
181 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 185 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
182 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
183 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 187 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
184 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 188 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
185 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 189 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
186 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
187 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
188 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
189 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 193};
194
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
196
197static struct clk_lookup lookups[] = {
198 /* main clocks */
199 CLKDEV_CON_ID("rclk", &r_clk),
200 CLKDEV_CON_ID("extal", &extal_clk),
201 CLKDEV_CON_ID("dll_clk", &dll_clk),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
203
204 /* DIV4 clocks */
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
209 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
210 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
211 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
212 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
213
214 /* DIV6 clocks */
215 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
216
217 /* MSTP32 clocks */
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
227 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
228 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
229 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
230 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
231 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
232 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
233 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
234 {
235 /* SCIF0 */
236 .dev_id = "sh-sci.0",
237 .con_id = "sci_fck",
238 .clk = &mstp_clks[MSTP007],
239 }, {
240 /* SCIF1 */
241 .dev_id = "sh-sci.1",
242 .con_id = "sci_fck",
243 .clk = &mstp_clks[MSTP006],
244 }, {
245 /* SCIF2 */
246 .dev_id = "sh-sci.2",
247 .con_id = "sci_fck",
248 .clk = &mstp_clks[MSTP005],
249 },
250 CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
251 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
252 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
253 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
254 CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
255 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
256 CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
257 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
258 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
259 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
260 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
261 CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
262 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
263 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
264 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
265 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
266 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
267 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
190}; 268};
191 269
192int __init arch_clk_init(void) 270int __init arch_clk_init(void)
@@ -202,14 +280,16 @@ int __init arch_clk_init(void)
202 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 280 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
203 ret = clk_register(main_clks[k]); 281 ret = clk_register(main_clks[k]);
204 282
283 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
284
205 if (!ret) 285 if (!ret)
206 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 286 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
207 287
208 if (!ret) 288 if (!ret)
209 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 289 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
210 290
211 if (!ret) 291 if (!ret)
212 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 292 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
213 293
214 return ret; 294 return ret;
215} 295}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 15db6d521c5..2030f3d9fac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25#include <asm/hwblk.h> 26#include <asm/hwblk.h>
26#include <cpu/sh7722.h> 27#include <cpu/sh7722.h>
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
94}; 89};
95 90
96static struct clk pll_clk = { 91static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
101}; 94};
@@ -121,68 +114,142 @@ static struct clk_div4_table div4_table = {
121 .div_mult_table = &div4_div_mult_table, 114 .div_mult_table = &div4_div_mult_table,
122}; 115};
123 116
124#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
126 119
127enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
128 121
129struct clk div4_clks[DIV4_NR] = { 122struct clk div4_clks[DIV4_NR] = {
130 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
131 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
135 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 128 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
136}; 129};
137 130
138enum { DIV4_IRDA, DIV4_ENABLE_NR }; 131enum { DIV4_IRDA, DIV4_ENABLE_NR };
139 132
140struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 133struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
141 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), 134 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
142}; 135};
143 136
144enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 137enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
145 138
146struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 139struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
147 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 140 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
148 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 141 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
149}; 142};
150 143
151struct clk div6_clks[] = { 144enum { DIV6_V, DIV6_NR };
152 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 145
146struct clk div6_clks[DIV6_NR] = {
147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
148};
149
150static struct clk mstp_clks[HWBLK_NR] = {
151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
154 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
155 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
160
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
162 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
163
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
165 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
174 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
153}; 176};
154 177
155#define R_CLK &r_clk 178#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
156#define P_CLK &div4_clks[DIV4_P] 179
157#define B_CLK &div4_clks[DIV4_B] 180static struct clk_lookup lookups[] = {
158#define U_CLK &div4_clks[DIV4_U] 181 /* main clocks */
159 182 CLKDEV_CON_ID("rclk", &r_clk),
160static struct clk mstp_clks[] = { 183 CLKDEV_CON_ID("extal", &extal_clk),
161 SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT), 184 CLKDEV_CON_ID("dll_clk", &dll_clk),
162 SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT), 185 CLKDEV_CON_ID("pll_clk", &pll_clk),
163 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0), 186
164 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 187 /* DIV4 clocks */
165 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
166 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), 189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
167 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
168 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
169 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 192 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
170 193 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
171 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), 194 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
172 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 195 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
173 196 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
174 SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0), 197
175 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 198 /* DIV6 clocks */
176 SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0), 199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
177 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 200
178 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), 201 /* MSTP clocks */
179 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 202 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
180 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), 203 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
181 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), 204 {
182 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), 205 /* TMU0 */
183 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0), 206 .dev_id = "sh_tmu.0",
184 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 207 .con_id = "tmu_fck",
185 SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0), 208 .clk = &mstp_clks[HWBLK_TMU],
209 }, {
210 /* TMU1 */
211 .dev_id = "sh_tmu.1",
212 .con_id = "tmu_fck",
213 .clk = &mstp_clks[HWBLK_TMU],
214 }, {
215 /* TMU2 */
216 .dev_id = "sh_tmu.2",
217 .con_id = "tmu_fck",
218 .clk = &mstp_clks[HWBLK_TMU],
219 },
220 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
221 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
222 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
223 {
224 /* SCIF0 */
225 .dev_id = "sh-sci.0",
226 .con_id = "sci_fck",
227 .clk = &mstp_clks[HWBLK_SCIF0],
228 }, {
229 /* SCIF1 */
230 .dev_id = "sh-sci.1",
231 .con_id = "sci_fck",
232 .clk = &mstp_clks[HWBLK_SCIF1],
233 }, {
234 /* SCIF2 */
235 .dev_id = "sh-sci.2",
236 .con_id = "sci_fck",
237 .clk = &mstp_clks[HWBLK_SCIF2],
238 },
239 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
240 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
241 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
242 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
243 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
244 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
245 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
246 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
247 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
248 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
249 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
250 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
251 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
252 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
186}; 253};
187 254
188int __init arch_clk_init(void) 255int __init arch_clk_init(void)
@@ -198,6 +265,8 @@ int __init arch_clk_init(void)
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 265 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]); 266 ret = clk_register(main_clks[k]);
200 267
268 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
269
201 if (!ret) 270 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 271 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203 272
@@ -210,10 +279,10 @@ int __init arch_clk_init(void)
210 DIV4_REPARENT_NR, &div4_table); 279 DIV4_REPARENT_NR, &div4_table);
211 280
212 if (!ret) 281 if (!ret)
213 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 282 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
214 283
215 if (!ret) 284 if (!ret)
216 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 285 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
217 286
218 return ret; 287 return ret;
219} 288}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 50babe01fe4..d3938f0d370 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <asm/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
25#include <asm/hwblk.h> 27#include <asm/hwblk.h>
26#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
@@ -36,8 +38,6 @@
36 38
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 39/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 40static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 41 .rate = 32768,
42}; 42};
43 43
@@ -46,8 +46,6 @@ static struct clk r_clk = {
46 * from the platform code. 46 * from the platform code.
47 */ 47 */
48struct clk extal_clk = { 48struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 49 .rate = 33333333,
52}; 50};
53 51
@@ -69,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
69}; 67};
70 68
71static struct clk dll_clk = { 69static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 70 .ops = &dll_clk_ops,
75 .parent = &r_clk, 71 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 72 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
94}; 90};
95 91
96static struct clk pll_clk = { 92static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 93 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 94 .flags = CLK_ENABLE_ON_INIT,
101}; 95};
@@ -123,92 +117,215 @@ static struct clk_div4_table div4_table = {
123 117
124enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 118enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
125 119
126#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
127 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 122
129struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
130 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
132 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
133 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
134 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
135 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
136}; 130};
137 131
138enum { DIV4_IRDA, DIV4_ENABLE_NR }; 132enum { DIV4_IRDA, DIV4_ENABLE_NR };
139 133
140struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 134struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
141 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), 135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
142}; 136};
143 137
144enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 138enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
145 139
146struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 140struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
147 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), 141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
148 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), 142 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
149};
150struct clk div6_clks[] = {
151 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
152}; 143};
144enum { DIV6_V, DIV6_NR };
153 145
154#define R_CLK (&r_clk) 146struct clk div6_clks[DIV6_NR] = {
155#define P_CLK (&div4_clks[DIV4_P]) 147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
156#define B_CLK (&div4_clks[DIV4_B]) 148};
157#define U_CLK (&div4_clks[DIV4_U])
158#define I_CLK (&div4_clks[DIV4_I])
159#define SH_CLK (&div4_clks[DIV4_SH])
160 149
161static struct clk mstp_clks[] = { 150static struct clk mstp_clks[] = {
162 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
163 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), 152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
164 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), 153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
165 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), 154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
166 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), 155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
167 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), 156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
168 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), 157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), 158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), 159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
171 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
173 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
174 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
175 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
176 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
177 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
178 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
179 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), 168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
180 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
181 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
182 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
183 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
184 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
185 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
186 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
187 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
188 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0), 177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
189 178
190 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), 179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
191 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
192 181
193 SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0), 182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
194 SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0), 183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
195 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), 184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
196 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), 185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
197 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), 186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
198 SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT), 187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
199 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), 188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
200 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), 189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
201 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
202 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0), 191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
203 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
204 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), 193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
205 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0), 194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
206 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
207 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), 196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
208 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), 197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
209 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0), 198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
210 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
211 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
201};
202
203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204
205static struct clk_lookup lookups[] = {
206 /* main clocks */
207 CLKDEV_CON_ID("rclk", &r_clk),
208 CLKDEV_CON_ID("extal", &extal_clk),
209 CLKDEV_CON_ID("dll_clk", &dll_clk),
210 CLKDEV_CON_ID("pll_clk", &pll_clk),
211
212 /* DIV4 clocks */
213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
217 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
218 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
219 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
220 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
221 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
222
223 /* DIV6 clocks */
224 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
225
226 /* MSTP clocks */
227 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
228 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
229 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
230 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
231 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
232 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
233 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
234 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
235 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
236 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
237 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
238 {
239 /* TMU0 */
240 .dev_id = "sh_tmu.0",
241 .con_id = "tmu_fck",
242 .clk = &mstp_clks[HWBLK_TMU0],
243 }, {
244 /* TMU1 */
245 .dev_id = "sh_tmu.1",
246 .con_id = "tmu_fck",
247 .clk = &mstp_clks[HWBLK_TMU0],
248 }, {
249 /* TMU2 */
250 .dev_id = "sh_tmu.2",
251 .con_id = "tmu_fck",
252 .clk = &mstp_clks[HWBLK_TMU0],
253 },
254 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
255 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
256 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
257 {
258 /* TMU3 */
259 .dev_id = "sh_tmu.3",
260 .con_id = "tmu_fck",
261 .clk = &mstp_clks[HWBLK_TMU1],
262 }, {
263 /* TMU4 */
264 .dev_id = "sh_tmu.4",
265 .con_id = "tmu_fck",
266 .clk = &mstp_clks[HWBLK_TMU1],
267 }, {
268 /* TMU5 */
269 .dev_id = "sh_tmu.5",
270 .con_id = "tmu_fck",
271 .clk = &mstp_clks[HWBLK_TMU1],
272 },
273 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
274 {
275 /* SCIF0 */
276 .dev_id = "sh-sci.0",
277 .con_id = "sci_fck",
278 .clk = &mstp_clks[HWBLK_SCIF0],
279 }, {
280 /* SCIF1 */
281 .dev_id = "sh-sci.1",
282 .con_id = "sci_fck",
283 .clk = &mstp_clks[HWBLK_SCIF1],
284 }, {
285 /* SCIF2 */
286 .dev_id = "sh-sci.2",
287 .con_id = "sci_fck",
288 .clk = &mstp_clks[HWBLK_SCIF2],
289 }, {
290 /* SCIF3 */
291 .dev_id = "sh-sci.3",
292 .con_id = "sci_fck",
293 .clk = &mstp_clks[HWBLK_SCIF3],
294 }, {
295 /* SCIF4 */
296 .dev_id = "sh-sci.4",
297 .con_id = "sci_fck",
298 .clk = &mstp_clks[HWBLK_SCIF4],
299 }, {
300 /* SCIF5 */
301 .dev_id = "sh-sci.5",
302 .con_id = "sci_fck",
303 .clk = &mstp_clks[HWBLK_SCIF5],
304 },
305 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
306 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
307 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
308 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
309 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
310 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
311 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
312 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
313 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
314 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
315 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
316 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
317 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
318 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
319 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
320 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
321 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
322 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
323 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
324 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
325 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
326 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
327 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
328 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
212}; 329};
213 330
214int __init arch_clk_init(void) 331int __init arch_clk_init(void)
@@ -222,7 +339,9 @@ int __init arch_clk_init(void)
222 pll_clk.parent = &extal_clk; 339 pll_clk.parent = &extal_clk;
223 340
224 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 341 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
225 ret = clk_register(main_clks[k]); 342 ret |= clk_register(main_clks[k]);
343
344 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
226 345
227 if (!ret) 346 if (!ret)
228 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 347 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
@@ -236,10 +355,10 @@ int __init arch_clk_init(void)
236 DIV4_REPARENT_NR, &div4_table); 355 DIV4_REPARENT_NR, &div4_table);
237 356
238 if (!ret) 357 if (!ret)
239 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 358 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
240 359
241 if (!ret) 360 if (!ret)
242 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 361 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
243 362
244 return ret; 363 return ret;
245} 364}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 6707061fbf5..2d9700c6b53 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <asm/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
25#include <asm/hwblk.h> 27#include <asm/hwblk.h>
26#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
@@ -39,8 +41,6 @@
39 41
40/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
41static struct clk r_clk = { 43static struct clk r_clk = {
42 .name = "rclk",
43 .id = -1,
44 .rate = 32768, 44 .rate = 32768,
45}; 45};
46 46
@@ -49,8 +49,6 @@ static struct clk r_clk = {
49 * from the platform code. 49 * from the platform code.
50 */ 50 */
51struct clk extal_clk = { 51struct clk extal_clk = {
52 .name = "extal",
53 .id = -1,
54 .rate = 33333333, 52 .rate = 33333333,
55}; 53};
56 54
@@ -74,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
74}; 72};
75 73
76static struct clk fll_clk = { 74static struct clk fll_clk = {
77 .name = "fll_clk",
78 .id = -1,
79 .ops = &fll_clk_ops, 75 .ops = &fll_clk_ops,
80 .parent = &r_clk, 76 .parent = &r_clk,
81 .flags = CLK_ENABLE_ON_INIT, 77 .flags = CLK_ENABLE_ON_INIT,
@@ -96,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
96}; 92};
97 93
98static struct clk pll_clk = { 94static struct clk pll_clk = {
99 .name = "pll_clk",
100 .id = -1,
101 .ops = &pll_clk_ops, 95 .ops = &pll_clk_ops,
102 .flags = CLK_ENABLE_ON_INIT, 96 .flags = CLK_ENABLE_ON_INIT,
103}; 97};
@@ -113,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
113}; 107};
114 108
115static struct clk div3_clk = { 109static struct clk div3_clk = {
116 .name = "div3_clk",
117 .id = -1,
118 .ops = &div3_clk_ops, 110 .ops = &div3_clk_ops,
119 .parent = &pll_clk, 111 .parent = &pll_clk,
120}; 112};
@@ -151,86 +143,215 @@ static struct clk_div4_table div4_table = {
151 143
152enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 144enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
153 145
154#define DIV4(_str, _reg, _bit, _mask, _flags) \ 146#define DIV4(_reg, _bit, _mask, _flags) \
155 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 147 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
156 148
157struct clk div4_clks[DIV4_NR] = { 149struct clk div4_clks[DIV4_NR] = {
158 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 150 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
159 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 151 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
160 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 152 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
161 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 153 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
162 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
163}; 155};
164 156
165struct clk div6_clks[] = { 157enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
166 SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0), 158
167 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), 159struct clk div6_clks[DIV6_NR] = {
168 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), 160 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
169 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), 161 [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
170 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 162 [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
163 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
164 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
165};
166
167static struct clk mstp_clks[HWBLK_NR] = {
168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
171 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
173 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
174 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
175 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
176 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
177 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
178 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
179 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
180 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
181 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
182 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
183 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
184 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
185 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
186 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
187 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
188 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
189 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
190 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
191 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
192 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
193
194 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
195 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
196 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
197 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
198
199 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
200 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
201 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
202 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
203 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
204 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
205 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
206 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
207 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
208 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
209 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
210 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
211 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
212 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
213 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
214 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
215 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
216 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
217 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
218 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
219 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
220 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
221 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
171}; 222};
172 223
173#define R_CLK (&r_clk) 224#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
174#define P_CLK (&div4_clks[DIV4_P]) 225
175#define B_CLK (&div4_clks[DIV4_B]) 226static struct clk_lookup lookups[] = {
176#define I_CLK (&div4_clks[DIV4_I]) 227 /* main clocks */
177#define SH_CLK (&div4_clks[DIV4_SH]) 228 CLKDEV_CON_ID("rclk", &r_clk),
178 229 CLKDEV_CON_ID("extal", &extal_clk),
179static struct clk mstp_clks[] = { 230 CLKDEV_CON_ID("fll_clk", &fll_clk),
180 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), 231 CLKDEV_CON_ID("pll_clk", &pll_clk),
181 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), 232 CLKDEV_CON_ID("div3_clk", &div3_clk),
182 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), 233
183 SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT), 234 /* DIV4 clocks */
184 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), 235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
185 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), 236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
186 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), 237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
187 SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), 238 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
188 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), 239 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
189 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 240
190 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 241 /* DIV6 clocks */
191 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 242 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
192 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 243 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
193 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 244 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
194 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 245 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
195 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 246 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
196 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 247
197 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 248 /* MSTP clocks */
198 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 249 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
199 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 250 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
200 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 251 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
201 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 252 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
202 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 253 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
203 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 254 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
204 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 255 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
205 256 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
206 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 257 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
207 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 258 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
208 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0), 259 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
209 SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0), 260 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
210 261 {
211 SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0), 262 /* TMU0 */
212 SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0), 263 .dev_id = "sh_tmu.0",
213 SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0), 264 .con_id = "tmu_fck",
214 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), 265 .clk = &mstp_clks[HWBLK_TMU0],
215 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), 266 }, {
216 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), 267 /* TMU1 */
217 SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0), 268 .dev_id = "sh_tmu.1",
218 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0), 269 .con_id = "tmu_fck",
219 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 270 .clk = &mstp_clks[HWBLK_TMU0],
220 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), 271 }, {
221 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), 272 /* TMU2 */
222 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0), 273 .dev_id = "sh_tmu.2",
223 SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0), 274 .con_id = "tmu_fck",
224 SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0), 275 .clk = &mstp_clks[HWBLK_TMU0],
225 SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0), 276 }, {
226 SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0), 277 /* TMU3 */
227 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), 278 .dev_id = "sh_tmu.3",
228 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 279 .con_id = "tmu_fck",
229 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0), 280 .clk = &mstp_clks[HWBLK_TMU1],
230 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0), 281 },
231 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0), 282 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
232 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 283 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
233 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 284 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
285 {
286 /* TMU4 */
287 .dev_id = "sh_tmu.4",
288 .con_id = "tmu_fck",
289 .clk = &mstp_clks[HWBLK_TMU1],
290 }, {
291 /* TMU5 */
292 .dev_id = "sh_tmu.5",
293 .con_id = "tmu_fck",
294 .clk = &mstp_clks[HWBLK_TMU1],
295 }, {
296 /* SCIF0 */
297 .dev_id = "sh-sci.0",
298 .con_id = "sci_fck",
299 .clk = &mstp_clks[HWBLK_SCIF0],
300 }, {
301 /* SCIF1 */
302 .dev_id = "sh-sci.1",
303 .con_id = "sci_fck",
304 .clk = &mstp_clks[HWBLK_SCIF1],
305 }, {
306 /* SCIF2 */
307 .dev_id = "sh-sci.2",
308 .con_id = "sci_fck",
309 .clk = &mstp_clks[HWBLK_SCIF2],
310 }, {
311 /* SCIF3 */
312 .dev_id = "sh-sci.3",
313 .con_id = "sci_fck",
314 .clk = &mstp_clks[HWBLK_SCIF3],
315 }, {
316 /* SCIF4 */
317 .dev_id = "sh-sci.4",
318 .con_id = "sci_fck",
319 .clk = &mstp_clks[HWBLK_SCIF4],
320 }, {
321 /* SCIF5 */
322 .dev_id = "sh-sci.5",
323 .con_id = "sci_fck",
324 .clk = &mstp_clks[HWBLK_SCIF5],
325 },
326 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
327 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
328 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
329 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
330 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
331 CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
332 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
333 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
334 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
335 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
336 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
337 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
338 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
339 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
340 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
341 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
342 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
343 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
344 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
345 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
346 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
347 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
348 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
349 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
350 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
351 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
352 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
353 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
354 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
234}; 355};
235 356
236int __init arch_clk_init(void) 357int __init arch_clk_init(void)
@@ -246,14 +367,16 @@ int __init arch_clk_init(void)
246 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 367 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
247 ret = clk_register(main_clks[k]); 368 ret = clk_register(main_clks[k]);
248 369
370 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
371
249 if (!ret) 372 if (!ret)
250 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 373 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
251 374
252 if (!ret) 375 if (!ret)
253 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 376 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
254 377
255 if (!ret) 378 if (!ret)
256 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 379 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
257 380
258 return ret; 381 return ret;
259} 382}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 86aae60677d..0a752bd324a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/clkdev.h>
15#include <asm/clock.h> 16#include <asm/clock.h>
16#include <asm/freq.h> 17#include <asm/freq.h>
17 18
@@ -87,7 +88,6 @@ static struct clk_ops sh7757_shyway_clk_ops = {
87}; 88};
88 89
89static struct clk sh7757_shyway_clk = { 90static struct clk sh7757_shyway_clk = {
90 .name = "shyway_clk",
91 .flags = CLK_ENABLE_ON_INIT, 91 .flags = CLK_ENABLE_ON_INIT,
92 .ops = &sh7757_shyway_clk_ops, 92 .ops = &sh7757_shyway_clk_ops,
93}; 93};
@@ -100,6 +100,13 @@ static struct clk *sh7757_onchip_clocks[] = {
100 &sh7757_shyway_clk, 100 &sh7757_shyway_clk,
101}; 101};
102 102
103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
104
105static struct clk_lookup lookups[] = {
106 /* main clocks */
107 CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
108};
109
103static int __init sh7757_clk_init(void) 110static int __init sh7757_clk_init(void)
104{ 111{
105 struct clk *clk = clk_get(NULL, "master_clk"); 112 struct clk *clk = clk_get(NULL, "master_clk");
@@ -123,6 +130,8 @@ static int __init sh7757_clk_init(void)
123 130
124 clk_put(clk); 131 clk_put(clk);
125 132
133 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
134
126 return 0; 135 return 0;
127} 136}
128 137
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 9f401163e71..1f1df48008c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -12,6 +12,8 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <asm/clkdev.h>
15#include <asm/clock.h> 17#include <asm/clock.h>
16#include <asm/freq.h> 18#include <asm/freq.h>
17#include <asm/io.h> 19#include <asm/io.h>
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
77}; 79};
78 80
79static struct clk sh7763_shyway_clk = { 81static struct clk sh7763_shyway_clk = {
80 .name = "shyway_clk",
81 .flags = CLK_ENABLE_ON_INIT, 82 .flags = CLK_ENABLE_ON_INIT,
82 .ops = &sh7763_shyway_clk_ops, 83 .ops = &sh7763_shyway_clk_ops,
83}; 84};
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
90 &sh7763_shyway_clk, 91 &sh7763_shyway_clk,
91}; 92};
92 93
94#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
95
96static struct clk_lookup lookups[] = {
97 /* main clocks */
98 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
99};
100
93int __init arch_clk_init(void) 101int __init arch_clk_init(void)
94{ 102{
95 struct clk *clk; 103 struct clk *clk;
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
107 115
108 clk_put(clk); 116 clk_put(clk);
109 117
118 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
119
110 return ret; 120 return ret;
111} 121}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 150963a6001..62d70635006 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -11,6 +11,8 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <asm/clkdev.h>
14#include <asm/clock.h> 16#include <asm/clock.h>
15#include <asm/freq.h> 17#include <asm/freq.h>
16#include <asm/io.h> 18#include <asm/io.h>
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
83}; 85};
84 86
85static struct clk sh7780_shyway_clk = { 87static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk",
87 .flags = CLK_ENABLE_ON_INIT, 88 .flags = CLK_ENABLE_ON_INIT,
88 .ops = &sh7780_shyway_clk_ops, 89 .ops = &sh7780_shyway_clk_ops,
89}; 90};
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk, 97 &sh7780_shyway_clk,
97}; 98};
98 99
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
101
102static struct clk_lookup lookups[] = {
103 /* main clocks */
104 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
105};
106
99int __init arch_clk_init(void) 107int __init arch_clk_init(void)
100{ 108{
101 struct clk *clk; 109 struct clk *clk;
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
113 121
114 clk_put(clk); 122 clk_put(clk);
115 123
124 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
125
116 return ret; 126 return ret;
117} 127}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index d997f0a25b1..c3e458aaa2b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7785 support for the clock framework 4 * SH7785 support for the clock framework
5 * 5 *
6 * Copyright (C) 2007 - 2009 Paul Mundt 6 * Copyright (C) 2007 - 2010 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -14,6 +14,7 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/cpufreq.h> 16#include <linux/cpufreq.h>
17#include <asm/clkdev.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19#include <cpu/sh7785.h> 20#include <cpu/sh7785.h>
@@ -23,8 +24,6 @@
23 * from the platform code. 24 * from the platform code.
24 */ 25 */
25static struct clk extal_clk = { 26static struct clk extal_clk = {
26 .name = "extal",
27 .id = -1,
28 .rate = 33333333, 27 .rate = 33333333,
29}; 28};
30 29
@@ -42,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
42}; 41};
43 42
44static struct clk pll_clk = { 43static struct clk pll_clk = {
45 .name = "pll_clk",
46 .id = -1,
47 .ops = &pll_clk_ops, 44 .ops = &pll_clk_ops,
48 .parent = &extal_clk, 45 .parent = &extal_clk,
49 .flags = CLK_ENABLE_ON_INIT, 46 .flags = CLK_ENABLE_ON_INIT,
@@ -69,48 +66,149 @@ static struct clk_div4_table div4_table = {
69enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 66enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
70 DIV4_DU, DIV4_P, DIV4_NR }; 67 DIV4_DU, DIV4_P, DIV4_NR };
71 68
72#define DIV4(_str, _bit, _mask, _flags) \ 69#define DIV4(_bit, _mask, _flags) \
73 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
74 71
75struct clk div4_clks[DIV4_NR] = { 72struct clk div4_clks[DIV4_NR] = {
76 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), 73 [DIV4_P] = DIV4(0, 0x0f80, 0),
77 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), 74 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
78 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), 75 [DIV4_GA] = DIV4(8, 0x0030, 0),
79 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), 76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
80 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
81 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
82 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
83 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
84}; 81};
85 82
86#define MSTPCR0 0xffc80030 83#define MSTPCR0 0xffc80030
87#define MSTPCR1 0xffc80034 84#define MSTPCR1 0xffc80034
88 85
89static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
89 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
90 MSTP_NR };
91
92static struct clk mstp_clks[MSTP_NR] = {
90 /* MSTPCR0 */ 93 /* MSTPCR0 */
91 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
92 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
93 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
94 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
95 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
96 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
97 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
98 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
99 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 102 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
100 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 103 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
101 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), 104 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
102 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), 105 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
103 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 106 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
104 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 107 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
105 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), 108 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
106 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 109 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
107 110
108 /* MSTPCR1 */ 111 /* MSTPCR1 */
109 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
110 SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), 113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
111 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
112 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
113 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
117};
118
119#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
120
121static struct clk_lookup lookups[] = {
122 /* main clocks */
123 CLKDEV_CON_ID("extal", &extal_clk),
124 CLKDEV_CON_ID("pll_clk", &pll_clk),
125
126 /* DIV4 clocks */
127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
133 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
135
136 /* MSTP32 clocks */
137 {
138 /* SCIF5 */
139 .dev_id = "sh-sci.5",
140 .con_id = "sci_fck",
141 .clk = &mstp_clks[MSTP029],
142 }, {
143 /* SCIF4 */
144 .dev_id = "sh-sci.4",
145 .con_id = "sci_fck",
146 .clk = &mstp_clks[MSTP028],
147 }, {
148 /* SCIF3 */
149 .dev_id = "sh-sci.3",
150 .con_id = "sci_fck",
151 .clk = &mstp_clks[MSTP027],
152 }, {
153 /* SCIF2 */
154 .dev_id = "sh-sci.2",
155 .con_id = "sci_fck",
156 .clk = &mstp_clks[MSTP026],
157 }, {
158 /* SCIF1 */
159 .dev_id = "sh-sci.1",
160 .con_id = "sci_fck",
161 .clk = &mstp_clks[MSTP025],
162 }, {
163 /* SCIF0 */
164 .dev_id = "sh-sci.0",
165 .con_id = "sci_fck",
166 .clk = &mstp_clks[MSTP024],
167 },
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
171 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
172 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
173 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
174 {
175 /* TMU0 */
176 .dev_id = "sh_tmu.0",
177 .con_id = "tmu_fck",
178 .clk = &mstp_clks[MSTP008],
179 }, {
180 /* TMU1 */
181 .dev_id = "sh_tmu.1",
182 .con_id = "tmu_fck",
183 .clk = &mstp_clks[MSTP008],
184 }, {
185 /* TMU2 */
186 .dev_id = "sh_tmu.2",
187 .con_id = "tmu_fck",
188 .clk = &mstp_clks[MSTP008],
189 }, {
190 /* TMU3 */
191 .dev_id = "sh_tmu.3",
192 .con_id = "tmu_fck",
193 .clk = &mstp_clks[MSTP009],
194 }, {
195 /* TMU4 */
196 .dev_id = "sh_tmu.4",
197 .con_id = "tmu_fck",
198 .clk = &mstp_clks[MSTP009],
199 }, {
200 /* TMU5 */
201 .dev_id = "sh_tmu.5",
202 .con_id = "tmu_fck",
203 .clk = &mstp_clks[MSTP009],
204 },
205 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
206 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
207 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
208 CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
209 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
210 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
211 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
114}; 212};
115 213
116int __init arch_clk_init(void) 214int __init arch_clk_init(void)
@@ -119,12 +217,14 @@ int __init arch_clk_init(void)
119 217
120 for (i = 0; i < ARRAY_SIZE(clks); i++) 218 for (i = 0; i < ARRAY_SIZE(clks); i++)
121 ret |= clk_register(clks[i]); 219 ret |= clk_register(clks[i]);
220 for (i = 0; i < ARRAY_SIZE(lookups); i++)
221 clkdev_add(&lookups[i]);
122 222
123 if (!ret) 223 if (!ret)
124 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 224 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
125 &div4_table); 225 &div4_table);
126 if (!ret) 226 if (!ret)
127 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 227 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
128 228
129 return ret; 229 return ret;
130} 230}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index af69fd46870..105a6d41b56 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,6 +13,8 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/clk.h>
17#include <asm/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18 20
@@ -21,8 +23,6 @@
21 * from the platform code. 23 * from the platform code.
22 */ 24 */
23static struct clk extal_clk = { 25static struct clk extal_clk = {
24 .name = "extal",
25 .id = -1,
26 .rate = 33333333, 26 .rate = 33333333,
27}; 27};
28 28
@@ -44,8 +44,6 @@ static struct clk_ops pll_clk_ops = {
44}; 44};
45 45
46static struct clk pll_clk = { 46static struct clk pll_clk = {
47 .name = "pll_clk",
48 .id = -1,
49 .ops = &pll_clk_ops, 47 .ops = &pll_clk_ops,
50 .parent = &extal_clk, 48 .parent = &extal_clk,
51 .flags = CLK_ENABLE_ON_INIT, 49 .flags = CLK_ENABLE_ON_INIT,
@@ -70,54 +68,191 @@ static struct clk_div4_table div4_table = {
70 68
71enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; 69enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
72 70
73#define DIV4(_str, _bit, _mask, _flags) \ 71#define DIV4(_bit, _mask, _flags) \
74 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 72 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
75 73
76struct clk div4_clks[DIV4_NR] = { 74struct clk div4_clks[DIV4_NR] = {
77 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0), 75 [DIV4_P] = DIV4(0, 0x0b40, 0),
78 [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0), 76 [DIV4_DU] = DIV4(4, 0x0010, 0),
79 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT), 77 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
80 [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT), 78 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
81 [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT), 79 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
82 [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
83}; 81};
84 82
85#define MSTPCR0 0xffc40030 83#define MSTPCR0 0xffc40030
86#define MSTPCR1 0xffc40034 84#define MSTPCR1 0xffc40034
87 85
88static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
89 MSTP005, MSTP004, MSTP002,
90 MSTP112, MSTP110, MSTP109, MSTP108,
91 MSTP105, MSTP104, MSTP103, MSTP102,
92 MSTP_NR };
93
94static struct clk mstp_clks[MSTP_NR] = {
89 /* MSTPCR0 */ 95 /* MSTPCR0 */
90 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 96 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
91 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 97 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
92 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 98 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
93 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 99 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
94 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 100 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
95 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 101 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
96 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), 102 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
97 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), 103 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
98 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 104 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
99 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 105 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
100 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 106 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
101 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 107 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
102 SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), 108 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
103 SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), 109 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
104 SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), 110 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
105 SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), 111 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
106 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 112 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
107 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 113 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
108 SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 114 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
109 SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 115 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
110 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 116 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
111 117
112 /* MSTPCR1 */ 118 /* MSTPCR1 */
113 SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), 119 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
114 SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), 120 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
115 SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), 121 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
116 SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), 122 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
117 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 123 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
118 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 124 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
119 SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), 125 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
120 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), 126 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
127};
128
129#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
130
131static struct clk_lookup lookups[] = {
132 /* main clocks */
133 CLKDEV_CON_ID("extal", &extal_clk),
134 CLKDEV_CON_ID("pll_clk", &pll_clk),
135
136 /* DIV4 clocks */
137 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
138 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
139 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
140 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
141 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
142 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
143
144 /* MSTP32 clocks */
145 {
146 /* SCIF5 */
147 .dev_id = "sh-sci.5",
148 .con_id = "sci_fck",
149 .clk = &mstp_clks[MSTP029],
150 }, {
151 /* SCIF4 */
152 .dev_id = "sh-sci.4",
153 .con_id = "sci_fck",
154 .clk = &mstp_clks[MSTP028],
155 }, {
156 /* SCIF3 */
157 .dev_id = "sh-sci.3",
158 .con_id = "sci_fck",
159 .clk = &mstp_clks[MSTP027],
160 }, {
161 /* SCIF2 */
162 .dev_id = "sh-sci.2",
163 .con_id = "sci_fck",
164 .clk = &mstp_clks[MSTP026],
165 }, {
166 /* SCIF1 */
167 .dev_id = "sh-sci.1",
168 .con_id = "sci_fck",
169 .clk = &mstp_clks[MSTP025],
170 }, {
171 /* SCIF0 */
172 .dev_id = "sh-sci.0",
173 .con_id = "sci_fck",
174 .clk = &mstp_clks[MSTP024],
175 },
176 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
177 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
178 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
179 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
180 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
181 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
182 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
183 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
184 {
185 /* TMU0 */
186 .dev_id = "sh_tmu.0",
187 .con_id = "tmu_fck",
188 .clk = &mstp_clks[MSTP008],
189 }, {
190 /* TMU1 */
191 .dev_id = "sh_tmu.1",
192 .con_id = "tmu_fck",
193 .clk = &mstp_clks[MSTP008],
194 }, {
195 /* TMU2 */
196 .dev_id = "sh_tmu.2",
197 .con_id = "tmu_fck",
198 .clk = &mstp_clks[MSTP008],
199 }, {
200 /* TMU3 */
201 .dev_id = "sh_tmu.3",
202 .con_id = "tmu_fck",
203 .clk = &mstp_clks[MSTP009],
204 }, {
205 /* TMU4 */
206 .dev_id = "sh_tmu.4",
207 .con_id = "tmu_fck",
208 .clk = &mstp_clks[MSTP009],
209 }, {
210 /* TMU5 */
211 .dev_id = "sh_tmu.5",
212 .con_id = "tmu_fck",
213 .clk = &mstp_clks[MSTP009],
214 }, {
215 /* TMU6 */
216 .dev_id = "sh_tmu.6",
217 .con_id = "tmu_fck",
218 .clk = &mstp_clks[MSTP010],
219 }, {
220 /* TMU7 */
221 .dev_id = "sh_tmu.7",
222 .con_id = "tmu_fck",
223 .clk = &mstp_clks[MSTP010],
224 }, {
225 /* TMU8 */
226 .dev_id = "sh_tmu.8",
227 .con_id = "tmu_fck",
228 .clk = &mstp_clks[MSTP010],
229 }, {
230 /* TMU9 */
231 .dev_id = "sh_tmu.9",
232 .con_id = "tmu_fck",
233 .clk = &mstp_clks[MSTP011],
234 }, {
235 /* TMU10 */
236 .dev_id = "sh_tmu.10",
237 .con_id = "tmu_fck",
238 .clk = &mstp_clks[MSTP011],
239 }, {
240 /* TMU11 */
241 .dev_id = "sh_tmu.11",
242 .con_id = "tmu_fck",
243 .clk = &mstp_clks[MSTP011],
244 },
245 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
246 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
247 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
248 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
249 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
250 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
251 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
252 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
253 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
254 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
255 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
121}; 256};
122 257
123int __init arch_clk_init(void) 258int __init arch_clk_init(void)
@@ -126,12 +261,14 @@ int __init arch_clk_init(void)
126 261
127 for (i = 0; i < ARRAY_SIZE(clks); i++) 262 for (i = 0; i < ARRAY_SIZE(clks); i++)
128 ret |= clk_register(clks[i]); 263 ret |= clk_register(clks[i]);
264 for (i = 0; i < ARRAY_SIZE(lookups); i++)
265 clkdev_add(&lookups[i]);
129 266
130 if (!ret) 267 if (!ret)
131 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 268 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
132 &div4_table); 269 &div4_table);
133 if (!ret) 270 if (!ret)
134 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 271 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
135 272
136 return ret; 273 return ret;
137} 274}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index e75c57bdfa5..236a6282d77 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -13,9 +13,10 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <asm/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18#include <asm/io.h>
19 20
20static int ifc_divisors[] = { 1, 2, 4 ,6 }; 21static int ifc_divisors[] = { 1, 2, 4 ,6 };
21static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; 22static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
@@ -94,7 +95,6 @@ static struct clk_ops shx3_shyway_clk_ops = {
94}; 95};
95 96
96static struct clk shx3_shyway_clk = { 97static struct clk shx3_shyway_clk = {
97 .name = "shyway_clk",
98 .flags = CLK_ENABLE_ON_INIT, 98 .flags = CLK_ENABLE_ON_INIT,
99 .ops = &shx3_shyway_clk_ops, 99 .ops = &shx3_shyway_clk_ops,
100}; 100};
@@ -107,6 +107,13 @@ static struct clk *shx3_onchip_clocks[] = {
107 &shx3_shyway_clk, 107 &shx3_shyway_clk,
108}; 108};
109 109
110#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
111
112static struct clk_lookup lookups[] = {
113 /* main clocks */
114 CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
115};
116
110int __init arch_clk_init(void) 117int __init arch_clk_init(void)
111{ 118{
112 struct clk *clk; 119 struct clk *clk;
@@ -124,5 +131,7 @@ int __init arch_clk_init(void)
124 131
125 clk_put(clk); 132 clk_put(clk);
126 133
134 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
135
127 return ret; 136 return ret;
128} 137}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 45eb1bfd42c..3681cafdb4a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = {
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 80, 80, 80, 80 }, 23 .irqs = { 80, 80, 80, 80 },
24 .clk = "scif0",
25}; 24};
26 25
27static struct platform_device scif0_device = { 26static struct platform_device scif0_device = {
@@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = {
37 .flags = UPF_BOOT_AUTOCONF, 36 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF, 37 .type = PORT_SCIF,
39 .irqs = { 81, 81, 81, 81 }, 38 .irqs = { 81, 81, 81, 81 },
40 .clk = "scif1",
41}; 39};
42 40
43static struct platform_device scif1_device = { 41static struct platform_device scif1_device = {
@@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = {
53 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
54 .type = PORT_SCIF, 52 .type = PORT_SCIF,
55 .irqs = { 82, 82, 82, 82 }, 53 .irqs = { 82, 82, 82, 82 },
56 .clk = "scif2",
57}; 54};
58 55
59static struct platform_device scif2_device = { 56static struct platform_device scif2_device = {
@@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = {
69 .flags = UPF_BOOT_AUTOCONF, 66 .flags = UPF_BOOT_AUTOCONF,
70 .type = PORT_SCIF, 67 .type = PORT_SCIF,
71 .irqs = { 83, 83, 83, 83 }, 68 .irqs = { 83, 83, 83, 83 },
72 .clk = "scif3",
73}; 69};
74 70
75static struct platform_device scif3_device = { 71static struct platform_device scif3_device = {
@@ -207,17 +203,14 @@ static struct platform_device jpu_device = {
207}; 203};
208 204
209static struct sh_timer_config cmt_platform_data = { 205static struct sh_timer_config cmt_platform_data = {
210 .name = "CMT",
211 .channel_offset = 0x60, 206 .channel_offset = 0x60,
212 .timer_bit = 5, 207 .timer_bit = 5,
213 .clk = "cmt0",
214 .clockevent_rating = 125, 208 .clockevent_rating = 125,
215 .clocksource_rating = 200, 209 .clocksource_rating = 200,
216}; 210};
217 211
218static struct resource cmt_resources[] = { 212static struct resource cmt_resources[] = {
219 [0] = { 213 [0] = {
220 .name = "CMT",
221 .start = 0x044a0060, 214 .start = 0x044a0060,
222 .end = 0x044a006b, 215 .end = 0x044a006b,
223 .flags = IORESOURCE_MEM, 216 .flags = IORESOURCE_MEM,
@@ -239,16 +232,13 @@ static struct platform_device cmt_device = {
239}; 232};
240 233
241static struct sh_timer_config tmu0_platform_data = { 234static struct sh_timer_config tmu0_platform_data = {
242 .name = "TMU0",
243 .channel_offset = 0x04, 235 .channel_offset = 0x04,
244 .timer_bit = 0, 236 .timer_bit = 0,
245 .clk = "tmu0",
246 .clockevent_rating = 200, 237 .clockevent_rating = 200,
247}; 238};
248 239
249static struct resource tmu0_resources[] = { 240static struct resource tmu0_resources[] = {
250 [0] = { 241 [0] = {
251 .name = "TMU0",
252 .start = 0xffd80008, 242 .start = 0xffd80008,
253 .end = 0xffd80013, 243 .end = 0xffd80013,
254 .flags = IORESOURCE_MEM, 244 .flags = IORESOURCE_MEM,
@@ -270,16 +260,13 @@ static struct platform_device tmu0_device = {
270}; 260};
271 261
272static struct sh_timer_config tmu1_platform_data = { 262static struct sh_timer_config tmu1_platform_data = {
273 .name = "TMU1",
274 .channel_offset = 0x10, 263 .channel_offset = 0x10,
275 .timer_bit = 1, 264 .timer_bit = 1,
276 .clk = "tmu0",
277 .clocksource_rating = 200, 265 .clocksource_rating = 200,
278}; 266};
279 267
280static struct resource tmu1_resources[] = { 268static struct resource tmu1_resources[] = {
281 [0] = { 269 [0] = {
282 .name = "TMU1",
283 .start = 0xffd80014, 270 .start = 0xffd80014,
284 .end = 0xffd8001f, 271 .end = 0xffd8001f,
285 .flags = IORESOURCE_MEM, 272 .flags = IORESOURCE_MEM,
@@ -301,15 +288,12 @@ static struct platform_device tmu1_device = {
301}; 288};
302 289
303static struct sh_timer_config tmu2_platform_data = { 290static struct sh_timer_config tmu2_platform_data = {
304 .name = "TMU2",
305 .channel_offset = 0x1c, 291 .channel_offset = 0x1c,
306 .timer_bit = 2, 292 .timer_bit = 2,
307 .clk = "tmu0",
308}; 293};
309 294
310static struct resource tmu2_resources[] = { 295static struct resource tmu2_resources[] = {
311 [0] = { 296 [0] = {
312 .name = "TMU2",
313 .start = 0xffd80020, 297 .start = 0xffd80020,
314 .end = 0xffd8002b, 298 .end = 0xffd8002b,
315 .flags = IORESOURCE_MEM, 299 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index c494c193e3b..8dab9e1bbd8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
23 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 25 .irqs = { 80, 80, 80, 80 },
26 .clk = "scif0",
27}; 26};
28 27
29static struct platform_device scif0_device = { 28static struct platform_device scif0_device = {
@@ -169,17 +168,14 @@ static struct platform_device veu1_device = {
169}; 168};
170 169
171static struct sh_timer_config cmt_platform_data = { 170static struct sh_timer_config cmt_platform_data = {
172 .name = "CMT",
173 .channel_offset = 0x60, 171 .channel_offset = 0x60,
174 .timer_bit = 5, 172 .timer_bit = 5,
175 .clk = "cmt0",
176 .clockevent_rating = 125, 173 .clockevent_rating = 125,
177 .clocksource_rating = 200, 174 .clocksource_rating = 200,
178}; 175};
179 176
180static struct resource cmt_resources[] = { 177static struct resource cmt_resources[] = {
181 [0] = { 178 [0] = {
182 .name = "CMT",
183 .start = 0x044a0060, 179 .start = 0x044a0060,
184 .end = 0x044a006b, 180 .end = 0x044a006b,
185 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
@@ -201,16 +197,13 @@ static struct platform_device cmt_device = {
201}; 197};
202 198
203static struct sh_timer_config tmu0_platform_data = { 199static struct sh_timer_config tmu0_platform_data = {
204 .name = "TMU0",
205 .channel_offset = 0x04, 200 .channel_offset = 0x04,
206 .timer_bit = 0, 201 .timer_bit = 0,
207 .clk = "tmu0",
208 .clockevent_rating = 200, 202 .clockevent_rating = 200,
209}; 203};
210 204
211static struct resource tmu0_resources[] = { 205static struct resource tmu0_resources[] = {
212 [0] = { 206 [0] = {
213 .name = "TMU0",
214 .start = 0xffd80008, 207 .start = 0xffd80008,
215 .end = 0xffd80013, 208 .end = 0xffd80013,
216 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
@@ -232,16 +225,13 @@ static struct platform_device tmu0_device = {
232}; 225};
233 226
234static struct sh_timer_config tmu1_platform_data = { 227static struct sh_timer_config tmu1_platform_data = {
235 .name = "TMU1",
236 .channel_offset = 0x10, 228 .channel_offset = 0x10,
237 .timer_bit = 1, 229 .timer_bit = 1,
238 .clk = "tmu0",
239 .clocksource_rating = 200, 230 .clocksource_rating = 200,
240}; 231};
241 232
242static struct resource tmu1_resources[] = { 233static struct resource tmu1_resources[] = {
243 [0] = { 234 [0] = {
244 .name = "TMU1",
245 .start = 0xffd80014, 235 .start = 0xffd80014,
246 .end = 0xffd8001f, 236 .end = 0xffd8001f,
247 .flags = IORESOURCE_MEM, 237 .flags = IORESOURCE_MEM,
@@ -263,15 +253,12 @@ static struct platform_device tmu1_device = {
263}; 253};
264 254
265static struct sh_timer_config tmu2_platform_data = { 255static struct sh_timer_config tmu2_platform_data = {
266 .name = "TMU2",
267 .channel_offset = 0x1c, 256 .channel_offset = 0x1c,
268 .timer_bit = 2, 257 .timer_bit = 2,
269 .clk = "tmu0",
270}; 258};
271 259
272static struct resource tmu2_resources[] = { 260static struct resource tmu2_resources[] = {
273 [0] = { 261 [0] = {
274 .name = "TMU2",
275 .start = 0xffd80020, 262 .start = 0xffd80020,
276 .end = 0xffd8002b, 263 .end = 0xffd8002b,
277 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index fd7e3639e84..24c6167a718 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -24,7 +24,7 @@
24#include <cpu/dma-register.h> 24#include <cpu/dma-register.h>
25#include <cpu/sh7722.h> 25#include <cpu/sh7722.h>
26 26
27static struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 27static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
28 { 28 {
29 .slave_id = SHDMA_SLAVE_SCIF0_TX, 29 .slave_id = SHDMA_SLAVE_SCIF0_TX,
30 .addr = 0xffe0000c, 30 .addr = 0xffe0000c,
@@ -78,7 +78,7 @@ static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
78 }, 78 },
79}; 79};
80 80
81static struct sh_dmae_channel sh7722_dmae_channels[] = { 81static const struct sh_dmae_channel sh7722_dmae_channels[] = {
82 { 82 {
83 .offset = 0, 83 .offset = 0,
84 .dmars = 0, 84 .dmars = 0,
@@ -106,7 +106,7 @@ static struct sh_dmae_channel sh7722_dmae_channels[] = {
106 } 106 }
107}; 107};
108 108
109static unsigned int ts_shift[] = TS_SHIFT; 109static const unsigned int ts_shift[] = TS_SHIFT;
110 110
111static struct sh_dmae_pdata dma_platform_data = { 111static struct sh_dmae_pdata dma_platform_data = {
112 .slave = sh7722_dmae_slaves, 112 .slave = sh7722_dmae_slaves,
@@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = {
174 .flags = UPF_BOOT_AUTOCONF, 174 .flags = UPF_BOOT_AUTOCONF,
175 .type = PORT_SCIF, 175 .type = PORT_SCIF,
176 .irqs = { 80, 80, 80, 80 }, 176 .irqs = { 80, 80, 80, 80 },
177 .clk = "scif0",
178}; 177};
179 178
180static struct platform_device scif0_device = { 179static struct platform_device scif0_device = {
@@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = {
190 .flags = UPF_BOOT_AUTOCONF, 189 .flags = UPF_BOOT_AUTOCONF,
191 .type = PORT_SCIF, 190 .type = PORT_SCIF,
192 .irqs = { 81, 81, 81, 81 }, 191 .irqs = { 81, 81, 81, 81 },
193 .clk = "scif1",
194}; 192};
195 193
196static struct platform_device scif1_device = { 194static struct platform_device scif1_device = {
@@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = {
206 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
207 .type = PORT_SCIF, 205 .type = PORT_SCIF,
208 .irqs = { 82, 82, 82, 82 }, 206 .irqs = { 82, 82, 82, 82 },
209 .clk = "scif2",
210}; 207};
211 208
212static struct platform_device scif2_device = { 209static struct platform_device scif2_device = {
@@ -401,17 +398,14 @@ static struct platform_device jpu_device = {
401}; 398};
402 399
403static struct sh_timer_config cmt_platform_data = { 400static struct sh_timer_config cmt_platform_data = {
404 .name = "CMT",
405 .channel_offset = 0x60, 401 .channel_offset = 0x60,
406 .timer_bit = 5, 402 .timer_bit = 5,
407 .clk = "cmt0",
408 .clockevent_rating = 125, 403 .clockevent_rating = 125,
409 .clocksource_rating = 125, 404 .clocksource_rating = 125,
410}; 405};
411 406
412static struct resource cmt_resources[] = { 407static struct resource cmt_resources[] = {
413 [0] = { 408 [0] = {
414 .name = "CMT",
415 .start = 0x044a0060, 409 .start = 0x044a0060,
416 .end = 0x044a006b, 410 .end = 0x044a006b,
417 .flags = IORESOURCE_MEM, 411 .flags = IORESOURCE_MEM,
@@ -436,16 +430,13 @@ static struct platform_device cmt_device = {
436}; 430};
437 431
438static struct sh_timer_config tmu0_platform_data = { 432static struct sh_timer_config tmu0_platform_data = {
439 .name = "TMU0",
440 .channel_offset = 0x04, 433 .channel_offset = 0x04,
441 .timer_bit = 0, 434 .timer_bit = 0,
442 .clk = "tmu0",
443 .clockevent_rating = 200, 435 .clockevent_rating = 200,
444}; 436};
445 437
446static struct resource tmu0_resources[] = { 438static struct resource tmu0_resources[] = {
447 [0] = { 439 [0] = {
448 .name = "TMU0",
449 .start = 0xffd80008, 440 .start = 0xffd80008,
450 .end = 0xffd80013, 441 .end = 0xffd80013,
451 .flags = IORESOURCE_MEM, 442 .flags = IORESOURCE_MEM,
@@ -470,16 +461,13 @@ static struct platform_device tmu0_device = {
470}; 461};
471 462
472static struct sh_timer_config tmu1_platform_data = { 463static struct sh_timer_config tmu1_platform_data = {
473 .name = "TMU1",
474 .channel_offset = 0x10, 464 .channel_offset = 0x10,
475 .timer_bit = 1, 465 .timer_bit = 1,
476 .clk = "tmu0",
477 .clocksource_rating = 200, 466 .clocksource_rating = 200,
478}; 467};
479 468
480static struct resource tmu1_resources[] = { 469static struct resource tmu1_resources[] = {
481 [0] = { 470 [0] = {
482 .name = "TMU1",
483 .start = 0xffd80014, 471 .start = 0xffd80014,
484 .end = 0xffd8001f, 472 .end = 0xffd8001f,
485 .flags = IORESOURCE_MEM, 473 .flags = IORESOURCE_MEM,
@@ -504,15 +492,12 @@ static struct platform_device tmu1_device = {
504}; 492};
505 493
506static struct sh_timer_config tmu2_platform_data = { 494static struct sh_timer_config tmu2_platform_data = {
507 .name = "TMU2",
508 .channel_offset = 0x1c, 495 .channel_offset = 0x1c,
509 .timer_bit = 2, 496 .timer_bit = 2,
510 .clk = "tmu0",
511}; 497};
512 498
513static struct resource tmu2_resources[] = { 499static struct resource tmu2_resources[] = {
514 [0] = { 500 [0] = {
515 .name = "TMU2",
516 .start = 0xffd80020, 501 .start = 0xffd80020,
517 .end = 0xffd8002b, 502 .end = 0xffd8002b,
518 .flags = IORESOURCE_MEM, 503 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 85c61f62470..0eadefdbbba 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 28 .irqs = { 80, 80, 80, 80 },
29 .clk = "scif0",
30}; 29};
31 30
32static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
@@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = {
42 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF, 42 .type = PORT_SCIF,
44 .irqs = { 81, 81, 81, 81 }, 43 .irqs = { 81, 81, 81, 81 },
45 .clk = "scif1",
46}; 44};
47 45
48static struct platform_device scif1_device = { 46static struct platform_device scif1_device = {
@@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = {
58 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
59 .type = PORT_SCIF, 57 .type = PORT_SCIF,
60 .irqs = { 82, 82, 82, 82 }, 58 .irqs = { 82, 82, 82, 82 },
61 .clk = "scif2",
62}; 59};
63 60
64static struct platform_device scif2_device = { 61static struct platform_device scif2_device = {
@@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = {
74 .flags = UPF_BOOT_AUTOCONF, 71 .flags = UPF_BOOT_AUTOCONF,
75 .type = PORT_SCIFA, 72 .type = PORT_SCIFA,
76 .irqs = { 56, 56, 56, 56 }, 73 .irqs = { 56, 56, 56, 56 },
77 .clk = "scif3",
78}; 74};
79 75
80static struct platform_device scif3_device = { 76static struct platform_device scif3_device = {
@@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = {
90 .flags = UPF_BOOT_AUTOCONF, 86 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIFA, 87 .type = PORT_SCIFA,
92 .irqs = { 88, 88, 88, 88 }, 88 .irqs = { 88, 88, 88, 88 },
93 .clk = "scif4",
94}; 89};
95 90
96static struct platform_device scif4_device = { 91static struct platform_device scif4_device = {
@@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = {
106 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
107 .type = PORT_SCIFA, 102 .type = PORT_SCIFA,
108 .irqs = { 109, 109, 109, 109 }, 103 .irqs = { 109, 109, 109, 109 },
109 .clk = "scif5",
110}; 104};
111 105
112static struct platform_device scif5_device = { 106static struct platform_device scif5_device = {
@@ -211,17 +205,14 @@ static struct platform_device veu1_device = {
211}; 205};
212 206
213static struct sh_timer_config cmt_platform_data = { 207static struct sh_timer_config cmt_platform_data = {
214 .name = "CMT",
215 .channel_offset = 0x60, 208 .channel_offset = 0x60,
216 .timer_bit = 5, 209 .timer_bit = 5,
217 .clk = "cmt0",
218 .clockevent_rating = 125, 210 .clockevent_rating = 125,
219 .clocksource_rating = 125, 211 .clocksource_rating = 125,
220}; 212};
221 213
222static struct resource cmt_resources[] = { 214static struct resource cmt_resources[] = {
223 [0] = { 215 [0] = {
224 .name = "CMT",
225 .start = 0x044a0060, 216 .start = 0x044a0060,
226 .end = 0x044a006b, 217 .end = 0x044a006b,
227 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
@@ -246,16 +237,13 @@ static struct platform_device cmt_device = {
246}; 237};
247 238
248static struct sh_timer_config tmu0_platform_data = { 239static struct sh_timer_config tmu0_platform_data = {
249 .name = "TMU0",
250 .channel_offset = 0x04, 240 .channel_offset = 0x04,
251 .timer_bit = 0, 241 .timer_bit = 0,
252 .clk = "tmu0",
253 .clockevent_rating = 200, 242 .clockevent_rating = 200,
254}; 243};
255 244
256static struct resource tmu0_resources[] = { 245static struct resource tmu0_resources[] = {
257 [0] = { 246 [0] = {
258 .name = "TMU0",
259 .start = 0xffd80008, 247 .start = 0xffd80008,
260 .end = 0xffd80013, 248 .end = 0xffd80013,
261 .flags = IORESOURCE_MEM, 249 .flags = IORESOURCE_MEM,
@@ -280,16 +268,13 @@ static struct platform_device tmu0_device = {
280}; 268};
281 269
282static struct sh_timer_config tmu1_platform_data = { 270static struct sh_timer_config tmu1_platform_data = {
283 .name = "TMU1",
284 .channel_offset = 0x10, 271 .channel_offset = 0x10,
285 .timer_bit = 1, 272 .timer_bit = 1,
286 .clk = "tmu0",
287 .clocksource_rating = 200, 273 .clocksource_rating = 200,
288}; 274};
289 275
290static struct resource tmu1_resources[] = { 276static struct resource tmu1_resources[] = {
291 [0] = { 277 [0] = {
292 .name = "TMU1",
293 .start = 0xffd80014, 278 .start = 0xffd80014,
294 .end = 0xffd8001f, 279 .end = 0xffd8001f,
295 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
@@ -314,15 +299,12 @@ static struct platform_device tmu1_device = {
314}; 299};
315 300
316static struct sh_timer_config tmu2_platform_data = { 301static struct sh_timer_config tmu2_platform_data = {
317 .name = "TMU2",
318 .channel_offset = 0x1c, 302 .channel_offset = 0x1c,
319 .timer_bit = 2, 303 .timer_bit = 2,
320 .clk = "tmu0",
321}; 304};
322 305
323static struct resource tmu2_resources[] = { 306static struct resource tmu2_resources[] = {
324 [0] = { 307 [0] = {
325 .name = "TMU2",
326 .start = 0xffd80020, 308 .start = 0xffd80020,
327 .end = 0xffd8002b, 309 .end = 0xffd8002b,
328 .flags = IORESOURCE_MEM, 310 .flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu2_device = {
347}; 329};
348 330
349static struct sh_timer_config tmu3_platform_data = { 331static struct sh_timer_config tmu3_platform_data = {
350 .name = "TMU3",
351 .channel_offset = 0x04, 332 .channel_offset = 0x04,
352 .timer_bit = 0, 333 .timer_bit = 0,
353 .clk = "tmu1",
354}; 334};
355 335
356static struct resource tmu3_resources[] = { 336static struct resource tmu3_resources[] = {
357 [0] = { 337 [0] = {
358 .name = "TMU3",
359 .start = 0xffd90008, 338 .start = 0xffd90008,
360 .end = 0xffd90013, 339 .end = 0xffd90013,
361 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -380,15 +359,12 @@ static struct platform_device tmu3_device = {
380}; 359};
381 360
382static struct sh_timer_config tmu4_platform_data = { 361static struct sh_timer_config tmu4_platform_data = {
383 .name = "TMU4",
384 .channel_offset = 0x10, 362 .channel_offset = 0x10,
385 .timer_bit = 1, 363 .timer_bit = 1,
386 .clk = "tmu1",
387}; 364};
388 365
389static struct resource tmu4_resources[] = { 366static struct resource tmu4_resources[] = {
390 [0] = { 367 [0] = {
391 .name = "TMU4",
392 .start = 0xffd90014, 368 .start = 0xffd90014,
393 .end = 0xffd9001f, 369 .end = 0xffd9001f,
394 .flags = IORESOURCE_MEM, 370 .flags = IORESOURCE_MEM,
@@ -413,15 +389,12 @@ static struct platform_device tmu4_device = {
413}; 389};
414 390
415static struct sh_timer_config tmu5_platform_data = { 391static struct sh_timer_config tmu5_platform_data = {
416 .name = "TMU5",
417 .channel_offset = 0x1c, 392 .channel_offset = 0x1c,
418 .timer_bit = 2, 393 .timer_bit = 2,
419 .clk = "tmu1",
420}; 394};
421 395
422static struct resource tmu5_resources[] = { 396static struct resource tmu5_resources[] = {
423 [0] = { 397 [0] = {
424 .name = "TMU5",
425 .start = 0xffd90020, 398 .start = 0xffd90020,
426 .end = 0xffd9002b, 399 .end = 0xffd9002b,
427 .flags = IORESOURCE_MEM, 400 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index e7fa2a92fc1..89fe16d20fd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -31,7 +31,7 @@
31#include <cpu/sh7724.h> 31#include <cpu/sh7724.h>
32 32
33/* DMA */ 33/* DMA */
34static struct sh_dmae_channel sh7724_dmae0_channels[] = { 34static const struct sh_dmae_channel sh7724_dmae_channels[] = {
35 { 35 {
36 .offset = 0, 36 .offset = 0,
37 .dmars = 0, 37 .dmars = 0,
@@ -59,51 +59,11 @@ static struct sh_dmae_channel sh7724_dmae0_channels[] = {
59 } 59 }
60}; 60};
61 61
62static struct sh_dmae_channel sh7724_dmae1_channels[] = { 62static const unsigned int ts_shift[] = TS_SHIFT;
63 {
64 .offset = 0,
65 .dmars = 0,
66 .dmars_bit = 0,
67 }, {
68 .offset = 0x10,
69 .dmars = 0,
70 .dmars_bit = 8,
71 }, {
72 .offset = 0x20,
73 .dmars = 4,
74 .dmars_bit = 0,
75 }, {
76 .offset = 0x30,
77 .dmars = 4,
78 .dmars_bit = 8,
79 }, {
80 .offset = 0x50,
81 .dmars = 8,
82 .dmars_bit = 0,
83 }, {
84 .offset = 0x60,
85 .dmars = 8,
86 .dmars_bit = 8,
87 }
88};
89
90static unsigned int ts_shift[] = TS_SHIFT;
91
92static struct sh_dmae_pdata dma0_platform_data = {
93 .channel = sh7724_dmae0_channels,
94 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
95 .ts_low_shift = CHCR_TS_LOW_SHIFT,
96 .ts_low_mask = CHCR_TS_LOW_MASK,
97 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
98 .ts_high_mask = CHCR_TS_HIGH_MASK,
99 .ts_shift = ts_shift,
100 .ts_shift_num = ARRAY_SIZE(ts_shift),
101 .dmaor_init = DMAOR_INIT,
102};
103 63
104static struct sh_dmae_pdata dma1_platform_data = { 64static struct sh_dmae_pdata dma_platform_data = {
105 .channel = sh7724_dmae1_channels, 65 .channel = sh7724_dmae_channels,
106 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels), 66 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
107 .ts_low_shift = CHCR_TS_LOW_SHIFT, 67 .ts_low_shift = CHCR_TS_LOW_SHIFT,
108 .ts_low_mask = CHCR_TS_LOW_MASK, 68 .ts_low_mask = CHCR_TS_LOW_MASK,
109 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 69 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
@@ -187,7 +147,7 @@ static struct platform_device dma0_device = {
187 .resource = sh7724_dmae0_resources, 147 .resource = sh7724_dmae0_resources,
188 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 148 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
189 .dev = { 149 .dev = {
190 .platform_data = &dma0_platform_data, 150 .platform_data = &dma_platform_data,
191 }, 151 },
192 .archdata = { 152 .archdata = {
193 .hwblk_id = HWBLK_DMAC0, 153 .hwblk_id = HWBLK_DMAC0,
@@ -200,7 +160,7 @@ static struct platform_device dma1_device = {
200 .resource = sh7724_dmae1_resources, 160 .resource = sh7724_dmae1_resources,
201 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 161 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
202 .dev = { 162 .dev = {
203 .platform_data = &dma1_platform_data, 163 .platform_data = &dma_platform_data,
204 }, 164 },
205 .archdata = { 165 .archdata = {
206 .hwblk_id = HWBLK_DMAC1, 166 .hwblk_id = HWBLK_DMAC1,
@@ -213,7 +173,6 @@ static struct plat_sci_port scif0_platform_data = {
213 .flags = UPF_BOOT_AUTOCONF, 173 .flags = UPF_BOOT_AUTOCONF,
214 .type = PORT_SCIF, 174 .type = PORT_SCIF,
215 .irqs = { 80, 80, 80, 80 }, 175 .irqs = { 80, 80, 80, 80 },
216 .clk = "scif0",
217}; 176};
218 177
219static struct platform_device scif0_device = { 178static struct platform_device scif0_device = {
@@ -229,7 +188,6 @@ static struct plat_sci_port scif1_platform_data = {
229 .flags = UPF_BOOT_AUTOCONF, 188 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF, 189 .type = PORT_SCIF,
231 .irqs = { 81, 81, 81, 81 }, 190 .irqs = { 81, 81, 81, 81 },
232 .clk = "scif1",
233}; 191};
234 192
235static struct platform_device scif1_device = { 193static struct platform_device scif1_device = {
@@ -245,7 +203,6 @@ static struct plat_sci_port scif2_platform_data = {
245 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF, 204 .type = PORT_SCIF,
247 .irqs = { 82, 82, 82, 82 }, 205 .irqs = { 82, 82, 82, 82 },
248 .clk = "scif2",
249}; 206};
250 207
251static struct platform_device scif2_device = { 208static struct platform_device scif2_device = {
@@ -261,7 +218,6 @@ static struct plat_sci_port scif3_platform_data = {
261 .flags = UPF_BOOT_AUTOCONF, 218 .flags = UPF_BOOT_AUTOCONF,
262 .type = PORT_SCIFA, 219 .type = PORT_SCIFA,
263 .irqs = { 56, 56, 56, 56 }, 220 .irqs = { 56, 56, 56, 56 },
264 .clk = "scif3",
265}; 221};
266 222
267static struct platform_device scif3_device = { 223static struct platform_device scif3_device = {
@@ -277,7 +233,6 @@ static struct plat_sci_port scif4_platform_data = {
277 .flags = UPF_BOOT_AUTOCONF, 233 .flags = UPF_BOOT_AUTOCONF,
278 .type = PORT_SCIFA, 234 .type = PORT_SCIFA,
279 .irqs = { 88, 88, 88, 88 }, 235 .irqs = { 88, 88, 88, 88 },
280 .clk = "scif4",
281}; 236};
282 237
283static struct platform_device scif4_device = { 238static struct platform_device scif4_device = {
@@ -293,7 +248,6 @@ static struct plat_sci_port scif5_platform_data = {
293 .flags = UPF_BOOT_AUTOCONF, 248 .flags = UPF_BOOT_AUTOCONF,
294 .type = PORT_SCIFA, 249 .type = PORT_SCIFA,
295 .irqs = { 109, 109, 109, 109 }, 250 .irqs = { 109, 109, 109, 109 },
296 .clk = "scif5",
297}; 251};
298 252
299static struct platform_device scif5_device = { 253static struct platform_device scif5_device = {
@@ -485,17 +439,14 @@ static struct platform_device veu1_device = {
485}; 439};
486 440
487static struct sh_timer_config cmt_platform_data = { 441static struct sh_timer_config cmt_platform_data = {
488 .name = "CMT",
489 .channel_offset = 0x60, 442 .channel_offset = 0x60,
490 .timer_bit = 5, 443 .timer_bit = 5,
491 .clk = "cmt0",
492 .clockevent_rating = 125, 444 .clockevent_rating = 125,
493 .clocksource_rating = 200, 445 .clocksource_rating = 200,
494}; 446};
495 447
496static struct resource cmt_resources[] = { 448static struct resource cmt_resources[] = {
497 [0] = { 449 [0] = {
498 .name = "CMT",
499 .start = 0x044a0060, 450 .start = 0x044a0060,
500 .end = 0x044a006b, 451 .end = 0x044a006b,
501 .flags = IORESOURCE_MEM, 452 .flags = IORESOURCE_MEM,
@@ -520,16 +471,13 @@ static struct platform_device cmt_device = {
520}; 471};
521 472
522static struct sh_timer_config tmu0_platform_data = { 473static struct sh_timer_config tmu0_platform_data = {
523 .name = "TMU0",
524 .channel_offset = 0x04, 474 .channel_offset = 0x04,
525 .timer_bit = 0, 475 .timer_bit = 0,
526 .clk = "tmu0",
527 .clockevent_rating = 200, 476 .clockevent_rating = 200,
528}; 477};
529 478
530static struct resource tmu0_resources[] = { 479static struct resource tmu0_resources[] = {
531 [0] = { 480 [0] = {
532 .name = "TMU0",
533 .start = 0xffd80008, 481 .start = 0xffd80008,
534 .end = 0xffd80013, 482 .end = 0xffd80013,
535 .flags = IORESOURCE_MEM, 483 .flags = IORESOURCE_MEM,
@@ -554,16 +502,13 @@ static struct platform_device tmu0_device = {
554}; 502};
555 503
556static struct sh_timer_config tmu1_platform_data = { 504static struct sh_timer_config tmu1_platform_data = {
557 .name = "TMU1",
558 .channel_offset = 0x10, 505 .channel_offset = 0x10,
559 .timer_bit = 1, 506 .timer_bit = 1,
560 .clk = "tmu0",
561 .clocksource_rating = 200, 507 .clocksource_rating = 200,
562}; 508};
563 509
564static struct resource tmu1_resources[] = { 510static struct resource tmu1_resources[] = {
565 [0] = { 511 [0] = {
566 .name = "TMU1",
567 .start = 0xffd80014, 512 .start = 0xffd80014,
568 .end = 0xffd8001f, 513 .end = 0xffd8001f,
569 .flags = IORESOURCE_MEM, 514 .flags = IORESOURCE_MEM,
@@ -588,15 +533,12 @@ static struct platform_device tmu1_device = {
588}; 533};
589 534
590static struct sh_timer_config tmu2_platform_data = { 535static struct sh_timer_config tmu2_platform_data = {
591 .name = "TMU2",
592 .channel_offset = 0x1c, 536 .channel_offset = 0x1c,
593 .timer_bit = 2, 537 .timer_bit = 2,
594 .clk = "tmu0",
595}; 538};
596 539
597static struct resource tmu2_resources[] = { 540static struct resource tmu2_resources[] = {
598 [0] = { 541 [0] = {
599 .name = "TMU2",
600 .start = 0xffd80020, 542 .start = 0xffd80020,
601 .end = 0xffd8002b, 543 .end = 0xffd8002b,
602 .flags = IORESOURCE_MEM, 544 .flags = IORESOURCE_MEM,
@@ -622,15 +564,12 @@ static struct platform_device tmu2_device = {
622 564
623 565
624static struct sh_timer_config tmu3_platform_data = { 566static struct sh_timer_config tmu3_platform_data = {
625 .name = "TMU3",
626 .channel_offset = 0x04, 567 .channel_offset = 0x04,
627 .timer_bit = 0, 568 .timer_bit = 0,
628 .clk = "tmu1",
629}; 569};
630 570
631static struct resource tmu3_resources[] = { 571static struct resource tmu3_resources[] = {
632 [0] = { 572 [0] = {
633 .name = "TMU3",
634 .start = 0xffd90008, 573 .start = 0xffd90008,
635 .end = 0xffd90013, 574 .end = 0xffd90013,
636 .flags = IORESOURCE_MEM, 575 .flags = IORESOURCE_MEM,
@@ -655,15 +594,12 @@ static struct platform_device tmu3_device = {
655}; 594};
656 595
657static struct sh_timer_config tmu4_platform_data = { 596static struct sh_timer_config tmu4_platform_data = {
658 .name = "TMU4",
659 .channel_offset = 0x10, 597 .channel_offset = 0x10,
660 .timer_bit = 1, 598 .timer_bit = 1,
661 .clk = "tmu1",
662}; 599};
663 600
664static struct resource tmu4_resources[] = { 601static struct resource tmu4_resources[] = {
665 [0] = { 602 [0] = {
666 .name = "TMU4",
667 .start = 0xffd90014, 603 .start = 0xffd90014,
668 .end = 0xffd9001f, 604 .end = 0xffd9001f,
669 .flags = IORESOURCE_MEM, 605 .flags = IORESOURCE_MEM,
@@ -688,15 +624,12 @@ static struct platform_device tmu4_device = {
688}; 624};
689 625
690static struct sh_timer_config tmu5_platform_data = { 626static struct sh_timer_config tmu5_platform_data = {
691 .name = "TMU5",
692 .channel_offset = 0x1c, 627 .channel_offset = 0x1c,
693 .timer_bit = 2, 628 .timer_bit = 2,
694 .clk = "tmu1",
695}; 629};
696 630
697static struct resource tmu5_resources[] = { 631static struct resource tmu5_resources[] = {
698 [0] = { 632 [0] = {
699 .name = "TMU5",
700 .start = 0xffd90020, 633 .start = 0xffd90020,
701 .end = 0xffd9002b, 634 .end = 0xffd9002b,
702 .flags = IORESOURCE_MEM, 635 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index e75edf58796..444aca95b20 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -63,16 +63,13 @@ static struct platform_device scif4_device = {
63}; 63};
64 64
65static struct sh_timer_config tmu0_platform_data = { 65static struct sh_timer_config tmu0_platform_data = {
66 .name = "TMU0",
67 .channel_offset = 0x04, 66 .channel_offset = 0x04,
68 .timer_bit = 0, 67 .timer_bit = 0,
69 .clk = "peripheral_clk",
70 .clockevent_rating = 200, 68 .clockevent_rating = 200,
71}; 69};
72 70
73static struct resource tmu0_resources[] = { 71static struct resource tmu0_resources[] = {
74 [0] = { 72 [0] = {
75 .name = "TMU0",
76 .start = 0xfe430008, 73 .start = 0xfe430008,
77 .end = 0xfe430013, 74 .end = 0xfe430013,
78 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
@@ -94,16 +91,13 @@ static struct platform_device tmu0_device = {
94}; 91};
95 92
96static struct sh_timer_config tmu1_platform_data = { 93static struct sh_timer_config tmu1_platform_data = {
97 .name = "TMU1",
98 .channel_offset = 0x10, 94 .channel_offset = 0x10,
99 .timer_bit = 1, 95 .timer_bit = 1,
100 .clk = "peripheral_clk",
101 .clocksource_rating = 200, 96 .clocksource_rating = 200,
102}; 97};
103 98
104static struct resource tmu1_resources[] = { 99static struct resource tmu1_resources[] = {
105 [0] = { 100 [0] = {
106 .name = "TMU1",
107 .start = 0xfe430014, 101 .start = 0xfe430014,
108 .end = 0xfe43001f, 102 .end = 0xfe43001f,
109 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 7f6b0a5f7f8..5b5f6b005fc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -131,16 +131,13 @@ static struct platform_device usbf_device = {
131}; 131};
132 132
133static struct sh_timer_config tmu0_platform_data = { 133static struct sh_timer_config tmu0_platform_data = {
134 .name = "TMU0",
135 .channel_offset = 0x04, 134 .channel_offset = 0x04,
136 .timer_bit = 0, 135 .timer_bit = 0,
137 .clk = "peripheral_clk",
138 .clockevent_rating = 200, 136 .clockevent_rating = 200,
139}; 137};
140 138
141static struct resource tmu0_resources[] = { 139static struct resource tmu0_resources[] = {
142 [0] = { 140 [0] = {
143 .name = "TMU0",
144 .start = 0xffd80008, 141 .start = 0xffd80008,
145 .end = 0xffd80013, 142 .end = 0xffd80013,
146 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -162,16 +159,13 @@ static struct platform_device tmu0_device = {
162}; 159};
163 160
164static struct sh_timer_config tmu1_platform_data = { 161static struct sh_timer_config tmu1_platform_data = {
165 .name = "TMU1",
166 .channel_offset = 0x10, 162 .channel_offset = 0x10,
167 .timer_bit = 1, 163 .timer_bit = 1,
168 .clk = "peripheral_clk",
169 .clocksource_rating = 200, 164 .clocksource_rating = 200,
170}; 165};
171 166
172static struct resource tmu1_resources[] = { 167static struct resource tmu1_resources[] = {
173 [0] = { 168 [0] = {
174 .name = "TMU1",
175 .start = 0xffd80014, 169 .start = 0xffd80014,
176 .end = 0xffd8001f, 170 .end = 0xffd8001f,
177 .flags = IORESOURCE_MEM, 171 .flags = IORESOURCE_MEM,
@@ -193,15 +187,12 @@ static struct platform_device tmu1_device = {
193}; 187};
194 188
195static struct sh_timer_config tmu2_platform_data = { 189static struct sh_timer_config tmu2_platform_data = {
196 .name = "TMU2",
197 .channel_offset = 0x1c, 190 .channel_offset = 0x1c,
198 .timer_bit = 2, 191 .timer_bit = 2,
199 .clk = "peripheral_clk",
200}; 192};
201 193
202static struct resource tmu2_resources[] = { 194static struct resource tmu2_resources[] = {
203 [0] = { 195 [0] = {
204 .name = "TMU2",
205 .start = 0xffd80020, 196 .start = 0xffd80020,
206 .end = 0xffd8002f, 197 .end = 0xffd8002f,
207 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
@@ -223,15 +214,12 @@ static struct platform_device tmu2_device = {
223}; 214};
224 215
225static struct sh_timer_config tmu3_platform_data = { 216static struct sh_timer_config tmu3_platform_data = {
226 .name = "TMU3",
227 .channel_offset = 0x04, 217 .channel_offset = 0x04,
228 .timer_bit = 0, 218 .timer_bit = 0,
229 .clk = "peripheral_clk",
230}; 219};
231 220
232static struct resource tmu3_resources[] = { 221static struct resource tmu3_resources[] = {
233 [0] = { 222 [0] = {
234 .name = "TMU3",
235 .start = 0xffd88008, 223 .start = 0xffd88008,
236 .end = 0xffd88013, 224 .end = 0xffd88013,
237 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
@@ -253,15 +241,12 @@ static struct platform_device tmu3_device = {
253}; 241};
254 242
255static struct sh_timer_config tmu4_platform_data = { 243static struct sh_timer_config tmu4_platform_data = {
256 .name = "TMU4",
257 .channel_offset = 0x10, 244 .channel_offset = 0x10,
258 .timer_bit = 1, 245 .timer_bit = 1,
259 .clk = "peripheral_clk",
260}; 246};
261 247
262static struct resource tmu4_resources[] = { 248static struct resource tmu4_resources[] = {
263 [0] = { 249 [0] = {
264 .name = "TMU4",
265 .start = 0xffd88014, 250 .start = 0xffd88014,
266 .end = 0xffd8801f, 251 .end = 0xffd8801f,
267 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
@@ -283,15 +268,12 @@ static struct platform_device tmu4_device = {
283}; 268};
284 269
285static struct sh_timer_config tmu5_platform_data = { 270static struct sh_timer_config tmu5_platform_data = {
286 .name = "TMU5",
287 .channel_offset = 0x1c, 271 .channel_offset = 0x1c,
288 .timer_bit = 2, 272 .timer_bit = 2,
289 .clk = "peripheral_clk",
290}; 273};
291 274
292static struct resource tmu5_resources[] = { 275static struct resource tmu5_resources[] = {
293 [0] = { 276 [0] = {
294 .name = "TMU5",
295 .start = 0xffd88020, 277 .start = 0xffd88020,
296 .end = 0xffd8802b, 278 .end = 0xffd8802b,
297 .flags = IORESOURCE_MEM, 279 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 86d681ecf90..7270d7fd676 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -165,16 +165,13 @@ static struct platform_device scif9_device = {
165}; 165};
166 166
167static struct sh_timer_config tmu0_platform_data = { 167static struct sh_timer_config tmu0_platform_data = {
168 .name = "TMU0",
169 .channel_offset = 0x04, 168 .channel_offset = 0x04,
170 .timer_bit = 0, 169 .timer_bit = 0,
171 .clk = "peripheral_clk",
172 .clockevent_rating = 200, 170 .clockevent_rating = 200,
173}; 171};
174 172
175static struct resource tmu0_resources[] = { 173static struct resource tmu0_resources[] = {
176 [0] = { 174 [0] = {
177 .name = "TMU0",
178 .start = 0xffd80008, 175 .start = 0xffd80008,
179 .end = 0xffd80013, 176 .end = 0xffd80013,
180 .flags = IORESOURCE_MEM, 177 .flags = IORESOURCE_MEM,
@@ -196,16 +193,13 @@ static struct platform_device tmu0_device = {
196}; 193};
197 194
198static struct sh_timer_config tmu1_platform_data = { 195static struct sh_timer_config tmu1_platform_data = {
199 .name = "TMU1",
200 .channel_offset = 0x10, 196 .channel_offset = 0x10,
201 .timer_bit = 1, 197 .timer_bit = 1,
202 .clk = "peripheral_clk",
203 .clocksource_rating = 200, 198 .clocksource_rating = 200,
204}; 199};
205 200
206static struct resource tmu1_resources[] = { 201static struct resource tmu1_resources[] = {
207 [0] = { 202 [0] = {
208 .name = "TMU1",
209 .start = 0xffd80014, 203 .start = 0xffd80014,
210 .end = 0xffd8001f, 204 .end = 0xffd8001f,
211 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
@@ -227,15 +221,12 @@ static struct platform_device tmu1_device = {
227}; 221};
228 222
229static struct sh_timer_config tmu2_platform_data = { 223static struct sh_timer_config tmu2_platform_data = {
230 .name = "TMU2",
231 .channel_offset = 0x1c, 224 .channel_offset = 0x1c,
232 .timer_bit = 2, 225 .timer_bit = 2,
233 .clk = "peripheral_clk",
234}; 226};
235 227
236static struct resource tmu2_resources[] = { 228static struct resource tmu2_resources[] = {
237 [0] = { 229 [0] = {
238 .name = "TMU2",
239 .start = 0xffd80020, 230 .start = 0xffd80020,
240 .end = 0xffd8002f, 231 .end = 0xffd8002f,
241 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
@@ -257,15 +248,12 @@ static struct platform_device tmu2_device = {
257}; 248};
258 249
259static struct sh_timer_config tmu3_platform_data = { 250static struct sh_timer_config tmu3_platform_data = {
260 .name = "TMU3",
261 .channel_offset = 0x04, 251 .channel_offset = 0x04,
262 .timer_bit = 0, 252 .timer_bit = 0,
263 .clk = "peripheral_clk",
264}; 253};
265 254
266static struct resource tmu3_resources[] = { 255static struct resource tmu3_resources[] = {
267 [0] = { 256 [0] = {
268 .name = "TMU3",
269 .start = 0xffd81008, 257 .start = 0xffd81008,
270 .end = 0xffd81013, 258 .end = 0xffd81013,
271 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
@@ -287,15 +275,12 @@ static struct platform_device tmu3_device = {
287}; 275};
288 276
289static struct sh_timer_config tmu4_platform_data = { 277static struct sh_timer_config tmu4_platform_data = {
290 .name = "TMU4",
291 .channel_offset = 0x10, 278 .channel_offset = 0x10,
292 .timer_bit = 1, 279 .timer_bit = 1,
293 .clk = "peripheral_clk",
294}; 280};
295 281
296static struct resource tmu4_resources[] = { 282static struct resource tmu4_resources[] = {
297 [0] = { 283 [0] = {
298 .name = "TMU4",
299 .start = 0xffd81014, 284 .start = 0xffd81014,
300 .end = 0xffd8101f, 285 .end = 0xffd8101f,
301 .flags = IORESOURCE_MEM, 286 .flags = IORESOURCE_MEM,
@@ -317,15 +302,12 @@ static struct platform_device tmu4_device = {
317}; 302};
318 303
319static struct sh_timer_config tmu5_platform_data = { 304static struct sh_timer_config tmu5_platform_data = {
320 .name = "TMU5",
321 .channel_offset = 0x1c, 305 .channel_offset = 0x1c,
322 .timer_bit = 2, 306 .timer_bit = 2,
323 .clk = "peripheral_clk",
324}; 307};
325 308
326static struct resource tmu5_resources[] = { 309static struct resource tmu5_resources[] = {
327 [0] = { 310 [0] = {
328 .name = "TMU5",
329 .start = 0xffd81020, 311 .start = 0xffd81020,
330 .end = 0xffd8102f, 312 .end = 0xffd8102f,
331 .flags = IORESOURCE_MEM, 313 .flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu5_device = {
347}; 329};
348 330
349static struct sh_timer_config tmu6_platform_data = { 331static struct sh_timer_config tmu6_platform_data = {
350 .name = "TMU6",
351 .channel_offset = 0x04, 332 .channel_offset = 0x04,
352 .timer_bit = 0, 333 .timer_bit = 0,
353 .clk = "peripheral_clk",
354}; 334};
355 335
356static struct resource tmu6_resources[] = { 336static struct resource tmu6_resources[] = {
357 [0] = { 337 [0] = {
358 .name = "TMU6",
359 .start = 0xffd82008, 338 .start = 0xffd82008,
360 .end = 0xffd82013, 339 .end = 0xffd82013,
361 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -377,15 +356,12 @@ static struct platform_device tmu6_device = {
377}; 356};
378 357
379static struct sh_timer_config tmu7_platform_data = { 358static struct sh_timer_config tmu7_platform_data = {
380 .name = "TMU7",
381 .channel_offset = 0x10, 359 .channel_offset = 0x10,
382 .timer_bit = 1, 360 .timer_bit = 1,
383 .clk = "peripheral_clk",
384}; 361};
385 362
386static struct resource tmu7_resources[] = { 363static struct resource tmu7_resources[] = {
387 [0] = { 364 [0] = {
388 .name = "TMU7",
389 .start = 0xffd82014, 365 .start = 0xffd82014,
390 .end = 0xffd8201f, 366 .end = 0xffd8201f,
391 .flags = IORESOURCE_MEM, 367 .flags = IORESOURCE_MEM,
@@ -407,15 +383,12 @@ static struct platform_device tmu7_device = {
407}; 383};
408 384
409static struct sh_timer_config tmu8_platform_data = { 385static struct sh_timer_config tmu8_platform_data = {
410 .name = "TMU8",
411 .channel_offset = 0x1c, 386 .channel_offset = 0x1c,
412 .timer_bit = 2, 387 .timer_bit = 2,
413 .clk = "peripheral_clk",
414}; 388};
415 389
416static struct resource tmu8_resources[] = { 390static struct resource tmu8_resources[] = {
417 [0] = { 391 [0] = {
418 .name = "TMU8",
419 .start = 0xffd82020, 392 .start = 0xffd82020,
420 .end = 0xffd8202b, 393 .end = 0xffd8202b,
421 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 02e792c90de..b12f537e4dd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -49,16 +49,13 @@ static struct platform_device scif1_device = {
49}; 49};
50 50
51static struct sh_timer_config tmu0_platform_data = { 51static struct sh_timer_config tmu0_platform_data = {
52 .name = "TMU0",
53 .channel_offset = 0x04, 52 .channel_offset = 0x04,
54 .timer_bit = 0, 53 .timer_bit = 0,
55 .clk = "peripheral_clk",
56 .clockevent_rating = 200, 54 .clockevent_rating = 200,
57}; 55};
58 56
59static struct resource tmu0_resources[] = { 57static struct resource tmu0_resources[] = {
60 [0] = { 58 [0] = {
61 .name = "TMU0",
62 .start = 0xffd80008, 59 .start = 0xffd80008,
63 .end = 0xffd80013, 60 .end = 0xffd80013,
64 .flags = IORESOURCE_MEM, 61 .flags = IORESOURCE_MEM,
@@ -80,16 +77,13 @@ static struct platform_device tmu0_device = {
80}; 77};
81 78
82static struct sh_timer_config tmu1_platform_data = { 79static struct sh_timer_config tmu1_platform_data = {
83 .name = "TMU1",
84 .channel_offset = 0x10, 80 .channel_offset = 0x10,
85 .timer_bit = 1, 81 .timer_bit = 1,
86 .clk = "peripheral_clk",
87 .clocksource_rating = 200, 82 .clocksource_rating = 200,
88}; 83};
89 84
90static struct resource tmu1_resources[] = { 85static struct resource tmu1_resources[] = {
91 [0] = { 86 [0] = {
92 .name = "TMU1",
93 .start = 0xffd80014, 87 .start = 0xffd80014,
94 .end = 0xffd8001f, 88 .end = 0xffd8001f,
95 .flags = IORESOURCE_MEM, 89 .flags = IORESOURCE_MEM,
@@ -111,15 +105,12 @@ static struct platform_device tmu1_device = {
111}; 105};
112 106
113static struct sh_timer_config tmu2_platform_data = { 107static struct sh_timer_config tmu2_platform_data = {
114 .name = "TMU2",
115 .channel_offset = 0x1c, 108 .channel_offset = 0x1c,
116 .timer_bit = 2, 109 .timer_bit = 2,
117 .clk = "peripheral_clk",
118}; 110};
119 111
120static struct resource tmu2_resources[] = { 112static struct resource tmu2_resources[] = {
121 [0] = { 113 [0] = {
122 .name = "TMU2",
123 .start = 0xffd80020, 114 .start = 0xffd80020,
124 .end = 0xffd8002f, 115 .end = 0xffd8002f,
125 .flags = IORESOURCE_MEM, 116 .flags = IORESOURCE_MEM,
@@ -141,15 +132,12 @@ static struct platform_device tmu2_device = {
141}; 132};
142 133
143static struct sh_timer_config tmu3_platform_data = { 134static struct sh_timer_config tmu3_platform_data = {
144 .name = "TMU3",
145 .channel_offset = 0x04, 135 .channel_offset = 0x04,
146 .timer_bit = 0, 136 .timer_bit = 0,
147 .clk = "peripheral_clk",
148}; 137};
149 138
150static struct resource tmu3_resources[] = { 139static struct resource tmu3_resources[] = {
151 [0] = { 140 [0] = {
152 .name = "TMU3",
153 .start = 0xffdc0008, 141 .start = 0xffdc0008,
154 .end = 0xffdc0013, 142 .end = 0xffdc0013,
155 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -171,15 +159,12 @@ static struct platform_device tmu3_device = {
171}; 159};
172 160
173static struct sh_timer_config tmu4_platform_data = { 161static struct sh_timer_config tmu4_platform_data = {
174 .name = "TMU4",
175 .channel_offset = 0x10, 162 .channel_offset = 0x10,
176 .timer_bit = 1, 163 .timer_bit = 1,
177 .clk = "peripheral_clk",
178}; 164};
179 165
180static struct resource tmu4_resources[] = { 166static struct resource tmu4_resources[] = {
181 [0] = { 167 [0] = {
182 .name = "TMU4",
183 .start = 0xffdc0014, 168 .start = 0xffdc0014,
184 .end = 0xffdc001f, 169 .end = 0xffdc001f,
185 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
@@ -201,15 +186,12 @@ static struct platform_device tmu4_device = {
201}; 186};
202 187
203static struct sh_timer_config tmu5_platform_data = { 188static struct sh_timer_config tmu5_platform_data = {
204 .name = "TMU5",
205 .channel_offset = 0x1c, 189 .channel_offset = 0x1c,
206 .timer_bit = 2, 190 .timer_bit = 2,
207 .clk = "peripheral_clk",
208}; 191};
209 192
210static struct resource tmu5_resources[] = { 193static struct resource tmu5_resources[] = {
211 [0] = { 194 [0] = {
212 .name = "TMU5",
213 .start = 0xffdc0020, 195 .start = 0xffdc0020,
214 .end = 0xffdc002b, 196 .end = 0xffdc002b,
215 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -251,7 +233,7 @@ static struct platform_device rtc_device = {
251}; 233};
252 234
253/* DMA */ 235/* DMA */
254static struct sh_dmae_channel sh7780_dmae0_channels[] = { 236static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
255 { 237 {
256 .offset = 0, 238 .offset = 0,
257 .dmars = 0, 239 .dmars = 0,
@@ -279,7 +261,7 @@ static struct sh_dmae_channel sh7780_dmae0_channels[] = {
279 } 261 }
280}; 262};
281 263
282static struct sh_dmae_channel sh7780_dmae1_channels[] = { 264static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
283 { 265 {
284 .offset = 0, 266 .offset = 0,
285 }, { 267 }, {
@@ -295,7 +277,7 @@ static struct sh_dmae_channel sh7780_dmae1_channels[] = {
295 } 277 }
296}; 278};
297 279
298static unsigned int ts_shift[] = TS_SHIFT; 280static const unsigned int ts_shift[] = TS_SHIFT;
299 281
300static struct sh_dmae_pdata dma0_platform_data = { 282static struct sh_dmae_pdata dma0_platform_data = {
301 .channel = sh7780_dmae0_channels, 283 .channel = sh7780_dmae0_channels,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 1fcd88b1671..f3e3ea0ce05 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = {
25 .flags = UPF_BOOT_AUTOCONF, 25 .flags = UPF_BOOT_AUTOCONF,
26 .type = PORT_SCIF, 26 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 27 .irqs = { 40, 40, 40, 40 },
28 .clk = "scif_fck",
29}; 28};
30 29
31static struct platform_device scif0_device = { 30static struct platform_device scif0_device = {
@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = {
41 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF, 41 .type = PORT_SCIF,
43 .irqs = { 44, 44, 44, 44 }, 42 .irqs = { 44, 44, 44, 44 },
44 .clk = "scif_fck",
45}; 43};
46 44
47static struct platform_device scif1_device = { 45static struct platform_device scif1_device = {
@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = {
57 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF, 56 .type = PORT_SCIF,
59 .irqs = { 60, 60, 60, 60 }, 57 .irqs = { 60, 60, 60, 60 },
60 .clk = "scif_fck",
61}; 58};
62 59
63static struct platform_device scif2_device = { 60static struct platform_device scif2_device = {
@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = {
73 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
74 .type = PORT_SCIF, 71 .type = PORT_SCIF,
75 .irqs = { 61, 61, 61, 61 }, 72 .irqs = { 61, 61, 61, 61 },
76 .clk = "scif_fck",
77}; 73};
78 74
79static struct platform_device scif3_device = { 75static struct platform_device scif3_device = {
@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = {
89 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
90 .type = PORT_SCIF, 86 .type = PORT_SCIF,
91 .irqs = { 62, 62, 62, 62 }, 87 .irqs = { 62, 62, 62, 62 },
92 .clk = "scif_fck",
93}; 88};
94 89
95static struct platform_device scif4_device = { 90static struct platform_device scif4_device = {
@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = {
105 .flags = UPF_BOOT_AUTOCONF, 100 .flags = UPF_BOOT_AUTOCONF,
106 .type = PORT_SCIF, 101 .type = PORT_SCIF,
107 .irqs = { 63, 63, 63, 63 }, 102 .irqs = { 63, 63, 63, 63 },
108 .clk = "scif_fck",
109}; 103};
110 104
111static struct platform_device scif5_device = { 105static struct platform_device scif5_device = {
@@ -117,16 +111,13 @@ static struct platform_device scif5_device = {
117}; 111};
118 112
119static struct sh_timer_config tmu0_platform_data = { 113static struct sh_timer_config tmu0_platform_data = {
120 .name = "TMU0",
121 .channel_offset = 0x04, 114 .channel_offset = 0x04,
122 .timer_bit = 0, 115 .timer_bit = 0,
123 .clk = "tmu012_fck",
124 .clockevent_rating = 200, 116 .clockevent_rating = 200,
125}; 117};
126 118
127static struct resource tmu0_resources[] = { 119static struct resource tmu0_resources[] = {
128 [0] = { 120 [0] = {
129 .name = "TMU0",
130 .start = 0xffd80008, 121 .start = 0xffd80008,
131 .end = 0xffd80013, 122 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
@@ -148,16 +139,13 @@ static struct platform_device tmu0_device = {
148}; 139};
149 140
150static struct sh_timer_config tmu1_platform_data = { 141static struct sh_timer_config tmu1_platform_data = {
151 .name = "TMU1",
152 .channel_offset = 0x10, 142 .channel_offset = 0x10,
153 .timer_bit = 1, 143 .timer_bit = 1,
154 .clk = "tmu012_fck",
155 .clocksource_rating = 200, 144 .clocksource_rating = 200,
156}; 145};
157 146
158static struct resource tmu1_resources[] = { 147static struct resource tmu1_resources[] = {
159 [0] = { 148 [0] = {
160 .name = "TMU1",
161 .start = 0xffd80014, 149 .start = 0xffd80014,
162 .end = 0xffd8001f, 150 .end = 0xffd8001f,
163 .flags = IORESOURCE_MEM, 151 .flags = IORESOURCE_MEM,
@@ -179,15 +167,12 @@ static struct platform_device tmu1_device = {
179}; 167};
180 168
181static struct sh_timer_config tmu2_platform_data = { 169static struct sh_timer_config tmu2_platform_data = {
182 .name = "TMU2",
183 .channel_offset = 0x1c, 170 .channel_offset = 0x1c,
184 .timer_bit = 2, 171 .timer_bit = 2,
185 .clk = "tmu012_fck",
186}; 172};
187 173
188static struct resource tmu2_resources[] = { 174static struct resource tmu2_resources[] = {
189 [0] = { 175 [0] = {
190 .name = "TMU2",
191 .start = 0xffd80020, 176 .start = 0xffd80020,
192 .end = 0xffd8002f, 177 .end = 0xffd8002f,
193 .flags = IORESOURCE_MEM, 178 .flags = IORESOURCE_MEM,
@@ -209,15 +194,12 @@ static struct platform_device tmu2_device = {
209}; 194};
210 195
211static struct sh_timer_config tmu3_platform_data = { 196static struct sh_timer_config tmu3_platform_data = {
212 .name = "TMU3",
213 .channel_offset = 0x04, 197 .channel_offset = 0x04,
214 .timer_bit = 0, 198 .timer_bit = 0,
215 .clk = "tmu345_fck",
216}; 199};
217 200
218static struct resource tmu3_resources[] = { 201static struct resource tmu3_resources[] = {
219 [0] = { 202 [0] = {
220 .name = "TMU3",
221 .start = 0xffdc0008, 203 .start = 0xffdc0008,
222 .end = 0xffdc0013, 204 .end = 0xffdc0013,
223 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
@@ -239,15 +221,12 @@ static struct platform_device tmu3_device = {
239}; 221};
240 222
241static struct sh_timer_config tmu4_platform_data = { 223static struct sh_timer_config tmu4_platform_data = {
242 .name = "TMU4",
243 .channel_offset = 0x10, 224 .channel_offset = 0x10,
244 .timer_bit = 1, 225 .timer_bit = 1,
245 .clk = "tmu345_fck",
246}; 226};
247 227
248static struct resource tmu4_resources[] = { 228static struct resource tmu4_resources[] = {
249 [0] = { 229 [0] = {
250 .name = "TMU4",
251 .start = 0xffdc0014, 230 .start = 0xffdc0014,
252 .end = 0xffdc001f, 231 .end = 0xffdc001f,
253 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
@@ -269,15 +248,12 @@ static struct platform_device tmu4_device = {
269}; 248};
270 249
271static struct sh_timer_config tmu5_platform_data = { 250static struct sh_timer_config tmu5_platform_data = {
272 .name = "TMU5",
273 .channel_offset = 0x1c, 251 .channel_offset = 0x1c,
274 .timer_bit = 2, 252 .timer_bit = 2,
275 .clk = "tmu345_fck",
276}; 253};
277 254
278static struct resource tmu5_resources[] = { 255static struct resource tmu5_resources[] = {
279 [0] = { 256 [0] = {
280 .name = "TMU5",
281 .start = 0xffdc0020, 257 .start = 0xffdc0020,
282 .end = 0xffdc002b, 258 .end = 0xffdc002b,
283 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
@@ -299,7 +275,7 @@ static struct platform_device tmu5_device = {
299}; 275};
300 276
301/* DMA */ 277/* DMA */
302static struct sh_dmae_channel sh7785_dmae0_channels[] = { 278static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
303 { 279 {
304 .offset = 0, 280 .offset = 0,
305 .dmars = 0, 281 .dmars = 0,
@@ -327,7 +303,7 @@ static struct sh_dmae_channel sh7785_dmae0_channels[] = {
327 } 303 }
328}; 304};
329 305
330static struct sh_dmae_channel sh7785_dmae1_channels[] = { 306static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
331 { 307 {
332 .offset = 0, 308 .offset = 0,
333 }, { 309 }, {
@@ -343,7 +319,7 @@ static struct sh_dmae_channel sh7785_dmae1_channels[] = {
343 } 319 }
344}; 320};
345 321
346static unsigned int ts_shift[] = TS_SHIFT; 322static const unsigned int ts_shift[] = TS_SHIFT;
347 323
348static struct sh_dmae_pdata dma0_platform_data = { 324static struct sh_dmae_pdata dma0_platform_data = {
349 .channel = sh7785_dmae0_channels, 325 .channel = sh7785_dmae0_channels,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 7e585320710..81657091da4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7786 Setup 2 * SH7786 Setup
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com> 6 * Paul Mundt <paul.mundt@renesas.com>
7 * 7 *
@@ -21,7 +21,10 @@
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h> 23#include <linux/sh_timer.h>
24#include <linux/sh_intc.h>
25#include <cpu/dma-register.h>
24#include <asm/mmzone.h> 26#include <asm/mmzone.h>
27#include <asm/dmaengine.h>
25 28
26static struct plat_sci_port scif0_platform_data = { 29static struct plat_sci_port scif0_platform_data = {
27 .mapbase = 0xffea0000, 30 .mapbase = 0xffea0000,
@@ -117,16 +120,13 @@ static struct platform_device scif5_device = {
117}; 120};
118 121
119static struct sh_timer_config tmu0_platform_data = { 122static struct sh_timer_config tmu0_platform_data = {
120 .name = "TMU0",
121 .channel_offset = 0x04, 123 .channel_offset = 0x04,
122 .timer_bit = 0, 124 .timer_bit = 0,
123 .clk = "peripheral_clk",
124 .clockevent_rating = 200, 125 .clockevent_rating = 200,
125}; 126};
126 127
127static struct resource tmu0_resources[] = { 128static struct resource tmu0_resources[] = {
128 [0] = { 129 [0] = {
129 .name = "TMU0",
130 .start = 0xffd80008, 130 .start = 0xffd80008,
131 .end = 0xffd80013, 131 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM, 132 .flags = IORESOURCE_MEM,
@@ -148,16 +148,13 @@ static struct platform_device tmu0_device = {
148}; 148};
149 149
150static struct sh_timer_config tmu1_platform_data = { 150static struct sh_timer_config tmu1_platform_data = {
151 .name = "TMU1",
152 .channel_offset = 0x10, 151 .channel_offset = 0x10,
153 .timer_bit = 1, 152 .timer_bit = 1,
154 .clk = "peripheral_clk",
155 .clocksource_rating = 200, 153 .clocksource_rating = 200,
156}; 154};
157 155
158static struct resource tmu1_resources[] = { 156static struct resource tmu1_resources[] = {
159 [0] = { 157 [0] = {
160 .name = "TMU1",
161 .start = 0xffd80014, 158 .start = 0xffd80014,
162 .end = 0xffd8001f, 159 .end = 0xffd8001f,
163 .flags = IORESOURCE_MEM, 160 .flags = IORESOURCE_MEM,
@@ -179,15 +176,12 @@ static struct platform_device tmu1_device = {
179}; 176};
180 177
181static struct sh_timer_config tmu2_platform_data = { 178static struct sh_timer_config tmu2_platform_data = {
182 .name = "TMU2",
183 .channel_offset = 0x1c, 179 .channel_offset = 0x1c,
184 .timer_bit = 2, 180 .timer_bit = 2,
185 .clk = "peripheral_clk",
186}; 181};
187 182
188static struct resource tmu2_resources[] = { 183static struct resource tmu2_resources[] = {
189 [0] = { 184 [0] = {
190 .name = "TMU2",
191 .start = 0xffd80020, 185 .start = 0xffd80020,
192 .end = 0xffd8002f, 186 .end = 0xffd8002f,
193 .flags = IORESOURCE_MEM, 187 .flags = IORESOURCE_MEM,
@@ -209,15 +203,12 @@ static struct platform_device tmu2_device = {
209}; 203};
210 204
211static struct sh_timer_config tmu3_platform_data = { 205static struct sh_timer_config tmu3_platform_data = {
212 .name = "TMU3",
213 .channel_offset = 0x04, 206 .channel_offset = 0x04,
214 .timer_bit = 0, 207 .timer_bit = 0,
215 .clk = "peripheral_clk",
216}; 208};
217 209
218static struct resource tmu3_resources[] = { 210static struct resource tmu3_resources[] = {
219 [0] = { 211 [0] = {
220 .name = "TMU3",
221 .start = 0xffda0008, 212 .start = 0xffda0008,
222 .end = 0xffda0013, 213 .end = 0xffda0013,
223 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
@@ -239,15 +230,12 @@ static struct platform_device tmu3_device = {
239}; 230};
240 231
241static struct sh_timer_config tmu4_platform_data = { 232static struct sh_timer_config tmu4_platform_data = {
242 .name = "TMU4",
243 .channel_offset = 0x10, 233 .channel_offset = 0x10,
244 .timer_bit = 1, 234 .timer_bit = 1,
245 .clk = "peripheral_clk",
246}; 235};
247 236
248static struct resource tmu4_resources[] = { 237static struct resource tmu4_resources[] = {
249 [0] = { 238 [0] = {
250 .name = "TMU4",
251 .start = 0xffda0014, 239 .start = 0xffda0014,
252 .end = 0xffda001f, 240 .end = 0xffda001f,
253 .flags = IORESOURCE_MEM, 241 .flags = IORESOURCE_MEM,
@@ -269,15 +257,12 @@ static struct platform_device tmu4_device = {
269}; 257};
270 258
271static struct sh_timer_config tmu5_platform_data = { 259static struct sh_timer_config tmu5_platform_data = {
272 .name = "TMU5",
273 .channel_offset = 0x1c, 260 .channel_offset = 0x1c,
274 .timer_bit = 2, 261 .timer_bit = 2,
275 .clk = "peripheral_clk",
276}; 262};
277 263
278static struct resource tmu5_resources[] = { 264static struct resource tmu5_resources[] = {
279 [0] = { 265 [0] = {
280 .name = "TMU5",
281 .start = 0xffda0020, 266 .start = 0xffda0020,
282 .end = 0xffda002b, 267 .end = 0xffda002b,
283 .flags = IORESOURCE_MEM, 268 .flags = IORESOURCE_MEM,
@@ -299,15 +284,12 @@ static struct platform_device tmu5_device = {
299}; 284};
300 285
301static struct sh_timer_config tmu6_platform_data = { 286static struct sh_timer_config tmu6_platform_data = {
302 .name = "TMU6",
303 .channel_offset = 0x04, 287 .channel_offset = 0x04,
304 .timer_bit = 0, 288 .timer_bit = 0,
305 .clk = "peripheral_clk",
306}; 289};
307 290
308static struct resource tmu6_resources[] = { 291static struct resource tmu6_resources[] = {
309 [0] = { 292 [0] = {
310 .name = "TMU6",
311 .start = 0xffdc0008, 293 .start = 0xffdc0008,
312 .end = 0xffdc0013, 294 .end = 0xffdc0013,
313 .flags = IORESOURCE_MEM, 295 .flags = IORESOURCE_MEM,
@@ -329,15 +311,12 @@ static struct platform_device tmu6_device = {
329}; 311};
330 312
331static struct sh_timer_config tmu7_platform_data = { 313static struct sh_timer_config tmu7_platform_data = {
332 .name = "TMU7",
333 .channel_offset = 0x10, 314 .channel_offset = 0x10,
334 .timer_bit = 1, 315 .timer_bit = 1,
335 .clk = "peripheral_clk",
336}; 316};
337 317
338static struct resource tmu7_resources[] = { 318static struct resource tmu7_resources[] = {
339 [0] = { 319 [0] = {
340 .name = "TMU7",
341 .start = 0xffdc0014, 320 .start = 0xffdc0014,
342 .end = 0xffdc001f, 321 .end = 0xffdc001f,
343 .flags = IORESOURCE_MEM, 322 .flags = IORESOURCE_MEM,
@@ -359,15 +338,12 @@ static struct platform_device tmu7_device = {
359}; 338};
360 339
361static struct sh_timer_config tmu8_platform_data = { 340static struct sh_timer_config tmu8_platform_data = {
362 .name = "TMU8",
363 .channel_offset = 0x1c, 341 .channel_offset = 0x1c,
364 .timer_bit = 2, 342 .timer_bit = 2,
365 .clk = "peripheral_clk",
366}; 343};
367 344
368static struct resource tmu8_resources[] = { 345static struct resource tmu8_resources[] = {
369 [0] = { 346 [0] = {
370 .name = "TMU8",
371 .start = 0xffdc0020, 347 .start = 0xffdc0020,
372 .end = 0xffdc002b, 348 .end = 0xffdc002b,
373 .flags = IORESOURCE_MEM, 349 .flags = IORESOURCE_MEM,
@@ -389,15 +365,12 @@ static struct platform_device tmu8_device = {
389}; 365};
390 366
391static struct sh_timer_config tmu9_platform_data = { 367static struct sh_timer_config tmu9_platform_data = {
392 .name = "TMU9",
393 .channel_offset = 0x04, 368 .channel_offset = 0x04,
394 .timer_bit = 0, 369 .timer_bit = 0,
395 .clk = "peripheral_clk",
396}; 370};
397 371
398static struct resource tmu9_resources[] = { 372static struct resource tmu9_resources[] = {
399 [0] = { 373 [0] = {
400 .name = "TMU9",
401 .start = 0xffde0008, 374 .start = 0xffde0008,
402 .end = 0xffde0013, 375 .end = 0xffde0013,
403 .flags = IORESOURCE_MEM, 376 .flags = IORESOURCE_MEM,
@@ -419,15 +392,12 @@ static struct platform_device tmu9_device = {
419}; 392};
420 393
421static struct sh_timer_config tmu10_platform_data = { 394static struct sh_timer_config tmu10_platform_data = {
422 .name = "TMU10",
423 .channel_offset = 0x10, 395 .channel_offset = 0x10,
424 .timer_bit = 1, 396 .timer_bit = 1,
425 .clk = "peripheral_clk",
426}; 397};
427 398
428static struct resource tmu10_resources[] = { 399static struct resource tmu10_resources[] = {
429 [0] = { 400 [0] = {
430 .name = "TMU10",
431 .start = 0xffde0014, 401 .start = 0xffde0014,
432 .end = 0xffde001f, 402 .end = 0xffde001f,
433 .flags = IORESOURCE_MEM, 403 .flags = IORESOURCE_MEM,
@@ -449,15 +419,12 @@ static struct platform_device tmu10_device = {
449}; 419};
450 420
451static struct sh_timer_config tmu11_platform_data = { 421static struct sh_timer_config tmu11_platform_data = {
452 .name = "TMU11",
453 .channel_offset = 0x1c, 422 .channel_offset = 0x1c,
454 .timer_bit = 2, 423 .timer_bit = 2,
455 .clk = "peripheral_clk",
456}; 424};
457 425
458static struct resource tmu11_resources[] = { 426static struct resource tmu11_resources[] = {
459 [0] = { 427 [0] = {
460 .name = "TMU11",
461 .start = 0xffde0020, 428 .start = 0xffde0020,
462 .end = 0xffde002b, 429 .end = 0xffde002b,
463 .flags = IORESOURCE_MEM, 430 .flags = IORESOURCE_MEM,
@@ -478,6 +445,83 @@ static struct platform_device tmu11_device = {
478 .num_resources = ARRAY_SIZE(tmu11_resources), 445 .num_resources = ARRAY_SIZE(tmu11_resources),
479}; 446};
480 447
448static const struct sh_dmae_channel dmac0_channels[] = {
449 {
450 .offset = 0,
451 .dmars = 0,
452 .dmars_bit = 0,
453 }, {
454 .offset = 0x10,
455 .dmars = 0,
456 .dmars_bit = 8,
457 }, {
458 .offset = 0x20,
459 .dmars = 4,
460 .dmars_bit = 0,
461 }, {
462 .offset = 0x30,
463 .dmars = 4,
464 .dmars_bit = 8,
465 }, {
466 .offset = 0x50,
467 .dmars = 8,
468 .dmars_bit = 0,
469 }, {
470 .offset = 0x60,
471 .dmars = 8,
472 .dmars_bit = 8,
473 }
474};
475
476static const unsigned int ts_shift[] = TS_SHIFT;
477
478static struct sh_dmae_pdata dma0_platform_data = {
479 .channel = dmac0_channels,
480 .channel_num = ARRAY_SIZE(dmac0_channels),
481 .ts_low_shift = CHCR_TS_LOW_SHIFT,
482 .ts_low_mask = CHCR_TS_LOW_MASK,
483 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
484 .ts_high_mask = CHCR_TS_HIGH_MASK,
485 .ts_shift = ts_shift,
486 .ts_shift_num = ARRAY_SIZE(ts_shift),
487 .dmaor_init = DMAOR_INIT,
488};
489
490/* Resource order important! */
491static struct resource dmac0_resources[] = {
492 {
493 /* Channel registers and DMAOR */
494 .start = 0xfe008020,
495 .end = 0xfe00808f,
496 .flags = IORESOURCE_MEM,
497 }, {
498 /* DMARSx */
499 .start = 0xfe009000,
500 .end = 0xfe00900b,
501 .flags = IORESOURCE_MEM,
502 }, {
503 /* DMA error IRQ */
504 .start = evt2irq(0x5c0),
505 .end = evt2irq(0x5c0),
506 .flags = IORESOURCE_IRQ,
507 }, {
508 /* IRQ for channels 0-5 */
509 .start = evt2irq(0x500),
510 .end = evt2irq(0x5a0),
511 .flags = IORESOURCE_IRQ,
512 },
513};
514
515static struct platform_device dma0_device = {
516 .name = "sh-dma-engine",
517 .id = 0,
518 .resource = dmac0_resources,
519 .num_resources = ARRAY_SIZE(dmac0_resources),
520 .dev = {
521 .platform_data = &dma0_platform_data,
522 },
523};
524
481static struct resource usb_ohci_resources[] = { 525static struct resource usb_ohci_resources[] = {
482 [0] = { 526 [0] = {
483 .start = 0xffe70400, 527 .start = 0xffe70400,
@@ -525,10 +569,10 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
525}; 569};
526 570
527static struct platform_device *sh7786_devices[] __initdata = { 571static struct platform_device *sh7786_devices[] __initdata = {
572 &dma0_device,
528 &usb_ohci_device, 573 &usb_ohci_device,
529}; 574};
530 575
531
532/* 576/*
533 * Please call this function if your platform board 577 * Please call this function if your platform board
534 * use external clock for USB 578 * use external clock for USB
@@ -536,6 +580,7 @@ static struct platform_device *sh7786_devices[] __initdata = {
536#define USBCTL0 0xffe70858 580#define USBCTL0 0xffe70858
537#define CLOCK_MODE_MASK 0xffffff7f 581#define CLOCK_MODE_MASK 0xffffff7f
538#define EXT_CLOCK_MODE 0x00000080 582#define EXT_CLOCK_MODE 0x00000080
583
539void __init sh7786_usb_use_exclock(void) 584void __init sh7786_usb_use_exclock(void)
540{ 585{
541 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; 586 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
@@ -553,6 +598,7 @@ void __init sh7786_usb_use_exclock(void)
553#define PLL_ENB 0x00000002 598#define PLL_ENB 0x00000002
554#define PHY_RST 0x00000004 599#define PHY_RST 0x00000004
555#define ACT_PLL_STATUS 0xc0000000 600#define ACT_PLL_STATUS 0xc0000000
601
556static void __init sh7786_usb_setup(void) 602static void __init sh7786_usb_setup(void)
557{ 603{
558 int i = 1000000; 604 int i = 1000000;
@@ -708,9 +754,19 @@ static struct intc_vect vectors[] __initdata = {
708#define INTMSK2 0xfe410068 754#define INTMSK2 0xfe410068
709#define INTMSKCLR2 0xfe41006c 755#define INTMSKCLR2 0xfe41006c
710 756
757#define INTDISTCR0 0xfe4100b0
758#define INTDISTCR1 0xfe4100b4
759#define INTACK 0xfe4100b8
760#define INTACKCLR 0xfe4100bc
761#define INT2DISTCR0 0xfe410900
762#define INT2DISTCR1 0xfe410904
763#define INT2DISTCR2 0xfe410908
764#define INT2DISTCR3 0xfe41090c
765
711static struct intc_mask_reg mask_registers[] __initdata = { 766static struct intc_mask_reg mask_registers[] __initdata = {
712 { CnINTMSK0, CnINTMSKCLR0, 32, 767 { CnINTMSK0, CnINTMSKCLR0, 32,
713 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 768 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
769 INTC_SMP_BALANCING(INTDISTCR0) },
714 { INTMSK2, INTMSKCLR2, 32, 770 { INTMSK2, INTMSKCLR2, 32,
715 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 771 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
716 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 772 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
@@ -722,7 +778,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
722 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 778 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
723 { CnINT2MSKR0, CnINT2MSKCR0 , 32, 779 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
724 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 780 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
725 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } }, 781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
782 INTC_SMP_BALANCING(INT2DISTCR0) },
726 { CnINT2MSKR1, CnINT2MSKCR1, 32, 783 { CnINT2MSKR1, CnINT2MSKCR1, 32,
727 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, 784 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
728 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, 785 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
@@ -731,14 +788,14 @@ static struct intc_mask_reg mask_registers[] __initdata = {
731 HPB_0, HPB_1, HPB_2, 788 HPB_0, HPB_1, HPB_2,
732 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, 789 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
733 SCIF1, 790 SCIF1,
734 TMU2, TMU3, 0, } }, 791 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
735 { CnINT2MSKR2, CnINT2MSKCR2, 32, 792 { CnINT2MSKR2, CnINT2MSKCR2, 32,
736 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, 793 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
737 Eth_0, Eth_1, 794 Eth_0, Eth_1,
738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 795 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
739 PCIeC0_0, PCIeC0_1, PCIeC0_2, 796 PCIeC0_0, PCIeC0_1, PCIeC0_2,
740 PCIeC1_0, PCIeC1_1, PCIeC1_2, 797 PCIeC1_0, PCIeC1_1, PCIeC1_2,
741 USB, 0, 0 } }, 798 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
742 { CnINT2MSKR3, CnINT2MSKCR3, 32, 799 { CnINT2MSKR3, CnINT2MSKCR3, 32,
743 { 0, 0, 0, 0, 0, 0, 800 { 0, 0, 0, 0, 0, 0,
744 I2C0, I2C1, 801 I2C0, I2C1,
@@ -747,7 +804,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
747 HAC0, HAC1, 804 HAC0, HAC1,
748 FLCTL, 0, 805 FLCTL, 0,
749 HSPI, GPIO0, GPIO1, Thermal, 806 HSPI, GPIO0, GPIO1, Thermal,
750 0, 0, 0, 0, 0, 0, 0, 0 } }, 807 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
751}; 808};
752 809
753static struct intc_prio_reg prio_registers[] __initdata = { 810static struct intc_prio_reg prio_registers[] __initdata = {
@@ -863,6 +920,19 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
863#define INTC_INTMSK2 INTMSK2 920#define INTC_INTMSK2 INTMSK2
864#define INTC_INTMSKCLR1 CnINTMSKCLR1 921#define INTC_INTMSKCLR1 CnINTMSKCLR1
865#define INTC_INTMSKCLR2 INTMSKCLR2 922#define INTC_INTMSKCLR2 INTMSKCLR2
923#define INTC_USERIMASK 0xfe411000
924
925#ifdef CONFIG_INTC_BALANCING
926unsigned int irq_lookup(unsigned int irq)
927{
928 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
929}
930
931void irq_finish(unsigned int irq)
932{
933 __raw_writel(irq2evt(irq), INTACKCLR);
934}
935#endif
866 936
867void __init plat_irq_setup(void) 937void __init plat_irq_setup(void)
868{ 938{
@@ -877,6 +947,7 @@ void __init plat_irq_setup(void)
877 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 947 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
878 948
879 register_intc_controller(&intc_desc); 949 register_intc_controller(&intc_desc);
950 register_intc_userimask(INTC_USERIMASK);
880} 951}
881 952
882void __init plat_irq_setup_pins(int mode) 953void __init plat_irq_setup_pins(int mode)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 780ba17a559..9158bc5ea38 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -70,16 +70,13 @@ static struct platform_device scif2_device = {
70}; 70};
71 71
72static struct sh_timer_config tmu0_platform_data = { 72static struct sh_timer_config tmu0_platform_data = {
73 .name = "TMU0",
74 .channel_offset = 0x04, 73 .channel_offset = 0x04,
75 .timer_bit = 0, 74 .timer_bit = 0,
76 .clk = "peripheral_clk",
77 .clockevent_rating = 200, 75 .clockevent_rating = 200,
78}; 76};
79 77
80static struct resource tmu0_resources[] = { 78static struct resource tmu0_resources[] = {
81 [0] = { 79 [0] = {
82 .name = "TMU0",
83 .start = 0xffc10008, 80 .start = 0xffc10008,
84 .end = 0xffc10013, 81 .end = 0xffc10013,
85 .flags = IORESOURCE_MEM, 82 .flags = IORESOURCE_MEM,
@@ -101,16 +98,13 @@ static struct platform_device tmu0_device = {
101}; 98};
102 99
103static struct sh_timer_config tmu1_platform_data = { 100static struct sh_timer_config tmu1_platform_data = {
104 .name = "TMU1",
105 .channel_offset = 0x10, 101 .channel_offset = 0x10,
106 .timer_bit = 1, 102 .timer_bit = 1,
107 .clk = "peripheral_clk",
108 .clocksource_rating = 200, 103 .clocksource_rating = 200,
109}; 104};
110 105
111static struct resource tmu1_resources[] = { 106static struct resource tmu1_resources[] = {
112 [0] = { 107 [0] = {
113 .name = "TMU1",
114 .start = 0xffc10014, 108 .start = 0xffc10014,
115 .end = 0xffc1001f, 109 .end = 0xffc1001f,
116 .flags = IORESOURCE_MEM, 110 .flags = IORESOURCE_MEM,
@@ -132,15 +126,12 @@ static struct platform_device tmu1_device = {
132}; 126};
133 127
134static struct sh_timer_config tmu2_platform_data = { 128static struct sh_timer_config tmu2_platform_data = {
135 .name = "TMU2",
136 .channel_offset = 0x1c, 129 .channel_offset = 0x1c,
137 .timer_bit = 2, 130 .timer_bit = 2,
138 .clk = "peripheral_clk",
139}; 131};
140 132
141static struct resource tmu2_resources[] = { 133static struct resource tmu2_resources[] = {
142 [0] = { 134 [0] = {
143 .name = "TMU2",
144 .start = 0xffc10020, 135 .start = 0xffc10020,
145 .end = 0xffc1002f, 136 .end = 0xffc1002f,
146 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
@@ -162,15 +153,12 @@ static struct platform_device tmu2_device = {
162}; 153};
163 154
164static struct sh_timer_config tmu3_platform_data = { 155static struct sh_timer_config tmu3_platform_data = {
165 .name = "TMU3",
166 .channel_offset = 0x04, 156 .channel_offset = 0x04,
167 .timer_bit = 0, 157 .timer_bit = 0,
168 .clk = "peripheral_clk",
169}; 158};
170 159
171static struct resource tmu3_resources[] = { 160static struct resource tmu3_resources[] = {
172 [0] = { 161 [0] = {
173 .name = "TMU3",
174 .start = 0xffc20008, 162 .start = 0xffc20008,
175 .end = 0xffc20013, 163 .end = 0xffc20013,
176 .flags = IORESOURCE_MEM, 164 .flags = IORESOURCE_MEM,
@@ -192,15 +180,12 @@ static struct platform_device tmu3_device = {
192}; 180};
193 181
194static struct sh_timer_config tmu4_platform_data = { 182static struct sh_timer_config tmu4_platform_data = {
195 .name = "TMU4",
196 .channel_offset = 0x10, 183 .channel_offset = 0x10,
197 .timer_bit = 1, 184 .timer_bit = 1,
198 .clk = "peripheral_clk",
199}; 185};
200 186
201static struct resource tmu4_resources[] = { 187static struct resource tmu4_resources[] = {
202 [0] = { 188 [0] = {
203 .name = "TMU4",
204 .start = 0xffc20014, 189 .start = 0xffc20014,
205 .end = 0xffc2001f, 190 .end = 0xffc2001f,
206 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
@@ -222,15 +207,12 @@ static struct platform_device tmu4_device = {
222}; 207};
223 208
224static struct sh_timer_config tmu5_platform_data = { 209static struct sh_timer_config tmu5_platform_data = {
225 .name = "TMU5",
226 .channel_offset = 0x1c, 210 .channel_offset = 0x1c,
227 .timer_bit = 2, 211 .timer_bit = 2,
228 .clk = "peripheral_clk",
229}; 212};
230 213
231static struct resource tmu5_resources[] = { 214static struct resource tmu5_resources[] = {
232 [0] = { 215 [0] = {
233 .name = "TMU5",
234 .start = 0xffc20020, 216 .start = 0xffc20020,
235 .end = 0xffc2002b, 217 .end = 0xffc2002b,
236 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 11bf4c1e25c..de865cac02e 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 SMP 2 * SH-X3 SMP
3 * 3 *
4 * Copyright (C) 2007 - 2008 Paul Mundt 4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2007 Magnus Damm
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -9,16 +9,22 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h>
12#include <linux/cpumask.h> 13#include <linux/cpumask.h>
13#include <linux/smp.h> 14#include <linux/smp.h>
14#include <linux/interrupt.h> 15#include <linux/interrupt.h>
15#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
19#include <linux/cpu.h>
20#include <asm/sections.h>
16 21
17#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12)) 22#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
18#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12)) 23#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
19 24
20#define STBCR_MSTP 0x00000001 25#define STBCR_MSTP 0x00000001
21#define STBCR_RESET 0x00000002 26#define STBCR_RESET 0x00000002
27#define STBCR_SLEEP 0x00000004
22#define STBCR_LTSLP 0x80000000 28#define STBCR_LTSLP 0x80000000
23 29
24static irqreturn_t ipi_interrupt_handler(int irq, void *arg) 30static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
@@ -37,7 +43,7 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
37 return IRQ_HANDLED; 43 return IRQ_HANDLED;
38} 44}
39 45
40void __init plat_smp_setup(void) 46static void shx3_smp_setup(void)
41{ 47{
42 unsigned int cpu = 0; 48 unsigned int cpu = 0;
43 int i, num; 49 int i, num;
@@ -63,7 +69,7 @@ void __init plat_smp_setup(void)
63 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 69 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
64} 70}
65 71
66void __init plat_prepare_cpus(unsigned int max_cpus) 72static void shx3_prepare_cpus(unsigned int max_cpus)
67{ 73{
68 int i; 74 int i;
69 75
@@ -72,11 +78,14 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
72 BUILD_BUG_ON(SMP_MSG_NR >= 8); 78 BUILD_BUG_ON(SMP_MSG_NR >= 8);
73 79
74 for (i = 0; i < SMP_MSG_NR; i++) 80 for (i = 0; i < SMP_MSG_NR; i++)
75 request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED, 81 request_irq(104 + i, ipi_interrupt_handler,
76 "IPI", (void *)(long)i); 82 IRQF_DISABLED | IRQF_PERCPU, "IPI", (void *)(long)i);
83
84 for (i = 0; i < max_cpus; i++)
85 set_cpu_present(i, true);
77} 86}
78 87
79void plat_start_cpu(unsigned int cpu, unsigned long entry_point) 88static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
80{ 89{
81 if (__in_29bit_mode()) 90 if (__in_29bit_mode())
82 __raw_writel(entry_point, RESET_REG(cpu)); 91 __raw_writel(entry_point, RESET_REG(cpu));
@@ -93,12 +102,12 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
93 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); 102 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
94} 103}
95 104
96int plat_smp_processor_id(void) 105static unsigned int shx3_smp_processor_id(void)
97{ 106{
98 return __raw_readl(0xff000048); /* CPIDR */ 107 return __raw_readl(0xff000048); /* CPIDR */
99} 108}
100 109
101void plat_send_ipi(unsigned int cpu, unsigned int message) 110static void shx3_send_ipi(unsigned int cpu, unsigned int message)
102{ 111{
103 unsigned long addr = 0xfe410070 + (cpu * 4); 112 unsigned long addr = 0xfe410070 + (cpu * 4);
104 113
@@ -106,3 +115,52 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
106 115
107 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ 116 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
108} 117}
118
119static void shx3_update_boot_vector(unsigned int cpu)
120{
121 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
122 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
123 cpu_relax();
124 __raw_writel(STBCR_RESET, STBCR_REG(cpu));
125}
126
127static int __cpuinit
128shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
129{
130 unsigned int cpu = (unsigned int)hcpu;
131
132 switch (action) {
133 case CPU_UP_PREPARE:
134 shx3_update_boot_vector(cpu);
135 break;
136 case CPU_ONLINE:
137 pr_info("CPU %u is now online\n", cpu);
138 break;
139 case CPU_DEAD:
140 break;
141 }
142
143 return NOTIFY_OK;
144}
145
146static struct notifier_block __cpuinitdata shx3_cpu_notifier = {
147 .notifier_call = shx3_cpu_callback,
148};
149
150static int __cpuinit register_shx3_cpu_notifier(void)
151{
152 register_hotcpu_notifier(&shx3_cpu_notifier);
153 return 0;
154}
155late_initcall(register_shx3_cpu_notifier);
156
157struct plat_smp_ops shx3_smp_ops = {
158 .smp_setup = shx3_smp_setup,
159 .prepare_cpus = shx3_prepare_cpus,
160 .start_cpu = shx3_start_cpu,
161 .smp_processor_id = shx3_smp_processor_id,
162 .send_ipi = shx3_send_ipi,
163 .cpu_die = native_cpu_die,
164 .cpu_disable = native_cpu_disable,
165 .play_dead = native_play_dead,
166};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 13:06:06 -0500