diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7786.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7786.c | 157 |
1 files changed, 114 insertions, 43 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 7e585320710..81657091da4 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * SH7786 Setup | 2 | * SH7786 Setup |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | 4 | * Copyright (C) 2009 - 2010 Renesas Solutions Corp. |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | 5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> |
6 | * Paul Mundt <paul.mundt@renesas.com> | 6 | * Paul Mundt <paul.mundt@renesas.com> |
7 | * | 7 | * |
@@ -21,7 +21,10 @@ | |||
21 | #include <linux/mm.h> | 21 | #include <linux/mm.h> |
22 | #include <linux/dma-mapping.h> | 22 | #include <linux/dma-mapping.h> |
23 | #include <linux/sh_timer.h> | 23 | #include <linux/sh_timer.h> |
24 | #include <linux/sh_intc.h> | ||
25 | #include <cpu/dma-register.h> | ||
24 | #include <asm/mmzone.h> | 26 | #include <asm/mmzone.h> |
27 | #include <asm/dmaengine.h> | ||
25 | 28 | ||
26 | static struct plat_sci_port scif0_platform_data = { | 29 | static struct plat_sci_port scif0_platform_data = { |
27 | .mapbase = 0xffea0000, | 30 | .mapbase = 0xffea0000, |
@@ -117,16 +120,13 @@ static struct platform_device scif5_device = { | |||
117 | }; | 120 | }; |
118 | 121 | ||
119 | static struct sh_timer_config tmu0_platform_data = { | 122 | static struct sh_timer_config tmu0_platform_data = { |
120 | .name = "TMU0", | ||
121 | .channel_offset = 0x04, | 123 | .channel_offset = 0x04, |
122 | .timer_bit = 0, | 124 | .timer_bit = 0, |
123 | .clk = "peripheral_clk", | ||
124 | .clockevent_rating = 200, | 125 | .clockevent_rating = 200, |
125 | }; | 126 | }; |
126 | 127 | ||
127 | static struct resource tmu0_resources[] = { | 128 | static struct resource tmu0_resources[] = { |
128 | [0] = { | 129 | [0] = { |
129 | .name = "TMU0", | ||
130 | .start = 0xffd80008, | 130 | .start = 0xffd80008, |
131 | .end = 0xffd80013, | 131 | .end = 0xffd80013, |
132 | .flags = IORESOURCE_MEM, | 132 | .flags = IORESOURCE_MEM, |
@@ -148,16 +148,13 @@ static struct platform_device tmu0_device = { | |||
148 | }; | 148 | }; |
149 | 149 | ||
150 | static struct sh_timer_config tmu1_platform_data = { | 150 | static struct sh_timer_config tmu1_platform_data = { |
151 | .name = "TMU1", | ||
152 | .channel_offset = 0x10, | 151 | .channel_offset = 0x10, |
153 | .timer_bit = 1, | 152 | .timer_bit = 1, |
154 | .clk = "peripheral_clk", | ||
155 | .clocksource_rating = 200, | 153 | .clocksource_rating = 200, |
156 | }; | 154 | }; |
157 | 155 | ||
158 | static struct resource tmu1_resources[] = { | 156 | static struct resource tmu1_resources[] = { |
159 | [0] = { | 157 | [0] = { |
160 | .name = "TMU1", | ||
161 | .start = 0xffd80014, | 158 | .start = 0xffd80014, |
162 | .end = 0xffd8001f, | 159 | .end = 0xffd8001f, |
163 | .flags = IORESOURCE_MEM, | 160 | .flags = IORESOURCE_MEM, |
@@ -179,15 +176,12 @@ static struct platform_device tmu1_device = { | |||
179 | }; | 176 | }; |
180 | 177 | ||
181 | static struct sh_timer_config tmu2_platform_data = { | 178 | static struct sh_timer_config tmu2_platform_data = { |
182 | .name = "TMU2", | ||
183 | .channel_offset = 0x1c, | 179 | .channel_offset = 0x1c, |
184 | .timer_bit = 2, | 180 | .timer_bit = 2, |
185 | .clk = "peripheral_clk", | ||
186 | }; | 181 | }; |
187 | 182 | ||
188 | static struct resource tmu2_resources[] = { | 183 | static struct resource tmu2_resources[] = { |
189 | [0] = { | 184 | [0] = { |
190 | .name = "TMU2", | ||
191 | .start = 0xffd80020, | 185 | .start = 0xffd80020, |
192 | .end = 0xffd8002f, | 186 | .end = 0xffd8002f, |
193 | .flags = IORESOURCE_MEM, | 187 | .flags = IORESOURCE_MEM, |
@@ -209,15 +203,12 @@ static struct platform_device tmu2_device = { | |||
209 | }; | 203 | }; |
210 | 204 | ||
211 | static struct sh_timer_config tmu3_platform_data = { | 205 | static struct sh_timer_config tmu3_platform_data = { |
212 | .name = "TMU3", | ||
213 | .channel_offset = 0x04, | 206 | .channel_offset = 0x04, |
214 | .timer_bit = 0, | 207 | .timer_bit = 0, |
215 | .clk = "peripheral_clk", | ||
216 | }; | 208 | }; |
217 | 209 | ||
218 | static struct resource tmu3_resources[] = { | 210 | static struct resource tmu3_resources[] = { |
219 | [0] = { | 211 | [0] = { |
220 | .name = "TMU3", | ||
221 | .start = 0xffda0008, | 212 | .start = 0xffda0008, |
222 | .end = 0xffda0013, | 213 | .end = 0xffda0013, |
223 | .flags = IORESOURCE_MEM, | 214 | .flags = IORESOURCE_MEM, |
@@ -239,15 +230,12 @@ static struct platform_device tmu3_device = { | |||
239 | }; | 230 | }; |
240 | 231 | ||
241 | static struct sh_timer_config tmu4_platform_data = { | 232 | static struct sh_timer_config tmu4_platform_data = { |
242 | .name = "TMU4", | ||
243 | .channel_offset = 0x10, | 233 | .channel_offset = 0x10, |
244 | .timer_bit = 1, | 234 | .timer_bit = 1, |
245 | .clk = "peripheral_clk", | ||
246 | }; | 235 | }; |
247 | 236 | ||
248 | static struct resource tmu4_resources[] = { | 237 | static struct resource tmu4_resources[] = { |
249 | [0] = { | 238 | [0] = { |
250 | .name = "TMU4", | ||
251 | .start = 0xffda0014, | 239 | .start = 0xffda0014, |
252 | .end = 0xffda001f, | 240 | .end = 0xffda001f, |
253 | .flags = IORESOURCE_MEM, | 241 | .flags = IORESOURCE_MEM, |
@@ -269,15 +257,12 @@ static struct platform_device tmu4_device = { | |||
269 | }; | 257 | }; |
270 | 258 | ||
271 | static struct sh_timer_config tmu5_platform_data = { | 259 | static struct sh_timer_config tmu5_platform_data = { |
272 | .name = "TMU5", | ||
273 | .channel_offset = 0x1c, | 260 | .channel_offset = 0x1c, |
274 | .timer_bit = 2, | 261 | .timer_bit = 2, |
275 | .clk = "peripheral_clk", | ||
276 | }; | 262 | }; |
277 | 263 | ||
278 | static struct resource tmu5_resources[] = { | 264 | static struct resource tmu5_resources[] = { |
279 | [0] = { | 265 | [0] = { |
280 | .name = "TMU5", | ||
281 | .start = 0xffda0020, | 266 | .start = 0xffda0020, |
282 | .end = 0xffda002b, | 267 | .end = 0xffda002b, |
283 | .flags = IORESOURCE_MEM, | 268 | .flags = IORESOURCE_MEM, |
@@ -299,15 +284,12 @@ static struct platform_device tmu5_device = { | |||
299 | }; | 284 | }; |
300 | 285 | ||
301 | static struct sh_timer_config tmu6_platform_data = { | 286 | static struct sh_timer_config tmu6_platform_data = { |
302 | .name = "TMU6", | ||
303 | .channel_offset = 0x04, | 287 | .channel_offset = 0x04, |
304 | .timer_bit = 0, | 288 | .timer_bit = 0, |
305 | .clk = "peripheral_clk", | ||
306 | }; | 289 | }; |
307 | 290 | ||
308 | static struct resource tmu6_resources[] = { | 291 | static struct resource tmu6_resources[] = { |
309 | [0] = { | 292 | [0] = { |
310 | .name = "TMU6", | ||
311 | .start = 0xffdc0008, | 293 | .start = 0xffdc0008, |
312 | .end = 0xffdc0013, | 294 | .end = 0xffdc0013, |
313 | .flags = IORESOURCE_MEM, | 295 | .flags = IORESOURCE_MEM, |
@@ -329,15 +311,12 @@ static struct platform_device tmu6_device = { | |||
329 | }; | 311 | }; |
330 | 312 | ||
331 | static struct sh_timer_config tmu7_platform_data = { | 313 | static struct sh_timer_config tmu7_platform_data = { |
332 | .name = "TMU7", | ||
333 | .channel_offset = 0x10, | 314 | .channel_offset = 0x10, |
334 | .timer_bit = 1, | 315 | .timer_bit = 1, |
335 | .clk = "peripheral_clk", | ||
336 | }; | 316 | }; |
337 | 317 | ||
338 | static struct resource tmu7_resources[] = { | 318 | static struct resource tmu7_resources[] = { |
339 | [0] = { | 319 | [0] = { |
340 | .name = "TMU7", | ||
341 | .start = 0xffdc0014, | 320 | .start = 0xffdc0014, |
342 | .end = 0xffdc001f, | 321 | .end = 0xffdc001f, |
343 | .flags = IORESOURCE_MEM, | 322 | .flags = IORESOURCE_MEM, |
@@ -359,15 +338,12 @@ static struct platform_device tmu7_device = { | |||
359 | }; | 338 | }; |
360 | 339 | ||
361 | static struct sh_timer_config tmu8_platform_data = { | 340 | static struct sh_timer_config tmu8_platform_data = { |
362 | .name = "TMU8", | ||
363 | .channel_offset = 0x1c, | 341 | .channel_offset = 0x1c, |
364 | .timer_bit = 2, | 342 | .timer_bit = 2, |
365 | .clk = "peripheral_clk", | ||
366 | }; | 343 | }; |
367 | 344 | ||
368 | static struct resource tmu8_resources[] = { | 345 | static struct resource tmu8_resources[] = { |
369 | [0] = { | 346 | [0] = { |
370 | .name = "TMU8", | ||
371 | .start = 0xffdc0020, | 347 | .start = 0xffdc0020, |
372 | .end = 0xffdc002b, | 348 | .end = 0xffdc002b, |
373 | .flags = IORESOURCE_MEM, | 349 | .flags = IORESOURCE_MEM, |
@@ -389,15 +365,12 @@ static struct platform_device tmu8_device = { | |||
389 | }; | 365 | }; |
390 | 366 | ||
391 | static struct sh_timer_config tmu9_platform_data = { | 367 | static struct sh_timer_config tmu9_platform_data = { |
392 | .name = "TMU9", | ||
393 | .channel_offset = 0x04, | 368 | .channel_offset = 0x04, |
394 | .timer_bit = 0, | 369 | .timer_bit = 0, |
395 | .clk = "peripheral_clk", | ||
396 | }; | 370 | }; |
397 | 371 | ||
398 | static struct resource tmu9_resources[] = { | 372 | static struct resource tmu9_resources[] = { |
399 | [0] = { | 373 | [0] = { |
400 | .name = "TMU9", | ||
401 | .start = 0xffde0008, | 374 | .start = 0xffde0008, |
402 | .end = 0xffde0013, | 375 | .end = 0xffde0013, |
403 | .flags = IORESOURCE_MEM, | 376 | .flags = IORESOURCE_MEM, |
@@ -419,15 +392,12 @@ static struct platform_device tmu9_device = { | |||
419 | }; | 392 | }; |
420 | 393 | ||
421 | static struct sh_timer_config tmu10_platform_data = { | 394 | static struct sh_timer_config tmu10_platform_data = { |
422 | .name = "TMU10", | ||
423 | .channel_offset = 0x10, | 395 | .channel_offset = 0x10, |
424 | .timer_bit = 1, | 396 | .timer_bit = 1, |
425 | .clk = "peripheral_clk", | ||
426 | }; | 397 | }; |
427 | 398 | ||
428 | static struct resource tmu10_resources[] = { | 399 | static struct resource tmu10_resources[] = { |
429 | [0] = { | 400 | [0] = { |
430 | .name = "TMU10", | ||
431 | .start = 0xffde0014, | 401 | .start = 0xffde0014, |
432 | .end = 0xffde001f, | 402 | .end = 0xffde001f, |
433 | .flags = IORESOURCE_MEM, | 403 | .flags = IORESOURCE_MEM, |
@@ -449,15 +419,12 @@ static struct platform_device tmu10_device = { | |||
449 | }; | 419 | }; |
450 | 420 | ||
451 | static struct sh_timer_config tmu11_platform_data = { | 421 | static struct sh_timer_config tmu11_platform_data = { |
452 | .name = "TMU11", | ||
453 | .channel_offset = 0x1c, | 422 | .channel_offset = 0x1c, |
454 | .timer_bit = 2, | 423 | .timer_bit = 2, |
455 | .clk = "peripheral_clk", | ||
456 | }; | 424 | }; |
457 | 425 | ||
458 | static struct resource tmu11_resources[] = { | 426 | static struct resource tmu11_resources[] = { |
459 | [0] = { | 427 | [0] = { |
460 | .name = "TMU11", | ||
461 | .start = 0xffde0020, | 428 | .start = 0xffde0020, |
462 | .end = 0xffde002b, | 429 | .end = 0xffde002b, |
463 | .flags = IORESOURCE_MEM, | 430 | .flags = IORESOURCE_MEM, |
@@ -478,6 +445,83 @@ static struct platform_device tmu11_device = { | |||
478 | .num_resources = ARRAY_SIZE(tmu11_resources), | 445 | .num_resources = ARRAY_SIZE(tmu11_resources), |
479 | }; | 446 | }; |
480 | 447 | ||
448 | static const struct sh_dmae_channel dmac0_channels[] = { | ||
449 | { | ||
450 | .offset = 0, | ||
451 | .dmars = 0, | ||
452 | .dmars_bit = 0, | ||
453 | }, { | ||
454 | .offset = 0x10, | ||
455 | .dmars = 0, | ||
456 | .dmars_bit = 8, | ||
457 | }, { | ||
458 | .offset = 0x20, | ||
459 | .dmars = 4, | ||
460 | .dmars_bit = 0, | ||
461 | }, { | ||
462 | .offset = 0x30, | ||
463 | .dmars = 4, | ||
464 | .dmars_bit = 8, | ||
465 | }, { | ||
466 | .offset = 0x50, | ||
467 | .dmars = 8, | ||
468 | .dmars_bit = 0, | ||
469 | }, { | ||
470 | .offset = 0x60, | ||
471 | .dmars = 8, | ||
472 | .dmars_bit = 8, | ||
473 | } | ||
474 | }; | ||
475 | |||
476 | static const unsigned int ts_shift[] = TS_SHIFT; | ||
477 | |||
478 | static struct sh_dmae_pdata dma0_platform_data = { | ||
479 | .channel = dmac0_channels, | ||
480 | .channel_num = ARRAY_SIZE(dmac0_channels), | ||
481 | .ts_low_shift = CHCR_TS_LOW_SHIFT, | ||
482 | .ts_low_mask = CHCR_TS_LOW_MASK, | ||
483 | .ts_high_shift = CHCR_TS_HIGH_SHIFT, | ||
484 | .ts_high_mask = CHCR_TS_HIGH_MASK, | ||
485 | .ts_shift = ts_shift, | ||
486 | .ts_shift_num = ARRAY_SIZE(ts_shift), | ||
487 | .dmaor_init = DMAOR_INIT, | ||
488 | }; | ||
489 | |||
490 | /* Resource order important! */ | ||
491 | static struct resource dmac0_resources[] = { | ||
492 | { | ||
493 | /* Channel registers and DMAOR */ | ||
494 | .start = 0xfe008020, | ||
495 | .end = 0xfe00808f, | ||
496 | .flags = IORESOURCE_MEM, | ||
497 | }, { | ||
498 | /* DMARSx */ | ||
499 | .start = 0xfe009000, | ||
500 | .end = 0xfe00900b, | ||
501 | .flags = IORESOURCE_MEM, | ||
502 | }, { | ||
503 | /* DMA error IRQ */ | ||
504 | .start = evt2irq(0x5c0), | ||
505 | .end = evt2irq(0x5c0), | ||
506 | .flags = IORESOURCE_IRQ, | ||
507 | }, { | ||
508 | /* IRQ for channels 0-5 */ | ||
509 | .start = evt2irq(0x500), | ||
510 | .end = evt2irq(0x5a0), | ||
511 | .flags = IORESOURCE_IRQ, | ||
512 | }, | ||
513 | }; | ||
514 | |||
515 | static struct platform_device dma0_device = { | ||
516 | .name = "sh-dma-engine", | ||
517 | .id = 0, | ||
518 | .resource = dmac0_resources, | ||
519 | .num_resources = ARRAY_SIZE(dmac0_resources), | ||
520 | .dev = { | ||
521 | .platform_data = &dma0_platform_data, | ||
522 | }, | ||
523 | }; | ||
524 | |||
481 | static struct resource usb_ohci_resources[] = { | 525 | static struct resource usb_ohci_resources[] = { |
482 | [0] = { | 526 | [0] = { |
483 | .start = 0xffe70400, | 527 | .start = 0xffe70400, |
@@ -525,10 +569,10 @@ static struct platform_device *sh7786_early_devices[] __initdata = { | |||
525 | }; | 569 | }; |
526 | 570 | ||
527 | static struct platform_device *sh7786_devices[] __initdata = { | 571 | static struct platform_device *sh7786_devices[] __initdata = { |
572 | &dma0_device, | ||
528 | &usb_ohci_device, | 573 | &usb_ohci_device, |
529 | }; | 574 | }; |
530 | 575 | ||
531 | |||
532 | /* | 576 | /* |
533 | * Please call this function if your platform board | 577 | * Please call this function if your platform board |
534 | * use external clock for USB | 578 | * use external clock for USB |
@@ -536,6 +580,7 @@ static struct platform_device *sh7786_devices[] __initdata = { | |||
536 | #define USBCTL0 0xffe70858 | 580 | #define USBCTL0 0xffe70858 |
537 | #define CLOCK_MODE_MASK 0xffffff7f | 581 | #define CLOCK_MODE_MASK 0xffffff7f |
538 | #define EXT_CLOCK_MODE 0x00000080 | 582 | #define EXT_CLOCK_MODE 0x00000080 |
583 | |||
539 | void __init sh7786_usb_use_exclock(void) | 584 | void __init sh7786_usb_use_exclock(void) |
540 | { | 585 | { |
541 | u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; | 586 | u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; |
@@ -553,6 +598,7 @@ void __init sh7786_usb_use_exclock(void) | |||
553 | #define PLL_ENB 0x00000002 | 598 | #define PLL_ENB 0x00000002 |
554 | #define PHY_RST 0x00000004 | 599 | #define PHY_RST 0x00000004 |
555 | #define ACT_PLL_STATUS 0xc0000000 | 600 | #define ACT_PLL_STATUS 0xc0000000 |
601 | |||
556 | static void __init sh7786_usb_setup(void) | 602 | static void __init sh7786_usb_setup(void) |
557 | { | 603 | { |
558 | int i = 1000000; | 604 | int i = 1000000; |
@@ -708,9 +754,19 @@ static struct intc_vect vectors[] __initdata = { | |||
708 | #define INTMSK2 0xfe410068 | 754 | #define INTMSK2 0xfe410068 |
709 | #define INTMSKCLR2 0xfe41006c | 755 | #define INTMSKCLR2 0xfe41006c |
710 | 756 | ||
757 | #define INTDISTCR0 0xfe4100b0 | ||
758 | #define INTDISTCR1 0xfe4100b4 | ||
759 | #define INTACK 0xfe4100b8 | ||
760 | #define INTACKCLR 0xfe4100bc | ||
761 | #define INT2DISTCR0 0xfe410900 | ||
762 | #define INT2DISTCR1 0xfe410904 | ||
763 | #define INT2DISTCR2 0xfe410908 | ||
764 | #define INT2DISTCR3 0xfe41090c | ||
765 | |||
711 | static struct intc_mask_reg mask_registers[] __initdata = { | 766 | static struct intc_mask_reg mask_registers[] __initdata = { |
712 | { CnINTMSK0, CnINTMSKCLR0, 32, | 767 | { CnINTMSK0, CnINTMSKCLR0, 32, |
713 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 768 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 }, |
769 | INTC_SMP_BALANCING(INTDISTCR0) }, | ||
714 | { INTMSK2, INTMSKCLR2, 32, | 770 | { INTMSK2, INTMSKCLR2, 32, |
715 | { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, | 771 | { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, |
716 | IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, | 772 | IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, |
@@ -722,7 +778,8 @@ static struct intc_mask_reg mask_registers[] __initdata = { | |||
722 | IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, | 778 | IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, |
723 | { CnINT2MSKR0, CnINT2MSKCR0 , 32, | 779 | { CnINT2MSKR0, CnINT2MSKCR0 , 32, |
724 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 780 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
725 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } }, | 781 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT }, |
782 | INTC_SMP_BALANCING(INT2DISTCR0) }, | ||
726 | { CnINT2MSKR1, CnINT2MSKCR1, 32, | 783 | { CnINT2MSKR1, CnINT2MSKCR1, 32, |
727 | { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, | 784 | { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, |
728 | DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, | 785 | DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, |
@@ -731,14 +788,14 @@ static struct intc_mask_reg mask_registers[] __initdata = { | |||
731 | HPB_0, HPB_1, HPB_2, | 788 | HPB_0, HPB_1, HPB_2, |
732 | SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, | 789 | SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, |
733 | SCIF1, | 790 | SCIF1, |
734 | TMU2, TMU3, 0, } }, | 791 | TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) }, |
735 | { CnINT2MSKR2, CnINT2MSKCR2, 32, | 792 | { CnINT2MSKR2, CnINT2MSKCR2, 32, |
736 | { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, | 793 | { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, |
737 | Eth_0, Eth_1, | 794 | Eth_0, Eth_1, |
738 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 795 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
739 | PCIeC0_0, PCIeC0_1, PCIeC0_2, | 796 | PCIeC0_0, PCIeC0_1, PCIeC0_2, |
740 | PCIeC1_0, PCIeC1_1, PCIeC1_2, | 797 | PCIeC1_0, PCIeC1_1, PCIeC1_2, |
741 | USB, 0, 0 } }, | 798 | USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) }, |
742 | { CnINT2MSKR3, CnINT2MSKCR3, 32, | 799 | { CnINT2MSKR3, CnINT2MSKCR3, 32, |
743 | { 0, 0, 0, 0, 0, 0, | 800 | { 0, 0, 0, 0, 0, 0, |
744 | I2C0, I2C1, | 801 | I2C0, I2C1, |
@@ -747,7 +804,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { | |||
747 | HAC0, HAC1, | 804 | HAC0, HAC1, |
748 | FLCTL, 0, | 805 | FLCTL, 0, |
749 | HSPI, GPIO0, GPIO1, Thermal, | 806 | HSPI, GPIO0, GPIO1, Thermal, |
750 | 0, 0, 0, 0, 0, 0, 0, 0 } }, | 807 | 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) }, |
751 | }; | 808 | }; |
752 | 809 | ||
753 | static struct intc_prio_reg prio_registers[] __initdata = { | 810 | static struct intc_prio_reg prio_registers[] __initdata = { |
@@ -863,6 +920,19 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, | |||
863 | #define INTC_INTMSK2 INTMSK2 | 920 | #define INTC_INTMSK2 INTMSK2 |
864 | #define INTC_INTMSKCLR1 CnINTMSKCLR1 | 921 | #define INTC_INTMSKCLR1 CnINTMSKCLR1 |
865 | #define INTC_INTMSKCLR2 INTMSKCLR2 | 922 | #define INTC_INTMSKCLR2 INTMSKCLR2 |
923 | #define INTC_USERIMASK 0xfe411000 | ||
924 | |||
925 | #ifdef CONFIG_INTC_BALANCING | ||
926 | unsigned int irq_lookup(unsigned int irq) | ||
927 | { | ||
928 | return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE; | ||
929 | } | ||
930 | |||
931 | void irq_finish(unsigned int irq) | ||
932 | { | ||
933 | __raw_writel(irq2evt(irq), INTACKCLR); | ||
934 | } | ||
935 | #endif | ||
866 | 936 | ||
867 | void __init plat_irq_setup(void) | 937 | void __init plat_irq_setup(void) |
868 | { | 938 | { |
@@ -877,6 +947,7 @@ void __init plat_irq_setup(void) | |||
877 | __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); | 947 | __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); |
878 | 948 | ||
879 | register_intc_controller(&intc_desc); | 949 | register_intc_controller(&intc_desc); |
950 | register_intc_userimask(INTC_USERIMASK); | ||
880 | } | 951 | } |
881 | 952 | ||
882 | void __init plat_irq_setup_pins(int mode) | 953 | void __init plat_irq_setup_pins(int mode) |