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-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h319
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64-4k.h (renamed from arch/powerpc/include/asm/pgtable-4k.h)55
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64-64k.h42
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h91
-rw-r--r--arch/powerpc/include/asm/pte-40x.h64
-rw-r--r--arch/powerpc/include/asm/pte-44x.h102
-rw-r--r--arch/powerpc/include/asm/pte-8xx.h64
-rw-r--r--arch/powerpc/include/asm/pte-fsl-booke.h46
-rw-r--r--arch/powerpc/include/asm/pte-hash32.h49
-rw-r--r--arch/powerpc/include/asm/pte-hash64-4k.h20
-rw-r--r--arch/powerpc/include/asm/pte-hash64-64k.h (renamed from arch/powerpc/include/asm/pgtable-64k.h)132
-rw-r--r--arch/powerpc/include/asm/pte-hash64.h47
12 files changed, 564 insertions, 467 deletions
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 98bd7c5fcd0..a9c6ecef365 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -19,55 +19,6 @@ extern int icache_44x_need_flush;
19#endif /* __ASSEMBLY__ */ 19#endif /* __ASSEMBLY__ */
20 20
21/* 21/*
22 * The PowerPC MMU uses a hash table containing PTEs, together with
23 * a set of 16 segment registers (on 32-bit implementations), to define
24 * the virtual to physical address mapping.
25 *
26 * We use the hash table as an extended TLB, i.e. a cache of currently
27 * active mappings. We maintain a two-level page table tree, much
28 * like that used by the i386, for the sake of the Linux memory
29 * management code. Low-level assembler code in hashtable.S
30 * (procedure hash_page) is responsible for extracting ptes from the
31 * tree and putting them into the hash table when necessary, and
32 * updating the accessed and modified bits in the page table tree.
33 */
34
35/*
36 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
37 * We also use the two level tables, but we can put the real bits in them
38 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
39 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
40 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
41 * based upon user/super access. The TLB does not have accessed nor write
42 * protect. We assume that if the TLB get loaded with an entry it is
43 * accessed, and overload the changed bit for write protect. We use
44 * two bits in the software pte that are supposed to be set to zero in
45 * the TLB entry (24 and 25) for these indicators. Although the level 1
46 * descriptor contains the guarded and writethrough/copyback bits, we can
47 * set these at the page level since they get copied from the Mx_TWC
48 * register when the TLB entry is loaded. We will use bit 27 for guard, since
49 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
50 * These will get masked from the level 2 descriptor at TLB load time, and
51 * copied to the MD_TWC before it gets loaded.
52 * Large page sizes added. We currently support two sizes, 4K and 8M.
53 * This also allows a TLB hander optimization because we can directly
54 * load the PMD into MD_TWC. The 8M pages are only used for kernel
55 * mapping of well known areas. The PMD (PGD) entries contain control
56 * flags in addition to the address, so care must be taken that the
57 * software no longer assumes these are only pointers.
58 */
59
60/*
61 * At present, all PowerPC 400-class processors share a similar TLB
62 * architecture. The instruction and data sides share a unified,
63 * 64-entry, fully-associative TLB which is maintained totally under
64 * software control. In addition, the instruction side has a
65 * hardware-managed, 4-entry, fully-associative TLB which serves as a
66 * first level to the shared TLB. These two TLBs are known as the UTLB
67 * and ITLB, respectively (see "mmu.h" for definitions).
68 */
69
70/*
71 * The normal case is that PTEs are 32-bits and we have a 1-page 22 * The normal case is that PTEs are 32-bits and we have a 1-page
72 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 23 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
73 * 24 *
@@ -135,261 +86,25 @@ extern int icache_44x_need_flush;
135 */ 86 */
136 87
137#if defined(CONFIG_40x) 88#if defined(CONFIG_40x)
138 89#include <asm/pte-40x.h>
139/* There are several potential gotchas here. The 40x hardware TLBLO
140 field looks like this:
141
142 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
143 RPN..................... 0 0 EX WR ZSEL....... W I M G
144
145 Where possible we make the Linux PTE bits match up with this
146
147 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
148 support down to 1k pages), this is done in the TLBMiss exception
149 handler.
150 - We use only zones 0 (for kernel pages) and 1 (for user pages)
151 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
152 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
153 zone.
154 - PRESENT *must* be in the bottom two bits because swap cache
155 entries use the top 30 bits. Because 40x doesn't support SMP
156 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
157 is cleared in the TLB miss handler before the TLB entry is loaded.
158 - All other bits of the PTE are loaded into TLBLO without
159 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
160 software PTE bits. We actually use use bits 21, 24, 25, and
161 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
162 PRESENT.
163*/
164
165/* Definitions for 40x embedded chips. */
166#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
167#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
168#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
169#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
170#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
171#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
172#define _PAGE_RW 0x040 /* software: Writes permitted */
173#define _PAGE_DIRTY 0x080 /* software: dirty page */
174#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
175#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
176#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
177
178#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
179#define _PMD_BAD 0x802
180#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
181#define _PMD_SIZE_4M 0x0c0
182#define _PMD_SIZE_16M 0x0e0
183#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
184
185/* Until my rework is finished, 40x still needs atomic PTE updates */
186#define PTE_ATOMIC_UPDATES 1
187
188#elif defined(CONFIG_44x) 90#elif defined(CONFIG_44x)
189/* 91#include <asm/pte-44x.h>
190 * Definitions for PPC440
191 *
192 * Because of the 3 word TLB entries to support 36-bit addressing,
193 * the attribute are difficult to map in such a fashion that they
194 * are easily loaded during exception processing. I decided to
195 * organize the entry so the ERPN is the only portion in the
196 * upper word of the PTE and the attribute bits below are packed
197 * in as sensibly as they can be in the area below a 4KB page size
198 * oriented RPN. This at least makes it easy to load the RPN and
199 * ERPN fields in the TLB. -Matt
200 *
201 * Note that these bits preclude future use of a page size
202 * less than 4KB.
203 *
204 *
205 * PPC 440 core has following TLB attribute fields;
206 *
207 * TLB1:
208 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
209 * RPN................................. - - - - - - ERPN.......
210 *
211 * TLB2:
212 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
213 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
214 *
215 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
216 * TLB2 storage attibute fields. Those are:
217 *
218 * TLB2:
219 * 0...10 11 12 13 14 15 16...31
220 * no change WL1 IL1I IL1D IL2I IL2D no change
221 *
222 * There are some constrains and options, to decide mapping software bits
223 * into TLB entry.
224 *
225 * - PRESENT *must* be in the bottom three bits because swap cache
226 * entries use the top 29 bits for TLB2.
227 *
228 * - FILE *must* be in the bottom three bits because swap cache
229 * entries use the top 29 bits for TLB2.
230 *
231 * - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
232 * because it doesn't support SMP. However, some later 460 variants
233 * have -some- form of SMP support and so I keep the bit there for
234 * future use
235 *
236 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
237 * for memory protection related functions (see PTE structure in
238 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
239 * above bits. Note that the bit values are CPU specific, not architecture
240 * specific.
241 *
242 * The kernel PTE entry holds an arch-dependent swp_entry structure under
243 * certain situations. In other words, in such situations some portion of
244 * the PTE bits are used as a swp_entry. In the PPC implementation, the
245 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
246 * hold protection values. That means the three protection bits are
247 * reserved for both PTE and SWAP entry at the most significant three
248 * LSBs.
249 *
250 * There are three protection bits available for SWAP entry:
251 * _PAGE_PRESENT
252 * _PAGE_FILE
253 * _PAGE_HASHPTE (if HW has)
254 *
255 * So those three bits have to be inside of 0-2nd LSB of PTE.
256 *
257 */
258
259#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
260#define _PAGE_RW 0x00000002 /* S: Write permission */
261#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
262#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
263#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
264#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
265#define _PAGE_SPECIAL 0x00000020 /* S: Special page */
266#define _PAGE_USER 0x00000040 /* S: User page */
267#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
268#define _PAGE_GUARDED 0x00000100 /* H: G bit */
269#define _PAGE_COHERENT 0x00000200 /* H: M bit */
270#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
271#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
272
273/* TODO: Add large page lowmem mapping support */
274#define _PMD_PRESENT 0
275#define _PMD_PRESENT_MASK (PAGE_MASK)
276#define _PMD_BAD (~PAGE_MASK)
277
278/* ERPN in a PTE never gets cleared, ignore it */
279#define _PTE_NONE_MASK 0xffffffff00000000ULL
280
281#define __HAVE_ARCH_PTE_SPECIAL
282
283#elif defined(CONFIG_FSL_BOOKE) 92#elif defined(CONFIG_FSL_BOOKE)
284/* 93#include <asm/pte-fsl-booke.h>
285 MMU Assist Register 3:
286
287 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
288 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
289
290 - PRESENT *must* be in the bottom three bits because swap cache
291 entries use the top 29 bits.
292
293 - FILE *must* be in the bottom three bits because swap cache
294 entries use the top 29 bits.
295*/
296
297/* Definitions for FSL Book-E Cores */
298#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
299#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
300#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
301#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
302#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
303#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
304#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
305
306#define _PAGE_ENDIAN 0x00040 /* H: E bit */
307#define _PAGE_GUARDED 0x00080 /* H: G bit */
308#define _PAGE_COHERENT 0x00100 /* H: M bit */
309#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
310#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
311#define _PAGE_SPECIAL 0x00800 /* S: Special page */
312
313#ifdef CONFIG_PTE_64BIT
314/* ERPN in a PTE never gets cleared, ignore it */
315#define _PTE_NONE_MASK 0xffffffffffff0000ULL
316#endif
317
318#define _PMD_PRESENT 0
319#define _PMD_PRESENT_MASK (PAGE_MASK)
320#define _PMD_BAD (~PAGE_MASK)
321
322#define __HAVE_ARCH_PTE_SPECIAL
323
324#elif defined(CONFIG_8xx) 94#elif defined(CONFIG_8xx)
325/* Definitions for 8xx embedded chips. */ 95#include <asm/pte-8xx.h>
326#define _PAGE_PRESENT 0x0001 /* Page is valid */
327#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
328#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
329#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
330
331/* These five software bits must be masked out when the entry is loaded
332 * into the TLB.
333 */
334#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
335#define _PAGE_GUARDED 0x0010 /* software: guarded access */
336#define _PAGE_DIRTY 0x0020 /* software: page changed */
337#define _PAGE_RW 0x0040 /* software: user write access allowed */
338#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
339
340/* Setting any bits in the nibble with the follow two controls will
341 * require a TLB exception handler change. It is assumed unused bits
342 * are always zero.
343 */
344#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
345#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
346
347#define _PMD_PRESENT 0x0001
348#define _PMD_BAD 0x0ff0
349#define _PMD_PAGE_MASK 0x000c
350#define _PMD_PAGE_8M 0x000c
351
352#define _PTE_NONE_MASK _PAGE_ACCESSED
353
354/* Until my rework is finished, 8xx still needs atomic PTE updates */
355#define PTE_ATOMIC_UPDATES 1
356
357#else /* CONFIG_6xx */ 96#else /* CONFIG_6xx */
358/* Definitions for 60x, 740/750, etc. */ 97#include <asm/pte-hash32.h>
359#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
360#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
361#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
362#define _PAGE_USER 0x004 /* usermode access allowed */
363#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
364#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
365#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
366#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
367#define _PAGE_DIRTY 0x080 /* C: page changed */
368#define _PAGE_ACCESSED 0x100 /* R: page referenced */
369#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
370#define _PAGE_RW 0x400 /* software: user write access allowed */
371#define _PAGE_SPECIAL 0x800 /* software: Special page */
372
373#ifdef CONFIG_PTE_64BIT
374/* We never clear the high word of the pte */
375#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
376#else
377#define _PTE_NONE_MASK _PAGE_HASHPTE
378#endif 98#endif
379 99
380#define _PMD_PRESENT 0 100/* If _PAGE_SPECIAL is defined, then we advertise our support for it */
381#define _PMD_PRESENT_MASK (PAGE_MASK) 101#ifdef _PAGE_SPECIAL
382#define _PMD_BAD (~PAGE_MASK)
383
384/* Hash table based platforms need atomic updates of the linux PTE */
385#define PTE_ATOMIC_UPDATES 1
386
387#define __HAVE_ARCH_PTE_SPECIAL 102#define __HAVE_ARCH_PTE_SPECIAL
388
389#endif 103#endif
390 104
391/* 105/*
392 * Some bits are only used on some cpu families... 106 * Some bits are only used on some cpu families... Make sure that all
107 * the undefined gets defined as 0
393 */ 108 */
394#ifndef _PAGE_HASHPTE 109#ifndef _PAGE_HASHPTE
395#define _PAGE_HASHPTE 0 110#define _PAGE_HASHPTE 0
@@ -600,11 +315,19 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
600 unsigned long address); 315 unsigned long address);
601 316
602/* 317/*
603 * Atomic PTE updates. 318 * PTE updates. This function is called whenever an existing
319 * valid PTE is updated. This does -not- include set_pte_at()
320 * which nowadays only sets a new PTE.
321 *
322 * Depending on the type of MMU, we may need to use atomic updates
323 * and the PTE may be either 32 or 64 bit wide. In the later case,
324 * when using atomic updates, only the low part of the PTE is
325 * accessed atomically.
604 * 326 *
605 * pte_update clears and sets bit atomically, and returns 327 * In addition, on 44x, we also maintain a global flag indicating
606 * the old pte value. In the 64-bit PTE case we lock around the 328 * that an executable user mapping was modified, which is needed
607 * low PTE word since we expect ALL flag bits to be there 329 * to properly flush the virtually tagged instruction cache of
330 * those implementations.
608 */ 331 */
609#ifndef CONFIG_PTE_64BIT 332#ifndef CONFIG_PTE_64BIT
610static inline unsigned long pte_update(pte_t *p, 333static inline unsigned long pte_update(pte_t *p,
diff --git a/arch/powerpc/include/asm/pgtable-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 1dbca4e7de6..6eefdcffa35 100644
--- a/arch/powerpc/include/asm/pgtable-4k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -1,5 +1,5 @@
1#ifndef _ASM_POWERPC_PGTABLE_4K_H 1#ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H
2#define _ASM_POWERPC_PGTABLE_4K_H 2#define _ASM_POWERPC_PGTABLE_PPC64_4K_H
3/* 3/*
4 * Entries per page directory level. The PTE level must use a 64b record 4 * Entries per page directory level. The PTE level must use a 64b record
5 * for each page table entry. The PMD and PGD level use a 32b record for 5 * for each page table entry. The PMD and PGD level use a 32b record for
@@ -40,28 +40,6 @@
40#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 40#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
41#define PGDIR_MASK (~(PGDIR_SIZE-1)) 41#define PGDIR_MASK (~(PGDIR_SIZE-1))
42 42
43/* PTE bits */
44#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
45#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
46#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
47#define _PAGE_F_SECOND _PAGE_SECONDARY
48#define _PAGE_F_GIX _PAGE_GROUP_IX
49#define _PAGE_SPECIAL 0x10000 /* software: special page */
50#define __HAVE_ARCH_PTE_SPECIAL
51
52/* PTE flags to conserve for HPTE identification */
53#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
54 _PAGE_SECONDARY | _PAGE_GROUP_IX)
55
56/* There is no 4K PFN hack on 4K pages */
57#define _PAGE_4K_PFN 0
58
59/* PAGE_MASK gives the right answer below, but only by accident */
60/* It should be preserving the high 48 bits and then specifically */
61/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
62#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
63 _PAGE_HPTEFLAGS | _PAGE_SPECIAL)
64
65/* Bits to mask out from a PMD to get to the PTE page */ 43/* Bits to mask out from a PMD to get to the PTE page */
66#define PMD_MASKED_BITS 0 44#define PMD_MASKED_BITS 0
67/* Bits to mask out from a PUD to get to the PMD page */ 45/* Bits to mask out from a PUD to get to the PMD page */
@@ -69,30 +47,6 @@
69/* Bits to mask out from a PGD to get to the PUD page */ 47/* Bits to mask out from a PGD to get to the PUD page */
70#define PGD_MASKED_BITS 0 48#define PGD_MASKED_BITS 0
71 49
72/* shift to put page number into pte */
73#define PTE_RPN_SHIFT (17)
74
75#ifdef STRICT_MM_TYPECHECKS
76#define __real_pte(e,p) ((real_pte_t){(e)})
77#define __rpte_to_pte(r) ((r).pte)
78#else
79#define __real_pte(e,p) (e)
80#define __rpte_to_pte(r) (__pte(r))
81#endif
82#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
83
84#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
85 do { \
86 index = 0; \
87 shift = mmu_psize_defs[psize].shift; \
88
89#define pte_iterate_hashed_end() } while(0)
90
91#ifdef CONFIG_PPC_HAS_HASH_64K
92#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
93#else
94#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
95#endif
96 50
97/* 51/*
98 * 4-level page tables related bits 52 * 4-level page tables related bits
@@ -112,6 +66,9 @@
112#define pud_ERROR(e) \ 66#define pud_ERROR(e) \
113 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 67 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
114 68
69/*
70 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
115#define remap_4k_pfn(vma, addr, pfn, prot) \ 71#define remap_4k_pfn(vma, addr, pfn, prot) \
116 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) 72 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
117#endif /* _ASM_POWERPC_PGTABLE_4K_H */ 73
74#endif /* _ASM_POWERPC_PGTABLE_PPC64_4K_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
new file mode 100644
index 00000000000..6cc085b945a
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
2#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6
7#define PTE_INDEX_SIZE 12
8#define PMD_INDEX_SIZE 12
9#define PUD_INDEX_SIZE 0
10#define PGD_INDEX_SIZE 4
11
12#ifndef __ASSEMBLY__
13
14#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
15#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
16#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
17
18#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
19#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
20#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
21
22/* With 4k base page size, hugepage PTEs go at the PMD level */
23#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
24
25/* PMD_SHIFT determines what a second-level page table entry can map */
26#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
27#define PMD_SIZE (1UL << PMD_SHIFT)
28#define PMD_MASK (~(PMD_SIZE-1))
29
30/* PGDIR_SHIFT determines what a third-level page table entry can map */
31#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
32#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
33#define PGDIR_MASK (~(PGDIR_SIZE-1))
34
35#endif /* __ASSEMBLY__ */
36
37/* Bits to mask out from a PMD to get to the PTE page */
38#define PMD_MASKED_BITS 0x1ff
39/* Bits to mask out from a PGD/PUD to get to the PMD page */
40#define PUD_MASKED_BITS 0x1ff
41
42#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index c627877fcf1..542073836b2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -11,9 +11,9 @@
11#endif /* __ASSEMBLY__ */ 11#endif /* __ASSEMBLY__ */
12 12
13#ifdef CONFIG_PPC_64K_PAGES 13#ifdef CONFIG_PPC_64K_PAGES
14#include <asm/pgtable-64k.h> 14#include <asm/pgtable-ppc64-64k.h>
15#else 15#else
16#include <asm/pgtable-4k.h> 16#include <asm/pgtable-ppc64-4k.h>
17#endif 17#endif
18 18
19#define FIRST_USER_ADDRESS 0 19#define FIRST_USER_ADDRESS 0
@@ -25,6 +25,8 @@
25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) 25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE) 26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
27 27
28
29/* Some sanity checking */
28#if TASK_SIZE_USER64 > PGTABLE_RANGE 30#if TASK_SIZE_USER64 > PGTABLE_RANGE
29#error TASK_SIZE_USER64 exceeds pagetable range 31#error TASK_SIZE_USER64 exceeds pagetable range
30#endif 32#endif
@@ -33,7 +35,6 @@
33#error TASK_SIZE_USER64 exceeds user VSID range 35#error TASK_SIZE_USER64 exceeds user VSID range
34#endif 36#endif
35 37
36
37/* 38/*
38 * Define the address range of the vmalloc VM area. 39 * Define the address range of the vmalloc VM area.
39 */ 40 */
@@ -76,29 +77,26 @@
76 77
77 78
78/* 79/*
79 * Common bits in a linux-style PTE. These match the bits in the 80 * Include the PTE bits definitions
80 * (hardware-defined) PowerPC PTE as closely as possible. Additional
81 * bits may be defined in pgtable-*.h
82 */ 81 */
83#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */ 82#include <asm/pte-hash64.h>
84#define _PAGE_USER 0x0002 /* matches one of the PP bits */ 83
85#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */ 84/* To make some generic powerpc code happy */
86#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */ 85#ifndef _PAGE_HWEXEC
87#define _PAGE_GUARDED 0x0008 86#define _PAGE_HWEXEC 0
88#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */ 87#endif
89#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */ 88
90#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */ 89/* Some other useful definitions */
91#define _PAGE_DIRTY 0x0080 /* C: page changed */ 90#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
92#define _PAGE_ACCESSED 0x0100 /* R: page referenced */ 91#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
93#define _PAGE_RW 0x0200 /* software: user write access allowed */ 92
94#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ 93/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
95 94 * pgprot changes
96/* Strong Access Ordering */ 95 */
97#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT) 96#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
98 97 _PAGE_ACCESSED | _PAGE_SPECIAL)
99#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT) 98
100 99
101#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
102 100
103/* __pgprot defined in arch/powerpc/include/asm/page.h */ 101/* __pgprot defined in arch/powerpc/include/asm/page.h */
104#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) 102#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
@@ -117,16 +115,9 @@
117#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE) 115#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
118#define HAVE_PAGE_AGP 116#define HAVE_PAGE_AGP
119 117
120#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \ 118/* We always have _PAGE_SPECIAL on 64 bit */
121 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \ 119#define __HAVE_ARCH_PTE_SPECIAL
122 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
123 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
124/* PTEIDX nibble */
125#define _PTEIDX_SECONDARY 0x8
126#define _PTEIDX_GROUP_IX 0x7
127 120
128/* To make some generic powerpc code happy */
129#define _PAGE_HWEXEC 0
130 121
131/* 122/*
132 * POWER4 and newer have per page execute protection, older chips can only 123 * POWER4 and newer have per page execute protection, older chips can only
@@ -163,6 +154,38 @@
163#ifndef __ASSEMBLY__ 154#ifndef __ASSEMBLY__
164 155
165/* 156/*
157 * This is the default implementation of various PTE accessors, it's
158 * used in all cases except Book3S with 64K pages where we have a
159 * concept of sub-pages
160 */
161#ifndef __real_pte
162
163#ifdef STRICT_MM_TYPECHECKS
164#define __real_pte(e,p) ((real_pte_t){(e)})
165#define __rpte_to_pte(r) ((r).pte)
166#else
167#define __real_pte(e,p) (e)
168#define __rpte_to_pte(r) (__pte(r))
169#endif
170#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
171
172#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
173 do { \
174 index = 0; \
175 shift = mmu_psize_defs[psize].shift; \
176
177#define pte_iterate_hashed_end() } while(0)
178
179#ifdef CONFIG_PPC_HAS_HASH_64K
180#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
181#else
182#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
183#endif
184
185#endif /* __real_pte */
186
187
188/*
166 * Conversion functions: convert a page and protection to a page entry, 189 * Conversion functions: convert a page and protection to a page entry,
167 * and a page entry and page directory to the page they refer to. 190 * and a page entry and page directory to the page they refer to.
168 * 191 *
diff --git a/arch/powerpc/include/asm/pte-40x.h b/arch/powerpc/include/asm/pte-40x.h
new file mode 100644
index 00000000000..07630faae02
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-40x.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_POWERPC_PTE_40x_H
2#define _ASM_POWERPC_PTE_40x_H
3#ifdef __KERNEL__
4
5/*
6 * At present, all PowerPC 400-class processors share a similar TLB
7 * architecture. The instruction and data sides share a unified,
8 * 64-entry, fully-associative TLB which is maintained totally under
9 * software control. In addition, the instruction side has a
10 * hardware-managed, 4-entry, fully-associative TLB which serves as a
11 * first level to the shared TLB. These two TLBs are known as the UTLB
12 * and ITLB, respectively (see "mmu.h" for definitions).
13 *
14 * There are several potential gotchas here. The 40x hardware TLBLO
15 * field looks like this:
16 *
17 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
18 * RPN..................... 0 0 EX WR ZSEL....... W I M G
19 *
20 * Where possible we make the Linux PTE bits match up with this
21 *
22 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
23 * support down to 1k pages), this is done in the TLBMiss exception
24 * handler.
25 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
26 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
27 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
28 * zone.
29 * - PRESENT *must* be in the bottom two bits because swap cache
30 * entries use the top 30 bits. Because 40x doesn't support SMP
31 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
32 * is cleared in the TLB miss handler before the TLB entry is loaded.
33 * - All other bits of the PTE are loaded into TLBLO without
34 * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
35 * software PTE bits. We actually use use bits 21, 24, 25, and
36 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
37 * PRESENT.
38 */
39
40#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
41#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
42#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
43#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
44#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
45#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
46#define _PAGE_RW 0x040 /* software: Writes permitted */
47#define _PAGE_DIRTY 0x080 /* software: dirty page */
48#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
49#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
50#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
51
52#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
53#define _PMD_BAD 0x802
54#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
55#define _PMD_SIZE_4M 0x0c0
56#define _PMD_SIZE_16M 0x0e0
57
58#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
59
60/* Until my rework is finished, 40x still needs atomic PTE updates */
61#define PTE_ATOMIC_UPDATES 1
62
63#endif /* __KERNEL__ */
64#endif /* _ASM_POWERPC_PTE_40x_H */
diff --git a/arch/powerpc/include/asm/pte-44x.h b/arch/powerpc/include/asm/pte-44x.h
new file mode 100644
index 00000000000..37e98bcf83e
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-44x.h
@@ -0,0 +1,102 @@
1#ifndef _ASM_POWERPC_PTE_44x_H
2#define _ASM_POWERPC_PTE_44x_H
3#ifdef __KERNEL__
4
5/*
6 * Definitions for PPC440
7 *
8 * Because of the 3 word TLB entries to support 36-bit addressing,
9 * the attribute are difficult to map in such a fashion that they
10 * are easily loaded during exception processing. I decided to
11 * organize the entry so the ERPN is the only portion in the
12 * upper word of the PTE and the attribute bits below are packed
13 * in as sensibly as they can be in the area below a 4KB page size
14 * oriented RPN. This at least makes it easy to load the RPN and
15 * ERPN fields in the TLB. -Matt
16 *
17 * This isn't entirely true anymore, at least some bits are now
18 * easier to move into the TLB from the PTE. -BenH.
19 *
20 * Note that these bits preclude future use of a page size
21 * less than 4KB.
22 *
23 *
24 * PPC 440 core has following TLB attribute fields;
25 *
26 * TLB1:
27 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
28 * RPN................................. - - - - - - ERPN.......
29 *
30 * TLB2:
31 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
33 *
34 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
35 * TLB2 storage attibute fields. Those are:
36 *
37 * TLB2:
38 * 0...10 11 12 13 14 15 16...31
39 * no change WL1 IL1I IL1D IL2I IL2D no change
40 *
41 * There are some constrains and options, to decide mapping software bits
42 * into TLB entry.
43 *
44 * - PRESENT *must* be in the bottom three bits because swap cache
45 * entries use the top 29 bits for TLB2.
46 *
47 * - FILE *must* be in the bottom three bits because swap cache
48 * entries use the top 29 bits for TLB2.
49 *
50 * - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
51 * because it doesn't support SMP. However, some later 460 variants
52 * have -some- form of SMP support and so I keep the bit there for
53 * future use
54 *
55 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
56 * for memory protection related functions (see PTE structure in
57 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
58 * above bits. Note that the bit values are CPU specific, not architecture
59 * specific.
60 *
61 * The kernel PTE entry holds an arch-dependent swp_entry structure under
62 * certain situations. In other words, in such situations some portion of
63 * the PTE bits are used as a swp_entry. In the PPC implementation, the
64 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
65 * hold protection values. That means the three protection bits are
66 * reserved for both PTE and SWAP entry at the most significant three
67 * LSBs.
68 *
69 * There are three protection bits available for SWAP entry:
70 * _PAGE_PRESENT
71 * _PAGE_FILE
72 * _PAGE_HASHPTE (if HW has)
73 *
74 * So those three bits have to be inside of 0-2nd LSB of PTE.
75 *
76 */
77
78#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
79#define _PAGE_RW 0x00000002 /* S: Write permission */
80#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
81#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
82#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
83#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
84#define _PAGE_SPECIAL 0x00000020 /* S: Special page */
85#define _PAGE_USER 0x00000040 /* S: User page */
86#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
87#define _PAGE_GUARDED 0x00000100 /* H: G bit */
88#define _PAGE_COHERENT 0x00000200 /* H: M bit */
89#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
90#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
91
92/* TODO: Add large page lowmem mapping support */
93#define _PMD_PRESENT 0
94#define _PMD_PRESENT_MASK (PAGE_MASK)
95#define _PMD_BAD (~PAGE_MASK)
96
97/* ERPN in a PTE never gets cleared, ignore it */
98#define _PTE_NONE_MASK 0xffffffff00000000ULL
99
100
101#endif /* __KERNEL__ */
102#endif /* _ASM_POWERPC_PTE_44x_H */
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
new file mode 100644
index 00000000000..b07acfd330b
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_POWERPC_PTE_8xx_H
2#define _ASM_POWERPC_PTE_8xx_H
3#ifdef __KERNEL__
4
5/*
6 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
7 * We also use the two level tables, but we can put the real bits in them
8 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
9 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
10 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
11 * based upon user/super access. The TLB does not have accessed nor write
12 * protect. We assume that if the TLB get loaded with an entry it is
13 * accessed, and overload the changed bit for write protect. We use
14 * two bits in the software pte that are supposed to be set to zero in
15 * the TLB entry (24 and 25) for these indicators. Although the level 1
16 * descriptor contains the guarded and writethrough/copyback bits, we can
17 * set these at the page level since they get copied from the Mx_TWC
18 * register when the TLB entry is loaded. We will use bit 27 for guard, since
19 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
20 * These will get masked from the level 2 descriptor at TLB load time, and
21 * copied to the MD_TWC before it gets loaded.
22 * Large page sizes added. We currently support two sizes, 4K and 8M.
23 * This also allows a TLB hander optimization because we can directly
24 * load the PMD into MD_TWC. The 8M pages are only used for kernel
25 * mapping of well known areas. The PMD (PGD) entries contain control
26 * flags in addition to the address, so care must be taken that the
27 * software no longer assumes these are only pointers.
28 */
29
30/* Definitions for 8xx embedded chips. */
31#define _PAGE_PRESENT 0x0001 /* Page is valid */
32#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
33#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
34#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
35
36/* These five software bits must be masked out when the entry is loaded
37 * into the TLB.
38 */
39#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
40#define _PAGE_GUARDED 0x0010 /* software: guarded access */
41#define _PAGE_DIRTY 0x0020 /* software: page changed */
42#define _PAGE_RW 0x0040 /* software: user write access allowed */
43#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
44
45/* Setting any bits in the nibble with the follow two controls will
46 * require a TLB exception handler change. It is assumed unused bits
47 * are always zero.
48 */
49#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
50#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
51
52#define _PMD_PRESENT 0x0001
53#define _PMD_BAD 0x0ff0
54#define _PMD_PAGE_MASK 0x000c
55#define _PMD_PAGE_8M 0x000c
56
57#define _PTE_NONE_MASK _PAGE_ACCESSED
58
59/* Until my rework is finished, 8xx still needs atomic PTE updates */
60#define PTE_ATOMIC_UPDATES 1
61
62
63#endif /* __KERNEL__ */
64#endif /* _ASM_POWERPC_PTE_8xx_H */
diff --git a/arch/powerpc/include/asm/pte-fsl-booke.h b/arch/powerpc/include/asm/pte-fsl-booke.h
new file mode 100644
index 00000000000..0fe5de7bea3
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-fsl-booke.h
@@ -0,0 +1,46 @@
1#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
2#define _ASM_POWERPC_PTE_FSL_BOOKE_H
3#ifdef __KERNEL__
4
5/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
6 * processors
7 *
8 MMU Assist Register 3:
9
10 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
11 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
12
13 - PRESENT *must* be in the bottom three bits because swap cache
14 entries use the top 29 bits.
15
16 - FILE *must* be in the bottom three bits because swap cache
17 entries use the top 29 bits.
18*/
19
20/* Definitions for FSL Book-E Cores */
21#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
22#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
23#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
24#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
25#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
26#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
27#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
28
29#define _PAGE_ENDIAN 0x00040 /* H: E bit */
30#define _PAGE_GUARDED 0x00080 /* H: G bit */
31#define _PAGE_COHERENT 0x00100 /* H: M bit */
32#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
33#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
34#define _PAGE_SPECIAL 0x00800 /* S: Special page */
35
36#ifdef CONFIG_PTE_64BIT
37/* ERPN in a PTE never gets cleared, ignore it */
38#define _PTE_NONE_MASK 0xffffffffffff0000ULL
39#endif
40
41#define _PMD_PRESENT 0
42#define _PMD_PRESENT_MASK (PAGE_MASK)
43#define _PMD_BAD (~PAGE_MASK)
44
45#endif /* __KERNEL__ */
46#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/arch/powerpc/include/asm/pte-hash32.h b/arch/powerpc/include/asm/pte-hash32.h
new file mode 100644
index 00000000000..6afe22b02f2
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-hash32.h
@@ -0,0 +1,49 @@
1#ifndef _ASM_POWERPC_PTE_HASH32_H
2#define _ASM_POWERPC_PTE_HASH32_H
3#ifdef __KERNEL__
4
5/*
6 * The "classic" 32-bit implementation of the PowerPC MMU uses a hash
7 * table containing PTEs, together with a set of 16 segment registers,
8 * to define the virtual to physical address mapping.
9 *
10 * We use the hash table as an extended TLB, i.e. a cache of currently
11 * active mappings. We maintain a two-level page table tree, much
12 * like that used by the i386, for the sake of the Linux memory
13 * management code. Low-level assembler code in hash_low_32.S
14 * (procedure hash_page) is responsible for extracting ptes from the
15 * tree and putting them into the hash table when necessary, and
16 * updating the accessed and modified bits in the page table tree.
17 */
18
19#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
20#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
21#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
22#define _PAGE_USER 0x004 /* usermode access allowed */
23#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
24#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
25#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
26#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
27#define _PAGE_DIRTY 0x080 /* C: page changed */
28#define _PAGE_ACCESSED 0x100 /* R: page referenced */
29#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
30#define _PAGE_RW 0x400 /* software: user write access allowed */
31#define _PAGE_SPECIAL 0x800 /* software: Special page */
32
33#ifdef CONFIG_PTE_64BIT
34/* We never clear the high word of the pte */
35#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
36#else
37#define _PTE_NONE_MASK _PAGE_HASHPTE
38#endif
39
40#define _PMD_PRESENT 0
41#define _PMD_PRESENT_MASK (PAGE_MASK)
42#define _PMD_BAD (~PAGE_MASK)
43
44/* Hash table based platforms need atomic updates of the linux PTE */
45#define PTE_ATOMIC_UPDATES 1
46
47
48#endif /* __KERNEL__ */
49#endif /* _ASM_POWERPC_PTE_HASH32_H */
diff --git a/arch/powerpc/include/asm/pte-hash64-4k.h b/arch/powerpc/include/asm/pte-hash64-4k.h
new file mode 100644
index 00000000000..29fdc158fe3
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-hash64-4k.h
@@ -0,0 +1,20 @@
1/* To be include by pgtable-hash64.h only */
2
3/* PTE bits */
4#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
5#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
6#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
7#define _PAGE_F_SECOND _PAGE_SECONDARY
8#define _PAGE_F_GIX _PAGE_GROUP_IX
9#define _PAGE_SPECIAL 0x10000 /* software: special page */
10
11/* There is no 4K PFN hack on 4K pages */
12#define _PAGE_4K_PFN 0
13
14/* PTE flags to conserve for HPTE identification */
15#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
16 _PAGE_SECONDARY | _PAGE_GROUP_IX)
17
18/* shift to put page number into pte */
19#define PTE_RPN_SHIFT (17)
20
diff --git a/arch/powerpc/include/asm/pgtable-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index 7389003349a..e05d26fa372 100644
--- a/arch/powerpc/include/asm/pgtable-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -1,76 +1,6 @@
1#ifndef _ASM_POWERPC_PGTABLE_64K_H 1/* To be include by pgtable-hash64.h only */
2#define _ASM_POWERPC_PGTABLE_64K_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6
7#define PTE_INDEX_SIZE 12
8#define PMD_INDEX_SIZE 12
9#define PUD_INDEX_SIZE 0
10#define PGD_INDEX_SIZE 4
11
12#ifndef __ASSEMBLY__
13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16
17#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
18#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
19#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
20
21#ifdef CONFIG_PPC_SUBPAGE_PROT
22/*
23 * For the sub-page protection option, we extend the PGD with one of
24 * these. Basically we have a 3-level tree, with the top level being
25 * the protptrs array. To optimize speed and memory consumption when
26 * only addresses < 4GB are being protected, pointers to the first
27 * four pages of sub-page protection words are stored in the low_prot
28 * array.
29 * Each page of sub-page protection words protects 1GB (4 bytes
30 * protects 64k). For the 3-level tree, each page of pointers then
31 * protects 8TB.
32 */
33struct subpage_prot_table {
34 unsigned long maxaddr; /* only addresses < this are protected */
35 unsigned int **protptrs[2];
36 unsigned int *low_prot[4];
37};
38
39#undef PGD_TABLE_SIZE
40#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
41 sizeof(struct subpage_prot_table))
42
43#define SBP_L1_BITS (PAGE_SHIFT - 2)
44#define SBP_L2_BITS (PAGE_SHIFT - 3)
45#define SBP_L1_COUNT (1 << SBP_L1_BITS)
46#define SBP_L2_COUNT (1 << SBP_L2_BITS)
47#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
48#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
49
50extern void subpage_prot_free(pgd_t *pgd);
51
52static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
53{
54 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
55}
56#endif /* CONFIG_PPC_SUBPAGE_PROT */
57#endif /* __ASSEMBLY__ */
58
59/* With 4k base page size, hugepage PTEs go at the PMD level */
60#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
61
62/* PMD_SHIFT determines what a second-level page table entry can map */
63#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
64#define PMD_SIZE (1UL << PMD_SHIFT)
65#define PMD_MASK (~(PMD_SIZE-1))
66
67/* PGDIR_SHIFT determines what a third-level page table entry can map */
68#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
69#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
70#define PGDIR_MASK (~(PGDIR_SIZE-1))
71 2
72/* Additional PTE bits (don't change without checking asm in hash_low.S) */ 3/* Additional PTE bits (don't change without checking asm in hash_low.S) */
73#define __HAVE_ARCH_PTE_SPECIAL
74#define _PAGE_SPECIAL 0x00000400 /* software: special page */ 4#define _PAGE_SPECIAL 0x00000400 /* software: special page */
75#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */ 5#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
76#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */ 6#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
@@ -107,21 +37,15 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
107 * of addressable physical space, or 46 bits for the special 4k PFNs. 37 * of addressable physical space, or 46 bits for the special 4k PFNs.
108 */ 38 */
109#define PTE_RPN_SHIFT (30) 39#define PTE_RPN_SHIFT (30)
110#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
111#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
112
113/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
114 * pgprot changes
115 */
116#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
117 _PAGE_ACCESSED | _PAGE_SPECIAL)
118 40
119/* Bits to mask out from a PMD to get to the PTE page */ 41#ifndef __ASSEMBLY__
120#define PMD_MASKED_BITS 0x1ff
121/* Bits to mask out from a PGD/PUD to get to the PMD page */
122#define PUD_MASKED_BITS 0x1ff
123 42
124/* Manipulate "rpte" values */ 43/*
44 * With 64K pages on hash table, we have a special PTE format that
45 * uses a second "half" of the page table to encode sub-page information
46 * in order to deal with 64K made of 4K HW pages. Thus we override the
47 * generic accessors and iterators here
48 */
125#define __real_pte(e,p) ((real_pte_t) { \ 49#define __real_pte(e,p) ((real_pte_t) { \
126 (e), pte_val(*((p) + PTRS_PER_PTE)) }) 50 (e), pte_val(*((p) + PTRS_PER_PTE)) })
127#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ 51#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
@@ -130,7 +54,6 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
130#define __rpte_sub_valid(rpte, index) \ 54#define __rpte_sub_valid(rpte, index) \
131 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index))) 55 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
132 56
133
134/* Trick: we set __end to va + 64k, which happens works for 57/* Trick: we set __end to va + 64k, which happens works for
135 * a 16M page as well as we want only one iteration 58 * a 16M page as well as we want only one iteration
136 */ 59 */
@@ -152,4 +75,41 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
152 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \ 75 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
153 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)) 76 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
154 77
155#endif /* _ASM_POWERPC_PGTABLE_64K_H */ 78
79#ifdef CONFIG_PPC_SUBPAGE_PROT
80/*
81 * For the sub-page protection option, we extend the PGD with one of
82 * these. Basically we have a 3-level tree, with the top level being
83 * the protptrs array. To optimize speed and memory consumption when
84 * only addresses < 4GB are being protected, pointers to the first
85 * four pages of sub-page protection words are stored in the low_prot
86 * array.
87 * Each page of sub-page protection words protects 1GB (4 bytes
88 * protects 64k). For the 3-level tree, each page of pointers then
89 * protects 8TB.
90 */
91struct subpage_prot_table {
92 unsigned long maxaddr; /* only addresses < this are protected */
93 unsigned int **protptrs[2];
94 unsigned int *low_prot[4];
95};
96
97#undef PGD_TABLE_SIZE
98#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
99 sizeof(struct subpage_prot_table))
100
101#define SBP_L1_BITS (PAGE_SHIFT - 2)
102#define SBP_L2_BITS (PAGE_SHIFT - 3)
103#define SBP_L1_COUNT (1 << SBP_L1_BITS)
104#define SBP_L2_COUNT (1 << SBP_L2_BITS)
105#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
106#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
107
108extern void subpage_prot_free(pgd_t *pgd);
109
110static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
111{
112 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
113}
114#endif /* CONFIG_PPC_SUBPAGE_PROT */
115#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/pte-hash64.h b/arch/powerpc/include/asm/pte-hash64.h
new file mode 100644
index 00000000000..62766636cc1
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-hash64.h
@@ -0,0 +1,47 @@
1#ifndef _ASM_POWERPC_PTE_HASH64_H
2#define _ASM_POWERPC_PTE_HASH64_H
3#ifdef __KERNEL__
4
5/*
6 * Common bits between 4K and 64K pages in a linux-style PTE.
7 * These match the bits in the (hardware-defined) PowerPC PTE as closely
8 * as possible. Additional bits may be defined in pgtable-hash64-*.h
9 */
10#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
11#define _PAGE_USER 0x0002 /* matches one of the PP bits */
12#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
13#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
14#define _PAGE_GUARDED 0x0008
15#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
16#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
17#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
18#define _PAGE_DIRTY 0x0080 /* C: page changed */
19#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
20#define _PAGE_RW 0x0200 /* software: user write access allowed */
21#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
22
23/* Strong Access Ordering */
24#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
25
26#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
27
28#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
29
30/* PTEIDX nibble */
31#define _PTEIDX_SECONDARY 0x8
32#define _PTEIDX_GROUP_IX 0x7
33
34#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \
35 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \
36 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
37 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
38
39
40#ifdef CONFIG_PPC_64K_PAGES
41#include <asm/pte-hash64-64k.h>
42#else
43#include <asm/pte-hash64-4k.h>
44#endif
45
46#endif /* __KERNEL__ */
47#endif /* _ASM_POWERPC_PTE_HASH64_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 17:59:20 -0500