diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-08-25 06:10:03 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-26 18:48:00 -0400 |
commit | 7f97a4bd47291e4ec9b9eaf63d7275ddfb498cb3 (patch) | |
tree | af60b056cbb1c87b042e4db2931bd391dc8d94cd /drivers/net/tg3.c | |
parent | 535ef6e1124d445efbcc13b7126561dc544b0b64 (diff) |
tg3: Convert code to use PHY_IS_FET
This patch converts the code to use the PHY_IS_FET flag rather than the
ASIC revision to decide whether or not to use FET paths.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 73 |
1 files changed, 46 insertions, 27 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 800f98069c1..2808152e869 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -784,7 +784,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |||
784 | unsigned int loops; | 784 | unsigned int loops; |
785 | int ret; | 785 | int ret; |
786 | 786 | ||
787 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && | 787 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
788 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) | 788 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
789 | return 0; | 789 | return 0; |
790 | 790 | ||
@@ -1069,6 +1069,7 @@ static int tg3_mdio_init(struct tg3 *tp) | |||
1069 | case TG3_PHY_ID_RTL8201E: | 1069 | case TG3_PHY_ID_RTL8201E: |
1070 | case TG3_PHY_ID_BCMAC131: | 1070 | case TG3_PHY_ID_BCMAC131: |
1071 | phydev->interface = PHY_INTERFACE_MODE_MII; | 1071 | phydev->interface = PHY_INTERFACE_MODE_MII; |
1072 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | ||
1072 | break; | 1073 | break; |
1073 | } | 1074 | } |
1074 | 1075 | ||
@@ -1474,13 +1475,37 @@ static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |||
1474 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | 1475 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); |
1475 | } | 1476 | } |
1476 | 1477 | ||
1478 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) | ||
1479 | { | ||
1480 | u32 phytest; | ||
1481 | |||
1482 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | ||
1483 | u32 phy; | ||
1484 | |||
1485 | tg3_writephy(tp, MII_TG3_FET_TEST, | ||
1486 | phytest | MII_TG3_FET_SHADOW_EN); | ||
1487 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | ||
1488 | if (enable) | ||
1489 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | ||
1490 | else | ||
1491 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | ||
1492 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | ||
1493 | } | ||
1494 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | ||
1495 | } | ||
1496 | } | ||
1497 | |||
1477 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | 1498 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1478 | { | 1499 | { |
1479 | u32 reg; | 1500 | u32 reg; |
1480 | 1501 | ||
1481 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | 1502 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
1482 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 1503 | return; |
1504 | |||
1505 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | ||
1506 | tg3_phy_fet_toggle_apd(tp, enable); | ||
1483 | return; | 1507 | return; |
1508 | } | ||
1484 | 1509 | ||
1485 | reg = MII_TG3_MISC_SHDW_WREN | | 1510 | reg = MII_TG3_MISC_SHDW_WREN | |
1486 | MII_TG3_MISC_SHDW_SCR5_SEL | | 1511 | MII_TG3_MISC_SHDW_SCR5_SEL | |
@@ -1511,7 +1536,7 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) | |||
1511 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | 1536 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) |
1512 | return; | 1537 | return; |
1513 | 1538 | ||
1514 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 1539 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
1515 | u32 ephy; | 1540 | u32 ephy; |
1516 | 1541 | ||
1517 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { | 1542 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
@@ -2662,7 +2687,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 | |||
2662 | break; | 2687 | break; |
2663 | 2688 | ||
2664 | default: | 2689 | default: |
2665 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 2690 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
2666 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : | 2691 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2667 | SPEED_10; | 2692 | SPEED_10; |
2668 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | 2693 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : |
@@ -2997,7 +3022,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
2997 | 3022 | ||
2998 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) | 3023 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) |
2999 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | 3024 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
3000 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) | 3025 | else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
3001 | tg3_writephy(tp, MII_TG3_IMASK, ~0); | 3026 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3002 | 3027 | ||
3003 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 3028 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
@@ -3107,7 +3132,9 @@ relink: | |||
3107 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | 3132 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3108 | else | 3133 | else |
3109 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 3134 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3110 | } else | 3135 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) |
3136 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | ||
3137 | else | ||
3111 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 3138 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3112 | 3139 | ||
3113 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | 3140 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
@@ -7349,7 +7376,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7349 | return err; | 7376 | return err; |
7350 | 7377 | ||
7351 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | 7378 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
7352 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { | 7379 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) { |
7353 | u32 tmp; | 7380 | u32 tmp; |
7354 | 7381 | ||
7355 | /* Clear CRC stats. */ | 7382 | /* Clear CRC stats. */ |
@@ -9746,20 +9773,8 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
9746 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | 9773 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { |
9747 | u32 val; | 9774 | u32 val; |
9748 | 9775 | ||
9749 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 9776 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9750 | u32 phytest; | 9777 | tg3_phy_fet_toggle_apd(tp, false); |
9751 | |||
9752 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | ||
9753 | u32 phy, reg = MII_TG3_FET_SHDW_AUXSTAT2; | ||
9754 | |||
9755 | tg3_writephy(tp, MII_TG3_FET_TEST, | ||
9756 | phytest | MII_TG3_FET_SHADOW_EN); | ||
9757 | if (!tg3_readphy(tp, reg, &phy)) { | ||
9758 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | ||
9759 | tg3_writephy(tp, reg, phy); | ||
9760 | } | ||
9761 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | ||
9762 | } | ||
9763 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; | 9778 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
9764 | } else | 9779 | } else |
9765 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | 9780 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; |
@@ -9770,8 +9785,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
9770 | udelay(40); | 9785 | udelay(40); |
9771 | 9786 | ||
9772 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | 9787 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; |
9773 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 9788 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9774 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800); | 9789 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
9790 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800); | ||
9775 | mac_mode |= MAC_MODE_PORT_MODE_MII; | 9791 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
9776 | } else | 9792 | } else |
9777 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | 9793 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
@@ -12268,12 +12284,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12268 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | 12284 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; |
12269 | } | 12285 | } |
12270 | 12286 | ||
12287 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | ||
12288 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | ||
12289 | |||
12271 | /* A few boards don't want Ethernet@WireSpeed phy feature */ | 12290 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
12272 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | 12291 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || |
12273 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | 12292 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && |
12274 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | 12293 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
12275 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || | 12294 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
12276 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) || | 12295 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) || |
12277 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | 12296 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) |
12278 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; | 12297 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; |
12279 | 12298 | ||
@@ -12284,7 +12303,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12284 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; | 12303 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; |
12285 | 12304 | ||
12286 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | 12305 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
12287 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 && | 12306 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
12288 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 12307 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
12289 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) { | 12308 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) { |
12290 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 12309 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
@@ -12409,7 +12428,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12409 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || | 12428 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
12410 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | 12429 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || |
12411 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || | 12430 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
12412 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 12431 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
12413 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; | 12432 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; |
12414 | 12433 | ||
12415 | err = tg3_phy_probe(tp); | 12434 | err = tg3_phy_probe(tp); |