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authorMatt Carlson <mcarlson@broadcom.com>2009-08-25 06:09:36 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-26 18:47:58 -0400
commit535ef6e1124d445efbcc13b7126561dc544b0b64 (patch)
treea961c86394eca3c40f660743ac79585dc2c0613c /drivers/net/tg3.c
parentbb85fbb6a98d8edab81599913559c7ff0a963984 (diff)
tg3: Create MII_TG3_FET namespace
Broadcom's phys come in two distinctly different register layouts. For the lack of an official term to distinguish between the two formats, we can loosely categorize them by their fast ethernet or gigabit ethernet transceiver description. This patch creates the (driver-internal) Fast Ethernet Transceiver (FET) namespace and converts the 5906 EPHY definitions over. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c38
1 files changed, 21 insertions, 17 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 41e0d40259e..800f98069c1 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1514,17 +1514,19 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 1514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1515 u32 ephy; 1515 u32 ephy;
1516 1516
1517 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) { 1517 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1518 tg3_writephy(tp, MII_TG3_EPHY_TEST, 1518 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1519 ephy | MII_TG3_EPHY_SHADOW_EN); 1519
1520 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) { 1520 tg3_writephy(tp, MII_TG3_FET_TEST,
1521 ephy | MII_TG3_FET_SHADOW_EN);
1522 if (!tg3_readphy(tp, reg, &phy)) {
1521 if (enable) 1523 if (enable)
1522 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX; 1524 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1523 else 1525 else
1524 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX; 1526 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1525 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy); 1527 tg3_writephy(tp, reg, phy);
1526 } 1528 }
1527 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy); 1529 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1528 } 1530 }
1529 } else { 1531 } else {
1530 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | 1532 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
@@ -1915,7 +1917,7 @@ out:
1915 1917
1916 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 1918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1917 /* adjust output voltage */ 1919 /* adjust output voltage */
1918 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12); 1920 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1919 } 1921 }
1920 1922
1921 tg3_phy_toggle_automdix(tp, 1); 1923 tg3_phy_toggle_automdix(tp, 1);
@@ -9747,14 +9749,16 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 9749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9748 u32 phytest; 9750 u32 phytest;
9749 9751
9750 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) { 9752 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
9751 u32 phy; 9753 u32 phy, reg = MII_TG3_FET_SHDW_AUXSTAT2;
9752 9754
9753 tg3_writephy(tp, MII_TG3_EPHY_TEST, 9755 tg3_writephy(tp, MII_TG3_FET_TEST,
9754 phytest | MII_TG3_EPHY_SHADOW_EN); 9756 phytest | MII_TG3_FET_SHADOW_EN);
9755 if (!tg3_readphy(tp, 0x1b, &phy)) 9757 if (!tg3_readphy(tp, reg, &phy)) {
9756 tg3_writephy(tp, 0x1b, phy & ~0x20); 9758 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
9757 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest); 9759 tg3_writephy(tp, reg, phy);
9760 }
9761 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
9758 } 9762 }
9759 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; 9763 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9760 } else 9764 } else
@@ -9767,7 +9771,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9767 9771
9768 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; 9772 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 9773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9770 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800); 9774 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9771 mac_mode |= MAC_MODE_PORT_MODE_MII; 9775 mac_mode |= MAC_MODE_PORT_MODE_MII;
9772 } else 9776 } else
9773 mac_mode |= MAC_MODE_PORT_MODE_GMII; 9777 mac_mode |= MAC_MODE_PORT_MODE_GMII;