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authorFranck Bui-Huu <fbuihuu@gmail.com>2007-05-07 12:01:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-05-11 09:28:31 -0400
commit1e54f778af4467b816bf1289e7c4bf7e50067b7b (patch)
treec6b6daff71c7e26d59dc84a61fb05ff1fe3dac02 /arch/mips/pci
parent0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0 (diff)
[MIPS] Remove Momenco Ocelot G support
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-ocelot-g.c37
-rw-r--r--arch/mips/pci/pci-ocelot-g.c97
3 files changed, 0 insertions, 135 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index df487c063b1..30a1c79c6f5 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -34,7 +34,6 @@ obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
34obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o 34obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
35obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o 35obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
36obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o 36obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o
37obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o
38obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ 37obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
39 pci-yosemite.o 38 pci-yosemite.o
40obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o 39obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
diff --git a/arch/mips/pci/fixup-ocelot-g.c b/arch/mips/pci/fixup-ocelot-g.c
deleted file mode 100644
index d7a652e326c..00000000000
--- a/arch/mips/pci/fixup-ocelot-g.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
8 */
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
15{
16 int bus = dev->bus->number;
17
18 if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */
19 return 2; /* irq_nr is 2 for INT0 */
20
21 if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */
22 return 3; /* irq_nr is 3 for INT1 */
23
24 if (bus == 1 && slot == 3) /* Intel 21555 bridge */
25 return 5; /* irq_nr is 8 for INT6 */
26
27 if (bus == 1 && slot == 4) /* PMC Slot */
28 return 9; /* irq_nr is 9 for INT7 */
29
30 return -1;
31}
32
33/* Do platform specific device initialization at pci_enable_device() time */
34int pcibios_plat_dev_init(struct pci_dev *dev)
35{
36 return 0;
37}
diff --git a/arch/mips/pci/pci-ocelot-g.c b/arch/mips/pci/pci-ocelot-g.c
deleted file mode 100644
index 1e3430154fa..00000000000
--- a/arch/mips/pci/pci-ocelot-g.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * This doesn't really fly - but I don't have a GT64240 system for testing.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <asm/gt64240.h>
15
16/*
17 * We assume these address ranges have been programmed into the GT-64240 by
18 * the firmware. PMON in case of the Ocelot G does that. Note the size of
19 * the I/O range is completly stupid; I/O mappings are limited to at most
20 * 256 bytes by the PCI spec and deprecated; and just to make things worse
21 * apparently many devices don't decode more than 64k of I/O space.
22 */
23
24#define gt_io_size 0x20000000UL
25#define gt_io_base 0xe0000000UL
26
27static struct resource gt_pci_mem0_resource = {
28 .name = "MV64240 PCI0 MEM",
29 .start = 0xc0000000UL,
30 .end = 0xcfffffffUL,
31 .flags = IORESOURCE_MEM
32};
33
34static struct resource gt_pci_io_mem0_resource = {
35 .name = "MV64240 PCI0 IO MEM",
36 .start = 0xe0000000UL,
37 .end = 0xefffffffUL,
38 .flags = IORESOURCE_IO
39};
40
41static struct mv_pci_controller gt_bus0_controller = {
42 .pcic = {
43 .pci_ops = &mv_pci_ops,
44 .mem_resource = &gt_pci_mem0_resource,
45 .mem_offset = 0xc0000000UL,
46 .io_resource = &gt_pci_io_mem0_resource,
47 .io_offset = 0x00000000UL
48 },
49 .config_addr = PCI_0CONFIGURATION_ADDRESS,
50 .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
51};
52
53static struct resource gt_pci_mem1_resource = {
54 .name = "MV64240 PCI1 MEM",
55 .start = 0xd0000000UL,
56 .end = 0xdfffffffUL,
57 .flags = IORESOURCE_MEM
58};
59
60static struct resource gt_pci_io_mem1_resource = {
61 .name = "MV64240 PCI1 IO MEM",
62 .start = 0xf0000000UL,
63 .end = 0xffffffffUL,
64 .flags = IORESOURCE_IO
65};
66
67static struct mv_pci_controller gt_bus1_controller = {
68 .pcic = {
69 .pci_ops = &mv_pci_ops,
70 .mem_resource = &gt_pci_mem1_resource,
71 .mem_offset = 0xd0000000UL,
72 .io_resource = &gt_pci_io_mem1_resource,
73 .io_offset = 0x10000000UL
74 },
75 .config_addr = PCI_1CONFIGURATION_ADDRESS,
76 .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
77};
78
79static __init int __init ocelot_g_pci_init(void)
80{
81 unsigned long io_v_base;
82
83 if (gt_io_size) {
84 io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size);
85 if (!io_v_base)
86 panic("Could not ioremap I/O port range");
87
88 set_io_port_base(io_v_base);
89 }
90
91 register_pci_controller(&gt_bus0_controller.pcic);
92 register_pci_controller(&gt_bus1_controller.pcic);
93
94 return 0;
95}
96
97arch_initcall(ocelot_g_pci_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 03:47:52 -0500